ELF          >            @       x          @ 8  @ * )                                                                                                P&      P&      P&      r      r                  "     "     "          1                  @     @     @                                                $       $                    0     0     0                                  P     P     P                              "     "     "                           Std   0     0     0                            Ptd   h$     h$     h$     d      d             Qtd                                                  Rtd   "     "     "     X      X                      GNU #Op=Ym{	h/f#      y        `(Q !@  LD  "P@
&%@	@    $A@B   P! ( @``  Ѐ! # `P@@X@#!!i P  !HD CPR@ dHBB  A !, B   D"(P bB @Q@' "(@P )   @@      Q  J J @  ` 8   @$   @~  8,M,8 `   @       H  ` aC    @    ("CCD  P  " C H      4  (  X*   8'AD I"- \ !  
$ @D@ !  	  A!@6    "@     ^ BH      @  	   ¢<# - @!@ B @@d  0	 GBFDcH0E @U  D   !LE    )
  $ `      9 d$  	   D c(  (    !@
 B@    I @ : 
  "     XXh XPB       @ 	B  @@ H   
  MPA $B	h@  ". A    H @! $5H   0 x  0DfQ @@   䁀HA(ʖ   @ @    P     
  AB A   Zp     @     P F AP "@DRC
 # B  -  @"P@@ @ t Z G   B        PXI`E  (@0LH02C!     L  R B A      (`  d   @b  	 G$MA   ,B  B  c $` J 0     @   @ ! `    @Bd  $( (     HK  
  A"`$A(DB9      D  @	 2  ( HJAX !8  Q{d( @  @D @@J 3 H   (  @B P@   )C P  @     @ @ (0" ap 
D49    149 ,( H	$ @ B 00) B J@ @
@ E2i  " ,   P  $  !@ Q
 "  P
 ( @ R     @  BPҤ(  B * P @Aq j @( @	F0DB B (      0@ (QS !P ("      
       JH@	 0      H` B  D2"  y    EP! ,b    (B @0 D
  k f BD&B  )B         L B@@%b$ @   A(  *   @ p$  @ ` "@@@HJ   He "  D L   "@ $Mh   0 A        $P@  $      $ B          * )         @rX        D(8      A
 0 " H  FD   I@ D2r   @ dD 	KJ`r` $    @ 

#   Pp@X	 0@   2   @  @	@R  !(h P	,   @
6$  qCPNM J%  @"D         BDE2 H 
b  H @    D        Dn1HAcP"j@" @hB    Y   ]"   Ȃ (@  P
!0@ "H 	'AH  `@ 0.(@  @P4 ( A    @D  L  @ @ YI   8   H b%	! @D@@ @` HbaH 	  @n@ !$   ( @    d@ P   @`QI *  A     0B  L  D    @ V)BD4!!!~       PdF A B        # @ %     $      @  B           !@1  
  D!   
 
b 1S"AJ  E @    <$ i	  @! &    
@  &    @          @@d @`  H  A         BR T$Qp"   Hd  $      @     !       $     `D  # @     	    0@ 8	  b$H !8$            (  @     [Q  U 0 @    `B  BXHB4,    @   @Y  b @@ D 4DY `68 %  D  9  P  `fH.0 
  @ B  A`ޡ $   @R*h0 0    	  HA 0 E     D   "`($BH@@G C 0 @@    @   
 0 .V`  9   1a  J @ 0IA A
	@" D  	 $ @ *Z@ G *   @ @C   0" C
  ,A @! A @ B@%X`0 @ @#Ɇ $ a0 2                 H8D      
 ,J ` d  H
  p      (<	     @  B" H @ b(ȑ  H  
e`Ѝ!	 !DL E    1 A@@) 0@ D"@ A
  `Ĉ   &     (    (    A @ $ # @ P   @@   E       
@    "@ B @ 8@D@   "    
    !" T  @ h    D        (   	   @     H(@d  `:
@  J"  D(h    H R! "  ( 9&
 @0  4 
@0 "P   !  (P0         y  {                                                                                                                                                                                                                                         
                               $      (  *  -  1      5  7  8  ;  <      @  C  E  I  N  Q  T  U          X  Z  [  ^  `  a          b  d  e  f  h  j  m  o  p  s  v      y  z  {  }  ~                                                                                                                                                                                                                        	                                    !          $  &              )  ,          0      3  5  6  7      9  ;  <      =  @  A  B  E      H  J  K  L  N      P  Q      R  S              T      V  W  X  Y  \  ]      a  c  f      g          h  j      m  o  r  s      v  w  y  {  |  }  ~                                                                                                                                                                                                                                           "  %  '  )  *  ,  .  /  1  2  5  6  8  :  <  A  B  F              H  K  M  P  S      T      U  W  X  Z      \  ^      _  `  a  b  e      g  i      j  l  n      o  q                  s  t  w  x  z  {  }  ~                                                                                                                                                                                              	  
                                   #      %  '          *  +  -  .  /  1  2  3  4  6  7  8  9  :      <  ?  @  A  C      D  G  K  L      M          N      O  R  T  W  Y  \      ]  a  c  d  f      g  k  n  o      p  q  t  u  y  }                                                                                                                                                                                                  	                             #  %  &  (  *  +  .  /  0  4  6  :  =  ?  A  C          G  L  M                  Q  R  T      V  Y  \  ^  a      c  d      f      g      i  o  p  r  s  u      v  w  x      {  ~                                                                                                                                                                                                                                                                             	                                                            "  #  $  &          (  )  +  ,  -      /  0  4  7  8  ;      >  ?  A      C  D  G  H      I      J      M      Q  T      V  W  \  ]  _      b  c  g  k  l  m      n  o  q  r  s  v  x  y  |  }  ~                                                                                                                                                                              	  	  	  	  	      	  	  	  	  	   	  "	          #	  &	      )	  *	  ,	  /	  0	  4	  6	  7	  :	  <	  ?	      A	  B	  D	  F	  G	  H	  J	      M	  P	  Q	  V	  W	  Y	  Z	      ^	  _	      `	      d	  h	  j	  l	  p	  q	  r	  t	  y	  z	  {	  |	  	      	  	      	              	  	      	  	              	      	          	  	  	  	  	  	  	  	  	      	      	  	  	  	  	  	  	  	  	  	      	  	  	  	  	  	  	  	  	  	  	  	      	      	      	      	  	  	  	  	  	  	          	  	  	  	  	  	  	      	      	   
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                                                !  "  #  $  %  &  '  *  +  ,  .  0      1  3  5  :      =  @  A  C  E      G  K  N      O  P              R  S  W  Y  Z  ]  _  a  c      e  f  g  i      l  m      n  q  s  u  v  x  z  {  }                                                                                                                                                                                                              	                                        !      "          $  `ieH:W1x~̒$emXLy~؉M_.{~vW\8EiEc{
~܂֛Gԋo|C[6@p->6TO.}my&F)]ӕBTmD`4n>j=jB+\D'bV28>S2Ϗ{;zkJn̓COޘZOMS5Ȣ~kO=#UQJd@$D)ҠOĭs'-u2ߕVooyPhl$XԄcqO-R}$xD	64H!v0#K\sKqɮy+L-%!6Ɗ}Dy%ek&Gc(rg4l Ӑos߿vܵ8%gEWd2YogFN0Lu}ܒTwV=JC=sbPhiOXz5m&~HZA_۝*/~"jO)آjC/#=#9ؖ񎺊I\q@3郙
sGL>|7{$
`e橭l7~jV(rяb:RfMcbuԣ.'N<: ejF1BNDt*|qdi`nB&KncZ}sl L'ߍ,ޛMͨk!gRN
PhVUҿ5^nuYt4!MCf
g6'-5\@T.1 A@
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                     ^                     /                     ѵ                                                               :                     d                     S                     A                                         ?                     2                                                                                   >~                     l                     c2                                          ¢                                          	                                         "                    }                     '                                                              V                     S                     B                      [                     4                                                              +                                                                                                         ww                     9                     +                     #                    2C                     B                                          h                                                              4                     \C                     :                                         *                     I,                                         <                                                                                   9                    F                    P                     6<                                          r                     _                     _                    Cn                                          )                     v                     3                                                                                                        %                                          E'                                                              U                    '                     k                     "1                     0                    :                                         $$                                                                                   ͳ                                          y                     |]                     q                     g;                    `q                                                                5                                          g                    j                     ,                                          h                    f                     9                                         /                     '                     d                                                                                  "                                          4                                          T                     V                                           !                                          .                    V
                                          ~                     7                     4                     "                     v#                    9                     >                                          (                                                                                    Y2                     cc                     M                                                              0                     F;                                         :                                        /:                    !                                                             W,                      ;                     j                     b                     f                    ?                     32                                          V-                     _                                                                                     =                     R                     }                                                                                   Rm                                         9                    g                                          '                                          ,                     Q|                     :                     ,                    `n                     g
                    N                     w                     ɀ                     
                                                             ǭ                                          tB                                                                                       ,                                          9                                          )                                         Y                                          G                                          9                    )                                                               =                     gw                     -                    0                                                              /                    D:                                         6                     -                                         K                     /.                                                                                                       r                                          F                     3;                    *                                          r                     K	                                         AL                     i                     	                                                                &                                          ;                    z                                         ?[                                                               !                     u                    =                                          7                                         9                                                               +                                          Z                     L                     :                                                             m:                                         C                                                               ](                     T                     I                     0                    U                     ج                     0                                          B                                          dY                     j                                          3                     h                     Ț                     D                                          ^                     Bf                     ݍ                     y                     (!                     [$                    w                     )                     W                                                               $                     3                     R:                    :                    0                                          !&                     _:                    6                     5                                                               u                                         |                     
                                          Y                     P                     :(                                         :                                         d~                     l                                                               I                     H                     O                     g                                          ,                     g                     X                     X                     x                                          $                                                               "                                          D                     J                                          |                                                                                   $                      :                    -                                                               -                    2                     {                     :                                                                RI                     	                    /                     Y                    (                                                               *                                         q                     z                                                                                    1                     u                                          g                     Ȟ                                          |                     1                     9}                     #                     R                     J                     "z                                          	                     Z
                    3                     3                                          9                                                              &;                                                              %                                         J                     f'                    m                     R                     yc                                         j                    #                     $                     .                    O                                                              Օ                                          #                                           8                    L                                          &                                         ,                     3                     ,                                          C                     3                     R.                     ,    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                                        aF                                          $                    8x                     	p                     z                    q                                          F   "                   #Q                                                                                    7                    3                                                                                    Q                                                                                    y[                                          O                                          9                    =                     k5                                                             w                     h                                          =                                          pJ                     SQ                     o                     '                                                              P                    T                                          |                                          ]                                          Ŀ                     ɜ                     #                                          N                                                               a                     [                     n,                                                                                   J                     \                                          9k                     !                     #                     ]                     \                     ,                                         <                                          _                                                               8                     ב                     L                                          8T                     !                    T                     "                     D>                                          `                     H                     2                    V                     Q                                                               s                    a0                     @                     '                                         w                     hx                     κ                                                                                    z^                                                               )B                                          J                                                              >E                     :                    S                                                                                   KU                                          -                    ^                     G                     Ed                     B<                     9                     Z#                                                              j                     ě                     b"                     i                     1                    _                                                               7                     _                     v                                         4         a                             H
            )    2                З     l       L    i     p       aP    @*            Z    \"     A          `     /       j    8!     Q          
     1       P    @z*                     U       ?          =       O    @j*            (v    T     3      p    y     ~       8    `     A            !                            b     	     V           5
            <                @         +           "               C!     /      O    y                     8            -               0            uP    0!            ׏    p            y   0     =       A     O     8       -7        8       I    I#     -      0         _      &   {            E  "  R%            i   `     J           0           a         2      m          \                       q          4           @     p       l     ,     2        s               {          E                8       UK    05            %"    
            9                F          8       
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     L         @           (    0                     V           С     =       @    p     ~       u    `     J      M         )       +     G     0       <         Y       !p    02     2           `            2    `            [d                          T                `       ,    p     G           @{     #      +)    t           H    @     @       6    <@                I           JP                 
   @7!     Q           Z     #       _    "            *        5       s    R     5       ƣ         g       i  "  %            s         h       $   =            f7         e      Ab    p               @                0     r            `           h    P            b    "
     +           `                0S     H      H    p            l          d       /         =       	        q                       s         ;         H           A   x>                ;$            0   `     Y           P#     O      x    ޚ     `       o    p5           	     g                n                 0     @       As                V,   @     5           `     .          -                          8    _            RX                    
                8                B     3            l     :      J    
     =                c          V     V       8    <     N       p8    P                 *               "  "%     2       W         e       }    *             p   0            #w                     p     \       &y                X    PW!     t       S    `*                      F           f     :       (    P!                     >           7     :       )   @)           *=    ?     A          5                p            )               	  "  %            e_          L       5    @                Џ#     E          I     R      D         d       d  "  %                g     p       0    f)     .           o            T "  %     /       W!    l               x     ]       _    03"           d     .            $    H
     r           `@             8    !     6       @-   0y            =                h    &           e/ "  L%            k    pb%           e    `     }       g                F                 i     h       5   `&     8       :                *L    4               *             p   *             L    0
     =       $    *             5    p     ;       '   3           y5   p0     6                         *             R    4"                Pn            I    *                @     +      	   *             |    }           $         b      j   *             '    ;     i       I    `A     7           `9     <       $    o            K  "  p     5       3e    @     l       #   @p           I                L                t         j       T   A     o          Y                V     h       0s               $   P     X       c    0     m           Y            PD    :     (      +    6     6       E    K            n0    Pr     U           	     +           @     o       L          B      I    A     <          @     j                Q       V                FJ                    
     F       qf     ]            vi    p            .\         <               n          !            GH  "  %     /           
               !                   9       x\     6     4      @         P      t4    pN            _    `            h-               q                   tv                `           k                I9    q     P       1    0O            M  "  %     (       f    9            4p    \!                          6.   $            C                                   Z     9            @     S       q                                   4     X       4,                 '                -    b
     #                P       /        2       _  "  p%     <       	         Z      \]         6       Ϋ               	         L          4               =            E    0"           hj          ~                 m       8              2                 G    C            1   `ę               "  %                0     !      |    x     8       ]    <     Q       4   0#     ?      ]	     P     <                         P     Q       >                i    `     N          B            A                +        s      iZ    !           v%    u     U      
    [            *    |     b      e    T!                0?!           :    W!            k    v!               `     +                C          `x            W    OV            :    f                            U                     b                o     k                %      V                5    A     Z       Y     H            i     )     3                       "  %     1       y    `     R      N         G          %     P      ^    P                            q                          [       Ӈ    p            x    `                g#            P2   @                             a          H            R     H       ]H    p            %         m           
           9    0            9          8           hR                           O    /     X       l                ;    }     a       ~    k!            w   o     <       ,m    !           6        f                      3    P            L                 _   pr     6           js     g      R    }#     t           #           *    oo
     u       w    б     9       ;    po     !      %w         ]       Ql    P                    +      F    0%     b       !    B     =      ,R  "  %     ^           0     8       ܛ    ?                @     @           /     3       Y         r       Ǩ    R#     {       V    PZ                C     r           @                pA     Z       c    Ь     P      n
   0D     2      F#    E
            %    G            >j    u     H               w       `     @+     z               b           q     ?       k    $     A      0   x           1n         6       ,   `     <       d                     _     c       "   p     X           I            P    P            i    `     ?           X     ]       $     !     k       O         @       -        N       #         B       '    !             e          
         @     @       X         ?       k    |     >      m    @            t         >       f3                    
            r    P     o          `D     9          F     @       h    "              "  "     1           `     @          M            ):    j!            K          W          d
     m       a                    C     5           0K           r    К     `                                           )            K  "  r%     <       3r                -   p2     4           @H     9      Q                b    #     <       )   p            e    p           qG                /    `T!     Z       G         @       =         X       @|    %     *      %         ;       μ    `7     R      Rp    I     3       .   #     !          0n                            W8    m%           D    G            	,                              h     i#               w            i                   p      >       !         O       ;    Џ           -    
     \       .                9{    `     {       (    r     g       6   p               @Қ     `                       z5     N     h          N            <                 US     	     8       Ѯ    Ù                p     i       *              ~e    `                0            H    PE            ܵ         3	      N    (     8       .    p
            Á     -     @       %     %            |    ҡ     %      S                  "  %     *       >         w       "	    C     S         "  l%     c           9                
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                 @     N          Y     5           
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     @               m       U    8~
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                     H                      #   #     q           !                     v                ;      I\                q  "  %            [         8                ;       %   @     5       S         F       W    p#     a           #                 ?     q       Bo     `"           L>    @~            ~         :      *    @%           i    r                      s       m    @(                 #            x    &     f            ę     H       e          8       8                )    !           _    &                pE#               @s!     5           З     t           P|             7    @     J       %                M          @           03     5                           p!     s       ޿    0     \      d         6                       3         |          7                p_                ,     F       Dz    Ù            K "  %            x    P>            D   K            cJ     9     9            7     T                        4         Q       %  "  %                    X                z       	          u       e    @w     6       (        O       D        8           0p           [    p                     8                      2              ,   y     &          q     9               @       I        o      [w    P'     L           PW     <       o]         L       '   @?     (          0     Y       @    p            [    "                @     <           pr     T          @           T6                ͡          ?       R         6       Q         8            s!     5       ?    0     =       ,        s       .	        @       [    @     @       W     P     *      #               -    Z     1           0#     \       9    h            1   h           1               F    `"     o      T    `q     9       k    `(           	    Ѐ#            @4               R                     Е           a    0     (      -    *           ;                )A         l       w    `R            E    `     6       v    C     <         "  %     m       O    @     ^           PI     @           pd%     '          `                P            X    T     g       ,   q     V      `         <       9    p     S      1    S!     H                !      q    [     k                7                |        "  %                `                            *    ?     Z           @$            )        Q       4        3      w!   p!            i     
     u       &*    2
     @       ]    @t"     A      '    M
     @           PI     Q       (    '           ~N                     t     +       d   P     y          ,            K               ű    4                p
     I       KN         0                      %    
     )                h       (        8           @     &      0         h           >                }
     )                Q                     C                $    
           
   !            d    *             Z    K                H                $            =    ;           \                    p            |   !                              pE     7                ;           !           5'         X      $    _     3          N     |       J    *     	          ~!     M                      H   p           Z                e    P     {       #    `%            K                    p*               D     C          %     R      <   E            d    `     ?       -l         a       w  "  0     4       o$   0     X      F    0Q#            =         +      k6          D       ^9   &     R       Cy    0#     B       
V         o       ߆     2                 p           e%    F            T    @F*                W     D           _            K    G     5       F    r     T           @B*                @>*            55   p     X                "       d    !     k       a    *            Ҙ  "  %     4       N#   0                           |    w     J       X    !                !           *<    `F                0     H           @     d       7   0            b    7!     P       .        8       O    1     6           ,            z    o     I           @Z     F       K    p               =                `P     X           )           J   P/     Q                          @=           g         ?       !}                V         @       v    a#                %'                     ;                d           pL     8      ~    !            -               4    !                #            X  "       f            К     X          j!     8       yh    0     N       LF    @     c      q    9     r       b
    0s            q    =     M       
$    >           *              ʰ    =           v#    m     ;       э                    C     5           /     8       !   p                 ]     p      :H    B               @            n    B            X  "  %     D       4    P     e          @<                H                 p!     2          &     8       [         H           '            ~     E     L                f       H-         N       	   0,     O       <                T    `            2        h                                         p                0"            x    H%            .1    @                     i      |    @&     O                      ~    0     
      2   v           
&               x	    i     6       ܝ         3           @           l&                     C                    V          `O            =    b                 n     P       A    
            [    p            ,   0            g    `x     W           y           gu    R     c       y     :           V          @                        E         Q       g    p     Y       8K    ;     n       ?    @)     I      z     t!     6       v    0>     d       Nh         v           P}     +               E           P            0   v     Q       ,    '               `
     ?       UZ    #            H    }     i      Ԕ    {"     :           м           +-   PU                      3       (    m
              P            F    0u     a       `    <           ?        d                     3    #           `    `     t       n                >3   P     i                >          P)     J       e    `                Ù            ^                   ;                p     u           PX     >      |                r          @       4    "            a[         8           )     0       XY         1       _    u     a       X         k      }    %           ,    te           pN               B    `            p'   p     p       ڷ    !     b               :       Z                (        P       
    =     5           Pz!           P1         V       )         m       z         D           `                r!     T       R   `c     F       L    
                           Y    O            &    
            7    p     @       Q          .       `    q     9       .o    P     u          '                PR     q       k    h"            y    !            Z         5       k    %           z0                                 p~#     d          p                     S       nD         W       z  "  L%     <           px            %        8       C     p     5      )_    0@     ]       5   `                `
     M          C     f           П            c                                  ѧ  "  V%     s       ֗         J           @&*                .            ^    @"*                           K    p	     F                      R    n            Q    0r%     $      x     `     V          p     ;                       V                fC         e       e    Ц"     b           P&     B           /     3       F    ;     }       D  "  %     [       ˊ    @_     F       c    U     t       ŷ    s     +      &    n     H      /          D       5V          V       w    (            ?         ^          i            8z    `#            =    `      
      0    +     3       9  "  %                            '    #                7!     T            9           b         =       ^    P@     2               Q                 &                       D    0<            &   p     j                _           P            6_    H     2       E               `    !                    5       Z    P$           T7   P     ;       +         S           0m     ~       N    L            >                                "  %     J       &    z"     d                8      X    !     T           "                     @                           /     n                 8       k    }
     #               i       .                                n    p            X         R          w!     5       |                6    P     X       ͟    Q#     ^               @                w      -6     #     P                       >    j               L     0            l            0         *      R  "  %     M            !     s            &     ]                5       +              +    	     j                                      jT  "  h%     /       L    @     @       d    (               0$     n       E   p     }      r    7                    >           #     7       q     y!     H      =F    @N!           $    Y            p   @     7       1   K     5           0a     m                j       VV         ]      9         6       5        D           @Z*            e{    0            ,    l            V    @J*            >    u!                              @:*            B   `                @**                0N     6       c    b            )G    z                ]     >       6    ~
            s                   0G!           @`                H    `               @            t    o0     P            \                p           Y                5+    D?                k     m       /   '            ֞               r     "     h                           E                     Q       P    %     .       [u         b          P     6       R "  %     Z       D    0     .       I    Ѝ              >     h           P!                P            xO    P           	#    
            t~    @^            !    {     ,       )P         3          @	               У     #       4    P           
         P       m    @     8       %F    "            fS    0            ,   @            g)                   B               p            @    `     @           @     8       =          _       $   d            +        (         "  %     "       ,    r_     V	                     B    0     C       'c         [          
     8           A           M         `      ]d         ;           M                      c         `/     >                @       $   %               0            )        o            r-            $    f[     M           Jl                #     <           0     s      Lq    P           z    0     A      T    `           Z    L            /         0               q       }	 "  &%     ?       h          J       s                 |    Э     G           |     y       s    _           6                O  "  %            D    %            ˛    p     P       s/          Z       w    w#     ]       \    p     [       8         s               7       S    *            Ƹ     *     b          P     d       ~d    p     R       J    p                p            4    `            n    @     @       '                   P#     \       e'    )                 _"     7            Z     m           pj%            m    P            t  "  2%            9Z    	            o|    2           Z    0P%            0    
     0       h    p     G       }    {     K       2 "  %     #                               @       U3   PK     T                           0     A      ba    p"     m          0p                T     5       E7    r!     4       ϴ    >     8      ɨ     U#     h       <         @                `          `             b  "  %            (    W     H       1                        1               @           @      i       (    
	                     %      5        @       ;    P     ?       \    з     <       '   1                b                C     U       4                   `.               tk            1         X       F    p3            R         m           p
            7   `M     E       >                d         W       !X    p              a     Y           S            9   0&     l           2            &   p           f    
            o    t     #           x           #   F                /                *            $                    @     8       @    8     m       ++               ,          @            #            @          @       ~7                )   ?            ?s    0     p       N    P     R                 g       L                    0~     V       4    	            L1 "  %     ^       6@                   p     c       :               k         L      ^         v           4     7       2    $            >    p     i           I           u    o     R       9   0&            c    P1     T       G          P       /                   `F!            28                                    I            "   `              "  %     +       4    0h     `       O$    ~
     '                K           .     b           `     \       9         ;          0!     E          C     >       K    `!     #                     ڦ    `     L           `"     8       G    p            O'    te           (    H
                @            	    f     `          n     Z                @         "  q%             (    j#     c       @"    7
     F           s           ,/   P     L           `v     P                           &           2   !     j                 9               6           
     q                      V    Q     l       !    K     6       ;     F              "  %     T          Ѝ$     $      e    @            H  "  %     M       A^    G            13    8            B          T       S         8       #    5     0      څ    L     6                @          N%     X         0     B       P0              ?m    #           O               ϖ               0    `}            ;    	%     |         @            d0   pc                `            i               3  "  &%     "       K         r       t  "  X%                !     {           !     '      t    "     ?       z     0     i      	    m     C      ~    @     Y       A&        z       /w    PV                J     4       K  "  0%     (       1   `      M                                      W         @           @*                      !      u                   @*                @~*            E+   #     \           G            i    M     Z       %    
            @    0           Bv    +            )         m       Z         8       !    
	                )     .       +    O     n          W"     j          L
     S       A                =         @       a    po     u                     f    I                ~%     V      _    t!            Mk    В     n       {               -    
               й                F     `       K    !     5       %        i                 @           P@     Z       '+    1v     I           &     S       k         8           N     <       yZ  "       7         "  
%     L           ^             <   $     c         "  %            ä                #   p!     6       |          K          0%           M/    %                ?     5       r     !           H                    @            ".         .       @    @Ù            x$    ^     .       x    P     M                       (   `     k         "  %     8       8    e     I       Y "  R%            5                A          K       ;    {           F#   B                 p     `      Wf    `             C    @!     T       "    f
     (       ͭ         5       ԁ         n           P     %      Lg    !     w       a          =           @     8       o    p                     V      6         r           
            l    PD           g.   "     q       >    ^!              P     5       c         |      )    J     U       	    P=     X           p                                        y{    `     S       t         Y         "  3%     {               8         "  %            u    p           qn     b           x          Z           w     ?                      \  "  %     J                V       7   `՚     `                 M           >            '         N       4         @                `       A    `     M          `                   Y       "+   @z            "%    :
                p     Y       =         Y       >    
            x_    &            I    q!     2       e   P           B    T            7         C      b  "  %     =           `     G           F            +    !                V     V       K     Q           DX    @^           8    `W                {           Z.   r     n       U                    0           F                    `.            >    P     	          *              "  %                `*             a     '            m3   "              "  v%                @*             g    w            )                A                          }          *             	    `*                 @)                *             iD          5                          @*             8
    A     F      gM         Z       m    *                 d            c    `*     +       r         <       9         5       y  "  H%            61   O            n     e!            7!    0
                   <       @2    0              "     $      x@                ~    `u     3       ٴ    pv            Jx    7     H          J            P    `{     S       tS         ^       	    N     =            k            L          ?      {    @D     ]           0     6       }F                c    U/     n       h  "  ,%     w       M    `|"     :       }    `     I       N               5   L            "    (T            u         K      {    `%     m       @    @     C       T'                  p     P      +    `     .       R"        /      
    =                *             i               pX    0                 *             De         F           i     6       &    [
            O     *             կ    *             Q  "  "%     2       y    0     X       :    G           Y     *             9?                                !J    p     n      @    `X!                 *             e    0     8       9    h            nL    !           Rj    @f*            +     *             o    P#     \           }
     -           @b*            )&    6Z            ,                                 #    @^*            *    o
            2    @     >       _    `]           ɋ    #     <       !     U     5                 6       $    ~            &   @I!               z                @     V       %i  "  %            7   u     D       )    $     #      6                         G       .                    !     b      F    y            (4    P     =           %     `      _               ;   \K            7a     1     e       2         T                          h
                1"           X   ;     Y          \     f       '        m       =9          X      1               '    P     s               L       ]    R!     d       v
    ?            u7                    
	            y                 7u    *             L   05           q     y"           $x    *             %    PQ           s         s           z*            }   *            )    h
     /      j     }     i       ɐ               H    `l                p%     @      %         1       U    `X     ]       ;    !     5               6                /      7    (     ]       :     9     g       ) "  %     h       ,Z     c     V       4&         3          #                           6    `a                    C       L    !            {    >     e       <                        H       ~         @           P           5    @D     O       0                 8        n       ,    u     &          0             =    P     l       [     [     7       4         m      7         -          @"     L       Y                u    0	           [         S       O         @       p         M          @*                 Г     a       H    A     )      ,(         J      f  "  T%              "  %     :       |7                               ;    P     8           V            *         >      h9    {     
           B           ՠ    p     O       D                 W    E            ֌                   p     [                >       .    p               pt           Y-   p           (          r           s!     2                 E            Q     M      e    `     6       ]
                gl    +     y       G{    w     Q           "           s                 !   P     6       j  "  %                 5!                /
            g         0       s    0d#            8    \G                ?'     6       5         :          u     z       {  "  i%                %           Ή    R!            ޖ                    #     1      X    `$     =       %        5       z    ̄
     @       "                    &     ]           @q!     3       	   @w           v    @     i       S  "  r%     P       P    >            %    "     ,      v2    pd     D                      %    M           b         q       Q    p(     c       
    D     >       #    A
            1         @       D         V                       G    b            &   @     H           r            	    E     D       E               z    0     z      [                 "  ,%                               P           &    G%            W@    T                    e       F(    U            W   Pr     n           pE              "  %     1       Gr  "  n%            %         9           !           (         6       *    i                                            a    u
     1      e?    @            L8   Z%     \      M         J           `                     E                        /         K          ߚ     @       #   p     f      ܾ     =           
   `            ~          {       f    H            !j               z    @           d    PX     ^          P!                           Y    ՚                     @       x   @           7               N                    0f     =       6    Э     _       v         >       _  "  %     ^       L^    z            M    w     q      N    T     5           k#     ]      ۜ          g        "  %     /                                        0              "  %            g    `&                PM!            E  "               N    @     ~       n8   "               c     i       p    0"           \         c      Ak     p     9      U     !     :       6         Q       ؈    =     5       3          B       /   0     m       5-    
            8    /!                                 G            %
    @                p%            q    ,            &                    !     5      U    `            J     8                                F            o         8           њ     `       +     n#            2     G     2      x.   @     _       0    L
     #       R   $            B         u           `              @     V       	                             b+    L                                ߚ     @       Y         c       l    {"     :       ?    Pk!     o       *4               +                  @G                               !     v       !   0     a       -N     f!            S    @            1   @2            Q    N                |"     :           0@     H      *    )     ~                A           '                     ;       /     O     1      &    H     D       l    @     K      ݒ  "  b%                             ;G               8    `            b4                 k    0     0      EC          ^           P            c    0w     8       \W  "  %     (       .    h%            .    ޘ     +       r    -!     {         0L     2       2    @)             8          g       8   K     5       L          A          p     8       ^!        @        a    @             xu    @     s                       N         |
         P     x       a         h       ^     j     5                          P     X       \    %     z           pv           0U               50        g       G    PG     >                 X       [   @*             "  %     -           `@     <      -   '           )E    _     a       ?    0'     y       EV    p           (I  "  4%            O         @       H                   g"               y
           C    @            3          ;       d    Z     *      6               I,    8
                0=     5           `3                P                    u       Ps         Q       ]     p           A    0z     L         %     )          1     m       fb    M           1   p     j           p     `       u,         &       "  %               @     G      %              	    0     `      F    0           
7   %     a           p           ӂ     :!            m    Jp
           9B    |            :    0     m      [Q     !           
0        K           -
     C       M    @            ,J    /            S~     }!           .    E                и            8  "  F%                W           6    3                P            ge                    U!            "    p     
      .}    @     @       k;     T           xk    i     Z       n                 h     p           0J     2           P0            #    =     U          G"     9           `     ]           w"     f      d    P     5            0-     *      [e    0.                    8       {    @B             )   
     [       rm    о                 *             H    p!     Q          *             +D    @     h       MS    `	           _$    Q           ]B    0           /   (     y           &            C          e       $    #r     M       [    p0           i                   #     <       ՚    @            KO    	     M      @          ~       v                d1     d     I       n         ]      `m    $           ;6    u               "                           i    @            ǩ    @p!     Q       A    P            #    h            1    M     J         H     P          pR                M           z    0Z                            E         6       E         <       ٺ    й!                w                a            W    0&     	          
                ?                          8	    ]                               j            Ns    p     k      +h    j%     R      X    |                           p          8           +     U      Sz    v%     D      3  "  l%     \       z                x          >       Qn    p&            x     #     i       L    0              !           ?     ;!     K      E    0"            Va          t                a       ҥ         w       n"    
     e       e    p     #      #'         j                          `            T                37    r               0V               `!     >       1    >            n<                  0U"            p          J       0    `     ~         п     X           V            e   _     P           pH     c          `B           5   @%               '                s!     4           ~#     B       H    
     @                /               >       ]    `     c          .            A    f               4     p       <]    й     Y       D    ?     7       p         e      2   "     ,      6>         @           @*             	k                    P     &      {    2     6       f   Pe            `A         =       4    0               a            W         :      ;   p@&           Sc          Y       1         Y               a      <f                        %          0*     @       A         +      h         *      y                n.         J          p     Q                      ``                   #           x    `N"            #   p           Y  "  %            w  "  4%     7       {    @H                @$           5    p     D       K    %            ~     >            k         .      3     U           \    @                     8           #     V       %    `#     C           v
     ~       f    ^     $      ]    !     s       "    e"     z         "  %            	          5       (    Y     :       <    p     M          @p#            D         Z      F9   &     n                             M     9       o    P!           4   !     m       {`    pn     3      ! "  l%     c       A    "     <       fp         8      ~         S         G     7           4     >       .    y     @          hx            /    pf     7           @     @       K                          5       N                W    `r     w       	                A    P5            p    *     i       2    11     ,      S    P                           x    `(     b       f!    w               P           -5         C                @       ΢               '    P5     w       t,                (         v           Ϛ     P       T    @     @           px     ]       %                !    Y     _       s   q!     6       s     3     l       :                    ~     6       G    %            g%         9                8       _    pk     k           }     x      a                &    s     R       2                <A               .   *                 =     ?       7               q    `     O                        Ga    P                A     Z       7
   (            A    m     L           `     H      .0    p}           i               +              lA    p     q       u  "  \%            7        u      '    
            w    #     B          в     ^       J    T     b                /      a    #            >    P<!               `!            ,    !     3      3q    :     :       HW         3       q(   j     B       T         \      )    @           k*   I     3           @     U      2 "  V%     Q       Q    #     /          С"            $          `       -   \                @               z     y                %      R               C    #     -      J         8       ؙ                                J    `H                    `         "  T%     M           pG     d       o(   f                             i
            {    A     T       D;    &                            9M    >     I           p     6       |     Z%     ]            >     (       a         @       m     G     L                (           @!           ,   pL     4       C0    p           b6               4   Pg     H       A         Y       >          |       %    #     \       K    
     \       N    @o     W       n  "  %     %       C:    P           >h    !     :               L          `]     l       @    t~
     <            0!     "               J           Z                t!     5       h(    
               H     Q       `     @     +      qj    z#     [      ZT     '     z            #            ,         +       ܉                V   J     @       s          8            *             V                          >       	X    p                           ^-    
            |               J                \                    @     ]           G     z       e    $     j       E    %           2                   #     
      M     $     
      j&   0     y           9
            <  "  %            {    `     >       !   `     ;           
            6   0                                    @       L          m       o         X          P               P5                @'           e2   0                           r    @           Ԁ    @#                    P       f^         6           E     q       #    $     8          @V*                      5       1                @                                w   @R*            B   @N*            wC    "     Y       $7              ]6   pG     N           p            29   pm                     t       G         Z       O    .     |       '   "           H.   2              @f#                I      #         
     y           0     :      N    ]            r    `           }    D     5       .    3     +       1               /         @                      J    [     w      y    p=     3       x1    >            L    
     >       t    PF                     <           "     V                0       O         X       w    v     W       E                !                (         _       {&    hw
     k           .     Q       U    P     g           P     \       y          6       j                    5                P     C       ؓ         Y         !                    i           T     j$      F         :           r
            ]w    '     h       g         ^       W    @"     b           N     5          O#     P       o2                [     q!     3           @     q           @!     9       }    .     2           C            5                	    w     ^       2    `     8       ݊    @     ^                [                ]       E                  p     `       H    :#           m          h          pI%                "     =      \#         ?       CC         f                 `      
   1     5       b         8       ^  "  D%            dk                 j     a"                p9            9         {       /   `                g            I5    F     @       +W         c       0    Py                     Q       /d  "  ;     6       5               3    >            8D     $     6      Re         7       ɝ         ?          6     &      =    R           Q               *                   $                               `{"     :       E   @L     R      P          @           !                r     $      v    @     M       @     {     i       /c    P     5       N         6       +         I       ?    p1     v                       m          i       %    r                &     D       ū          @           P                      ?           @b"               )     l       N*    Ѯ
     u       sY    `     $      (    %               #            /    \     T      %H    v                
            P    ҧ
            l    P-     8           P           h    `                5     <       
         5       Ȭ    @               
            %                <     $                P7     7       6         @       a   p     ]           ps     K          d"                u     6       )         8       4    U     I       3{    pv%     ?       v    p     `       E    z                    =      5    k               p|     h       7    +     c           /%           g,    h     7       G    0     9               O       *    @     @           {     <       Y&        Y          8     A       5   Ї     &      n          m      T    J     l       '    {     1       0'        O       r    c     
                       @                )         S                      L"         y          	     A       4        d       f    H>            F   @     @       =         h       2W    0     8       6        M      a     Ӛ     `          N#            "    
     4          @r!     T       ,>    p           x         <       )?         H       	   0            ls         6       ]    pw            9    D            T                   `<            (   '     F       /                     }                 !              @6*            8         {          @2*            TL    1            ќ    !     s          D            R    @.*            8    D     9      ^    P     O      >c    @     &          @               p     `       H    V!            & "              uo    `     g       ?    @L            P     D     B      q
    0            t    (     R       (    M
            Cw    M     F       8   з           t    :            X    A            &r    >            6   `	     8           `Z"     H      l    !            -         5           d     :           Е     b           1     5               9           P     o       *   p!            q         @           @             {   H           qy         @       =6   -     y       [y    o#     q       H    o     `          	     v               +       l    
     B       yt  "  %     R       "    E     g      E    !     8       .   P+     j       j    @E     G       ,        ]       Y  "  &%            [    x     (       M7         O      p    %     D      3    Pk#     c       p)   p!                    ;       :    0     6       ;    V
     @       ].    1               .     1         "  P"     1           P     !          R           3    F                     |       i    v#     B           @     e       vM         X       4    2#     C       0    @:            ;    F            h"   !           t+    
	            5&   p     .      y          X       a,        5          M     f           I     &         0     T       :         2          0                Y            g    0     Q       n    y#                     8                        J&    6X                      h       {    @U     5       3  "  T%                     q                       6    @P     C      o     :            E   e     6      6               9    G     :       -        /      <P    @t!     8       g                    pZ     o       }         3       ,    O     X       Y                t    N     ;           p               0            y         8                6           `=     8       )    %     6       ˏ     ՚     `           2     b       )    
     #       6         Z      f    pJ     6       I+    
     0                0      Y/         :       {                    0           s% "  %     g       X         I      9    %     :       :$    hh     s       M    '           n5               \                 r    
     F       
        W       A    h            '                ]    0"           Q    G     \                7          0A     e       lE    `[     7       w    f            G    Й     n               a                8      f    ~            LE         B      |}         h       >   P#               TQ           R    (                     e       U    J     R      :    S     8           `$     x      [)   @4     J       }    (     5       	   pV           9        8       7         *          q     D       b    =     O                5       ƾ                     @*            
    @*            B    @*            v    E!            C    C     Q           _            q    `           8    !     q      #    00     2       |    	            rK    !     8                       )    	     I       8   G"     v      hV  "  %     =       K   0w            `:     R     A                !       L    p2#           
         V           4)               `
     0       41                {    0           n  "  |%     6       %]    @     @       H    @/     h                                      ~    u     @       	         2       i7   P            +   h            ]    r     G      +   `j           8     R#     i       8    !           jR    Қ     `           M     k         "  2%                ,                F            ?    0           gh    /     @      1    !     ~       *   њ     `       ^                    %            j  "  %     [            +     I               e           P     <       g   ڗ$     f           F
     l       bO    l"           #                  &     )      R   0     4       ^     $            
   pe     ?      =   |>                     H       !    !     s           0v#     I       +    N     P          J     T       4          8       
                  O#     U           `     E      I    0                    W       =         <       . "  %            -   +                0            }         [      q    @"           z&         6           }
            	"    
	               F            Ď    "     4       "                        m       "1        n       2    p     r           @            t1   B     5           )                                     X       S<          u      K    0     N       ?    `}     M                [                       Q                F    "            28                   0b#     {           *            "   t           R    w                @                    y          \     8                           p9     ,      g                &         1       3 "  f%            5    P(     x       .    `B             Z         q       .                    
            0   ,            (    g           -               ߺ    `s%           9    !     U          w#               +     `          p3                t
     C       i\    >               X            0    `]            #         t           Ј     H       f    [     u       J    p#            gN                 0  "        3       c#   Po!                %     X      f                m-    =            &f    pN     8           c                      <       |X                     >                i%            5    `                    W                         ]     I          ;                @     A      ,         #       .     #     }            #            R    9     <           W	               @     ^      =         @       a    p%     Q       1                   0e            1   pA                5"     
      +t  "  %     Z           0%            .               o    `                0     T       g    ,     `       ,    =            _         6                L                       K    R     \      '    {     +                 Q       $    6     5           @     <       '    f!           0    `     Y       I    Ё%     Z       ۨ  "   #"     1          "     e      k  "  4%            ש    `               #     0          V     5       rD         +      ۃ         @           d>            1               y    7     H           /!     h       @        y       _    y     w       1    Ù             U                .    AP           m6         T      _    @     N       6    `!     *      dG          @                r           Є     k           4            c}  "  &%     ?           @+            {         O      M         O      6    ,/     )       Y    p%     6      `     \           m+        Z       b
   !     s       )              #    X                _            w         6       I         @       k                NA                         V      P3                S    p           " "  X%              "  d%     P       (              -    `              0     f       /   q     8       w                  0            k    h           F5                 QM    )     D       }    [     A      Y    n#     F          x            _I     y     P       @/    W
            1                    F               pA            '`    a%            m                "    ڲ
     -          q%           Ʀ         @           D"           ]    0/     M       Y         k      m    `            ǲ    0!                      Y       4    P                \
            &                 a        %      6                P     6#           ]&    ¡     .       x   p                 "           ]         N           	     8       {    K     =       @1    `                p     L      ߸    P     `       /#   `$     8       {    `     ;               X       {'    R           L    Ps           ~    p     t          P     D       9    j
             "  %            3g  "  %     D                      "Z          @           #     e      Є         k       ^   0            ;*    
            [    ]3           n*    s
           q         X       z>         /           &     F       7    
     y       u    
     C       K                g	              c    {     F       q                    p     M       !2    p#     n       @     "     :           p%     J       ~8         |       6                         D      +    [     {           0     T          @     ;            
     0       k    O     2      6    @S     O       l    #            y    d"            9.    `     /       Zv  "  %            ~    0            
    0F     z       k    0     W       ǃ    o            '    j     +      @    F            b    )     j          @Ϛ     h       R    P            (               /              T  "  %     ^       3    @           Y    %           a         _                     r=    Px                @\     9      {    @                            {    S!     s       6    $               Y                   Y       d    q                           w    0                                              `     8       o          3       +% "  %     +       x    @     8       3  "  f%     e       w   o     <       t          B          Ù     0          P/            +    }               %     .       ^5   "     B      O    #           f@    `Q     q       'a    r     k       '                v    @     y       eQ  "  ,%            .   #            Z=         d          |!                @               D     S      E    "     O                #       ;    Q               3     V      ]    @     8       -    p
                &            hU  "  
%     L       O    `Ù             [    p            $~    p"     a           )            	                  !     b      i!   %            S                  @     u           `N     <           wf
     *                      s    p`#     y       -    W            
         9       s    P     -      %    A                @                o
            s)    +     ;      c                |         b       V               c   @ߚ     @           	            C
               3,   P             Xo    @X           5Q    H     c       /               $    pN            _f         G       +    hF            j                 r    a            B    `            M   P8!     a       s    p                M     8       M_          8       * "  J%            [    `)             ;    `Y           7        R                       9   p     m       G    "                               @     [      м    8     G       A    ~           iI  "  ,%     w       `    :                
     8       K    `\            >         `       s    @     Z         "  %            
         Z       ,^               nH    Z            m    `o               л            c4   a               P     y         0b           |    0                     +       +        G       S  "  0%     (               @       md    p     H       h    o#            8    ؔ            a   @v*            ;	    "            4    %     `       $    @r*               @n*                             M                    $            P    3            x     "           -   `B     6       	    5     ;           o
            v    `            5          J       8                b    ` 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  ( <    
  $ <    
   <    
   <       t;        ui	   <       ;        2   <       ;        (   <       ;        b  
 =       ;        	  1 
=    6	  . =    ؞	  ' (=    О	  & 7=    枙	  # F=    7	   U=    8	   d=    Þ	   s=    !	   =    	   =    瞙	   =    ➙	   =       .<        ii  0 =      - =    ii  , =      * =      ) =      " =    si	  ! =    ii    
>       >       >       *>       5>    ii   @>    ri	   J>    ii  	 V>       `>       k>    ti	   v>    ii   Z<       >    ui	   <     "                 "                 "            `     "            P&     "            P&     "            #P&     "            5P&      #            <P&     #            PP&     #            jP&     #            sP&     0#            P&     @#             o     `#            (     h#            /(     p#            B(     x#            Z(     #            j(     #            (     #            (     #            (     #            (     #            ă(     #            փ(     #            (     #             (     #            (     #            .(     #            B(     #            V(     #            a(     #            p(     #            ~(      $            (     $            (     $            (     $            ʄ(      $            ׄ(     ($            (     0$            (     8$            (     @$            (     H$            (     P$            *(     X$            C(     `$            \(     h$            u(     p$            (     x$            (     $            (     $            (     $            (     $            (     $            ؅(     $            (     $            (     $            (     $             (     $            +(     $            5(     $            A(     $            L(     $            _(     $            s(     $            (      %            (     %            (     %            ˆ(     %            چ(      %            (     (%            (     0%            (     @%            (     H%            &(     P%            5(     X%            =(     `%            D(     h%            I(     p%            (     x%            (     %            O(     %             (     %            +(     %            \(     %            `(     %            m(     %            t(     %            (     %            |(     %            (     %            (     %            (     %            (     %            (     %            (      &            ȇ(     &            Շ(     &            އ(     &            (      &            (     (&            (     0&            (     8&            t(     @&            (     H&             (     P&            '(     X&            0(     `&            ?(     h&            S(     p&            i(     x&            o(     &            u(     &            (     &             (     &            (     &            (     &            (     &            (     &            (     &            Ɉ(     &            ֈ(     &            ܈(     &            (     &            (     &            (     &            (      '            (     '            (     '            (     '            (      '            (     ('            &(     0'            2(     8'            9(     @'            A(     H'            J(     P'            S(     X'            (     `'            Z(     h'            &(     p'            a(     x'            r(     '            V(     '            (     '            a(     '            p(     '            (     '            (     '            5(     '             (     '            (     '            (     '            (     '            (     '            +(      (            (     ((            .
     8(            (     `(            .
     p(            (     (            .
     (            (     (            .
     (            +
     (            (     )            .
     )                  )            (     @)            .
     H)                  P)            (     x)            .
     )            +
     )            (     )            .
     )                  )            (     )            .
     )                  )            &(      *            .
     (*            
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     `*            
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     x+            %
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      ,            <
     (,            (     P,            .
     X,            <
     `,            (     ,            .
     ,            I     ,            (     ,            .
     ,            I     ,            (     ,            .
     -            (     0-            .
     @-            (     h-            .
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     -            
(     -            .
     -            (     .            .
      .            (     H.            .
     X.            (     .            .
     .            .(     .            .
     .            :(     .            .
     .            3      /            F(     (/            .
     0/            3     8/            J(     `/            .
     h/                 p/            Z(     /            .
     /                 /            b(     /            .
     /                 /            t(     0            .
     0                 0            ~(     @0            .
     H0                 P0            (     x0            .
     0                 0            (     0            .
     0                 0            (     0            .
     0                 0            (      1            .
     (1                 01            (     X1            .
     `1                 h1            (     1            .
     1                 1            (     1            .
     1                 1            (      2            .
     2                 2            (     82            .
     @2                 H2            (     p2            .
     x2            K     2            (     2            .
     2            K     2            (     2            .
     2            (     3            .
      3            T$     (3            (     P3            .
     X3            T$     `3            (     3            .
     3            (     3            .
     3            (     3            .
     4             (     04            .
     @4            1(     h4            .
     x4            <(     4            .
     4            (     4            .
     4            (     5            .
      5            2(     H5            .
     X5            9(     5            .
     5            A(     5            .
     5            r(     5            .
      6            F(     (6            .
     86            N(     `6            .
     p6            c(     6            .
     6            y(     6            .
     6            S(     7            .
     7            Z(     @7            .
     P7            V(     x7            .
     7            a(     7            .
     7            (     7            .
     7            (      8            .
     08            (     X8            .
     h8            (     8            .
     8            (     8            .
     8            (      9            .
     9            (     89            .
     H9            (     p9            .
     9            (     9            .
     9            (     9            .
     9            )(     :            .
     (:            9(     P:            .
     `:            I(     :            .
     :            ](     :            .
     :            m(     :            .
     ;            }(     0;            .
     @;            (     h;            .
     x;            (     ;            .
     ;            (     ;            .
     ;            (     <            .
      <            (     H<            .
     X<            (     <            .
     <            (     <            .
     <            (     <            .
      =            -(     (=            .
     8=            E(     `=            .
     p=            S(     =            .
     =            e(     =            .
     =            w(     >            .
     >            (     @>            .
     P>            (     x>            .
     >            (     >            .
     >            +(     >            .
      ?            0)     ?            &(     ?            7)     ?            @)      ?             )     (?             )     0?             )     8?             )     @?            !)     H?            !)     P?            "!)     X?            4!)     `?            F!)     h?            X!)     p?            j!)     ?             \&     ?            +\&     ?            7\&     ?            D\&     ?                 ?                 ?                 ?            "     ?            7     ?            :     ?            >     @            :     @            @;      @             =     @@             \&     H@            +\&     P@            7\&     X@            D\&     `@            `5'     h@            Yl&     p@            ^l&     x@            Im&     @            q     @            @q     @            o&     @            o&     @            p&     @            p&     @            $p&     @            &      A            9o&     A            p      (A            r&     8A            ,&     HA            ''     XA            r&     hA            r&     xA            r&     A            r&     A            s&     A            r&     A            s&     A            (s&     A            ;s&     A            Ms&     A            r&     B            Ys&     B            bs&     @B                 HB            В     PB                  pB                 B                 B            @     B            s&     B            {&     B            Q'     B            Q'     B            '     B            O&     B            Q'     B            Q'     B            Q'      C            &     C            R'     C            R'     C            S'      C            5R'     (C            IR'     0C            ]R'     8C            kR'     @C            {&     HC            {&     PC            {&     XC            {&     `C            {&     hC            {&     pC            |&     D            g&     D            |&     D            "|&     D            /|&     D            8|&     D            G|&     D            P|&     D            ^|&      E            g|&     E            v|&     E            |&     E            |&      E            |&     (E            |&     0E            |&     8E            |&     @E            |&     HE            |&     PE            |&     XE            |&     `E            |&     hE            |&     pE            }&     xE             (     E            &     E            &     E            '     E            0&     E            m&     E            '      F            W&     F            '     F            F&     @F            V'     HF             '     PF            
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I            &     (I            &     @I            T&     HI            &     PI            c&     XI            k&     `I            s&     hI            {&     pI            }&     xI            K\&     I            &     I            a&     I            59'     I            m&     I            x&     I            &     I            &     I            &     I            Xy&     I            &     I            &     I            &     I            &     I            &     I            Ɛ&     I            ѐ&      J            &     J            y"'     J            &     J            &      J            &     (J            &     @J            &     HJ            &     PJ            &     XJ            $&     `J            y"'     hJ            &     pJ            P     J            N&     J            ʔ&     J            Δ&     J            ʔ&     J            Ӕ&     J            ʔ&     J            ה&     J            ʔ&     J            ۔&     J            &     J            &     J            &     J            &     J            &     J            &     J            &      K            &     K            &     K            &     K            &      K            &     (K            &     0K            &     8K            &     @K            &     HK            &     PK            &     XK            &     `K            &     hK            &     pK            &     xK            &     K            &     K            "&     K            &&     K            "&     K            +&     K            "&     K            0&     K            5&     K            9&     K            5&     K            >&     K            5&     K            C&     K            H&     K            L&     K            H&      L            Q&     L            H&     L            V&     L            [&      L            _&     (L            [&     0L            d&     8L            [&     @L            i&     HL            D&     PL            n&     XL            D&     `L            s&     hL            D&     pL            x&     xL            H&     L            }&     L            H&     L            &     L            H&     L            &     L            L&     L            &     L            L&     L            &     L            L&     L            &     L            Q&     L            &     L            Q&     L            &     L            Q&      M            &     M            V&     M            &     M            V&      M            &     (M            V&     0M            &     8M            [&     @M            Õ&     HM            [&     PM            ɕ&     XM            [&     `M            ϕ&     hM            `&     pM            Օ&     xM            `&     M            ە&     M            `&     M            &     M            e&     M            &     M            e&     M            &     M            e&     M            @B     M             '     M            o&     M            &     M            &      N            &      N            &     (N            up&     0N            ȗ&     8N            ՗&     @N            &     HN            '     PN            &     XN            '     `N            '     hN            ('     pN            W&     xN            r&     N            &     N            &     N            &     N            Ԙ&     N            &     N            &     N                 N            `n     N            f      O            "|&     O             f      O            s     (O            /|&     8O            p     @O            Z     HO            `     PO            G&     `O                 hO            `Z     pO                 xO            P&     O                 O            Z     O                 O            Z&     O                 O            Y     O                 O            b&     O                 O            @Y     O            `     O            g&      P                 P            X     P                 P            n&     (P                 0P            X     8P            0     @P            &     PP                 XP            @X     `P            {     hP            v&     xP             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     S            O     S                 S            0&     S            @     S            @O     S                  T            @&      T            &     (T            &     0T            &     HT            h     PT             [     XT            `g     `T             f     hT            `p     pT            `p     xT             f     T            f     T             [     T            g     T            o     T            po     T             [     T            e     T            e     T             Z     T            p     T            `Y     T             [     T             [     @V            `     HV            `W     PV            X     hV             [     pV            Y     xV            X     V            d     V            V     V            b     V            X     V            W     V             o     V            V     V            b     V             V     V            i      W                  W            P     W                 W                   W            p     (W            P     0W            @     8W                 @W                 HW                  PW            @     XW                  `W                 hW                 pW                 xW                 W            @     W                  W            @     W                 W                  W                 W            @     W                 W                 W                 W            &     W            &     W            &     W            &      X            l:'     X            &     X            0&     X            L&      X            \&     (X            y&     0X            &     8X            &     @X            l:'     HX            '     PX            8'     XX            L&     `X            &     hX            p'     pX            ̱&     xX            '     X            &     X            &     X            &     X            2&     X            '     X            +&     X            v     X             )     X            g     X            )     X             Y     X            @)      Y            I&     (Y            R&     0Y            ]&     8Y            g&     @Y            q&     HY            &     PY            ~&     XY            &     `Y            &     hY            &     pY            &     xY            &     Y            &     Y            &     Y            ʲ&     Y            &     Y            ɲ&     Y            ֲ&     Y            ݲ&     Y            &     Y            &     Y            &     Y            &     Y            &     Y            &     Y            "&     Y            (&     Y            6&      Z            H&     Z            Y&     Z            _&     Z            j&      Z            u&     (Z            {&     0Z            &     8Z            &     @Z            &     HZ            &     XZ            &     `Z            &     hZ            &     pZ            &     xZ            &     Z            &     Z            ų&     Z            ĳ&     Z            γ&     Z            س&     Z            &     Z            &     Z            &     Z            &     Z            &     Z             &     Z            	&     Z            &     Z            &     Z            &     Z            %&      [            +&     [            4&     [            &     [            F&      [            
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&     0b            &     8b            &     @b            %&     Hb            3&     Pb            8&     `f            H&     hf            Z&     pf            i&     xf            x&     f            &     f            &     f            &     f            &     f            &     f            &     f            &     f            ɼ&     f            м&     f            ܼ&     f            &     f            &     f            &     f            &     f            &     f            &&      g            2&     g            J&     g            \&      g            s&     (g            &     0g            &     8g            &     @g            &     Hg            &     Pg            ͽ&     Xg            ؽ&     `g            &     hg            &     pg            &     xg            &     g            &     g            )&     g            :&     g            @&     g            K&     g            V&     g            b&     g            p&     g            &     g            &     g            &     g            &     g            F&     g            
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&     j            	&     j            &     j            &     j            C&     j            &     j            2&     j            &      k            &     k             &     k            u&     k            &      k            &     (k            &     0k            &     8k            |&     @k            &     Hk            &     Pk            m&     Xk            &     `k            &     hk            &     pk            &     xk            &     k            &     k            &     k            &     k            &     k            ʷ&     k            &     k            Է&     k            ݷ&     k            &     k            &     k            	&     k            2&     k            @&     k            P&     k            &     k            &      l            &     l            &     l            
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&     8r            &     @r            &     Hr            %&     Pr            3&     Xr            >&     `r            H&      u            H&     (u            Z&     0u            i&     8u            x&     @u            &     Hu            &     Pu            &     Xu            &     `u            &     hu            &     pu            &     xu            ɼ&     u            м&     u            ܼ&     u            &     u            &     u            &     u            &     u            &     u            &&     u            2&     u            J&     u            \&     u            O&     u            s&     u            &     u            &     u            &      v            &     v            &     v            ͽ&     v            ؽ&      v            &     (v            &     0v            &     8v            &     @v            &     Hv            )&     Pv            :&     Xv            @&     `v            K&     hv            V&     pv            b&     xv            p&     v            &     v            &     v            &     v            &     v            ߶&     v            es&     v            }&     v            F&     v            
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&     Xy            &     `y            &     hy            &     py            e&     xy            Ĺ&     y            ų&     y            ĳ&     y            &     y            	&     y            y&     y            m&     y            &     y            &     y            &     y            J&     y            &     y            &     y            v&     y            l&     y            3&     y            &      z            &     z            &     z            E&     z            &      z            `&     (z            &     0z            º&     8z            &     @z            &     Hz            &     Pz            &     Xz            c&     `z            &     hz            $&     pz            &     xz            &     z            ]&     z            &     z            &&     z            Q&     z            _&     z            &     z            _&     z            +&     z            &     z            &     z            &     z            &     z            &     z            &     z            Է&     z            ݷ&      {            &     {            &     {            
&     {            u&      {            &     ({            A&     0{            R&     8{            &     @{            &     H{            (&     P{            &     X{            &     `{            '&     h{            0&     p{            '&     x{            \&     {            6&     {            I&     {            &     {            &     {            &     {            ɶ&     {            &     {            ˹&     {            &     {            &     {            &     {            o&     {            r&     {            &     {            &     {            ʷ&      |            5&     |            `&     |            &     |            #&      |            2&     (|            @&     0|            P&     8|            &     @|            ?&     H|            G&     P|            
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&                 &                 &                 0&                 %&                 3&     肙            &                 &                 $&                  +&                 2&                 8&                 &                  &     (            &     0            &     8            3&     @            C&     H            S&     P            c&     X            w&     `            &     h            &     p            &     x            &                 &                 &                 &                  &                 &                 %&                 9&                 P&     ȃ            b&     Ѓ            y&     ؃            &                 H&     胙            Z&                 i&                 x&                  &                 &                 &                 &                  &     (            &     0            &     8            ɼ&     @            м&     H            ܼ&     P            &     X            &     `            &     h            &     p            &     x            &&                 2&                 J&                 \&                 O&                 s&                 &                 &                 &                 &     Ȅ            &     Є            ͽ&     ؄            ؽ&                 &     脙            &                 &                 &                  &                 )&                 :&                 @&                  K&     (            V&     0            b&     8            p&     @            &     H            &     P            &     X            &     `            &     h            &     p            A|&     x            &                 	&                 &                 &                 &                 &                 T'                 9&     ȅ            I&     Ѕ            V&                 &     腙            &                 &                 6&                  T&                 r&                  '                 &                  &     (            &     0            &     8            59'     @            &     H            &     P            &     X            &     `            &     h            &     p            &     x            &                 &                 &                 H'                 &                 0&                 ;&                 &                 c&     Ȇ            j&     І            t&     ؆            |&                 &                  2&                 V&                 3&                 }&                  z&     H            i&     P            &     X            &     `            &     h            &     p            &     x            &                 &                 ('                 &                 &                 &                 &                 &     ȇ            &     Ї            &                 
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'     X            '     `             '     h                  p                   x                              @!                                   '                 '                 '                 '                 "'     ȗ            ='     З            U'     ؗ            m'                 '     藙            '                 X((                 ((                  '                 '                 '                 '                  "'     (            ='     0            U'     8            m'     @            '     H            '     P            '     `            '     h            '     p            '     x            '                 '                 '                 '                 3'                 ((                 Q'                 Ğ&     И            h&                 U&                 i'                  m'                 v'                  ~'     0            '     @            &     P            '     `            '     p            '                 ,&                 '                 '                 '                 ˪&     Й            '                 '                 '                  %!     (            +!     0            !     8            '!     @            @!!     H            "!     P            `!     X            `#!     `             !                  C'     (            '     0            '     8            '     @            '     `            C'     h            '     p            '     x            '                 '                 '                 &                 '                 '     Ȟ            '     О            '                 &'     螙            '                 /'                 3'                  ='                 O'                 '                 C'      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            !'     (            &     0            &     8            <"'     @            R"'     P            o"'     `            }"'     p            "'                 "'                 "'                 y"'                 "'                 &     ࠙            la&     蠙            "'                  a''                 l:'                 l:'                 l:'                  f''     (            l:'     0            k''     8            p''     @            l:'     H            t''     P            x''     X            l:'     `            }''     h            l:'     p            l:'     x            l:'                 ''                 '.'                 (&                 ,&                 0&                 4&     ȡ            8&     С            <&     ء            @&     ࡙            D&     衙            H&                 L&                 Q&                  V&                 [&                 `&                 e&                  j&     (            o&     0            t&     8            y&     @            ~&     H            &     P            &     X            &     `            &     h            &     p            &     x            &                 &                 &                 &                 &                 +.'                 &                 &                 &                 Ò&     Ȣ            ƒ&     Т            ɒ&     آ            ̒&     ࢙            ϒ&     袙            Ғ&                 Ւ&                 ْ&                  ݒ&                 &                 &                 &                  &     (            &     0            &     8            &     @            &     H            &     P            &     X            	&     `            &     h            &     p            ..'     x            2.'                 &                 6.'                 &                 !&                 :.'                 >.'                 ;0'     Ȥ            ?0'     Ф            C0'     ؤ            G0'     ङ            K0'     褙            O0'                 S0'                 W0'                  [0'                 _0'                 c0'                 h0'      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            2'     (            [&     0            2'     8            2'     @            ʔ&     H            &     P            &     X            &     `            "&     h            5&     p            H&     x            [&                 D&                 H&                 L&                 Q&                 V&                 [&                 `&                 e&                 ʔ&     ȱ            &     б            &     ر            &     ౙ            2'     豙            H&                 "&                 5&                  [&                 3'                 :0'                 >0'      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            )3'     (            03'     0            73'     8            >3'     @            E3'     H            3'     P            [&     X            2'     `            Q3'     h            Z3'     p            c3'     x            l3'                 u3'                 ~3'                 3'                 3'                 3'                 3'                 3'                 3'                 3'     ȴ            3'     д            3'     ش            3'     ങ            2'                  3'                 3'                  L3'     @            ϔ&     P            O&     `            ˔&     p            Ԕ&                 &                 &                 &                 &                 &     ж            &     ඙            &                  &                  &                 &                  &     0            &     @            '&     P            &     `            #&     p            ,&                 :&                 1&                 6&                 ?&                 M&     з            D&     ෙ            I&                 R&                  W&                 `&                  \&     0            e&     @            E&     P            t&     `            o&     p            j&                 I&                 &                 ~&                 y&                 M&     и            &     น            &                 &                  R&                 &                  &     0            &     @            W&     P            &     `            &     p            &                 \&                 ʕ&                 ĕ&                 &                 a&     й            ܕ&     ๙            ֕&                 Е&                  f&                 &      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            L4'     0            P4'     @            T4'     P            X4'     `            \4'     p            3'                 3'                 3'                 3'                 3'                 4'     п            4'     ࿙            4'                 3'                  3'                 3'                  3'     0            3'     @            4'     P            	4'     `            4'     p            ~4'                 ?'                 O'                 r '                 O'                 $&                 &                 d&                 )'                  n4'                 v4'                  4'     0            '     @            #     P            #     X            #                 @'                 ,'                 @'                 @'                 7&                 @'                 #@'     H            )@'     `            B'     h            C'     p            *C'     x            :C'                 LC'                 eC'                 |C'                 C'                 C'                 C'                 C'                 C'                 C'                 	D'                 D'                 1D'                 CD'      Ù            SD'     Ù            lD'     Ù            D'      Ù            D'     (Ù            D'     @Ù            D'     HÙ            D'     `Ù            D'     hÙ            D'     pÙ            E'     Ù            $E'     Ù            ?E'     Ù            VE'     Ù            iE'     Ù            E'     Ù            E'     Ù            E'     Ù            E'     Ù            E'     Ù            E'      ę            
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x            P&     (x            0#     hx            7     px            7     xx            9     x             t&     x            U&     x            H['     x            H['     x            H['     x            H['     x            H['      y            	     (y            (     8y            (     Hy            (     Xy            (     hy            (     xy            (     y            (     y            (     y            (     y            (     y            (     y            (     y            .(     y            9(     z            M(     z            M(     (z            (     8z            (     Hz            e(     Xz            s(     hz            }(     xz            (     z            (     z            (     z            (     z            X)     z            !)     z            !)     z            !)     z            !)     z            !)     z            ")     z            ")      {            ?")     {            O")     {            h")     {            ")      {            ")     ({            ")     @{            =))     H{            G))     P{            U))     X{            `))     `{            o))     h{            z))     p{            ))     x{            ))     {            Xf)     {            f)     {            f)     {            5d)     {            5d)     {            f)     {            f)     {            f)     {            f)     {            f)     {            f)      |            f)     |            f)     |            f)      |            f)     (|            f)     0|            f)     @|            f)     H|            f)     P|            f)     X|            f)     h|            f)     p|            f)     x|            f)     |            f)     |            f)     |            f)     |            f)     |            f)     |            f)     |            f)     |            f)     |            f)     |             g)     |            g)     |            g)     |            g)     }            g)     }            g)     }            g)      }            g)     0}            g)     8}            !g)     @}            %g)     H}            )g)     X}            -g)     `}            1g)     h}            6g)     p}            ;g)     }            @g)     }            Dg)     }            Ig)     }            Ng)     }            Sg)     }            Wg)     }            \g)     }            ag)     }            fg)     }            jg)     }            og)     }            tg)     }            yg)      ~            }g)     ~            g)     ~            g)      ~            g)     (~            g)     0~            g)     8~            g)     `~            l)     h~            N     p~            l)     x~                 ~            0l)     ~                 ~            <l)     ~            C     ~            Jl)     ~                 ~            hl)     ~                 ~            |l)     ~                 ~            l)     ~                 ~            l)     ~                 ~            l)     ~                              l)                 X                 m)                 '                  #m)     (            ;     0            9m)     8                 @            Sm)     H            L     P            mm)     X            X     `            m)     h                 p            m)     x                             m)                 
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4                  &                 d                  %                  %                   J     (            @%     p            <Y&     x             4                  &                 @d                  %                  %                  F                 @%                  CY&                  4                  &     (            c     0             %     8             %     @             B     H            @%                 KY&                  4                  &                 c                  %     Ȇ             %     І             >     ؆            @%                  SY&     (             4     0             &     H            Pc     P             %     X             %     `            9     h            @%                 [Y&                 `(                  &     Ї             o     ؇            n                  %     臚             %                 !                 %     @             '     H            `(     P             &     `            n     h            0n     p             %     x             %                 !                 %     Ј            &     ؈            `(                  &                 m                 m                   %                  %                 !                 %     `            bY&     h            `(     p             &                 @m                 l                  %                  %                 !                 %                 hY&                 `(                   &                 l                 Pl                   %     (             %     0            !     8            %                 X&                 >'                 ^Z&                 fZ&                 mZ&                 ^Z&                 sZ&     Ȋ            ^Z&     Њ            ^Z&                 zZ&     芚            Z&                 Z&                  l&                 Z&                 ^Z&                   U'     (            Z&     0            ^Z&     @            m&     H            Z&     P            Z&                                  @                                                                    P                                       `            if&     p            of&                 vf&                 |f&                 f&                 f&                 f&     Ў            f&                 f&                 f&                  f&                 f&      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            p     (                 @            &     H            P     `                 h            @                 &                                                                    &     ȡ            P     ࡚            0     衚            @                  &                 `                       (                 @            &     H            p     `                  h            P                 &                                  З                 &     Ȣ            PU     ࢚            w                  &                 T                  c     (             U     @            &     H            T     `            v                 &                 0T                 Pc                 0&     ȣ            S     ࣚ             c     裚                              ?&                 S      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     X                 `            `     h            `     p            k&                                                   Y&                 T&     Ȩ            X&     ب            `&     訚            h&                 p&                 x&                 &     (            &     8            &     H            &     X            &     h            &     x            &                 z'                 &                 &                 &     ȩ            &     ة            &     詚            &                 &                 &                 &     (            &     8            &     H            &     X            &     h            (&     x            4&                 @&                 L&                 S&                 \&     誚            &                 &                 b&                 &     (            g&     H            &     X            &     h            &     x            &                 &                 &                 &                 &     ȫ            &     ث            &     諚            &                 &                 	&                 &     (            &     H            &     X            &     h            &     x            &                 &                 &                 &                 &     Ȭ            &     ج            &     謚            &                 &                 &                 "&     (            ,&     8            >&     H            Q&     X            f&     h            |&     x            &                 &                 &                 &                 &     ȭ            &     ح            &     譚            &                 &                 &                  &     (            &     8            &     H            '&     X            .&     h            7&     x            >&                 H&                 R&                 Y&                 _&     Ȯ            i&     خ            t&     讚            &                 &                 &                 &     (            &     8            &     H            &     X            &     h            &     x            &                 %&                 8&                 Q&                 f&     ȯ            w&     د            &     诚            &                 &                 &                 &     (            &     8            &     H            &     X            &     h            &     x            &                 &                 (&                 6&                 I&     Ȱ            W&     ذ            c&     谚            q&                 &                 &                 &     (            &     8            &     H            &     X            &     h            &     x            &                 &                 "&                 4&                 G&     ȱ            W&     ر            f&     豚            r&                 &                 &                 &     (            &     8            &     H            &     X            &     h            &     x            &                 &                 &                 '&                 4&     Ȳ            C&     ز            M&     貚            W&                 q&                 &                 &     (            &     8            &     H            &     X            &                 &                 &                 &                 2&     ȳ            &     س            A&     賚            &                 &                 &                 '     (            &     8            &     H            $&     X            !&     h            w&     x            a|&                 0&                 ?&                 N&                 &     ȴ            \&     ش            d&                 h&                 s&     (            &     8            &     H            &     X            &     h            &     x            &                 &                 &                 &                 &     ȵ            &     ص            	&     赚            &                 )&                 =&                 M&     (            b&     8            s&     H            &     X            &     h            &     x            &                 &                 &                 &                 &     ȶ            5&     趚            &                 &                 &                 &     (            &     8            &     H            !&     X            +&     h            D&     x            [&                 q&                 &                 &                 &     ȷ            &     ط            &     跚            &                 h(                 &                 (&     (            5&     8            (     H      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'     Ϛ            '     Ϛ            '     Ϛ            '&     Ϛ            .&     Ϛ            '     Ϛ            `'(     Ϛ            '     Ϛ            
'      К            '     К            )'      К            6'     (К            '     0К            7&     8К            I'     @К            _'     HК            '     PК            l'     XК            '     `К            '     hК            }'     pК            '     К            '     К            '     К            '     К            '     К            '     К            '     К            К     К            К      њ            &'     њ            ''      њ            $''     0њ            5''     @њ            B''     Pњ            S''     `њ            `њ     hњ            `њ     њ            &     њ            ]&     њ            0b$     њ             "$     њ            E$     њ            Ј$     њ             U$     њ            R$     њ            /$     њ            B$     њ            F$     њ            @"$     (Қ            oG'     0Қ            xG'     Қ            oG'     Қ            &     Қ            '     Қ            `g(     Қ            '     Қ            '     Қ            '     Қ            '     Ӛ            '     Ӛ            '     Ӛ            '     (Ӛ            '     0Ӛ            '     8Ӛ            '     Ӛ            <<'     Ӛ            l:'     Ӛ            Ӛ     Ӛ            hJ'     Ӛ            %     Ӛ            Xs(      Ԛ            v&     Ԛ            %     Ԛ            s(      Ԛ            d&     (Ԛ            @%     8Ԛ            s(     @Ԛ            rJ'     HԚ             %     XԚ            s(     `Ԛ            J'     hԚ            `%     xԚ            J'     Ԛ            J'     Ԛ             %     Ԛ            t(     Ԛ            J'     Ԛ             %     Ԛ            0t(     Ԛ            J'     Ԛ            %     Ԛ            J'     8՚            o&     ՚            o&     ՚            &&     ՚            .&      ֚            =&     ֚            >     ֚            D&      ֚            Q&     0֚            a&     @֚            g&     `֚            &     ֚            Y&     ֚            &     ֚            &     ֚            &      ך            &      ך            &     @ך            0&     `ך            &     ך            K\&     ך            &     ך            &&     ך            .&      ؚ            &      ؚ            &     @ؚ            &     `ؚ            Ђ&     ؚ            s&     ؚ            6&     ؚ            =&     ؚ            C&      ٚ            H&     ٚ            U&     0ٚ            &     Hٚ            &     `ٚ            &     xٚ            =&     ٚ            F&     ٚ            _&     ٚ            l&     ٚ            w&     ٚ            &      ښ            &     8ښ            &     Pښ            &     hښ            &     ښ            &     ښ            &     ښ            &     ښ            3&     ښ            &     ښ            &     ۚ            &     (ۚ            &     @ۚ            &     Xۚ            &     pۚ            3&     ۚ            J&     ۚ            T'     ۚ            &     ۚ            >'     ۚ            C&      ܚ            &     ܚ            &     0ܚ            '     Hܚ            J'     `ܚ            &     xܚ            &     ܚ            &     ܚ            &     ܚ            '     ܚ            &     ܚ            &     ݚ            V&      ݚ            &     8ݚ            &     Pݚ            59'     hݚ            
&     ݚ            &     ݚ            &     ݚ            &     ݚ            &     ݚ             U'     ݚ            &     ޚ            &     (ޚ            *&     @ޚ            &     Xޚ            /&     pޚ            >'     ޚ            7&     ޚ            ?&     ޚ            &     ߚ            y&     @ߚ            &     `ߚ            `     ߚ            J&     ߚ                  ߚ            V&     ߚ                              [&                                   l     (                 P            Yd&     p            KB'                 VB'                 Y&                 }&                 &                 &                  Yq&                 &                 &     @            R'     H            O'     P            5&     X            &                 &                 &                 ǆ&                 ӆ&                 u&                 &                 G~&                 &                  &                 '&                 1&                 >&                 M&                 X&                 e&                 &                  &                 &                 j&                 w&                  %&     (            &     0            &     8            &     @            &     H            O'     P            &     X            O'     `            O'     p            T'     x            T'                 O'                 la&                 l:'                                    O'     (            .&     8            hx(     @            &     H            -&     X            O'     `            O'     h            ,&     x            x(                 O'                 @+&                 x(                 O'                 &&                 O'                 R'                 p&     8            2&     H                 h            2&                 @"                                  &                  &                 @/&                 R'                 &                 py(                  O'                  %&                 y(                  R'     (            7&     8            y(     @            e&     H            `0&     X            y(     `            \&     h            /&     x            R'                 &                 &                 R'                 r&                 p&                 z(                 R'                 $&                 0z(                 f&                 &                 Xz(                  R'                 !&                 S'                  &     (            &     8            z(     @            t~&     H            &     X            z(     `            m~&     h            P&     x            z(                 S'                 p&                  &     (             &     P            "                                  @                 P&     @            S'     `            (S'     h            &                 8S'                 ~&                 HS'                 &                 XS'                 ӆ&                  jS'                 u&     (            S'     0            &     P            S'     X            O'     x            S'                 \&                  &                  {(                 R'                  &                 0{(                  O'                 &                 X{(                  F&     (             &     8            S'     x            S'                 P4&                 "     P            `     X                               S'                 P
&                 @&                 S'     `            ^&                 S'                 T'                 	T'                 '                  T'                 &                 7T'                  NT'                  ST'     x            gT'                 4&                 {(     8            &     @            1&                 &                 uT'     0            &     X             &                  &                 "                                  &                 0&&                 {(                 }&                  &                 {(                 ~T'     0            &     h                             #     (            &                 p&                 1&                 T'     0            &     h                             0#     (            
&                 P&                 @2&                 T'     X            @&                 @#                                  T'                 T'                 T'                 T'                 T'                 T'                 T'     8            T'     @            U'     `            U'     h            %U'                 /U'                 8U'                 IU'                 ӆ&                 YU'                 fU'                  qU'                 &     (            {U'     0            U'     P            U'     X            U'     x            U'                 U'                 &     P            p&     p            p#                 `     `            T'                 T'                 T'                 T'                 T'                 T'                 T'                 T'                  U'                  U'     (            %U'     H            /U'     P            8U'     p            IU'     x            ӆ&                 YU'                 fU'                 qU'                 &                 {U'     8            U'     x            `&                 #                                  T'                 T'                 T'                 T'                 T'     0            T'     8            T'     X            T'     `            U'                 U'                 %U'                 /U'                 8U'                 IU'                 ӆ&                 YU'                   fU'                   qU'     (             T'     H             T'     P             T'     p             T'                  U'                  @&     P            #                 @     @            T'     `            T'     h            T'                 T'                 T'                 T'                 T'                 T'                 U'                  U'                 %U'     (            /U'     0            8U'     P            IU'     X            ӆ&     x            YU'                 fU'                 qU'                 &                 /U'                 NT'                 U'     8            V'     x            &                 #                                  T'                 T'                 T'                 T'                 T'     0            T'     8            T'     X            T'     `            U'                 U'                 %U'                 /U'                 8U'                 IU'                 ӆ&                 YU'                  fU'                  qU'     (            &     H            {U'     P            59'     p            '     x            &                 /U'                 ?U'                 IU'                 V'     X            &                 #                 	     	            T'     	            T'     	            T'     	            T'     	            T'     
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            YU'     
            fU'                  qU'                 &     (            {U'     0            T'     P            T'     X            T'     x            T'                 &                 *V'                 7V'     8             &                  $                                  T'                 T'                 T'                 T'                 T'                 T'                 T'                 T'                  U'     @            U'     H            %U'     h            /U'     p            8U'                 IU'                 ӆ&                 YU'                 fU'                 qU'                 &                 {U'                 T'     0            T'     8            MV'     X            GV'     `            T'                 T'                 XV'                 RV'                 59'                 '                 ]V'     X            &                 P$                                  T'                 T'                 T'                 T'                 T'                 T'                 T'     8            T'     @            U'     `            U'     h            %U'                 /U'                 8U'                 IU'                 ӆ&                 YU'                 fU'                  qU'                 &     (            {U'     0            sV'     P            mV'     X            T'     x            T'                 T'                 T'                 L&                 xV'                 O'                 V'                 >'                 V'                  V'     @            V'             E
                  E
          p        E
                                                                                          6                  6                  6                  u                  u          (        u          8        u          H        u          X        u          h        u          x        u                  u                  u                  u                  u                  u                  u                  u                  u                  u          8        u          H        u          X        u          h        u                  u                  u                  u                  u                  u                  u                  u          (        u          8        u          H        u          X        u          h        u          x        u                  u                  u                  u                  u                  u                  u                  u                  u                  u          (        u          8        u          H        u          h        u          x        u                  u                  u                  u                  u                  u                  u                  u                  u                  u                  u          (        u          8        u          H        u          X        u          h        u          x        u                  u                  u                  u                  u                  u                            H                  (        s          x        s                                                                                                                                                                                              (                  8                  H                  X                  h                  x                                                                                                                                                                                                      (                  8                  H                  X                  h                  x                                                                        
                          
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          8        f          x        f                  f                  f          8        f          x        f                  X                   X          `        X                  O          (        O          h        O                  Q                  R                  S                                                      3                  3                  6                  6                  7                  7                                                                                                                                                                                                      	                  	                  	                  	                  	                  	                                                                                                                                                                              (                  0                  8                  @                  P                  X                          B                   C                   E          @        J          `        O                  R                                                                        k	                                                @                  P        
          `                  h                                                                                                                                                                   `                  h        
          p        
                                                                        d                  	                  	                   	                   ;	          @        >	                                                                                           y                  y          0        y                                      {          @        {                  v           	        F          ՚        F          	                  ۚ                  	        x          	        W           	                  (	                  hܚ                  0	        q          8	        	
          @	        5
          H	                  P	                  h֚                  ֚                 ֚                 ֚                ֚          @      ך                (ך          `      Hך                hך                ך                ך                ך          0      ך                ؚ          0      (ؚ                Hؚ                hؚ          P      ؚ                ؚ          p      ؚ           	      ؚ          	      X	        6           `	                  h	                  p	        	          Xښ        	          x	        ?           	                  ܚ                  	        G          ۚ        G          	                  ՚                  	                  	        
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          8'        G          @'                   H'                   P'                   X'                  `'                   h'        	          p'                  x'                  '                   '                  '        
          '                  '                  '        .          '        <          '        	          '        (          '        N          '                  '        o          '        _          '        
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          )                    *                  *                  *        c          *        w	           *        
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          P0                  X0                  `0                  h0        w          p0        -          x0                  0                  0                  0        Z          0                  0        c
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          0                   0                   0        
          0                  0                   0        O          0                  0        u           1        =	          1        F          1        t          1                   1                  (1                  01        d
          81        	          @1                  H1                   P1                   X1                  `1                  h1                  p1                   x1        b          1                  1        
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          (2                  02                  82                  @2                   H2                   P2                  X2                  `2        
          h2                  p2        
          x2        N          2                  2                  2                  2                  2        G	          2                   2                  2                  2                  2                   2                  2                  2                  2        B          2                  2        
           3                  3                  3                  3        ;           3                  (3        5          03                  83         
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           4                  4                  4        G          4        ;           4                  (4        Q          04                  84                  @4                  H4                  P4                  X4        n          `4        }          h4                  p4                  x4                  4                  4                  4        P          4        7          4                  4                  4                  4                  4        y          4        	          4        	          4                  4                  4                  4        
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          =                   =        \          (=                  0=        k          8=                  @=                  H=        ]          P=                  X=                  `=        3          h=        	          p=                  x=        ^          =        _          =                  =        l          =        	          =        
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          =        b          =        K          =                  =        c          =        d          =                  =        e           >        t          >        W          >                  >                   >        R          (>        	          0>                  8>                  @>                  H>                  P>        o          X>        f          `>                  h>        m          p>                  x>        !          >                  >                  >        g          >        +          >        8
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          E                  E        k
          E                  E                  E                  E                  E                  E        -          E        L
          E        H          E                  E                   F                  F                  F        +	          F                   F                  (F                  0F                  8F                  @F        v          HF        |
          PF        
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          xF        d          F        /          F                  F        l          F                  F                  F        M          F        J          F                  F        s	          F        	          F                  F                  F        e	          F                  F                  F                   G                  G        >          G                  G                   G                  (G                  0G        	          8G                  @G                  HG        c	          PG                  XG                  `G                  hG        K
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          xH                  H        {          H        V          H                  H        
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          M                  M                  M                  M                  M                  M        E	          M        |          M                  M                  M                  M        8          M                   N                  N        8          N        J          N                   N                  (N                  0N        h          8N        p	          @N                  HN                  PN                  XN                  `N                  hN        
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          O        	          O                   P        @          P                  P                  P                   P                  (P        ?          0P                  8P                  @P        
          HP        =          PP        4          XP        2          `P                  hP        h          pP        =          xP        /	          P                  P                  P                  P                  P        2          P        9	          P                  P        d          P                  P                  P                  P                  P        y          P                  P                  P                   Q                  Q        z          Q                  Q        
           Q                  (Q        $          0Q                  8Q                  @Q        #          HQ        x          PQ                  XQ                  `Q                  hQ                  pQ        1          xQ                  Q        Q          Q                  Q                  Q        _          Q                  Q        #          Q        	          Q                  Q                  Q        O          Q                  Q                  Q                  Q        	          Q        l          Q                   R        E          R        F          R                  R                   R                  (R        	          0R                  8R                  @R        
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          PR        -          XR        <          `R                  hR                  pR                  xR        r          R                  R                  R                  R        (          R                  R                  R        Y          R                  R                  R                  R                  R                  R        
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          (W                  0W                  8W                  @W        
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          X        .          X        H          X        v
          X                  X                  X        h          X        !          X        >           Y        "          Y        #          Y        i          Y                   Y        
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          pZ                  xZ                  Z                  Z        w          Z        	          Z                  Z        	          Z        g          Z        ,          Z                  Z                  Z        	          Z        }          Z                  Z        #          Z        U          Z                  Z        }           [                  [        U          [                  [        -           [        .          ([        -
          0[                  8[        /          @[        0          H[                  P[        s          X[                  `[        T	          h[        Z          p[        1          x[        2          [                  [                  [                  [                  [        x	          [        +          [                  [        3          [        ~          [        4          [                  [                  [                  [                  [        5          [                   \        
          \        6          \                  \        e           \        [          (\        7          0\        o	          8\                  @\        8          H\                  P\        !          X\        L          `\                  h\        9          p\                  x\        '          \        :          \                  \                  \        ;          \                  \        <          \        =          \                  \        (          \        >          \        
          \        )          \        ?          \                  \        '	          \                   ]        L          ]        @          ]        A          ]        B           ]        )          (]        g          0]                  8]        C          @]                  H]                  P]        D          X]                  `]                  h]        E          p]                  x]                  ]        Y          ]        F          ]        u          ]        G          ]        
          ]        H          ]        I          ]                  ]        2          ]        z          ]                  ]                  ]        g
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          ha        _          pa                  xa        2          a                  a        V          a                  a                  a        ]	          a        F          a        	          a                  a                   a                  a        `          a                  a                  a                  a        ;          a                   b        a          b                   b        b          b                   b                  (b        -          0b                  8b        ^          @b        c          Hb        	          Pb        d          Xb                  `b        e          hb                  pb        B          xb        ?          b        \          b        k          b                  b                  b        P          b                  b                  b                  b        
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          c                  c                  c                   d                  d        l          d        k          d                   d        
          (d        t          0d        l          8d        4
          @d        m          Hd        j          Pd                  Xd        
          `d                  hd        n          pd                  xd                  d        h          d        
          d        M          d        R          d                  d        	          d                  d                  d        o          d                  d        
          d                  d                  d        ,          d        (          d                   e        p          e                  e        q          e        8           e                  (e        [          0e                  8e        r          @e        s          He                  Pe                  Xe                  `e        t          he        (          pe                  xe                  e                  e        	          e                  e        
          e        u          e        v          e                  e                  e                  e        [          e                  e        U          e        $          e        w          e        x          e                   f        f          f                  f                  f                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  HHZ HtH     5_ %_ @ h    fh   fh   fh   fh   fh   fh   fh   rfh   bfh	   Rfh
   Bfh   2fh   "fh   fh   fh   fh   fh   fh   fh   fh   fh   fh   fh   rfh   bfh   Rfh   Bfh   2fh   "fh   fh   fh   fh    fh!   fh"   fh#   fh$   fh%   fh&   fh'   rfh(   bfh)   Rfh*   Bfh+   2fh,   "fh-   fh.   fh/   fh0   fh1   fh2   fh3   fh4   fh5   fh6   fh7   rfh8   bfh9   Rfh:   Bfh;   2fh<   "fh=   fh>   fh?   fh@   fhA   fhB   fhC   fhD   fhE   fhF   fhG   rfhH   bfhI   RfhJ   BfhK   2fhL   "fhM   fhN   fhO   fhP   fhQ   fhR   fhS   fhT   fhU   fhV   fhW   rfhX   bfhY   RfhZ   Bfh[   2fh\   "fh]   fh^   fh_   fh`   fha   fhb   fhc   fhd   fhe   fhf   fhg   rfhh   bfhi   Rfhj   Bfhk   2fhl   "fhm   fhn   fho   fhp   fhq   fhr   fhs   fht   fhu   fhv   fhw   rfhx   bfhy   Rfhz   Bfh{   2fh|   "fh}   fh~   fh   fh   fh   fh   fh   fh   fh   fh   fh   rfh   bfh   Rfh   Bfh   2fh   "fh   fh   fh   fh   fh   fh   fh   fh   fh   fh   fh   rfh   bfh   Rfh   Bfh   2fh   "fh   fh   fh   fh   fh   fh   fh   fh   fh   fh   fh   rfh   bfh   Rfh   Bfh   2fh   "fh   fh   fh   fh   fh   fh   fh   fh   fh   fh   fh   rfh   bfh   Rfh   Bfh   2fh   "fh   fh   fh   fh   fh   fh   fh   fh   fh   fh   fh   rfh   bfh   Rfh   Bfh   2fh   "fh   fh   fh   fh   fh   fh   fh   fh   fh   fh   fh   rfh   bfh   Rfh   Bfh   2fh   "fh   fh   fh   fh   fh   fh   fh   fh   fh   fh   fh   rfh   bfh   Rfh   Bfh   2fh   "fh   fh   fh   fh   fh   fh   fh   fh   fh   fh   fh   rfh   bfh   Rfh   Bfh   2fh   "fh   fh   fh   fh   fh  fh  fh  fh  fh  fh  fh  rfh  bfh	  Rfh
  Bfh  2fh  "fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh   fh!  fh"  fh#  fh$  fh%  fh&  fh'  rfh(  bfh)  Rfh*  Bfh+  2fh,  "fh-  fh.  fh/  fh0  fh1  fh2  fh3  fh4  fh5  fh6  fh7  rfh8  bfh9  Rfh:  Bfh;  2fh<  "fh=  fh>  fh?  fh@  fhA  fhB  fhC  fhD  fhE  fhF  fhG  rfhH  bfhI  RfhJ  BfhK  2fhL  "fhM  fhN  fhO  fhP  fhQ  fhR  fhS  fhT  fhU  fhV  fhW  rfhX  bfhY  RfhZ  Bfh[  2fh\  "fh]  fh^  fh_  fh`  fha  fhb  fhc  fhd  fhe  fhf  fhg  rfhh  bfhi  Rfhj  Bfhk  2fhl  "fhm  fhn  fho  fhp  fhq  fhr  fhs  fht  fhu  fhv  fhw  rfhx  bfhy  Rfhz  Bfh{  2fh|  "fh}  fh~  fh  fh  fh  fh  fh  fh  fh  fh  fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh   fh  fh  fh  fh  fh  fh  fh  rfh  bfh	  Rfh
  Bfh  2fh  "fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh   fh!  fh"  fh#  fh$  fh%  fh&  fh'  rfh(  bfh)  Rfh*  Bfh+  2fh,  "fh-  fh.  fh/  fh0  fh1  fh2  fh3  fh4  fh5  fh6  fh7  rfh8  bfh9  Rfh:  Bfh;  2fh<  "fh=  fh>  fh?  fh@  fhA  fhB  fhC  fhD  fhE  fhF  fhG  rfhH  bfhI  RfhJ  BfhK  2fhL  "fhM  fhN  fhO  fhP  fhQ  fhR  fhS  fhT  fhU  fhV  fhW  rfhX  bfhY  RfhZ  Bfh[  2fh\  "fh]  fh^  fh_  fh`  fha  fhb  fhc  fhd  fhe  fhf  fhg  rfhh  bfhi  Rfhj  Bfhk  2fhl  "fhm  fhn  fho  fhp  fhq  fhr  fhs  fht  fhu  fhv  fhw  rfhx  bfhy  Rfhz  Bfh{  2fh|  "fh}  fh~  fh  fh  fh  fh  fh  fh  fh  fh  fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh   fh  fh  fh  fh  fh  fh  fh  rfh  bfh	  Rfh
  Bfh  2fh  "fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh   fh!  fh"  fh#  fh$  fh%  fh&  fh'  rfh(  bfh)  Rfh*  Bfh+  2fh,  "fh-  fh.  fh/  fh0  fh1  fh2  fh3  fh4  fh5  fh6  fh7  rfh8  bfh9  Rfh:  Bfh;  2fh<  "fh=  fh>  fh?  fh@  fhA  fhB  fhC  fhD  fhE  fhF  fhG  rfhH  bfhI  RfhJ  BfhK  2fhL  "fhM  fhN  fhO  fhP  fhQ  fhR  fhS  fhT  fhU  fhV  fhW  rfhX  bfhY  RfhZ  Bfh[  2fh\  "fh]  fh^  fh_  fh`  fha  fhb  fhc  fhd  fhe  fhf  fhg  rfhh  bfhi  Rfhj  Bfhk  2fhl  "fhm  fhn  fho  fhp  fhq  fhr  fhs  fht  fhu  fhv  fhw  rfhx  bfhy  Rfhz  Bfh{  2fh|  "fh}  fh~  fh  fh  fh  fh  fh  fh  fh  fh  fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh   fh  ҿfh  ¿fh  鲿fh  颿fh  钿fh  邿fh  rfh  bfh	  Rfh
  Bfh  2fh  "fh  fh  fh  fh  fh  Ҿfh  ¾fh  鲾fh  颾fh  钾fh  邾fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh   fh!  ҽfh"  ½fh#  鲽fh$  颽fh%  钽fh&  邽fh'  rfh(  bfh)  Rfh*  Bfh+  2fh,  "fh-  fh.  fh/  fh0  fh1  Ҽfh2  ¼fh3  鲼fh4  颼fh5  钼fh6  邼fh7  rfh8  bfh9  Rfh:  Bfh;  2fh<  "fh=  fh>  fh?  fh@  fhA  һfhB  »fhC  鲻fhD  颻fhE  钻fhF  邻fhG  rfhH  bfhI  RfhJ  BfhK  2fhL  "fhM  fhN  fhO  fhP  fhQ  ҺfhR  ºfhS  鲺fhT  颺fhU  钺fhV  邺fhW  rfhX  bfhY  RfhZ  Bfh[  2fh\  "fh]  fh^  fh_  fh`  fha  ҹfhb  ¹fhc  鲹fhd  颹fhe  钹fhf  邹fhg  rfhh  bfhi  Rfhj  Bfhk  2fhl  "fhm  fhn  fho  fhp  fhq  Ҹfhr  ¸fhs  鲸fht  颸fhu  钸fhv  邸fhw  rfhx  bfhy  Rfhz  Bfh{  2fh|  "fh}  fh~  fh  fh  fh  ҷfh  ·fh  鲷fh  颷fh  钷fh  邷fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  Ҷfh  ¶fh  鲶fh  颶fh  钶fh  邶fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  ҵfh  µfh  鲵fh  颵fh  钵fh  邵fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  Ҵfh  ´fh  鲴fh  颴fh  钴fh  邴fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  ҳfh  ³fh  鲳fh  颳fh  钳fh  邳fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  Ҳfh  ²fh  鲲fh  颲fh  钲fh  邲fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  ұfh  ±fh  鲱fh  颱fh  钱fh  邱fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  Ұfh  °fh  鲰fh  颰fh  钰fh  邰fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh   fh  үfh  ¯fh  鲯fh  颯fh  钯fh  邯fh  rfh  bfh	  Rfh
  Bfh  2fh  "fh  fh  fh  fh  fh  Үfh  ®fh  鲮fh  颮fh  钮fh  邮fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh   fh!  ҭfh"  ­fh#  鲭fh$  颭fh%  钭fh&  邭fh'  rfh(  bfh)  Rfh*  Bfh+  2fh,  "fh-  fh.  fh/  fh0  fh1  Ҭfh2  ¬fh3  鲬fh4  颬fh5  钬fh6  邬fh7  rfh8  bfh9  Rfh:  Bfh;  2fh<  "fh=  fh>  fh?  fh@  fhA  ҫfhB  «fhC  鲫fhD  颫fhE  钫fhF  邫fhG  rfhH  bfhI  RfhJ  BfhK  2fhL  "fhM  fhN  fhO  fhP  fhQ  ҪfhR  ªfhS  鲪fhT  颪fhU  钪fhV  邪fhW  rfhX  bfhY  RfhZ  Bfh[  2fh\  "fh]  fh^  fh_  fh`  fha  ҩfhb  ©fhc  鲩fhd  颩fhe  钩fhf  邩fhg  rfhh  bfhi  Rfhj  Bfhk  2fhl  "fhm  fhn  fho  fhp  fhq  Ҩfhr  ¨fhs  鲨fht  風fhu  钨fhv  邨fhw  rfhx  bfhy  Rfhz  Bfh{  2fh|  "fh}  fh~  fh  fh  fh  ҧfh  §fh  鲧fh  颧fh  钧fh  邧fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  Ҧfh  ¦fh  鲦fh  颦fh  钦fh  邦fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  ҥfh  ¥fh  鲥fh  颥fh  钥fh  邥fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  Ҥfh  ¤fh  鲤fh  颤fh  钤fh  邤fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  ңfh  £fh  鲣fh  颣fh  钣fh  那fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  Ңfh  ¢fh  鲢fh  颢fh  钢fh  邢fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  ҡfh  ¡fh  鲡fh  颡fh  钡fh  邡fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  Ҡfh   fh  鲠fh  颠fh  钠fh  邠fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh   fh  ҟfh  fh  鲟fh  颟fh  钟fh  邟fh  rfh  bfh	  Rfh
  Bfh  2fh  "fh  fh  fh  fh  fh  Ҟfh  fh  鲞fh  颞fh  钞fh  邞fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh   fh!  ҝfh"  fh#  鲝fh$  额fh%  钝fh&  邝fh'  rfh(  bfh)  Rfh*  Bfh+  2fh,  "fh-  fh.  fh/  fh0  fh1  Ҝfh2  fh3  鲜fh4  颜fh5  钜fh6  邜fh7  rfh8  bfh9  Rfh:  Bfh;  2fh<  "fh=  fh>  fh?  fh@  fhA  қfhB  fhC  鲛fhD  颛fhE  钛fhF  邛fhG  rfhH  bfhI  RfhJ  BfhK  2fhL  "fhM  fhN  fhO  fhP  fhQ  ҚfhR  fhS  鲚fhT  颚fhU  钚fhV  邚fhW  rfhX  bfhY  RfhZ  Bfh[  2fh\  "fh]  fh^  fh_  fh`  fha  ҙfhb  fhc  鲙fhd  颙fhe  钙fhf  邙fhg  rfhh  bfhi  Rfhj  Bfhk  2fhl  "fhm  fhn  fho  fhp  fhq  Ҙfhr  fhs  鲘fht  题fhu  钘fhv  邘fhw  rfhx  bfhy  Rfhz  Bfh{  2fh|  "fh}  fh~  fh  fh  fh  җfh  fh  鲗fh  颗fh  钗fh  邗fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  Җfh  fh  鲖fh  颖fh  钖fh  邖fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  ҕfh  fh  鲕fh  颕fh  钕fh  邕fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  Ҕfh  fh  鲔fh  颔fh  钔fh  邔fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  ғfh  fh  鲓fh  颓fh  钓fh  邓fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  Ғfh  fh  鲒fh  颒fh  钒fh  邒fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  ґfh  fh  鲑fh  频fh  钑fh  邑fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  Ґfh  fh  鲐fh  颐fh  钐fh  邐fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh   fh  ҏfh  fh  鲏fh  颏fh  钏fh  邏fh  rfh  bfh	  Rfh
  Bfh  2fh  "fh  fh  fh  fh  fh  Ҏfh  fh  鲎fh  颎fh  钎fh  邎fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh   fh!  ҍfh"  fh#  鲍fh$  颍fh%  钍fh&  邍fh'  rfh(  bfh)  Rfh*  Bfh+  2fh,  "fh-  fh.  fh/  fh0  fh1  Ҍfh2  fh3  鲌fh4  颌fh5  钌fh6  邌fh7  rfh8  bfh9  Rfh:  Bfh;  2fh<  "fh=  fh>  fh?  fh@  fhA  ҋfhB  fhC  鲋fhD  颋fhE  钋fhF  邋fhG  rfhH  bfhI  RfhJ  BfhK  2fhL  "fhM  fhN  fhO  fhP  fhQ  ҊfhR  fhS  鲊fhT  颊fhU  钊fhV  邊fhW  rfhX  bfhY  RfhZ  Bfh[  2fh\  "fh]  fh^  fh_  fh`  fha  ҉fhb  fhc  鲉fhd  颉fhe  钉fhf  邉fhg  rfhh  bfhi  Rfhj  Bfhk  2fhl  "fhm  fhn  fho  fhp  fhq  ҈fhr  fhs  鲈fht  颈fhu  针fhv  邈fhw  rfhx  bfhy  Rfhz  Bfh{  2fh|  "fh}  fh~  fh  fh  fh  ҇fh  fh  鲇fh  颇fh  钇fh  邇fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  ҆fh  fh  鲆fh  领fh  钆fh  邆fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  ҅fh  fh  鲅fh  颅fh  钅fh  邅fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  ҄fh  fh  鲄fh  预fh  钄fh  還fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  ҃fh  fh  鲃fh  颃fh  钃fh  邃fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  ҂fh  fh  鲂fh  颂fh  钂fh  邂fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  ҁfh  fh  鲁fh  颁fh  钁fh  邁fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh  fh  Ҁfh  fh  鲀fh  颀fh  钀fh  邀fh  rfh  bfh  Rfh  Bfh  2fh  "fh  fh  fh  fh   fh  fh  fh  fh  fh  fh  fh  rfh  bfh	  Rfh
  Bfh  2fh  "fh  fh  fh  ~fh  ~fh  ~fh  ~fh  ~fh  ~fh  ~fh  ~fh  r~fh  b~fh  R~fh  B~fh  2~fh  "~fh  ~fh  ~fh  }fh   }fh!  }fh"  }fh#  }fh$  }fh%  }fh&  }fh'  r}fh(  b}fh)  R}fh*  B}fh+  2}fh,  "}fh-  }fh.  }fh/  |fh0  |fh1  |fh2  |fh3  |fh4  |fh5  |fh6  |fh7  r|fh8  b|fh9  R|fh:  B|fh;  2|fh<  "|fh=  |fh>  |fh?  {fh@  {fhA  {fhB  {fhC  {fhD  {fhE  {fhF  {fhG  r{fhH  b{fhI  R{fhJ  B{fhK  2{fhL  "{fhM  {fhN  {fhO  zfhP  zfhQ  zfhR  zfhS  zfhT  zfhU  zfhV  zfhW  rzfhX  bzfhY  RzfhZ  Bzfh[  2zfh\  "zfh]  zfh^  zfh_  yfh`  yfha  yfhb  yfhc  yfhd  yfhe  yfhf  yfhg  ryfhh  byfhi  Ryfhj  Byfhk  2yfhl  "yfhm  yfhn  yfho  xfhp  xfhq  xfhr  xfhs  xfht  xfhu  xfhv  xfhw  rxfhx  bxfhy  Rxfhz  Bxfh{  2xfh|  "xfh}  xfh~  xfh  wfh  wfh  wfh  wfh  wfh  wfh  wfh  wfh  rwfh  bwfh  Rwfh  Bwfh  2wfh  "wfh  wfh  wfh  vfh  vfh  vfh  vfh  vfh  vfh  vfh  vfh  rvfh  bvfh  Rvfh  Bvfh  2vfh  "vfh  vfh  vfh  ufh  ufh  ufh  ufh  ufh  ufh  ufh  ufh  rufh  bufh  Rufh  Bufh  2ufh  "ufh  ufh  ufh  tfh  tfh  tfh  tfh  tfh  tfh  tfh  tfh  rtfh  btfh  Rtfh  Btfh  2tfh  "tfh  tfh  tfh  sfh  sfh  sfh  sfh  sfh  sfh  sfh  sfh  rsfh  bsfh  Rsfh  Bsfh  2sfh  "sfh  sfh  sfh  rfh  rfh  rfh  rfh  rfh  rfh  rfh  rfh  rrfh  brfh  Rrfh  Brfh  2rfh  "rfh  rfh  rfh  qfh  qfh  qfh  qfh  qfh  qfh  qfh  qfh  rqfh  bqfh  Rqfh  Bqfh  2qfh  "qfh  qfh  qfh  pfh  pfh  pfh  pfh  pfh  pfh  pfh  pfh  rpfh  bpfh  Rpfh  Bpfh  2pfh  "pfh  pfh  pfh  ofh 	  ofh	  ofh	  ofh	  ofh	  ofh	  ofh	  ofh	  rofh	  bofh		  Rofh
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  2Tfh
  "Tfh
  Tfh
  Tfh
  Sfh
  Sfh
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  Sfh
  Sf%Ƭ fD  %V fD  %^ fD  %ƭ fD  %v fD  % fD  %6 fD  %^ fD  %. fD  % fD  %沒 fD  %޲ fD  %ֲ fD  %β fD  %Ʋ fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %~ fD  %v fD  %n fD  %f fD  %^ fD  %V fD  %N fD  %F fD  %> fD  %6 fD  %. fD  %& fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %汒 fD  %ޱ fD  %ֱ fD  %α fD  %Ʊ fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %~ fD  %v fD  %n fD  %f fD  %^ fD  %V fD  %N fD  %F fD  %> fD  %6 fD  %. fD  %& fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %氒 fD  %ް fD  %ְ fD  %ΰ fD  %ư fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %~ fD  %v fD  %n fD  %f fD  %^ fD  %V fD  %N fD  %F fD  %> fD  %6 fD  %. fD  %& fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %毒 fD  %ޯ fD  %֯ fD  %ί fD  %Ư fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %~ fD  %v fD  %n fD  %f fD  %^ fD  %V fD  %N fD  %F fD  %> fD  %6 fD  %. fD  %& fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %殒 fD  %ޮ fD  %֮ fD  %ή fD  %Ʈ fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %~ fD  %v fD  %n fD  %f fD  %^ fD  %V fD  %N fD  %F fD  %> fD  %6 fD  %. fD  %& fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %歒 fD  %ޭ fD  %֭ fD  %έ fD  %ƭ fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %~ fD  %v fD  %n fD  %f fD  %^ fD  %V fD  %N fD  %F fD  %> fD  %6 fD  %. fD  %& fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %欒 fD  %ެ fD  %֬ fD  %ά fD  %Ƭ fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %~ fD  %v fD  %n fD  %f fD  %^ fD  %V fD  %N fD  %F fD  %> fD  %6 fD  %. fD  %& fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %櫒 fD  %ޫ fD  %֫ fD  %Ϋ fD  %ƫ fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %~ fD  %v fD  %n fD  %f fD  %^ fD  %V fD  %N fD  %F fD  %> fD  %6 fD  %. fD  %& fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %檒 fD  %ު fD  %֪ fD  %Ϊ fD  %ƪ fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %~ fD  %v fD  %n fD  %f fD  %^ fD  %V fD  %N fD  %F fD  %> fD  %6 fD  %. fD  %& fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %橒 fD  %ީ fD  %֩ fD  %Ω fD  %Ʃ fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %~ fD  %v fD  %n fD  %f fD  %^ fD  %V fD  %N fD  %F fD  %> fD  %6 fD  %. fD  %& fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %樒 fD  %ި fD  %֨ fD  %Ψ fD  %ƨ fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %~ fD  %v fD  %n fD  %f fD  %^ fD  %V fD  %N fD  %F fD  %> fD  %6 fD  %. fD  %& fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %槒 fD  %ާ fD  %֧ fD  %Χ fD  %Ƨ fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %~ fD  %v fD  %n fD  %f fD  %^ fD  %V fD  %N fD  %F fD  %> fD  %6 fD  %. fD  %& fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %榒 fD  %ަ fD  %֦ fD  %Φ fD  %Ʀ fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %~ fD  %v fD  %n fD  %f fD  %^ fD  %V fD  %N fD  %F fD  %> fD  %6 fD  %. fD  %& fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %楒 fD  %ޥ fD  %֥ fD  %Υ fD  %ƥ fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %~ fD  %v fD  %n fD  %f fD  %^ fD  %V fD  %N fD  %F fD  %> fD  %6 fD  %. fD  %& fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %椒 fD  %ޤ fD  %֤ fD  %Τ fD  %Ƥ fD  % fD  % fD  % fD  % fD  % f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% fD  % fD  % fD  %敒 fD  %ޕ fD  %֕ fD  %Ε fD  %ƕ fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %~ fD  %v fD  %n fD  %f fD  %^ fD  %V fD  %N fD  %F fD  %> fD  %6 fD  %. fD  %& fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %攒 fD  %ޔ fD  %֔ fD  %Δ fD  %Ɣ fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %~ fD  %v fD  %n fD  %f fD  %^ fD  %V fD  %N fD  %F fD  %> fD  %6 fD  %. fD  %& fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %擒 fD  %ޓ fD  %֓ fD  %Γ fD  %Ɠ fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %~ fD  %v fD  %n fD  %f fD  %^ fD  %V fD  %N fD  %F fD  %> fD  %6 fD  %. fD  %& fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %撒 fD  %ޒ fD  %֒ fD  %Β fD  %ƒ fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %~ fD  %v fD  %n fD  %f fD  %^ fD  %V fD  %N fD  %F fD  %> fD  %6 fD  %. fD  %& fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %摒 fD  %ޑ fD  %֑ fD  %Α fD  %Ƒ fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %~ fD  %v fD  %n fD  %f fD  %^ fD  %V fD  %N fD  %F fD  %> fD  %6 fD  %. fD  %& fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %搒 fD  %ސ fD  %֐ fD  %ΐ fD  %Ɛ fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %~ fD  %v fD  %n fD  %f fD  %^ fD  %V fD  %N fD  %F fD  %> fD  %6 fD  %. fD  %& fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %插 fD  %ޏ fD  %֏ fD  %Ώ fD  %Ə fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %~ fD  %v fD  %n fD  %f fD  %^ fD  %V fD  %N fD  %F fD  %> fD  %6 fD  %. fD  %& fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %排 fD  %ގ fD  %֎ fD  %Ύ fD  %Ǝ fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %~ fD  %v fD  %n fD  %f fD  %^ fD  %V fD  %N fD  %F fD  %> fD  %6 fD  %. fD  %& fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %捒 fD  %ލ fD  %֍ fD  %΍ fD  %ƍ fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %~ fD  %v fD  %n fD  %f fD  %^ fD  %V fD  %N fD  %F fD  %> fD  %6 fD  %. fD  %& fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %挒 fD  %ތ fD  %֌ fD  %Ό fD  %ƌ fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %~ fD  %v fD  %n fD  %f fD  %^ fD  %V fD  %N fD  %F fD  %> fD  %6 fD  %. fD  %& fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %拒 fD  %ދ fD  %֋ fD  %΋ fD  %Ƌ fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %~ fD  %v fD  %n fD  %f fD  %^ fD  %V fD  %N fD  %F fD  %> fD  %6 fD  %. fD  %& fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %抒 fD  %ފ fD  %֊ fD  %Ί fD  %Ɗ fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %~ fD  %v fD  %n fD  %f fD  %^ fD  %V fD  %N fD  %F fD  %> fD  %6 fD  %. fD  %& fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %扒 fD  %މ fD  %։ fD  %Ή fD  %Ɖ fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %~ fD  %v fD  %n fD  %f fD  %^ fD  %V fD  %N fD  %F fD  %> fD  %6 fD  %. fD  %& fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %戒 fD  %ވ fD  %ֈ fD  %Έ fD  %ƈ fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %~ fD  %v fD  %n fD  %f fD  %^ fD  %V fD  %N fD  %F fD  %> fD  %6 fD  %. fD  %& fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %懒 fD  %އ fD  %և fD  %· fD  %Ƈ fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  % fD  %~ fD  %v fD  %n fD  %f fD  %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D  %>y fD  %6y fD  %.y fD  %&y fD  %y fD  %y fD  %y fD  %y fD  %x fD  %x fD  %x fD  %x fD  %x fD  %x fD  %x fD  %x fD  %x fD  %x fD  %x fD  %x fD  %x fD  %x fD  %x fD  %x fD  %~x fD  %vx fD  %nx fD  %fx fD  %^x fD  %Vx fD  %Nx fD  %Fx fD  %>x fD  %6x fD  %.x fD  %&x fD  %x fD  %x fD  %x fD  %x fD  %w fD  %w fD  %w fD  %w fD  %w fD  %w fD  %w fD  %w fD  %w fD  %w fD  %w fD  %w fD  %w fD  %w fD  %w fD  %w fD  %~w fD  %vw fD  %nw fD  %fw fD  %^w fD  %Vw fD  %Nw fD  %Fw fD  %>w fD  %6w fD  %.w fD  %&w fD  %w fD  %w fD  %w fD  %w fD  %v fD  %v fD  %v fD  %v fD  %v fD  %v fD  %v fD  %v fD  %v fD  %v fD  %v fD  %v fD  %v fD  %v fD  %v fD  %v fD  %~v fD  %vv fD  %nv fD  %fv fD  %^v fD  %Vv fD  %Nv fD  %Fv fD  %>v fD  %6v fD  %.v fD  %&v fD  %v fD  %v fD  %v fD  %v fD  %u fD  %u fD  %u fD  %u fD  %u fD  %u fD  %u fD  %u fD  %u fD  %u fD  %u fD  %u fD  %u fD  %u fD  %u fD  %u fD  %~u fD  %vu fD  %nu fD  %fu fD  %^u fD  %Vu fD  %Nu fD  %Fu fD  %>u fD  %6u fD  %.u fD  %&u fD  %u fD  %u fD  %u fD  %u fD  %t fD  %t fD  %t fD  %t fD  %t fD  %t fD  %t fD  %t fD  %t fD  %t fD  %t fD  %t fD  %t fD  %t fD  %t fD  %t fD  %~t fD  %vt fD  %nt fD  %ft fD  %^t fD  %Vt fD  %Nt fD  %Ft fD  %>t fD  %6t fD  %.t fD  %&t fD  %t fD  %t fD  %t fD  %t fD  %s fD  %s fD  %s fD  %s fD  %s fD  %s fD  %s fD  %s fD  %s fD  %s fD  %s fD  %s fD  %s fD  %s fD  %s fD  %s fD  %~s fD  %vs fD  %ns fD  %fs fD  %^s fD  %Vs fD  %Ns fD  %Fs fD  %>s fD  %6s fD  %.s fD  %&s fD  %s fD  %s fD  %s fD  %s fD  %r fD  %r fD  %r fD  %r fD  %r fD  %r fD  %r fD  %r fD  %r fD  %r fD  %r fD  %r fD  %r fD  %r fD  %r fD  %r fD  %~r fD  %vr fD  %nr fD  %fr fD  %^r fD  %Vr fD  %Nr fD  %Fr fD  %>r fD  %6r fD  %.r fD  %&r fD  %r fD  %r fD  %r fD  %r fD  %q fD  %q fD  %q fD  %q fD  %q fD  %q fD  %q fD  %q fD  %q fD  %q fD  %q fD  %q fD  %q fD  %q fD  %q fD  %q fD  %~q fD  %vq fD  %nq fD  %fq fD  %^q fD  %Vq fD  %Nq fD  %Fq fD  %>q fD  %6q fD  %.q fD  %&q fD  %q fD  %q fD  %q fD  %q fD  %p fD  %p fD  %p fD  %p fD  %p fD  %p fD  %p fD  %p fD  %p fD  %p fD  %p fD  %p fD  %p fD  %p fD  %p fD  %p fD  %~p fD  %vp fD  %np fD  %fp fD  %^p fD  %Vp fD  %Np fD  %Fp fD  %>p fD  %6p fD  %.p fD  %&p fD  %p fD  %p fD  %p fD  %p fD  %o fD  %o fD  %o fD  %o fD  %o fD  %o fD  %o fD  %o fD  %o fD  %o fD  %o fD  %o fD  %o fD  %o fD  %o fD  %o fD  %~o fD  %vo fD  %no fD  %fo fD  %^o fD  %Vo fD  %No fD  %Fo fD  %>o fD  %6o fD  %.o fD  %&o fD  %o fD  %o fD  %o fD  %o fD  %n fD  %n fD  %n fD  %n fD  %n fD  %n fD  %n fD  %n fD  %n fD  %n fD  %n fD  %n fD  %n fD  %n fD  %n fD  %n fD  %~n fD  %vn fD  %nn fD  %fn fD  %^n fD  %Vn fD  %Nn fD  %Fn fD  %>n fD  %6n fD  %.n fD  %&n fD  %n fD  %n fD  %n fD  %n fD  %m fD  %m fD  %m fD  %m fD  %m fD  %m fD  %m fD  %m fD  %m fD  %m fD  %m fD  %m fD  %m fD  %m fD  %m fD  %m fD  %~m fD  %vm fD  %nm fD  %fm fD  %^m fD  %Vm fD  %Nm fD  %Fm fD  %>m fD  %6m fD  %.m fD  %&m fD  %m fD  %m fD  %m fD  %m fD  %l fD  %l fD  %l fD  %l fD  %l fD  %l fD  %l fD  %l fD  %l fD  %l fD  %l fD  %l fD  %l fD  %l fD  %l fD  %l fD  %~l fD  %vl fD  %nl fD  %fl fD  %^l fD  %Vl fD  %Nl fD  %Fl fD  %>l fD  %6l fD  %.l fD  %&l fD  %l fD  %l fD  %l fD  %l fD  %k fD  %k fD  %k fD  %k fD  %k fD  %k fD  %k fD  %k fD  %k fD  %k fD  %k fD  %k fD  %k fD  %k fD  %k fD  %k fD  %~k fD  %vk fD  %nk fD  %fk fD  %^k fD  %Vk fD  %Nk fD  %Fk fD  %>k fD  %6k fD  %.k fD  %&k fD  %k fD  %k fD  %k fD  %k fD  %j fD  %j fD  %j fD  %j fD  %j fD  %j fD  %j fD  %j fD  %j fD  %j fD  %j fD  %j fD  %j fD  %j fD  %j fD  %j fD  %~j fD  %vj fD  %nj fD  %fj fD  %^j fD  %Vj fD  %Nj fD  %Fj fD  %>j fD  %6j fD  %.j fD  %&j fD  %j fD  %j fD  %j fD  %j fD  %i fD  %i fD  %i fD  %i fD  %i fD  %i fD  %i fD  %i fD  %i fD  %i fD  %i fD  %i fD  %i fD  %i fD  %i fD  %i fD  %~i fD  %vi fD  %ni fD  %fi fD  %^i fD  %Vi fD  %Ni fD  %Fi fD  %>i fD  %6i fD  %.i fD  %&i fD  %i fD  %i fD  %i fD  %i fD  %h fD  %h fD  %h fD  %h fD  %h fD  %h fD  %h fD  %h fD  %h fD  %h fD  %h fD  %h fD  %h fD  %h fD  %h fD  %h fD  %~h fD  %vh fD  %nh fD  %fh fD  %^h fD  %Vh fD  %Nh fD  %Fh fD  %>h fD  %6h fD  %.h fD  %&h fD  %h fD  %h fD  %h fD  %h fD  %g fD  %g fD  %g fD  %g fD  %g fD  %g fD  %g fD  %g fD  %g fD  %g fD  %g fD  %g fD  %g fD  %g fD  %g fD  %g fD  %~g fD  %vg fD  %ng fD  %fg fD  %^g fD  %Vg fD  %Ng fD  %Fg fD  %>g fD  %6g fD  %.g fD  %&g fD  %g fD  %g fD  %g fD  %g fD  %f fD  %f fD  %f fD  %f fD  %f fD  %f fD  %f fD  %f fD  %f fD  %f fD  %f fD  %f fD  %f fD  %f fD  %f fD  %f fD  %~f fD  %vf fD  %nf fD  %ff fD  %^f fD  %Vf fD  %Nf fD  %Ff fD  %>f fD  %6f fD  %.f fD  %&f fD  %f fD  %f fD  %f fD  %f fD  %e fD  %e fD  %e fD  %e fD  %e fD  %e fD  %e fD  %e fD  %e fD  %e fD  %e fD  %e fD  %e fD  %e fD  %e fD  %e fD  %~e fD  %ve fD  %ne fD  %fe fD  %^e fD  %Ve fD  %Ne fD  %Fe fD  %>e fD  %6e fD  %.e fD  %&e fD  %e fD  %e fD  %e fD  %e fD  %d fD  %d fD  %d fD  %d fD  %d fD  %d fD  %d fD  %d fD  %d fD  %d fD  %d fD  %d fD  %d fD  %d fD  %d fD  %d fD  %~d fD  %vd fD  %nd fD  %fd fD  %^d fD  %Vd fD  %Nd fD  %Fd fD  %>d fD  %6d fD  %.d fD  %&d fD  %d fD  %d fD  %d fD  %d fD  %c fD  %c fD  %c fD  %c fD  %c fD  %c fD  %c fD  %c fD  %c fD  %c fD  %c fD  %c fD  %c fD  %c fD  %c fD  %c fD  %~c fD  %vc fD  %nc fD  %fc fD  %^c fD  %Vc fD  %Nc fD  %Fc fD  %>c fD  %6c fD  %.c fD  %&c fD  %c fD  %c fD  %c fD  %c fD  %b fD  %b fD  %b fD  %b fD  %b fD  %b fD  %b fD  %b fD  %b fD  %b fD  %b fD  %b fD  %b fD  %b fD  %b fD  %b fD  %~b fD  %vb fD  %nb fD  %fb fD  %^b fD  %Vb fD  %Nb fD  %Fb fD  %>b fD  %6b fD  %.b fD  %&b fD  %b fD  %b fD  %b fD  %b fD  %a fD  %a fD  %a fD  %a fD  %a fD  %a fD  %a fD  %a fD  %a fD  %a fD  %a fD  %a fD  %a fD  %a fD  %a fD  %a fD  %~a fD  %va fD  %na fD  %fa fD  %^a fD  %Va fD  %Na fD  %Fa fD  %>a fD  %6a fD  %.a fD  %&a fD  %a fD  %a fD  %a fD  %a fD  %` fD  %` fD  %` fD  %` fD  %` fD  %` fD  %` fD  %` fD  %` fD  %` fD  %` fD  %` fD  %` fD  %` fD  %` fD  %` fD  %~` fD  %v` fD  %n` fD  %f` fD  %^` fD  %V` fD  %N` fD  %F` fD  %>` fD  %6` fD  %.` fD  %&` fD  %` fD  %` fD  %` fD  %` fD  %_ fD  %_ fD  %_ fD  %_ fD  %_ fD  %_ fD  %_ fD  %_ fD  %_ fD  %_ fD  %_ fD  %_ fD  %_ fD  %_ fD  %_ fD  %_ fD  %~_ fD  %v_ fD  %n_ fD  %f_ fD  %^_ fD  %V_ fD  %N_ fD  %F_ fD  %>_ fD  %6_ fD  %._ fD  %&_ fD  %_ fD  %_ fD  %_ fD  %_ fD  %^ fD  %^ fD  %^ fD  %^ fD  %^ fD  %^ fD  %^ fD  %^ fD  %^ fD  %^ fD  %^ fD  %^ fD  %^ fD  %^ fD  %^ fD  %^ fD  %~^ fD  %v^ fD  %n^ fD  %f^ fD  %^^ fD  %V^ fD  %N^ fD  %F^ fD  %>^ fD  %6^ fD  %.^ fD  %&^ fD  %^ fD  %^ fD  %^ fD  %^ fD  %] fD  %] fD  %] fD  %] fD  %] fD  %] fD  %] fD  %] fD  %] fD  %] fD  %] fD  %] fD  %] fD  %] fD  %] fD  %] fD  %~] fD  %v] fD  %n] fD  %f] fD  %^] fD  %V] fD  %N] fD  %F] fD  %>] fD  %6] fD  %.] fD  %&] fD  %] fD  %] fD  %] fD  %] fD  %\ fD  %\ fD  %\ fD  %\ fD  %\ fD  %\ fD  %\ fD                                                  1%    %    1%    %    Hx  m   H5K H=K 9WH%   H%(   %@   %@   %@   %@   H=s I HH8I HH8I H="s I H=cs H H=9s vI H=s eI H=Ds HMEMUHMJ H=u 5H_̀ H=u H%    %     %    1Hu
   %    %    1%    %    LD9 H=Ī I]HH;]txL#HSfHnH{flIT$L"^H{`赏  HLzI$LL;et3IH= LE1~ H=} 8H{`o  {L2H=ɩ #" H=H & I]H=0 MLMLMt	IQ  ! 1Kd I+m H%    H1'L,%    H1wL,%    1H%    1H%    1%    %    1%    %    H%   H%   H%   1
   HEdH+%(   uHH=6 [A\A]]XH=G 1/` A H5 ]C H1胿L,%    LH   1H/    3HV H%    DDh1H{
   UuLhH%    fD  UHHdH%(   HE1HEdH+%(   uɺ   H5e H=+ }W     H=y Hr H9tH  Ht	        H=I H5B H)HH?HHHtHE HtfD      =  u+UH=  HtH=W YNd ]     wUHH}uHEH@    HEH@    HE@    HEPHEHEUP]UHH@H}ȉuHEȋPEЉE܋EHHHEEHHHEHEH@HUHHhOHEH} u
   HEH@HUHH<OHEH} uHEHe   EHH    HEȋ@HH    HEHȾ    HVEHHHHEȋ@HHHHEHȾ    HVHEȋU܉PHEHUHPHEHUHP    UHH }u       ϕHEH} t5UHEHStHEHHE    
HEUPHEUHHH}HEH@HIHEH@H9HE    HXUHHH}HEH}HEHUHH0H}uЉMfEHE EHEHE@9u HEPHEHRyjHEHPHE HHHEHEHPHE HHHEfBHEHPHE HHHE܉BHE PHEEUHH0H}uHUHE؋ 9E|
   HEH@UHcHHHEHEH@UHcHHЋHHE@HE0HEHnQE} x8HEH@UHcHHHEH@MHcHHHHRHHQEUHH0H}HUHMfEE    HE u
       E       HEH@UHcHH@f   HEH@UHcHH@f#EftXH} tHUЋMHELE؉HAHEH@UHcHHf@  HUHRMHcHH@fB&HEH@UHcHHЋ@uEEHE 9E+EUHHH}uHE HcHEH@UHHwUHH H}HuHEH< HEHHǸ    p{EE    NHEH@UHcHHЋ} t	H; H; H5; H}H¸    {EEHE 9E|H; HEHHǸ    zUUHH}uHUMHEUHEUPHEHUHPHEHUHPHEHUHPHE@     HE@$ ]UHH0H}dH%(   HE1HE@$t
   HE؋@    HE    HE؋ EfE HE؋P HE   H}HHEH} uy n   H} ~Eu[    HEH} HE@$gHE؋@HEHHHE؋ HΉHEH} HE@$,HEHPHEHPHEHPHEHHEHP    HUdH+%(   tOUHH H}HEHPHEH@H9uHEHE} tEHEH@HHHUHJ UHSH   H8H0H($dH%(   HE1ǅ@    HǅH    HǅP    ǅD    H0H HA  H8H#DD 3  @      HPH   HHHHjGHXHX   HXHHHHHPHH`HhHHXHpHxHHHXHMH]HH HX(HMH]HH0HX8HMH]HH@HXHHMH]HHPHXXHMH]HH`HXhHMH]HHpHXxHPǅ@    @P@DH`D;$@HcHPHHPHHHH=FHXHX    HXHH@HcHHHPHH`HH@HcHPHHHH  @HHPH0HHHH(HPHHP6HHHH0H     H(H     HHUdH+%(   tZLH]UHHH\ HEHEH  UHHH\ HEHH HH_xHEHZ  UHHpHEHU\ HEH} tHEHEHk	  UH9H]UHHHn\ HEHEH5  UHHHI\ HEHH# HHwHEH  UHH]sHEH\ HEH} tHEHEH  UH&sH]UHHH\ HEHEH  UHHH[ HEHHt HHvHEH  UHHjtHEH[ HEH} tHEHEH  UH3tH]UHHH[ HEHEH  UHHH[ HEHH HHFvHEHA  UHHHEH\[ HEH} tHEHEHR  UHH]UHHHu[ HEHEH  UHHHP[ HEHH HHuHEH  UHH4eHEH	[ HEH} tHEHEH  UHdH]UHHH"[ HEHEHi  UHHHZ HEHHg HHtHEH  UHHAHEHZ HEH} tHEHEH  UH
H]UHH   H$ H   HhdH%(   HE1H2 H2 HHHxHx ui       HhHHHHu?HH讖HHhHPHxHaLHhH@HFHHH5W2 HxHǸ    ECoHxHL    HUdH+%(   tGUHH   HxHpdH%(   HE1HUHxHH eyHEH9pt    HUdH+%(   tFUHH H}HEH@HEXHEHP@HEH HHLu5HEH H[HHEHPHEH@Hu       HEHEH Hu    UHHH}Hu#HE HEHEHmH} u֐UHSHHH}dH%(   HE1HHHEH H负HEHEHHHHUк   HHо       HHkHH HH)H9tH   H$   H  H)H  Ht%  HHH HHEHEHHUHEHHHUHEHHHUHEH _PATf@H HEH舁HEH} u    0HEH誓HHEHPHEH@Hu       HHUdH+%(   tODH]UHHH}HEHttXHEHtEHEHt2HEH@HtWH\/ H5/ H/ HѺ   H?HEH@Hu%H*/ H5. H. HѺ   H>UHH}HEH@]UHSH8H}dH%(   HE1HHHEH H~HEHEHHHHUغ   HHо       HHkHH HH)H9tH   H$   H  H)H  Ht%  HHH HHEHEHH=- HuHEHHHǸ    IuHUHEHHHEHZHuHEH@H HHUdH+%(   tSBH]UHH H}HEHHHEHHEH} uwHEHHEHEHHEA        Hƿ    CuCHEHP@HEHHu(HEHؐHHEHPHEH@HEHEHHHEUHHpH}HudH%(   HE1HE    HǸ    EE} yW AHME@   HΉ~H~HEHHUE    EkEHUdH+%(   t@UHHĀH}HuUdH%(   HE1HE    HǸ    >EE} y WHME@   HΉm}H~/UHE    H~HUHHEH HtE    EjEHUdH+%(   t@UHHH}HuHMHE   HHUHHH}HuHMHE    HHUHH   H(H HdH%(   HE1H(    HǸ    @@yy    @HpH@   HH H     HH H@H<< y"H H HH H     
ǅ<    @Gi<HUdH+%(   t>UHHpH}udH%(   HE1HE   HǸ    EE} yn NUH) HEHHǸ    :[HME@   HΉdH@uE    EhEHUdH+%(   t=UHH   H$ H@HHHdH%(   HE1eHH uWHHH5( HIHH   HǸ    pHHHHHԺHUdH+%(   t =UHH   H$ H@HHdH%(   HE1nHH uVHHH5( HIHH   HǸ    ?oHHHHHUdH+%(   t\<UHHH}HuHMHE   HHUHHH}HuHMHE    HHUHH   H$ H0HHdH%(   HE1THH uPHHH5& HIHH   HǸ    %nHHHHjHUdH+%(   tH;UHH   H$ H@HHHdH%(   HE1蕨HH uWHHH55& HIHH   HǸ    fmHHHHH6HUdH+%(   t:UHH   H$ HpHHdH%(   HE1ǅ    ̧HH u
  HHH5i% HIHH   HǸ    lH    HǸ    qy    HH   HYHHyt-y@nt/n6YtY,NtN"0t1uH H  
ǅcHUdH+%(   t9UHH   H$ H0HHdH%(   HE1`HH uPHHH5$ HIHH   HǸ    -kHHHHhHUdH+%(   tP8UHH   H$ H0HdH%(   HE1襥HH u\HHH5E# HIHH   HǸ    vj=  ~HHqHUdH+%(   t7UHHH}HuHMHEH" H=7 IH       iUHH訾HEH} u    HEH" HHH7 UHHjHEH} u    HEH`" HHCHG7 UHHkHEH} tHEHEHEUHHH}HEH " HHUHH H}dH%(   HE1GwHHUH5! HEHHHǸ    2Ey    HEHUdH+%(   t5UHHH}HEHUHH H}dH%(   HE1vHHUH5A! HEHHHǸ    Dy    HEHUdH+%(   tr5UHHH}HEH脱UHHHE    H  H^HEH} tHEHg?HEHEHHEUHH H}H  HHEH} uHEH         4Hۑ HHuHEHѺ    H]EHEHEUHH   H$ H   lH`HXHPLHdH%(   HE1HHHuH HPH5 HIHH       fltl   (  賰uZ   Hv H   HHduPLPHH4 HD HXH`HHMIHǸ    fH   HH3 H HXH`IHǸ    e   H H  HXH`HǸ    esHLHg3 Hp  HXH`IHǸ    reBHpl   HΉ`HH   HXH`HǸ    /e    HUdH+%(   te2UHH   H$ H`HHHdH%(   HE1Hǅ    Hǅ    H HtmH HHHH)uMH H HH;s'H HP HHHb        H{ Hv HHHH u
  ƅ   H    HtHH W  HHHH    H5HH   HHPH  H H   HHm   HH <2uHHHH`   HHHHHԌHH    HH H7 H]Ht\HHIHH H H(Ht'HHHH:`7
HHHHH+QHIHH«HHs4H\ޒ Hu      oHAޒ H:ޒ Ht>H.ޒ HH   HHԁHޒ HP HHHw_t8HH-H;s HHHH;_    HUdH+%(   t.UHH   H$ H0HdH%(   HE1HH HHByDH5 HH   HǸ    `HHHHCHUdH+%(   t.UHH   HHXH`HhLpLxt )E)M)U)])e)m)u)}dH%(   HH1ǅ0   ǅ40   HEH8HPH@Hԑ H H0HHH~u,,HHdH+%(   t+-UHH}HuHUHґ HUHH@Ց HUHHґ HUH]UHH0}HuHUHUHMEHΉL'E} t2DEHM؋UH= HuHEEIȉHHǸ    1_HEf.     f.     f.     f.     f.     f     UHHdH%(   HE1HEdH+%(   uHgӑ HH   H8D+fD  UHH   H`HhLpLxt )E)M)U)])e)m)u)}dH%(   HHHB> Ht6HMH0ǅ0   H8HPǅ40   H@HHdH+%(   u6+fD  UHSHdH%(   H]H   9Hڒ H= HEdH+%(   uH]*f.     f.     f.     UHHdH%(   HE1)HUdH+%(   u*    UHAUATSH(dH%(   HE1   LcAHuK|-lHH      fAnHuH{fnKT- fbf$HM   LHME~`At^      LCf9LCtHcfLsHA9SHEdH+%(   u)H(H[A\A]]     1@ 1̺   )     UHHdH%(   HE1wHEdH+%(   uL)ff.     UHSHdH%(   HE1t)HcǉH| jHt   fnfnfbf HUdH+%(   uH](fff.     UHHdH<%(   H}
   mjHtH>  HfPHUdH+%(   u(@ ff.     UHHdH%(   HE1Ht@ J9t
BvHEdH+%(   uH(     UHH dH%(   HE1Ht)If     J9rA9tuHEdH+%(   uifD  uA uHEdH+%(   uGL齣{֒ uHΑ       H=3 LEHOFLEE֒    J'f.     UHAWAVAUATSH8dH%(   HE1HE    HX  H}R!H}IH HHHf% u6  fW  1E1E11HuHE    kIH=  wOHUt<,t<-   <
u4MI     EtSIcHLI
HH9tGfD9 u1LHE胢HEHUdH+%(     H8[A\A]A^A_]1ff.     A9  fEAM9   IH~HzHu1LEHE    LEH=  IiHE <,ZHHFM9=I  {Ԓ H̑    Hh    LEH81LM	$LMLE7Ԓ    M9H}?    I$ SE   LD     IY   LHML)LMH9LEHBDHcHHhHMLMILE0Z1SHGI$HEHwHDqt>HE1t HH5    1r0mI$E(Hff.     UH= HSHUHuH8dH%(   HE1HE    &x<H}+H}HEHEHtHUdH+%(     H]@ T   ެÅ  S   HEƬLMȉA9_  E{  IcLMH| -eHa  LM    AQDHQ  Dɿ   fo<  Hfn   Hfnfp Hfp f.     ff.     fofofoHfffafifofafifaBH9uAD΃D)yvL~ <  fn~<  fpfffofafafpNfafpHcʍrfTHA9sftH
A9bfTHXD  EȉH5 1    LME1'@ 11:!f.     UHSHdH%(   H]
   zcHtH7  fXHHUdH+%(   uH]!fff.     UHHdH%(   HE1Ht9wHUdH+%(   uD  HcDw1!UHHdH%(   HE1   HtGHUdH+%(   u fUHHdH%(   HE1   HtfHUdH+%(   u fff.     UHHdH%(   HE1Ht ufHUdH+%(   u
Ð   T @ UHHdH%(   HE1HHUdH+%(   u f     UHHdH%(   HE1Ht4AO1&fD  PAHcfD9Wt~"9|AHEdH+%(   uDfpfD  UHHdH%(   HE1Ht1AO1#fD  PHcfD9Wt~%9|1HUdH+%(   u@ pfD  UHHdH%(   HE1H9thHHu`HcO;Nu7~KH1ff.     HH9t/DDfD9Dtf     HUdH+%(   u       1w    UHHdH%(   HE1HtfHUdH+%(   u2fU1HAUE1ATSHdL$%(   LeIuyfu#ALD[yLD9ܻHUdH+%(   uH[A\A]]fD  UHHdH%(   HE1Ht	HcGDGHUdH+%(   ulff.     UHHdH%(   HE1H9HuUHtPDNHcWD9|C~?LW1    HI9t'HcDWfD9TN|uD9uݸ        HUdH+%(   uf.     UHAVAUATSH dH%(   HUHH9thIHt`HH  DfDJE9  E  IcHH<J1@ HH9tGHcAtvf9p8uA9ufD  1HUdH+%(     H [A\A]A^]fD  E9T  C<HUHcDMH]IH  DMHUE  E     11-    DfADuDJA9~3A9~.HHcDDBHcADFfA9~fADuDJA9AD9}8HcIcH)MTu f.     tBIfA4BH9BD)FDD9}3IcDEI|E AD$M)HT HcItFDED+eEDL]LIH;jL#E9f     E~TIcLI<N1D  HH9Hctrf9pzu߃A9uHLߋH'C<HUHcDMH \HUHIt-EE1115D  E111fff.     UHSH8dH%(   HUHH9tnHtiH   DRDNE9   E   IcHLN1     HI9tGHc\zf9X9uA9u@ ff.     HEdH+%(     H]HE9}@E   f1HEdH+%(   r  HH]E9|fff.     E~IcHLJ1D  HI9t?Hc\~f9X1uA9uHEdH+%(     H]H'    E111    D9}6A9~1HcLc|zFDFfA9܍XfA9MA[DMD9|EIcD]H| DUDMHUHuYHHD]DU    1DMHUDXHuE11D  D9A9HcLc|zFDFfD9|ԃfD9McÃAfB|C@ UHcHAUATS1HdL$%(   LeIHHHt_UIHt'HcA)1HIcHHH.AEHEdH+%(   uHL[A\A]]@ UHcHHHdH%(   HE1T>HEdH+%(   u@ UHcHHHdH%(   HE1HD>HUdH+%(   u UHAWAVAUATLcSI|$HH(dL,%(   LmIXHHtb   fAnL1fnHH{MfbfECE~#E1MtJfCT DHIl9M9uHEHHEdH+%(   u<H(H[A\A]A^A_]    E1D  DHA9E9uUHHdH%(   HE1HEdH+%(   u1   7d@ UHHdH%(   HE1Ht@ J9t
BvHEdH+%(   uH     UHATSHdH%(   HE1Ht%HfD  J9r9t'uHEdH+%(      H[A\]@ u܋uJC~$E1@ DHAH虐D;c|HEdH+%(   uFHH[A\]t6Ò uH       H= H
3Ò    	f     UHHdH%(   HE1   HtGHUdH+%(   ufUHHdH%(   HE1HtHcHD7HUdH+%(   u	øx     UHHdH%(   HE1Ht@WH# H9t97uHUdH+%(   uøf     1f.     f.     f.     UfHnflHHdH%(   HE1H   fHnfl   oGoFG oF G0oF0G@oF@GPoFPG`oF`GpoFp   o      H      HEdH+%(   u&fD  UHSHdH%(   H]H  G  H   fHnH   fl fHnfl   o@oC@ oC @0oC0@@oC@@PoCP@`oC`@poCp   o   ǀ       H      HUdH+%(   uH]If     UHSHdH%(   H]HH   跏H   諏HEdH+%(   uH   H]{dfD  UHSHdH%(   H]HH   WH   KH   /dHEdH+%(   uHH]鳌~ ff.     UHAUATASHDHdL,%(   LmAպ   DE  H   H   E~mE~hMc1EEfD  H   1H;Hs7H;P sH8HpHHHD(I9tH   HH;HrHI9uH    t1HUdH+%(   uH[A\A]]ø@ ff.     UHAVAUATSHdH%(   HEH   HH~~HP IE1~p 1 ff.     H9s<I9s7H0HHIHLd(IA<$x9A$I   HP HHH9Av9}IHEdH+%(   uH[A\A]A^]fUHSHdH%(   H]HH   E  Hǃ       HEdH+%(   uH]bfUHAVAUATSHdL,%(   LmIH   H   HW   HG E1~ufD  1 ff.     I9s>H9s9HHWIHLd(IA$x`8A$I   HG HHW9AN9}I,D  Iǅ       HEdH+%(   uH[A\A]A^]pUHAWAVAUIATISHHHUdH%(   HE1H  H} n  I$      L1MMhID$E1HELzD9  HEE1ˋ@   LuMMMI   L;k   L;{    I   I9  H   HO  L;h   L;x    HHPIIHDD(A   HMLHuE1H*  L]L#TM1LsaL]  MMILAD(HED9x2LuMMAt$LIUgfD  MܻLثHEdH+%(   ~  HH[A\A]A^A_]@ MܻfD  A'D  HELXx   މAA  I$   H~   E'Mc1DCD  I$   1H;Hs7H;P sH8HpHHHD(L9tI$   HH;HrHL9uI$        H HEH~aHEH HeL- MGTH| IH/fD  Mxt{1|Mܻg2
fUHAVAUATSHdH%(   HEH   Ht^HP ~VILc1@ L;hs<H9s7H0HHIHLd(IA<$xQ4A$I   HP H9HEdH+%(   uH[A\A]A^]	D  UHAUATSHdH%(   HEH   H   IH   H   HP   HH E1   @ 1 ff.     I9slH9sgHHpIHHT(xMHHt+L;g   H;_    HHWIHHT(HH6  I   I   HH HHP9At$9}I^	?  Iǅ       HEdH+%(   uH[A\A]]@ 1G    UHAWAVAUATSH8dH%(   HE1H) E   0FEH   H  IH      p x`   =  I   Hg  I   HS  HC E1HuHuDe   DeE1   f.     I9   HHCuIIHD(HbxZM   Mt'M;f|   M;~ svIIVIIHT(I111LE>3  MLHu3  uhI   IHC HSD9~(I   I9Pu8bfD  E1 M9}IDe1f.     LE3EHUdH+%(   uH8[A\A]A^A_]ø۸QUHcHHdH%(   HE1H   H;psUHcH;P sLL HHLHLD(x2H   Ht(H;ps H;P sH0HPHHD(	    1HUdH+%(   u     UHHdH%(   HUHW0HЃHEu<      D΃t
   HUdH+%(   uf.           /@ ff.     ULcHAWAVAUATSHHXHG0dL$%(   LeIHJEѨ(  A      IDDAtD   HcH   H;N/  L;N %  LH~fID$     A$LAD$II|8(L>EE  M  H   HtH;OsL;O s@  DHuDHc:  H~yHC0HUI$   HU       IT$   tHTIT$HHtHTIT$Hʨt
HDID$ 1fD  A      軝 HUdH+%(     HX[A\A]A^A_]D  ID$     fA$AD$뺐         O@ HC0IHAB    IrEHƃIW        IAL]Dt
   H   H;HxL;H nHLHHED(ET   DEHcHBH(  }HHHEK9  HMH   M   HAA            ID$   MtHHcIT$LHI$MtHID$FH} tHHID$ H)~1[fHLDULOULEJD	(H|5  
LEDUUE      A               ?H}蓛 eff.     UHAULcATIS1HdH%(   HEH   HP Pyf     H9sFHHPIHHȋ|(x,11 $  3SuI$   HHP 9~+L;hrHUdH+%(   uH[A\A]]fD  1     UHAULc1ATS1HdL$%(   LeIH   [Of.     L;h s^HHHIHHȋ|(xD11 $  rRu7HI$   {[I$   m9~2I$   H;XrHUdH+%(   uH[A\A]]D  1@ ff.     UHAUATSHdH%(   HEH   HH   HP IE1   fff.     1M@ H9sIHHPIHHȋ|(x/11 $  {Qu"I$   HHP HH9~'I9rHUdH+%(   u&H[A\A]] Au9}It1ff.     UHAULcATIS1HdH%(   HEH   HP Pyf     H9sFHHPIHHȋ|(x,11$  PuI$   HHP 9~+L;hrHUdH+%(   uH[A\A]]fD  1    UHAUATSHdH%(   HEH   HH   HP IE1   fff.     1M@ H9sIHHPIHHȋ|(x/11$  Ou"I$   HHP HH9~'I9rHUdH+%(   u&H[A\A]] Au9}It1ff.     UHAWE1AVE1AUATISHdL,%(   LmIfI$   iE   D9~}I$   1HP LaH9sJHHPIHHȋ|(x0L$@1NAƅu I$   HHP 9~L;xrAIrfE1 HEdH+%(   uHD[A\A]A^A_]"fUHHdH%(   HEH   HUdH+%(   uf.     UHHdH%(   HEH   HUdH+%(   uf.     UHHdH%(   HE1HUdH+%(   uHGkff.     UHSH(dH%(   HE1tFtBUHֺ   }0  H   HtM}}HcH&0  H   Ht1HUdH+%(   u$H]H   g1  Hǃ       UHAUATSHdL$%(   LeIH   #1  IǄ$       I$   I   /  I<$AD$    L9t,H ff.     HGHCHpvL9HHuHEdH+%(   uH[A\A]]fD  UHHHW(dH%(   HE1H҃tHUdH+%(   u     G8UHH0dH%(   HMHHA8   iGaLI@8HtfH9p(   H@HuHy    0   uHMHULEf.  H   uHMfHnflLE p(HqH   H   H   fHnHUfHnfl HIp8HxHHptH~HT8Ix8HPH HUdH+%(   u1fUHHdH%(   HE1@tHOHu/H    HtHEdH+%(          HwH9sHH   fH*Hx}fH*YHxKfH*^^  f/sH,H   {fD  \H,HH??D  HȃfHH	H*XD  HfHH	H*Xnf.     IfII	I*X8mf.      UHcHHHHwdH%(   HE1H>HtHEdH+%(   u}%  D  HEdH+%(   ufUHHdH%(   HE1HEdH+%(   u#  ff.     UHAWAVAUATSH(u@UdH%(   H]Hh  HD`  Ht9HcEL$@IIHEdH+%(      H(L[A\A]A^A_]D  HcG0IH<@HT+  IHtEM|$E1EAE0~&D  I`UH1LLA%"  E;u0|߀} tMh  LYf.     M`  fUfHnǾ@   flHATSHH@HdL$%(   LeE1G    GWH{hHC`    HǃX      H)`  LHHEdH+%(   u	H[A\]3 UfHnflHHHFdH%(   HUHHBHoHEdH+%(   u U  HSH(dH%(   H]1)  HHtWfHn@    Hx@@   flHE VHUHzhHB`    HǂX      H)`  HHHEdH+%(   u	H]H> ff.     UHHdH%(   HE1HHD1HH9HDHUdH+%(   uff.     UHATISH H   dH%(   H]HV-&  H         A|$ t    E  H          u    [         H,  H       uFFI|$(?oH   HEdH+%(     H   H I|$ [A\],a@ sFJ@ H   HiH   IH   HbH   HE;qHEH    H_H   #IT$ H  HHUpH}1MtH   H+fff.     HL腒HLHE`HEHtI9t        H I9uHEdH+%(     H [A\]D  H   GpH   cH   H@ H   +   A|$ t       H   bH   H@ It$pH   oI|$bH   Hf     H   HapumH   I|$VbH   H     H   ;    IT$H7H   H'7D  I|$H   HnI|$aH   D@ UfHnHHdH%(   HEG   HGHwfHnflH0G uHEdH+%(   u    HEdH+%(   ufD  UHSHdH%(   H]HH:nH{ 1nH{(CHC(    fCHEdH+%(   uH{@H][VfD  UHATSHH HdL$%(   LeIH9tHumH}`HCH{(L9tBLkHC(CH{ mHHC     HH9t7L     u#HHL9tI$LIԀ    tL9uH3H9t1L&    uL9t I$LIĀ    tHL9uHEdH+%(   u	H [A\]Kff.     UHATSHdH%(   H]H_H9tI     HH[I9uHEdH+%(   u	H[A\]fUHATSH dH%(   H]HH9tDI    HI9t0H   H   H"CyLExEfD  1HUdH+%(   u	H [A\]Yf     UHATSHdH%(   H]HH9tIf     HHI9uHEdH+%(   u	H[A\] UHATSHdH%(   H]HH9tIf     HHI9uHEdH+%(   u	H[A\] UHHdH%(   HEHH@0HUdH+%(   uZf.     UHHhHHdH%(   HE1HG    HǇ      H)`  HHEdH+%(   u UHcHHdH%(   HE1H   H;PssHcH;H sjHHHHT
(HH냵FaIL@HpII8JL`LHHtHAHD`JT`HP   H   H   LHEdH+%(   u<ff.     UfHAWAVAUATSHcHHdH%(   HE1H   )E)EH;X<  LcL;h /  IIHU$D1E=HMtcք8   I$@0   AF0   Hu    D'H   IF0HHHHHLŠHMI   H;XsrL;h slHLhJT+(HH냵FaHHHLpHH8It`HH0HtHFID`IT`HPA   I   pA   H1HUdH+%(   uHH[A\A]A^A_]f     @ UHAWAAVAUIATSDHxHEHuDƉUH HEHEHMHEHE DMHxdH%(   HE1DMe fEM9L  EE  HcEMHEIE@Hpff.     A    t
}   A^;I   uE  HE1LPIH*    LU   H}HcMI   HMH;HEHMH;H 7HHHUHEHDd(A  HEE"AG   H HtLhH1LLLhA
11H5B    Lh	HEMLLhHuAPxKHx 7  Mx  A   HpDڃ~  L  HUdH+%(      Hx[A\A]A^A_]    HcMHpIE@Hh=   LU   H}HcuI   HuH;pHpH;H ҊHHEH0HDd0(Ay  HEE"AG   H HtL`HMLLL`A
U1H5    L`覺HEMLL`HuAPHx A   HhDڃ&H      DHIEXL81AF0  M6M9"  A    t} uA^;I   uEtHEULPIH7  oLU   jH      DHIEXL81AF0   MUELL0I   HEH;CHEH;C HCLeL#uJD (HC     I   y@ufC$I   vC( M6M91TD  LU   1f.     11H5    DLh豸1$  DLhA6L   U1H5l D   L``1$  DL`A6L7  fD}MELLDqI   H}H;{HpH;C H;DHCHD8(HËEC I   #?ufC$I    
C(     Mp  @ qUHATSHdH%(   H]HH hPAH{(lHH9tlA1 ff.     B&ƀ    HEH9uCD+C@9|1HUdH+%(   u3H[A\]@ H{@Wyո@ CD1+C@9}D  UHAVATIH@SH(dL4%(   LuIDXx'H      HID$XML01MHEdH+%(   uH([A\A^]*f.     UHHdH%(   HE1HEdH+%(   uH@1H/ff.     UHHdH%(   HE1HEdH+%(   u
H@<    UHATSHdH%(   H]HH`  Ht6S0~oE1f     H`  KdIHH  D9c0Hh  Ht4C0~-E1    Hh  KdIHHU  D9c0H`  C  HEdH+%(   uHHh  [A\]   ff.     UHAUATSHdH%(   HE1H   I_kLjI<$I9t5Hff.     HGfHnflHCHT_I9HHuAD$    I|$^I|$ ^I|$(3fI|$@ID$(    AD$HEdH+%(   u0HL[A\A]]\@ HEdH+%(   uH[A\A]]UHAWAVAUATSHhHuHUdH%(   HE1H  H~   H~   IHHl IG8Mg +GI _LI D]|  A_0II9uN ff.     HI9t8C0tH    uH   HߋP pyϸ   D  IP   L\I(  I AƉEKE   H ÉEH5H 1E    育  EEEw  HE1LuHELmE1@ AD9et^HEA؉AVLAUuHMHukH t LhHUdH+%(   ,  He[A\A]A^A_]Ð;]  EEpI(\rfD  I EJDE   H A1E    H5 mDUE  L}LuLmE1DeDLe@ AD9   HEE1DEEAVAUATHMHuH}QH tL}I II(II9  1D  ff.     ff.     ƀ    HEI9uAGDA+G@9I@ L}DeACT"AX     pD)ЉtftI DUEB4E{7M/DUfEM9  IG@E  Hx A];I   u踻E  HEULPIH     HUH}HcMI   HMH;HLHx  AHDDd(A  HEAF   D"H HtHMLLЋU1DH5P    HEMDHuLPEA   HxDyL	  f.     H      DHIGXL01AE0txDu1ELLDAhI   H}H;x'~Hx  ~H8DH\8(EC I   51fC$I    C(D  Mm M9#DUAD;pAO0U9u,1U1D  9tH9uUAO09t1H5N 1跭1   HUfU1H5 D   DE胭U1$  D+YLa  _@ HEDU      HUHuHcMI   HMH;H|Hx  |HDDd(A'  HEAF   D"H HtH1LL11D   H5 ìHEMDHuLPE  Mx   A   H}DڃAH      DHIGXL01AE0   Mm M90  A];I   uEtHE1LPIH   HU@ 11H5    DDx蹫x1D$  )L      Du1ELLD1XI   HEH;B{Hz  {HDH\(C     I   21fC$I   C(Mm M9    DU    Mp  T11=E1_@ ff.     UHH0~	 dH%(   HE1HsHUHE    fHnHo fl0EHuHG8HUdH+%(   u+ff.     UHHdH%(   HE1HtHFXHUdH+%(   u tHx   Hp  f.     U1HHdH%(   HEHH9t/    ff.     ff.     H   H H9u   HEdH+%(   uRfUHHdH%(   HE1Gt&HH9t6H1ҐH   H H9u   HEdH+%(   u    1    U1HATSHdH%(   H]H*uHteHE1D  HuHHt(H9   u1   HAtHHuHEdH+%(   uHD[A\]D  E1FfD  UHHdH%(   HE1    uƆ    uHEdH+%(   ufD  HEdH+%(   uf.     @ UHHdH%(   HE1GW0HO@G    HtH~XHEdH+%(   uUHHdH%(   HEHt GDHUdH+%(   uAUE1HAUAATAESHHH- dH%(   HE1HG    F	G1t   HHt%Dk1fDcHUdH+%(   uH[A\A]]H    ff.     UHSHdH%(   HE1HtoHHH  H;HCP    Ht*Hp Ct]H    CC    HC@Ht HUdH+%(   u&HH]    HEdH+%(   uH]fD  UHHdH%(   HUWfJO9t
BvHEdH+%(   ufUHH dH%(   HMHH? tAQfD  r9rq9tuHEdH+%(   uyfD  uHyHHM  HMH9HAP    Ht.H( At[HMH    AA    HA@HtHUdH+%(   uHf.     UHHdH%(   HEHH   HUdH+%(   u    UHHdH%(   HE10 uHWHH  GtHEdH+%(   u9     HH   H;WuH8   uHEdH+%(   uaff.     UHAWAVAUATSH(dH%(   HEȋGM  HIL   H~ H_W0L/H؄IDIEHG(H)H_ H;G8'  HcwHuIHH9      IH 1ILH5w    AIIF HH)L9r/{     HH51 1   HHI+F L9s[LeI!MAD$fuH5o    I^(1HUdH+%(      H([A\A]A^A_]H#EMd @ 1H5    蝢HI+F I9sAD$H)롸렋y} tMfLcHu 3      H=2 H"8}    !UHHdH%(   HEGtHH   HGHEdH+%(   uff.     UHAWAVAUATSH(dH%(   HEȋGC  I0   IG HW()AŃ  H5| McGIM!ILJ<	HMOHMIf   9   HII!M9tsIHI9OPs5HHH   IGHAwMwP     AwAJ< D!D9AGD!HuALDA)uIHHEIG IG A0 uIG IGHEdH+%(   uCH(H[A\A]A^A_]D  HH   HW(IG )AŃ1@ 1W    UHHAWAVAUATSHdH<%(   H}HH0H   F(   IE11E1E1E1 tq3D~0NA9   DNHFHGHV HWD~(At/H9t*1H Df4DV2H	H^8IA t	LnPLvXANL^uHUdH+%(      H[A\A]A^A_]@ HoO@   H D)H	fH~HfH~HLH9t3M)DM!K(IHHA@HEHfHnflfGH71ifUHHdH%(   HE1HEdH+%(   uH   
 UHSHdH%(   H]HH?FH    HEdH+%(   uH]Zf.     UHAWAVAULcATLcLSH(dL<%(   L}MHULIH(-Ht!LHUL8ALhHPL` HcHXHUdH+%(   uH([A\A]A^A_]@ UH(HHdH%(   HUHWHWHEdH+%(   u1s~ ff.     UHHdH%(   HE1HEdH+%(   upE;f.     UHAWAVAUATSHdL<%(   L}IHt^AIM t(I)tIILLDHHyb8tHEdH+%(   uHH[A\A]A^A_]D  L ff.     UHAWAVAAUATISHH(HUdL,%(   LmIHu_    t.H)tQIILHLDRZIHyEb8tHEdH+%(   uH(L[A\A]A^A_]    L}fff.     UHAWAVAUATSHdL<%(   L}IHt^AIM t(I)tIILLDbHHya8tHEdH+%(   uHH[A\A]A^A_]D  LNf.     @ SI      H  dL%(   L$  IH   H[n IH1 H    H81H$  dH+%(   u	H  [fPXH   Ht$(HT$0HL$8LD$@LL$Ht7)D$P)L$`)T$p)$   )$   )$   )$   )$   dH%(   HD$1H$   H$   HD$HD$ D$0   HD$   [Tff.     AWAVSH   H$ H@  dH%(   H$8  1H|  In  H</  H4$H$0     -H  H=޴ xL$HIHtH$0  YL$`  H$0  L$H<$HD$Ht$L$HTH      Ƅ40  /HPH41  H)LL= LH L$0  ML$IE1HŻ    HYH  H<$@LL   H` L HML$IE1hY  H$8  dH+%(      H<$H@  [A^A_@ H$8  dH+%(      H@  [A^A_@ LHژ L= ML$IE)    Ht$H$0  NH$   L>L$rHD$H9$   _HD$H9$   L   LH$0  G"L$.fD  H=a H=r 1L¾<   H= 1 Huj H8H= HP   HpHHE!D  HdH%(   HD$1H$    ?/tKH$j I1H    HLBHE Wt9H$HT$dH+%(   u HfHD$dH+%(   u	HH= 1@ SHHtBH? t:HHsff.     HH9r
:/uH9sHH[@ 1HH[D  HHHT$H)mH6q HtHT$HHZH[@ ff.     Hi H=q H   Hxfff.     H=p Ht HHh HxtHt8 uHh HxHfD  HH    ATUSHdH<%(   H|$H=} H$    IjHHHH55p HH5=H,$H L[ HHEMtM1H    HUt?H<H4$   H=(} H<$<HD$dH+%(   uH[]A\H=u 1w    AUATUSHH{g HL(H   H1    HHH|  uzHcH   L(IĐff.     ff.     IHH\HuHI    LLG.L;H[]A\A]       n   L(I뷐Hh  H$8  LT$    H$H  LH$@  L$P  L$X  dH%(   H$(  1H$p  D$   H|$ HD$H$0  HD$   V/   H$p  HAHt\    A    L$x  1A)HcLL$Mff.     ff.     HL9tIIHu tbHcLHD     H$(  dH+%(   ubHh   H40  HqHt tH*f.     He H   H* H81мf.     f.     H?H6HH)Rf     AWFAVAUATUSH8dL<%(   L|$(IH=< D$HtY1HǺ
   j)H= fD$ iHt4
   1HE)fD$"f|$  tf  @ ff.     1HT$ T     0  D$  P O   |$9  HcHIG1HDHIą   HD$    @HD$fD  H5Z 1IcE1   G,Ll$JQ@ K   D9tC,H9BT$IGH5.:    AJ1IH+D9t	IGI9rH` 
   H0GH|$H9|$tHHHD$Zf.     HD$(dH+%(   uKH8[]A\A]A^A_ù      f|$  D$"fлSI      H  dL%(   L$  IH   Hb IH Hr|    H81#H$  dH+%(   u	H  [RfPXH   Ht$(HT$0HL$8LD$@LL$Ht7)D$P)L$`)T$p)$   )$   )$   )$   )$   dH%(   HD$1H$   H$   HD$HD$ D$0   HD$   Hff.     AUIATUHSHZ	HHHt$;Ht{IL(H    HCHt$I|$LHHUHM CD, H}HBH9s0HtI0HH9HBHu HHHtHUHEHBHEL$H[]A\A]H=| 1fAWAVAUATUSHH   H|$HdH,%(   H$   HHD$(    HR  IHm  HD$I1IH|$(   H H ,NM  HD$0HD$f     LXCH   HHXSHHH7uL|$(IH Hۯ    H|$(MIEM   L5Ht$H|$( uT$H      kD$H@`HD)Hv|.exeuHcD$H|$HcH4LBH*LH|$(w4H$   dH+%(   u<H   []A\A]A^A_fD$   A   H- H= 1 ATIUSHI|$ t,11D  H<3I|$H    ]HI;\$r3fID$    A$[]A\ÐAWAVAUATUSHLwM   H_I      It2f.     DmH<N<HIwwKt;EHL9r111fHHtp9tHÉQHL9sG L 3I\$Mt$EHJ    L9rMuH[]A\A]A^A_    IT$9sH)H<1[H   ]A\A]A^A_zf.     H~ 1  AWAVAUATIUSH(LwH|$Lt$M   HD$    H_E1E1 @ I   M9soM;|$   ID$NI(LD$J4H}H2JyHL$IEHqL9tLD$H,I     IHt$M9r@ ff.     HD$L9sfD  H< }YHI9uHD$HT$HPH([]A\A]A^A_    H1HD$HXLpJ    If    HT$LKfff.     ff.     ff.     ff.     H4H4H    HI9tHH9uHI9uHl$LL)Hl$AWAVIAUIH= q ATIUSHyHHH   HLLHY I~   IvHH$DL'H   H^HD$H(@   HHbHtLHL0I_:   H/<IHuHH,HtLHLH|$ 0I|$It$   H$DL`'H/HLL[]A\A]A^A_?    HtHHD$I  LLLLx{:   L~;HuLLL[H|X H$Qff.     AWAVAUIATIUHSHHvH  I|$111fff.     HǉH H9B؍BHH9rH}H   LE11fD  ff.     IH H9B؍BHH9rH   L=.V LH5    1!H5i    1!LuAąt! ff.     I7-   AuI7
    H&I7H
   []A\A]A^A_ #L   H5 HHD$I1B!H5R5    1/!LLIA   L=DU A     I7-   cAsI7
   PLvI7
   9H|$o-H} H[]A\A]A^A_D  Hz1HXL=T fD  AUATUSHHoHtILgHE11 AEIH9s,I4HHDuH   []A\A]     H1[]A\A] HH9T H8iHW H8Z      H=_ HPfD  H     1E1dH%(   H$  1H|$HH$   HǄ$      H   H$   H   H$   1H5 H= H$  dH+%(   uH  袯fHMS SH8zHV H8k      H=^ O[Dff.     HUV Hx H=^ @ AVSHdH%(   HD$H V Hx Hp^ H      1HT     uD$B^ ; teH5͞ HBtRH[ H=] ^    H] H<HE ] H]        HD$dH+%(   $  H[A^@    I#t1HT     [ uD$] M   H= HH!   H=ٝ ufHɝ f.     =\    `   uZ=\ H=;H=? f.        H=P /H<  =~\    fD  L^ \ D  HH=| Hui\ ҍBN   DH    
   1HHf.     f.     USH(HcoHc^      =  v;  wpHt$H|$蔰H|$Ht$H EuJH([]fD  Ht$H|$T$]H|$Ht$H |$  ,wYu<{   t)uHHvH HHDHHDH([]@D  {   D؉)o뽅u{   )]f.     AVUSHH?  G0uu tH[]A^@ H-R HH    1H} KH} Lc   H    1ݩHMHKHt1C  H}    1LD$H& 觩LD$HIH}     7  	w7C05  H{ LD$Hۚ      1JLD$HII      D)H} LK 1   L Hɚ C1H} LK(H1[L~ ]   H    A^Ө H?    1轨HMfHu 
      j     H-1Q 
   Hu HK 9 AH} HHhK 1[   ]A^O    C0HKH      H{ LD$H t}   1LD$HIfx    C0 H}    1LD$H~ 輧LD$HKHIHH2 w@ H .@ t\H{ LD$H H f     LD$H "    LD$H     LD$Hǘ @ ff.     SI      H  dL%(   L$  IH   *HkO IHA Hh    H81裦H$  dH+%(   u	H  [ҧfPXH   Ht$(HT$0HL$8LD$@LL$Ht7)D$P)L$`)T$p)$   )$   )$   )$   )$   dH%(   HD$1H$   H$   HD$HD$ D$0   HD$   k5ff.     AWAVAUATUHSH8HL$Ht$(T$$HJ L%FN HHt&I<$Hh    1H;"H    HM I<$   1HD HQLE Mu/yfD  I<$LH   H  1"LE MtLA8 uHB ff.     A8 I<$Hz H+g HE˾   1H֤LE MuHD$( tI4$
   HD$( LT$(E11fLEtfD  DC`H`AEuH{XDHLT$ @HcHHT$薞IH  IcHT$Ht$H<@DHHH9HBD)HH@H)LH LSXMtAELYMcoK@HAoCADoC AD oC0AD0oC@AD@oCPADPA  LL1ff.     H`  uHcH `   5LA>tcHD$Ht}P   HD$rH LhH\M} AAw<-   @uxA;F   II9uAF`I`uI4$
   H8H[]A\A]A^A_U \$$LwAv`I~`tI   ]Au@ I~HtLT$8T$t&I~ HhLT$:T$HOt$$LI`AIHD$     @A;Ft@-I~HIwT$7T$@ HcH`   |3H1҅=NHu%Lt$(VHb`   1LC38I0fD  H1J HIH9u3HHtH    1`H    1MD  HHA    12fAVIIATUSH   dH%(   H$   Ӄ_  H   F0l  ƃ A  AA@a  HW I9t	H  MS I{   A    AA    fMJ(H|$0         L\$H L LT$LE1H|$LT$H|$Ƅ$    L\$AB0          A:      I{ g  ASt^  IH@8-N  
  IAS5  D  F0   @tHW H9t	H  MS A      A:W
  H59 HcH>    I{ tA:v   fEw     HG IJIH    H811E    '  HxG IJH8  L> H͐    1觞H$   dH+%(   	  H   []A\A^ IC    E   HG IJIH`    H81C1       fo )D$0f)D$@)D$P)D$`)D$p)$   )$   )$   HF H EO  IJI  HH    1躝D  E1;     HAF AJIHd    H81|1D  foX )D$0f)D$@)D$P)D$`)D$p)$   )$   )$   fD  L HN    1bf     IRHHt  Is  HtIC    1LAR8IR1uf.     1uAB@IR   I{  H2  IC    ?-  Ht$(
   L$IjLT$?LT$L$HE HD$(8 H5A LfD    I{  H  IC    ?-A  
   Ht$(LT$L$LT$L$IRHD$(8  IRIB@2	!DǉfIB@(IBHH     IR  H    1IRHHttIRHHt	8 \  u      I{3  H  IC    fD  1uIB@IRH(f.       I{  H  IC    Ht$(
   L$IjLT$<f.       I{-  H  IC    Ht$(
   L$IjLT$/IRHHt  "11LAR8Xf.     HH    1ڙ.HvB HNH8H       DJA   Et{H|$0L;    1      LT$H|$H|$LT$H
B H E  IJI  HHW    11E1LJMD  H|$0L    1      LT$H|${LT$H|$sH}A H8  HNLb    1H 謘     IBH     AJI   HH} 1sfD  IB     f     Is  H_  IC    HH2f   
H"ASt  IH@8-  &  IASHPHxIHASt_  IH@8-O    IASHPHxIHASt6  IH@8-&    IASHPHxIHASt  IH@8-  ?  IASHPHxIH6ASt  IH@8-z    IASHPHxIHQAst  I;H?-    AsI3H~HvI;IBIR@IBIR@HHEASt;  IH@8-+  9  IASHPHpI	Ir@DJ+IR@IBHHH    1褕nAJI   HH 1肕LH> HNL H~    H81UIz@mIz@[Iz@Iz@Iz@NL    1H ZH= IJL H    H81ٔ-Ir@Ir@H5| L H= 1H5X LH5D L׉ډL$LT$LT$L$AB0fPXHHt	11h   # ff.     ATIUSHH   HL$8LD$@LL$Ht7)D$P)L$`)T$p)$   )$   )$   )$   )$   dH<%(   H|$H=8 H$   H   HD$HD$ $   D$0   HD$H/t&HHt11LH   "H= 1fff.     AWAVAUAATIUHSHH   L=; HH1H    I?LCM}   H+fD  I?LH   H 1賒LMtLA8 uL5  ff.     A8 I?H~h HT IEξ   1HgLMuI7
   u tE   LmMtbLLLHH       LH=[ H9HFHuI|$lH}It$HtwM`H`uH[]A\A]A^A_     A$9EtU`H`t9Eu1H<f.     1H&LHNfD  H1H`M vfAWAAVIAUATUHSH   H$LD$dH%(   H$   DHt
I8 V  fHǄ$       $   
  LeAAI  Lt$E1E1҃D$M4$A>-t[   IcEHMcLJ| IcHD     H$   dH+%(     H   D[]A\A]A^A_AFt<-   D\$IVHT$ Eu<h  H4$+     ff.     ff.     9F  H`DEuHvXHuIc  I$AE1HT @ IcALt IAA~ /  D\$I~H|$ E&  H|$ H5ׂ LD$0LT$($  H|$ H5 $  H|$ =   LT$(LD$0HH  H$D$l    D$h    H|$`HD$0    LT$XLD$HLt$pE1D|$8IHl$@D\$TLE/E  M  H|$0 .  MXM
  E/EtDl$(E1MgMg  LH|$ LHI\  HD$ L|$(  0@
  @=  LIAD|$8LD$HHl$@LP\$TL$   H$   H$   D$   D$   L$   L$   $   HL$   H$   D$   D$   L$   L$   $     HT$ H4$1LD$H|$_LD$IPH  H4$11@   HHL$(Ht$(LH  I`E    1IFA~ L$   HDº   H$   D$   H$   H$   HD$   L$   $   HD$(pL$   H$   D$   D$   L$   o  L$     $   MH|$ LD$8LT$0LT$0LD$8HH  A~nuHD$ xou
x-N  H$DE  LT$0ILD$@Ld$8Ld$ \$HHf     H{HtLL  DC`H`EuLd$8LD$@Lt$0L$H\$M	  u
A>h
  H4$>  AD  V`H`  9Fu1IFA~ H|$(HDº   L$   H$   D$   D$   H$   L$   $   L$   H$   D$   D$   L$   q  L$   $     MfD  H	3 LL$   H` H} L   HǄ$       L 1    ME1M   \$R@ H$   H-`    LHR HHE14    HIOM   MtH$      LH_ L H HHE1t5H-Od@ L@H$} 1      H=| 1f\$L$      LHQ_ L Hw MIE1YtLH$   HT$H!    Dl$(fD  LT$Lt$   HT$ H4$H|$LT$?oH=- I$H^ HHHEˀx- E1   H3|  HH4$H|$f.       u8  D  H5{ LD$0LT$(LT$(LD$0  H|$ H5Â LD$0LT$(LT$(LD$0H|$HL$   H$   D$   D$   L$   H4$H$   1L$   $   VLt$ HT$ H4$   LD$H|$tLD$A@	H4$   1$   H$   D    |$(A<$n  A|$o  A|$-   ID$HHD$(xHt$(H|$ HHD$x  HD$x   HD$ D   <=  HcLt$pDmIHl$@LT$XD|$8LD$HLt \$T@ HvXHI~LD$(Lt$ LD$(I$ -IcsfA@H|$ HT$ LT$(LD$0H<HT$`Ht$ LH) A  H|$ n   Ht$ H=/y H9HF   HD$ 8nxox-HD$pLLHHHHL$(HL$(HJ)   1A1Lt$LT$1dH4$H|$L   LL$Lt$5LT$RM֋\$H|$ Ht$ H|$(HH|$0 S  AG`D$(  T$hD$h   IG`Lt$0T$lL|$0I3L\$0HT$`M   :    AW`T$(  LALT$XD|$8Hl$@Lt$I܅Lw HXZ t$hIEH, LT$MK   H:qHz PH$Z LDHL$01_AXLT$LT$XIAD|$8LD$HHl$@LT$ \$T:   T$lLt$0T$hHT$`HHT$XAW`T$(6  T$hLt$0IG`D$h    T$lH|$HCL$   H$   D$   D$   H$   AILIALT$XD|$8LD$HHl$@\$TLt$Mt,IHt$IH5{    1IIVHuH' 
   H0   VLAL\$0LT$XD|$8Hl$@Iܺ   Lt$.AG`D$(  D$h   IG`L\$0LIALT$XD|$8LD$HHl$@\$TM  L$   H$   H$   D$   D$   L$   L$   $   :LT$ 4MLT$hMIG`D$h    T$lD$lT$hAMLT$XD|$8IHl$@Lt$D$hHL$05LT$XL1D|$8H5t Lt$AILT$Hl$@LT$H|$HH4$H$      L$   H$   D$   D$   L$   L$   $   <LIALT$XD|$8LD$HHl$@\$TMP     HD$H$   H4$1HHL$(L$   H$   D$   D$   L$   L$   6H$H$8 HSHt"H5s    1H`uVC`H`uFAW`T$(tE1IG`DL$hIH=.v 1LIALT$XD|$8LD$HHl$@\$TMD$lMLt$D$hR	HZ( HL$    Hv H81   D$lM   Lt$D$hIALT$XD|$8LD$HHl$@\$TD$hHL$0Lt$ff.     EI1O@ ff.     HO1uN1HփvD1fDE   HAVAAUAATIU@SHuVH{Ht@tL*tAS`H`u[]A\A]A^fH{Ht@tLtC`H`t
D;suD	k0[]A\A]A^    DE   AWAAVIAUEATIUSHHH@Ņue     H{Ht@tLztIS`H`uH[]A\A]A^A_@ H{Ht@tLBtC`H`t!D;{uELs(A	Dk0A   Dk0H[]A\A]A^A_fS         Lq H  dL%(   L$  IH薨H% IHm H^?    H81}H$  dH+%(   u	H  [>~ ff.     PXH   Ht$(HT$0HL$8LD$@LL$Ht7)D$P)L$`)T$p)$   )$   )$   )$   )$   dH%(   HD$1H$   H$   HD$HD$ D$0   HD$   ff.     AVAUATU1SH   G,dH%(   H$   HuK  E1i  E1uC  1C   C,d    {  z  E    p  E  {~   u{=fff.     H{Htb  HC H  H(Hu#  HC HhHPHS H  H=   uHHuȬfD  J    {   E~  {   E   1H$   dH+%(     Hİ   []A\A]A^ÐSH|$m  D$A   CC,dD  H|$  D$A   CM@ H|$Ɛ
  D$   CC,f     |$ǥ8f軥#fD  諥fD  1ɯ{葥C,     |$   袯|$i|$`+ HC0HtHC8H   HЉ@    H=m 1-1ŉBC,   H=l 1   ŉפC,c   H=l 1   ŉڮ裤nfD  H3C,  H3   )f     D0   {<  E  {2  E   1A-'  D  |$E9f     |$Kf      @ |$   |$|$踣C,?    |$1ͭ|$蔣|$苣C,fH>X |$g|$^f     |$G|$>f     |$'|$
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w  HH    Hǅ      HHHH tHH   HH'HH tHH   Hǅ    JHH x9
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D  UHEPTHE <?uHEƀ    HEHE@0   HE@4   HE؋PHEP8HE@<   H#m HEHHu        HEP@HEƀ   (      HHEHPhHEH@hHu
  HEH@hHEHE؋@HHHEHPHEH   HxHHEHHEHHHÀHHEHPHEH@HtHEH HtHEH@Hu
   HEPHE؋@ЉHEH@H9s.HUHEH5l HH¿           HE؋@HEHHE@HHEH@HHHXUHEP HExHMUHEH5k AIȉH¿       EHEHEH9E    UHH0H}E       HEH   EHcHHHHHHEHE ubEHcHEHH#`  HHEHHa  HEH} u_MHEHHUHuHEHE} tE$EEHcHEH   H9O    UHH0H}HuHUHMHEHH  Hƿ   $}HEH} u1HEHj HHο        H   HEH  HEHHlH} tHEHMк   HHFHEHCHHE   HHiHE.   HYHEH} tHE  HEǀ   HEHUH   HEHUH   HEǀ   HEǀ   HEǀ  G HUBPHE@T    HEUHH H}HEH   H   HEH   H͆HEHǀ       HEHǀ       HEHǀ       HEHǀ       HEH   HNHEHǀ       HEHǀ       E    HE苀   xHE苀   jeEHEǀ   HEHǀ       HEHǀ       UHH0H}E    HEH   Ht#Hh Hƿ        x`  HEH   Ht*HEH   HEH   HH蛦HE   HEH     HǸ    HU؉   HE؋   yE	 ؉EE?R HHEH  Hh Hƿ        E  HE؋          [HEH} u={HHEH  Hg Hƿ        dE`u  HEHUH   HEHit0E_HEH  Hg Hƿ        %  HEHZkt0E_HEH  Hg Hƿ          HEH虁HEHEHUH   HEH   Hu=zHHEH  Hgg Hƿ        gE_x  HE@<t<HE@<t0E]HEH  HPg Hƿ        0  HEPHE؈   HEH   HEHHUt=yHHEH  Hg Hƿ        E_   HEH   HEHHE    H}Hu:~yHHEH  Hf Hƿ        IE_]HE@fuHE@ft;HE@f= t-HEH  Hf Hƿ        E_    HEH!EUHH}HE   <]UHH@H}HuHUdH%(   HE1H} u+HEH  Hf Hƿ        b_kHEHHEHE@   HUHEH9HGHEHHHEHH>HEHHHEH  HDf Hƿ           HUdH+%(   t5UHH0H}HuHUdH%(   HE1H} tH}t+HEH  He Hƿ        _BHE EUHEPPHE@PHUH  H5e        =    HUdH+%(   t5UH}}t}u       ]UHH0H}HuHUH} uQHUHEHHW  HEHUHEHHY  HEH} tHEH@HE؉    UHH0H}HuHEH   HEHE       HUHEHHZ  HEHE@   HE@<tHE@<upHE HEHHhU  HEH} u.HEHd HHο        HXHUHEHHu
HE;HEHEH@HHHHH9EHUHHE	   H$d HEUHEHEE} xEK# t 4EHEHIE} y EUHH H}HEH@pHPHEHpxHEHhHѺ   H E} tEHHyHEHphHEH@pHHHUHJpHi   HHEHEHUHHUBHE@yHE@HHZHE@,HEƀ   HEUHH0}܉uؿ    HEE   UEЃM    EEHHEHEHEHUHEHHHu    HHHEHHEHEUHH H}   yHEHE@0t!t)HEP<HE@8։/HE@<HE    UHH@H}HuHUdH%(   HE1HEH@`Hu
   HEH;Eu
       HEA    A!      Hƿ    ilHEH}u ^HEHEHEHEHUHEH9HGHEHH`HEHHMHEH@`HUHHHEHUHP`    HUdH+%(   t0UHHPH}HudH%(   HE1HE   HEHHEHUHEH9HCEċEăvE   HEH.   H辷Ht	E    3EH   H)HUHEH蓉HEHUHEH9HFEHM}ċUH5D` HEHuAIȉH   HǸ    aHHEHEHQ)HHE HHH uHE <_tHE <.tHE _HEHE tHEHH9ErHEH}HUdH+%(   t.UHH0H}HuHEЋ@Tu
       HEЋPTHEH(  HYHEHEHt
       HEH:HEE    HEHEUHEHEH(  HYHEHEHuHEH t   EHEE;E|    UHHPH}؉uHUȉMLELMHEHHEHEHtHEH  HEUԉP\HEUЉPHEH@     HEH/|HHEHPHUHEHHHUHBHEH@HtHEH@HuBHEH@HHEH@    HEH@HӨHEH@      HEH0HEHE    HE@   HEHEPHE@   }t}u       HEPHUHEHHB  HUHEHHtHE@HEPHExHEHH HEPHEH@H5\ AIȉH¿       HEHJHEHEA    A!      Hƿ    bgHUHB`HEH@`H    ؉EHEH@`    EC HHEH@H5\ HH¿        1HEH@H?HEH@    HEH@H#HEH@    EiH} tHEH@`HUHMHHТHEH@HUHRhHMH)HH=<<HH5%\ H           UHH0H}E    E     HEH   EHcHHHHHHEHEH@H  HEH@H@Hk  HE    G     5  EHcHEHHkL  HHEHHN  HEHEH@HxHEH@H0MHUHEII   HE   HEƀ   EHcHEHHK  HHEHHM  HEHEH@HxHEH@H0MHUHEII   H~E^EHcHEHHK  HHEHH.M  HEHEH@HpMHUHEIA       H!E} tE$EEHcHEH   H9+    UHH H}HuE    MHEH   UHcHHH@HUHHpuHEH   UHcHHEHE苀   9E|    UHH0H}HuUE    tHEH   UHcHHH@HEHEH܁HEHH9u7EHcHMHEHH6uHEH   UHcHHEHE苀   9Ey    UHH H}HuЈEHE@(t]   t   }mu1UHEH@H5X H¿           }yHEj}yuHE    X}muHE    FHE     :HEU.UHEH@H5qX H¿        wHE@     UHH0H}HuHUHE@(t2HEH@HUH5`X HH¿           HEHHEH}vHEHPHEH <"t2HEH@HUH5AX HH¿           HmHE@,HH9ErLHE@,xHEH@HMHUH5%X AIHH¿        \HE@,HHEHEHHHUHEHH/HUHEH  HE@     UHH0H}HudH%(   HE1     HMHEغ    HHHUHо t>ž ؉EE< HHEH5W HH¿        E7HE t'HEHW HHο        S    HUdH+%(   t!$UHH}HuHE@,EHE@,u   KHE@8t*E   HHEHEHHHEHUHHH]UHH H}HuHUHE@(tJHE@(t>HE@(t2HEH@HUH5V HH¿        P  HE@(u9H}v2HEH@HUH5V HH¿           HUHEHHt9HEH,HEH@HUH5V AHH¿        sHE@,tFNt.Dtt8HEHE1HEHEf"HEHEHEHUHHE@     UHH`H}HuHUdH%(   HE1E    HLV HE   HH莠t
    k  HE=   HHEH} u*HEHV HHο        %  HEH{E̋EHHPHEH <
uEHHPHEH  HE  HEH u1HE =HEHU HHο        &  HUHEHHHEH} tHE@ t
    q  HE@4HcHEHHEHEHHEHE ytyV"t2"|LmwDHE HMHEHH(E   HUHMHEHHE   HUHEHH6Eȃ} t0HEH@HUH5T HH¿        E   HE@(t;HE@(t/HEH@HUH5T HH¿        SHUHMHEHHEȐ} tE-HEH@HUH5T HH¿       |    HUdH+%(   tQUHH   H$ H  HHH@dH%(   HE1ǅP    H`HnH`H   HPT H   HǸ    QTT y
2  T  ~
  HT HHH蘯HXHX u HS HS HHnHXHX    HS Hƿ        B   H@HHHHHPP t5PQ6 HHH5S HH¿        ֿ(HHX   HH HuHXHPHUdH+%(   tqUHH   H$ H@HHHdH%(   HE1ǅ    HHJwHHR HHHHH     ؉45 HHR Hƿ        þ   HHHHH_ t54 HHH5yR HH¿        V$HH   HHxHH HUdH+%(   tUHH0H}HE    E    3HEH   UHcHHHEHE uHEHEEHE؋   9E|H} u    tHEP4HE@,HHEHE؋  HMH5Q HEIA    H   HE} tEHEH@pHE؉       UHH0H}uHU؋UHEHFHEH} t8HE؋U-H} tHEPHE؉HEPHEHUFHEHEH`uHEH/uHEUHH0H}uHU؋MHE    HBHEHEHCt    8HEHHUHEHHEHEH<tHE    UHfEE                    o    T    9  x    f  
  
T  	   	B     0            t}   tc   tI   t/   t
t   HN    HN    HN    H8:    HN    HN    HN |HN sHN jHN aHN XHN OHN FHN =HN 4HN +HN "HN HN HN HN ]UHHH}HEH<UHH@H}HuHUHMHEȋHHEк    HiHEHEȋHEЉHMgHEHEHRt@HEHgHHUHEH5N IHH¿        "       HEPHEЉHBHEH} u5HEHHUHEH5M AHH¿        ʸ    rHEH˭t=HEHHHUHEH5M IHH¿        z    "HEH HEHEPHE   UHHPH}HuHUHMdH%(   HE1HEHHE    HHEHEHEHeHEHEHլt6HMHUHuHEH	EӀ} tEԉHEHE   HEHtSHEH t@HEHHHUHEH5L IHH¿        L       HEHft+HUHEH5L HH¿            [HEHOt#HEH贮HEHE@HcHEH#HEH裮HEHEH襮HUH   HUdH+%(   tUHH0H}HuHUHMHMHUH=UL HuHEIHHHǸ    FE} yEHH;Er    UHH   H$ H0HHdH%(   HE1H uHK HHHD_HHH   H tHHHHHUdH+%(   tRUHH  HHHLLdH%(   HE1H )HH胩0HHH@ǅ,       H@HHbHPHP u2,HH5J H¿        x  HJ HPHH胦uUHHHH@HHHlt
  H HB  HJ HPHHuUHHHH@HHHt
J  H  H  HI HPHH蟥uUHHHH@HHHt
  H @H^  HPI HPHH-uTHHH H@HHHt
f  H H  HH HPHH輤   H8H@HHHt
  H@tSHP89t?8HPHH5gH AȉH¿          8HPH H
  HEH HPHH٣  H@PHH&;HXHX u6H@PHH5G H¿        K
  HXH%t?HXH7HHH5G HH¿        
  HXPHH?7HhHh yBHXPHhHH5G IȉH¿        芰Hh"
  H@tUH@H9ht@HPHhHH5jG IȉH¿        %	  HhHPHXPHPH H	  H2G HPHH   H8H@HHHt
&	  H@tSHP89t?8HPHH5F AȉH¿        +  8HPH H;  HF HPHH
  H@PHHW8HXHX u6H@PHH5>F H¿        |  HXHVt?HXHhHHH5F HH¿        '  HXPHHp4H`H` yBHXPH`HH5E IȉH¿        軭H`S  H@tUH@H9`t@HPH`HH5E IȉH¿        V  H`HPHXPHPH HO  HE HPHHH  H@*H@+* tH=E HHH>E HH) t-HH3E HHο        h  09,t4HPHH5.E HH¿        #  *t;+t-HHE HHο        ګt  H@tEH@t6HPHH5D H¿        臫!  H@   H@PHH4HXHX uAH@HHHHH5D AHH¿          HXHuHXH薢@t4HHHH5D HH¿        謪F  HXHLH    H]HXHXHXtIHXHjHHHHH55D IHH¿          HXHH    HHX+ tYHXH  HXHHHH5C HH¿        薩0  HXH貞t?HXHHHH5C HH¿        A  HH5C HpHH   HǸ    9HHXHHpA    IHt44 t4`  H H  HbC HPHH赚   ) t-HH>C HHο        S  H8H@HHHht
  8t=8t28HH5B H¿        קq  8HP$H H   HB HPHH趙u`H8H@HHHt
   H8HHP(H Hj t4HPHH5DB HH¿           HPHH58B HH¿       车,H@,;0H@u*HHB HHο        h    HUdH+%(   t6UHH H}   JEH} u    wuHE    HHHHu!MHE    HHytHE<E   EEH9EsEEe    u;EsHEUHH}HE@0tHE@0u       ]UHHH}HuHEPHEP0HEPHEP4HEPHEP8HEPHEP<HEPHEP@HEHP(HEH   HEP HEPDHEPHEPPHEPHEPTHEH(tHE@<HoHEP<HE t*HEPHEH@H5O@ H¿       uHE t6HEHHEPHEH@H59@ AȉH¿       47HE t*HEPHEH@H5-@ H¿       HE t6HEHHEPHEH@H5@ AȉH¿       躣7HE t*HEPHEH@H5@ H¿       聣HE  t*HEPHEH@H5@ H¿       JHE @t*HEPHEH@H5? H¿       HE %   t,HEHP(HEH@H5? HH¿       آHE %   t*HEP$HEH@H5? H¿       蟢HE %   t*HEP HEH@H5? H¿       fHE %   t$HEH@H? HHο       3UH}}t&}w)} t}tH? H? H? H6 ]UHSH   H8H0,(L DȈHEHdH%(   HE1f)E)E)Ef)E)E)EH0H{H,HcHHHHHHPHPH8H(  H*HXHXHH`HXH8H(  HNHhHhH-t+,H> Hο        觠
  HP@HP@HH H@H9s-HhHZ> HHο        O  HXHzt?HXH;HHhH55> HH¿        ]  H` t@H` HHhH5> HH¿        謟  HXHH8H(      H]HpHpH蚔t?HXHjHHhH5= HH¿        )  Hp@HPR9s-HhH= HHο        G  H8HHxHxHtHxH
  HhHKHHxHPHxH@Hu-HhH@= HHο        M  Hx@\    Hx@0    Hx(PHP@HxHP ,HxPHHxHH HxPHhH5< IȉH¿       趝H8H(  HxH@LEH}HpMIHLL tL  HUHxHHEuZHHxHHLL t2HxH@HE< HHο        LT  E%           ;HHxHPpHxH@pHu
  HxHXp2CHxH@p@yHxH@p@   HxH@p(PHhHcTHHxHZpH;HCHxH@pH@Hu|HxH@pH@HhH6 HHǸ    HxH@pHUHH[HxH8HHR  LL tL    HUdH+%(   tmH]UHHPH}HuHUȉMLELM   jHEHEHEHUHEHHHu    HHHEHHEHEHHEHEH9Es2HMHUHEH5W: IHH¿        њvHEHl:HHEH  HEH  HuEHEH  HUHMHHypHEHUH  HEH  HEHP`    UHH`H}HUEHE    HE   y
    4  HE   HcHEHH  HEHUHEHH  HEH} u5HEH  H9 H9 Hƿ        谙  HEH(  HQXEE      UHEH(  H
#HEHEHuPHEHEH(  HGHEH9 HEHHNuHEHEЋUHE  EE;EpH} u*H8 H8 Hƿ        ͘  HEHAEE    LDEHE   H}UHuHEHuEIHHẼ} tE{  EE;E|E      HEHPhEHHi   HHEHE@0!   HE  xPHEHPhHE  HHi   HHPHEH@H5$8 HH¿        ɗ   HEU  HEH   HtXHEH   L@HEH   HHE  H=	8 HuHEMIȉHHẼ} tEfEEHcHEH@pH9HEH   Ht5HE  y'H7 H7 Hƿ            UHH H}HuE    H} t,HEH HvHE@EeEH} tHEH HvHEH@HEHE    MHUHEHEEtEHEHEEtEHEHEEtEHEHEEUHH H}uEHcHEHH_  HHEHHd  HEH} u    HEH@HUHH}H} tHE <?u       ]UHH H}HE   HY  EHE   HX  EHE   HX  EHE   HX  EHE   HX  EHE   HX  EHE   HX  EHE   HuX  EEuMEuBEu7Eu,Eu!EuEuEt       UHSHhH}HuHE   HW  EHE   HW  EHE   HW  EHE   HW  EHE   HW  EHE   HW  EHE   HkW  EHE   HWW  EE    E   8  UHEHHEEtHEH蠉uEt9HEHt)HE@   HE@   HEH      E  HEH^   HEHHEHEHHEHEHEH@HE"HE <.tHE <?uHE _HEHE uHEHEE   HEPE    THE@    HEȉPHEHEȉPHEHEHHEHEHEȉEHEHEE;E|  EtcHEHHtSHEHEH?H+t3HEHEH?HEHE <?C  HE _7  EtFHEH蘇t6HEHEE   HEPHE@     Et HEH&tHE@     Et HEHtHE@     Et*HEHTtHE     HE@   \  Et*HEHatHE     HE@   
'  EtHHEH躅t8HEHބHEH踄    މHUB   E   HEH脅   } uCH51 HE       H3E} yE   UHEH^HEHEHӇHEHEH*EE   HEPE    UHE؉PHE@    EHEE;E|EHEHNU9    H]UHH}HE   yHE  uHE   ~       ]UHH}HE  ]UHHpH}HuHUdH%(   HE1EH}    HEH@HEH H$HUH(  HEH(  HE} tAHEHǀ(      E HH\/ H^/ Hƿ        f  HEH(     H\H} B  HEH(  Hu,H/ H1/ H7/ Hƿ       跍  HEH@HEH H7HUH0  HEH0  HE} tAE HH. H/ Hƿ        CHEHǀ0        HEH0  HHEHEH0  H8HEHEH0  HXHEE    0  EHHDHEHEȋ@  HEȋ@H   H*HHEHPHEH@HuE   E    HEH HE   EHEHEH(  H;:HEHEH讈uLHUHEHHF  HEH} t1HEH}HHEH@UHcHHHЉʉHEȋPHE@HHEHEHHEȋ@HH9EEEE} t.HEHktH- Hƿ        |E    HUdH+%(   tLUHH}HuHEHEHEHEHEPHE@)]UHSHxH}HuHUdH%(   HE1E    HEHwEHEHEH8HEE H} u#H- Hƿ       諊  H HEHH|@  H, HEHH|"  HE@uqHUHMHEHHFE} uEu<E~  HUHEH5, IȉH¿         UHEPEE    HEHHE|  HEHEHWHEH} tHEHt*HEHf, HHο       {]  HEHjHEHEЋ    HEЋ    HEȋHEH7HEH} u,UHEH5%, H¿          HUHEHHbHEHEH0{t.HUHEH5, HH¿       讈   } tHEH@HEPHE@tHE@uHE     EHEE;Ex]HEHJHHH   HWv    HUdH+%(   tH]UHH0H}E    HEH(  Hu
       HEH(  HtFEE   \UHEH(  HL HEHEH}t,HEH(  HUHEHH8E} tEEE;E|    UHH}HE   tHE   u   )HE   uHE   u       ]UHHH}HEHUHH0H}HEH0  Ht,HEH0  @dtHEH@  Hu
     E    @HEH   UHcHHHEHE uHE@8t
      EHE؋   9E|HEؾ    HHE>HE@|uHEHt   pHUHEHHNHEH} uHEؾ    Hr"HE.HEHt   #HUHEHHB"HEH} u˸    UHH H}EHEH8  HuHEH   Ht
       EtHEHWt    kHUH8  HEH8  HE} t:E- HH\( Hƿ        輄HEHǀ8      E    UHH`H}dH%(   HE1HEH(  HEE    HEH(  Hu
      HE   HG  t?HEHHtE  H' Hƿ           \  E      HEHPXEHHi   HHEHE@   HUHEHHa(     HEH(  HNBEE      UHEH(  HG HEHEH[yugHEH}uVHEHEH(  HHEHEHHEHH:uu            }HUBEE;EVEEHcHEH@`H9HEHDE}    HEH(  HUHHD+HEЋUHEЉHHEHEHE} tE  HEH(     HPHUHEHHE} tEu  HEH   Ht_E    HUHEHH*HEH} u
6  UHEH   HMHH苄 HEȾ    HEDHE  HE  HEHx  HEHp  HEAH=f E} tH} u4HEHHEH(  HHEȾHHEHY} tjHEHE} t(EB HH$ Hƿ        р-E HH% Hƿ       詀E    EHUdH+%(   tyUHH H}HuHEH   HEH   HUHHqHEH} uBI HHEH  HEH5$ IHH¿        
    HEUHH H}HuHEH   HEH   HUHH2qHEH} uBHHEH  HEH5$$ IHH¿        ~    HEUHH H}HuHEH   HUHHHEH} uB<HHEH  HEH5# IHH¿        ~    HEUHH0H}HuHE    HEH   HEDHUHEHH   HEH} u    BHUHEHHptHE#HUHEHH:_HEH} u    UHATSH H}HuH} u    hHEHHEH} uM"IHEH  HEHXHH# MHHƿ        }    HEH [A\]UHATSH H}HuH} u
       HUHEHH/HEH} u    sHE HEHHcHEH} uMYIHEH  HEHHH}" MHHƿ        }    HEH [A\]UHAUATSH(H}HuH} u
       HE    HNHEH} urIHEL  HUHEHHHHuH" HEHHH! MMHHƿ        J|    HEH([A\A]]UHH}HuHEH   H@HHHHH9Er    "HEH   HHUHHHHH]UHH}HuHEH@HH9Er    HEH HUHH]UHHH}HO! HE   HHXUHHH}HuHE@u
      HE@=Lou
      HE@u1HEH@ Hu$H  HEHHmu
      HEHCt   {H  HE   HHNWuWHEHEHt   @H HEHHltH HEHHlu       UHH}HuHEHEHEHEHEHPHEH@H9t#HEHPHEH@H9s(   !HEHP HEH@ H9s   ]UHH`H}HEH   HEHE    HE    E    E    HEH   HEH   HH	t;uHHEH  H8 Hƿ        @y_
  HEH      H\HHEH   HEH   Hu
	  HE       HUHEHH|HEH} u
_	  HE@   HEH   Ht.HEH  H Hƿ        }x_Q	  HUHEHHeHEH} u
_)	  HEHEHEHUH   HEU  HE@(HEH   HUHEHHXHEH} HEH   Hu.HEH  H Hƿ        w  HE      HEHEHEH   EHcHHHHHHEHUHEHHHEH} u
_!  HE HEHH/HEH} u
_  HUHEHH  HUHEHHHEH} u
_  HE@AHEHHHE@(AHEHxHUEH5@ APQIHщ¿       vHH_ HEHHhu3HEHPHEHHEHH蘝E} @  E  H HEHHOhu3HEHPHEHHEHH%E}   E  H HEHHhu#H Hƿ        u  H HEHHguHEU     H HEHHgu#HE@t
_/  HEHEE  H HEHH\gu#HE@t
_  HEHE  HE@  HE@  HEH@H  HEH@HtSH HEHHfuHEU  MHUHuHEH{E} {  EQ  H HEHHftH HE   HHPu'HE    HEHUHPHEHUHP  Hp HEHH+ftH^ HE   HH|Pu'HE    HEHUHPHEHUHP  H! HEHHetNH HEHHet4H HEHHetH HEHH}eu2HE    HEHUHPHEHUHPHEƀ    H HEHH1eu!HEHUH   HEU    Hw HEHHd   HEH@H^HHEH  HEH  Hu
f  HEHPHEHHEH  HHaHHEHPHEH  HEU  >  HUEH5 Hщ¿       r    HE@	g  HE@,EHEH@8HuEHcHEH   H9r
_  UHEH   H HEHHc   H HEHHc   Hv HEHHc   Hi HEHHlctxHe HEHHRct^EHcHEHHHHEHH5HuH} }HMUH5 IA       p   HE    HEHUHPHEHUHP   HE@u]H HEHHbtH HE   HHLu$HE    HEHUHPHEHUHP3HEHH HUEH5 IHщ¿       pHUHEHHPHEH} >HEH   HtHEH   UHcH9s+HEH  Hk Hƿ        o_jHEH讖tHEH6zHEH@`Ht'HEHp`HEH@XHHѺ   Hw]HUHMHEHHUUHH}HE@EHE@fu%}t}uHE@u       ]UHH}uHE@EHE@EHE@9Et    4} u}u   !}t}u}u       ]UHH0H}HuH} u
   HEH,EE      UHE؉HHEHEH,dtHEHc   HEHE؉HHEHUHEHH_uZHEHctHEHf tFHEHgctHEHgtEEE;E'UHH0H}؉uH} u
   HEH+EE   wUHE؉HzHEHEH1cuJHEHeHEE    HEE9uE1EHEHEHa9E|EE;E|UHH@H}؉uHUȋMHEغ    HHEHEHE؉H HEH} tHE  HEHw`       s  t  `  HEHIcEEt HE@u
   3      )  H} tEHUȈHE@u
      HE@t#HE@wHEPHE@!Ѕt
             HE@t
       H
 HEHH%]t
          }H HEHH\t    \   UHEHgb@u    ;HEHMb HEغ    Ht           UHH H}HuHEHEHEHEHEHE 9t$HEHE 9s
         HE udHEP0HE@09t HEP0HE@09~T   MHEP,HE@,9t HEP,HE@,9}"   HEHPHEH@HH[UHH H}HEH!(EE   >UHEHHEHEH^tHEH`< uEEE;E|    UHH@H}H} u
      Hc HEȺ   HHL/E܃} y
       UHEȉHHHEHEHaHEE    1HEHEȉHHEHEHk^uEHEHEH\9E|HEH\9Eu    QHEHEUH5% HEȉѺ   HE} yH Hƿ        gEUHH   HHHǅx    HE    HHH   Hu
    B  HH  HcHHHHHEHUHHHHHEH} tHEH@8Ht
_  HHH(  Hhh yh  HEH@ HUHJ8    HllH% Hο       fǅ\    i  \HcHHHHeHEH} u
_5  HEHX  HE HHHHHEHEHb  HHH   HEHH   HcHE@   HH_HEH} u

  HHHUH   HH   HHHEHE@       HHH   PHH   HHH(  HUHH+HUBHE@2HEPHEH5 H¿        <eHE@	  HE@HHH(  HHEHEHHH(  HHHHEHPHEH@Hu
t	  HE\PHE@<HEP!HEH@H?  HEHEH@    HEH@HH9Et9HEH@HUHH萻HHEHPHEH@Hu
  HEPHHH(  HHUBHE@<HEHHEPHEH5 AȉH¿        cHE@t  HE@HHH(  H@HEHEHHH(  H^HEH HEHHU  HEHTYt5HEH@H H5. HH¿        #c  HEHxHE    HEPHHH(  HSHEP,HE@,2HEP,HEH5 H¿        bHE@,P  HEPHHH(  HHUB0HE@00HEP0HEH5 H¿        Hb  HEHP8HE@HHH(  HHUB(HE@(   HEH HHο        a  HO HEHHSu;HEHEHE    HEHP8HEHHHH(  Hd.HEHk HHο        `a  \\;lHH   HK Hο       aHH   u
      HH   HcHHH   HnHѺ@   HNH} 1  HHH(  H!phHHH(  HHEǅ\    iHHH   \HcHHHEHE u4HEHHHEP\H5q Iȉщ¿       `\HH   9\|HEHEHEHdTlǅ\    ǅ`      HEHXH\HcHHHHHHEHEHHH(  HHEHEHHH(  H*HEHUHHHH訔HEH} u6HEH6HHEH5
 H        ^  HEHT   HEPHHH(  H\HEHEHWHEǅd    adHH    HEHЋ@t<dHH    HEHЋ udHH    HEHHE dHEHR9d|hHEHE@f  HEPHE@HEPHEHV    pHEP`HEPHE@   \``\;l`HEPHx #  HxHEǅ`    ǅ\       HHH   \HcHHHEHE    HE@0ttP`ЙttHEP4HEP4HE@,Љ`HEHxHEH4HEP\H5r IAȉщ¿       \\HH   9\%`HEPHEHPlǅ\       HEHRUH\HcHHHHHHEHE؋HHH(  HHEHEHHH(  H	HEHUHHHH7HEH} u'HEH HHο        [@HEHT    HE@4HE؉P\\;l    UHH}HuHEHPHE  HH9]UHH H}HuHE    HzHEOHUHEHHu HEH HUHHLuHE/HUHEHH)HEH} uR        UHH}uHEH   EHcHHHHHȋ w       ]UHH}uHE   9E]UHH}uHE  9Eu   SHEH   EHcHHHHHȋ tw!tt	             ]UHH H}E    HEH@@   HHEH} u
  E      HEH@8UHcHHЋUHcH    HUHH HEHH    HEH <E  EHH    HEH@<t#EHH    HEH@<   EHH    HEH@    EEHcHEH@@H9szHEH@8UHcHH u^HEH@8UHcHH@u>HEH@8UHcHH@uHEH@8UHcHH@ftE   HEH@8UHcHHЋUHcH    HUHH HEHH    HEH@    EEHcHEH@@H9QHEH   HEH@@H    HEHH HEH1EUHHĀH}HuUHMLELMHEH@8UHHHEHEH@pH@pHEHEH@pHEHE@EHEH\tWHEH~StDHE HEH MHUH5 AAHH¿        V[  HEH{!  HEH@H EHE苀   EE    ,HEH   UHcHHHEHEЋ@9EtEE;E|E;E|7HEH MHUH5 AHH¿        V[H  HED@HEHxHEH UH5 HMQEIH¿       UHHE <uHE    
HE    UHEPHEUP      HEHnZ,  HE@<t-HEH HG HHο        ,U[r  } tHE苀  9Et`UHEHHHHEHH%HEHEH HMHUH5 IHH¿        T[  HEH@Ht<HEHHHEH HUH5 IHH¿        kT[  HE    UHEPHEH@HEP      } t	}  v7HEH MHUH5 AHH¿        S[<  HE苐  HEH   HEH@HuHE؋@HHtFHE؋xHEHHHEH HUH5 AIHH¿        oS[  HE    UHEPHEH@HEP      UHEH EUHEHHHHEHH:HEHE苀  9E   HE苀  y/HEH UH56 H¿        R[  HE    UHEPHE苐  HEPHEH@HEPHEHPhHE苀  HHi   HHEHEHH HEDHHEL@HE苐  HEH H5  }WQH¿       	RH    K  HE苀  9EuKHE    UHEPHE@HEH@HEPHEH@HEP      }   UHEH@t8HEH HMHUH5w  IHH¿        QQ[  HE       HEHPhHEHi   HHEHE@\9EuuHEPHE@9u_HEHP HEH@H9uJHEHH HEDHHEL@HEH HUH5  }WQHH¿       PHHEHEH;EQHEH;Er<HEHHHEH HUH5 IHH¿        OP[  HE     UHEPHEȉHEPHE@        _  UHEHpt1HEH HUH5 HH¿        O[  HE       HEHPhHEHi   HHEHE@\9Eu`HEPHE@9uJHEHH HEDHHEL@HEH HUH5q }WQHH¿       9OHHEHEH;EfHEH;Er.HEH HUH5q HH¿        N[7HE    UHEPHEȉHEPHEH@HEP    UHH}HuHEH@ H9Er HEHP HEH@(HH9Es       ]UHH8H}HuHUE    HEH@`EHEH@`Hu|       E+EEЉEHEHPXEHHi   HHEHEH@H;ErHEH@H9EuHEH@ H9ErEE	EEE;E|HEHPXEHHi   HHEHEH@H9EuHUHEHHtHE    UHH   H}HuHxHE@,HEHEH   H9Er
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  HMHUHEH5/ IHH¿       aLHEH@ HUHJ8    HEE    5  EHcHxHHRHEH} u,UHEH5 H¿        K_  HEH@H HEHUHEHHHEH} u4MHUHEH5 AHH¿        K_  HE@HEH   H9rBHE@ȋ}HUHEH5 AIHH¿        6K_8  HEH HuHEHHEH@H9r7HEHMHEH5 AHH¿        J_  HEH HEHE@u<HE u2HE@HEHHHHEHHHEHE HEHHHEHEHtHEH/ HEH}MUHEH5 IAȉH¿       JUHMHEHHHEH} u4}HMЋUHEH5 AIȉH¿       I   HE@PHcHEH@H   HH;CHEH} u
   HEHUHPHHEH@ )EHE@PHcHHHHHHEH4LEH}HMUHEMIHE} tE&HE@PPHEPPEE;E    UHH H}HuHEH(  Hu
   HEPHE苀   9tHEHWt    `HEHJtFHEHPHEH(  HH	E} yEHE@P    UHEPT    UHH   H$ H   H$ H0HdH%(   HE1H HA   HǸ    dHh       H苦H HHHAHH |  ? ؉踽 HHH5 HH¿        =Gg  HH HHHǸ    ;uH   HH HHHǸ    uHP   HH HHHǸ    辥uHPvHH HHHǸ    肥uHP:HHY HHHǸ    FuHPHH   H/HHH讨    HUdH+%(   t襣UHH}HEH @TuHE   t       ]UHH}HE   ]UHHH}EHEHt@HEU􈐒       UHHH}EHEHPTt@HEU􈐓       UHH}HE   ]UHH   HhddH%(   HE1ǅxh   xHE    HJHxHMdHΉ?|| t&K< uHUdH։|| t|?  HEHHE}u>UHhH@HMHHHe uHhH@HHEHEHHHEH} u; ؉(?   d     Ǹ    ܜE} y^; ؉|   Hh@U։kA||    HhH@H#HhHUHPUHhP0UHhP4UHhP8UHhP<UHhP@UHhPPUHhPTHhƀ   HUHhH       HEH|>HUdH+%(   t4UHH}HE@<]UHHH}HE@0jt:        HEH@pUHHH}uHEHtj=9HEUP<HEHtHE@<HNHEP<    UHSH8H}EHEH  Ht<HEH   u*HEH} HHο       *A      HEH  HE׀} t	E    E   HEH  HtHEH HEHE      HǸ    HAE܃} yk8 ؉E} t	H H Eڶ HHUH}H5	 EIIǸ    ^@} tE        Eܾ    EE܉}    E׃t4}u.HEHUH5 HH¿       ?       } t	HH H@ HULEMH5 }I    ?} tEh    a`      HHEH  HEH  HuE#HEȋU  HEH  UP\    H]UHH@  HdH%(   HE1EEEEEfE  E    EEEEEfE  E    ǅ   Hx       H|H  t       H  AH`       HHHǅ`x   tDEH`HhHHHpHxHHHEHUH HHEHUHHHEHUH H(HEHUH0H8HEHUH@HHHEHPHH   Ht
        t)諳 HH Hƿ        :=HcHHEH IIH        y9HcHHEH IIH       S yG4  HHB Hq Hƿ        y<    HUdH+%(   t7UHHH}uHEH   Ht   7HE  tHEH  UH	/ Eƿ    . UHH   HxtdH%(   HE1Eh   EHE    HzHUHMtHΉ7E} t#3 uHUtH։%E} t8E蝱 HtH5 Hщ¿        $;       Hx@0tHx@0uE$EUHx@09ubUHx@49uQUHx@89u@UHx@<9u/UHx@@9uHUHxH   H9u       HUdH+%(   tSUHH H}HEH   HE} y@2 ؉E}u1HEH   H HHο       9       E? HHEH   H5 HH¿        9E   UHEHt8HEH   H HHο        y9E`UHEHEE} tE7HEƀ   HEH   H HHο       9    UHSHHH}HudH%(   HE1HE@\EE    HEH   H   HEH8HEHP`HEH@hHuH)HH=<<HƉHEH   H	o }t}u8HEH@hHUH)HH=<<HHEH   Hu       HEHP`HE@Huȹ    IEԃ} tL0 ؉EԋEԉA HHEH[HHi HHƿ        7Ev  }t}ucHE@誒Eԃ} tL/ ؉EԋEԉҭ HHEHHH2 HHƿ        O7E  HEHcHEHE@@%      HE@@%   t	E   E   HEHHEH@`UHuA    Aȹ   HHEH}uI. ؉EԋEԉ HHEH%HH HHƿ        6ECHEHUHP`0HEH@`Ht#HEH@`HUHHHEH@`        HUdH+%(   tH]UHH   H8H0Ј,dH%(   HE1H`H       H跔f)E)E)E)EfEHEH   HEHUH`HhHEHUHpHxHEHUHEHUHEHUHEHUHEHEH0H0HXHǅP    ǅL    H8    HtH0H@HPH0@(EHX@|H0@DEH0H   HEH8  EH8  t|   |H0H   HtOH0H   HLL tL  H0H   H   HEE    H0HCt:H0@XtH0@LxH0@LE|̀|H8H(  HtVH8H(  H蛐x<H8H(  H聐hH0@PlH0@TpHX [\   H0H@pH   H0H@pHt  LL tL  H0HHpH8   HHLL tBLK HH0H@H5 HH¿        2L{  H0H@pPH0P,H0@,xH0@,xHX !tC!   tqwxt+wnwisw_strPwHǅh    ǅl    ǅp    H0@P    H0@T    ǅp    H8H   H   , t)H8H@hH0H)HH=<<HHXDHHXD@HXHHX0H8H   HPWH`WH6 HH0@HHHXxHXHHXPHX L`HPMA8HH    lup   ( ؉LL HH0H@H5 HH¿        0ǅh    ǅl    ǅp    H0@P    H0@T    HXxHXHHXPHX L`HPMAKHHX XtjH0H@pHtZH8H   HtH0H@p@H0H@pH謟  H0H@pH	H0H@p    H yH2H0@9Hu    H0@H։-HUdH+%(   t UHH0H}HudH%(   HE1E    E      HEH@xUHHH HV  HEH@xUHHH HEHE@EHEH   HtbHEH@hHUH)HH=<<HEHEH@hHUH)HH=<<HHEH   Hi HEЋ@HUHu    fE} tb(& ؉EE^ HDEHEHxUHEH@H5 HQEIH¿        -HE   }HEHHUHEH@H5 AIȉH¿       -EEHEЋ   E9iHEH@xHqHEH@x    HEǀ           HUdH+%(   tUHH0H}HudH%(   HE1HEH   Ht
c  E      HEH@xUHHH H   HEH@xUHHH HEHEHLEHEЋ@HUHu    讲E} tap$ ؉EE覢 HDEHEH8UHEH@H5o HQEIH¿        ,HE   }HEHUHEH@H5x AIȉH¿       +EEHEЋ   E9HEH@xHHEH@x    HEǀ           HUdH+%(   tXUHH H}E    [HEHPhEHHi   HHEHE   t-HE@0u!HUHEHHE} yEEEHcHEH@pH9r    UHH H}HE@0utHE@<uiE} y+HEH@UH5Y H¿        *E5HEH@UH5v H¿       T*UHEP<    UHATSH0H}E      HEHPhEHi   HHEHEH轺t#HEȾ   HtHEƀ    HE   t)HEH@H HHο       ){  HEHE}   E HEH   HtHEHE} t)HEH@H HHο        7)9  } t;HE@y0HEH@H HHο        (E  HE   t/HEPHEH@H5 H¿       (  HMHEȺ    HHuE}   HEPHEH@H5v H¿       d(HEHt%HUHEHH;E} =  6  HE@0!(  HEXHEH   HtA   A   HEHyTHHEH   A    AD   HHUHB`HEH@`HuQ ؉EHEH@`    E HHEH@H5 HH¿        h'E  HEH  HtYHEH  HEH  HMHq`HMH  HHHHEH  H$HEHǀ      HE苀   t,HE@0t HUHEHHE}    HEH   H   HE   tuHE    HtE} t[E׃t}u	EE讜 HHEH   HEH@H5 IHH¿        $&)EUHEH@pH9       ED HHEH@H5s HH¿        %E&E    eE    HEHPhEHi   HЋ@x"HEHPhEHi   HЋ@EHEHPhEHi   H@EE;ErEH0[A\]UHH}HE <_tCHEH <_u4HEH <_u%HEH <_uHEH <_t       ]UHH H}HEHHEHEE'EHcHEHH[t
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EE;Ej    H]UHH   HhdH%(   HE1ǅp    HhX  t
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    v  x t/T u#HF Hƿ       &!    >  x tC ؉xxL HH; Hƿ         x  p|| y[    ؉xxݖ HpH5 Hщ¿        d x{  ǅt    HE        HHEH"HEE@   HE    HtHM|HΉ}xx tE ؉xx) HpH5r Hщ¿          EtHz HEHHu|l  HhH8  |H։# HEHEHxxx t=x胕 HpHEH5  IȉH¿           HhH`  HPHhHh  HhHP  HѺ    H> xx    HhHP  HhH`  HHHEHEHUHpHEPHE|PHEHdHHEHPHEH@Huǅx,HhH`  HPHhH`  }wx tHEH|bxHUdH+%(   t{UHHpH}HuUdH%(   HE1HE    HE    HEHEEEUHEHHEH} uH  HEHEH!HEHEHtHa  HEH:HEо      =HEH} uH&Z  HEHH  HtHEHEH8  HEH}H HUHuHEIA   HTE}    HE؋@t	HE   HEHH  Ht	HE   HEH%E}    E    qHEH8  HAHEHP  UHcHHHHHEHP  UHcHHHH}HuHEIHE} u*EEHcHEH`  H9uHE HEHEHHHUdH+%(   tcyUHH H}uHUMMHUuHEA    H_ UHH H}uHUMMHUuHEA    A    Hі UHH}HuHE]UHH}HuHUHEH;E]UHH0H}HuUHE@PHcHEH@H   HH.HEH} ugHE@PHcHHHHHHEHHEHE    HEU܉PHEHUHPHEHUHPHHE@PPHEPP    UHH}uE    HHEHHHEHcHHHHHHEHE uHE@9Eu
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   H`HXH(A    A       H \\ tH`H\EH`LH0<H@HhH MIHڇ HHUdH+%(   ttH]UHH   HhH`dH%(   HE1HE    E    HhH0  @du
      H` toH`    HHhHH  HhHH  H~E} t.E誌 HH Hƿ        9Ee  HCH&    HHr HEHEH]tHEH?Eh  HhH0  HXHEE    HEH HE  HEH@UHcHHЋ EEHEHhH(  H`HEHEHtE  HEPHEH5 H¿       <ǅ|    HEHHEP  HE t
>  HE EEHcЋEHcHhHHzHEH} u0M|HEH5 AȉH¿         HE@|  UHEH@ )ȉEEHcHEH@@H9r
  HEH@8UHcHHHEȋUHMHEHHlE} t=Et HHEH |H5F IȉH¿        i  HEH@pH   H   HhH(  LEH}|HuHEMIHE} t=E HHEH |H5 IȉH¿        a   HEH LEЋ|HMUHuMAHnw E} tDEt HHEH }|H5 IAH¿        f|HE@HEHE@|9HEPHE@HHEHEHHE@HH9EHhHH  HkHhHǀH      HEHtyǅ|    KHEH@|HcHHH HEHEH@HHEH@HEH} u݃||HcHEH@ H9rHEHK EHUdH+%(   toUHH@H}uUHMDELMHEHHHEH DEԋ}UH5j HQEAH¿       UHE    FHE HEPPHEPPHEf@  Eԍ@DwHE؉PHEE}~UHH0H}uUHMDELMHEHxHEH MUH5  IAȉH¿       HE HEPPHEPPHEf@  E䍐TwHEPUHH}HuUHE    ]HEH  HUHHЋ@9Eu:HEH  HUHHH H9EuHEH  HUHHЋ@HEHEH  H9Er]UHH@H}HuЉỦMHEH  HEHE   HEHHHEH  HUHH	HEH} u
   HEHUH  HEH  HUHHHEHHEH  HUHHẺBHEH  HUHHEȉBHEH  HPHEH      UHH}uHE苀   E+HEH   UHcHHЋ@U9rEm} yϸ]UHHĀH}HuHUdH%(   HE1E   HE@EHE@EE    uEE   HE    HE    UHMHEHHẼ} xE,  E    uЅt*UEH5j щ¿          E    uЅt*UEH5w щ¿          UċEH5 A    AЉ   "   Ẽ} yE~  HEH  Hu%HS Hƿ        #E<  UEЉHEH  H9s:UEHEH  H5A H¿        E  EHE@xHE@HcHEH@@H9r.HE@H: Hο        xE  HEH   HtHEPHEHfEHEH  EHHEE       EH    HEHH HHEЃ} xCHEH   UHcHHЋ H)EHEH   UHcHHЋ@HEHEH@ H)EиH;EsOEEEEH    HEHH HHc HHƿ        ^EzHEЉEHUHuE̹    uE} uLEEE;EẺfE} u'M̋UHuHEH"E} uEẺOEHUdH+%(   thUHH@H}HuE    @  HEHHHEHcHHHHHHEHEHP8HE@HHHHEHE 8            1  t    b     P  t{  >  HEHPhHE@HHi   HHEHEH   Ht$HEPPPHEPHEP'  HE   t$HEPPHEPHEP  HExHEPLEHMuHEMAHo  HEHPhHE@HHi   HHEHE@HE@HEHPHEPHEȋ  9u%HEH@HEH  HEHPHEH   Ht$HEP`PHEPHEP  HE   t$HEP PHEPHEP  HExHEPLEHMuHEMAHb  HEH   HE@HHHHEHE    HEH   Ht$HEP`PHEȋ   HEP9HEP PHEHPhHEȋ   HHi   HЋPHEPHEHPHE@4B  HE@8tBHE@ t6HEP0PHEP4HEPHEHPHE@0B  HEH@(HEPHEH@(H HHEHP  HEH   HE@HHHHEHEP PHE@ t#HEP4HEPHEP<HEfP)  HExHEPLEHMuHEMAHb   HE@<@   HEH UH5o H¿           HUHMHEHHtE܃} y4HEHHEH UH5A AȉH¿        E|HEP PHEU܉PHEf@  <HEHEH UH5/ AȉH¿        j EHE@P9E    UHH   H}HuHUHMLxLpHE    HE    E    HEH HE-  HEH@UHcHHЋ EEHEHPEHH9  E    HEHHEnHEȋ EUHEH@ H9r@UHEHH HEH@(HH9sGH} uHEHEHE@HEHHEEHE@HEHEЋ@U9rH} u
v  Hx HE@HHEHEH+EHHEHHEHEH HUHHZHEH} u
  HEHUHHE@HE    HHxHEH+EHHUHEHHEHHHaHEH@0HEH@ )ЉEHUHEHHEHUHEHHE+HEHEHE EHEHE@HEHEH;ErHEPHp    >HEPHEЋ@HHEHEHHE@HH9EUHH0H}HuHUHEH0  HtHE   Ht
    %  HEH;EtHEH   H   HEL   HEH   HEH   HEH0  HPHuHEMIHE}    }t8E&x HHEH H5 HH¿        Ev  HEH   Ht+HEH H HHο        pE;  HEH H HHο        EHEH;EtHEH   Hu
       HEL   HEH   HEH   HEH0  HP8HuHEMIHE}    }t5Ew HHEH H5m HH¿         E`HEH   Ht(HEH Hu HHο        Z E(HEH H} HHο        2     UHH}HuHEH HEHEHEHE@HH9Eu    HE@HH9Es   ]UHHH}HuHE@Pu    -HE@PHcHEHpHHkHEIȹ   HUHH H}HuHEPPHE@PЉEHEH;Eu
      EHcHEH@H   HHHEH} u} t
   HE@PtQHE@PHcHHHHHHEHHHHE@PHcHHHHHHEHHHHHE@PESEHcHHHHHHEHЋ@HEH@0EHcHHHHHHEHЉʉPEE;E|HEHUHPHHEUPP    UHH0H}HuHE   HE؋   EEHcHEH   HUHHHEH} utHEHUH   HEHH HEH   UHcHHЉʉHEHH0HEH   UHcHHЉʉPHE؋   PHE؉       UHH@H}HuHUHEHP@HEHP0HEHP@HEH@@HHEHEH@8HM   HHHEH} u-HEH H HHο           HEHUHP8HEHUHP@HEH@@H    HEH@8HMHq8HMHI0HHHHqHEHHEHP@HEH H5, IHH¿       >HUHEHHE} tEVHUHEHHE} t5ELr HHEH H5 HH¿        E    UHHPH}HuHUHUHMHEHHEԃ} tE  HE      HEHP8HEHH0HEHHHHEHEHtHEHY   HUHEHHDHEH} tHE Z  H} tPHE tEHE t:HEHEH HUH5 AHH¿        [   H} tHHE u"HE@HE@HHHHEHEPHE@HEdHEHot1HEH HUH5 HH¿        "[  HEHP HEHHE@HHHHEHEȋ  HcHUHEHHoHEH} u-HEH H HHο        [  HEH@0HuPHUHMHEHH!Eԃ} tE   HUHMHEHHEԃ} tE   HEHP8HEHH0HEHHHHEHEH@0HEH@0HE)BHEPHEHH0HEL HExHEH HUH5ܼ HQMAHH¿       HHEHEH@(H9E    UHH H}HuE    HHEHPXEHHi   HHEHUHEHHuHEH@0    EEHcHEH@`H9rHUHMHEHH2E} tE    UHH H}E    FHEHPXEHHi   HHEHEH@HHHEH@H    HE@P    EEHcHEH@`H9rUHH}HuHEHEHEHEHEPHE@9t HEPHE@9}:   3HEHE 9tHEHE 9s       ]UHH H}E    VHEHPXEHHi   HHEHE@Pt+HE@PHcHEH@HH!HѺ   HEEHcHEH@`H9rUHHPH}HuH HEHEHRHEHEH(  HtHE   Hȹt
    6  HEH(  H詴EE     UHEH(  HI HEHEH[  HEH   HEHEH(  HEVHEHUHMHEHHp  HEPHEH(  H轹 HEHEH*uHEHt-HEH H HHο          HEHEH(  HUHHEH HH  HE   xHEǀ     HEHEHEHt-HEH H: HHο        O}  E       HEHPXEHHi   HHEHUHEHH辘   HEHHEHH   HE@~uHE@t4HEHHEH H5ظ HH¿           HE   x4HEHHEH H5 HH¿        [   HEUЉ   EEHcHEH@`H9HE   y7HEH HUH5ɸ HH¿        EE;E    UHH@H}HuHU؉MDELMȋMHE    Ho5HEHEHp  HEPHEH{HEHEHuHEHtlHE   tHE   uNHEHEHRHtHEH¸ HEH1 HEHHu
      HEHHE    H4HEHEHSt
   b  HEHEHMRHtHEH< HEHEHt!HUHEHHtu
      HE         t}   t
t9   HEH(t~H HEHHud      HEHtMH HEHHu3   iHEH`tHE@u   F
HEH H}ȋMHUH5/ IAHH¿        6    UHHpH}uHUUHEH茴 HEHEPHEHs HEHE EHEHgEHE@EHE@EHEH<E̋UHEHEЃ} y
  E       UHEH HEHEHNUHcHHHEHE EHE@H HEHHУE܃} tE   UHEH腳 HEHEHUHcHHHEUHEEE;EJUHEH0MHEHknEԃ} y!UHEH HEUHEEUHH   HxHpHE    H| HEHxH(  HEE    HxH0  HtHpH   Hu
      Hx   H覱t
      E    IEHHHH_ Hp   9uEHHHH^ HHEEEvH} u
    3  Hp      H薋HEH} u
  E    MHpH   Hp   EHHEHEHEHH    HEHЉʉEHp   U9rE   HEH脫EO  UHEЉHKvHEHEHD  HEHEЉHLMHHEHH  HE@EUHEЉHΰ HEHEH;  HEH  HEPHEЉH艰 HEH} x  HEHa  HE    E    QEHH    HEHЋHE@9u,HpH   Hp   EHHEEHp   U9rH}   HEHEHEHh E}   E;E  HEHUHcHHHEHEHEЉHKHtHEH HEHE@AH}MHUHpHEIH3  HEPE9u6HpMHEЉHRE} yEE  UHEP} uGHMHEк    HHEUHEЉHoE} x} yE   HE@ǋUHuHEЉщHE} yE   HEPHEЉHQ HEHEPHEЉH8 HEHEHUHcHHHEUHEP
EE;EHEHu    HEHbEUHSHhH}HuHEH0  HtVHUHEHHE} t.EI_ HH  Hƿ        E  HEHHE     HE   HZt}HEHPhHE  HHi   HHEHEHHÿ   HEHEH  HEHHHMȺ    HHHEHH)HHEH  HE       HEHPXHEHi   HHEHE    ]HEHHHHUHHHHHHEHEHP8HE@HHHHEHE uHEP@PHEHEЋ@PHH9ErHEHEH@`H9EYHE    Z  HEHPXHEHi   HHEHUHEHH  HE@|  HUHEHH~E} t8EF] HHEH H5N HH¿        E  HUHEHHQE} tE  HEЋ      HEHPXHEЋ   HHi   HHEHEH@0HuTHUHMHEHHE} tEZ  HUHMHEHHZE} tE2  HEHEH@`H9EHE       HEHPXHEHi   HHEHUHEHHl   HE@|   HUHEHHE} t5E[ HHEH H5 HH¿        REqHUHEHHE} t9E|[ HHEH H5 HH¿        E HEHEH@`H9E    H]UHSH   HXHPHHǅl   ǅp   HE    HE    HE    HE    HX  tHXH(  Hu
  HX  HXH(  HmHEH} u
  HPH@ HPHZ8    Htǅd    ^  dHcHHHHgHEH} u+dHի Hο        _$  HEH@H HHXHH<gHEH} u:HEH@H HdH5 Hщ¿        5_  HE HXHHbHtHEH HEHEHEH8HEHHHEH@H IdH5P uRIILщ¿       Hǅh       HXHPhhHHi   HHEHEPHX   9ulHEHkHHE@HHHHHHHEHE@HEH H9r,HEHlHHHEHHE@ȉH9s)hhHcHXH@pH96hHcHXH@pH9u9HEHHUdH5q IHщ¿          HE@0J
bHE@0cb tH\ HEHS HEb    HE@HX   9t/HUdH5 Hщ¿        [m  HE@0uEHE@4t9HEHPdH5 A   Hщ¿          HUHXHHaHEH}   HUdH5 Hщ¿        ?  c    HUHXHHpHEH} u/HUdH5ܩ Hщ¿        k  HEHPHE@H9u7HEH@ H    HEH@H9uHUHXHH@t9HUdH5 Hщ¿        d[    HEHXH(  HhHEHEȋHHXH(      H!HEHEHfu
~  HEHHHEHZHHHHHHHEHE؋HXH(  HuHEHw HEHHt
  HEHHEЉHxHEHHE@H)xH9s
  HEH HE@)+xxlx    щȅt
j  lx    xHE   9x   x|pHcЋ|HcHEH@xHHHEH} u
   HEHUHPxHE   |)pHHUHJxHU   HcHHH¾    H;HE|   b tHEHEHUHRxxHHHHEHPH}xdH5 HuIAHщ¿       Hdd;t    H]UHH@H}E    ?  HEH   EHcHHHHHHEHE   HEH@HEHEH@HEHE@,EHE@	u} xEHcHEH   H9r(Hj   Hƿ        \   HEH   EHcHHHHHȋ uHUHMHEHHZc  EEHEȋ   9EuHUHMHEHHeEHUHMHEHHčE} tE0EEHcHEH   H9HEH    UHH}HuHE u[HE %   =   uEHE u4HE@u%HE@uHE@HE       ]UHH0H}HudH%(   HE1HEH@8HEHEH   Ht
       E       HUHEHHucEqwpsWrwO%HEؾ   H{t8HE@   +HEؾ   HVtHE@-   	EHEEHcHEH@@H9Y    HUdH+%(   t47UHH@H}HuHUdH%(   HE1HEȉEEt'HEH@p   H谜tHE@    EtHEЋ@HEЉPHE؋   uEtHEЋ@ HEЉPE t2HEH@p   H6tHEǀ   0   HE@0   E   HE؋      E    E    HEH@/   H;HEH} u*HEH Hʢ HHο        fHEHMHUHuHEHgj  E} tE;EHE؉   EHE؉   EHEЉP(EHEЉP     HUdH+%(   t\5UHH  HHHLDHEHdH%(   HE1H x       H5HU       HHHEx   HEHUH HHEHUHHHEHUH H(HEHUH0H8HEHUH@HHHEHUHPHXHEHUH`HhHEHpHǅ    Hǅ    Hǅ    ƅH@hH   tt=}HHPHH H5 HH¿          H   u0HH H	 HHο        ~  H t	 u
  H    HtHH HH   $H   (H    H   H   HH(  H   HH(  Hc1   H   H2   HH(  H)1HH   H8H   DH   @HH   HHH   TH   PXH   HH  H0H  lH  t   HH@H   HH@H@(H   HH@L@(HH@HPH HHHAЉ yANI HHH H5Þ HH¿          HH@8HHH@@HH   Hu   HH@XHH)HH{{HǋLcHHH   HH   LHWH WH HH     #     HH@XHt0HH@XHHH@`Hƅ    HHp  Ht6HHp  HHHx  Hƅ    Hǅ HHHHHH9HCHHHHH'HH uǅ  HHH  ƅHH`H\XHcH   L HHHMIp c   t6 t-HH HH5L HH¿       H      H	   H訓   ǅ       HH@pHPhHHi   HHH@\uiHH    ΉetH E HHHPHH H5 IHH¿        :HcHH@pH9;Hǅ       uǅ    t uH ؉HHHHH+   D HHH H5 HH¿        QP tGH t=H t/HH HH5) HH¿         tHHHUdH+%(   t+UHH}HuHEH;Eu    4HEHHEHmHEHH;ErHEH <
uHE]UHH@H}HuHUHMLELMHUHEHHUHEHHH)HEHEH5HEHEH;E   HEH9E   HUHEHHUHEHH9r6HUHEHHUHEHH)HHEH)HHEHE    /HEH+EHUH+UH9sHEH+EHHEH+EHHEHUHEH4HUHEHHEHH}HUHMHEHH6UHH  HHHHLLHEHxdH%(   HE1HH HHHǸ    *%  HH莱HH    HH@pH(  HH HHH)     HH   H5 =   v	H Hy~ HH5ߗ HIIȉH       n[HxH+IHHHHHIH)HEdH+%(   tb(UHH   HHH@H8H0L(L HEHdH%(   HE1HHH@pH`H\HXH5. H(HǸ    )   \-@Dw\\   \HcH`H@pH9   H`HPh\HHi   HHhHhHHXH5 HpIȉH   HǸ    YHH+(IHpH(H0H8H@IHHEdH+%(   t&UHH   HHH@H8H0L(L HEHdH%(   HE1HHH@pH`H\HXH5 H(HǸ    '   \-Tw\\   H`   \9   H`H   \HcHHHhHhHHXH5 HpIȉH   HǸ    VXHH+(IHpH(H0H8H@IHHEdH+%(   tM%UHHPH}HuHUHE
   H}   HEHDHHEHEHPHEHHEE      HUHEHH-HEH}   HĔ HE   HH`uXHUHEHHHEH}   LEH}HMHUHuHEHuMIH:H  Hm HE   HHuXHUHEHHuHEH}    LEH}HMHUHuHEHuMIHH   H HE   HHruXHUHEHHHEH} t9LEH}HMHUHuHEHuMIHH(EHEHE؋EHH;E^UHHPH}dH%(   HE1HEH@pHEE      HEHHHEHcHHHHHHEHEH   HEЋ@HHHHEHEЋ   O  t   <  HE؋ 0  HE؋@HEH(  H#NHt	E   E   HEЋxHE؋@8HE@!HEHpHEH   DEHWEA   Ha H   HEЋHHE@!HEHpHEH   HQA   A        H HWHEЋ@EHEH@@EHEH@@EHEH@@EHEH   HUHHS EHE@P9E@    HUdH+%(   t3!UHH0H}؉uHE    (  HEHPXHEHi   HHEHUHEHHg   HE@|t(HEH H HHο          HEPhE	HEPhHEH   HtHEH3HEHHxHE؋xPHEL@HEH@@AHEHP8HuHEHQADHHE} t6E8 HHEH H5 HH¿        E)HEHEH@`H9EHEH    UHH0H}HE    @HEHPXHEHi   HHEHUHEHH4E} tEHEHEH@`H9Er    UHH H}HuHE    HKHE	  HEH@HD  HUHBHEH@Hu0HEHPHEH H5 HH¿          HEH@PHE   HEH@PHE   HEH@H@ HtbHEH@HH HEH@HPHEHHщE} y5E6 HHEH H5/ HH¿        LE'HUHEHHJHEH}     UHHpH}HuHUHMLEH} tH} uH"     蓾u=HEHuH H HHο        西H`ױ]  H} t7HEHH HEX   HwtH虱  H} tHEH Hv
HEH@    HtHEH} t*HEHEHEHV HHο        HEHd HHο       پH} tHEH H?vHEH@8HEHE    H} tHEH HGvHEH@@HEHE    H} tHEH HKvHE@HEE    H;EsH腰  H} tH} uHf  H} tHEH HWvHEH@PHEHE    H} uH HXHEH} t%HEHuH=  vH|  HMHUHuHEHzHEHEHt	HEG  HEHUHp  HEHUHx  HEỦ  H} t6HEHNjHHEH  HEH  HuE  H} tHEH H7vHEH@0HEHE    H} tVHEHtH=  vEu  HEHiHHEH@  HEH@  HuE?  H} tHEH H/vHEH@(HEHE    H} t6HEH`iHHEH   HEH   HuE   HEHdEȋEȅtEHEH.BEȋEȅtEHEHTEȋEȅtEHEH3EȋEȅtEHUHEHH$EȋEȅtEHUHEHH EȋEȅtEHEHEȃ} uHEHHEHEHbEHHuUHHH}HuH} u*HUHEIй            HHUHHH}HE    HZUHHpH}HuHUdH%(   HE1H} tH} ulVHUHMH5 HEIHH@   HǸ    JHuHMHUHEIHƿ    H2HUdH+%(   tUHH H}H} u蚵/  HE       E    HEHPhHEHi   HЋ@x#HEHPhHEHi   HЋ@BEHEHPhHEHi   H@HEHPhHEHi   HH@hHtHHEHPhHEHi   HH@hH@HTHEHPhHEHi   HH@hH@    HEHEH@pH9EHE    #HEHPXHEHi   HHcHEHEH@`H9Erϸ    UHH H}HE    HXUHEXHEHFIu-HE   H)|tHE@@HEP@HUHEHHTHEH} u    UHH0  HHdH%(   HE1ǅ    HVK H HHݱHH uCׯ ؉. HHn Hƿ        薷   H HHH5` HIHǸ    ~uHHxeuvt-H& Hο        ǅDHHH LHAЉ u5HHHUdH+%(   tUHH@H}؉HUHMEHEHEH HEHHpHE}du*H} t#HEH+EȉHMHEHHHEHUHEHHHEH} tHE t
       HE@HEH(  Ho?HEHEHt
       HE@ tDHEH@(H9Et6HEHP(HMHEH5 IHH¿        gLHE@ t8HE@ HEHUHP(HUHEH5 HH¿           UHHH}HEHfHHUHHPH}HuЉHMLEfEHEH8  HEHE    UHMHEHH{E}   HEHVE} tE   E    KHEHP  UHcHHHEHEH HEUHMHEHHӅ E}uEEHcHEH`  H9r} HEHUHHEHUHEUHATSHpH}HudH%(   HE1HE    HE    HEHpHMHUHEIHѺ   HE} yH}uHE@!t
      HEH@H  HHο        5E  HE@8EUHEH<HEHEHEH`HEHEHHEHUHHEȋMHUHEH(  uHIE}    HEH(  UH5<HEHEЋHEH(  HV`HEHEȋHEH>`HEHEHkHDeHEHXHHEH@H}؋UH5 HuSATIIȉH¿         H tHE@ HEHt	HE@    HUB0HEUP4HEHHHEH@H}UH5 IIȉH¿       膱    HUdH+%(   t[He[A\]UHH@H}HudH%(   HE1HE    HE    HE@8EHEH@HuHEH@HMHUH}IHѺ   H	Eԃ} yH}uHE@!t
    {  HEH@HU HHο        誰EO  UHEH/:HEHE@E؋MHUuHEH(  HE܃} dHE@!t
      HEHt
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l HUHR}؋MH5 AI          HEH  HE@   HEH  H=  u4HEPHEH@H5 H¿        蠯C  HEH  HuHEHǀ     HEH  HPHEH  HEH  HѺ   H` E܃} tE   HEH  HEPHUHEH  HEH  HpHMH  HHBHE@ HEUԉP4HEHtHE@    HEfP<HEHt	HE@    HUB0HEHt
HEH@H\j HUHRMH5 AH       X    HUdH+%(   t-UHH0H}E       HEH   UHcHHHEHE    HE@8   HEH   Ht HE@ HE@0    HE@4    lHE@HEH(  H77HEHEHͣtHUHEHHEHUHEHHE} tEEHE؋   9E    UHH@H}HuE E E HE    HEȋ   u
    y  HEȋ   x&HEHPhHEȋ   HHi   HH@`HEE    U  HEH   UHcHHHEHE uHE@8t	E  E  HE   HE@4HcHEHHEHE    HEH@Hv>    HH輈u	E  HEH@H~ HH%uDgo HEH}   HEH@H~ HHο        蹫;  HEH@H~ HHÝuHEȾ   H9oHE   HEH@H~ HH舝uHEȾ   HnHE`HEH@Ht~    HH軇uHE@!t.HEH@HI~ HHο        h  HUHMHEHHE܃} tE@  HUHEH@H5/~ HH¿       茪.HEH@H9~ HHο        f  EHEȋ   9E}    H}    HUHMHEHHE܃} t
  E E    @HEH   UHcHHHEHE uHE@ tEEHEȋ   9E|} t&HUHEHH0E܃} t

  } tHEHZE܃} t
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   E       HEH   UHcHHHEHE@ t:HE@!t+HEH@H| HHο        ʨOHE@ t$HEH@H| HHο       萨EHEȋ   9EQ    UHH@H}HEH@hHEHEP HEH H(  H1HEE    gHEH UHHH HEH} tCHEHXEHEHPHEH@MHHȋ HHEEHcHEHEHEHA9ErUHH H}E    VHEHPhEHHi   HHEHEHu HE   uHEHEEHcHEH@pH9r    UHH H}E    oHEHPhEHHi   H   tIHEHPhEHHi   H   t$HEHPhEHHi   Hо    HܠEEHcHEH@pH9zUHH H}HEH  HzHEHǀ      E    mHEHP  UHcHHЋ@.HEHP  UHcHHH H}HEHP  UHcHHH@HEEHcHEH`  H9yHEHǀ`      HEHP  HHEHǀP      HEH8  Hw}HEHǀ8      UHH H}HuHE@Tt*HEHy HHο        (  HEHcEEtEHEHeEEtEHE    HeEEtEHEH   HEHHEEtEHEHEEtEHEHEEEtEHEH3EEtE&HEH@  HuHEHUHHEEtEHEHoEEtEHEHyEEtEHEHE} t(HEHHEHHE@T   EHE@T       UHH0H}uHUH} u  HE@Tv/HEHw HHο        >ݞ  HEH   Ht,HEH@pHEH@`HEH   uH BHEHt/HEHw HHο        ]_T  HE@Tu+HUHEHH,E} tE)  UHEH'EEtEHEHvEEtEHEHEHEH   HtZHEH(  HtHEH(  H>} u,HEH@pHEH@`HEH   H胠 EHEH<HE@T   } tHHEH|HEHHEH  Hv Hƿ        nE    UHHH}HE    HܜUHHH}HE        HtUHH0H}E    HEHMHEH} uHEH&FHEHE  HUt踘 t謘 ؉EHEHz} t-E HHEH5u HH¿        XEUHH   HXdH%(   HE1ǅl    HX u
   HXHMHpHp u
   HpH5EHxHUHxHHtC迗  HHxH5t HH¿        肟苗 ؉lHpHyl u;HUJH9t-HXHt HHο        *ǅllHUdH+%(   tUHH H}HuHE@xy2HEH Ht HHο        a   HEHE} tE=   HEH0E} tE   HE@xHUH։贚tO[ ؉EE HHEH HUH5%t IHH¿        E讙,HEH HUH5t HH¿       ܝ    UHH H}HuHE@xy/HEH Hs HHο        蓝2tHEH(E} tESHEHE} tZ ؉,HEH HUH5s HH¿           UHSH(H}HuH} u(Hs Hƿ        ܜ{  HE؋@y3HEH@Hs HHο        螜=  HEH   H   H} tjHEH   HEHH舎tLHEH   HEHEHHMHWs IHHƿ        踗  HE      HEH   HEH^EHH<s HHƿ             H} u7HEH"EHH@s Hƿ        舛'n  HE   t7HEHDHH*s Hƿ        B(  HEH5HHHEH   HEH   Hu ؉E   HEH   HE} tE{   HEH   HgE} tEP   HEH   HE؋@H։t苒 ؉E9HEƀ   HEH   HNr HHο       B    0E HH=r Hƿ        E贕H]UHSH(H}HuH} u(Hp Hƿ        ЙoX  HEH   H   H} tjHEH   HEHH躋tLHEH   HEHBHHMHp IHHƿ        K   HEH   HE>H} u7HEHBHHDq Hƿ        蛔   HEHE} tEwcHEH^E} t ؉P<HEƀ    HEHBHHEH5p H       n    H]UHH H}HuHE    H} t)HEHBEHEH} u2 ؉'HEH   H"rHEHUH       UHH}HEH   ]UHH}HE   ]UHH}HE <.uHE _HEHE uސ]UHH   H$ H@HHdH%(   HE1H u  H@Tu(Ho Hƿ        貒  H    H3H   Hǅ    H      H t[HH%@HHH   H u\HHHHHH   Ht0HHHHU t	cHHHH2HH     aHH   HtH    HHHHH!HH u*HUdH+%(   t[UHH   H$ H@HHdH%(   HE1H uː   H    H1H   Hǅ    H tmHHW>HHH   H' tH   HHHHHH   Ht7HHHH荎 t܏4HHHH0HH     HUdH+%(   tUHH   H$ H0HHdH%(   HE1H uGj  H@Tw(H	l Hƿ        q3  H    HH|HHHH   H u`HHHHVq u;HHHHNHH v       HEHHHH   HuHHHHHHHH{HH u؍HUdH+%(   t	UHH   H$ H0HHdH%(   HE1H uy   H    H5H   HHHH   H tjHHHH t܌3HHHHHH X    HUdH+%(   tUHH H}HuHUHEHHwE} tEW@HUHEHHwE} tHUHEHH;E    UHH H}HuHUHEHHhE} tEً-HUHEHHE} tE豋    UHH H}HEH@pHt,HEH@pHHEH@pHiHEH@p    HEH@xHiHEH@x    HEǀ       HEH@`Ht=HEHP`HEH H  H9t"HEHHHEH@`HH xHEH@`    HEH@hH   HEH@hH@H/iHEH@hH@    HEH@hH HiHEH@hH     HEH@hH@HhHEH@hH@    HEH@hHhHEH@h    HEH@HhHEH@    HEH@HhHEH@    HEH   HrhHEHǀ       HE@x.E    HE@xHE@EHE@UHH H}HEHg  HEHZHEH  H HEHǀ      HEH   H; HEHHEHzHEH(  HweHEH8  HdeHEH0  H(HE    #HEHPhHEHi   HH,HEHEH@pH9ErHEH@  H#gHEHǀ@      HEH   HgHEHǀ       HE       HEH   HUHHH@HfHEH   HUHHH@    HEH   HUHHH@HfHEH   HUHHH@    HEHE苀   HH9EeHEH   H7fHEHǀ       HEǀ       HEH@hH
fHEH@h    HEH@p    HEH@XHtHHEH@`Ht;HE    #HEHPXHEHi   HH\HEHEH@`H9ErHEH@XHeHEH@X    HEH  HneHEHǀ      HEH  HLeHEHǀ      HE苀  ~HE苀  ~HEH  HeHEHǀ      HEH  HdHEHǀ      HEHǀ      HE    %HEH  HUHHЋ@HEHEH  H9ErHEH  HxdHEHǀ      HEH]dUHHH}H} tHE
UHH}H} t	HE@P    ]UHH}HE  tHE  ]UHH}H} tHEH(      ]UHHH}HEH(  HtHEH(  H5UHHH}uHE@TvބHEUPP    UHH H}HuH} u覄   H} t2HEHHa HE!   Hۃtji     &HEH} uDCHEHUHHEH谯HUB(HEHUH       UHH0H}HuЈEHEH@`HEH} u
       H} u5} tHEH@X   HEH@XHUHi   H   H   HEH@pH9Et+H` Hƿ        軇        tHEH@XHUH)HH{{HH} t   HHHEHEH@`HUH9sH} y    HEHPXHEHi   HUHH H}HuHEHEHMHE   HHHEH} tHUHEHH+uHEUHH H}HuHEHEHMHE    HHOHEH} tHUHEHH8+uHEUHH}uUHE   ]UHH}HEH ]UHH}HEH@]UHH}HE@|]UHHH}EHEH@p@Tv蕁HEUP|    UHH}HE@}]UHH}EHEUP}]UHH}HEH@8]UHH}HEH@@]UHH0H}HuHUHEH@p@Tv   HEH@8HMغ   HH~HEH} u6H} t/HEH HG HHο        莀<HEH    HMHEHHZHEHUHP8HEHUHP@    UHHH}H} u-HE@xyHE@xUHH}HE   ]UHHH}uHEH@p@TvHHE   9Eu    2HEU􉐀   HEHPH H9tHEH@        UHH}HE   ]UHHH}uHEH@p@Tv5HEU􉐄       UHH}HE   ]UHHH}uHEH@p@Tv~HEU       UHH}HE@h]UHHH}uHEH@p@Tv~HEUPh    UHH}HuHEHP`HEHHEH@X]UHH H}HuHUH} tH} u~WHEH@`H9s}9HEH@p@Tv}HEHUHPXHEHUHP`    UHHH}HE   t}HEH   UHH}HE   ]UHHH}HE   t}HEH   UHH}HE   ]UHH0H}uUHMH} t5HEHH_ HEؾ(   H;|t|    =u|  H} tbH HHH} 8   HH{zHEH} uk|  HEHH HA H2 Hk8HHE%v t+|V  H$ HEH} tHEHm-H    HEHH} tHEH Hu{  HEUPHEUPH} tHEH Hv
HEH@    HUHBH} tHEH Hv
HEH@    HUHB H} tHEH Hv
HEH@    HUHB(H} tHEH H'v
HEH@     HUHB0P G A HEPH} tHЎ HHŎ  HE@UHSH(}܃} z  ߎ t5 9Eu*H 8       H      P  E    HF EHHk8HЋ@9EtEEHcH H9rEHcH H9uz   H EHHk8HH HbXEeH͍ EHHk8HH MHcHk8H8HH
HZHHXHJHZHHHXHJ HZ(HH HX(HR0HP0EEHcHZ H9rHN HHC H< H= 8   HH;wHEH} uH HuHEH     H]UHH H}HuHEH He5HEHEH HUHH </u@HEH H95HHEHHEHHYu
             HEH HUHH <+u\HmHEHHUHEHHPYt    MHUHEH tHUHEH </u   "    HEHHEHHnUHH H}Hϋ EE    8Hċ EHHk8HHEHUHEHHtHEuEE;E|Ei   E    8EHHk8H HHEHUHEHHQtHE%EE;E| t	HA     UHSH8EE   EHHHEH} u
      HE  E       EHHk8HZ HHE} t,HEHP(H̡H9   HEH@H   HEH3HËEHHk8H HH2HHUHcH9sHEHT    XHEH2HHEHf   EHHk8H HHEHHsEE؃hHEH]UHH0H}HuHUH} uu   HEHHEH} t!HEPHEHEPHE؉    kHEHW HHο       y    +HEH} t,HEHW HHο       yHEHSuUH}}:v    EH    H֔ H]UH}}v    EH    H H]UH}}"v    EH    H֖ H]UH}} v    EH    HƗ H]UHH(H}uHUHE    pHEHPhHEHi   HHEHEHu=HE@9Eu2HEH@ H9Er$HEH@ HUH)HE@8H9sHEHEHEH@pH9Er    UHHĀH}HuHUHEH(  HEHEH@ HUHz8    HEE       EHcHEHHHEH} u(EHU Hο        w_  HEH@H HHEHH$HEH} u2HEH@H HHU Hƿ        %w_  HEЋ HEHH{HtHEH HEHEHHE@,HEHHEH} u-HEH HuU HHο        v  HEH HEH@ )ЉEHE@EHEH@hHEHEЋ8HEHH HEHHEH@IHEH@H IHEH@DEH5 U uWQREMLH¿       vH }  v;HEHHEH@MH5QU AHH¿        u[,  HEH@Ht6HEHPHEH@H5hU HH¿        }u_  HEH@HEHEP HEHHEE    HEH褀HEH} u0HEH@UH54U H¿        uk  HEHmHUH)HHHEHEHEH"HEHEHHE    HHu2HEH@HUH5T HH¿        qt   UMHEHH%HEH} u7HEH@HMUH5T IȉH¿        t   HE   t2HEHHEH@H5T HH¿        sBHEH UHHHEHHEHPEHHEHEE;E    UH}HuHU}+t:}+wh}tH}w\}t}tNHEHT HHE    MHEHrT HHE    3HEHaT HHE    HEHm& HHE    ]UHH   HXHPHHDdH%(   HE1HHHPH5 HpIHH   HǸ    ll xlvDHpHXHH8HUdH+%(   tUHH@H}HuЉUdH%(   HE1HUHMEHΉ`EHuHUHEHHUdH+%(   tUHH H}uRHEHEHE} t%HR Hƿ        rqEmUUHMHEHH.E}  HEHR HHο        'qHEHIElUHH  HdH%(   HE1ǅ     H    HH HHΉ(( t< HH5R Hщ¿        Zp  ǅEuHR Hƿ        %p   E    ] HHH# t0. HEH5Q Hщ¿        obHH   HH6HHG %HHQ HHο        WoHUdH+%(   t(UHH`H}HuUHMLEE    HE    HE:   HUHEH} tHEHEHEH+EEHEH} t EHcH* HEHHQKu^H} tHEHEHUH8  UHHcE} ~HE     HEU       }tE   HEHLE} tE   E       HEHP  UHcHHHEH} t!EHcHEH@HMHHJuWH} tHEHEHUH
UHHE} ~HEPHEHEU    2}tE'EEHcHEH`  H9CUHH0H}HuHUHMHE苀   EHE苀   EE    HE苀   t
}    } u-HEH HpO HHο        l@  HEH@p  MHEHE} yDE HHEH H}UH5?O IIH¿        wlE   HE     HEЋU       HEH@pH   Ht7HEH@pH   UHMHHGz HE     HE    %HEH@pH}HM؋UHuIHE} t<E' HHEH HUH5N IHH¿        kE    UHH H}HuH} ug   HEHHEH} umHEHN HHο       8k   HEH} t,HEHN HHο       kHEHEfNHEHP(HH9tvf.HEH@HuZfHEPHE    UHHH}H} u#f!HEH$tHE@UHHH}HE@\u%HEH@H HHM\t   6HE@\u%HEH@H] HH\t       UHHH}H} u    "HEH]t
HEH@HEH@UHH}HE@0]UHHH}uHEH#teHEUP0    UHH}HE@@]UHHH}uHEH\#tdHEUP@    UHH}HEH   ]UHHH}HuHEH#tRdHEHUH       UHH}HE@D]UHHH}uHEH"tcHEUPD    UHH}HE@4]UHHH}uHEHS"tcHEUP4    UHH}HE@8]UHHPH}uHEH HHEH} u
  HEHHEЉH, HEHEH]t2HEHHHK Hƿ        @gW  HEH[E} u2HEHHHK Hƿ        f  HEH_HEHcHHHHHHHEHEHEЉH0+ HEHEHHEк    HoHEHEH[t2HEHHHJ Hƿ        Nfe  HEH]HEHEHEЉHEă} ~"HE@U)uĉȺ    щȅt:HEHgHMEH5gJ Aȉ        e   HE@U)uĉȺ    EHE HE@ƋUHEЉщH'Ẽ} yE   HEPTHEЉH) HEHEH[^HEHcHHHHHHHEHEHEЉH) HEHE؋UPHE@U)HEPUHEP    UHSH8H}ȉuHEHtX`4  HEH@`H  HEȋ@0t,`  HEHHEHEȋP<Eĉ։]HEHUHMHEHH,E܃} tDE܉ HHEHHHI HHƿ        cE܉_}UHEȉHE܃} tT}tNE܉ HHEH8HHH HHƿ        cHE@T    HE@P    HEȋUĉP8    H]UHH}H} t	HE@P    ]UHH}H} t	HE@T    ]UHH0H}HuHUHEHQt^   HEH@`HtHE@\uy^cHE@0!uHEH H  HEHE@8HEHEH;Et6^ HEH@`HUHMHHn8    UHHH}HuHEHqt%H} tHE@8HEHHEH@hH@OHEH@`Hu    ;HE@0!uHEH H  HEHHE@8HEHHEH@`UHH}HE@\]UHH}HE@(]UHHH}uHEHt]UHEP(    UHHH}uHE@0t%HF Hƿ        a\yHE@,t%HF Hƿ        `\HHEH@pHt,HEH@pHHEH@pH:HEH@p    HEUP,    UHHH}HuHEHt%HKF Hƿ        [`[MHEHHEH@pH9t%HRF Hƿ        "`[HEHUH       UHH}HEH   ]UHH@H}HuЉUH} tHEH@hHuW           HEH@hHEHEHPhHEH@pHi   HHEHEH;Er
HEH;Er2He HE Hƿ        I_RW        eHEH@hHUH)HH=<<HHEHHHEHEH@pHUH9sH} y    HEHPhHEHi   HUHHH}HuH} uH} t
HEH@hHMHE   HHUHHH}HuH} u=H} t6HEH@pHu    :HEHPhHEH@pHi   H-   HHMHEHH3UHH H}HuHE    HHE   HE <.u1HEH@HtvHEH@HUHHOu[HE   HEHMt!HEH@HUHHOu*HEWHEH@HUHHOu
HE6HUHEHHHEH} L?U        UHHH}HuHUHEHHHUHH@H}HuHU؉LEȈEHEHt
[  HE@4H9Et<HEH4HEH@HUH5*C AHH¿        t\  HE@y.HEH@H6C HHο        ;\  Eԃt
      HE@0t!Y  w
sJ  
A  EE   HEP8EЃ}    EHEHEȃH   HEȃHt:HEȃHt.HEH@HB HHο        m[	  HE@8H9E   HEH8HEH@HUH5B AHH¿        [   EHHEH9E   EHHEHHEH@LE}HUH5B HQMAHH¿        ZHTHE@8H9Et?HEH8HEH@HUH5B AHH¿        mZ    UHH@H}HuHUHMLELMHMHUHuHEIȹ   H!E} tEUHE@HMHUHu=UHH@H}HuHUHMLELMHMHUHuHEIȹ   HE} tE5UHE@HMHUHuUHH0H}HuHUHMHUHuHEIй        H>E} tETHE@HUHMHΉ UHH@H}HuHUHMLELMHMHUHuHEIȹ   HE} tESTHE@HMHUHuJUHH0H}HuHUHMHuHEA            H]E} tESHE@HUHMHΉPUHSHH}HEH}Jt    4HEHCJtHEH%J؉OډO HH]UHH H}HuHEHYE} y/HEH H@ HHο        oWS,HEHE    Ɖ貾EESUHH}HE@]UHH H}E    HEHuIt
       HE@tHEH HtHEHHEH҉EHEH@HtHEH@H0HEH@HtHEHPHEHHEH0ERUHH}HE@]UHH}HEH@]UHHH}HE@QUHH H}HEH E} y=M ؉EUHEH5> H¿        UEQ          HEH} uEtQXHEH<HHEUPHEHpHHEHPHEH@HuHEH QHEUHHH}HE@<EtM     UHH H}HuHEH@HtvP   HEH賳E} tERP   HEHEE} tE.P   HEHHHEHPHEH@HuO   HEHPHE@H։Pt49L ؉EHEH@H2.HEH@    EO/HEHPHE@H5< Hщ¿       S    UHH H}HEH@HuMOoHEH@H0E} tK KHEHPHE@H5< Hщ¿       TSHEH@Hb-HEH@        UHH0H}HEHEHEHEE    HE@     $  Ǹ    +yJ ؉EHEP HE؋@9tHE@ ;HE؋@-HEH@(HtNHE@0t"HE@1HEH@(H0  E HE@1HEH@(H3  EEUHH H}HEHEHEHEHEH@(H=,HEH1,UHH   H($HdH%(   HE1ǅ<H t;HHH; H   HLtM  $ y:H(H $H5: H¿        [Q=M  H(HDD y5H(H H: HHο        QL3  8      (HHHH uL  HHHHHHH\HPHH$P H t#HH HvH@;ƅ; H(H@p   Hu  ;c  HPP       HH tHH HvHH@    f)E)E)E)E)EHEP   HEHEHUHPHXHEHUH`HhHEHUHpHxHEHUHEHUHEHUHEHUHP$DHѺ)   蒥<< yR>G ؉@@n HH(H $H58 IȉH¿        N  HH<P  H tUHH HvEHH@Ht5H(H H8 HHο        ~Nǅ@w  D$$@Ǹ       SF ؉@@ HH(H $H5z8 IȉH¿        M@   H(H $H58 H¿        M   HH$PH tHH Hw       uH@to$     $  Ǹ    yOZE ؉@@ HH(H $H518 IȉH¿        M
HH3< x<`HHH&@HHUdH+%(   t蠪UHHH}uMHE    HuUHH0H}HudH%(   HE1H HEHHJFHEH} uAJD ؉EE HHEH5s7 HH¿       LE   HUHMHEHHǸ    rE}tY}tC ؉EEE HHEH5 HH¿       KHEHeEHEHTEHUdH+%(   tMUHHH6 HEH6 HEHHUHHH6 HEH6 HEHH|UHHH6 HEH6 HEHHMUHHH6 HEH6 HEHHUHH   H0H(D$L<8dH%(   HE1HǅX   H;s
  HXH`    H< tLLL yPL7 H< t	H"6 H H56 HH¿        ILh  8    < tPxPP yPP谿 H< t	H5 Hb H55 HH¿        #IP   HhP   HH	HhHXdL`HhHH H	HhH0HwKHEH(HE$u    $IH`A   AHƿ*      5TT yQ@ THUdH+%(   tUHH   HH H`HhLpLxt )E)M)U)])e)m)u)}dH%(   HH1ǅ    ǅ(   ǅ,0   HEH0HPH8H(H H@   H   x =  vH     HǸ    G$$ y? G HcH@$HΉ@Hy> ؉$;HHdH+%(   t莤UH y,HD3        Hƿb \ ]UHt	H2 H
3 ]UHt	H3 H$3 ]UHat	H23 HQ3 ]UH>t	H_3 H3 ]UHt	H3 H3 ]UHSH8H}HuHUHM   kU `H}H3 HuHEHuIAHǸ    HE    CoH UHcHUHHHH uEHcHEH _EEHcHEH uH]UHATSH H}HUHMЈE} t	H+3 H-3 } tAr   Ap   YHHMHUH
3 HuIIHDHƸ    5HHe[A\]UHSHH}E} t	H2 H2 HHEH52 HHڸ    H]UHSH(  HdH%(   HE1 t	H72 H92 VHHHE2 HIIؾ   HǸ    H/ HHHHUdH+%(   t9H]UHH   H8H(H D04dH%(   HE1HǅX   4H H(H8HLL yHL HH H(H5f1 IHH¿        BLo  4H8HqPP yNPLL蒸 HH H(H5+1 IHH¿        B   HXH`    HˠHXdPHHhǅ`   0u    0IH`A   AHƿ*      [TT y:w9 ؉LL觷 HH0 Hƿ        6AT4H8HLHUdH+%(   tUHHk0 ]UHH   \dH%(   HE1HhHh u
       HhH50 HpHH@   HǸ    xZVHpA    Aй    H¾        dd xdd[HpHE    @   HSHpHE        Hy    HE    Ht   HUdH+%(   t蒝UHH   H(H HdH%(   HE1Hp       H4f)EfEHE   HEHUHpHxHEHEHǅH    H t;HHH. H    H9t:3  H t"HH HvH@<
ǅ<    H t#HH HvH@:ƅ: H t$HH HvHH@HPHǅP    H tHH HvHH@    Hx;<t\<   <t(<wt< tz<ubƅ;Eh; t9  EJ; uH(H@p   H"t!D9  59  ;t5:HPH A    Aƿ    d@{HPH HE@   H;HEHHHHH u8  :HPH HHAHC@@ y}4 ؉DD貲 H: t	H+ Hd H(HLPH H5+ HQMIH        <H@  Hp@H(H̹HXHXHDD    @&D H: t	H++ H H(HLPH H5V+ HQMIH        C;H; tx\; tJHXH`H`HhHhHHHP(Hh@0Hh:P1HX7:HHHvHHHD6HUdH+%(   tzUHHpH}HUEdH%(   HE1HE        H*f)E)EHE    EEHEHUHEHUHEHUHEHUHUHMHEHHHUdH+%(   tԗUHH   H(H HdH%(   HE1H0        Hvf)P)`HǅP    HPHXH0H8H`HhH@HHH t;HHHX) H   H4t4  H(H@p   Ht=HuHE H H) HpIH       E-H H5( HpHH   HǸ    H tHH HvH@    HH tHH HvHH@    H8H0HpH(HHHUdH+%(   t͕UHHH}Hu=HE <?uHEHE&HEHE 8t
       HEHEHE tHE tHE <*uHE <*uUHEHE <*tHE u-   VHEHPHUHUHHBt   0HE uHE uHE u       UHHH}HuHEHHEH HH(UHH`  HHHdH%(   HE1HHHH@HHHHHH_t
      HHPHH0H-HIȹ   H6H   HHHH HH&HH u
    	  HHHH)H HIȉ   HǸ    HHPHH0HpHIȹ   HyHu
       HH@HPHHpHHHѺ   Ht   t<HHpHH@HHHHJHHHH    HUdH+%(   t~UHHp  HdH%(   HE1{Hǅ    Hǅ    Hǅ    Hǅ    H HHH.HH uM, ؉A HHH59$ HH¿        3]  H H*$ HHHǸ    $uHH  t0H# Hο        F3ǅo  HHH HH>   HHPHHHѺ   Hd     H HHH u* ؉   HHHPHHHHHH uǅ   HH`HHѺ   Hi HHHHHHHH@HHyHH@Huǅǅ    )HHcHHH HHH;rHHHHBHUdH+%(   t8UHu   H]UHH0  HdH%(   HE16Hǅ    HI HHH*HH uM( ؉ HHH5  HH¿        0k  H HH5+! HHǸ    uHHk   t0H  Hο        /ǅ   HHH HH   HH@HPHHpHHHѺ   H   u_HHpHH@HHHHJHHHHHH@HuǅHHHUdH+%(   tUHH0  HHHdH%(   HE1HPP       H腍f)E)E)E)E)EHEP   HEHUHPHXHEHUH`HhHEHUHpHxHEHUHEHUHEHUHEHUf)0)@HH0Hǅ    H t;HHH H+   H(t)  HHd   y5HH H HHο        q-S)  H t$HH HvHH@H Hǅ     H t$HH HvHH@HHǅ    H t$HH H'vHH@ H(Hǅ(    H t$HH HvHH@HHǅ    H t#HH H*vH@*ƅ H u#H uH  u(`  H t7H uH  uH u
H( t'  H uH( u'  H u t'  H tH  te'  H    tH0H(H0H ;   tSHHHtFHHHH HH5- IHH¿        *ǅ  H8HHHH(H t#HH H(vH@(ƅ H t#HH H)vH@)ƅ  t t&f   tǅ8   
ǅ*   H HxHHEHHEH(tp       HH uǅ   HHJHHP      yGa! ؉葟 HHH H5 HH¿        ))HPH8HH,HHH8H$HUdH+%(   t藆UHH   H}HuHxdH%(   HE1HE        HBf)E)EHE    HEHUHEHUHEHUHEHUHE    HxH     HEH@H. HH.tHEH@H HHu
    (  HEH@H| 
   HHSEEȄtHEH@H
HEHEH@HHEHMHUH56 HEHǸ    葆E} *HEH% HHο        :'   EȄt5HEHt,HEH1H
 Hƿ        &GHEHEHMHUHEHH袿HxHHEH HxH HڎHUdH+%(   t膄UHHpH}HuHUdH%(   HE1HE       H7f)EfEHE   HEHUHEHUHEHEHEH     HEH@HH HH5tHEH@H3 HHu
       HEH@H    HHZEEЄtHEH@HHEHEH@H	HEHUHMHEHHQHUHHEH Hui     HUdH+%(   t*UHH   HhH`HXdH%(   HE1HE0       Hσf)E)E)EHE0   HEHUHEHUHEHUHEHUHEHUHEHUHXH     HhH@H HHt!HhH@H HHu
       HhH@H    HH EEtHhH@HHEHhH@HHEHUHp HEHHǸ    || 'HEHZ HHο        #BHMHUHhHHHXHHEHHXH H茋HUdH+%(   t8UHH   HhH`HXdH%(   HE1HE0       H݁f)E)E)EHE0   EHEHUHEHUHEHUHEHUHEHUHEHUHXH     HhH@H^ HHu
       HhH@HHEHUH HEHHǸ    v|| 'HEH HHο        "OHMHUHhHHHXHHEH HXH Hu     HUdH+%(   tUHH   HXHPHHdH%(   HE1Hǅh    Hǅp    Hǅx    HE8       H!f)E)E)EfEHE8   HEHUHEHUHEHUHEHUHEHUHEHUHEHEǅ`HHH     HXH@HxHpHhH5 IHǸ    ddtdt   ǅ`       HhH    HHEHhHp    HHEHxHpHuHXIHHHHHHH H`2HXHPHXH H5 HH¿        HhHHpHHxH`HUdH+%(   tO}UHATSH H}HUHMЈE} t	H H } tAr   Ap   HHMHUH HuIIHDHƸ    HHe[A\]UHSHH}E} t	H: H< HHEH5@ HHڸ    iH]UHSH(  HdH%(   HE1 t	H H HHH HIIؾ   HǸ    覮H	 HHHjHUdH+%(   t{H]UHH   H8H(H D04dH%(   HE1HǅX   4H H(H8HLL yHL蝓 HH H(H5 IHH¿        Lo  4H8HqPP yNPLL" HH H(H5 IHH¿           HXH`    H[{HXdPHHhǅ`   0u    0IH`A   AHƿ*      TT y: ؉LL7 HH Hƿ        T4H8HLHUdH+%(   txyUHHpH}HuHUdH%(   HE1HEH HEHEHt=HEHHEHUHEH5 HH¿        HE  HUHMHEHH HHEH} t0HMHUHEH5c IHH¿        A  EHUHEH5r IHH¿       Eft1HUHEH5r HH¿        WHE_   EHEHHHEH} u>/HHUHEH5] IHH¿        HE`~HUHMHEHH& HEH} ~PEHEHDEH}HUHEH5- QuEIHH¿       HEHEHEHHEHC HEHUdH+%(   t9wUHH ]UHH`H}HuHUdH%(   HE1f)EfEH HEHH)uH HEHH2Ht0H H莳HEH HEcHEE   %H H^HEH HEE   E      EHHDH  EHHDHE   HE <:uHEHEо:   HEHEH} tHEH+EЉEHEH!Ẽ} tzLEHMЋUH= HuHEMIȉHHǸ    fUHE   Hƿx.HUHEH5 HH¿           <HEо:   HHEH} EEăHUdH+%(   tuUHH   H$ H0  HHHLdH%(   HE1Hǅ(    Hǅ0    HPP       Huf)))))HǅP   HHHPHXHHH`HhHHHpHxHHHHHHHHHǅ    ǅ    HǅH    H t;HHH H2   Ht  HH? y5HH H HHο        L.j  H t$HH HvHH@H@Hǅ@    H t$HH HvHH@H0Hǅ0    H t$HH HvHH@H(Hǅ(    H t$HH H'vHH@ H8Hǅ8    H tHH H/vHH@(    H H t#HH H0vH@0ƅ H t#HH H1vH@1ƅ H u  H uH Huq  H tCH@ u*H0 u H( uH8 uH Ht:$`  H@ H0 1Єt5   t t  H    H/   HH   HH   HHf tR׈ HHH HH5 IHH¿        O.j  HHH HHHHj  y  HH0eH@ t[H HH@HA   H  yt  HH0 tǅ9   
ǅ0   HHxH0HH(HH8HH tp u ~       
HHHH uǅ   HHH_HHP    f yGv ؉覆 HHH H5 HH¿        ((HHPHH%HH+HHHHHHUdH+%(   tmUHH   H$ H0  HHHLdH%(   HE1Hǅ(    HǅP    Hǅ0    Hp       Hnf)fօHǅ   HHHpHxHHH t;HHH H,   H	t
  H t"HH H+vH@(
ǅ    H t#HH HvH@
ƅ
 H t$HH HvHH@H8Hǅ8    H tHH HvHH@    HxH u	  H HHH HPHP t~ƅ Hǅ   HPH+HH H HH9HGHHHHUHH(HPHH   H/   HH   HH   HH tR HHH HH5 IHH¿        h  HHH t$HH H'vHH@ H@Hǅ@    H@    H( t7H@HH(HHpHHH(H H@HHH HHHH yHH  HHHctf   t/w~    uhƅƅk t;  ƅJ uHH@p   Ht!    t?
H8HHIAƿ      H8 tZ  H/   H HuHHHHH¾@   HH*H0H0 u  
HHH0AH y} ؉ H
 t	H  H HHLHH5o  HQMIH        L	H@  HpHHHXHXH=q    m7 H
 t	H H HHLHH5 HQMIH        H tx\ tJHXH`H`HhHhH0HP(Hh@0 Hh
P1HX7
H0H1H0HHUdH+%(   teUHH   HHH@H8dH%(   HE1HE0       Hfff)E)E)EHE0   HEHUHEHUHEHUHEHUHEHUHEHUHǅh    Hǅp    Hǅx    ǅ`HE    H8H     HHH@HxHpHhH5 IHǸ    eddtid  dtdt  ǅ`      HHHPHHH H5 HH¿        U  Hx+   HHEH} tZH\HUH5 HEHǸ    <eddu \HcHEH u	HE  HE    HhH HHtHhH HHu       EEt4HEHt+HHH HW HHο        T   HxHEHEHHpHMHHIHHH8HH8H H*m`2HHHPHHH H5 HH¿        HhHHpHHxH`HUdH+%(   tibUHH   H}UHxLpEdH%(   HE1HE0       H	cf)E)E)EHE0   EEHEHUHEHUHEHUHEHUHEHUHEHUH}HpHxuHEIHHUdH+%(   taUHH`  HHHLLdH%(   HE1HH@pHH t;HHH H,   H#te  HH賳y5HH Hv HHο          H u  H/   HH   HH   HH0 tRx HHH HH5 IHH¿        h  HHHH  H=tHH  H%  HH  HuRHHf HH  HH  HtHH  Hn   H t$HH HvHH@HHǅ    HH  LHHHHMIH] HHHHh tHHUdH+%(   ty^UHHPH}HuHUdH%(   HE1HE    HE    HE    HEH輹HEHd HEHHRuHEH            H}HMHUH5. HEIHǸ    _Eԃ}t)HEH& HHο        E?HuHMHUHEA    IHHUHHEH HgEHEHHEHyHEHmEHUdH+%(   t&]UHH   H$ H0HHdH%(   HE1誸HHHH HII   HǸ    c y W=  v1HHH5/ HH¿       tH HHHϱHUdH+%(   t.\UHH   H8H0dH%(   HE1HǅX   H0H8HHLL yHL't HH0H8H5 IHH¿        L   HXH`    HZ\ǅ`   HXdLHHhH`A   A    Hƿ*      PP yT! ؉TTQs HH0H8H5 IHH¿        TPHUdH+%(   tZUHHpH}HuHUHMdH%(   HE1HE       HE[f)EfEHE   HEHUHEHUHEHEH} t5HEHH| HE   Ht  H} tHEH Hv
HEH@    HEHUHEHHE} yMEr HHEH H}HUH5 IIHH¿        }E_   HUMHEHGyHEHEHwcE} tTE贃Eq HHEH H}HUH5 IIHH¿        EHEHUdH+%(   tXUHH H}HuHUHUHuHE    H/UHH@H}HuHUHEH     HEH@Hb HHtHEH@H{ HHru
       HEH@H4HEH} u
   HEH@H    HHuHEHHEHEHHEHE/   HHEH} uHEHEHE  HEHUHMHEHH@HUHHEHHEH HaUHHpH}HuHUdH%(   HE1HE       HWf)EfEHE   HEHUHEHUHEHEH} t5HEHH HE   Ht0  HEHjE} y2HEH H HHο        b          蠖HEH} u9   HEHHHEHEH} tHEH Hv
HEH@    HEHUEH։E} y[ ؉EHEHE$n HHEH HUH5  IHH¿        EHEUPHEHUdH+%(   tbUUHHH}HuHMHE    HH蔃UHH@H}HuHUHE    HEH     HE       HEH    H'. HHHHEH    H. HHEH@HH^urHEH    H- HH軮HEHEHPHEH u
       HEHPHEH </uHEH@HUHHHEHEH}*H} u2HEHPHEH H5 HH¿        )HUHEHHȄHUHHEH H^UHH   H8H0dH%(   HE1HPP       HkTf)E)E)E)E)EHEP   HEHUHPHXHEHUH`HhHEHUHpHxHEHUHEHUHEHUHEHUH0 t;H0HH H0   Ht~  H8Hu@@ y5H8H H HHο        d+         袒HHHH u5   HHHHH0 tH0H HvH0H@    HpH8HHP@Hщ    JDD yc ؉DHHHDi HH8H H5 HH¿        nDMHHDPHHHUdH+%(   t"QUHHH}HE    H?UHHH}HuHUHEHHUHHH}HE    HUHH H}HuHUHEHHUHHEH HZUHH H}HuHUHEH!HUHHEH H{ZUHH@H}؉uHUHMHEHE} y2HEH H# HHο                  HEH} u   HEHvHHEHĜEHMUuԋEGE} y[ ؉EHEHEg HHEH HUH5 IHH¿        7EHEUPHEUHHH}uHlp uHE    HUHHH}uHHp uHE    HrUHHH}uHCp uHE    HBUHHH}uHMn uHE    HUHH   H84H(dH%(   HE1HPP       HNf)E)E)E)E)EHEP   HEHUHPHXHEHUH`HhHEHUHpHxHEHUHEHUHEHUHEHUH( t;H(HHh H(    Hht:X  H( t"H(H HvH(@H
ǅH    H( t"H(H HvH(@L
ǅL    L t>H t5H8H H HHο           H( tH(H HvH(H@    HxLpHtH( tH(H HvH(@    XHPH=wm 4H8HHHHUdH+%(   tKUHH   H84H(dH%(   HE1HPP       HnLf)E)E)E)E)EHEP   HEHUHPHXHEHUH`HhHEHUHpHxHEHUHEHUHEHUHEHUH( t;H(HHH H(    Ht  H( t"H(H HvH(@H
ǅH    H( t"H(H HvH(@L
ǅL    4 u5H8H H HHο        .   L t>H t5H8H H HHο           H( tH(H HvH(H@    HxLpHtH( tH(H HvH(@    XHPH=j 4H8HHHHUdH+%(   tIUHH   H84H(dH%(   HE1HPP       HIf)E)E)E)E)EHEP   HEHUHPHXHEHUH`HhHEHUHpHxHEHUHEHUHEHUHEHUH( t;H(HH H(    H*t  H( t"H(H HvH(@H
ǅH    H( t"H(H HvH(@L
ǅL    4 u5H8H H HHο        pR   L t>H t5H8H HD HHο        )   H( tH(H HvH(H@    HxLpHtH( tH(H HvH(@    XHPH=+h 4H8HHH*HUdH+%(   tOFUHH   H84H(dH%(   HE14 H( 1Єt5H8H H HHο        {  H8   t5H8H H HHο        4  4   HPP       HNFf)E)E)E)E)EHEP   HEHUHPHXHEHUH`HhHEHUHpHxHEHUHEHUHEHUHEHUH8H@p  4H(HuLL yLFLlHPH= 4H8HHH(H8HHUdH+%(   t<DUHH   H(H dH%(   HE1HPP       HDf)E)E)E)E)EHEP   HEHUHPHXHEHUH`HhHEHUHpHxHEHUHEHUHEHUHEHUǅ<    H  t;H HH H    HUt'  H  tH H HvH H@    H`H  tH H HvH @    hH(H聕@@ y5H(H H HHο        p          讂HHHH uA   HHHH<HP@HѺ   k:DD yc ؉DHHHD8Z HH(H H55 HH¿        DHHDPHHHUdH+%(   tnAUHH H}HuHUHE    HHHUHHEH HmKUHH   H8H0dH%(   HE1HPP       HAf)E)E)E)E)EHEP   HEHUHPHXHEHUH`HhHEHUHpHxHEHUHEHUHEHUHEHUH0 t;H0HH H0   HPt"  H8H@@ y5H8H H HHο                 HHHH u  HHHbHH0 tH0H HvH0@    pH0 tH0H HvH0@    tH0 tH0H HvH0@    xH0 tH0H HvH0@    |HP@HѺ-       7DD yc ؉DHHH誺DV HH8H H5 HH¿        VD5HHDPHHHUdH+%(   t
>UHH0H}dH%(   HE1HE    HEH@HtHEH@H@0Hu   HEHxy/HEH H> HHο        uWHEH@L@0HEH@HHHUHEHHAЉE} tE7HEHu"HEHUdH+%(   t
=UHH0H}dH%(   HE1E    HEHEHEHEHE@ yHE؋@HUH։BHE؋@2gHUdH+%(   t<UHH0H}dH%(   HE1E    HEHt3HEH@H< HHο        A#[  HE؋@y3HEH@H6 HHο          (      #|HEH} u   HEH@hHPHE؋@Hu    cE} t1HE؋@@%    t}tHEH蛷E_   HEHIHHE؋@@%    uHE؋PHEPHE@ HEZHE؋@    ,       b3E} yHEHEHEUPHE؋PHEP HEHUdH+%(   t:UHH0H}HudH%(   HE1E    HEHt#   HEЋ@y3HEH@HA HHο        F   HEHEHEHEHE@ ytHEH@hHPHEЋ@Hu    +bE} t}tE=HEЋHHE؋@    Ή+CE} yEHEЋPHEP     HUdH+%(   tv9UHHĀH}HuHUHMLELMHEHEHEHHEHEH  HEHUHEHHEE;  HEHH#EHHEHHEHE@HEHUHEHHMHUHH9   HEHEHUHEHH+EHEHEH+EHEHEH H;EsSHEH H賴HEH7zHHEHHEH HuHEH     E   HEHUHHEH HUHMHH5HEHHEHHUHEHHHEH HEHUHEHMHHщEHEHE}uHEH;EHUHEHHZE`UHHH}HuH}    HEH@HtLHEHP(HEH@ HHEH@HH!t"HE@$H Hο        =HE@ x+HE@     $  Ǹ    SHE@ aHEH@HHEH	UHH H}HEHD   HEH@0Ht{E    VHEH@0UHcHHH HEH} t.HEHP(HE@HH։HUHEHHEHE@@9E|HEH@0HXHE@DxHE@D`HEH@8H/HEH#UHH0H}HuU܉Mؾ0      vHEH} uH  HEHUHHEU܉P$HEU؉P(UHEA   AѺHƿ*      NHEP HE@ y<e ؉EEM HEH5 Hщ¿        %   HEH HEHP(HEH@ HA    Aȹ      Hƿ    pHUHBHEH@HuEHEH@     ؉EEM HEH5o Hщ¿        `HE@      $  Ǹ    謆y9s ؉EEL HEH5M Hщ¿        3HE!HUHEHHcEHHIUHH   H HHLLdH%(   HE1Hǅ   f) )0)@)PH t;HHH H   HptB   H t"HH HvH@
ǅ    u
ǅ   HH`    H3HdHǅh
   ǅ`   Hǅx   EH`H HH0HH8HH@H H HΉt  HcHUdH+%(   t32UHHĀ}HuHUHMLELMdH%(   HE1f)E)E)E)EH} u   H} t5HEHH$ HE    Ht   HEHEHEHEHEHEH} tHEH Hv	HE@    EH} tHEH Hv
HEH@    HEH} tHEH Hv
HEH@    HEHUHMEHΉ   HHUdH+%(   t0UHH   LH@H8dH%(   HE1H" HxHǅp    H@ tH@HH#@Ht4H@H HHο        ^H  HEh       H1ǅTh   HTHMLHΉ``     ؉``tF`/H HLH5` Hщ¿        `HH  LHZ Hο       :Et2HEHPH} Hƿ        UH  P      soHEH} uH\h  H8HPHEHH8HPHEHPH8HPHEHPH8HP HEHPxHcHEHP HEH@ H@HHEHP(HELPH   誴HUBDHE@Dy= ؉``F HH Hƿ        BZ  H8@(~H8P(HEP@JyHUB@HE@@yHE@@`  EtUHE@@9sEHEP@HE@@H   HmHHEHP8HEH@8Hu(ǅ`H Hƿ          HE@@H   HmHHEHP0HEH@0Hu(ǅ`H Hƿ        +C  HXHpHxHH8  `` t.`?E HH Hƿ          ǅd    ǅh      H8@(~%H8H@0dHcHHЋ ldlH8@(~H8H@8dHcHHЋ d\H8@(2X9l  HplHH   \H8H0lHEHHEHEH tHEH`  HEH@0hHcHHHEHHEHP HE@HH\    S`` tWd ؉``C HHEx \lH5H IAщ¿        	!  HEHH8hHcHHHHH    HEHH8hHcHHHHHHEHBHEHH8hHcHHHHHHEP HE@D   yyK} ؉``B HHEP lH5 Iȉщ¿        +FhdHE@@9dUHEhP@HpHHE2HpHH} tHEH`HHHUdH+%(   t)UHH@H}HuHEHEHEH HEHEHEHEH Ht'HEL HE؋H$HEH@HUȉHA   HEȋ tU	   HEHEHEH@H   HEL@HEPHEHxHE؋p$HEH@HHAfHEHEHEH@HtTHEL@HEHPHE؋H$HEH@HA+HEȋ H, Hο        z	UHH H}HuHEHxHEHHHEHP HEHp(HEH@LHuMIHHE}tE    UHH}HE@D]UHH0H}؉uHE؋P@HEHp8HE؋@DMԉmE} y    E    xHEHH8EHcHHHHHH@HEHUHEHHE} t2E? HH Hƿ        'EEE;E|EUHH}HE@@H]UHH H}HuHE@@HH9Ero4HEH@0HUHHH HEH} uBHE@ UHH0H}uHUHMHE@@9E|RHEH@0UHcHHH HEH} u#HEHPHEHHEHP(HEH    UHH H}HuHE@@HH9Er@HEH@0HUHHH HEH} uVHUHEHH0UHH H}E    {HEH@0UHcHHH HEH} tSHUHEHHE} t8E= HEH5 Hщ¿        EEHE@@9Eu    UHH@H}؉uHUdH%(   HE1E    E    H} t} yI3  HEH@p@Tv*  } tH} uUHE؉          } t<HEH@p  MHEȉH$UEE   E   H} u   HEH@p   Hy@E} tEnHE؋   HEH@pH}HMHuIHuVE} tEC0EHE؉   EHE؉   UHE؉       HUdH+%(   tB#UHH0H}HuHUHEHuE} y2HEH HU HHο           HE苀   u2HEH Hd HHο        `   HEHt2E} y0HEH@HT HHο        yVHEHt0HEH@HY HHο        6տHU؋MEΉUHHPH}HuHUdH%(   HE1E    EHEH     HE       HE <,tHE <
u
HEe  LEH}HMHUH5 HEMIHǸ    "E} ~}~.UHEH5 H¿        GE:  }uEEEx
UE9~3UEHMH5 Iȉщ¿        E   EHcHEH HHHEH} uE   HEHUHUHE )HcHUHcHUHH¾    H^!UE)BHUHcHUHH¾   H4!EPHEEHHEHE lHE u H Hƿ        $    HEH HHEH     EHUdH+%(   tUHH   HXHPHHdH%(   HE1ǅd    HX   HǸ    hh yMr ؉dd7 HHXH5 HH¿        'd   Hph   HΉ[lhkIl _l t ؉d
ǅdd7 HHXH5 HH¿        delv*HXH HHο        W0lHƄp HHHPHpHHHUdH+%(   tUHHPdH%(   HE1E    HϏ HEHEHEE   }tM}W}t3}K}t}t=HEHE؈IHEHEf9HEЋHE؉+HEHHEHEHHMHUHHHNEE} ~E  H2 HUHMHHSE} tE跺   E    E    HUȋEHH tEEE9E|HEHEEHΏ HEHEHEE   }tM}W}t3}K}t}t=HEHEIHEHEf9HEHE+HEHHEHEHHMHUHHH*EHUdH+%(   tUHHPH}HuHUHME       EHHEHHEHHEHEH@HEHEH HEHEH@HEHUHEHHwHUHHEH Hu'HEH HHο        i@H} t!HEH @\tHEH HP`HEHEEHH;E=    UHH@H}HuHUHME       EHHEHHEHHEHEH@HEHEH HEHUHEHHHUHHEH Hu'HEH HHο        胼EEHH;Eq    UHH H}HuHEHHHEHPHEH@HuIHƿ    HEHEHltOHEHNEEJ2 HHEH@H5 HH¿        λEm   HEH@ HUHHE@,HcHE@(HcHEHp0HEHvE} t=E1 HHEH@H5I HH¿        NEsHE@<HcHE@8HcHEHp@HEHE} t=E\1 HHEH@H5 HH¿        E    UHSHhH}HEH@HuN  HEH@HRHEH} uAHEH@HNHH Hƿ        Yb ؉U  HE@HcHE@HcHEHpHEH@HE} t5EZ0 HH Hƿ        E舵  HE@$HcHE@ HcHEHp(HEH@HE} t5E/ HH' Hƿ        E  E    `  HEHP8HE@4EHHHEHEH@H HEHEH3EUHEHBHEHEHntSHEHiHHEH[bHH HHƿ        辸]   HEH-EHEH許HEE    tHEHEHBHEHEHEH6fHEHEHHEHHlu!HEHP`HE@HEH@HHEHEE;E|EHE@09E    H]UHHH}H} t>HEH@HHEH@(HБHEH@8HHEH贑UHH0H}HEH@ H H<E} t@E- HHEH@H5O HH¿        4EӲ   E       HEHP0HE؋@,EHHHEHEH@H HEHEH@HtGHE@0!u&HEHH`HEH H  HEH@HHHEH@HUHR`HEHE؋@(9El    UHSHXH}E      HEHP@HE@<EHHHEHEH@H HEHEH@HEHE@|   HE@}   HEH@H   HEH@H@0H   HEH HuHEH@L@0HEH@HHHUHEHHAЉE} tNE+ HHEHEHH HHƿ        hE  EHE@89EE    m  HEHP0HE@,EHHHEHEH@H HEHE   !  HE     HEH$   HE@,w-HEH*^HH Hƿ        萴   HEH@HEH} u-HEH]HH Hƿ        P   HEH HuuHEHaHUHHEH HuW) ؉EE_* HHEHy]HH HHƿ        ܳE{ EHE@(9E    H]UHH@H}E    FHEHP@HEȋ@<EHHHEHEH@HEHEH HGHEH     EHEȋ@89E|HEȋ@,vdE    MHEHP0HEȋ@,EHHHEHEH@HEH} tHEH HjGHEH     EHEȋ@(9E|UHHH}H} tZHEH'$HEH@ HtHEH@ H HxHEH@0H藌HEH@@H臌HEH{UHH}HuHUH} t[HmHE     HUHEHHMHUH HEHEH;EsHUHEH uHUHEH  ]UHH}HuHE t    HEHmH} ݸ   ]UHH H}HuHUHMH}w+HUHEH5; HH¿        h    THEH+EHHUHEHHH]t'HEH HHο               UHH}} yUډEUHH}} y EUHH}} yEE     Ǹ    
UHH }EE} yEh}_EEq EE8]U} y.E؉EH5A щ¿         )UEUHH}HE]UHH}HuUMHUEƿA      bUHH }HuUUHMEHΉEE
UHH H}uUUHEHƿ   E} yu u
m} ͋EUHH   dH%(   HE1Hǅ0   ƅ@AAAAfǅB  ǅD   ƅHIIIIfǅJ  ǅL    Hǅ8   H0HP    HfǅP   H@H^HXH8TH H;H`E t|   |H0HPHƿ   1,, x,g6       HUdH+%(   tUHHH} tHEH     UHH dH%(   HE1f u       k t    RA HF Hu    8H3 HEHEHEHEHƿ   >Bt     HUdH+%(   t
UHH   <H08,D(L dH%(   HE1HǅH\   HHHP    HTH  t;H HH H D   Ht+  <PH0 t5         t"H0HPHJ   HH8T,X(\H  tH H HvH @    EH  tH H HvH @    EH  tH H HvH @    EH  tH H HvH @    EH  tH H H3vH @0    EH  tH H HvH @    dH  tH H HvH @    `H  tH H H'vH H@     HEH  tH H H+vH @(    hH  tH H H/vH @,    |H  tH H H7vH @4    EH  tH H H?vH H@8    HuHEH  tH H HCvH @@    EHHHPHƿ    cDD;HUdH+%(   tUHH@H}؉uԉUЉM̋UЋEHHEHEHHHEH} u    gHEHEE    JUHMHEHH~E+ẺUHEHHʾ    H^EHE؋EHEEE;ErHEUHH0  HHHLLdH%(   HE1HǅH   Hǅ     Hǅ(    eH t;HHH) Ht   Ht  H t"HH HvH@
ǅ     yZ@   u
ǅ   HHHP    HPH tHH HvH@    EH tHH HvH@    EH tHH HvH@    |H tHH HvH@    EH tHH HvH@    xH tHH HovH@l    EH t5         t"HHPHJ0   HHuHHH`H;sz  HHzHXHTH t"HH H'vH@$
ǅ    H t"HH H+vH@(
ǅ     t t  H tHH H#vH@     E tE	EH t$HH HgvHH@`H@Hǅ@    H t"HH H_vH@\ 
ǅ     H t"HH H[vH@X
ǅ    H@   1Єt  H t"HH HGvH@D
ǅ    H t$HH H?vHH@8H0Hǅ0    EH0H8HEH tHH HCvH@@    EH t"HH HWvH@T
ǅ    H t$HH HOvHH@HH8Hǅ8    EH8HHEH tHH HSvH@P    EH tHH H7vHH@0    HHEH tHH HsvH@p    E䃽 t.H@HHp lhHHHPHH tHH HkvUHPh ^  <  H  uoEthE;s]MuH0HH H  u      H HHEE   H(    E   E;   MuH8HH(H( u蘘    4  H(H_HEEHHHPHH tHH HkvUHPh     uH  H(     H@ t~H@HHp lǅh   HHHPHH t"HH HkvUHPhH HZyH(HKy7HUdH+%(   tUHH   <H0H(H dH%(   HE1HǅH    HHHP    H<PH0HHXH(HiH`H HhHHHPHƿ   EDDLHUdH+%(   tUHH   <H0H(dH%(   HE1HǅH    HHHP    H<PH0HHXH(HH`HHHPHƿ   oDDvHUdH+%(   t9UHH   <H0H(H dH%(   HE1HǅH    HHHP    H<PH0HHXH(HH`H HhHHHPHƿ   DDHUdH+%(   tNUHH   <H0H(dH%(   HE1HǅH    HHHP    H<PH0HHXH(HH`HHHPHƿ   DDHUdH+%(   txUHH   <H0H(H dH%(   HE1HǅH    HHHP    H<PH0HHXH(HH`H HhHHHPHƿ   DDHUdH+%(   tUHH   <H0dH%(   HE1HǅH    HHHP    H*<PH0H HXHHHPHƿ   
DDHUdH+%(   tUHH   <H0H(dH%(   HE1HǅH    HHHP    Hj<PH0H`HXH(HhHHHPHƿ   <DDCHUdH+%(   tUHH   <H0H(dH%(   HE1HǅH   HHHP    H<PH0HHXH(H|H`HHHPHƿ   fDDmHUdH+%(   t0UHH   <dH%(   HE1HǅH   HHHP    H<PHHHPHƿ   DDHUdH+%(   tUHH   <8H0H(L LHEHHEHdH%(   HE1HǅH8   H t;HHH H   Hct3  HHHP    H8tH0HHPH(HHXH HH`HHoHhH pH tHH HvHH@    HxH tHH HvHH@    HEHH<HPHΉDpHDHUdH+%(   tUHH }HuHUHMHUEuuA    Iй        ƿ   HUHH0}HuHUHMLELMH}HuHMHUEuuIIƿ   pHUHH0}HuHUHMLELMH}HuHMHUEuuIIƿ   HUHH0}HuHUHMLEHMHUEuuIIй        ƿ   HUHH   <H0H(dH%(   HE1HǅH   H( t;H(HH H(   HQt   HHHP    HH( tH(H HvH(@    `H0HzHPH( tH(H HvH(@    \<XHHHPHƿ   'DD.HUdH+%(   tUHH}HuHME    HΉFUHHH}HE    H3sUHH   H8H0dH%(   HE1HǅH   H0 t;H0HH H0   Ht1   HHHP    HH0 tH0H HvH0@    `H8HHPH0 tH0H HvH0@    \HHHPHƿ   DDHUdH+%(   tNUHH`}uUMdH%(   HE1HE        Hf)E)EHE    EEHEHUHEHUHEHUHEHUHMUuEHUdH+%(   tUHH   ,($HdH%(   HE1HǅH    H t;HHH H    Ht0  H t"HH HvH@8
ǅ8    H t"HH HvH@@
ǅ@    H t"HH HvH@<
ǅ<    @ t8 tm  HHHP    H6(P,T$XH tHH HvH@    `H tHH HvHH@    Hh8 t< \8d<\@dHHHPHƿ   rDDyHUdH+%(   t<UHH   ,($HdH%(   HE1HǅH    H t;HHH H    H0t  H t"HH HvH@8
ǅ8    H t"HH HvH@@
ǅ@    H t"HH HvH@<
ǅ<    @ t8 t   HHHP    H(P,T$XH tHH HvHH@    Hh8 t< \8d<\@dHHHPHƿ	   2DD9HUdH+%(   tUHH}uUE    ƿ    Q)UHH}uUUuE    %)UHHP  HdH%(   HE1Hǅ@   H t;HHH HL   Ht(_  H t"HH HvH@
ǅ    H t"HH HvH@
ǅ     u     t t  Hǅ    H t7HHHH)HHHHHH`t       uQ  HHP    HPTXH tHH HvH@    \ t`  :  :  9  9  8  8  7  6  5  1?
  0  0  /y  .I  -	  -R  +	  +8  *  *  )  )  "	  "
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  H tHH HvHH@    H|H`h
  H tHH H'vHH@     H`Hǅ((   H t7HHH(H)HH(HHHHt       	    H tHH H#vH@     `H tHH H'vH@$    dH tHH H/vHH@(    H,HhH tHH H7vHH@0    HHpH tHH H?vHH@8    HHxHǅ @   H t7HHH H)HH HHHHt       Z  K	  H tHH H#vH@     EH tHH H'vH@$    EH tHH H/vHH@(    HH`H tHH H7vHH@0    HuHhH tHH H?vHH@8    H:HpH tHH HGvHH@@    HHxH tHH HKvH@H    EHǅP   H t7HHHH)HHHHHHt       x  f  H tHH H'vHH@     HhHǅ0(   H t7HHH0H)HH0HHHHt           H tHH H#vH@     `H tHH H'vH@$    dH tHH H+vH@(    hH tHH H/vH@,    lHǅ0   H t7HHHH)HHHHHHt           H t"HH H#vH@ 
ǅ    H t"HH H'vH@$
ǅ     t t;   t`\ \`H tHH H/vHH@(    HhHǅ0   H t7HHHH)HHHHHHzt       K  0g  H t"HH H#vH@ 
ǅ    H t"HH H'vH@$
ǅ     t t   t`\ \`H tHH H/vHH@(    HhHǅ 0   H t7HHH H)HH HHHHt           H t"HH H#vH@ 
ǅ    H t"HH H'vH@$
ǅ     t tBy   t`\ \`H tHH H/vHH@(    HhHǅ80   H t7HHH8H)HH8HHHHt          n  Hǅ@   H t7HHH@H)HH@HHHHIt       u':  
HHPHƿ    x   t ؉t   Tu
`tc   HǅH   H t7HHHHH)HHHHHHH>t       u/wƿ    HUdH+%(   tUHH   <dH%(   HE1HǅH   HHHP    HM<PHHHPHƿ"   CDDJHUdH+%(   tUHH   <8H0dH%(   HE1HǅH   H0 t;H0HH H0   Ht  H0 tUH0H HvEH0@t7H0 t-H0H HvH0@t7H  HHHP    H <P8TH0 tH0H HvH0@    XH0 tQH0H HvAH0@t3H0 tH0H HvH0@    \YH0 tOH0H Hv?H0@t1H0 tH0H HvH0@    \HHHPHƿ   DDHUdH+%(   tUHH   <dH%(   HE1HǅH   HHHP    Hs<PHHHPHƿ!   DDpHUdH+%(   t3UHH   <8H0dH%(   HE1HǅH@   H0 t;H0HH H0@   H-t+  HHHP    H<P8TH0 tH0H HvH0@    XH0 tH0H HvH0@    hH0 tH0H HvH0H@    HH`H0 tH0H H/vH0H@(    HHxH0 tH0H H'vH0H@     HrHpH0 tH0H H7vH0H@0    H7HEHHHPHƿ   $DH0 t H0H Hv\H0PH0 tH0H H?vHUH0HP8H0 t H0H HvhH0PDHUdH+%(   tqUHH   \XTHHL@L8dH%(   HE1Hp@       Hf)E)E)E)EHE@   HEHUHpHxHEHUHEHUHEHUHEHUHEHUHEHUTxH@HEH8 EHpX\ΉlHH t|HHUH8laHUdH+%(   t$UHH   <H0dH%(   HE1HǅHP   H0 t;H0HH{ H0P   H$t  HHHP    H|<PH0 tH0H HOvH0@L    EH0 tH0H HKvH0@H    EH0 tH0H HGvH0@D    EH0 tH0H H?vH0@<    pH0 tH0H HCvH0@@    tH0 tH0H H3vH0@0    xH0 tH0H H7vH0@4    |H0 tH0H HvH0@    XH0 tH0H HvH0@    \H0 tH0H H'vH0H@     HHEH0 tH0H H/vH0H@(    HeHEH0 tH0H HvH0H@    H-H`H0 tH0H HvH0H@    HHhHHHPHƿ
   DH0 t H0H Hv\H0PH0 t H0H H7v|H0P4H0 t H0H HCvtH0P@H0 t H0H H;vTH0P8D;HUdH+%(   tUHH   <H08dH%(   HE1HǅH   HHHP    H<PHH8HPHΉ舿DD uTH0DwHUdH+%(   t:UHH}HuHME   HΉUHH}HuHME   HΉUHH}HuHME   HΉUHH}HuHME   HΉUHH   <H0dH%(   HE1HǅH   H0 t;H0HH`v H0   H莼t   HHHP    H<PH0 tH0H HvH0@    XHHHPHƿ   ڽDD貼HUdH+%(   tuUHH}E    eUHH   <H0dH%(   HE1HǅH   H0 t;H0HH'u H0   HUt   HHHP    H<PH0 tH0H HvH0@    XHHHPHƿ   衼DDyHUdH+%(   t<UHH}E    AUHH   <H0dH%(   HE1HǅH   H0 t;H0HHs H0   Ht諺   HHHP    Ht<PH0 tH0H HvH0@    XH0 tH0H HvH0@    \HHHPHƿ   7DDHUdH+%(   tUHH}E    UHH   <H0dH%(   HE1HǅH   H0 t;H0HHr H0   H貸tA   HHHP    H
<PH0 tH0H HvH0@    XHHHPHƿ   DDָHUdH+%(   tUHH}E    UHH   <H0H(dH%(   HE1HǅH   HHHP    H<PH( TH0HHXHHHPHƿ   DD uTH(DϷHUdH+%(   tUHH }HuHUHUHMEHΉUHH }HuHUHUHMEHΉVUHH }HuHUHUHMEHΉ(UHH }HuHUHUHMEHΉ UHH   <H0dH%(   HE1HǅH   H0 t;H0HHo H0   Hڵti   HHHP    H2<XH0 tH0H HvH0H@    HHPH0 tH0H HvH0H@    H`HHHPHƿ   DDHUdH+%(   tUHHPH}udH%(   HE1HE       H:f)EfEHE   HEHEHEHUHEHUHEHEHUEH։CHUdH+%(   tUHH   H(H HdH%(   HE1HǅH(   /HHHP    HH t;HHHm H$   HȳtWl  H t$HH HvHH@H8Hǅ8    H t%HH HvH@H@Hǅ@    H t"HH HvH@0
ǅ0    H;@s葳  H@ tH8 un  H(HTHPH `H tHH HvH@    pH tHH H#vH@     t0 t/H8HƳHXH@d0hHHHPHƿ   Ƴ44 ycH8 tY0 uPH8HXHXH@dǅh   HHHPHƿ   Z4H t HH HvlHP4HUdH+%(   tUHH   <84H(L LHEHHEHHE H dH%(   HE1HǅH0   HHHP    H-<P8T4XH(HH`H  \HHHPHƿ   D\H hHlHHpHHHxH HD螰HUdH+%(   taUHH   <dH%(   HE1HǅH   HHHP    H<PHHHPHƿ    *DDHUdH+%(   tžUHH   <8H0dH%(   HE1HǅH   H0 t;H0HHh H0   H迮tN   HHHP    H<P8TH0 tH0H HvH0@    XHHHPHƿ#   ЯDD׮HUdH+%(   t蚽UHH   <H0dH%(   HE1HǅH   H0 t;H0HHg H0   H蚭t)   HHHP    H<TH0 tH0H HvH0@    PHHHPHƿ$   DD辭HUdH+%(   t聼UHH   <8H0,L dH%(   HE1HǅH   H  t;H HHf H    Hnt   HHHP    HƼH0HȭHP,X8\<`HHHPHƿ%   莭DD蕬HUdH+%(   tXUHH   <8H0dH%(   HE1HǅH   H0 t;H0HHe H0   HRt   HHHP    H誻8P<TH0 tH0H HvH0@    XHHHPHƿ&   cDDjHUdH+%(   t-UHH}HEH]UHH}HE ]UHH}HuHE EHE +EHEEHcHEH]UHH}u}~#HE fvHE 9E|       ]UHH}HE@?]UHH8H}؉uHUE    HEHE} xE;E~
      EHcHHHHHHEHHEHE fv
       HE@ftHE@E-HE ft!HE HH Hˎ EHEHy;EszHE@ft$HEHTHE@9~IHE fu7HEHHEHEHHHPHEH t    UHH}HE ]UHH@H}؉uHUȉMLEdH%(   HE1EԃHH    HEؾ    H虸HEHEEЉE   HEH
EE;E   H} t&HUMHEHE} yE   EHH    HEHH HtEHa Hο        &YEHH    HEHHEHHUHEHHHEUHEH0    HUdH+%(   t譶UHSH(H}uHUHMHEHjHEHJHHMЋuHEIȉHcH]UHHĀH}dH%(   HE1f)EfEfE fE HE    HE@%   u
       HEHHEE   HE@%   uHEHHEEHcHEHHEHE HEHH+EEHuMHUHEI   Ht H` Hƿ        kW    >HEHtHEHHEHEH` HHο        +W    HUdH+%(   t UHfEE]UH}E]UHH}HE]UHH}HE]UHH}HEH= H]UHH}H} HuHEH= Ht       ]UHH}HE@]UHH}HE@]UHH}HE@]UHHH}HEHfUHHH}HEHfUHHH}HEHgfEf}tf}u       UHHH}HEH,fUHHH}HEHfUHHH}HEHfUHHH}HEHfUHHH}HEHfEf}	tf}
tf}tf}u       UHHH}HEH_fUHHH}HEH>fUHHH}HEHfUHHH}HEHuHEHt       UHH}HEH]UHH}HEH]UHH}HEH]UHH}HEH]UHH H}uHEHHUHHHHHHEHEHvE} tHE@    UHH}HEH]UHH}HEH]UHH}HEH]UHH}HEH]UHH0H}HuHUdH%(   HE1    HEHeq   HEHȃHt    HUHEHH۩HUdH+%(   tװUH}uUEE	E]UHH}HuHE t    HEHmH} ݸ   ]UHH H}HuHUHMH}w+HUHEH5[ HH¿        JR    THEH+EHHUHEHHH]t'HEH[ HHο        Q       UHHH}HE HUHE@HUBUHHH}HE HUHE@HUBHE@nHUBHE@YHUBUHHH}HE 2HUHE@HUBHE@	HUBHE@HUBUHH}} yHUډEUHH}HUډ    UHSHH}HEHtHEH؉HډHEHuHE    H]UHH}H} tHE u       ]UHH}u} u    "HEH|Jy7Hи@   +EHH]UHH}HE]UHH@H}HuHUHMLELMHUHEHHEH H9rHEHHEHEH  HUHEHH9Es
       HEH HEHEHHEH}wHE   HEH9EsHEHEHUHEHH9EsHUHEHHEHEH HUHMHHHEH} u    eHEH HUH)HHEHUHHHMHUHH¾    H茭HEHUHHEHUHHEHEHHEHUHH0H}HuHUHMHEH H;Er    MHEH HUHH)HEHHUHuHEIIHAHEH} u    UHHH}HuHE@@HEHp8HEH0HUIA   HUHH H}uHE   HHEH} uHEU    UHHH}HE DHUfHE@AHUBHE@,HUBHE@HUBHE@HUBHE@HUBUHSH(H}HEH@HEHE؋@w#HtV Hƿ       L  HE  tf9u\HE@HE@kt3HE@XH3V Hƿ        ;L  HEH<HE f=t/HE HCV Hο       K9  HE؋PHE@9s2HE؋PHE@H5V щ¿       K   HE؋PHE@)UUHE@HE@HH9},HE؋@HU Hο       QK   HE@HE@HHE@H9~CHExHEHHEPHE@H5U AAȉщ¿       J3HE@t HU Hƿ       J    H]UHH0H}HEH@HEHEH@XHEHEH@@HEHHEHEH@HHtHE@u
       HE@tHE@xHEH t HmU Hƿ       J=HEH@HHu+HE t H]U Hƿ       I    UHH H}E   HEH=fEHEH   I     7  &  %                           }8tF      }etX   t   E   E   E    E   UE   E}UEgE    EUEMUE7E/HEHHS Hο       HUHHH}HE HUHE@HUBHE@HUBUHATSHPH}HEH/fEHEHQ         f       y    g    U     C  :  }@tj'    w      t        HEH HUHZ      E    HEH2HE3HE \HUHE@HHEPEHEE9E|ĸ      E    HEHHEFHEȋ HUȉHEȋ@HUȉBHEȋ@HUȉBEHEE9E|    $  HEHVHEHE HUHE@HUBHE@kHUB      E    HEH.HEFHEЋ 4HUЉHEЋ@ HUЉBHEЋ@HUЉBEHEE9E|    [  E    HEH+HE1HE؋ HU؉HE؋@HU؉BEHEE9E|Ƹ       HEHD HEHHDe       E    HEHHEFHE 3HUHE@HUBHE@
HUBEHEE9E|    ]HEHj HEHSډ    /HEH8HrO Hο       CHP[A\]UHH0H}HEH@HEHEH@ HEHE@HEHHE   HE@tHEH,HEH^E} yE   EHcHEHH9Es5HE؋@PHE؋@@HN Hƿ        B   HE@tHEHt
   HEH@ HUH)HE؉HE} tE[EHHEHE؋@@PHE؉P@HEHH9EHEH;Et HTN Hƿ        $B    UHH0H}uHU؉MUHEH蹢HEH} u/MHU؋EH5N AHщ¿        A    UHH H}uUUHEH!HEH} u'UEH5M щ¿        XA    UHHpH}HuUHEHEHE0UH=M HEHHE} tE  }  }{  }q  }   }  }S  }  }?  }   }+  }$  }  }  }  }  }s`}  }  }l  }  }  }   }tK}  }  }  HEHUHEH1E}   E  HEHmHEHEUHEHEEtEHEHUHEHE} 8  E9  HEH@HEHEHEE    bHEȋ0UH=K HEHHEEtEHEȋHUHEHFE} tE  EHEE;E|  HEHHEHEHNEE    ;HEЋ0UH=XK HEHHgE} tEB  EHEE;E|'  HEH!HEHEHEE    ;HE؋0UH=J HEHHE} tE  EHEE;E|  HEHUHEH!E} tE  HEPHEHCHEHEHf[  HEPEH5PJ щ¿        g=3  HEHHEHEHEE    bHE0UH=8J HEHHEEtEHEHUHEH@E} tE   EHEE;E|   HEH3HEHEHHEE    .HEUHEHE} tEIEHEE;E|1UEH5yI щ¿        @<    UHH0H}HEHEHE؋@PE=UHE؉Hq   HEUHMHEHHE} tEEE;Er    UHH}HE@PHE@@]UHH}HEH@H]UHHH}u} u	HYK QHE@P9EsHEH@HUH.HEHP HEHH0HE@PƋE)HHȋ HUHHH}uHE@PHE@@9Er2        UHEH>UHH0H}HEH@HHtHEH@H@p~HEH@H@p   HEH-EE      UHE؉HHEHEH   HE@tHE@umHEHE؉HHEH} tQE    8EHH    H.q HHEHH+u	HE@*EE
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y1. ؉LH臥LHH	   HEHƋHA    A          蘶HP ؉LH%HPuLHH[HEH0HP   HHXHXHtHEHHPHHHXHUdH+%(   t
zUHH0H}HuHUH} tHEH     HUHEHHHEHEHE} uHE,}tEHHHUHMHEHH'UHHH}HuHUHE    HMHUHHH}HuHMHE    HHHUHH   HhH`HXTDPdH%(   HE1HE(       Hyf)E)EfEHE(   HEHUHEHUHEHUHEHUHEHEE    HE    E    Hh@lxz;  HX tH` uW  HtHh    HH  HEH} uE  tHhPHhHUHT    H` uaǅx E||x9CEUHEHHppHEH} uEC  HEHEHE  H` t	H`HEHEH` t	HXEETEPEP tE   EtHUHEHHHhBlHh@l   T uǅT   H` u uE ؉EE  HHp( Hƿ        pH` u-HE t"HEH^( HHο        ;HEHJE:HUdH+%(   tuUHHH}HEA                HUHH}HE@l]UHH}uHEUPl]UHHH}HEH@XHt
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 HHHE.HһHEuHUHE    HHEHEHHEHUdH+%(   tjpUHSHH}HuUdH%(   HE1HEк       Hq           HEHU؃} tE   E؋EEHUЋEH։轶Eă} y	 ؉ +HUEH։HEȋEĉCHEHHUdH+%(   toH]UHH}HuHME    HΉUHH}E    tUHHH}HEH HtHEH]HEH@HtHEH@H-HEH@    HE@D    UHH0H}HE    EHEHtHEHf      HEH@@HIHEHEH@@H0HEH} 1  H} &  HEH@@HEHHHEHHBHEH@@HEHH HEHHHEH@@HEH@XHƿjo HEHEHtHEHE   HEHUHPHEHUHP HEH@@HEHP(HEH@X    HEHUHP`HEH@@uHE@hHEH@HHuHEH@@uHE@hHEH    (HEH:p HEHGHEH;EUHH H}HuHEH@HHt%HEH@HHUHHE}tETHEHtн8HEH@`HUHHkp E} yE褽HEPTEUHH H}HuHEH@HHt%HEH@HHUHHBE}tErHEH5t4VHEH@`HUHHp E} yE*HEH@`H3o HHEH@PHEPTEUHHH}HuHEH@@HEHp(HEH HUIA   H蛽UHATSHH}HEHHEHD`HEH辶D>HUBH[A\]UHH H}uHEH@PHEH-E} tE\HEH@HUHEH@ʉPHEH@HUHEH@ʉPHE@@PHEP@HE@PHE@@ЃUHH0H}HudH%(   HE1HEЋ u
       HEH@Ht9HEЋ HEH@HUHH  tHEHEЉ       HEЋHEH HlHHEH@HHiE} yEXHEH@Ht=EHcHEЋ HEH@A    A       H  E} tEUHEЉ    HUdH+%(   t?iUHHpH}HudH%(   HE1HEHaE} yE%   HEH@Ht   EHcHEH@HH
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UHH H}HuUHEHftMHUHEA       HUHHH}uUHEA    Ѻ    	   HUHHH}uUHEA    Ѻ    
   HzUHHH}uUHEA    Ѻ       HDUHH H}HuUHEHqt̤MHUHEA       HUHH H}HuUHEHtyMHUHEA      HUHH0H}HuU܉MHEHȤt#} t}t}taMHUHEA       H*E} ~0UHEH8HEEܺ    ƿ   贡HUBE袣UHH H}uEtu   HEHWtVsE   EHcHEHH^HEH} u#@HE                HUBUHEPUHEHUHH@H}HuЉUE    Ẻt詢?  HE؋@@u菢%  HEHPHEHEHit]   HEH?t>   E   EHcHEHHCHEH} u   HEH莢t!HUHEHHcE} yEjUHEUHEPHEHHEHEHHEH@HUHEH@ʉPHEH@HUHEH@ʉP    UHH@H}HuЉỦMHEHԡt/	  } t}t}t   Eȉt   HEHtҠ   E   EHcHEHHHEH} u蜠yHUHEHHE} yEXUHE           ]HUBUHEPHEH葝HEUHEUHE؉HUHH0H}HuUHEH蓠t   HEHtϟ   E   EHcHEHHHEH} u號`HUHEHH
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  UHH0H}؉uԉUdH%(   HE1HEHP0HEH@8H9uwHE   HEH@8HHEHUHEH9HBHEH@8HHEHP8HEHH8HEH@(   HH誈HEH} uQHEHUHP(HEHp(HEH@0HHHUHJ0HHEԉHEH@ UHHEЉ    HUdH+%(   t9UHH}E    2HEHP HEH@(MHcHHȋ HH EEHcHEH@0H9rHEH@0    HE@@ ]UHHH}HEH@H|  HEH@    HEH@HHEH@    HEH@ HHEH@     HEH@(HʴHEH@(    HEH貴UHH}HuHE]UHH}Hu    ]UHH}HuHUHEH;E]UHH@H}Huh      ^xHEHHEE    H} uH  H} t$HEH HvHE@tHPHEHEHUHH} tHEH Hv
HEH@    HUHBH&HE    HHկ  HUHBHEH@H节t$HEH@HhEHEH@    9  HEHEEHHHxHHEHPHEH@HuE   HEH@     E   sUHEH HLHEHEHuHEHtHEH@UHcHHE܉HEH@UHcHH EE;E|EHHHwHHEHP HEH@ Hu	E1E    HEH@ UHcHH EE;E|ِ} tHEHEHHHEUHHĀH}HuHUdH%(   HE1E       HEH PPEЉHEH HHEHMHE   HH E} t*E   HUHEHMHHщE} tErHEH HEH} uǃEHEH @@U9_HEH@Hu    .HEH@HUHMHHT9  E} tE    HUdH+%(   t4UHH0H}HuHEHEHE؋ E} tHEH @T9Es
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    *          4 HUHB`HEH@`H~tHEH@`Hr~E   HEH H@HHu'HEH@`H HH7 E}    HUH`HEHH%E} uhHEH H@`H5 HEH@`H$6 HHEH H@PHEH HUHR`HP`HEH@`    HEH @h    #HEH@`H~5 HEH@`    EUHHH}HE Hƿ    ;HEHE@HEHHHEHEUHHH}HE Hƿ    HEHE@HEHHHEHE@HEHHHEHEUHH}HuHEHE 9u+HEPHE@9uHEPHE@9u       ]UHH}HuHEHE 9uHEPHE@9u       ]UHHH}HE@EHEHHEUHEHHHEHEUHH H}HuHUHEHHt    HE@EHE@EE;EUHHH}HE Hƿ    WHEHEUHH0H}HuHEH{fEHEH}HEHEH}HEE    7HEHE 9uHEPHE@9t    HEHEEE9E|   UHH0H}HuHEHB{fEHEHh}HEHEHX}HEE    IHEHE 9u$HEPHE@9uHEPHE@9t    HEHEEE9E|   UHHH}HuHUHEHH>t    :HEHdzfuHUHEHHlHUHEHHUHHH}HEH|tHEH#zfu       UHHH}HuHEHt(HEHtHUHEHH?HEHE 9u'HEHw{tHEHg{t       UHH(H}HEH{HEHEHQyEHEHHEE    @HE HEHHrHEHE@HEHHVHEHEEE;ErHEUHH0H}HuHUHEHHft    ~HEHxfEHEHzHEHEHzHEE    7HEHE 9uHEPHE@9t    HEHEEE9E|   UHHH}HEH%zHEHEHEHEHE HEHH?HEHE@HEHH#HEHE@HEHHHEHEUHH H}HuHUHEHH(t    cHEHwyHEHEHgyHEHEHE 9u+HEPHE@9uHEPHE@9u       UHSHH}HuHUHEHHt    #HEHxXHEHx@9H]UHH(H}HEHHyHEHEHvfEHEHHEE    @HE HEHHHEHE@HEHHHEHEEE9E|HEUHH0H}HuHUHEHHt    ~HEHufEHEH{xHEHEHkxHEE    7HEHE 9uHEPHE@9t    HEHEEE9E|   UHH0H}HuHE؋HEЋ 9uHE؋PHEЋ@9t    lHEHufEHEHwHEHEHwHEE    %HEHE 9t    HEHEEE9E|Ҹ   UHH0H}HEH H@HHu
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      UHE؉HHEHEH@H@Ht\HEH@HXHEH@H@(AHEH@HHEH@HPHEHHDH6cHHH HE   HE       HEH@L@HEH@HPHEH HMHHAЄ   HEH@EHEH UȉHnwHEUHMHEHH6uWHEH*UȋMHEHẼ} yE   } t#HEH-HE@@uEȉEHEH@HEH} HEH@UHHEĉE;Eu!UHMHEHH?t    H@[A\]UHH H}E    1HEH PPEЉHEH{E} tEEHEH @@U9r    UHATSH`H}uEEHEH@UHHЋ u
  HEH@UHHЋ xUHEHb  HEH UHuHEHEH@UHH HEHZtN      L      	}t    HE؋PHEHE} yE  UHE؉PHEHJHEHEH@H@Ht\HEH@HXHEH@H@(AHEH@HHEH@HPHEHHDH_HHH HE   HE       HEH@L@HEH@HPHEH HMHHAЄtFHEH@EHEH UHtHEHUHEHHtEE  HEH@HEH} s  HE؋PHEHE} yE  UHE؉PHEHHEHEH@H@Ht\HEH@HXHEH@H@(AHEH@HHEH@HPHEHHDH^HHH HE   HE       HEH@L@HEH@HPHEH HMHHAЄtFHEH@EHEH UHrHEHUHEHH_tEE[  HEH@HEH} s?  HEHYHEHEHEHEE} yEM  UHEHEPHEHE} yE  UHEPHEHHEHEH@H@Ht\HEH@HXHEH@H@(AHEH@HHEH@HPHEHHDH]HHH HE   HE       HEH@L@HEH@HPHEH HMHHAЄtFHEH@EHEH UHIqHEHUHEHHtEE  HEH@HEH} s  HE؋PHEHE} yE  UHE؉PHEHUfEHEHXHEE    9HEЋPHEHqE} yEy  UHEЉPHEEE9E|HEHHEHEH@H@Ht\HEH@HXHEH@H@(AHEH@HHEH@HPHEHHDHV[HHH HE   HE    HEH@L@HEH@HPHEH HMHHAЄtCHEH@EHEH UHoHEHUHEHHt	EE HEH@HEH} vCHEH@UHHEE;Eu!UHMHEHHtEH`[A\]UHH H}E    1HEH PPEЉHEHE} yE6EHEH @@U9rHEH@H葁  HEH@        UHH0H}HuHEH HhEE      HEH UHAnHEHEH6SfEf}tf}   HEH@UHHЋ 9EulUHE HEA    A        H  E}u-HE HEA    A           H荃  E} t	EEE;E0    UHHPH}HuUdH%(   HE1HEH UHDmHEHEHaREHEH'RfEf}t
       HEH@UHHЋ 9Et
       HE HUHEHHτ  t    {HEHu    kHEHEH HlHEHEHQfEf}u} uf}u}t    HMHEH@UHHЉʉ    HUdH+%(   tUHH H}H0H    HH}  HEHEHPtHEH{P|HUHEHHFE} xME    1HEH PPEЉHMHEHHE} xEHEH @@U9rHEH^~  EUHH@H}HEH @PEHEH@      E   HEH@ UHcHHEEHEH @P9E|E    HEH @PE#HEH@ UHcHH EEHEH @@U9rHEH H@ HEE    HEH @PE   HEH@UHcHHЋE9   UHEH Hr/HEHEH\E} yE  EHcHMHEHHhVHEH@ UHcHHE؉HEH H@ HUHH)HEH HP0HEH @PƋE)HHЉʉEHHEEEEHEH @@U9HEH @PHEH U)ʉP@HEH P@HEH HP8HEH H@ HUH)HEH H@PHEH HH8HEH H@0   HH=QHEHEH H@8HtH} uiHEH HUHP0HEH HPHEH H@RPHEH H@PHEH H@@HEH H@PHEH ʉP    UHH H}HuHEHEHEHEHEHEH@ UHHЋ EEyHEU    UHHpH}dH%(   HE1E       HEH PPEЉHEH HgHEHMHE    HHݚ E} tME   HEHEHBEHEH@ UHHЋ EEy~HEUHEH踞 HEH} uEHEH @@U9<HEH@Hu    1HEH@HUHHH  E} tE    HUdH+%(   tN UHH   H$ H   dH%(   HE1HG HHQ H HW H(Hi H0H{ H8H H@H HHHɸ HPH       HƿXyAHH HHο        H`H^Oǅ      H    H衃HHHcJtH    HmHH uT ؉G  HHH5W HH¿        ̠O:  HHZ HHο       藠H  HH H`H   H   HǸ    0H      HƿdWuuH    Hl~HHH6J  HHH5 HH¿       ϟ uH=H Hƿ        芟NHUdH+%(   tZUHHpH}HudH%(   HE1HUH5c HEHHP   HǸ    /HUHEHHdHUdH+%(   tUHHPH}HuHUHEHHEHEH HExE    HEHHE:HEHHHEHUHH҉E܃} yE  EHE@HEHE@U9rHEPHE@HHEHEHHE@HH9EkHEHXHEHEH HEuE    HEHHE7HEHHHEHUHH҉E܃} yE\EHE@HEHE@U9rHEPHE@HHEHEHHE@HH9En    UHHPH}HuHUHEHHEHEH HE@HEHUHMHHщE܃} tE  HEPHE@HHEHEHHE@HH9ErHEH8HEHEH HE   HEHUHMHHщE܃} tE  E    HEHHEcHEHHHEHUHH҉E܃} tEX  HEHHHEHUHH҉E܃} tE/  EHE@HEHE@U9rHEPHE@HHEHEHHE@HH9EHEHXHEHEH HE   HEHUHMHHщE܃} tE   E    HEHHE7HEHHHEHUHH҉E܃} tE\EHE@HEHE@U9rHEPHE@HHEHEHHE@HH9EI    UHHpH}udH%(   HE1HEH UHk_HEHMHE    HHh E} :  ER  HE   HEHE@ 9  HEHPHE HHЋ    HEHEH H^HEHEHCS}tD9u4HEHEHPHE HHЉʉHEH DtB6HEHmCHE H5 щ¿        VHE u+HEHEHE} tE*HEHR HEH}     HUdH+%(   t=UHH@H}HEH@@PEHEH@HWEE    E     HEH@UHcHHЋ d  UHEH HU]HEHEHJBEHEHEH HFHE}?  }  }  }  }   }  }`  }x  }n  }B  }tR}T  }   }@  }6  }}N}t}    E     E߃W  HEHUHHrE  } t4HE +  HEHHEH@HUuH'E   HE    HEHUHHE   } t1HE    HEPHEH@HMHHbEwHE    HEHUHH诋EQ}    HEHUHH荋E/MUHEH5d AȉH¿        诖W} xMEPUHUHRMHcHHʉ
EHEȋ@ U9TEUHHpH}udH%(   HE1HEH@UHZHEHMHE    HH蚍 E} tnE   HEHPHE HHЋ t#HEHPHE HHЋ HE&HEHE@ 9rHEHE@()HEHEHT HEH} u    HUdH+%(   tCUHSH   HxHpHhdH%(   HE1HE    HE    HxHSEf)E)E)EE    HxHHEHp tHh tH} uC  kHEH} uCd  HxHIHEHY'E   H2HEHEHuE  HxHEHEHEHĹH    HHpj  HEHEH-=tEh  HEHREHEH@@EHx@PE"UHEHE}   EE;ErHEHBE}    HEHHEH} ut ؉E   HEHEHx@PE8UHxHWHEHUHEHHɇE} xEE;ErHEHE} xa]HEHQ)ÉډЉEHEHQEE   UHEH^E} xEE;Er
HEHlHEHi  } t$HEH]jHEHQjEaA!HpHUHHhHUH    HUdH+%(   t H]UHH}HEH@]UHHH}HuHEHUHPHHEHPHEPPHEH@PHE@TЉHEPTUHH H}HuHMHE    HH E} uHE@i Er@UHH H}HuHEHEHE EHEH @P9Es    UHEH HO9Er:HEHPHEH @PƋE)HE@ȉHHЋHE    UHH   HHH@<H0dH%(   HE1HE    HE    ǅX    ǅd    H0 t;H0HHH H0   H=tA?  HHH#HtHH@@`;H@ t>E  HHHN`ǅd   <;`t>	  <   H-HEH} uǅX  HHH@@   H-HEH} uǅX  HHH>~tǅX^  d\   \HH    H@HЋ hHH@P9hrHHHM9hrǅX  HH@Pd)hhH    HEHЋ tǅX  HHPP\ЉhH    HEH+d\\;<HHHEH@HEdEHEHxd\   \HH    HEHЋ hhHHHRHEHEHCllHcHMHxHH}cHxHE    HH XX   &HUHEHHXX c  HEH HEH} uËlHHx\\;< H0 t$H0H HvH0H@HpHǅp    Hp t0HUHDHpHHXX    HEHxǅ\    LHxH+EHHHH@0\HcHHЉʉHxHeBHHx\<+d\9rHEHfHHH@ HeHHHUHP     ,HEHeHEHeX:HUdH+%(   twUH}E]UHH}HEH]UHH}} y`UډEUHH}} y> EUH}uEUʉ]UHH0}HuHUH} tH} uv,  EIE}  9HUHMEHΉ,EHEHPHEH  EI   }  zE-  HH    HV HHEHUH=m HuHEHHHǸ    EHEHPHEH  EHH;Era    ZUH= HuHEHHǸ    EHEHPHEH  EHH;ErQ
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1HD$H   ËH   a1ÉڋH1AHH?ǅ         Ë   1Ë   1Éڋ##1HH    H HЉ   AË   -1Ë   1Éڋ3##1ȉ   Ë   1Ë   1Éڋ##1HH    H HЉ   #Ë   1Ë   1Éڋ3##1ȉ   Ë   1Ë   1Éڋ##1HH    Hv HЉ   Ë   1Ë   1Éڋ3##1ȉ   Ë   1Ë   l1Éڋ##1HH    HX HЉ   Ë   1Ë   1Éڋ3##1ȉ   vË   b1Ë   N1Éڋ##1HH    H: HЉ   Ë   1Ë   1Éڋ3##1ȉ   XË   D1Ë   01Éڋ##1HH    H HЉ   Ë   1Ë   1Éڋ3##1ȉ   :Ë   &1Ë   1Éڋ##1HH    H HЉ   Ë   y1Ë   e1Éڋ3##1ȉ   Ë   1Ë   1Éڋ##1HH    H HЉ   oË   [1Ë   G1Éڋ3##1ȉ? HHHHHHʉHHHHʉHHHHʉHHHHʉHHHHʉHHHHʉHHHHʉH@HxHPHxHHEdH+%(   tHĀ  [A\]UHH   H(H HdH%(   HE1ǅPg	jǅTgǅXrn<ǅ\:Oǅ`RQǅdhǅhكǅl[H HHH@Hǅp    Hǅx    HE    HE    HE    HE    HE    HE    HE    HE    HE    HE    HE    HE    HE    HE    H ?HHH HHH(HPHH<H H+HHH(HHHHpHHAJHpHHH ǅ<@   <HcHHHH	<Hc    HH<HHHHHHHPHpHH@HHHHHHpHPHHbǅ8    68HcHH8HPH։88vHEdH+%(   t*UHH}HuHE t    HEHmH} ݸ   ]UHH H}HuHUHMH}w+HUHEH5 HH¿        r    THEH+EHHUHEHHH]t'HEH HHο        pr       UHH}} yZjUډEUHH}HEH]UHHH}HEH UHHH}HEH UHHH}HEH UHHH}HEHH UHH}HEH]UHH}HE HHEH]UHSH8H}؉uHUȉMHE؋ EЃ=   v
   H} } 1Єt
   HEHrHEEԉHEfPEЍPHEfH} t'EHcHEH)HHEHHHFHE؋ HE HE؉    H]UHH H}uHEHHEÈHE        Ht    HEUHHH}HuHEHH+EHEfUHH@H}ȉudH%(   HE1E   HE       HfE Eĉ¾     E} yg    HUEA   HѺ     AGyH Hƿ        voHME   HΉyeg ؉EME   HUHMEHΉ Dy7g ؉EE܃t	E\UHEȉEEuEHUdH+%(   tUHH}ECUHH }HuUUHMEHΉE} yf tf t˃} yzf EUHH H}uEHcHEH HHHEH} uHEHUHEHcHEHP    UHH   }uUHxLpLhdH%(   HE1HE    HE    f)E)E)EfEHEHEHE   EHE    HE} *    E HME"   HΉE} yEE  EHHUH9sUHEHE}   HME    HΉ:E} yEE  }   HEHE.  HE@9EtEUy  HEPE9tET_  HE@tEHE@ttAHx    <HEHHEHE t|HE EHEH   E       HhHpHELxHHAЉE}t}   } t}v   E       MHE )ЉEHE HE}~HE vHE U9} tEH Hο        ]k} tE    HEHREEHUdH+%(   tUHHPH}؉uHUHMLEdH%(   HE1E    UHEHE} yE   HE@        }YHE؉PHE؋ Hu؋E    9KHyb ؉E2HE؋@AuH}HMHUȋEIIHD҉EEE^EHUdH+%(   tUHH`H}HuHUdH%(   HE1HEHHEHEHHEHEHEHE HUHEA       HHEHu    HEHHUf   HUdH+%(   thUHH   H8H(f4dH%(   HE1HP       HHHHǅP   fǅT fǅV ƅ`ƅa4H8HP   HPLL yL*H(HHPIȹ       H{HUdH+%(   tpUHH   <840dH%(   HE1HP       HǅP    fǅV fǅT ƅ` <dHP+   HPHHHH u
   H8HP      H,DD yD   0t:H0HP      HDD yD   0t7H4HP      HDD yD=HHHPHHHPA                HHUdH+%(   tUHH0}uUHMH} t2HEHHk HEؾ   H}tZH} tHEH HvHE؋@EE    } tMEMUuEEEUHH}uHUHMUEr`UHH`  HHHdH%(   HE1HHHH  HHHHHA    B   HItS%HHHLHHAHUdH+%(   tUHH   H}HuHxdH%(   HE1HEHEHEHEHE tHEHE@9t
      HxHX  H Hu
       HxHX  HHE       HE} tE   HEHu
       HEHHUBHE@u    uHEHtHEHHUBHEHtHEHHUBHEHtHEHHUBHEHtHEHHUB    HUdH+%(   tUHH   HHH@H8dH%(   HE1HHHHXHXHH`H8HhHH H`HpA       HHxHt	HEHu    hHxHTHh 9Tt    ;HEHHhHBHEHtHEHHhB   HUdH+%(   tRUHH  HdH%(   HE1HP       HHHHǅP    fǅT fǅVƅ`f) )0fօ@Hǅ    Hǅ    H t;HHH H,   Ht*  v  #t   $H HHHPI    H th  H t HH Hv(HPH t HH Hv,HPH t HH Hv0HPH t HH Hv4HPH t!HH Hv8HPH tHH H'w
      H
H~ H¾   H8 y/uHH@     <  /  HP       H7ǅP   fǅV 
fTƅ`ƅaHHP      H y   HHKHPIȹ       H tA^H t"HH H'vHHHP H t"HH H+vHP(    HUdH+%(   tUHH   |xHpdH%(   HE1HE0       Hļf)E)E)EHE0   HEHUHEHUHEHUHEHUHEHUHEHUHUx|ΉE} tE   xE<tx uUHp^xtUHpCxtUHp(xtUHpHp         HUdH+%(   t辺UHHH}HuHE@HE@  H{ HE      H UHH H}HuH} tHEH HvHEH@HEHE    H} tHEH Hv	HE@HUBH} tHEH Hv	HE@    HUBHEHHUHE   HHUHH}HuH} tHEH Hv	HE@    tYwiwu	^t=WH} tHEH HvHE@t6HEHH    !HEHH    ]UH}Hu}w} u
D}t-<HE t8}uHEHE u    ]UHH   H840dH%(   HE1HHH8HHDD yD   HP       HǅP$   0fV4fTƅ` H8 tH8H HvH8@    dHHH8HPHHщDD yD$HPA                HbHUdH+%(   tWUHHH}HE   $   HUHHH}HE    %   HhUHH H}H} tLH} t&HEHHw HE    HuH} tHEH HvHE@HHEH5EE-UHHH}H} tLH} t&HEHHqw HE    HNuH} tHEH HvHE@   H} tHEH Hv	HE@    t@w\tKwRwu	Gt!@HE       H	  T+HEHi?3
'UHSH   HhH`HXȈTdH%(   HE1HhHxHx tHxH Hu
F  T tHx@t
$  HXHH Hu
      HXHHHE       HHEHu
   HxH Ht,HxH H HvHEHxHHxCHxH Ht*HxH H HvHxH H`RPHxH Ht-HxH H HvH`PHxH PHx@T t      HUdH+%(   t讳H]UHH   HXHPHHdH%(   HE1HXHHhHX $HhHPHpA       H9HxHu    7HX@HpHhHHHqHUdH+%(   tҲUHH   HdH%(   HE1ǅ   H     HoHH HΉ y   HH      H y   H HH@H#s HA   HǸ     yK 8=   v$HHH   HHUdH+%(   tsUHSH  HHdH%(   HE1Hǅ0    Hǅ8    H tvH tlH t,HHH!r H    Hu6H t;HHHq H   HtT  H t"HH HvH@
ǅ    H tHH HvH@     H t"HH HvH@
ǅ    H t"HH HvH@
ǅ    H t"HH HvH@
ǅ    H t"HH HvH@
ǅ    H t"HH HvH@
ǅ    H t"HH HvH@
ǅ     ~ t	 t    vd  vLz  tǅ   
ǅ   ǅ    H@       HAǅ@$   ffFfǅD, ƅP TXË 	؉`H H։$$ y$e   \Hn H@      H$$ y$F  H@   HH(H( u  H@HH$$ y$   ǅ   HH@      HX$$ y$a   H(H@HHUHH0H0HH@Iȹ        HR$$ y$ 8t$HUdH+%(   t	H]UHSH  HH ЈdH%(   HE1ǅ    H tlH t,HHHl H    Hu6H  t6H HHl H    Het
l  H t"HH HvH@0
ǅ0    H tHH HvH@    H t"HH HvH@4
ǅ4    H  t"H H HvH @ 
ǅ     H  t"H H HvH @$
ǅ$    H  t"H H HvH @8
ǅ8    H  t"H H HvH @(
ǅ(    H  t"H H HvH @,
ǅ,    0 ~, u8 u	( t
  $  v
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S  ǅ     u	$ t
+  H@       Hکǅ@$   fǅF fǅD- ƅP 0Tt2 X$Ëv	؉`4HH։U<< y<u\t7Hni H@      H<< y<$H@A                HHUdH+%(   tħH]UHH H}HuH} uI%HMHE    HH|EE"UHSH  HHdH%(   HE1Hǅ0    Hǅ8    H tvH tlH t,HHH h H    Hu6H t;HHHg H   HtS  H t"HH HvH@
ǅ    H tHH HvH@    H t"HH HvH@ 
ǅ     H t"HH HvH@
ǅ    H t"HH HvH@
ǅ    H t"HH HvH@$
ǅ$    H t"HH HvH@
ǅ    H t"HH HvH@
ǅ     ~- u$$ u u t	 uc    vH|  ǅ(   H@       H`ǅ@$   fǅF fǅD. ƅP TXË(
	؉` HH։,, y,   \He H@      H6,, y,?vHH0H0HH@Iȹ        HL,, y, 8t,HUdH+%(   tH]UHH}HuHUHEH@HEHEHEHEHHEH H9_  HEH@     HEȋ@$EHEȋ@ EE    E   E      HEȋ@,HEHEH HEHEHEEH    HEHHHEH H9   HEH@UHHEԉE܃H    HEHH HUH)HBU܃H    HUHʋH9   HEH@U܃HHE+E؉EԉE؃EHEH H9EsLEE;EsE;EE;Eu/HEH@UHHE+E؉    ]UHHH}H} tMHEH HXHEH@HHHEH@H8HEH@H(HEHUHH0H}HE؋   E} u:        [  HE؋   w:        7  0      HEH} u:          HEUP HE؋   HEP(EHUR(HHEHEHHHEHHEH H  HEH   HHEH HUHHHE؋@hE} tTHEH   HtDHE؋   9Eu5HE؋   v&HE؋@l9EuHEH@pHtHEH@xHu	HE"  HEUP$HE؋   HEP,EHUR,HHEHEHHHEHPHEH@H   HEH   HHEH@HUHH
EHHHHEHPHEH@Ht\EHHHHEHPHEH@Ht8HEH@xHHEH@pHHEHHuHE)
HEHt8        UHHPH}HuUMHEȋ@$9ErG8          HEH@UHHЋ E؋E;Er8           HEH@UHHЋEЉEHEȋ@,EHEHPEEHHEHEHEHEH H9Es7        rE)EHEȋ@(EHEHEEHHEE    'HEH H9Er$EHEEHEHEHEEE;ErEHHHEHUHH0H}؉uԉUHE؋@ EE;Er6           HE؋@(EHEHEEHHEHEHEHE 9Es6        HE)EE    HE 9ErEHEHEHEEE;ErEHHHEHUHH}} yG6UډEUHH0dH%(   HE1HA] HEHE      Hƿt
       H%] HEHH7HEH} u    cH}HMHUH5\ HEIHǸ    荗EHEH^}t     EEE   9GHUdH+%(   t-UHH0H}dH%(   HE1HEH   Hp\ HH`HEH} u    SH}HMHUH5H\ HEIHǸ    t     EEE   9GHUdH+%(   twUHH  dH%(   HE17ll tl   HpH)HpHll tloLhHdH`H5t[ HpH   HH¸    t    )`dh   9GHUdH+%(   t耙UHH   H$ H`  HHHLdH%(   HE1Hx       H	H HAHp       HHHǅpx   DHHHpHxHHHHH HHHHHHHH H(HHH0H8HHH@HHHHHPHXHH`ǅ    Hǅ     k   j  9  P  F  6  Z                              }  f  tBP  C  @  3  t2  ǅ
     ǅ     ǅ$         ǅ      HHPǅL   ǅH   uǅ   
ǅ   ǅ   ǅHdW HuHHPǅL   ǅH   ǅ   ǅHFW H/ǅ   #ǅǅ-      HHHH5W IIHH    )/ ؉ xy tT y;t    DH t%HHHHHu       HUdH+%(   tjUHH@}HudH%(   HE1EEEEEfE  E    EEEEEfE  E    HE   H} t*HUHuEA        FEԋEԉzHUdH+%(   t裓UHH   HhH`HXHPDLdH%(   HE1f)EfEfEEE   H`EH`EHPEHE(       HL t       Lf)E)EfEHE(   UEHEHUHEHUHEHUHEHUHEHEUEEЉppHHIHxHx u
   HMHx   HHc
EEHxHHhHH=
EƋEEHHxHHXHHH
pHcHUHxHH
tHxHtHUdH+%(   t譑UHHĀdH%(   HE1H bpf_spiHn_lock vHEHUH_lock vaHl cnt l HEHUE    E   E   E   E   E  E   E   E   E    E   E  E   E   E   E    E   E   E    HUHEA       L   HHUdH+%(   t蟐UHH   ,dH%(   HE1H`H       HPf)E)E)E)EfEHEH   HEHUH`HhHEHUHpHxHEHUHEHUHEHUHEHUHEHEǅD    ǅH    ǅLǅPǅTǅX    ǅ\    ǅ8   ǅ<   ǅ@   ,"  ,"!  ,!  ,!  ,   ,   ,<  ,  ,h  ,  ,  ,  ,  ,  ,  ,k  ,h  ,Q  ,K  ,7  ,*  ,  ,   ,  ,   ,  ,   ,  ,  ,  ,t^,  ,
  ,  ,w, y  j  ,]  ǅ<   \  ǅ8   ǅ<   ǅ|   9  ǅ8   ǅ<   ǅ@      ǅ8      ǅD   ǅH   ǅ<   ǅ@    ǅ|   cPP    P  ǅ8    ǅ<       @   ǅt   EǅXlǅ8    ǅ@   Vǅ8    ǅ<    ǅ@   HE    ǅ|   $ǅ8   ǅ<   N  ,t	,uDA    A                WTT    TxP x$PhDlHp@<8H`,IA    L% ؉\L xLT xTֵP xPX t%L y\;Xu       LHUdH+%(   tUHH }HuH} t}EEEdUHH   H$ H@HdH%(   HE1ƅfǅ  ƅfǅ  ǅ    Hǅ   H t   w
   ƅ HHHA    y*o uaH9K HHHHu<H)K HHHHuHK HHHwHt       HUdH+%(   tUHH}HE]UHH}H} HuHEH= Ht       ]UHH}u} u    "HEH|Jy7Hи@   +EHH]UHH}HuHEHHEHPHEHUH]UHH}HuHEHPHEHHEH@    ]UHH}HuHUHMHEHUHHEHUHPHEHUHPHEH@    HEH@     HEH@(    HEH@0    ]UHH0H}HuHUؿ8   -HEH} uHvHMHUHuHEH?HEUHH0H}HE    QHEH@HUHHH HEHEH$HEHEH} tHEH@HE   uHEHEH@ H9ErHEH@HHEH@    HEH@0    HEHP0HEHP(HEHP(HEHP UHHH}HEHuHEHHEHjUHH}HEH@0]UHH}HEH@ ]UHH}HEH@ Ht-HEH@0HHHHHHEH@ H9s       ]UHSHXH}HEH@(HHEH}wHE   HE   HHHEHEо   HHEH} u
   HE       HEH@HUHHH HE\HEHEHHEHPHEH HHщH\HEHEH    HEHHEHHrHEHEH} tHEH@HE   uHEHEH@ H9EUHEHUHP HEHUHP(HEH@H HEHUHP    H]UHH@H}HuHUHMLEHEH@Hu
       HEH@HUHHHEHEH HEdHEL@HEHPHEH HMHHAЄt$H} tHEHUHHEHUH   $HEHHEHEH@HEH} u    UHSHXH}HuHUMLELMdH%(   HE1H} tHEH     H} tHEH     HEH@(HEHHEHPHEHHщHiHE}   HMHUHuHEIȹ    HthH} tHEHHEHH} tHEHPHEH}t}u!HEHUHHEHUHP       } u
   }u
   HEH>tPHEHEԃ} tE   HEH@(HEHHEHPHEHHщHcHE   HEHEHuRHEHUHHEHUHPHEHUHRHMHHHHDHEH@0HPHEHP0    HUdH+%(   toH]UHSHHH}HuHUdH%(   HE1HEH@(HEHHEHPHEHHщH~HEHMHUHuHEIȹ    Ht    H} tHEHPHEH   HUdH+%(   t豀H]UHSHHH}HuHUHMdH%(   HE1HEH@(HEHHEHPHEHHщHHEH}HMHUHuHEIHt    cH} tHEHHEHH} tHEHPHEHHUHEHHHEHHEH@0HPHEHP0   HUdH+%(   tH]UHH}HE]UHH}HEH= H]UHH}H} HuHEH= Ht       ]UHH}HE@]UHH}HE@]UHH}HE@]UHHH}HEHfUHHH}HEHfUHHH}HEHgfUHHH}HEHFfEf}tf}u       UHHH}HEHfUHHH}HEHfUHHH}HEHfEf}	tf}
tf}tf}u       UHHH}HEHfUHHH}HEH_fUHH}HEH ]UHH}HEH]UHH}HEH]UHH}HEH]UHH}HEHEHEH H HHEH H	]UHH}HEH]UHH H}uHEHHUHHHHHHEHEHE} tHE@% HE@UHH H}uHEHrHUHHHHHHEHEHFE} tHE@    UHH}HEH]UHH}HEH]UHH}HEH]UHH}HE    (HUHHH)HHE HHHEHEHE uHE]UHH0H}HuHUdH%(   HE1    HEHeq   HEHȃHt    HUHEHHDtHUdH+%(   t@{UHH}HuHUH} t[HmHE     HUHEHHMHUH HEHEH;EsHUHEH uHUHEH  ]UHH}HuHE t    HEHmH} ݸ   ]UHH H}HuHUHMH}w+HUHEH5< HH¿        `    THEH+EHHUHEHHH]t'HEHd< HHο               UHH}} yUډEUHH}Uډ    UH}EH   H9s   EHH)H; HH; ]UHHH}HuHEHSUHH H}HuHUHUHEHHhUHHH}uHEH UHUHH   H(H H`HhLpLxt )E)M)U)])e)m)u)}dH%(   HH1ǅ0   ǅ40   HEH8HPH@H(L@H(H@H0H HHAАHHdH+%(   txUHH0H}HuHUHMH} t5HEHHt: HEо   HBtk  H} uU        HEH} u,  HEHUHHEHUHPHEHUHPHEHoHt   HEPHH    HHHUHBhHEH@hHpt!HEH@hHNEHEH@h    wHH\    HH2HUHBpHEH@pHt!HEH@pHEHEH@p    HEH(   E} uHEHEHuEUHH H}HEH HEHE@ 9E
       EHHUHr0HUHz(H   t
   EHHUHr@HUHz8H   LtZHE@ u&HEH@(HEH@(HEHq  E} tEHEUP     UHH H}H} tiHE    CHEH@HUHHH HEHEH H:HEH@HEH} uHEHEH@ H9ErHEHfUHH H}HEHC   HEH@(HHEH@8HtVE    AHEH@8UHcHHH Ht HEH@8UHcHHH H|EHE@ 9E~HEH@8H\HEH@HHLHEH@XH<HEH@hHHEH@pHHEHUHH H}uHEH H9Er   HEHIE} tE~HE@T    MHE    H  E} yE_HE    .HEH@HUHcHHЋHE    H  EHE@T9E|Ƹ    UHHPH}HEH HEHE@ E_  UHEH HlHEHEHfEHEHf  
               tm  $      }D         t@t  r  b  HEHP(HE@HH@E  HEH<HEHEHP(HE@HH@HEHP(HE HH@   HEHRHEE    )HEHP(HE؋@HH@EHEE9E|   HEHHEE    )HEHP(HE@HH@EHEE9E|THEHHEE    (HEHP(HE HH@EHEE9E|EE;E    UHH0H}؉udH%(   HE1HE؋PTHE؋@P9|xE   HE؋PPЉEUE9MHHEHEH@HHM   HH&HEH} uFHEHUHPHHEHE؉PPHEHpHHE؋@THHU؉JTHHHEԉ    HUdH+%(   tqoUHH@H}ȉuĉЈEHEH@(UHHHEHE <u
   z  HEH UĉHŚHEHE <uRHEHct} tHE t
    *  EHo1 Hο          HEHo!                   p      U  p  g  	v    L  C  v  1     te  t
t  HE      HEHHEȺ   HEHEE  HEHHEȺ    H  HEH8HE} tHE t
    s  HEHEHfEE    4HEHHEȺ    HqE؃} yE   EHEE9E|HE t"UHEȉHDE؃} yE  HE     HE uHE @u"UHEȉHE؃} tE  HE   v  UHEHHEȉHE܃} yEL  } t} u
    6  UHEȉHvE؃} tE  HEH@(UHH      UHEHHEȉH   HEH:HEUHEHHEȉHE؃} yE   } EHEHfEE    :UHEHHEȉHE؃} yEK} ~EEHEE9E|E)HEH@(UHH    UHH H}uHEH UH6HEHE u    .HEHEH<HH- HHUHHPH}uUHEH@(UHHHE} EHE <#  HEH UH蕕HEHEHfEHE <  HE   E΃
}   t|   E;E  HE u#EHP, Hο        n  HUMHEH	  HI, HEHHǸ    /HEXUHEH[t3HUuHE    H  H+ HEHHǸ    HE  E΃         H      	   W        teq  h       M  t
t{>  HUMHEH  HE  } t3HUuHE    Hj  H* HEHHǸ    HE  HEHUHEH<  HEHUHEH  HUMHEH  HF* HEHHǸ    ,HED  HEHEHUHEHHE uKUHEHt3HUuHE    H  H) HEHHǸ    HE  HE} u
HE umHEHIHEHEH"fEHE uEEEEE    !UHEHHEHEHEE9E|RHE uDE;Et<HUMHEH  H( HEHHǸ    HE} tGHUuHE    H  H( HEHHǸ    mHE   HEwHEHHEHEHfEHEHUHEHE    !HEHUHEHEHEE9E|
UHHPH}ȉuHUdH%(   HE1E   HEHHEHEHbfEE    ~HEPHEȉH菏EUHEHE} t)} u#HE@UѺ    Ѕt   UEE؋EE܋U܋E9MEEHEE9EuHE@u    щȅt       HUdH+%(   tcUHSH   Hhd`\DDTXdH%(   HE1f)E)E)E)EH]& HEHh@EHG& HEE    H9& HEE   H-& HEE   E    E    HE    d;`  E    bEHHH@HHH EEHHH@HHPH HEEEEPdЙ}EEE;`~EEvE;d  E;`  X uUE;`u'\EEPdЙ}E;Eu#E;`tk`+EE+d9SX tE+d    THHUH5$ HhAHHHǸ    Ed  `+dxE||x9NEE;EuITHǋMHUH5W$ HhAHHHǸ    Ed   E      EHHH@HHPH HEEHHH@HHH EE;E|FT HǋMHUH5# HhAHHHǸ    Edm} od;`HEdH+%(   t@`H]UHATSH H}uHU؋UHEH^  IHE؋ t	H,# H%# HEH1t	H# H# H5# H}MHH¸    H [A\]UHHpH}uHUMdH%(   HE1HEHmHEHEHEE E    HEH,fEHEH UHcÈ} t&HEH HUMHHt       EUHEH:  HHE t	H" H" } t	H! H! H5! H}IHH¸    E      HEHEHYHEUHEHEЋUHEH[EԀ} uHEPHEH H`EE   } t} t       EeED@}MȋUԋuHEEAH1E!HH! HEHHǸ    EHHEpHUHEHB
  } t/UH  HEHHǸ    {UԋEЉEELHE    HEPHEH HHEHUHEH9HMEЋEЍ    EЉEE Hi  HEHHǸ    EHEE9EW} t1EHHE@ǋŰuHEAA    щH f} uHE@tEH HEHHǸ    EHH HEHHǸ    aH HEHHǸ    D} tH HEHHǸ    #HEdH+%(   t\UHH0H}uHU؋UHEH+  HEE    cEHHHH<q HHEHHu5EHHHHq HHMH5n HEHǸ    zEEvUHH H}uHUUHEH  HH* HEHHǸ    "UHSHXH}HuUfEHEHHEHEHEE       HEЋHEHHEHEHHpHUHEHH  HEH}v`} tH HEH HEHEЋXEHHMHUHuHEAIHHHǸ    :W} tHK HEHJ HEHEЋXEMHHUHuHEAHHHǸ    EHEE9EH]UHHPH}HuUfEHEHDHEHEHtEE      HE؋HEȉH>HEHEHHpHUHEHHl  HEHEHHEH}v]} tHX HEHa HEEIHLEHMHUHuHEMIHHHǸ    T} tH( HEH+ HEEHHMHUHuHEIHHHǸ    |EHEE9EUHH0H}uHU؉MHEHfEUHEHn  HHE؋ t	H< H5 H5 H}HH¸    f} T  Hl HEHHǸ    HEH\tMUHuHEHMUHuHEHEHH HEHHǸ    aHE؋@u H HEHHǸ    :   HE؋@   HE@   HEHtELEE    6HEHHEHcHHHHHȋ@tE EE9E|} tHZ HEHHǸ    UHH0H}uHU؋UHEH  HEHEH?t!HUH HEHHǸ    2HUH HEHHǸ    UHH0H}uHU؉MUHEHX  HEHE؋@u7H HEHHuH HEHHǸ    5H HEHHǸ    HE؋pMHUHEH  UHH0H}؉udH%(   HE1HE؋PdHE؋@`9|xE   HE؋P`ЉEUE9MHHEHEH@XHM   HH&HEH} uFHEHUHPXHEHE؉P`HEHpXHE؋@dHHU؉JdHHHEԉ    HUdH+%(   tqTUHH0H}uHUH} t5HEHHu HEؾ   Ht0   HEHE} tE   H} tHEH HvHEH@HEH HEH} tHEH HvHE؋@EE    H} tHEH Hv
HE@    HUBMHUuHEH   HE@     UHHPH}ȉuHUMdH%(   HE1HEȋ@dEHEH UĉH~HEHE@tHEHuOUHEȉHEԃ} y8Eԉ1kHH Hƿ        HEȋUЉPd  }    HEHO   itE_   Qt-GB	}8}it)tZuHE؋@EAHEH E.HEHUH5r щ¿        	HEH@XUHcHHHEHEȋ@d+EЉEMHUHuHEH  HEȋUЉPdHEdH+%(   tyQUHH H}Hu   HEHHE@HHHHЋ EHEH UH|HEHEHtO   	t
txH HEHHǸ    9H HEHHǸ    H HEHHǸ    HE@PHEPHE@)UHH H}Hu\HEHHE@HHHHЋ EHEH UH{HEHEHuHE@PHEPHE@uUHH0H}HuЈEHE tE܃t       Ee} t	H H HUH5q H}HH¸    UHH`H}HuHUMEu  HEHHE@HHEHHE@HHHЋ EЃ} u7HUHEHHH HEHHǸ    	E   HEH UЉHzHEHEHfEEȃ           {    i    W  
_  
E  	-  	3    !  _           }t    t    HUHEHH[HEHEHHEHUH HEHHǸ      HUHEHHHE u*HE@tMHUuHEHW  HUMHEH =  HUHEHHHE u*HE@tMHUuHEH  HUMHEHy  HUHEHHJHUMHEH'  HUHEHHUHEH 	  HHW HEHHǸ    mh  } t	H4 H- H5! HMHHϸ    72  H	 HEHHǸ      H HEHHǸ      H HEHHǸ      HUHEHH@HEHEHHEHEHt$HUH HEHHǸ    xs  HUHx HEHHǸ    TO  HEHHEHUHEHHHE@u>UHMHEHHHEPH1 HEHHǸ      HEHHE@HHHHЋ EHEH UԉHWvHEHEHEHE t&EƃtH HEHHǸ    kEǃtH HEHHǸ    EMHUHuHEHEǃtHX HEHHǸ    HEPH/ HEHHǸ      HEHHEHEHfEHUHEHH$HE@tOH HEHHǸ    MHUHuHEHH HEHHǸ    VUHMHEHH5Hp HEHHǸ    "f} tf}u+HE؋@u HC HEHHǸ      E       } ~H HEHHǸ    Eʃ9Eu(HE؋@uH HEHHǸ    HHE؋HEHKHEHE؋pMHUHEHEHEE9EcHu HEHHǸ    %TEȋUH5 щ¿        1f}EHE@|UHMHEHHUHH H}uЈEHEH@x@4   HEH UH5sHEHEH   HEH   } tH HEHHǸ    @HE@HE@HT
 uHE    HHE@ HE@ } t!H4 HEHHǸ    UHHPH}HuHUdH%(   HE1HE    HEH蹕HEH} u   tHMHUHEHHHEHHEHEHHuHUHEA    Iй   HHE܃} tHEHSHEHGHEHUdH+%(   tEUHSHxH}uHUdH%(   HE1HEH@(UHHHEHEH UH\qHEHEHEHsHEHEH@8UHHHEHE uH   HE  t!HEH HtHEH s  HEj  HEHu!HEHt&HEHfuHE HE$  HUHMHEHHHEH}   HHHE   HEHHEظ   HPHEHо       HHkHH HH)H9tH   H$   H  H)H  Ht%  HHH HHEHMHUH=}
 HuHEIHHHǸ    vHEHHHEHHHE HEH Ht	HEH HEHUdH+%(   tCH]UHHH}uHEHPhMHEHUHHH}uHEHPpMHEHZUHH}HEH@x@uHEH@x@0u	HV Hv ]UHH}HEH@x@0u	H) HL	 ]UHH H}HEH@x@HEH@x@0ЉEHEH@x@u>E    +HEH@xHPHn HEHHǸ    EE;E|UHH H}HuUHEHH HEHHǸ    2UHHPH}HuHUȉDLMEĉЈEHEHEHE    EăEUEЃPHEUHEHHEH@xH H9s
   HEЋ@v,HEЋ@H Hο           HEЋ@E)HEHHEHcHEH HHEm} yUEЈEU@   )fEU@   )fEEHUHEHHEH    UHH@H}HuHUȉDEĉЈEdH%(   HE1}MLEHUHuHEMAH^E} tEHEHu    HUdH+%(   tJ@UHSHHH}HuHUDEЈEdH%(   HE1}MLEHUHuHEMAHE܃} tEBHEH~HHEHHHUH5S HEIHǸ        HUdH+%(   t?H]UHH0H}HuUHMHEH&fuHE@E
HE@E} ~}~'U܋EH5 щ¿        &,EHcH  HEHH^u    UHH0H}uHU؋UHEHiE} u    HE؋UHcʺ    HHHHUHSHhH}HuUHMDEdH%(   HE1HEHEEEHE@E} tEv*UEH5 щ¿          HEH HUMHt!EHcHMHEHHӵHEHE}tK}&  }   }  }g  }  }w  }    HEHEHEH HEHEHH HEH} uBHEHHHEHHHUH5 HEIHǸ      HEHHHEHHHMHUH5 HEIIHǸ    Y  } tEHEHOHHEH}HHEHH5f HEIHǸ    x  HEH
HHEH8HHEHH5* HEIHǸ    3  } tDHEHHHEHHHEH5 HEIHǸ      HEH{HHEHHHEH5 HEIHǸ    ;  } tHHEH1HHEH_HHE H5W HEIHǸ    W  HEHHHEHHHE H5 HEIHǸ      HEH@x@6   HEH@x@5|  HE uJHEHnHHEHHH5 HEHHǸ    HEH@x@5(  4HHE HHH % @  tHHEHHHEH*HHE H59 HEIHǸ    "   } tEHEHHHEHHHE H5  HEIHǸ    mHEHiHHEHHHE H5  HEIHǸ    (UEH5  щ¿        w    HUdH+%(   tD9H]UHSHXH}HuUHMdH%(   HE1HEHEHE@EHEH HUMH
t!EHcHMHEHHٰHEHEȃ}t}  }   }tU   HEH;HHEHiHHE(H5 HEHd$<$HHǸ    ]H   HEHHHEHHHEH0H=f HEHfHnHHǸ   HEHHHEHHHE fZfH~H= HEHfHnHHǸ   贾'UEH5E щ¿            HUdH+%(   tj7H]UHH@H}HuЉUHMHEH E} t}tHx HEHs HEH< HEHUH HEHHǸ    HEЋ@EHEH UHwbHEMHEغ    HHEЋHE؉HxHH HEHHǸ    能HuMHUHEHj A    I    H  HUHH@H}HuЉUHMHEH豸HEHEHEE    9UHEHHEH@xH H9r
  UHEH tEHE@9ErHE@9Eu
   HEHH	 HEHHǸ    葼E    UHEH E} t{/H HUHH % @  t!UH HEHHǸ    1"EH HEHHǸ    EHE@9EqHS HEHHǸ    ۻ    UHSHXH}HuUHMHEH2HEHE؋ EHEH MԺ    HrHEHEH UԉH\HEH} ,UHEH5 H¿        K  HEH,tHH}uAHEH@x@t%HMUHuHEHu
    Y  HEH@x@6HEH@xP0P0HEHeHH^ HEHHǸ    褺HEH@x@4EHEH@x@4HEH@x@5EHEH@x@5 E    KHEH@x@5uIHuMHUHEHj A    I    H[  HEHEHEHE؋@9ErHEH@xUΈP4HEH@xUψP5HEH@xP0P0HEHHEHgHHEHHH5U HEHHǸ    藹    H]UHSHXH}HuUHMHEHTHEHEH-fEE    HEH@xP0P0HEHHH HEHHǸ    E       HE؋PHEH H]HEHE؋HEH詸HEUHEH迴EԋUHEHE}ɋEAEHELHE؋HHUHuHEHWH  HEЃ} yEoEHEE9E<HEH@xP0P0HEH.HEHHHEHHH5 HEHHǸ    EH]UHSH8H}HuЉUHMdH%(   HE1HEH HUM̉HtQHE؋@uEHEH#HHEHQHHEHH5 HEIHǸ    L   HE؋@HcHMHEHH2HE؋@u>HEHHHEHHUH5 HEIHǸ    =HEHwHHEHHHUH5L HEIHǸ    裶    HUdH+%(   t/H]UHHPH}HuHUȉMLEdH%(   HE1HEH4EHEH HUȋMĉHHtOHMHUHuHEIA        HE} tE  HEHHEH       HEЋ@t&   t0   tstC   HEHHEH       } t
HEȋ HHEȋ HUH    } tHE H
HE HUH    T} tHE H
HE HUH    )HEЋ@UH5 щ¿        HUdH+%(   t-UHATSHPH}HuUHMdH%(   HE1H}ЋMHUHuHEIHẼ} tE#  HEHVEHEH   E    HEHگHEzHE؋@HcHEH9u]HEHIHEHHHE؋HEHγHH5& HEMHHǸ    ֳ    w  EHEHEH菭9EnHEHAHHEHoHHUЀ} t	Hy He H}IHƸ    ^   E    HEHHEyHEHHUH9uZHEHIHEHHHEHEHвHH5( HEMHHǸ    ز    |EHEHEH蔬9EoHEHFHHEHtHHEHƀ} t	H~ H| H}IHHHƸ    Z    HUdH+%(   t9+HP[A\]UHATSH@H}HuUHMHEHIHEHHHEHEȉH迱HH5 HEMHHǸ    ǱE    HEH蘮HE   HEHEH H<VHEHE@HEH4HEHUHEHj A    I    H  HE܃} yEAH HEHHǸ    (EHEHEH9E\    He[A\]UHH@H}HuUHMDDʈE؉ЈÈ} tIUEЃPHEUHEHHEH@xH H9r	E    HEH U܉HQHEH} x
H}~,HEUH5r H¿        @   HEH Mܺ    HHEH} u%EHV Hο        jHEH虩tIt?4u/EHEHHEHHEH@xH H9s
HEUHHĀH}HuUHMDDʈEЈEdH%(   HE1HEH@x@
u2HEH@x@0t#HEH@x@4tHEH@x@6t
      HEH M    HHEHEH茨         m      }  tz  t
tKx  } t$}MHUHuHEAHZS  HMUHuHEH7  HMUHuHEHz  HEHzHEHE EHEH UȉHKOEHEH MȺ    HHEHEH訧t}u       EeE    g} u} tHE u
{  }EẺHEHUHuHEA    AHE}tE9  EHE@U9r  HEHHEHEH迦fEE       HE؋PHEH HfQHEUHEH諨EċUHEHE}EAEHEHHE؋PHuHEAHE}=tEeEHEE9E^HH}ЋMHUHuHEIHE} tEHEHu        HUdH+%(   t$UHHPH}HuHUȉMLEDʋEUEdH%(   HE1E    DE}HMUHuHEEAHoE} yE  DE}HMUHuHEEAHE} t}uEG  E?  HEHHEH@x@	tGH} t*HE tHUHk HEHHǸ    ªMHEغ   HHEH Mĺ    HHEHEHE  [     I    7    %      
  }dt_  :                   t
t#  UHMHEHH+E  } t'}MHUHuHEAH!E  }HMUHuHEAHEb  HMUHuHEHEC  HMUHuHEH.E$  HMUHuHEHE  HMUHuHEHCE   } tZ}MLEHUHuHEMAHpE}    HEHEHMUHuHEHE   HMUHuHEH|EjHMUHuHEHENHMUHuHEHE2HEȋ@EH5         } yEEHUdH+%(   t UHHĀH}uHUHMLEdH%(   HE1f)E)E)EfEH} t5HEHH/ HE   H軥tJ  HEH UHKHEH} u  HEHUHPxHEH@xHMHUHHH} tHEH HvHE@    HEH@xPH} tHEH HvHEH@HuHEH@x@	$HEH@HUHRxHJ    HH&H} tHEH Hv
HE@    HUHRxBH} tHEH Hv
HE@    HUHRxB	H} tHEH Hv
HE@    HUHRxB
H} tHEH Hv
HE@    HUHRxBHuMHUHEHj A    I    HHEHEH@x    EsHUdH+%(   tPUHH0H}HuHUdH%(   HE1    HEHeq   HEHȃHt    HUHEHHHUdH+%(   tUHH}HuHE t    HEHmH} ݸ   ]UHH H}HuHUHMH}w+HUHEH5_ HH¿        l    THEH+EHHUHEHHH]t'HEH8 HHο               UHH}} yUډEUHHH}HuHEH@Ht'HEHPHEH@HHoHEH@    HEH@ Ht9HEHPHEH@(HHHHEH@ HH)HEH@     HEHqUHH   HXTHHH@dH%(   HE1ǅhh   HEh       HHhHMTHΉjll tRֵ ؉ll4HTH5 Hщ¿        荽lq  Et0TH Hο        R9  HX@HcHXH@   HHHpHp u  HXHpHPHX@HcHXH    HH\HpHp u$  HXHpH8      ZHxHx uR  HXHPHX@HHHHxHHxTP0HxHHHHxH@HPEHxHP(HXH@TA    Aй      Hƿ    UHpHpuE赳 ؉ll1HTH5 Hщ¿        l  HxHpHPHXH@UHHHEHXH@HTHEIAй      Hƿ    THpHpuE ؉ll.1HTH5 Hщ¿        赺  HxHpHP HXHPHpHHxHPHXHHX@HcHHHHHHEHE       HHE    HXPHEPHX@HMT   gyB ؉ll70HTH5 Hщ¿        边HX@PHXP    &HxHXHHliHUdH+%(   tRUHH H}H}    E    +HEH@UHcHHHHEHH*EHE@9E|HE@xHE@lAHEH HHEH@HHEHUHH0}HuHUHMH} t;HEHH HEо   Ht                  VHEH} uP           k_HcHEHP   6HUBHE@y4 ؉EEE.HHT Hƿ        Է'HMHUuHEHE} uHEHEH訯Uډ    UH}emEE]UHH   H8H0dH%(   HE1Hǅh    HE    H8H@HEHEHEǅT   Tt\TcTt<TQTtTt=HEHELHEHEf<HEHE.HEHHEHTHHMHUHHHyHEHxHxHpƅG HE    H8H@ HEHEHEǅX   Xt\XcXt<XQXtXt=HEHELHEHEf<HEHE.HEHHEHXHHMHUHHH蜋HEHEHEHE  H8HPH8H@(H#pHHEE    HEHEHEHEǅ\   \t\\c\t<\Q\t\t=HEHEȈLHEHEf<HEHEȉ.HEHHEH\HHMHUHHH變EHHLL A  ƅGLHHpL%   @  HEHHEH8L LHcH8H@HMHHAЉPP    HpHEH8H@HEHEHEǅ`   `t\`c`t<`Q`t`t=HEHEЈLHEHEf<HE؋HEЉ.HEHHEH`HHMHUHHHRPH  HhHpHEH8H@HEHEHEǅd   dt\dcdt<dQdtdt=HEHENHEHEf>HEHE0HEHHEH dHHMHUHHH} HhH;0s#HpH;EG HhHUdH+%(   tUHH0H}HuHE    E    bHEH@UHcHHH HEHUHEHHiHEH} yHE:HEHEHEH)EH} tEHE؋@9E|HEH9HOUHH0H}HE    E    eHEH@UHcHHH HEHEHHEH} yHE0HEHEH}~
HEEHE؋@9E|HEUHH@H}ȉuHE    HEȋPHEH0HEȋ@MĉonE} y豨 ؉   E    qHEHEHcHHHHHȋ@EHEH@UHHH HEHEHHEH} yHE*HEHEEE;E|H}~HEHEUHH}HE@]UHHH}uHE@9ErΧ "       HEH@UHHH UHH@H}dH%(   HE1HE    HEH@HEHEHEE   }tM}W}t3}K}t}t=HEHEIHEHEf9HEHE+HEHHEHEHHMHUHHHڄHEHEHEHUdH+%(   tUHH@H}dH%(   HE1HE    HEH@ HEHEHEE   }tM}W}t3}K}t}t=HEHEIHEHEf9HEHE+HEHHEHEHHMHUHHHHEHEHEHUdH+%(   tUHH H}HEHJHEHEH!HEHEH+EUHH}HEH@(H]UHH}HE@0]UHH H}HuHUHEHHHEH} yHE!HEH9HOUHHH}HEHyUHHH}HEH@Ht'HEHP0HEH@HHHEH@    HEH@Ht9HEHP0HEH@(HHHHEH@HH9HEH@    UHHH}H} t3HEHPHE@<xHE@<4HEHBUHH   HhddH%(   HE1ǅph   HEh       H
HpHMdHΉGtt tK賣 ؉tt!HdH5$ Hщ¿        jtX  Et+dH0 Hο        6%  HhdP8EHhHP(HhH@0dA    Aй      Hƿ    DHxHxuKТ ؉tt !HdH5 Hщ¿        自tu  HhHxHPHhH@0UHHHEHhH@0HdHEIAй      Hƿ    CHxHxuK ؉ttC HdH5T Hщ¿        ʩt   HhHxHPHhHP0HxHHhHP HhHEHE    Hh@<HMd   VyH] ؉ttHdH5 Hщ¿        t    HUdH+%(   tUHH }HuH} t;HEHH HE   H	t躠           @      FHEH} u苠           OHcHEHP0   qHUB<HE@<y4J ؉EEHH/ Hƿ        !UHEHE} uHEHEHtUډ    UHH}HuЉЈEHEHP(HEH@ HMH)HHHHEHEHP HEH@(H#EHHEHE %E} tM   @HEU]UHHH}HuHMHE   HHXUHHH}HuHMHE    HH)UHH   HxtdH%(   HE1t?vŞ          HE    HxH@HEHEHEE   }tM}W}t3}K}t}t=HEHE؈IHEHEf9HEЋHE؉+HEHHEHEHHMHUHHH|HEHEHEHEHE    HxH@HEHEHEE   }tM}W}t3}K}t}t=HEHEȈIHEHEf9HEHEȉ+HEHHEHEHHMHUHHHL{HEHEHEHEHxH@(EHEHE)EЉEtEE9Es
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       HuHE@<UѺ   6`E} y    m}tKHEHƿ   E} t    FHUHEHH    HuEE+EE} 5UHEH)HUdH+%(   tUHH}HE]UHH}HEH= H]UHH}H} HuHEH= Ht       ]UHH}HE    (HUHHH)HHE HHHEHEHE uHE]UHH H}HuHEHEHEHHEHHEHEH{UHH@H}HuHUHEHEHEHHEHHEHEHHEHHEHUHEHHɒUHH@H}HuHUȾ(      >HEEH} uHjM  HEH5MH
HHvHEHEHF   HEHUHPHEHUHP H}    HEH?HHEHHEH H   HEH HUHMHHuHEHUHPHEHUHPHE    \HUHuHEA    A        HyE}t} uEHEHHEHHaWHUHHHEHEH@HUH9rHE HEH   EHHUHHH}HEH(u-HEH@ HGvHEH HxHEHxUHH}HEH@]UHH}HEH ]UHHH}HuHEHHHEHPHEHpHEH}IIHѺ   HZNUHH@H}HudH%(   HE1HEH#VHHEHUHEHHjHEH} uMHEH@HEHUHMHEHHsHEH@ HUHMHHztHEHUdH+%(   teUHH@H}HudH%(   HE1HEHdUHHEHUHEHHHEH} u
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  H@HH@PHH(H(HHH@P    H蘕H(HHpPH`H0H(HIIȹ   H$$ t*HH֍ HHο        CR    DH L@(HHpPLMH`H0HHH}WHHHUdH+%(   tүUHH@H}HuHUHMLELMHE؋@t} u*HEHX HHο        Q    ,  UHEH@(HHEHEHõtIHEH菵t6HEHSHHEH5 H        Q       HE؋@tdHEHH(HE؋@HcHHHHHH H HHBu(DEH}HMHUHuHEEIHHuHEHH(HE؋@HEHPPHEAIȉ   H`t       UHHH}HEH螴tHEH u HEH[tHEH聵t       UHH`H}HuHUHMLEE    HEH@(Hu-HEH H HHο        OE  HEH@(H?EE     UHEH@(HHEHEHtBHEHEH@(HHEHUHEHHHAm  EԉEf  HEH聳N  HEHӳHEE    HEH膲E  HEHEH@(HHHEHEHEH@(H\HEHUHEHH@   HEHȲtHEH0    HEH聲tHEH觳tl} tBHEE9t5HEUHEH5 AȉH¿        M   HEUԉHE HE    wEHEE;EEE;E} tHE     HEU܉    %HEH4 HHο        QMUHH H}HuE   =HEH@8UHcHHHEHEH HUHH,?uHEEHE@@9E|    UHH`H}uHUMUHEH7HEUHEH"HEHEHtHEHZ                     HUBHEPHEHHEHEPHEHHEHEH߰HEHEHϰHEE    HEH覯E]HE؋ tDHE؋HEH蕬HEHUHEHHN Eԃ} yE'UHEEHEHEE;E|    UHH}uEHE@HEP]UHH}uHE@EHEP]UHH}uHE@HEPHE@E	ЉHEP]UHH   H}HuHUHMD|dH%(   HE1HE    HE    HE    E    E    HE@EHE@EHE@EHE@fE} t4HEH@(H   H- Hƿ        J  HE@f=   HEHP8HE@HHHEHE@t
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       HEH@HEH} tEUHEH@HMHH9E+ẺHEHPEHHEHHHUHEH@    HrHEHPEHHEHPHEH@HUH)HUdH+%(   tqUHHH}HE@<@u0HU @   Hƿ        HE@D    HE@<HHUJ<UHH H}HE苀   =   u1HE       HdEHE苀   U)HcHHE苀   HHU艊   @UH}}t }w6}t}w*}t}t             ]UHAUATSHH}؉uԉUб HHрHHH  H!HыUH H	HѰ`H  H!ЉH}HHA LILIH  L!IŋEH DH	IALIL`IH  L!IDIHELLHa{H؀HH؀HH  H!HÉHHEHHH[A\A]]UHAVAUATSH H}؉uԉUЉMA LILIH  L!IЋUH DH	Iа`H  H!ЉHMLHHEЉaALIL IH  L!IDIHELHA LILIH  L!IŋEH DH	IALIL`IH  L!IDIHELLHEЉ#cH؀HH؀HH  H!HÉHHEHH5H [A\A]A^]UHATSH H}uUMA LILIH  L!IЋUH DH	Iа`H  H!ЉHMLHHEJaALILIH  L!IDIHELHZEcH؀HH؀HËEHH  H!H	HÉHHEHHH [A\]UHAWAVAUATSH(H}ȉuĉUMDEEsaALIL`IǋEHH  L!H	IDIHELHv} t@ALILIH  L!H   IDIHELH0A LILIH  L!IŋEH DH	IALIL`IH  L!IDIHELLH	E[cH؀HH؀HH  H!HÉHHEHHmH([A\A]A^A_]UHAVAUATSH H}؉uԉUЉM̋EЉaALIL̠IƋEHH  L!H	IDIHELHA LILIH  L!IŋEH DH	IALIL`IH  L!IDIHELLHEЉcH؀HH؀HH  H!HÉHHEHH H [A\A]A^]UHATSH H}uUM܋EaALIL̠IċEHH  L!H	IDIHELHE?cH؀HH؀HËEHH  H!H	HÉHHEHHDH [A\]UHAWAVAUATSH(H}ȉuĉUMH  H!ЋUH H	HUHHA LILIH  L!IǋEH DH	IALIL`IH  L!IDIHELLHALILIH  L!IŋEH DH	IHELH&ALILIH  L!IDH       H	IHELHH؀HH؀HH  H!HÉHHEHHH([A\A]A^A_]UHH}HEHH9E]UHATSH H}HEHH0HEHP HEH@H)HH)HPHHHHHHEHEHtMALILIHEHH  L!H	IDIHELH>HE@DH؀HH؀Hø  H	HÉHHEHHH [A\]UHAWAVAUATSHX  HHLdH%(   HE1H@@  HHH   HT  : x1 y(HH葿HHH  r=%f@d HHiHHHHbH HH  H!HH H	HAILIIL`IH  L!IDIHLHTALILIH  L!IƋH DH	IHLH xVALIŋHLH	IH  L!IDIHLHW xVALIċHLH	IH  L!IDIHLHH؀HH؀HH  H!HÉH       H	HHHHHEdH+%(   t"cHX  [A\A]A^A_]UHH   H($ HLpLxt )E)M)U)])e)m)u)}dH%(   HH1ǅ0    ǅ40   HEH8HPH@H0H $H(IH:HHdH+%(   t2bUHH   H(H H`HhLpLxt )E)M)U)])e)m)u)}dH%(   HH1ǅ0   ǅ40   HEH8HPH@H0H H(IHѺ   HWHHdH+%(   tOaUHATSHH}ՀHUR@t      HH  H!H	ЉHUHHgAL	ILIH  L!IDIHELH'H؀HH؀HH  H!HÉH       H	HHEHHHD HEHѺ    	   HǸ    6H[A\]UHHH}ua̠UHH  H!H	ЉHUHHgHEHUHSHH}u H  H!ʋMH H	ʰ`H  H!ȉHMHHKaH؀HH؀HH  H!HÉHHEHHHEHH]UHATSH0H}ȉuĉUHEȋ@8U9rHEȋP<E9tKHEȋx<HEȋP8MEH5uC AAȉщ¿         HE@DHEȋ@DU  HEȾxHhE    KEHH"HEȋ@<H    EHHHHEȉѺ   HEHEȋ@8U9rE    5UHEȉHEHEȉѺ   HXEHEȋ@<U9rALILIH  L!IDIHELH3H؀HH؀HH  H!HÉHHEHHHEH Ht+HEH H H vHEH @ tHEH>  HEȋ@DuHHA Hƿ       5HEȋ@D   HEH HEHEHPHEHPHEHP HEH@H)HEPHEHPHEHPHEHPHEH@H)HEPHE@(tBHEH@HEHE@EE    HEHPHUHeEE;E|HEȋ@DH0[A\]UHHH}H} t.HEH@H`HEH@HPHEHDUHH`H}dH%(   HE1HEHPHEH@H)HHEH@HUHHE    |HEHPHEMHcH<DHHHEEHHDHEHE@(tHEHkHEHEHEHEȉHEPHEH HHEHPEExHEdH+%(   t[UHSH   H(H dH%(   HE1ǅ0   0HcH@    H[H H(HH84H(@(t4`44P0H@H(HH<0<8H5> AAȉщ¿       <H(A          HZ<H(A          H0<H(A          H8<H(H0<H(   HHR> H(HHǸ    H(HcH؀
HH؀pHH  H!Hڸ  xH	HÉHH(HHBHEdH+%(   tXH]UHAVAUATSH   HHDDHEHdH%(   HE1ǅH   ƅ HcH0    HY H@(t   0H@(t4H@(tz8H@H@(t<@HH@ H(H@(tH(HH(H(HpH t"HH0HJ   HHQH@(H@(tHH@,H@(tO\H@(t<H@H@(tdH@H@(thH0HHH HD@UHH5|: Q QEAH¿       >HH@t$ 0Hx   Hw- H|   Hƅ} x2E HA   Ѻ   H H    HHxDDMHH59 HHWHǸ    HHH} ySAcL
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}܋uHE@E    [}ܡuUHE HED`HE@HUHEH5 HSEIȉH¿         HEHe[A\]UHH H}uUHMMUHEH5 AȉH¿       讜HE HEPPHEPPHEf@  HE@#UHH}HE t1t%'tt            ]UH}}t }w6}t}w*}t}t             ]UHH`H}HuUHMDELMHE EHE@tNHEHtHEHHEPuHEHjHMUuHEHT      HEH HEHEH@HEE߃t8  t*  f         HE t
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   HEHUHEHH9EsHE u
   HUHEHH+EHHEо    H9HEH} u
   HEHUHEHH9ErsHEHUHHEHUHPHE tHE <:uHEH HPHEHUHPHUHEHPHUHEHP HUHEHP(    HUdH+%(   tWUHH@H}HuHUdH%(   HE1HEHUH   HEfǀ(    HEH@HEa  HE(  f~EHEHHHEHPHEH H5J IIH           U  HE(  HcHHHHHUHHEHE(  HMHUHEH  E} yE   EHEPEyE؉EEt*uE   )HEP8MHE(  HUH5 AHщ¿        T8EHHEHE(  HEf(  HE     HUdH+%(   txUHH H}E    |E    gEHcȋEHcHHHHH    Hȋ HHEHHYFu$EHcHHHHHHǋ HAEEvEExHEHʰ HHο        SUHHpH}uHUHMdH%(   HE1HE    HE    HE    HE    E   HE    LMLEHMHUH5n HEH}WH}WHǸ    SH   LMLEHMHUH5_ HEHH}WHǸ    HtqLMLEHMHUH5M HEHH}WHǸ    Ht7LEH}HMHUH5; HEMIHǸ      HE@HEHHEHHEHE} yE  EHEfPHEHEă} yE  Ef%HUf%B
f% 	fB
EtQ_t4UttIHEPPaHEPPNHEP P;HEP0P(EHQ Hο        wQ    LEH}HMHUH5P HEMIHǸ    X uEHE@HEHHEHHEHE} yEe  EHEfPP  H}HMHUH5 HEIHǸ    uBHE@HEH     HEHE} yE   EHEfP   H}HMHUH5 HEIHǸ    yu?HE@HEH     HEHE} yE   EHEfPwH}HMHUH5E HEIHǸ    u"HE@ HEHHEHHEf@  )HUEH5 Hщ¿        OEHUdH+%(   twUHH}HE]UHH}uUUEHE@9rUE;Es    HEHEH]UHH0H}؉uԋMHEغ   HHEH} tHE =PKt
   HE@fEUEHHPHE؋@H9t
   HE@fEHE@fuHE@fuHE@
f9EtNHE@EHE@EUMHE؉HHuHE؋UPUHE؉P    UHH(H}EHE؋@w`HE؋@HHEHEH-   HE"HEHE؉HE}tHmH} xHEH;E~	} uEUHH0H}HEؾ   HǸ    NE} ywE HH4  E       HEH}tH9E~EH   HEUA    Aй      Hƿ    HED ؉EENH}uEHH5      [HEH} u!HUHEHHM5H_HEHUHHEHEPHEH4E} t.HUHEHH4HEHS&EHHHEUHHH}HE@HEH HH4HEH&UHH H}uMHE   HDHEH} tHE =PKt    HEUHH8H}؉uHUȋUHE؉HHEH} u
*  EHE@uHE@t
   HE@ЋMHE؉HHEH} u
   HE@EHE@ЋMHE؉HUHu
   HE@EHE@EUMHE؉HHEH} uPHEPHEfHEPHEfPHEHUHPHEHUHPHEȋUP HEȋUԉP$    UHHPH}HuHUHEH)HEHEȋ@EE      MHEȺ.   HbHEH} tHE =PKt
   E.HE@fEU܋MHEȉHHEH} u
   HE@fEEރuUEރuJEH9Eu@HEHEHHUHEHHuHEH*HUHEȉH}<EEHE@EHE@ EEHEȋ@9EUHH H}HuHEH     HE@   _Gu*HEH` HHο        }H`   HE   HǸ    HE} y>]@ ؉EE蓾HHEH5. HH¿        HEwE       `HEH} u>HHEH5 HH¿        GE>_HEUPHEHUH    UHHH}H} tHEH HHE@UHHpH}uHUdH%(   HE1)HUHEHHHtUE9uHE$HUHEHH'HEH} u    HUdH+%(   tʤUHH   HXHPHHDD@dH%(   HE1Hǅh    HX       HTHUHPHHHu:_HHHH5 HH¿        +Fn  DHP    HHhHh u-HHHl HHο       E  HpHhHHLHu
  EHXHP(Hh    H	HXHBHXH@Hu:dHHHH5 HH¿        0Es  HXH@H@HM    HHHXHP HXHPHHX@   Dt
      HP    oHIHhHh u
       Hh    HHXHBHP    oHHhHh u
       Hh    HHXHBHXH@HtHpHhHHHu*HHH HHο        CEHXHP0    HUdH+%(   t荡UHHPH}dH%(   HE1HEH@HEHEHHEHE    HEH@8HEk  HEЉHEH@HUHH1  HE@HE   9  HE HEHH(HEH HHR4HEH}    HE@HEH HHHEH}    HEHP HEHH0H   HEHPHEHP8HEHUHHE@`    HE@d HEH@HtQHEЉHEH@HUΉHHtEE%  HE؉P`E%   HE؈PdHE,
HEHEH@ H9E    HUdH+%(   t襟UHH@H}ȉudH%(   HE1HEH@Hu
       E    fE9EtEtwUEЉEFUEЉHEH@HU؉HHtHE؉HEHH0HEH HH}2-HEH@HUMԉHHx    HUdH+%(   t躞UHH@H}uHUHMLELMHEH HUHMHH+t
       HEHHEH tHEHHEH <@t    pH} u   b}uAHE؋P`HEHpHEH} u    5HUHEHH.2HEH HUHH2UHH}HEHPHEH@0H)HEH@8H]UHHp  HHHdH%(   HE1E   E   HǅHUHHHHu@MHHH5 HH¿        ?Hǅ_9  EfH@   H%HH tCHH+HHH <@uHHHH!HHHHǅ    ǅ      ǅHLHHHA   HMHHH_  H 1    HtLHHHHMIH   H@H    HHHHH9   tPtGHH HHH5 IHH¿        %=Hǅ_E  t*HH!HHH5HH H :H ~9HHHH5 IHH¿       Y<   H uM t	H H HHH5* I        
<Hǅ-HHH5& HH¿        ;HHUdH+%(   t裙UHH@H}HudH%(   HE1HEHUHEHHHHEH} tHE+HEHUHMHHHEHEHHEHUdH+%(   tUHH H}HuHEHEHEHEHEHHEH HH-UHH@  HHHDdH%(   HE1E   E   ǅ    ǅ    H HHH t  H   HvHH   HZHH t
H uǅ  ǅ    cHH    HHЋHcHHHHH HHHHHHB;|HcHDHHѺ   H'ǅ      HLH HH@AH3       H HHH @Hǅ0    Hǅ8    H H H0HcHcHH0Iȹ   HHH    H@HH    HHHHH H   HH H9   H@t\tSHH8H H HHH57 IIHH¿        7ǅ   u	.HHHHPH@HH H  R;tǅHHHHH tHHH H HUdH+%(   t葔UHSH(  HHHHdH%(   HE1E   E   Hǅ     Hǅ    Hǅ    ǅ    H HHH? t  ǅ    !  HLH HH0A   H         HH HHHuqHHPHH HѺ   H    H HHPHHHHH,HH0HVHH GH uH t$H HHHHHǅ tH HH HHUdH+%(   t'H]UHH}HuHUH} t[HmHE     HUHEHHMHUH HEHEH;EsHUHEH uHUHEH  ]UHH}HE]UHH}} x
EEUHH   ,dH%(   HE1Hǅ8   ƅ@AAAAfǅB  ǅD    ƅHIIIIfǅJ  ǅL    H8HP    H褑ǅP   H HH`H@HHXǅT   ,E, t|   |H. HPH0   HHH8HP   H胂44_HUdH+%(   tUHH  dH%(   HE1EEуEEу EfE  E    E EكEEكEfE  E   EzEEEEfE  E*   EEEEEfE  E    EEEEEfE  E    H0H       H؏ t       f))))fօHǅH   HHH0H8HHH@HHHHHPHXHHH`HhHHpHx       H tA   A    HP       HHHǅPx   DduHPHXHHH`HhHHHpHxHHHEHUH HHEHUHHHEHUH H(HEHUH0H8HEH@ǅ$   H0Hӑ IA          Hƿ   (( yG& ؉,,HHZ H Hƿ        .,\(Eԋ$HcHHEH% IIH       ,(誶,oHUdH+%(   tUHH0}dH%(   HE1E   E   E   E   MH HEAȹ      HHUdH+%(   tUHHP}dH%(   HE1E   E   E   E   E    E  E    E   E   E   E   E   MH HEAȹ	   0   HGCHUdH+%(   t͊UHHP}dH%(   HE1E   E   E   E   E    E  E    E   E   E   E  E   MHO HEAȹ	   0   HHUdH+%(   tUHHP}dH%(   HE1E    E   E   E   E   E   E   E    E   E  E   E   E    E   MH HEAȹ	   8   HHUdH+%(   t[UHHP}dH%(   HE1E    E   E   E   E   E   E   E    E   E  E   E   E    E   MH HEAȹ
   8   HHUdH+%(   t蛈UHH0}dH%(   HE1E   E   E   MH HEAȹ      HHUdH+%(   t(UHHP}dH%(   HE1E    E   E   E   E   E   E   E    E   E   E   EMHې HEAȹ   0   HHUdH+%(   tvUHH@}dH%(   HE1E    E   E   E   E   E   E   E    E   E   MH< HEAȹ   (   HLHHUdH+%(   t҆UHH   LdH%(   HE1H`H       H胇L t     Lf)E)E)E)EfEHEH   ỦEHEHUH`HhHEHUHpHxHEHUHEHUHEHUHEHUHEHEH`H5 IA         Hƿ   \\HUdH+%(   t訅UHH@  dH%(   HE1Hx       HY tA   A    H`       HHHǅ`x   ǅl   DtuH`HhHHHpHxHHHEHUH HHEHUHHHEHUH H(HEHUH0H8HEHUH@HHHEHPEEEEEfE  E    EEEEEfE  E    ǅ   HcHHEHֈ IIH    	   ~-HUdH+%(   t跃UHH`  dH%(   HE1Hx       Hh tA   A    H@       HHHǅ@x   DTuH@HHHHHPHXHHH`HhHHHpHxHHHEHUH HHEHUHHHEHUH H(HEH0EEEEȠEfE  E    EEɃEEɃEfE  EEзEуEEуEfE  E   EطEكEEكEfE  E    EEEEEfE  Eq   EEEEEfE  E    ǅ   HcHHEH@ IIH       HUdH+%(   t!UHH  ,dH%(   HE1EEEEEfE  E    EEEEEfE  E    H@H       H舁, t       ,f))))fօHǅH   HHH@HHHHHPHXHHH`HhHHHpHxHHHx       H藀, tA   A    ,H`       HHHǅ`x   DtuH`HhHHHpHxHHHEHUH HHEHUHHHEHUH H(HEHUH0H8HEHUH@HHHEHPǅ0   H@H IA          Hƿ   44 yJ ؉<<豖HH HA Hƿ        9 <   0HcHHEH IIH       88 y4]    H48    Ή輵<4)8<HUdH+%(   tj}UHHp}dH%(   HE1E   E   E   E   E    MHq HEAȹ      HcE} y    YHE        H}HEH&HEE   HUHMEHΉBEE5} HUdH+%(   t|UHH@  dH%(   HE1EEEEEfE  E    EEEEEfE  E    Hx       H| tA   A    H`       HHHǅ`x   DtuH`HhHHHpHxHHHEHUH HHEHUHHHEHUH H(HEHUH0H8HEHUH@HHHEHPHHEH IA   H       w y r    )   s ؉ x yu       HUdH+%(   t7zUHH  dH%(   HE1Hx       Hz tA   A    H`       HHHǅ`x   ǅl0   DtuH`HhHHHpHxHHHEHUH HHEHUHHHEHUH H(HEHUH0H8HEHUH@HHHEHPH@P       Hyf)))))HǅP   HHH@HHHHHPHXHHH`HhHHHpHxHHHHEEEEEfE  E    EEEEEfE  E    Hǅ8    HHEH| IA   H       ;,, y B  H| HhH8Hpǅd   H@,HѺ0   o0L ؉40 y	4t-0 x0芡,}       ǅH4| HhH8Hpǅd   H@,HѺ0   n0 ؉40 x0,0 y4u       HUdH+%(   t(vUHH@  dH%(   HE1EEEEEfE  E   EEEEEfE  E    Hx       Hv tA   A    H`       HHHǅ`x   DtuH`HhHHHpHxHHHEHUH HHEHUHHHEHUH H(HEHUH0H8HEHUH@HHHEHPǅ   HcHHEH`y IIH       HUdH+%(   tAtUHH0}dH%(   HE1E   E   E   MHb} HEAȹ      HHDHUdH+%(   tsUHH  <dH%(   HE1E   E   E   E   E    E   E    E    E  E   E   E   E   E  E   E    E  E   E   E   E   E  E   E   E   E   E    ƅ`aaaafǅb  ǅd   ƅhiiiifǅj  ǅl    ƅpqqqqfǅr  ǅt   ƅxyyyyfǅz  ǅ|    ǅP    ǅT   ǅX   ǅ\   HPx       Hr< tA   A    <H       HHHǅx   D<HHHPHXHHH`HhHHHpHxH HHHHHHHH H(HHH0H8HHH@HǅD   <Hy HEAȹ   l   HHH y
       H`HPHǅ   ǅ   DHcHPH`Ht H5iu IIH   蒲LHoL4HUdH+%(   toUHH  dH%(   HE1H0H       Hop t       f))))fօHǅH   HHH0H8HHH@HHHHHPHXHHH`HhHHpHx       H~o tA   A    HP       HHHǅPx   Ddǅ   HHHPHXHHH`HhHHHpHxHHHHH HHHHHHHH H(HHH0H8HH@ƅ fǅ  ǅ    ƅ fǅ  ǅ   @ƅfǅ  ǅ    ǅ    H0Hq IA         Hƿ   $$ yJx ؉,,訄HHu H8q Hƿ        0,!  $ƅ  HcHHHp H5Oq IIH   h( ؉,$6( x4Hu Hq Hƿ        ( wH*q HHHHt    RHq HHHHu/HHt H5q H        ,   HUdH+%(   tjUHH   HxtdH%(   HE1tHHH= HHEHx uH HxE    tH    HxHHEHEHEE   }tM}W}t3}K}t}t=HEHEIHEHEf9HEHE+HEHHEHEHHMHUHHHEz  HEHPHx@\҉E}    E   tH    HxHHEHEHEE   }tM}W}t3}K}t}t=HEHEIHEHEf9HEHE+HEHHEHEHHMHUHHH  }    E   tH    HxHHEHEHEE   }tM}W}t3}K}t}t=HEHEIHEHEf9HEȋHE+HEHHEHEHHMHUHHH?   E膀HHEH H5p HH¿        
E   tH    HxHHEHEHEE   }tM}W}t3}K}t}t=HEHEЈIHEHEf9HE؋HEЉ+HEHHEHEHHMHUHHHYE    tH    HxHHEHEHEE   }tM}W}t3}K}t}t=HEHEIHEHEf9HEHE+HEHHEHEHHMHUHHHEHUdH+%(   tzfUHH}HE@]UHH}HE@]UHH@H}HuЉUdH%(   HE1HEH@    HE@ HE@$    HE@(    } t}    HEHd               p       }    k  b  }[tAO  F     t`/  	y!  t  HEf f@  HEf f@HE    HE@      HEf f@HE    HE@   HE@      HEf f@HE@   HE@   HE@   zHEf f@HE    HE@   HE@   HE@   HE@   2HEf f@HE@   HE@   
    HEHo   g  ^  }o  G  >  }Oti+  "     t    HEf f@   HEf f@HE       HEf f@HE    HE@   HE@      HEf f@HE    HE@   HE@   kHEf f@HE    HE@   HE@   9HEf f@HE    HE@   HE@   ;2HE؋@tHEHHE؉P(HEHUHP    HUdH+%(   tbUHH}HEH@Hu
    /  HE@ yhHEP$HE 9}-HEHpHE@$HHUJ$HUHDHH   HE@     HEH@HPHEHPHE@$    HE@uHEH@           HEP$HE@9|8HE@ PHEP HEHPHE@HHHEHPHE@$    HEP HE@(9}.HEHpHE@$HHUJ$HUHHDHHHEH@        ]UHH}HE@]UHH}HE@]UHHH}HEHfEf}tf}u       UHH}HEH ]UHH}HEH]UHHpH}udH%(   HE1HEH UHHEHMHE    HHE} t$E;HEHP0HE HHЋHEHEHHEH} uʸ    HUdH+%(   t{_UHH0H}HuHEHEHEHEHEHHEH HH|E} u:HE@t+HE@tHE@HE@)EUHH@H}HuЉUHE    ẼEE    iUEЉEEHHHHEHHEHUHEHHE} uHEHE} EE	EEE;E~HEUHHpH}udH%(   HE1HEH UHHEHEHut
      HMHE    HHE}    E   HE E   HEH UH=HEHEHt#rm}t|^wV'HE@EPHEHHEHE E5HE@ 9EsHEH@0UHH E    E    } KHEHHEH} "    HUdH+%(   t\UHSH   HxdH%(   HE1HE    E    Hx@    HќHEH} uE  Hx@ HHHEHHEE       HxH@UHHEHEHxH@MHHHMHHHEHHHEHEBHEPEHHHEHȁP	ʉPEHHHEHPPEHx@ 9E?Hx@ HHEHѺ   HHx@ E%UHxHE} N  EHxP Hx@9ErHx@(H   H@HEH} uE   E   mHxH@UHOHEHEHu9HEȋ t/HEȋ HEH <tHEȋ HEHEHx@9ErE     HE    HE    HxH@UHHEHEȋ V  HEHCEEEHEȋHxH@H˩HEЃ}t_}  }tO}  }   }  }t+}  }t}   E  &E؃EHEȋ@% E؃	ЉEEHEȋ HEH <E؃	ЈEHEȋ@% E؃	ЉEHx@ HMHEHHHE  HE@tHEPHx@ 9r0HEPEH5Nb щ¿        E  HEPHxH@H
HEHEHE}  }Q  }tF}A  }   }-  }   }   E
     }t}  }t.}t=  HEH(HEH8t3  HEHt$  HEH        E;E  HEHHEH8t_a  E;EtUX  E;EtK}tEE  HxHP0HE@HHЋ u!HEȋPHE@9  	HxHP0HE@HHЋ    HxHP0HE@HHЋ tiHxHP0HE@HHЋHEȋxHEPHEDEH5S` HQEAH¿        ^HEc  HxHP0HE@HHEHxHP8HE HHHEȋ 
HEH} t+HEH;Es!HUHEHHIEHx@9EUE      HxH@0UHHЋ tHxH@0UHHЋ ufHxH@UHٻHEHEHxH@HHEUHEH5q_ H¿        EEHx@ 9EKHEHHEHEHUdH+%(   tTH]UHH H}E      HEH@UH
HEHEHE}t}H}t} ~<Ew1HE uNUEH5^ щ¿        "AUEH5^ щ¿        EHE@ 9EE    UHSHxH}udH%(   HE1HEH UH&HEHMHE   HH#E}    E   HE    HEHE@$9r"HEHEH(HE@$)HEmHEHP8HE HHЋ E} u?HEUHEH HUHH^ Hƿ        ,UHEHEHHEH} 7    HUdH+%(   t|RH]UHH   H}HuHxdH%(   HE1HEHEf)E)E)E)EE    HEH3]HEH} t
HEH9Eu
  HEH踲EHEH該EȋEЋU)UHEHEHEHEE   HHEHEHa@   HّHEHEHaHEHEHoaHEHE@EHE@EHEHt	HEHuE  HEHE}    EЉE$UȋE4EHUMHHʉ)
EE;ErHEHE}    E    EЉE"UHEHE} uEEE9ErE    #UЋEHEHE} uJEE9ErHUHEHHi`Hx t$HUHxHHE    
HEHBHEH6EHUdH+%(   tOf.     f.     f.     f.     D  UH=B HHdH%(   HU֪H HEdH+%(   u1uOD  UHATSHdL$%(   LeAH= Hn ~Wub   HB H5D 1蘾   >   ӥu/HEdH+%(   upH[A\]       fu2f    EtHEdH+%(   u6H[A\]鉿f     Hi 8 uċxNx{Nff.     UHHdH%(   HEH 8t#HEdH+%(   uH= OJ    @߈N     UHSH   dH<%(   H}H`_   H`e11H`FIHEdH+%(   uH]Mff.     UHSH   dH<%(   H}H`G_   H`e1ҿ   H`HHEdH+%(   uH]9Mf     UHHdH%(   HE1HEdH+%(   uL@ ff.     UHHdH%(   HE1HEdH+%(   uL@ ff.     UHHdH%(   HE1HEdH+%(   u1}Lfff.     UHHdH%(   HE1HEdH+%(   uH H H 1LUHHdH%(   HE1HEdH+%(   uH H H@KUHHATSHH}HHdL$%(   LeI   x.H}荣H}HEdH+%(   u)H[A\]@ H LHھ   H8~cgK    UHH   HXH`HhLpLxt )E)M)U)])e)m)u)}dH%(   HH1HEH0ǅ0   H8HPH@ǅ40   HHdH+%(   uJfD  UHH H}dH%(   HE1LH}HEdH+%(   uC^J ff.     UHHdH%(   HE1HEdH+%(   uH H H@JUHH   HXH`HhLpLxt )E)M)U)])e)m)u)}H(dH%(   HH1lHEH(H0H8HPH@ǅ0   ǅ40   |HHdH+%(   uCI UHHdH%(   HE1HEdH+%(   uI@ ff.     UHHHGdH%(   HUHHHwHGH9r@LGIL1HIH)HHOHEdH+%(   u'H? H H@D  HEdH+%(   uzHf.     UA   HHdH%(   HE1HHHHG    IDHw O(HGHGH H H HtHUdH+%(   ufD  HEdH+%(   uGf.     UHHdH%(   HEH` H H@HtHUdH+%(   ufHEdH+%(   uGf.     U   HAUATIH=`: SHH dL,%(   LmI   H,fH;L   L9_HEdH+%(   uH1[A\A]]G     UHH dH%(   HEH 8 uGL, IHu	      H=9 LEI
eL HM   HUI:^HEdH+%(   u1|Fff.     UHH   HXH`HhLpLxt )E)M)U)])e)m)u)}dH%(   HH1HEH0ǅ0   H8HPH@HW` ǅ40   HHdH+%(   uEfUHH   HXH`HhLpLxt )E)M)U)])e)m)u)}dH%(   HH1H! : u>HEH0ǅ0   H8HPH@H_ ǅ40   PHHdH+%(   uDD  UHHdH%(   HEHP_ H99_ uH=0_ 1HUdH+%(   uD  Dff.     UHHdH%(   HE1H9=^ u$H^ H^ 1HUdH+%(   u ,Df.     f.     f.     f.     @ UHHdH%(   HEHF@H+B@HUdH+%(   uCf     UHHdH%(   HEHG@HUdH+%(   uCfff.     UHHdH%(   HEHGHHUdH+%(   uMCfff.     UHHdH%(   HEHGPHUdH+%(   uCfff.     UHHdH%(   HEHGXHUdH+%(   uBfff.     UHHdH%(   HEHG`HUdH+%(   uBfff.     UHHdH%(   HEHGhHUdH+%(   uMBfff.     UHHdH%(   HEH   H HUdH+%(   uB    UHHdH%(   HEH   H@HUdH+%(   uAfD  UHHdH%(   HE   HUdH+%(   uAff.     UHHdH%(   HEHGpHUdH+%(   uMAfff.     UHHdH%(   HEHGxHUdH+%(   uAfff.     UHHdH%(   HEH   HUdH+%(   u@f.     UHHdH%(   HE1HEdH+%(   u1@fff.     U1HHdH%(   HEH  H9GtHEdH+%(   u ɉD  H9Fu⋆   9   $@@ U1HHdH%(   HEHH9G@tHEdH+%(   uɉD  H9F@uHF(H9G(?     UHSHdH%(   H]苟   u_|Hr x tEH@x) HH    HuPH9tH9   uH Hu    W|9LH?o9MHUdH+%(   u-H]D  H9tH9   u  H Hu>f     UHSH   HPt)pdH%(   H8H_HEPH?H(HH@pH0   ǅ    ǅ$0   HLHcȍCH9LH8dH+%(   uH]C> UHSH   HPHXL`Lht#)p)M)U)])e)m)u)}dH%(   H8H_HEH?IH(HH@L    H0ǅ    ǅ$0   HgHcȍCH9LH8dH+%(   uH]b=fUIHQHAWIAVAUATSH(L.dL4%(   LuIH9G@     D`A  Ic     I  1 HH9   D9$uHHÅ   MWI  E1EH<   H| F  H|   H|   H|  *  H|(   H|0   H|8 f   ff.     HEdH+%(   ^  HeD[A\A]A^A_] HKI  fffvfrM0HofvfvfpfoHfvfvfpѱfoP ffvfvfpʱfoP0fvfvfpڱfʈfffofsffofsff~fA~@|MoM'D  L脕    MLHHcHl H)HLI))ø    APH8. LHS8AXZfD     DDM跱Ic   LIHy 1DMAo       DDMwIcL   IHy 1DMHcA)AI  IH|8 k    DDMIcL   IH.y 1cDMHcA)AI  IH| vc   1DLUʰHcuL   IHx 1D}AHII  E)H| VfD     DDMoIcL   IH~x 1DMHcA)AI  IH|0     DDMIcL   IH&x 1[DMHcA)AI  IH|( S    DDM迯IcL   IHw 1DMHcA)AI  IH|  .S    DDMgIcL   IHvw 1DMHcA)AI  IH| S Hۊ H}HK+    M01}MLEA HEdH+%(   u*HeMLL[   A\1A]Hv A^A_]7f.     UHHdH%(   HEHG@HUdH+%(   u7fff.     UHHH]ߊ dH%(   HE1y tHH   HxH   L@   L9r(HI9rH   1H9   t"f.     HUdH+%(   u<    f(   tހy tHP  H"ڊ H+P  R(uHH6UHHHފ dH%(   HE1y tHH   H8H   L    L9r*HI9rH   1H9   t$ff.     HUdH+%(   u<    f(   tހy tHP  Hbي H+P  R(uHH6UHAWIAVIAUEATSHhEHUHML%݊ EHLMdH%(   H]H  HEHGHEA|$   E   H@   H9 f     uH  H@LHHxHEUHuA|$ Hc}HxHFA   FtH9 &  EM    IH(  }HuDmL,   f.     A|$) tI   tUINL1HuUHcII)WIM9uHuMH԰HEIHEIFHEdH+%(     Hh[A\A]A^A_]ÐfUHuL   UHcII)WIM9tA|$) tI   tAFtIVHG  fH*f*^@ E      a    HuDmL,Ɛff.     A|$) tI   tuIV}I>HU  HUfHt0HP  fH*YI H  fH*^UHuL   UHcII)WIM9iHuMD  8   OȉMHcD  8H@Ht4LHHV"fH9   uH  H HHzHtI9uIG0Hc}HPI9xH}HL}HLxIDmID  I  MI9tYIL9u     IV0LrL9uuLH}LxDmHփfHH	H*XD  LUIGA   AG롐HUUHfHH	H*XlHփfHH	H*X11f.     UHAWAVIAUIATSH   dL$%(   LeA̅u_|HAي x tTI@x)     IHH   ff.     H9tH;   uH Hu    W|9LL?L,9MÉI  @ D9H LEHEdH+%(   uPIuI} HM[Ho A\1A]A^A_]Լ@ H9tH;   u  H Hukv0fD  UIHHPH~@dH%(   HMHH&؊ DH  Hq@Etz uX   H9r6HH9r*1z t"I  H@H9 t[ff.     HUdH+%(   O   I     H9rH9H@H9   Hcf     D8A~Ic   DMH}LUHMoH}   HEoLEHM  HDMLUHM  IB0H0I9tdfD  ff.     ff.     ff.     ff.     H  H @+   Hx@H@0HcI<H0I9uHA0H0H9t3H  H @+   Hx@H@0HcH<H0H9uθ   HIH9rDH9rGHL9u1ff.     LHEHu耪H}wHENfD     ѐH    D8AaEXE9OIc   UHMLUDED]H})nH}   HEnLMUHM+  HD]DELUHM  IB0H0I9t@ ff.     H  H @+   Hx@H@0HcI<H0I9uHA0H0H9t3H  H @+   Hx@H@0HcH<H0H9uIcHI   H9r9HH9r-   A9tHIH9r8H9r:HL9u1fD  LHEHuH}רHE   H,LHuU誨H}表HcE1E1LHu芨H}聨11E1D  UIHHPH   dH%(   HMHHӊ DH  H   Etz uR   H9r0HH9r$1z tI  H@H9 tUD  HUdH+%(      I     H9rH9H@H9   Hcf     D8A~Ic   DMH}LUHMkH}   HEkLEHM>  HDMLUHM)  IB0H0I9t7fH  H @+   H   H@0HcI<H0I9uHA0H0H9ts    ff.     ff.     ff.     ff.     ff.     H  H @+   H   H@0HcH<H0H9u˸   HIH9rAH9rDHL9u1f     LHEHu@H}7HE>fD     ѐH    D8AQEHE9?Ic   UHMLUDED]H}iH}   HEiLMUHMk  HD]DELUHMR  IB0H0I9tC ff.     H  H @+   H   H@0HcI<H0I9uHA0H0H9ts    ff.     ff.     ff.     ff.     ff.     H  H @+   H   H@0HcH<H0H9uIcHI   H9r6HH9r*   A9tHIH9r5H9r7HL9u1 LHEHu`H}WHE^   H	(LHuU*H}!HcE1E1LHu
H}11E1D  UIHHPH~xdH%(   HMHHvϊ DH  HqxEtz uX   H9r6HH9r*1z t"I  H@H9 t[ff.     HUdH+%(      I     H9rH9H@H9 ^  Hcf     D8A~Ic   DMH}LUHMgH}   HEgLEHM  HDMLUHM  IB0H0I9t4fH  H @+   HxxH@0HcI<H0I9uHA0H0H9t3H  H @+   HxxH@0HcH<H0H9uθ   HIH9rDH9rGHL9u1ff.     LHEHu H}HE~fD     ѐH    D8AEE9Ic   UHMLUDED]H}eH}   HEeLMUHM+  HD]DELUHM  IB0H0I9t@ ff.     H  H @+   HxxH@0HcI<H0I9uHA0H0H9t3H  H @+   HxxH@0HcH<H0H9uIcHI   H9r9HH9r-   A9tHIH9r8H9r:HL9u1fD  LHEHu`H}WHE   H	$LHuU*H}!HcE1E1LHu
H}11E1D  UIHHPH~pdH%(   HMHHvˊ DH  HqpEtz uX   H9r6HH9r*1z t"I  H@H9 t[ff.     HUdH+%(      I     H9rH9H@H9 ^  Hcf     D8A~Ic   DMH}LUHMcH}   HEcLEHM  HDMLUHM  IB0H0I9t4fH  H @+   HxpH@0HcI<H0I9uHA0H0H9t3H  H @+   HxpH@0HcH<H0H9uθ   HIH9rDH9rGHL9u1ff.     LHEHu H}HE~fD     ѐH    D8AEE9Ic   UHMLUDED]H}aH}   HEaLMUHM+  HD]DELUHM  IB0H0I9t@ ff.     H  H @+   HxpH@0HcI<H0I9uHA0H0H9t3H  H @+   HxpH@0HcH<H0H9uIcHI   H9r9HH9r-   A9tHIH9r8H9r:HL9u1fD  LHEHu`H}WHE   H	 LHuU*H}!HcE1E1LHu
H}11E1D  UIHHPIz@dH%(   HMHHvǊ DH  Hq@Etz uX   H9r6HH9r*1z t"I  H@H9 t[ff.     HUdH+%(      I     H9rH9H@H9 ^  Hcf     D8A~Ic   DMH}LUHM_H}   HE_LEHM  HDMLUHM  IB0H0I9t4fH  H @+   Hx@H@0HcI<H0I9uHA0H0H9t3H  H @+   Hx@H@0HcH<H0H9uθ   HIH9rDH9rGHL9u1ff.     LHEHu H}HE~fD     ѐH    D8AEE9Ic   UHMLUDED]H}]H}   HE]LMUHM+  HD]DELUHM  IB0H0I9t@ ff.     H  H @+   Hx@H@0HcI<H0I9uHA0H0H9t3H  H @+   Hx@H@0HcH<H0H9uIcHI   H9r9HH9r-   A9tHIH9r8H9r:HL9u1fD  LHEHu`H}WHE   H	LHuU*H}!HcE1E1LHu
H}11E1D  UIHHP   dH%(   HMHHtÊ DH     Etz uT   9r3H9r(1z t I  H@H9 tQf     HUdH+%(      I     9r9H@H9   Hc D8A~Ic   DMH}LUHM[H}   HE[LEHMF  HDMLUHM1  IB0H0I9t>f.     H  H @+      H@0HcI<H0I9uHA0H0H9ts     ff.     ff.     ff.     ff.     ff.     H  H @+      H@0HcH<H0H9u̸   HIH9rBH9rEHL9u1f.     LHEHuH}跕HE>fD     ѐH    D8AOEFE9=Ic   UHMLUDED]H}iYH}   HEWYLMUHMk  HD]DELUHMR  IB0H0I9tB ff.     H  H @+      H@0HcI<H0I9uHA0H0H9ts     ff.     ff.     ff.     ff.     ff.     H  H @+      H@0HcH<H0H9uIcHI   H9r7HH9r+   A9tHIH9r6H9r8HL9u1@ LHEHuH}דHE^   HLHuU誓H}術HcE1E1LHu芓H}聓11E1D  UIHHPH~hdH%(   HMHH DH  HqhEtz uX   H9r6HH9r*1z t"I  H@H9 t[ff.     HUdH+%(      I     H9rH9H@H9 ^  Hcf     D8A~Ic   DMH}LUHMVH}   HEVLEHM  HDMLUHM  IB0H0I9t4fH  H @+   HxhH@0HcI<H0I9uHA0H0H9t3H  H @+   HxhH@0HcH<H0H9uθ   HIH9rDH9rGHL9u1ff.     LHEHu耑H}wHE~fD     ѐH    D8AEE9Ic   UHMLUDED]H})UH}   HEULMUHM+  HD]DELUHM  IB0H0I9t@ ff.     H  H @+   HxhH@0HcI<H0I9uHA0H0H9t3H  H @+   HxhH@0HcH<H0H9uIcHI   H9r9HH9r-   A9tHIH9r8H9r:HL9u1fD  LHEHuH}׏HE   HLHuU誏H}衏HcE1E1LHu芏H}聏11E1D  UIHHPH~`dH%(   HMHH DH  Hq`Etz uX   H9r6HH9r*1z t"I  H@H9 t[ff.     HUdH+%(      I     H9rH9H@H9 ^  Hcf     D8A~Ic   DMH}LUHMRH}   HERLEHM  HDMLUHM  IB0H0I9t4fH  H @+   Hx`H@0HcI<H0I9uHA0H0H9t3H  H @+   Hx`H@0HcH<H0H9uθ   HIH9rDH9rGHL9u1ff.     LHEHu耍H}wHE~fD     ѐH    D8AEE9Ic   UHMLUDED]H})QH}   HEQLMUHM+  HD]DELUHM  IB0H0I9t@ ff.     H  H @+   Hx`H@0HcI<H0I9uHA0H0H9t3H  H @+   Hx`H@0HcH<H0H9uIcHI   H9r9HH9r-   A9tHIH9r8H9r:HL9u1fD  LHEHuH}׋HE   HLHuU誋H}衋HcE1E1LHu芋H}聋11E1D  UIHHPH~XdH%(   HMHH DH  HqXEtz uX   H9r6HH9r*1z t"I  H@H9 t[ff.     HUdH+%(      I     H9rH9H@H9 ^  Hcf     D8A~Ic   DMH}LUHMNH}   HENLEHM  HDMLUHM  IB0H0I9t4fH  H @+   HxXH@0HcI<H0I9uHA0H0H9t3H  H @+   HxXH@0HcH<H0H9uθ   HIH9rDH9rGHL9u1ff.     LHEHu耉H}wHE~fD     ѐH    D8AEE9Ic   UHMLUDED]H})MH}   HEMLMUHM+  HD]DELUHM  IB0H0I9t@ ff.     H  H @+   HxXH@0HcI<H0I9uHA0H0H9t3H  H @+   HxXH@0HcH<H0H9uIcHI   H9r9HH9r-   A9tHIH9r8H9r:HL9u1fD  LHEHuH}ׇHE   HLHuU誇H}衇HcE1E1LHu芇H}聇11E1D  UIHHPH~PdH%(   HMHH DH  HqPEtz uX   H9r6HH9r*1z t"I  H@H9 t[ff.     HUdH+%(      I     H9rH9H@H9 ^  Hcf     D8A~Ic   DMH}LUHMJH}   HEJLEHM  HDMLUHM  IB0H0I9t4fH  H @+   HxPH@0HcI<H0I9uHA0H0H9t3H  H @+   HxPH@0HcH<H0H9uθ   HIH9rDH9rGHL9u1ff.     LHEHu者H}wHE~fD     ѐH    D8AEE9Ic   UHMLUDED]H})IH}   HEILMUHM+  HD]DELUHM  IB0H0I9t@ ff.     H  H @+   HxPH@0HcI<H0I9uHA0H0H9t3H  H @+   HxPH@0HcH<H0H9uIcHI   H9r9HH9r-   A9tHIH9r8H9r:HL9u1fD  LHEHuH}׃HE   HLHuU誃H}衃HcE1E1LHu芃H}聃11E1D  UIHHPH~HdH%(   HMHH DH  HqHEtz uX   H9r6HH9r*1z t"I  H@H9 t[ff.     HUdH+%(      I     H9rH9H@H9 ^  Hcf     D8A~Ic   DMH}LUHMFH}   HEFLEHM  HDMLUHM  IB0H0I9t4fH  H @+   HxHH@0HcI<H0I9uHA0H0H9t3H  H @+   HxHH@0HcH<H0H9uθ   HIH9rDH9rGHL9u1ff.     LHEHu老H}wHE~fD     ѐH    D8AEE9Ic   UHMLUDED]H})EH}   HEELMUHM+  HD]DELUHM  IB0H0I9t@ ff.     H  H @+   HxHH@0HcI<H0I9uHA0H0H9t3H  H @+   HxHH@0HcH<H0H9uIcHI   H9r9HH9r-   A9tHIH9r8H9r:HL9u1fD  LHEHuH}HE   HLHuUH}HcE1E1LHuH}11E1D  UHAUIHATHLSH8   dL$%(   LeDeu_|Hު HxH ugH?LMHMHUHu]HuHU9HMLMLAD$E1AHEdH+%(   EDu2DeH8L[A\A]]HEdH+%(   uDeA   pUL$L HVHHdH%(   HE1jyHUdH+%(   u# ULL> HHHdH%(   HE1j)HUdH+%(   u ULL H6HHdH%(   HE1jيHUdH+%(   u UL4LT@ HHHdH%(   HE1j 艊HUdH+%(   u3 ULL@ HVHHdH%(   HE1j 9HUdH+%(   u  ULL HFHHdH%(   HE1jHUdH+%(   u  UL HHHL7 dH%(   HE1j虉HUdH+%(   uC  ULLe HfHHdH%(   HE1jIHUdH+%(   u UL HHHL dH%(   HE1jHUdH+%(   u ULTL HHHdH%(   HE1j詈HUdH+%(   uS UL| H=HHL dH%(   HE1jYHUdH+%(   u ULL% HHHdH%(   HE1j	HUdH+%(   u UL H]HHLW dH%(   HE1j蹇HUdH+%(   uc ULL HƺHHdH%(   HE1jiHUdH+%(   u UL< H}HHL dH%(   HE1jHUdH+%(   u ULtL HHHdH%(   HE1jɆHUdH+%(   us UL HHHL dH%(   HE1jyHUdH+%(   u# UHHdH%(   HEHऊ x uZ   LHvtAHUdH+%(   uOHV DH   LHML; 1HID  G| HEdH+%(   u˅fD  UL4L HfHHdH%(   HE1jYNHUdH+%(   u3 UL\ HHHLע dH%(   HE1j	NHUdH+%(   u ULL HHHdH%(   HE1jMHUdH+%(   u UL H=HHL7 dH%(   HE1jiMHUdH+%(   uC UHAWIAVAUATSHHHUHLELMdH%(   H]H  HEHFHEHc  ~.H  1 HH9t9uHIf     IH  E    E1J&o@ooH oP0ffffofsffI~UfH*Y M   fI*^HuL   UEHcI7I)wAAt{H  IcHHJ<& tHMH   J HyHƃfHH	H*XY. MwLLfHH	H*X_@ HEIHEIGHEdH+%(   uEHH[A\A]A^A_]s UHHdH%(   HE1HEdH+%(   uL   Lz c(     UHHdH%(   HE1HEdH+%(   uL L0    }c     UHHdH%(   HE1HEdH+%(   uL^   Lڴ -c     UHHdH%(   HE1HEdH+%(   uL L    b8     UHHdH%(   HE1HEdH+%(   uL   L: b     UHHdH%(   HE1HEdH+%(   uLw L    =b     UHHdH%(   HE1HEdH+%(   uL   L aH     UHHdH%(   HE1HEdH+%(   uLם LP    a     UHHdH%(   HE1HEdH+%(   uL~L 1Paff.     UHHdH%(   HE1HEdH+%(   uL7 L 1 a[ff.     UHATSHdL$%(   LeL% ID$hI$
  )     ff.     ff.     H   H9t2HHfHnfl@H8 ufHnH   flpH9uH H8DumH { t.{+ Q        
O{* $  H I${+    1   N{*    { uw{ uY{ u#HEdH+%(      H[A\]    HEdH+%(      H1	   [A\]yNf     1   dN{ t@ 1   LN1   @NHi 8 a1   $N1   ND       N{ (D        M      M      M/@ ff.     UfHnHHHGdH%(   HUHVXfHnflHWFXHHEdH+%(   uUHOfHnHHHGdH%(   HUHVhfHnflHWFhHHEdH+%(   u|ff.     UHOfHnHHHGdH%(   HUHVhfHnflHPFhHWHEdH+%(   uff.     UHAWAVAUATSH8H}dH%(   HEH㖊 H8km  L5 IIL9   HXH L%? Lx^HSXHC`fInflHBHHChHShCXfHnHCpflHBHHCPChHtHMoXIGXLM9ttLxI$  HtI$`  HЄuI$8  HtI$  HЄbID$HHtHLЄtH4 MoXHLIGXM9uHEHHMH9a      HEHH  HH  HEHMH9#   ff.     HUHBLjHL9   HL% LpLyd@ IvXIF`fHnflHFH0IFhIvhAFXfHnIFpflHFH0IFPAFhHtLI_XIGXML9ttLxI$  HtI$`  LЄuI$8  HtI$  LЄ`ID$HHtLLЄtH I_XIMIGXL9uHEH HEH;EHEH HEH9EHEdH+%(   uH8[A\A]A^A_]C UHAWAVAUATSHHH}dH%(   HEH H8i  Ht H8HtH5< XLHE  L- IE HL9   L%Q LxH LpI$   HE`IOXIG`fHnflHAHIGhIOhAGXfHnIGpflHAHIGPAGhHtLI^XIFXML9tPLpI$   HtH}LЄuI$8  HtI$  LЄdI^XIFXML9uHEHHMH9N       HEHH  HH  HEHMH9   ff.     HUHBLjHL9   L%! HLxI$   LqHEh     IwXIG`fHnflHFH0IGhIwhAGXfHnIGpflHFH0IGPAGhHtLI^XIFXML9tPLpI$   HtH}LЄuI$8  HtI$  LЄdI^XIFXML9uHEH HEH;EHEH HEH9EHEdH+%(   uHH[A\A]A^A_]w    UHAVAULoATSHdH%(   HEHGI9   IHXfD  HChHXI9tcH{( uH{  tI$I9t&LpHCHHt_LHЄuIFXLpI9uH=Ǒ HWHChHXI9uf.     HEdH+%(   u<H[A\A]A^]@ IFXHPI9tHBXHPI9uH=g HpUHAVAUATSHdH%(   HEHH9teIHXLwID$I9t&LhHCHHtfLHЄu*IEhLhI9uH= H ff.     HCXHXI9uHEdH+%(   u0H[A\A]A^]    IEhHPI9tHBhHPI9u@ ff.     UHATSHHdL$%(   LeIH9t|HHzHHZ"f     HCXL9tXHSXHHJHHO`fHnHGhflHJHHWhGXfHnHGpflHBHHGPGhHuHCXL9uIT$IHL9t{H2HzH^     HChL9t\HshHHVHHOXHW`HwXfHnHQflH
HOhHWpGXfHnflHQH
HGPGhHuHChL9uHEdH+%(   u	H[A\]D@ UHAWAVAUATSH8dH%(   HUH  HH9   IHXA   E1<f     EAD$LHDDHuE1SI  AHCXHXH9t={x uHotLHuHCXI  HXH9u     H ~R,AD$DEHEdH+%(   uH8D[A\A]A^A_]@ E16fD  UHAWAVAUATSH8dH%(   HEH  HH9   IHZA   E1Ef     Hu<EAD$HLDDHuSAHCXHXI9  tE1H|tDHUdH+%(   uH8[A\A]A^A_]1n ff.     UHAVSHHdL4%(   LuIuUHu0   w'   H HcH>f     C|   HEdH+%(   u[H[A^]ÐHEdH+%(   uBHLH[A^].fD  C|8       C|       C|	   f.     UHAWAVAUATSHH  dL$%(   LeIHH9t)HZ     HLjHCXHXI9$  uM$  M$  M9tN ff.     IFMnI9t+HX@ ff.     HL5jHCXHXI9uM6M9uHEdH+%(   uH[A\A]A^A_]fff.     UHAUATSHdL$%(   LeL%S I$L9t8HX@ HCXHHXL9t
   Hu	RH}Љ   ?,tHEdH+%(   uH[A\A]]ff.     UHAWAVAUATSH8H}HudH%(   HEH x )  L.L9  HGHEHEH@H9E  I  L`HUIH  f     L8tHuL   Et$xEuLAƄ2  MH  L9   A$        M?L9   A9GPuL=H  EuAGT IOHpXIIwIW HxXHH`H1IO(HphIw(HPhHHpH1ID$hL`H9E*Mm L9m1HUdH+%(      H8[A\A]A^A_]     X   &&IHteDpTA$   IAGP|IP  fHnAX  MP  fHnflAL8D  HuL$AUIE H9EEH H9Eu7 ff.     UHAWAVAUATSHhdH%(   HEHH9,  IIHXE1L=~)fD  ff.     ff.     HCXHXI9t[L9{@u틃   AL$v-Hs H9    x01(xBDHCXAHXI9uE   AF    Mu M9txDH    HxHEHp   H#I`  IHt^@   H"Ih  HtEHxHpLZE\  M6M9u1HUdH+%(   uHh[A\A]A^A_]ø:f.     UHAWAAVAHU AUA   ATISH(dH%(   HE1E~>  A9ANE1Ef.     HS L1A   fD9}LcE~61@ AHC rHkU    L1*HIA9uH9    L1
HLHUdH+%(   uH([A\A]A^A_]2fUHAWEAVAUATISH  HXDm   HhHT dLPdH%(   HE1Hǅx    |E~6  A9DOE1fD  HR    L1AFE9HcHR dtH    L1HHE   H    L1HPHXLLcY3H    LHI1IHcLD  HhH1ɺ   V:IH x    LLW
   LHx[HEdH+%(      HĈ  H[A\A]A^A_]fD  HYS H L1   HHYf     Hh1@   H<L1   HxLH L- sLIx*    UHAWEAVAUEATISH  HEHP   H`DuHR lHXdH%(   HE1Hǅx    5E~C  A9ANE1hf     HwP L1A   D9hۋlHcۅ~nDpE  EHu rH*P    L1HHE9   HQ L1AH    ~HHD9luH`H1ɺ   8IH| x    LL
   LZHxYHEdH+%(   G  HĈ  H[A\A]A^A_]fD  H    L1HXHPLLcA0H    LHI1IHcL(     H`1@   H6:L1   HxLH L-Z kqLIx@ E1D  EDhHN sH    L1H/P    LLcHT 1DhIHcLAD9luT@ ff.     UHAWAVIAUATASDH   DD4H(H dH<%(   H}H0AL$Mǅ    I   LE101ǅ    Љ MY  HLI+@@MpI+@8L8HA@,A@0L8HH  4DL8H(L8HMxIHI9tqLID8ME1ff.     4ELLAP 8D0H(M$$YH^M9uLD8H} AL$x   Ip D0H D4H(E2Hc} HË9B   fHA} Lx   HEdH+%(   A  HeH[A\A]A^A_] IP@Ip D0H(D4EH=| HË9GzLfD  H| xuH B !01MKL; >H@1   H=  HHLMHA| x8uMtIHt@p+E4AD$E1DRHˍ  D0H(AHXZ@ ff.     UHAWAVAUATSHH  dH%(   H]1H  L6IIM|  M>M
  IHH  H HH  H HH;  LM   I1LbLHMAIM9tyLLMILM̐H{   HH1ɺ   2Hb    LH13HHIL9uLLMLHL@LHM9t|LMILLM@ H{ B  HH1ɺ   |1H    LH1HHIL9uLLMLHL@LHM9t|LMILLM@ H{   HH1ɺ   0HB    LH1HHIL9uLLMLHL@LHM9t|LMILLM@ H{   HH1ɺ   \0H    LH1HHIL9uLLMLMGIM9tiLILMD  I Z  LH1ɺ   /H2    LH1M?HII9uLLM~IM9tY@ ff.     I    LH1ɺ   l/H    LH1M?HHM9uMt$IM9tN     I~ wfLH1ɺ   /Hf    LH17M6HHM9uHEdH+%(      HH  H[A\A]A^A_]fM6M9ufD  M?M9Y    M?I9    HL99    HL9L    HL9    HL9AfUHAWAVAUATSHX  HdH%(   HEHa{ LhHH MLD1H  LHA   Mk  IH  LM  MM  M
M7  M9MR  HI7LLLHL1MwLHHLHAILLM9H   HLHLLLHHHDMMID  I|$ wGH1ɺ   L,HҦ HIDI   1H 1HIM$$M9uMLHLLLALHMqMyM9   HLHLLHHHDMMII|$ wGH1ɺ   L+H HIDI   1H
 1HIM$$M9uMLHLLLAHMrMzM9   HLHLHHHDMMI ff.     I|$ wGH1ɺ   L*H HIDI   1H* 1HIM$$M9uMLHLLHAMxMpM9   HLHHHHDMI@ ff.     I|$ wGH1ɺ   L*HB HIDI   1HZ 1#HIM$$M9uMLLHHALrLzM9   HLHHHLEIfff.     H{ wIH1ɺ   HP)EH HIDI   1H E1bHIHL9uMLHLAMsM{M9   HHHHLEIff.     I~ wIH1ɺ   L(EHҢ HIDI   1H E1HIM6I9uMHLALqLyM9tuHHHLII~ wIH1ɺ   L(EHB HIDI   1HZ E1"HIM6I9uLHEdH+%(   uHX  H[A\A]A^A_]9f     UHAWIAVAUIATSH
  HHdH<%(   H}H!HtHI3H  Hp E11HLxLLDL0!Iǅ    Hǅ    ǅP   DHǅ    Lǅ    M  IELHHI+E@I+E8HAE0AE,jHH  H?    LHH1Åt(E1L5= L   L1rAAuH]    L1P   LLcH^ HHX1-HcHcLMeHL4IULI9t\LLE1IԋHHELAPPL0HHZIYL9uLLH0HHHxuIE@HHPI} THHǅ    ǅ<    IHǅ    Hǅ@    HMt	  IELH@HI+E@I+E8HAE0AE,H H  H   L1Ët,E1L%"< @ L   L1AAu⋅PHcH uH=    L1hH_    LHH1MHX   LA14IuHcIcHHHHHIEHH9  HLL%q E1HH   L1Hǅ    Aŋt/1ېff.     H; L1   AŃuEMc19fD  H< H L1   KHIōC      TH rH:    L1HIŅt tH    L1HHH@LHcLH    LHH1LHL,HH1ɺ   N"HA|$ $	  LHAPL
   HCHLH HH;VLHHHHxuIE@HTI} E1Hlǅh    Hǅ    Hǅ    HH  HAHHHHH+A@H+A8HA0A,hHHHp[  H1   LH;HËt-E1IfH8 L1A   AuLHcE1IfH DrH:    L1AHHAuHXL1L   LHHLaHHQHL9W  Hm HxE1IHHHff.     H   L1Hǅ    Ët/1ɐ   L1Hg7 ÃuEHcAE1   fHy    L1DD`HHHAu	E   1H8    LHߓ D`DeD`DHcHAA   lD`DDPH6    L1
D`DHHHKf.     H    L1HHLHc1HĿ    LHH1HHHH1ɺ   L4IHx   LLA1L
   tH?M$$HM9HxHHHxuHA@HDlHy 1E1ADxǅ    Hǅ    IHHM_  ID$LHHI+D$@I+D$8HAD$0AD$,H`Ht  x   LcIT$MT$II9   LAMHME1ff.     EHED8   AL PHH(0HAZIA[H(L9L D8uMDIHx  DELHIt$ A   IH;XtL`MHx  LHM;AtHpHZHHx  HH<LH<;FtL MHL@Hx  HHHH;FtLMUHDLLDx  1D  HUdH+%(   
  He[A\A]A^A_]IT$@EIt$ LDA   IH9X\HxlHH\H9OH1   H=Au  HHHh&Hx8u.H t$HH Ht@p+\EE1LA   HTt PXAXAYI@ HxuH qAh@ L1@   LLLLYL1HHH    SLt LILH1@   LLH1   LHHH H ,SHI~HxuH l~HH9H1   H=zs  HHHhHx8u.H t$HH Ht@p+h\klL   E1HL%/ Hǅ    1ÅtL   L1 AAuDHcE1&H1 L1AH5    ĻHHEHd rH/    L1蜻HHAuH    L1{HHLLcHu    LHI1GL   1HHH=}q HHNd IĀz `  LLIL
   &Hj8HxuH THxH 	Ѓ!PHH9H1   HH=9q  HHhHx8u"MtIHt@p+\THLE1   L%y- Hǅ    1ÅtL   L1ҹAAu⋍Hcۅ  H^    L1蟹H.    LHH H1}L   LHH1fHy    LHH1KHHLHLcHE    LHI1L1ɺ   HHH=Mo HIHb x   LL趻L
   H=6H1@   HH=n WL1   HLH L%{ NLILLHs    ID<Ic+ML90H1   H=n  HHLhHx8uMtIHt@pD)\HHn E11SL0LHXZAoD$8fofsffH~H9ID$IL$HIH9  H\ H8   Hw,    LHH10HZ    L1H   LD,1H    LA1Lǅ    A\ HHH_ HH̋ HH&[ HH1ɺ   LAH    LH1hHx    H   L1?HË;AQ  M6L90  HL1Aݾ   E1HY) L1A   صAuA\ /1@   HH=l lL1   HLH L% KLI11LL#H[ H H8sxy@mIIH9HY E1HEHMl$ x:f.     AL   AL   H?Y E11HLUHAWAVAUATSHHH] dL$%(   LeIԀx   HX HO@@$    ?  H0  Huf
HuH"  IH? Hu1HEHE     LIH   H) L1   ۳HULILcHHU   LE1貳IwLEcHU   LI1荳HcUHIHcUMIIHW Lm;X[HUU  f.     H   HHW @
  H0  HuJ	H
  HuIH# E1HEHE    HufD  LIHqHULIA@H'&    LE1觲IwLLc8HU   LHE1聲Hc]HLH]HHV H]D;pt    HEdH+%(   u]HHHH0  L[A\A]A^A_]AHV HF 1011HEdH+%(   uHHH[A\A]A^A_]/@ ff.     UHAWIAVAUATISH8HUdH%(   HEHZ x tH   Q  HMHH9A  H5Z LpA   H2 HVHI7HHuHEEHE7D  AV(LLLAHII)GIFXLpH9E   A~x uLI$  ucD
]t%IwI?HA 1HMDL>HII)GHY LLLHxH hIF H[ЉXfHLuIFXLpH9Ea@ ff.     I+EHUdH+%(   uH8[A\A]A^A_]@ 1@ ff.     UHf   HAWIH=. AVAUATSH  H`   dH%(   HE1H)Hǅ    HHǅ   HX H5X HHvHI  GHpP H0  _  HE1HxfHyX Hǅ    LqHH9   MH Lj   LD fD  I  1IUXLjH9   A}x uLucuuH`L覱LxDLLHAUuH`Hnyf     LLuIUXI  LjH9cf     H`
   AHhHpP A9}%Hٺ      H=, PI  H0   HEdH+%(   O  Hĸ  [A\A]A^A_]E  HHEEA	F  @Hd CLvM  HEӉ@I  L`HHHXD,Lhǅx    ǅP    H8     F u&@   L1L~  H AHhHAHQIHXH9tPfD  HߋxE1LHSLXL1HHݤ    裬HCXHXI9uH8@ p;x~KL
   H8xx;A   L      H=* x HhH HhH;HtLpPIfD  IBMzI9   DGL`HLPHhDMAX xE1LE1HpHhAVHC5H{    LH1zIFXLpI9t[A~x uLlu(EuH    L1=vfD  HpLuIFXLpI9uLPML;HLht&H7    L1LhfPLpCD,PH`      H=5) F a  H@T HPM  MbIBHxI|$L9   LpLHAT$HP   H`Hɚ L1I$H9xLp   hE L5 L`LE0H`f.     HL襬LLHAT$HP   HHA L1葩ID$XL`H9xuLphI
1HH;H   HxHωfff.     HGLoI9A  L`GAHpL㉍hXA1fD  AHxLHA E1SAHCXHXI9t5{x uHתtLH(uHCXHXI9u    HphXD9H?AB΃H;H3H0AH1 H`H    HHHEHPL	H1/   Hپ   H= V      H`   H=&    *I  L`HLhH9tkA}x uWLѩ      HLL1AUAą    L.   A9uI  1IEXLhH9uH`
   H   Hپ   H=5 xHpP 0HP CLvH`H AȾ   LHP1uAYLLKI  UL      H= I  1HHߧ@ ff.     UHAWAVAUAATLcSH   H 6   LLhD\dH%(   HEHVO HXH-H\ H
  ]   @-[...fP1Hn\ H 
HO H   Htb/ǅX    E  LtUHǅ0    9X|BH=k\ FHEdH+%(   
  H0H   [A\A]A^A_]f.     L LHzN DhI  HyH LDL>HPH	  LMW0M	  MHǅ0     ID$L9MCHJL`*  HH\/   HPM  fHE    )EHpH`M   HxHM DXE8  x   I  x    HpH-HP   1HhH+G AfA   t r  McL0LtX;X  A      I      L   貶IH  fA   uHL I^x  I  Mf(!H  HL y tIVxL"Mx4fI*Y HxEfH*^Z`     LAfHL	H*XY HyHfHH	H*XfD  \H(H A	    ~1J u(L@Hh1L AH    v fHhLZx H       Z\@LeX;XR@ ff.     HP]    HF 8)I   HhH8HFHHK    HH$ H1诡f.     HPHuHHE    )EHEH`HE*} pHPHhH\D 1   GHH0Af     x tI   $HEJ H`HK Lv HPL@H@HD8HA	  @1N.L@HpHxHD8I  HH)HpHJHHxH@H9  LaHH; LLLpEHHEKH(Hp H8EAD
K[  H(H81-HHpH)xHI HLLHxH +  AT$(LLHHpIT$XHxHHH)HpHxH9@  LbETLLR AT$(LLHHpIT$XHxHHLbH)HpHxH9@  H8H(1,HLLHHpH)xHH HxH qID$ HcЉaf.     E1     ID$ HЉf     I LeE1L`L@LPD8D  AEII;srM  fHE    HH@LeL})EEnI  _'} uHhL   1H@ 8AEII;rD8McL0f    HhH =XfMH   HH)1H8HpHPHhHx   L@CL@AI  HH9   HL= L(LbHIDLpL8LPH@N     AT$(LH@   HhIH 1诜AID$XL`I9  tBH`LpHLH8HxHE HxH uID$ Ht@ L(Hh
   L@yEd A   t#fA   L@tHAE x    IcH0      LLH UA  Lq H L@L@1-)HpHxL@HHhLHAtHk H8LHhHHDHH0@Hǅ0    Hǅ0vHC ,      H=( H8> ff.     UHAWAVAUIATSH(G8dL4%(   LuIEEE1E1S@ DffHH*E   LY" H H*ȸ   ^`HIIIWtlDH5 HH/tH\C GD8x) tEtMt
} mHH L1   IHIIWuHEdH+%(   uH(L[A\A]A^A_]f.     D  UHHW.dH%(   HEH\? G     fG$H]>  fG&)fG(HEdH+%(   u蠚U   HAWAVAUATISHdL<%(   L}IH5ˎ    H= L- IMHtL{.t'I~ I HuE1LLID  L(IIHt־,   H "Ht  HxHcHHMdID1HUdH+%(   uH[A\A]A^A_]詙f     UHSHdH%(   H]_0w0HHEdH+%(   uH]\ff.     UHHdH%(   HE1@t5       t)    u f/q 2   s1f.h @ƃ3HEdH+%(   utߘ@ ff.     UHHdH%(   HM1HMdH+%(   uw" 荘fff.     UHHdH%(   HMHudH+4%(   uHw" @.6fD  UHAWAVAUATSH(G$dH%(   H]HEW`4   EH腬    t          Ds&E1Dk$vAFJ1HHHIĿ   Et+E1DDH01E9@A`E9u1ES(A    { s")MC.*   u0HsPHt'HEdH+%(   uAH(11[A\A]A^A_]HEdH+%(   uH([A\A]A^A_]fEvfUHHdH%(   HE1HEdH+%(   uHk%視fD  UHHdH%(   HE1HEdH+%(   uHHjeD  UHH   H`HhLpLxt )E)M)U)])e)m)u)}dH%(   HH1HEH0ǅ0   H8HPH@ǅ40   HHdH+%(   u譕fff.     UHAVAUATSHdH%(   HE1      IItCHG   u{H!    HLЄtHI;\$   ID$xHuH_MnM~kD  H HLЄtHI;\$~   ID$xHuIsI\$HEdH+%(      H[A\A]A^]f     1ItH[fHLЄtH[I;\$tID$xHuIf     1HX     ID$xH4HLЄ$H[I;\$u1+ff.     UHATSH dH%(   H]H   H{tOu-HuHuHLfH~KfHIsH{HEdH+%(   uXH [A\]fD  Hu跜HuHLfHIHt@ ff.     HIuH{|RfUHAUATSHH_dL,%(   LmIHt^E1HhHHt(D1L+DHLAUhAE(AD9uDHUdH+%(   u'H[A\A]] I}HIE1Hu誒f.     UHHHwdH%(   HE1H;7HUdH+%(   uc UfHHdH%(   HE1HEdH+%(   uHGp11@ ff.     UHATSH1HdL$%(   LeI1E8   HhHEdH+%(   uS$HLH[A\]/誑f.     UHSHH(HudH<%(   H}H= 9 3HuHG)HEdH+%(   uH=8 H]GBfUHATISHH   HXL`Lht#)p)M)U)])e)m)u)}dH%(   H8HCXH   HHH=d8 wLH(H{@LH{HHC@HE   HH(H{HH@H H0ǅ    ǅ$0   eAą6H=7 2AH8dH+%(   uBH   [A\]fD  H{HH=7 1    H18 HCX	ӏ UHSHdH%(   H]HH=T7 grH{HH{@HEdH+%(   uH="7 H]pkff.     UHSHdH%(   H]HH=6 HH=6 #HEdH+%(   uH]1    UHSHdH%(   H]H1ܥHc H6 Hs@HHHD1HEdH+%(   uHH]]+蘎     UHAVAUIATISH   HHLPLXt&)`)p)U)])e)m)u)}dH%(   H(1HEL   HHH0HH ǅ   ǅ0   yk LHH H=) 謅tH	H(dH+%(   uUH   [A\A]A^]D  HELHǅ   HH0H ǅ0   L/1# UHAVAֺ    AUIHuATSH0dL$%(   LeIHMDLLa HP MME1聓HUdH+%(   uH0[A\A]A^]蠌UHATISHdH%(   H]H@ L`HHtHUdH+%(   u	H[A\]FfD  UHATISHdH%(   H]H@ L Ht   tH5z3 ȍPE<YHEdH+%(   uH[A\]UHHdH%(   HE1   HG    HEdH+%(   uHwHGp1vfD  UHAVL5G AUATSHHL%2 dL,%(   LmAff.     LHLD*      ti    u`v"f{* tvv uƃ   f.     HUdH+%(   G  H[A\A]A^]Ã t+wЍ  IcL>    HKs(   H1H9LJ<H9sHHL)H1H;HHS   SpfHCHs(H9  H)HHHSH޺   HH)Sp S*fK,9fC,vfD  f{* S,ffS,L@    HH93HKS(HHHH9H      HHKSp H s(   PHcH9   HH)HH޺   HHCSp@ 1џHSXHs@H H{HHHtHSHHH9`HHHHS   SpAH1pfD  H1iQUHAVAUATSHLwH_dL$%(   LeIL9|   HtwE1@ ID$xHtHLЄu*D1L DHLAT$hAD$(AD9tHI9uDHUdH+%(   uhH[A\A]A^]f     I HLЄtHI;\$t"ID$xHuI\$I9S1fD  1I\$I99If     UHHdH%(   HE1tHt#uHGHGHEdH+%(   u2fD     HT0HGHHG    HHwɆf     UHAWAVAUATSHHGLodH%(   H]HAM   E1;   sdL=* P HCxHtIu HЄu&D1H=DLHShC(AD9tAID;   sAA9rHEdH+%(   u&HD[A\A]A^A_]    LkLk\ޅ ff.     UHAVAAUI   ATDSHdH%(   H]؉
LDD|D){~#HEdH+%(   uH1[A\A]A^]W    U   HSHdH%(   H]CHEdH+%(   uH]1x UHAWIAVAUATASH   H(dL,%(   LmIH9   /S(HCIHI9  E1L9sEA)D)ADDHvD~"DDH`L;k   l   |AT$DH<q   bHAT$D"+   HsfD  HC   1I9   S(IHI9rpAEDH߉MMA<!HDDC(HCm   I9RHEdH+%(      H(1[A\A]A^A_] EA)ED  EDH߉EA)DQl   wDHAT$7   MAtMHCDD)D  EDHA)Dm   "HAT$D   E,HC.тUHAWAVAUATSH(dH%(   HE1~2IEƿ   AAՉ ID$Et6B+HH9   HEdH+%(     H([A\A]A^A_]@ DH9rA)AWLD&t   LLDD   $HEdH+%(      H(1[A\A]A^A_]\@ )EwLDt   y"d@ LD   rDDA+t$9|DLuzl   uLDb   xO DA+t$<If     UH=HHdH4%(   Hu1IH5ҥ HA  Hҥ Hå =ͥ @H5ɥ H  Hɥ H =ĥ H5 H   H H = H5 H   H H = ŝH5 H   H H = 蜝H5 HtxH H = wH5 HtSH H = RH5 Ht.HEdH+%(   u0H H = D  HEdH+%(   ufU@HSHHdH4%(   HuHH' uo~:  z         HT HcH>fD  O@HPt H1\HEdH+%(   U  HH]ÉH&t H1-     Hs    uMfff.     HM H1
D  Hs t܉Hs H1
h@ >wٍ Hs H1
=f     Hds     H^s t@ H<s d@ H2s T@ H's D@ Hr 4@ Hr $@ Hr @ Hr @ Hr }f.     f.     f.     f.     f.     f.      UHHdH%(   HE1HEdH+%(   uHL}ff.     UHHdH%(   HE1H9HUdH+%(   u	}f     UHHdH%(   HEH&  tH~(HUdH+%(   u|ff.     UHHdH%(   HE1HEdH+%(   u{|ff.     UHH   H`HhLpLxt )E)M)U)])e)m)u)}dH%(   HH1HEH0ǅ0   H8HPH@ǅ40   HHdH+%(   u{fff.     UHHdH%(   HMt5       t8    u/HG8HO# 2   RH@H)H ;H0t1@ƃ3HEdH+%(   uƏ1{UHHdH%(   HE1HEdH+%(   u鐏zff.     UHHdH%(   HE1HEdH+%(   u
@鼁z    UHAWAVAUATSHHHW8Hp" dL,%(   LmIHZ@H)`qAHF" xHҋX$H$ ڀx uL4   LǎAE(1҉LH@HEdH+%(     HHD[A\A]A^A_] M   H57 UI@MLEIE8HHH# LE@Hy-HMALEUHZLuHuLǉUHi! LE@I)I@$E$LEI>Ip8訌LEH  uuuH5" > q  A   @xuEE    I~ tH" x	E6   LLE|IuLUM@@utuD֦LEI@xHPHx(   Hh" 8       @ ff.     ff.     HBxHPHx(tH׉MLEHU諁HULEM   HrHHIHI   M萏MEE1;ELAu)ȉI@@tuDh HBxHPHx(t   Y    A   @tuE H2\Ip8H=m GwfD  UHH   H$ H`dH%(   HEH   HVHx(uPL@@MtgH1@     Hql HHMHEdH+%(   uB@ HEdH+%(   u-H=1m @ HEdH+%(   uH=k v    UHAVAUIATSHHpHp dL4%(   LuAHW8@LbI)DH5"  EE E   E1> u      H@EC$fHnHH]~O fHn o   H=GflÉEH   )E~O H}fl)Ef)Eo   foflfm)E)pH= w	HtHEHpHULLm} tL   HEdH+%(   u'Hp[A\A]A^]f.     ȃ"   	;uff.     UHAVAUATSHHHG8dL,%(   LmIL`H HǇ       @MI)LLLL   pIHH9  Lhff     I     Ic   ~^HP f@Hw=HcID HH)IT  ff.        H8_f(H9u f/vI   HI  f. z:  H   H:     H Hk8Lc@HIKt      \f/wvHBHt=HJ1   Lpf.zuH8H9uHBHuff.     HB7f.     HJHtHQHuHAHD  HBHuHBI   fI   LA   H8޾fIEpLhI9iLL)|H   HEdH+%(   u-H[A\A]A^]fD  I   I   L1srUHATSH   H$ HpHb LGG HO8BHz Hg LQLYLEdH%(   H]H   HL HH@     @  AQLg MJ-PIC H   1`1H 1Hl8   H蓆S$HH߃mHEdH+%(   unHe[A\]D  H! A   H4h H!g    LH81LLApLLH) Lkqff.     UHATSH   H$ H   H$ H    HGH@ dH%(   H]H_Hg  謂1Hs-HH=f HEdH+%(   uH   [A\]p UHAWAVAUATSHH dH%(   HEH   RHHG8H@H)L(L9tGHC L'I8 tH     H{(tH{0IHtI   Hu[HL9uH=e w1   H{0IHtI   Hu"HL9uH=e >1       LEfAG&fInLflfAt[MtVH5 >    H[H{(   HIWt'Ht"H[H{(tHIWu    I_   AƇ   AƇ    HUdH+%(   u^H[A\A]A^A_]f     ID)f     B H[MgMIuH[H{(K7nD  UHAWAVAUATSHH dH%(   HEH   RHXHG8H@H)L(L9tGHR L'I8 tO    H{(tH{0IHtI   HucH[L9uH=d 膌1       H{0IHtI   Hu"H[L9uH=c E1   fD  LEdAG&fInLflfAtSMtNH5 > tH[H{(   HIWt#HtH[H{(tHIWu I_   AƇ   AƇ   HUdH+%(   uqH[A\A]A^A_]f     ID) ff.     ff.     B H[MgMIu{H[H{(<(lfUHAWIHAVIAUATSH  HXH H@*   MgLPSHp~wF HdH%(   HE1HHƅfHnHXLflfHnƅ)~ LflH()M  IGH@ HHg    LH)H(H HHH9HHtAD$++  HXHLHg  L-S A}  u=H(H@4HHfD  Hx( H `  H9uH=a 1课H@ H ! I9 tLI  H" I   H=l! LHz! A   ! iH  HH=` A}   H(H@FfHR(HfHA}  )  HP V  HXE1H  H8HH H@HH% DpH@HtD`L      H8LLPHǅh    A}   HP1H` H  HHL)HHHXH{LM  Iƅ L M~A}    ANdH߉0x`0fHnfHfl)pHtbft]A}  j  rH) ff.     ff.     ff.     MHxHHuLL ƅ HXHh1qH  ,  fD  DHEeAEQ  =  .	  .  @=      Ht HcH>A}  H H   H^ I<HEH)H	^ 1S+ ff.     Hx(H H9u     MI(t"D  HHxMI(uANh7A    A      E1fff.     H] DDHE1HH  Hx(!  Hx '  Hx	  H{HhHH lH0H wYHtTHG HtF1ېff.     HWL$Mt" I|$&Md$MuH0HG HH9r1HH9   t#H= jwH= H     cHEdH+%(   6  HeD[A\A]A^A_]E1AEH
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  AEH     L MYM~A}    ANdH߉0\0fHnfHfl)ptUHtPA}  utrH)D  ff.     ff.     MHxHHuLƅL MI(uf     MI(tHHxttMI(uӀ9 u;H9G$HZ H5Z H=Z U,9 HH=h[ E1Ht x      fPHHuH Hǅ0    HtH@H0HH  HHpH+xLB@Iκ   HI)LA} LLuAEA}  ,  I x4 8	  IcWxI9l  @(L   AE  HH߉AGtHL)HxHpA} tAE H=@Z 軁HXH<HHH0H8vLpHLDL LP      H8LA} u3A}  H H   HX I<HEH)HX 1HP1HY H*HE1Au	/E1xHHH57 H=1^ H V @,PLx1LpY^E1AE   <CAEE1HHAu%E1AusE1AufE1H5\Y H4OE1H HH4E1AuH    H0   HP1H`X HxHH  A} HH@Lx Ag  H=3X 1褴Ag  E1HHXH 
uE1HhHu  H:UE1H9G$HV H5V H=V M$9 HE111FcE1HHAu}E18 e9 Y  HsE1HfD  HXHMtDM;6t?A  f  A./  AG=   yH5o HcH>     A  &A.   AG=   *H5r HcH>f     @Hu HcH>MqLIHmHzhIPf=  B=   M(LyIH$HIf     ANhAGZHu HcH>AGLHv HcH>IcWx  L9I HAE LN   @,LHIcGxHL)x    @ H: HH@LzI)I@,HP H(HPI+t$H8[qHHH1H5H=cH HH0H(H84 (RfL M     I?HH.C  L-/ @EwtLMIGLEL  AA   H Iw8PHH@H)HHH9t4HpE1A}  tfH   H9tcHIHPpHBH9uH=R 1AfD  ff.     ff.     HPpIHBH9tH;   uHPpHH0SDH0fHnHfflH)pt>ft9A}  v  H)4HRHx@H@H@uHƅVIHH9u  fH H9  DHxExHcPxIAbuCAEH   hA  A   aH5.X uAbuAEH   %H A9  HQ HP    H81YAbAEH    1H5H=H0RH9G$HP H5P H=P ]49 l"H H@Hx ~H EOxAE  I8LLD cHHXLVLAE D I @4IHH9u/@ ff.     H9tHx( H x
Hx(t5H H9uH=P 1D LTLD IHL:L9u   @ ff.     M?L9k  E9OxuL1IcwxHA}  LI H=_U wH@HXH  IGH9u   @ H@H9   xxx\H=HU [wvH=gU JweH@ WH@HxEAHXHHRHz(uHRHz(tHHxHRHz(uH@ uE1H@ uE1hL   HHI L8AHAXD  UHAVAUIATISHHdL4%(   LuI111_   HEdH+%(   u$HMLLH   H[A\A]A^]7mWfUHAWAVAUATSH8dL<%(   L}L   MsIGHUIHH   H$ Lw8RH)HI>I  Ip[H   AoL)EIGHEHME1HuH   LlHHEdH+%(      H8[A\A]A^A_]D  HEdH+%(   u\H8H=fS [A\A]A^A_]t    LHHEdH+%(   u$IwH8H=RS 1[A\H-A]A^A_]饩@VUHAVAUATSHL   dH%(   H]H-fff.     ff.     ID$(I9D$(Md$0A|$@ tIE1' HC(H[(H9IExIDHtPHLЄtDL9tB{@ tHH[ HtHS(H9S(tH;C0tfff.     HIExHu@ IHEdH+%(   uHL[A\A]A^]IUf     UHAWAVAUATSHHHHuHG8UL(  H  dL4%(   LuLvHEswM  HEHfH-  HE[H}HG(H9G(K  @H5PN H1+LuLe15f1H52K H1DfHn[HcEM$$Me  HML9HT  HUI9$   B  H y) tA$  tHMPHIc$   UHAHE    LhIGXHH@Ht5M   fI*Y(j H   fH*^EuH*vEHDDZHo x u)x EH5$J H߸   ֆLH5I H1輆    HƃfHH	H*XdfLLfHH	H*X'    HELuH8IvIF(   I~HtI H9tH}H5% @ HDHH5\' HDHA~4Av0D    RL<' PHAv H5II 1H HEdH+%(      S$HeHH5& [A\A]A^A_]龭fD  H   I~HH H9oH}H	% H5H @ HEP@ fHX1    HH5{K F   H5u& HߍP;HEL\& HLLH52H @8D    1HEdH+%(   vQfD      H5K H1ʄD  IFLG H9tHEx@ H*$ LDAN4AV0H1MF H5G 耄ff.     UHAVATSHdH%(   H]H^K4   IIHE1ff.     DC0H1EMcIfff.     H9  tZH9   uQHg x) t
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ǅ   ǅ0   At$	I<$8HsH;LD   輽HI<$H5  A1dH(dH+%(   uH   D[A\A]A^]J1f.     UHHdH%(   HE1HEdH+%(   uLwډ LP    靛0     UHHdH%(   HE1HEdH+%(   uL'ډ L     M0     UHHdH%(   HE1HEdH+%(   uLى L    X0     UHHdH%(   HE1HEdH+%(   uLى L`    魚0     UHHdH%(   HE1HEdH+%(   uL7ى L 1`/ff.     UL" HHHL؉ dH%(   HE1j蹸HUdH+%(   uc/ UL" H-HHL؉ dH%(   HE1jiHUdH+%(   u/ UL<" HHHLW؉ dH%(   HE1jHUdH+%(   u. UL! HHHL؉ dH%(   HE1jɷHUdH+%(   us. UL! H}HHL׉ dH%(   HE1jyHUdH+%(   u#. ULL! HHHLg׉ dH%(   HE1j)HUdH+%(   u- UHSHdH%(   H]HH   ;fC$HEdH+%(   uHH]$-@ ff.     UIHAWAVAAUA    ATSHH8HULMdH%(   HE1~y t~xEAA-E1    t"IB(HtHԉ E1RH)H8 AS$AFEHDLU)URO4   tLUHE5   IL   @H5A1DHDH5 H1HDH5! _AH+螙HEdH+%(   uUHuH8H[A\A]A^A_]鲇-,fff.     U1HAVAUIATSHL   H   dL4%(   LuIMMtpMd$Hc1LH)H" LI$  M$  ٷI$  LM$  H" 1HcH)L護A$   u0L(jHEdH+%(   u9H[A\A]A^]f.     HcLH]" H)I| 1T+ff.     UHATSHH Hԉ dH%(   HUHHx(    H҉ HHB(H)H8    H   H   L   H   HrE1HL0@qtu6   I$   tFHUdH+%(      H [A\]f.     H   H߉E؋rH,E؅u1H   HߋpH,H1fH   H-  NfD  H   Hp(HUtHU؅1[)ff.     UHAWIAVAUATSHhH~dL,%(   LmIHC  (H讃D`dMcL/kHHt  I}  H3  (Hv  HLH1gAI} HuKI   HH  +H=1HUdH+%(     He[A\A]A^A_]f     HЉ L   IL9uH@B I@B     HuDtYHM    LHHxYH   1HxHctLML QA)HHIcuXZ  I}(Ht?H-fD`dMcf.     IM(E1HH-H< Ad   Ad   x'UHSHH   H   dH%(   H]HH   H@H芊HEdH+%(   uH]1~' ff.     UHHdH<%(   H}H~ HHEdH+%(   u16'fD  UHHH   N4dH%(   HEH   H    H   ]HEdH+%(   u1&D  UHAVAUATSHHL   dL$%(   LeILA  H HI1L譲MtHLH LH)H<1苲HEdH+%(   uH1[A\A]A^]8&     UHAWAVAUATISH8  dH%(   H]H~HAHD  <AL4Ij:H͉ x tH9   @  HLHH藊D   H? L HHA LDHH 1AU薱HH5o LLc1XH  H5[  	  XYHthAƄ$   E   HHD   H L Hb A HLEH1HHIAT$$LD)7EtI$   HEdH+%(      He[A\A]A^A_]        H۽IHHH  % H9     H IHnH9ud@ 2   LH8H#ff.     UHAWAVAUATSHdL$%(   LeI$   uFI$@  HA$6  AƄ$4  HEdH+%(      H[A\A]A^A_]    I$0  I$0  HA$6  E1<xHtHgHAI$0  xHHtL5dƉ f.     HhgHHZHCL{DhyHCH9CtHS HCH@yLAFtuL"fUHH0Hʉ dL%(   LUIx uo   MJtYIrI:L 1Hfa LMLU蕮LULMH5m E1II9UMHEdH+%(   u5ɉËO| HLˉ LHjLB EXZ!f.     UHH0Hɉ dL%(   LUIx uo   MJtYIrI:L. 1H` LMLUŭLULMH5 E1II9TMHEdH+%(   u5ɉËO| HLʉ LHjLr uXZ*!f.     UHAWEAVAUATISHӺ   H  EH`Hh   HLXLmldL4%(   LuLu Hǅp    Hǅx    {IHvȉ x upE   lMLHDhLAHp莜Hx肜HEdH+%(      HĘ     [A\A]A^A_]     L1@   HLLHLPi}LP1HHHxH    衴L LIxE0HXH`@   HLPLP1HpHH    9L LIpN ff.     UHAWAVAUATSH   H$ HH  H=Z dH%(   H]1[HH  H=)IH  HH    E1HHH    HHHHL踨H  xuHHX1   S      LL) HkH5+ HRIXZMtHL      HvHL   L"ASH=< 1EqLmRH1D~D9  AHMcIN4+ff.     HHRL9uHID  HHRL9u   f.     HIculHH?HXlHHt	AHH<rRH=# 1dpL!ff.     LxQEAHEdH+%(   uzHeD[A\A]A^A_]HHkHtA=Ԋ  uH HE1Ԋ H HH;蜘HH= 1oKff.     UHHdH%(   HE1t$H= 1no1HUdH+%(   u ff.     UHAVIֺ   SH   dH%(   H]H@HHvHtbH{É IHHپ   LBHH  MLD1Ho& 9xNHHUdH+%(   u]H   [A^] LHMt!IH 1   y1 HH 1   ʯy1fff.     UHAWAVAAUDATMSH   H}HH]dHULXHUHU fMHUdH%(   HU1H zMDLEOoDmH  HCvH}|^EH}H  DxD}D}Hj  H}i^H}HpLoHwLGI9"  HhE1A   HuLE;    HHD}H}DU  A+   Mm E1L;mt|Eu}    DEA    A}y tA}xEAA-HHuHDLSu|DPLEHuH}D#M fEH D}\D  HhA-uDALO@Hw DdHuSuLXH}fED}H D}H}DUuHpD  DxED)HUdH+%(   u7He[A\A]A^A_]D  oG8fofsffH~L9E*`UHAWIAVAUAATISH   HELHLXH`fndH<%(   H}H  H8Hڿ x    I   L0H E@O     H`MDXI0  LHL8H HXy tM$   HUdH+%(   a  He[A\A]A^A_]    Mw@a    I0  lH1HtHHPk[ƅ HPHu!oB8fofsffH~L9 nHPDhL       H@H8@   HuHxHM   1HxH EHxH0  H E11E1HxHǅ0    HHHLLLXDh   H0=L5fnnhhL`i  HP [  HPHH@ZHǅx    HPHXH HHXHHI0  TjDPH  HHP   YHPHuoB8fofsffH~L9nhDLXLADPH*  HBHH@H((YH@A   ǅ@    H LrHrI9c  DH0MHA?HIE DPDL`   +$  M?E1L90  Euh /  @p    Ay tAxۃ-IE HuHDLLAUHVL8H(D#hfnH DnC DLPD)@ Hǅ0    H@LhH(H(I9a  H01LMA$   L(1H, M?M9tPHxHLA$   MHHHuIH  ǅ@      @ E1H@LxHPI9  HH@LE M?E1L;@t9   HLIHxEMEHuIHA DfIIH4fhL+     HELZH8I9   H0MHf     HIE DPDL`5+   M6E1L90   Eu	h u{@P    A~y tA~xۃ-IE HuHDLAUHRLL8H(D#hXfnH DnG    ǅ@      z@ EDL`aH E1A   1I UHAWAAVDAUIATIDSH  \_$dH%(   HE1>3A$0  fA$(      H~ y    ʄI  A$4   u#L爅pHxypHxA$6      A$5     H  HQ1fE9}(txHLLfHlAH   LLwHǅ    PvXZ!tI$   M   I   ftA1HEdH+%(     He؉[A\A]A^A_] HuǅT   ƅ[ ǅT    ƅ[ [11DfLxǅ    LI   xH  H2H9  Lv  HLhME1HxH`HpP        A      4   L%#`   TJ  ID$ H  HHhLH`H`HhLAƉPIcL1HxH58 Aƅ` I   E+xID$XL`H9     HxfHǅ    )HHpHǅ   HA|$x uHhLL  N   AE,E~D9I   EfD  HǅT   ƅ[+I$   M   I   D  LhPH5 LA   x ڻ   kh[-/D\x1A@ LLB'I   1H5. L?ID$ HHhHLAT$(HhLHNHxH5Y 1L? [L1H5 ?5   L ifD  HLxMLHpHH`1ƅhZ       4   L3 h F  T  IG HL  HxH`LH`HxLhMHchH5S 1LL>ƅh +DI   DIGXLxH9     HpfHǅ    )LHǅ   HAx uHxLPL  gPu%AE,Dr9I   DhD  LLP@PuI   <1H5+ L=IG HHxH`LAW(H`HxLrLLL1H5
 ^=f     LxZD  [L1H5R =      ǅT   ƅ[-+	D  UHAWAVAUATSH  dH%(   H]H   L  AD$   HLXIǅ    Hpf  fHpH*    )h1Hǅ    HHǅ   HcHH)  L  ICIKH9c  LxHIL`HxA   HLE1@ AE,D9fHxE1HߋHSHHHHH)HHt81H) EHHH)tE1HCXAHXI9{HL`H  @ ;  E  IL  L9{  HLxLh HA   HALaLpI9      f     E1HLHAVHH H荏HIRaHII9tHPLYHIcHH)HtjE1IFXLpI9tZA~x uL   EZHH1H ΒHHH)(     HH HH;xt2HH1HG zHHH)Lh1Lރ 8   LAU$HpLtaHX9X }   I   fHL;hHHD LI HLL@1贑LHcHH)4HEdH+%(   u0HĈ  [A\A]A^A_]H  @ ;lfff.     UHAWAVAUATSHx  dL,%(   LmL   I  P Hh,  HHǅ|    Hp@ HpfHǅ    Hǅ   HLǅ    )At   tHC z y  H  HH9  LpE1   f.     C,EgD9rHL|LLAVHHHHH)HH   u 1HI% HHH)tqH   EH  IFXLpH9tSA~x uLDLLL99H   H  IFXLpH9u ff.     D|1HDA8   HS$HpH߃^HhD|D9x ~NL   5D  HpHS$ 1   HcHH)oH   JHEdH+%(   uHx  [A\A]A^A_]}fff.     UHATSHH EdH%(   HE1H   D  H  Lc(@H   H  z tHSxL"M   fI*YQ HxdfH*^Zf   u
/E   HFHtrH
FHHn1HUdH+%(      H [A\]HfHH	H*XD  LAfHL	H*XPH1HH     fD    Hl UHAVAUATSH D   dH%(   HE1E   H_IIH         A$   I|$ExUEH   HID$1f  H   M   fID$Itu   t1   t(    )L9\  1I)f  A$   H1EEHHHufff.     HEdH+%(   V  H [A\A]A^]H   HX0H_   )fD       t     ff.     MA$   ] ff.     H踇HH\H  Lp(<|H   H z tHSxL2M   fI*YM H|   fH*^Zf   u/EwMI\$I     8IՀ   (  HL9  1N,0f   HfHH	H*XofLAfHL	H*X4fL    I|$6H.HHx  A$   mTfI*Y7 H   fH*^Zf   u
/E   HHH   H  Lk(zHthHa z tHSxL*M{LAfHL	H*XY HjHfHH	H*XUffR    1   1I\$f  MI݄F  HL9FDf  I\$        f  ID$1f  rfUHAWAVAUATSH   H$ H   _$<DII`DAdH%(   HE1LA$0  fHǅ    I$  H@  8tI$   M   I   A$4   uLA$6  ƅg etA$5  <e-ggH@ A"$$    1DL1f tA   p  4   L`H5 LHHD,@DD)oVI$  H  HBHH9q  Lhf   HX1ILxLƅpHhHP   @ gH5 L1-XIE HxHH  HXLHXHxLp<HcpH5# 1LLo-+ƅp B#DXIEXH9P  LhHxL  HhfHǅ    )LHǅ   HA}x uL=  AG,Ds9<  A      4   Lp XH5 L1,D  HX1ILxLƅpHhHP   fD  g1H5h L0,XIE H/  HHxLHXHXHxLp:HcpH5{ 1LL++ƅp B#DXIEXH9P  LhHxL  HhfHǅ    )LHǅ   HA}x uLe  AG,Ds9  4   L?p 1H5 LX*IE HHHxLHpAU(HpHxL9LL1H5O *fD  IEXDH9P@@ ALxXp u 8HHLDl@DD)WRAG,D9   HfHǅ    HxHH)Hǅ   Hf tA      4   L
I$  HH9}   LjLp tNgH5 L1L)IE LLLH  )IEXI9$  tLhHH   LWQD  A   HHL ڻ   /QD<A$$  Ae t  HEdH+%(   '  He؉[A\A]A^A_]D  LLu+c     HpLAU(HpHxL7LL1H5" v(D     AU(Hx)NXH5 LH1:(HK  Hxff.     PH uf.     5   L	%fD  LL}*H@15   LE1`H5 LHHD,@DD)OI$  H  HBHLhH9(
5   LcmfD  fE9w(4HfALH@`Hǅ    LLLHHмPXZƅpE1xJf.     UHAWAVAUATSHhdH%(   H]H      LcM!  H   fHx   E       @ L 	   /wSD}AA}    A$	  LH,AC(D}D9   E$  E6  fD  L1IH   fA$   u~L-' Mt$A}  _I$  M|$(5oH  A} tIT$xL:M   fI*YK HxnfH*^Z     AƄ$   RfLHEC(;E5HEdH+%(     EHh[A\A]A^A_]HfHH	H*XD  LAfHL	H*XFuHD{$E$	  uH   Au  JMQ  1H4   HzGlm H5 HDE)PLH   D}L  IGIOHMH9  LxE1K1H   LAWAH51 H߃AAKD)uE1IGXH9Et@H   LxAx uLHuHuurC,A9}IGXAH9Eu EH5 HD<@DKDuC,E)A9      H5 HA DVKED  L%uM    Hxf1H 興    5   Hf     f    L            H}f   Z   p<HHUDhH5 1"E)    Hᖉ H߀x tJsLcMfD  H   fL`0   LcMt%H   HxE1|E    ff.     UHAUATSHHL H   dH%(   H]H   z tD   Hx0E18       t   t
  AH1   HHuIcH   C,HUdH+%(   usH[A\A]]D  Hxx tD   uD  H    uH    uۋx  yH    uf.zuz u    uDhH%`UfHATE1SHH   dH%(   H]HHǇ       Hx0   .z<u:H z u-H@PH   :    H1I   HjHufInfl   H=H      H߃fC$HEdH+%(   uHH[A\]bx     UHSHH(dH%(   HMHH   H  P8u@<teHIHt\H~x ttH   HxS1   xeH   HxxHEHEH@x    (H   '(HoHEdH+%(      H]1@ H5U y!    u[H= 1HMLHMH   HHU"HU1   HBxdH   H   Hpxǎ_fQH=N 1HMkLHMD  HHMHMHH   H  P8XfUHSHdH%(   HUHH   H  H4tXB0xQx  HxbH   Hx  WRH   1   ǀx  cH   NHHEdH+%(   u@H]1    x        cH   H   Hx  虍fUHAVSHHdH<%(   H}HH   H  @0tuHtpH    t~H   H~Q1   "cH   Hǀ       k&H   <HEdH+%(      HH[A^]@ HEdH+%(   unH[A^]Lw H5 uI   1H= gJ      H   L   zbH   H   H   pPfD  UHAWIAVIAUATISHH   dL,%(   LmMH  HLD Ha H1   LO}  HLcLk(HCǅ8   ǅ<   H H8H   H5 DH   M   IFHD|   H0L@I  ƅD ǅ@ in -   PpH HcHcfA   H   H)I  LM   L
MH` HH01   J|xHLc@HCH8Lk`<I  HC8HEdH+%(      <HĨ   [A\A]A^A_]ÐMtIM-L H	 v@ 1H    LH {dff.     ǅ8   ǅ<    g    MtIM-MH      H01LH,    C{aUH`HAWAVAUATS1HhdH%(   HE1;Ht\AHHCHSH9t6    ff.     ff.     @x HH AH9uyy u7H/*HHuDHEdH+%(     Hh[A\A]A^A_]H{ :HtII1EIEIUH9t"f.     @x HH H9uyy u(L)IHuALG$/bf     I} :HtLxID}A1ID$IT$H9t(D  ff.     @x HH H9uyy u(L0)IHuALxD}\@ I|$ 9HtLeE1D}M]HHCHSH9t)D  ff.     @x HH AH9uyy u'H(HHu]MLeD}DYH{ 9IHtL}E1DmIFIVH9t0ff.     ff.     @x HH AH9uyy u'L/(IHuDmL}E`    I~ 8HtDeE1HHBHJH9t4D  ff.     ff.     @x HH AH9u~y uH'HHuDeEd Hz HU8HUHtDmE1HUH]HHCHSH9t,     ff.     @x HH AH9u~y u'H/'HHuDmH]HUE\ H{ 7HtH]E1HHCHSH9t4D  ff.     ff.     @x HH AH9u~y uH&HHuH]Ed H{ 7IHtE1I@IPH9t     @x HH AH9uyy uLO&IHuEfIxLpLpA@ ff.     UH`HAWAVAUATS1HxudH%(   HE1r6HtXAHHCHKH9t2} utf     ff.     @x PyAH H9uu`H%HHuDHEdH+%(     Hx[A\A]A^A_]fD  ff.     PyAPxH H9u H{ 5HtDlDuII1IEIMH9t1EuUf.     ff.     @x PyH H9uuAL$IHuDlALE@ PyPxH H9u@ I} 5HtLpIĉx1ID$IL$H9t0EuTf     ff.     @x PyH H9uuAL1$IHuA܋xLpD8PyPxH H9u@ I|$ ~4HtL}E1Le|HHCHKH9t0EuS     ff.     @x PyAH H9uu@H#HHu|L}LeD9fPyAPxH H9u H{ 3IHtH]E1DmIGIOH9t7EuZ@ ff.     ff.     @x PyAH H9uu@L"IHuDmH]E@     PyAPxH H9u I ?3HtDe1MHHBHrH9t8Eu\fD  ff.     ff.     @x HyH H9uuAHQ"HHuMDeABf.     HyHxH H9u@ Hz HU2HUHtLeE1HU]HHCHsH9t,EuO@ ff.     @x PyAH H9uu@H!HHu]LeHUD<D  PyAPxH H9u H{ 1HtH]E1HHCHSH9   E   ff.     ff.     @x HyAH H9u   H{ 1IH   E1I@IPH9t;f     ff.     ff.     @x HyAH H9u   L IHuEH HH-H]EfD  ff.     HyAHxH H9uu)HQ HHH]Ef     H{ E10IHtI@IHH9t6f     ff.     ff.     PyAPxH H9uuALIHuE Ix1L`L`A    Ix   L`sL`A"fUfHAWAVAUATSHHH}udH%(   HE1H      H@0HEHq  fD  H]   LsHLugHE   uL貶  UE1!  b     G  H  E1H/IH  ff.     IGIWH9   E1}        ff.     @x pyAH H9u@   I E1.IH   IAIqH9tM     ff.     ff.     @x xyAH H9u@tIy1LMLMALIHuE9fD  ff.     ff.     pyA@pxH H9u@  ELIH1} DDfD  H  Lc(VH1  Hڀ z tHSxL"M  fI*Y+ H   fH*^Zf   u?HE   /w.	   tu} [     t}  H]H   H} H]H   HEdH+%(     H}HH[A\A]A^A_]Nf     H      u}   ƃ   @ HfHH	H*Xf.     LAfHL	H*XI E1,IHUIAIyH9t=ff.     pyA@pxH H9u@tIy   LMLMALIHuEfD  L0  MY  E1\ fH*Y_ H   fH*^ZfA   uHE/   ALIHIO(I  HMSH   H5{~ HM~ tIOxH	HiH΃fHH	H*XY HYHfHH	H*XDf     H      H}( HEH      ƃ  f  s f    fE1f.     UHAVSHdH%(   H]HH~ H   H  @0tVHtQH    tiH   H=1   NH   Hǀ       H   (HHEdH+%(   uxH1[A^]     Lw WH5 uI   1H=t 6      H   L   *NH   H   H    xefD  UH`HAWE1AVAUATSHXdH%(   HE1D)H_  IIFIVH97  Axy a  xx   -   H H9uۀ-	  I~ (H  E1HHCHSH9  Axy   xx   -   H H9uۀ-  H{ (H  LuE1DmH]HHCHSH9-  Axy   xx   -   H H9uۀ-  H{ 6(IH  D}E1IEIUH9  Axy |  xx   -   H H9uۀ-  I} 'Hr  DuILmDeE1IGIOH9  Axy )  xx   -   H H9u@-   I w'IH   H]E1IFIVH9   Axy   xx    -   H H9uۀ-uyI~  'HtkDeHE1HCHKH9t4Axy   xx t -   H H9u@-uH{dAĐH8HHuEDef     LIH8H]ED  LIHDuLmEDefff.     LIH)D}ED  HHHDmLuH]Efff.     HxHHEf     LXIHHEdH+%(   uHXD[A\A]A^A_]     fD      fD      >fD      fD      fD      (fD      cif     UHAWAVAUATSHHdH%(   HE1%H  IE1ff.     HQs @   txIGIWH9t&1f     HH H9uyx    ALIHuHEdH+%(     HHD[A\A]A^A_]Àxx   fD  Af.     IGIOH9I  xy uQH H9tWH    H9tH H9uIGIOH9tff.     H H9uAHD  xx tH H9u    I #HL}E1]HHCHSH90  Axy J  xx   -   H H9uۀ-  H{ y#IH  DuE1IEIUH9  Axy   xx   -   H H9uۀ-  I} #Hu  D}ILmDeE1IFINH9"  Axy   xx 
  -   H H9u@-   I~ "IH   H]E1IGIWH9   Axy `  xx    -   H H9uۀ-u|I c"HtnDeHE1HCHKH9t7Axy !  xx t#-   H H9u@-uH{A@ HxHHuEDef     LXIH5H]ED  L8IHD}LmEDefff.     LIH&DuED  HHH]L}DD      fD      fD      YfD      fD      E1aIGIO1H9xy iH    H9 ff.     UHAVAUATSHdH%(   HE1$   5  A   7      HH  E1H   I   H  Ls(HH+  HDs z tHSxL2M  fI*Y Ht  fH*^Zf   uA/   AHUHHuHEdH+%(     HD[A\A]A^]fD  Hs   LAĐff.     HHHtH  Ls(GH7  H`r z tHSxL2M   fI*Y HxTfH*^Zf   uA/   {A   JHbHHfHfHH	H*XD  LAfHL	H*X`HfHH	H*XwfLAfHL	H*X<HEdH+%(   u:HH0  [A\A]A^]f     f    f2fUHATSH H   dH%(   H]H   H  H  H   IH9  Pa[  p`4   uHԤ2  A)$   2  $   I  I)$   Hrp x    1ɀ5      $   MY  1HL|MH52p f2  ~ t)A$   2  $   *  f!     ƃ7     f2  \       HL5   `Ho x t2  )A)$   7      1f2  1A$   2  $   tCI$      HEdH+%(   uH [A\]@ 1@ I)$    I$   fD  6  t5  Lƃ7   f@ H0  M@ Mff.     UHAVATSHxdH%(   H]HZH	  HC H   g     IHJIIIHtrHcn PHH)H8    H-1H5 L   LU![   LUAoAD$IBID$(HID$   pfD  HH}A   1Hx@      L AS@   L]H}LEH}11Ҿ   fZLxHYu(IB    1HUdH+%(   ukHe[A\A^]@    HLUHEHMLUHt%H{ HLUHM
<HMLUIJHLULU|/@ ff.     UHATSH H   dH%(   H]H   Hz  Hq  H   IH9  xa T  p`4   uH 2  A)$   2  $   ?  I)$   H`l x    1ɀ5      $   MO  1HLjMH5 l f2  ~ t)A$   2  $      f     ƃ7     f2  ZD     HL5   bHk x t2  )A)$   7      1f2  1A$   2  $   t;I$   HEdH+%(   u|H 1[A\]f     I)$    I$   fD  6   t5  X ƃ7   n@ H0  M@ U UHAWAVIAUE1ATSHH   H   dL$%(   LeAHtDhH   HH(HC   H   Ht   H H1LHj HH $(  Eu7L5 DHվAăe=B  @"w,IcL>fAeAB  AD$":  fHXHEdH+%(     HeD[A\A]A^A_] H   Hp5   cH[VfD     S(   $  H   H  @ ȈC.)HfC(f+Sf9)BHH)H    HfD  Lc5y H   A$  A$  DFHJH   Dx WH= P1s3DK(DC.!H k 1HnYf     t#+H:2  D  H   H   HH
  HxH      Hxx    fHx0.z4  E1fH1I   HrHufInfl   HEH߉{ t8HHH 	  9T
  tT
     H1H :H   Ht   H HH Hf     C.C. fC(D  H     H    x  H    f.    Hf Qy   Hx0H@PH   @ H HcH>H   HP5   CHB6D  A  A+tHA+   Yf     Hȋ;v Hpe A  H Hp v       H81蛼H      C(     H   HH  R S.)Љf+SfC(f9])BHH)HE   HO3Lc15ku H   A$  A$  DFHJH   D=u WH= P1s3DK(DC.NH 1H    !Hx0H   L   H  HxH      Hxx    fHx0.z  E1"f     H1I"   HHufInfl   HH߉ t1IH 	  9T
  tT
     H1H6 H   Ht   H HH HuS.C. fC(H    H     x   H    f.z@u>HTc Qy tHx0H@PH       uۄHx0AQ57s LdHib A  H Hi s       H81蔹H   $ӺHb RHb RM UHH-H5֋H=HHdH%(   HEH^ HP H	H   HH@  H5]H  H=H`  H1H  HӉH  H5uH  H=Hp  HH   H  H 	  H	  HEdH+%(   uxù U1HH~ dH%(   HE1HTH   fHnHqƇ   HGpHOa flGXP   tH  J O.x teL  DO*I@II9t#HHAA@ fG*HQXAHJI9uAfDO*HEdH+%(   uKH     H  HH9tG*HJfD  fG*HQXHJH9  u衸UHSH(dH%(   H]H   HtHHHEHEHUdH+%(   uH]G    UHHdH%(   HE1HEdH+%(   u@4ff.     UHAWAVAUATSH   H$ H   H$ H  HXH  LMΉTHHPLxLHdL$%(   LeDeH0IǸM}  H?HI   M   I   ǅǅ    t	CF111   (fI   ."    A   Hx0.zuH^ z   1 H1HRA   H!HufHnflA      葯I   HQ  HH.1   H HHp   HHH^ H   HtS>Hx tH IGPAMHǅ(    HH     1AE1E1ǅ    HLI   HtI   L   D  Laz     Hw   H5K HcH>f     =      TXMI   L聮Lf.     LITI9uHUdH+%(     He[A\A]A^A_]    A   Hx0LxM   ff.     H L)H HfD  H9\ z   HX     H\ 0;H  UH  HX   9  ǅM     Hx H5! H: LHDf     =  ts=    =  HXH@  DP,E  I   Hh  H[] 9a  H  H   HHH`AHIcI   HhHHpHtyH(  HtmHxX tfHH8Hp1H    D`GD`x6IcHAHk8HHIcHhHHpI   H  P8uH<   M   Hf H~x HS HEL A}!   D`  EMHpH 1   FD`x>IcHAHk8HHLIcHhHHpI   H  DX0E   M   LD`D`L7 uID$ L   I   Ho HpH    D`H    H? HE1FD`x>IcH|AHk8HHLIcHhHHpI   I   H  H   H   H9  xa    HHxA      D`
D`II   I   H  H  H   H9  @`HR HT HDHp1H    D`DD`x6IcHAHk8HHIcHhHHpI   I   H  H   DI0L@E   M   Hp1H    D`L@VDD`L@x>IcHAHk8HHLIcHhHHpI   H  y4   E   x  H EH HpH D`   HI1CD`x>IcHAHk8HHDIcHhHHpHx   Hp1H    Dh.CDhxIcH)zAHk8HLhED`LLp0     D9  HLHk8H4uHLDuD  HLL6Hx N  H=O 1 Hx HLHǅ    Hǅ    脃oI   H_H H8LHh  @HT p0I   @  P H5p L/L@H LH5X H= D 1@ H0LDHXLP  舷L{HxHkH@  [HHHx IHXH襻0LLLHXH@  DH,E  I   HL`MIL$ Hg  HHH^  HbS rHH)H:   LH@HHLA|HN H= 4)օ1A   1ZEI   DH  Db4E#EDx  Hx  E  I   I   1   ǀx  $I   ~L6A   L A   HA       [  @   L1Hw }61L#tH5	 L@FHhH
  A   I~A   ppH~LIH'  L`H LfD  HQ I_x {  H`fA	  Hǅ    Hǅ    HhL ~    H@1)I    TR@H2 A      ptA  <p-HhI  L  IMIHyI9Q	  H8HHQHHLHH8HH)HHHI9   L8LhI@ ff.     HHH 14LHHHHH)AU(HHHHH)HHIEXLhI9uL8@H L| 14HHHHH)HHI  HLhH9tmf     H 13LHHHHH)AU(HHHHH)HHIEXLhI9  uL`L/1L   HhHH A   tp   A   L1p莸pH^IHH LHh蘫LH= 1Hr H@H5 H= D, EHH@Hff/wf/ 
  H DL   ٬D@ H HHfD  H@PI   eMgI$`  HI$`       AGH HD  HHǅh    Hp`f.     fo L@)@fo )Pfo )`L`H`fHǅ    Hǅ    H)fA   t>HL x t1A     A     ƅ@--     @ I   ƅ@ H  LL9  M`A   [ LHLLAT$(LLH߉E1HHH)I   H  ID$XL`H9   A|$x uI  LHpҤu>EuHHHu 10HHH)P     HpLuI   H  ID$XL`H9mfff.     H`Hh1H2E    @-iHhf1HH)LLoHHl   L)P越A]XfD  H= 1:%D  I    t)HXH@  P8t	M  @,  Hkh8E11LHpD`H跹D`AI   McH  HJ<HpH      1Hv Hz    L`Dh7DhL`x8Mk8HzHAJBǄ    McJHpI   H  H      Hp1H H    L`Dhk6DhL`x8Mk8HNzAJHBǄ   McJHpI   H   H    tyHp1H_ HP    L`Dh5DhL`x8Mk8HyAJBǄ   McHJHpI    1Hp1H    DhL`X5DhLk`8H*HAJIcHHp@ HpH    14D`f.     LpLhD`8Hx@    H# Hƅ@     HhHU    1YI   H  LL9HH|LD@H`ўD@H`II   H  P8Hhf1HA	  H)LHHhLkkL)P舆XZDx        ;I   I   Hx  1BI   LyHI   H   H9'  HPxH9Hx  H9H  DB4E~px  _x  M    H L4 1Ƥ1H   H  H(H  H(HHHH HHHcH(HhIHHpHPH9PP  HhHHH`HP@D`H߃8HD`AH( kHE1Hǅh    HpI   L@MZHkh8Hp1LD`HD`HAIcHhHHpƅ@++   HpLE1LHkh8D`H豳D`HAHXIcHhHH@  HpHL9tHDJ   1AQ      L@L˝ LSAZA[HE1Hǅh    Hp6   H1ɺ   D`D`LH`HhHS= 1   >H 5I   pLg0upf(^ H  fH*Yf/ ?  H,HpHR> Hh`@ZA   f     LxIH  M}A   tE1Aƅ   fE  A   tHfA   t=HB x t0H= x@  H= HpI8  I  Q    LAƅ   LIYvAƅ   A   t\A      I  HHt:D  HCHSH9t @x HH H9uyy u+H3HHuE1fE  A   fH{ IHtIGIWH9t f@x HH H9uyy t	I"LIHuM0  Mt@ I  dLIHudLHhЫ[HRHC 8  H  H(H+L`HMLh`H1LLA   @      AUL @   LpLp11L   8_AXIHL     HH.  I|$ LH(LH@HHH!@ x    IE(H  fH*Y`f/a    H,HprI   \6 H,H?HpHE1Hǅh    Hp5  GHfHH	H*XF\ͭ H,H?HpIExH (H-H L4 1hL   H1LLA   @      AULՎ @   Lp7Lp11Ҿ   LY^IHtn   HHHtTI|$ LfI   LH@KHfHH	H*X`ǅMJL'I   Hǅ    H@HuLH(Hǅ    H@HHK10H@   8^LH=& H1*D  U(IHAWAVIAUIATSH   HDdH%(   H]ȋ_  l  He= x t>II9  1fD  ff.     1H9   H I9uA  1   H ~: HHnL8fHnH,aLXflfHn؉U)E~; fl    H= LM)EMM>M9t5fLHDHH9   fDM?M9uHXHM   1H EuH5 H 6  DH           I}AU } u} t tH!    H 1螚E     M?M92    1H/ H5 H |  1H 6M       %    } u} t tHp    H 1E    HGxHx	{    HI>1M(PH_AXHUdH+%(   0  He[A\A]A^A_]fD  =  W=     qt<1DH 2/D  =  =  "  q	  q   @ H 辦[ H5Ί H M   fD  LUMD M։HLUI}AU HM   LPHLMEH5 H 'XZ	f     q=     MvL;gMv^fLuMHL藯E1H   LPLMEHH5, H AtY^A	     Aq_A   MvL;tMvk11I     D ||ff.        fD  11H f     H5Έ H M |M6L;M6A}6AFDD xM6L;M6AD萏UHAUATISHhEdL,%(   LmIHE    jH  L   HEHkhH   L      111    f1H}LHE    )E)E)E՗%  fff.     1ɺ   H5 HBt}S?   R   uDHH}
1HUdH+%(      Hh[A\A]]f     atKqtH̇ 1҉HnfD  Hu1H H   H= AH   H0Hx %HPHuHHUH@HEb@ H5 H@ Hq7 @     H5A r腍D  UHATSHHdL$%(   LeIׯfHHg   AT$*уtwHIL$H   PML$ 1H5 An   S$D )XYHEdH+%(   u4He[A\]    HEdH+%(   uHeIt$-H[A\]$蟌@ ff.     UH   HAVAUH ATSH  ~{1 dH%(   HE1HHB HHx0HfHnH2 H8flH)H  L%A/ HE1ff.     HG A$I9LB苅~GHHuι      1MH   LŁ A$H0 H H$` H HOHH@ H   12_  1H AŃ/td"t)t$11H D qt=  uH xHEdH+%(     H  D[A\A]A^]fA$~E1H HH5 H=d $s0u!H2 H<xtbHH.Ht0H0fn@fl) D  L%q- E1kHH= 1T1H   ,HHMAۉf.     UHAWAVIH5 AUIATSHdH%(   H]HӺ   D|   AHcC?pHI}L<IHcCHH<    H< tGH{1LC LH    	x%CHEdH+%(   uHD[A\A]A^A_]A UHATSHHdL$%(   LeI F uEID$uY               HEdH+%(      H[A\]H -F +metGric HID$tHfoB Hn --xed HTID$   HgH -F +ireHDegs ID$\H;H -F +ureHDegs ID$   9HHH -F +phyHHys_addr HC赇D  UHH HATSH   HL%* dH%(   HE1A4$;HëxWH5Y    1H* H8-111   HEdH+%(   u*H[A\]@ A4$HH 11qf.     UHAWAVAUATSH   H$ H   H$ H      dL4%(   LuE1H@IHL@HfHnHfInH`   fl)LHH$fo$   H HHHLH `  H8ƅ ) HxH>
  H	  HsH@HHc0H HL5- H L\Z    HH Hc0L?Z A~! LEHH(SH8H<H 15Y^0x	0H HH6 LY L    HH+ A~! LEHHc0H(SH8H<H3 1A[A_0x	0H HH LgY L    HH~ A~! LEHHc0H(SH8H<H~ 1?AYAZx0H H=}Hc0H H LX LX    HH%~ A~! LEHH(\Hc0SH8H<H'~ 1_D0AXxAD0A?z  AGÃ'  @   H   ~xD)fAnfHnIc׉H   fo Hfp LfnflfH1flfp f     fofffofrffrfofofrfbfjfffDfDH H9u@   DHxHcD)RHcHH@HH@H?tWHcD)RHcHH@HH@P>t'HcD)@HHH@HH@H% fH Hǅ   B111HpHHHPHH=   LLp1      L.|    LL   L1,$1LH
| H$ 01;  袵IH  @   L@ǅ    D)IcHhfff.     L(Hp  Lhx ;  A} .uA} tA} .uA}.uA} tH5o{ L/Hu   LGtHHH  D  H
H  PtX  HHHH5z Hu9  LcLhM1J@LHz    HpLH.   HLHNHN H)I8LHp1KL  1HHBz IH11H5 zwHHLLff.     HH    
H#  HcIƀ#tL@tLfD  H5y L1H~   HxH5|y HIt_MLM LHc      1H(  L L9u<@ M$$L;(  t+LLtA> jLfD  HLLLHHH٥\HLL貂6L蘥LHLL@H(DEH1D=Å  9\L  D9  HxbE   D9A11     I<HcA9;  Hq  HQ H5v HH HHDHDMLDE   PHw M1VL`   HPdZY   H~H1HUdH+%(     He[A\A]A^A_]HҰ-H H H  M   H5/v H,v THH@6E1HP HH5[ H=v WtRHxE1E; HH`   H@JDLHH`1LHMv       L-O !={¥貥HʗEMtHO HL-O LLf.     fU    HAVAUATSHL.dH%(   H]HfE*LAAHHELs8HMI9LC4S$HLHEdH+%(   uH[A\A]A^]Kzff.     UHAVAUHHATSH   dL$%(   LeIH@   HHLH1~L@LfD  HxӾ
   SHuHc   IH   HMe Mu~P fHnfl)0fD  L`  IMf
   LHuHP   fo0HMt HHr  ]HPH5Dt HLhHE1)Ux<@ 1Hu=     a?t{   t	   HHLH@HEdH+%(      Hİ   1[A\A]A^]    =  uHE
w    =  uGH5B HUD  HEHPH	HGHE7    htqRH{ 1҉H
xD  UHAVSHHdL4%(   LuIH5s tHEdH+%(   u8H1[A^]@ HEdH+%(   uHLHH= [A^]קwfUHHdH%(   HE1HEdH+%(   u1H=LwBwfUHAWAVIAUATSHh     HHdH<%(   H}H   HHcHHxH   HX  MHpIE1HAD  AIIE9   I<$@   HEL$1LED$H   Hq yHEt;IcIHHTH\AGHH)ID  HHdI9uLH$@ ff.     HUdH+%(     He[A\A]A^A_]fD  H1Lp}HHcHxIL$D  LIԪM9uLHh;\LHL@   LL IHI<$H+=2 H=& I<$HcЍpƄ@,Hc   H)LYI<$@   LHHHHuH ED$@!E       8  H1I HH    HKg    1HAT$Lz L
  ED$Lwo E   Hg 1       HLLLAD$LHLL  H5o \f   n    HEH HHL0H MMED$EHHH HH HH Lfm HH HHDLDHHn AVASRHy SARAQI1QV   AUHH`HH1       A  H[G HHl H
D  tq   H'G HHyl HH1H*HHcHl HHF HHrl HHl HHQl HHF HaH0l HHk H,Hl HHNF HHk HHk HHk HHlk HHk HHE HLE "qH5E fD  UHHdH%(   HE1K)    HEdH+%(   upD  UHATSHH dL$%(   LeL%( uY    
8u;L   xtHEdH+%(   uH   [A\]f     k
8u ;L,ztD  K
8u;   H5k cHtHEdH+%(   uH   [A\]lo    UHHdH%(   HE1@u
( tFH=W (     `l{FHEdH+%(   u(H=( zf.     HEdH+%(   uZof.     UHATASH   dH%(   HE1tX=}'  LP   Hh   Hǅ`   LPHHHǅX    IcHP9f     E1="'     Hh   E1Hǅ`   HH11H`   k!     E1Ƀ8AAHEdH+%(      Hİ   D[A\]D  LHHh& 6   H5
1   HHEHǅ`   LHM     軕AhH   1HH1fo LPH`   Hǅ`   )PhDH   xAARmfUHH dH<%(   H}͐8讱   11t      ͎E      H=ph H5     蠛H5     菛H5x     ~H5g     mH5V     \H5   KH5   :H=k ΄y?:MHEdH+%(   u&ɉ@ HY Hg 101臱Mkfff.     UHHdH%(   HE1@tH 8 ud   zH=[ u*uHEdH+%(   uWH= Yrf     KH= j     H5 1H_ H=f Dc{:kf.     UHSHdH%(   H]1ͥH5f p18     UHSH  dH%(   H]1芥H5of \pH=ff     HHHcHF H8p1f.     D  UHATSHHdL$%(   LeIǌH4~HEdH+%(   uS$I4$HH[A\]jfff.     UA   HATIHp SH`H   ~ dH%(   HE1HHDHxH`fHnH H5 DEflHE1)E\   M   1H`fq   "t+      A$De=  ty=  uD`H`}HEdH+%(   u`HĐ   D[A\]Ð=  t9=  tf1H`eqtۃttuܐff.     AAhff.     UHAWAVAUIATE1S<   HXH}HuHUHMdL4%(   LuEfD  HL)9Lڀ8 t'ALh
   LSHuLF9LL- LdAt$	K1H uM AAAǉAA)HI  )U{EUDHƉMMEpuH} tDH}qfuAUH}AwAL$A   AWCD<ED`DxuDAH== E9uD}uK   DuARH}貲LDAǃ;  2  DeEH/ 1HMADeD`O    }A4    BLj1   DAǃtat\AtVLbAtHE}HcA4D<~D6@ LDAǃu     SHMHcH}HcH sHEdH+%(   uIHXD[A\A]A^A_]fHMH=k A   HMvHM2   륺   1H vefD  UHAWAVAUIATE1S1H8H}HudL<%(   L}I%f     HL)9LAT$8 t+LhAԾ
   L7HuL*AT$9LAD$KAEM  Hi 1M DD)H-	 U AAAŉAA)ZM}DDEuuH} t}AuH}YcDmDADM   DeH}ADA   DD.C|,DqH=& C|,DVHEdH+%(   ugH8L[A\A]A^A_]    UAD  HEdH+%(   u)H}H8AD[DA\DA   A]A^A_]鐓{cff.     UHSHH(HudH<%(   H}H=
 `Hu1H HEdH+%(   uH=
 H]cff.     UHATSHH HuH=
 HUdL$%(   LeA_HUHuHz腮H=V
 HEdH+%(   uH D[A\]JbD  UHHATSHH}HHdL$%(   LeI   j~FHuH=^ 1HV -ZH}RHUdH+%(   uXH[A\]     LQ	 H] H 1   I8`HL   L"	    I8yafD  UHHATSHH}HHdL$%(   LeI   ~FHuH=A] 1HU ]YH}HUdH+%(   uXH[A\]     L H\ H 1   I8_HL   LR    I8x`fD  UHHdH%(   HE1HEdH+%(   uHHU 1H=\ X`     UHHdH%(   HE1HEdH+%(   uH11H9\ RXM`f.      UHHdH%(   HE1HEdH+%(   u`@ ff.     UHATSHHH= dL$%(   LeI\Hc=    HH)H= L豹H H { u H<
t'H=( {HEdH+%(   u%H[A\]ÐH}#)     B_fU1HSHH dH%(   H]H8p1نH Hߋ0êHEdH+%(   uH= HH]   k^fD  UHHH= dH%(   HEHy HHEdH+%(   uH= |u^D  U   HHH dH%(   HEHG 
HcH9r1HHfHnflGHEdH+%(   u^@ ff.     UHSHdH%(   HEH  ~y1tH=s ZHW 1XzH# 1A       mZXHEdH+%(   u.H= H]h     HEdH+%(   uH]F]fD  UHAWAVAUATSH   dH%(   HEHD     HH     (   L/1sH= YHm  1Dp艄   1DL%( A$   DDxL[A$A    D      HAY5   'A$1DA       HHCHs    	YH= HEdH+%(      H   [A\A]A^A_] L HW   L`LL]L@HS    LL]Hd   1LLHW H`v[fD  UHT HHdH%(   HEH HHEdH+%(   u0[f.     f.     f.     f.          UHSHdH%(   H]HX   HtH` HH@9;HP0HUdH+%(   uH]ZD  UE1   HAUATHMSHHXH(dL$%(   LeIt+E1HM   LH   uDL-] 
 L-  LLHsHEdH+%(   uH(L[A\A]]fD  E1YfD  UHATSHdL$%(   LeI   H   HH{    HI$H5!` H{XHC0;+  fC9HHCH uLH      H5!` u HHUdH+%(   u5H[A\]D  H{XW    HXC 1Y@ UE1   HAUATHMIHǘ   SH(dH%(   H]Hdu8L- LHLHEdH+%(   uhH(L[A\A]]fD  E1I|$XHMH޺   t+H5. HL-J݈ uL-      L- {?X@ ff.     UHATSHH>dH%(   H]H,   4H     H;IHC8A$,H{8    ILHCH   LHu   H}HC L9tr<   IHt`Hx>   HEHtI  LA$ 艦HCA$<HE >H{ t"1HUdH+%(   u*H[A\]     H{臌H{8~WfUHATSHdL$%(   LeI   H   HHR    HI$H5R H{XHC0/+  fC9HHCH@uLH      H5y] $u HHUdH+%(   u5H[A\]D  H{Xw    Hxc 14V@ UHAWAVIAUATSHD&dH%(   H]HAb   H5R H+  L% H5
R HH5Q HAAEtH5Q H   E   L% LHLΡHEdH+%(   q  HL[A\A]A^A_]f     {tt*AbF{f<{ I-    { 3@ H5KQ HA]EtM_hfD  L%I H@ H5P HH5P HH5P HH5P HH5P HzH5P HcAbu{ru
{ MH5YP Ha6H5
 HE1G#SD  UHSHdH%(   H]HX   Ht HP H5HH@9/HP0HpHHUdH+%(   uH]Sf.     UHAVIAUATSHD.dH%(   H]HAbu
{l   H5O Hwu;L% LHLnHEdH+%(      HL[A\A]A^] ;btcAbtu   H51O HtK   H5O Hqt3E1     L%׈ { sTf.     { uL%׈ RfD  {eu{qtAbu{nu{etfD  AbY{lt AbI{g?{et4{ttR UfHAWAVAUATSHHhHpHBLjdL$%(   LeIHx)E)E)E)EMt"AU( rAu(9t
BvLmL;#   LLIHpp9<   LHC8HC@L9   H   1   LGHHs LhHEHHxLpH@ A}4 uIu IMIHI)H)H9HuL9	ЈC1I$H8u H}Hu4 uHwH+7؞H;C tr1{1 uHEL)HC(   C0H}HEdH+%(   uIHh1[A\A]A^A_]fD  M1I~   _H    HEHC1PUHAWIAVAUATISHhH>#   dL,%(   LmI(H@  HxHx   I]Hx<   ID$ Aw:Lp@   >   LIH     L語ID$A>I|$    Ht S( JK(9t
BvIt$ H胟fHu)E)EH]HE)E)EIE H8Wu!H}Hu4 uHwH+7I;D$ tRH}y1HUdH+%(   uCHh[A\A]A^A_]f     LH     HEID$NUHSHdH%(   H]HX   艃Ht HJ H5HHHpHHP0@9#HUdH+%(   uH]*Nf.     UHAUIATSHdH%(   H]H>bu
{a     H5EJ Hu=L%V LHLHEdH+%(     HL[A\A]]       H5I H4t   H5I Ht   H5I Hw   H5I H[   H5I H?   H5I H#   H5I H   H5jI Hx   H5TI H\   H5>I H@   H5(I H$   H5I H{   H5H H_   H5H Ht8<bu&L%+ 8fD  {l!KE1$L%M 
     UHSHdH%(   H]HX   ɀHt HZH H5vHH@9#HP0HpHHUdH+%(   uH]jKf.     UHAWAVIAUATISH   F@H8HUH>HL   dH%(   H]HˉDǅH    Z  HD4Eh  H[(H3  H-H5G H   L5i L- IEAu E	  DHZG 11ID$(I$(  ff.     ff.     x t  H0H9uH8HPH|H   A>Au HF Ic$  foP4H[IHAfo`AD*AD$    AD(AD     1DH[HPHAt*Zf.     HEdH+%(   ;  He[A\A]A^A_]fD  Ha  xd  xdu  IFuLHǅp    L   H@Lh謖tK/LcmH(KDm HAD+} .  Lc}KDm HA|*	  OTm IKHhC*  <
  <H(LLH8LPLLDLEfoPKDm DMMH4HqE Afo`AD*AD$    AD(ADHb 0H DE0  11脍KDm HHAt*H     s   xu   xb   uL8Hc]H[HAD+} 	  LcuL,[IMA}*  H[DMHE)t$H 0H DE	  4M11HwD 贌H[LHLp*H8H8@*<cH[HE)t Ql  xe  xa  ]LFuL3} LcLcuKDm HLo )po@)Eo@ KvHAD+AD( )E9D  A9$    } LP}L	  Ik0Lo )Po@)`uLuLIHPUKvMHfopAT*UAfoEAAD(AL$Hh AADDHʋE	  H LQA 2PH( HM SLI411XZK<vHLw*fD  uL赒   }    HcEH<@HLdH   HϺ   H5PB H(H(t"DAm_	  yuU	  ylK	  H DMEH B 0HU D0E	  11HcEH@HAD( AD+ H9myoAvAA~D   }   } uLDm蔑lHcEH(H@HAD+   DLctIcH<IHL( t
*I
  A ^  DL)tIcH@HA|*  DLtIcH<@HL( t
*
  }   D9m  ED9  AD9D  E9$    DL蘐"IcH<@HL( 
* w$HPuHHk(0foP1H DEAt$2AH[ fo`AD*AD(ADE: A  QEP4Hj@ 11XZHk(0Lw*} EuL諏Hc]H[HA|( kE;DtA;$  REHL牅()ȉƉ AαHH[HLH8H  < K  L5W L- EDEAAu ;Dk  >  WEH? 1P41ۆAXAYH[HED$Et!MAu H? A>   11褆H[H8HAt*eD  4H=    1g^f11WuLGUtHcH@HLx*   I~UHH(HLHpLHr  HpH5L= W  KDm IHA|*2Ik01AD*AT$AD(AD I#f.     } .<&} AKDm DMMHE|$H 0Ht  J  4H< 11OTm IKs*H3C*} :uLLcmKDm MHAD+IVEHJHI f  t
}k    DEKDm 4H< HAD*ED AD$    AD(H! 0H DE6  11CfD  KDm HE| L^AE*} w<o}  4H];    1σIFH   HPHxHrNIv8HHHDH>HsǅDuLIhPHcEH@HLx*7Dp .4M   1H: "iE+HLA臭HHoBKvDMHDEAoB AD*ADD+j0H El$AD(H 2 9D  K  HHxD 11AQ4A|AXAYI@ IHp\'}Ik0HPIL:H}g       1uL  HcEH@IHA|(   Hk0Ik0Lo Ao@ADH*AL*p At @$AD(AD$uED+H7߈ DMH9 40H 8   11KK|m HLw*fE} jv Hǅp    E  H(H@HAD( $HϺ   H58 H(D H( duyiu
yvkHϺ   H5}8 H(軹H(AHϺ   H5W8 蘹H(HϺ   H588 uH(HϺ   H5 RH(HϺ   H5}: /H(HϺ   H57 H(HϺ   H5: H(oHϺ   H57 ƸH(LHϺ   H57 H(蜸H(xDED;EjH݈ 4HS7 0Hjވ 8   11 HcEE1Hk0El AD(fAD*D  w$HPuH HHk 0DEHk(0Lo Ao@AD*ADH$EAD(DAL$HJ܈ 2H݈ :   AREH@ 1P41\~A[[t@ H   H(@ 1AQ4A.~^_HuHPH.Hk(01foPDEAT$Hۈ Afo`2H݈ AD*AD(ADE: Q  AVEH@ 1P41}A_XD  4AH8? 6  11o}H!ۈ L3    2PHw HT? SLI412}A_XKKDm HAD(    1
}EHL牅8)؉AgH   x<   Hk(0o@Ao@ ADH=AL*Dx4Hk(0H[ڈ DM2E|$AD(Hۈ  D9Dn  ;  APEAQEe   1Q|Hk(0AD( :HcEIH(J  HBLLH8H   LPLpHPL(z  H(pH(H  Ik0E1DMMfoP4H= Afo`AD*E\$AD(ADH2و 0Hڈ 8   11W{Ik0Lw*w"   16{REWAQE鋍4H3    1{A]A^&+84HT3 A؅7  11zDHPHx+p0HoHk(0foPAfo`AD*AD   1z1IFH   HcMH@HP} tQ]D9u]LHH <H HtHcHk0Lx( tx*u@ HH8LPLpL聵  Hk(0AD( 
I~H   HHGHPIՋUL©H8LLLPLpHH8HPpH?H1DMIH< Hk(0foPAfo`AL$4AD*AD(ADHֈ 0HD؈ 8   11xHk(0HPAt*Hk0H8DAT*ED$软REH1    P41xY^D D+(HE1 4  11gxHLHpHcL)7HpH50 Hk(0E1DEH0 4AD*ET$AD(HՈ 0H!׈ 8 J  11wM2   1wEAWP   1w   1woWEH:    P41qwAXAYASE   H: P41Iw[A]apHPHPH6Hk(01DEfoPHԈ Afo`1AT$AD*AD(ADHֈ E} t`MDMt2PH9 11Q4vA^A_   1vPH]9    1Q4rv[A]t\AQHe9 E1P41JvAZA[aHk0H8DLAT*ED$   1vQ   EH9 P41u^_Ik0AD( Ik01ۋ4EH 8 AD*A\$AD(Hhӈ 0HԈ 8    1ue   1yu@ UHHSH(dH%(   HU1҃,u+O(v#HHH5 U߉M1Ht$@ HEdH+%(   /  H]D  H5 H}   HtH5R. HËH   H5- H請   HuH5/ H߈U菋   HqH5- Hr   HTH5 HU   H7H5I/ H8   HH5), HH HtH5- HHtH5- HHD     Y.f     UHAVIHSH dH%(   H]HH5 菊1Ht(HEdH+%(     H [A^]f.     AN,vϺ   H5t, H߉M耬   tDMAcu
{m   G  Aau
{d   Asu
{u   Aau!{nu   {dTff.     Ai   Adu {eu   {c#ff.     ;ou   {rAxuDCAou	DCArE       {dE@ {pH5+ HDE؈U(MDEغ   HfD     {bq@ {n    {cOf1AT,@ UHAUIX   ATSH(dL$%(   LeIBaH   HH* HIE HC0Mte1HMHULLEH5* Bo   fnMfnEк   LH5v* fbfC(bH[HHDHC@HӰ %(  HCm   HC#  fC8H5* HC HfS;C=$HCPHEdH+%(   u#H(H[A\A]]fD  S 1$+@ UHHdH%(   HEAhFQ uFP1fF2HEdH+%(   u1*fD  UHHdH%(   HE1   fFPAhFP1fV2HEdH+%(   u1*UHHHHHHdH%(   HMDLEdL+%(   uL
L H* 1d/*@ ff.     UHAVATIHUSH8H>HL   dH%(   H]H}x"Chu%  =x     LDwu HEdH+%(     H8[A\A^]fuLHc]w   HcEIH@HLx(    o H[DMDHAo@AD@*AD(AD*Hẗ H& 0H͈  tf11nH[HI<w*; ELuƉEev8     H[HAD( D     1,n(D  UHAVSH dH%(   HU1Ҁ>b   IH~c      H5( H      H5( H   HYxrʃ+   EHltrateru|l   H͈ HLHU'tHUHEdH+%(      H H[A^]@ 1@ ~dt4D  |luH5( HtH5' H讻yH5' H藻bH5' H耻KH5' Hi4H5' HRH͈ fD  HaΈ &    UHHHHHHdH%(   HMDLEdL+%(   uL
L H' 1Ĳ&@ ff.     UHH@DWhdL%(   LMIEAE   H=N    At^ ff.     HDHHHH+p   ~HH   HxD  H   Hf.     EH=P 8   AEA  @ HDHHHH+ptf~HH   HxѐH   HfI8 tXH HUdH+%(     @ H     1@ I: uH8LMLtLMI H}к       1H LMH}H}tLMIo    DLM      ff.     HщHHHL+pK~HHtL@fHtHfD  A  H     Ax  HEX$     UHSHdH%(   H]HX   IYHt<~| H$ HH@9#HP0H͈ B
HfHnfl@HHUdH+%(   uH]#f.     @ UIHSH(dH%(   HMHju
ya   9ju9yru3Hʈ HHLoHEdH+%(      HH]fHϺ   H5 LEHMHMLEЅtruyet-<bu;H,Ȉ f.     ylscytuHSʈ bfD  1c"ff.     UHSHdH%(   H]HX   WHt H#( H5HH@9#HP0HpHHUdH+%(   uH]Z"f.     UHAVIAUATSHdL$%(   LeIj   LMH\  H-ǈ E,$H5' L9tH5' L&   H AbuA|$r   H5j' LtH5[' Lu?H HLLmHEdH+%(     HH[A\A]A^]    H5' L葵tH5& L~tH5& LktH5& LXqHoxfA|$ /H]Ȉ #     H5& LH HD    E,$HAbu"A|$cuA|$tuHň fD  A<$buA|$rthk ff.     UHATSHH>dH%(   H]H,   dH     H;I=oHC8A$,H{8    ILoHCH   LHu   H}HC L9tb<   HtSL`>   LHEHt9  LnHCHE >H{ t1HUdH+%(   u$H[A\]fH{TH{8TRfUHAWIAVAUATISHhH>,   dL,%(   LmIHH@  HxHx   I]Hx<   ID$ H  Aw:Lp@   >   LIH     LmID$A>I|$    HtS(fJK(9t
BvIt$ HnfHu)E)EH]HE)E)EIE H8ou!H}Hu4 uHwH+71lI;D$ tJH}葔1HUdH+%(   u;Hh[A\A]A^A_]ÐLH
     HEID$UHATIX   SHpdH%(   H]HRH   IH8# II$IB0HIBHHtHHHELUHMPHU1LMLEH5& H`ZLUY~5EAB(    AB,AB9#HEdH+%(   u"HeL[A\]fD   E1 UHAUIATSHdH%(   H]HH5 HݰtH5q Hʰu6L%È LHLhHEdH+%(     HL[A\A]]H5" H聰tH5 Hn   H5! HW   H5 H@   H5 H)   <c  <b   E1<fR{bHS   B<1QhH"C   g  l  ne  <e  <z	  E1@ L% @ L%iĈ C<r   tU<a   <c   <e  <gD  Ct-<t   E1<exCt<uh{ ^L%迈 DCE1w<@CHCluR{zt=<ltE1<gSE1e   <gz녃<e{ z<zu{ b{ SCE1<c{ 2C&E1<qy<eo{z^{ T<lu!C<th<u[<nt#<bt?E1<vC<cdC<et(E1<zDCE1<pt)<z1CaE1<gG{o{s8E1uP~   Hs
{ <gtE1<lZE1{eMf     UHSHdH%(   H]HX   MHt HS H5HHHpHHP0@9#HUdH+%(   uH]Jf.     UHHdH%(   HEHFHPHVHWHHEdH+%(   u1ff.     UfHAWAVSHh  dH%(   HE1H )Hǅ    xt*1HUdH+%(   E  Hh  [A^A_]    HIARbHx t@@tH=bLD   HPLHIHH r"H   AGH   HHDI     uIǂ      I  HHLA   H=A   LL LHIzIHUHI  I)HA   L)Hu
HtHfD  H @(HHEKf.     UHAWIAVAUMATSH  HEHLuHDHDdH%(   HE1Hǅ0    MtL.KMtL!KHHt     H01ёL MgMHǅ    E1L@ IcAD@A
   LM9e  LbMeD2EE   A   uHH   DH^  fo@DHA   foPDfo`D fopD0foED@foEDPfoED`foEDp1HD@A
'fD  DLML HcHL$HIt$=H  HH<H@HH*LC! L0M.  L&MtLIIMtL<IHEdH+%(   K  H  [A\A]A^A_]D  A}$ %AU u-AUIuA} PHK  IUHIE! AE    H8ǅ<   8@HHu4DLMNL  n   AG$  >`DLML     fH	 LH7 H    01&X1  L0     L1螎LMgMHǅ    E1L "f     IcAD@A
   LM;e  LbMeD2EE   A   uHH   D
H]  fo@HA   DfoPDfo`D fopD0foED@foEDPfoED`foEDpH1" DL MLHcHL$HIt$
Hz  HHH<H	LC! L0MH LH(5 H    013VMtH0H_IE H01HHEH0袌IWLMHǅ    E1L I"f.     HcÃD@A
   LM9e+  LbMeD2EE      uHI   DH_  fo@D   HB8foPBD8fo`BD8 fopBD80foEBD8@foEBD8PfoEBD8`foEBD8p1ID@A
!f     L LLHcHL$HIt$Hc
  HHH<HLC! L0MH LH3    H 01TH
   H0H,HHHEH蜖Ht  H59 H蕢  :   HpH    Hx11HMtH0-]IH   YC@ A}$ AU    AUIuA} JHg  IUHIE  H   L0     A}$ AU    AUIuA} XJH  IUHIE%    AE    H8ǅ<   8:HH   L LML n   AG$ AE    H8ǅ<   8+:HH   DL M誦L n   AG$)D  L0IA9,H0A1^f.       >DL LM%L    D    >lDL MߥL    0    IE  I  ID$L0HZ  MD$ffLȹ0000LfofnH



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HPL9   AT0d  
^  HPL9A0Z  
T  HPL9A0"  
  HPL9A0  
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  HPL9pA0  
YHPL9sAD<0  <
:2"    L0H H    01LL01ۃ8SL0A90uAyxuDLML HPL9KcHPL9.H0A<IGIOHBIG   
   HH9uA$    AW    AWIwA?CH   IWHIOA$ )AW    AWIwA?NCH   IWHIOHBIG
HH9u랃HPL9?HPL9*A   H8ǅ<   8E3HH   ՟ n   IGIOAG$A   H8ǅ<   82HHuq萟 n   AG$1fD  L LML`WDL MLf1   1fo1~>    {D  +>1    D  LL HE1Hǅ0    yL Lf     UfHAWAVAUATISLH  HEH(HH HEHD HdL%(   LUM   )PHǅ@    HǅH    ǅ<    Hǅp    )`M   =    D= EtoL(L@   1Lz	       LLPL   LAz蠞LHO  H x"   H@E1OHHCHEdH+%(   #  HeD[A\A]A^A_]fD  H5 茖tL5 Hd
 @   LHǅ    M   MIEHHh HHv HH>" HH] H7IH  H,LH@@HILyrLI      =  L   V@ ff.     Az   H5 L$LHABH   LHHǉ>H	  DHLA,L<  A0  H7 x" E  L- Au H    1Ff.     HY MH% 1H 01}F     ABfInL@HPflLA   L≅PHP DǅT    LhLpH<HHXPHHHPH(AZLA[     LE1Mt#HHL(A   9OL(IHHt<H  t  T  L(LD LHHf.     SDLE1AUL   LP^_tL(D HDtmf.     L(E1DLj A      j HAXAYDtL(A  tH릈 x"   E1H@L({HH{EL(Hǃ       AztE	   萔H(L(ABAz)L(Az)L(LzU     H H    HLA   012 $    CLHHEHMH     HL9t?~
uAu      LH,L@    H:H~L<H    HY x"   DtbfH H    HLA   012 $    BHL@ L1MLDE1IHǅ(     IcAD@I
   M9   AAЅ   A   uH(H    lH  fo@H(A    DfoPDfo`D fopD0foED@foEDPfoED`foEDpH1!f   L8H~Md M DLMcH(N,3D IuD HI  H<H@LD(sC/ D(L- M11H H D(Au @Au M1(H 1@D  H颈 x" H8 MH H 1L(01U@L(f     H M1E1HB H L(01@DtL(    L- A1MLH' 1L(Au ?L(AztE	   H(wL(ABAz$L(Az$L(L vHǃ       A~" Au MHd 1H 1<?    L-霈 HB 11Au ? H@HHHLHD<H(>H(DHHKH HHRpLD(LH L1L@ HAU   LE1AVLDHZY   H  wHHH@<HH H(g(HHnJH HHxou.ǅ(   MD  LD(H LH HL MH H; 1L(01i=L(H x" z1AE1H(1DLH(D E1sD  ff.     UHATSHdH%(   H]H   HtI{u-HesIǄ$       HEdH+%(   u5H[A\]Ð	   HNC{!{w!UfHHdH%(   HE1HG     H       HG(    HG0GHEdH+%(   ufD  UHSHdH%(   H]HH:-HC    H;:H    HEdH+%(   uH])f     UHATSHHH?dL$%(   LeIH{,Ao$AoD$CAoD$ C AoD$0C0I<$jHIL$Ht%Q(     rq(9t
BvHKHEdH+%(   u	H[A\]gf.     f.     f.     f     UHHdH%(   HEHHHHUdH+%(   u@ UHHdH%(   HE1H9HUdH+%(   uf     UHHdH%(   HE1HEdH+%(   u@ ff.     UHHdH%(   HE1HEdH+%(   u1Mfff.     UHHdH%(   HE1HEdH+%(   u1fff.     UHHdH%(   HE1@*H
H HEdH+%(   uf.     UHAUATSHHdL$%(   LeIHH= HH= A诇Eu(LH=a 虇ue1f.     t$HUdH+%(   uxH[A\A]]D  LH= I    tL- !    L- LLtuLLfyff.     UHHdH%(   HEH-t_=H= +tH= ,Hx HDHUdH+%(   u6H@ H= .H? HDf     H=- fUHH   H`HhLpLxt )E)M)U)])e)m)u)}dH%(   HH1HEHH0H8   HPǅ0   ǅ40   H@~	HHdH+%(   uUD  UHAWAVIHEAUATSH8H}H7dL,%(   LmIHE    HHEH9  f     HcS|o  L= fAGHw9HHH)H@ ff.        H8_f(H9u f/  IFI~Hp>LK(IV1A   I4IFLJ1Hx =~HCHIAGHL}EMu/  IGHS  II8Ld  yIGHuIwLHcK|~Z}!  Hk8HH<t(H H   HC8H9t)fD  ff.     Ha HpHH0HHhH9uH{fHS[H>Hu<;HEH0HH9yH}PDHH   @ HI3HuLH8IU H  IcL$l~PHk8ff.     1A   f/   z   wAHBH   H@ ff.     HJH   HQHuHAHHBHuHBfI$LLAD$L G:H.HEdH+%(   t  H8[A\A]A^A_]@ H8H9=HBHZ ff.     HBf.     S|}    I   ff.     H8\B;C||VfIwDEJ<    MI)HHNHff.     ff.        H8DhL9uL1MH41D  ff.     ff.     ff.     ff.     A   X   A   H8;C||Hu1fUHAVISHHH HCdL%(   LEIH   H9uQf     H H9t@HHHqH;   |HIH;   1HUdH+%(      H [A^]@ HH9u< ff.     H H9t&HHHqH;   |HIH;   ~H H9uڿ    LED!Hta~Eؿ    HEfl@fHnfl -HUHt)HPHSfHnLpfHnHCfl H,Hg@ ff.     UHH5 HAVAUATSH   H dH%(   HE1ZH= 1HH   H+@IH   L-      AD$l1fɅ~XHk8MHA   f(fI~I} fInHF HƸ   -fIn_]f(A9\$lI\$8f(kI} H HH1c-L.IH_HEdH+%(   uFH [A\A]A^]HEdH+%(   u*  H    H5 [   A\A]A^]Y5D  UHAVAUATISHH5v HdL,%(   LmIպ	   h^  H5S L~o  H5R L~  H5} L}y  H5} L}  H5{ L}[  H5y L}d  H5y L}  H5{ L~}V  H5 Lg}`  H5| LP}d  H5 L9}  H5{ L"}  H5w L}  H5r L|  HH=a 7Ht @1HUdH+%(     H[A\A]A^]fD  I}HH5 :AE<wuAE뱐AEf     HH= 6AE      Hw; n,   H!pIH  AA)AtyA      H5\ Hkfc  H슈 ID1HD 01-f.     HH=Z 5AED     H5 He      H5 Heu      4@ A[   H5 He?      AE8tW  Au9tF@  Au9t4@  Au9t"@  Hډ H3 101,MI^ofD  HH= 4H8 @A} tA} t11s     HX@AAHH= 4AEuD  HH= a4AEUD  HH= A4H @/HH=  4AEH4IE0HHH H 101*H4IE(HHL f      YHY4H H   HH; f     HH= q3H، @_H( L   H) 01P*;1AT2         D  UHAWAVMAUATISHH(HMdL<%(   L}Mπ4 uLL+GH H&    H	 01)HSHC I9smHn HLK-A      1PH 1AVRH} )H     HUdH+%(   ^  He[A\A]A^A_]fD  I9r
H9uI9uHuHc   IIM\$M   LI|$H)HUHH	HHEbu8   HEH   I|$HuE1E11H_   IE IG0MLC-IEHE   H5W H HUIG06HBHBHKP2HEH    PLH)P1Z(H 1H LK-A      1K*QHo P1AVRHJ (H zf.     UHH dH%(   HE1Ht@HGHtHUdH+%(   u,fD  H}0   BHUHB     1    UHATSH dH%(   HEH @H)HIHt+H{ tLHEdH+%(      H H[A\]D  H   uuHHtXfHnfl I$s Hc   !HCHt!1H5VH=YHCH= wI$qD  I$    _ H{wHC         UHAWAVAUATSHHdH%(   HE1  IIHOALH  H9Na  LFH  HGLILM9  HɃ HIJLUH    0j 1%LUZ1^IJH  MR HLq HUI$  LyHMLU  EH @H)2dIH  LHM)HMLUHUMM  EtIx( %  HAI9  HI I9  HtH9u  H9l  L9  D11)ǉ}1EDHkxLȃ@lHHH9HsHHLH Mq  L9h  Hl  xp u#PhHHDJe  @xpH0HHDHhLLE)LDD  )LEM@(H   M   D@  LLEI$  D  b1HUHauEt|Dm}ĸ   LEHE1ɍpG.@ ff.     ff.     I       DHMHIH!HI	H9IDAIE9u     1HEdH+%(     He؉[A\A]A^A_]f.     DH)H)Ɖ}   k     HH HPhu<HHA   1EL\( H   HGLIE1L@ xp t2LL9r*I9C^@ HV H"fD  PrftfPrzfHV HLFE1HHGLIL E1     x   LHMLUHUHELu?LEL]HHULUII@HMif     E1E1%D  }   LEHMILMLUHULEHUHLULMI@(HMf.     H ٿ   H$ 01!,ff.     UHHdH%(   HEHH9u-fff.     H H9tH9p(uHUdH+%(   uÐ1    UHAWAVSH(dH%(   H]HHHtVH  IL{ HUȋpHt7HMdH+%(   uDHsH{MMHMH(H[A^A_]@ HEdH+%(   uH(1[A^A_]@ ff.     UHAVSH dH%(   H]HH   Ht]H  IHUHMЋpKHt>HudH+4%(   uILEHMMHH   H   H [A^]fD  HEdH+%(   uH 1[A^]if     UHAVAUATSHL/dL4%(   LuIMt^I}HtDHG Ht6E1HWJHt H{gH[HuI}HG II9rvSI}?LVI^Ht>H{%H{(UHEdH+%(   u9HH[A\A]A^]Uf     HEdH+%(   uH[A\A]A^]o@ ff.     UH5THSHdH%(   H]HH=행 H= HtL   tH|Jy7HHHH   HUdH+%(   u(H]HfD  HEdH+%(   uH] ff.     UH5HSHdH%(   H]HH== H=I HtL   tH|Jy7HHHH   HUdH+%(   u(H]H.6fD  HEdH+%(   uH] ff.     UHATSHHH dL$%(   LeI@H)HtHHtHcP Hx1HHHxkPHCHtHxHtIT$ I+T$1HkxjHEdH+%(   uHH[A\]+hVfD  UH5DHSHdH%(   H]HH=ݔ H=锉 HtL   tH|Jy7HHHH   HUdH+%(   u*H]HFfD  HEdH+%(   uH]1ff.     UHHdH%(   HEHFH~H7HGH8HEdH+%(   u_@ ff.     UHHdH%(   HEHH9u-fff.     H H9tHx( xHUdH+%(   u1    UHHAWAVAUATSHXH} dL%(   LEI@H)H1HMLL9}  HG H+GHEf     M	I9Z  Iy(tLLELMLULMHLEtLP(L1M  LUfD  I9    L9     H| x) t    BMa(E1E1EHELHc   HHI{L;e}gLMUH}LE HELHc   LI{HUHH	:StHEHtD0LxIL9euLMHcUH}LEH? tPHcDfDHk8H*Y LL   H   H7H4  fH*^     t2DffHcH*H*Hk8YI ^A1   HGHtBHcHk8LM  fI*Y H   fH*^   H  Ht?Hk8LM  fI*Y H   fH*^   HcUHHHEM	H0I9HEdH+%(      HX[A\A]A^A_]     IfII	I*XfHƃfHH	H*XfLLfHH	H*X    HfHH	H*X!f.     LAfHL	H*XLff.     UHAUATSHdL,%(   LmIH   HH?2HUHIHI$  HtHR8؋uԉkHt&MtIE 1HUdH+%(   uGH[A\A]]ÐHt AHO 1H 01k IE     pUfHAWIAVAUATSHHuHhH&y LodL4%(   LuIH?)ED`Hz HE    HE    HE)E)EE   LL)MtHEIHHtH; ulHEL}HEHH   H5x    ~ tHH9   tox$IGIHHpHFz x t@ HC8HuL:HEdH+%(      Hh[A\A]A^A_]D  [f        ~L x H  Ax) urfH9tH9   uHHu    ҿ   OBH   tHxHxtHt?fHnfl H H9tH9   u  HHufD  H    bfUHHdH%(   HEH w @H)HHc   HcP HHxHHEdH+%(   u1 UHAWAVAUATSHHc   dH%(   HEHv H@H)HHXH    HL8L9tbIIfD  Iw(HtDIc   HHxH	HUMt!HUHtH
H    H)HHHI$M?I9uHEdH+%(   uH[A\A]A^A_]'    UHAUATSHdL$%(   LeIH?I9t3H@ HGfHnHpflHCHGpOI9HHuAD$4 HEdH+%(   uH[A\A]]@ ff.     UHAWAVAUATSHdH%(   HEHH9
  IILx13@ H    L1HLHIGpLxI9   I   HtTMH L1   MOLcA9 t   L ?    L)H 1zHIpI   Hkn L1   SHHIGpLxI9lfff.     HEdH+%(   uHH[A\A]A^A_]    1O@ ff.     UHH dH%(   HE1HtHH tAH}Hu\]t0H}@ t&A u HW8HxHuHF H+FH9 1HUdH+%(   uUHHHmu dH%(   HUHx t?JCJBHJBJ@x tHBAB@B@HEdH+%(   u       x uJDBfUHATSHHt dH%(   H]HBBHVH~HRL#Hքt*5ID$8HEdH+%(   uHH[A\]@ UHHHp dH%(   HE1:uHzo @,HUdH+%(   ut@ UHAVAUATSH dH%(   HEH      II1H}#   I$  HH9t;CZt(H(  1H}HH  H5D "  HI;$  u1H5 H}   H5L H}1Å   1H}I   @ 1H5 H}f   I$  HH9t[ ff.     CZt:1H5 H}(utH(  1H}HH  H5n uPHI9$  u1H5 H}u-H5 H}uH5j H}H}8HEdH+%(   uH [A\A]A^]û     UAHAWE1AVAUATSHxHhHUdL,%(   LmAMt
I  L81H}LEDU!DULEE  IcLEfE1HEABA*ƅx EuHMf H%{ J#H*^EfTf.v;H,f(f-> H*fTX< fUf(fVHj D,r  |   H}dSA!  HEJ4H   HEL  M9t$     AGZtE9@    M?M9uMH  E  HpELUL!LH}H   AE9B  AuLUE+   H}LxDMRuhLxDMƅxM:EiAu7A  @ -   H}jRu.A   fD  AA      H}<RtH}?6HUdH+%(     Hx[A\A]A^A_]     HEL  M9tAGZtE9@  <  M?M9uI$H  I$H  H}HsHEJ<       H5 H}wGHEJ<        H}bQ"D9u~,   H}FQMIL9u0HVh  u|   H}Q1H}HhH1fD  1H5_ H}DHEJ< L+   H}PLiM     MtHpLUH?@xu1M:E1Hg HE)    $Ez"fUHAWAVAUATISHhHuHk XdL<%(   L}LIGMw L}HEEt,HEdH+%(     EHh[A\A]A^A_]    MLL2(I)1Me I$fAD$FID$(    I9trLmM1E1I"AG,PAW,AD$xM$$M9tDA_FEo(I|$0dH9sfAGFAEAG(El$tI|$(uAD$xM$$M9uLmHEH5 Hx-[H  IMH  Hy   HEI} LHMH+uH  HuH^1  EHMHG  I} 1H9tHP(HtH9rH H9uqIELH     IEH@    IE@    I_H   D]IN    L]MM%f     ff.     HM)H   IELkxL`tI|$ tI} HIHq  HxP F  A|$p   AD$lt.ID$1IyPHHGIAPIT$HPIAPIT$ HPIEHx( dIy`H  fn]HELHfAnD$lIAhfbfAAXIEHp(LM)/9H&D  LQH]H{ H+{IU BCIU BBIU B@H{ IU BDIM    Q0c	AAM} II9V  E1@ ff.     H{(tH{A9DLHI9uEgELeHEH+     A|$p DHEI$I} HHE|LMHI} H91HH(HtH9rH H9ut"ET$hEtM\$MtfA|$r  MfI$I} LMHHELMHI} H9uD  H}   LMLMHIA`HHLuLkxH;]|!;ff.     HIxL9IELHHtHy tI} H_IHtHxP^I`U IE L8L9LuLe1fD  MIWLHDHI>I} t*Iv8HHt@pBpI} ;G0~G0I} M?I9uLu@     HELMIAPHE11HuLML]DU|rLMHEIu H9   L]|fDUMHH*   fI*f1I*^^fZHx(Ht H9r#HxPHt.zuIu H H9uLLMMUAMLMHIt$UH0AT$hHHPwLAfHL	H*XLLLM<ALMC ff.     UfHHdH%(   HEHf @@4@@@@@H    @@$HEdH+%(   u蝼fff.     UHHdH%(   HEH0f Hx0HEdH+%(   uHf Hx(BfUH=HSHdH%(   H]He H@!{ tHEdH+%(   uH]D  CC<tڄtJC<t΄tJC<ttEHEdH+%(   u=H^ H]   1H@ 01   D뀸      w    UHATSHdH<%(   H}Hl
Htw-   HHgCHtZ  L`HLpt3Hd E1BHH67HEdH+%(   u/HD[A\] HL-uAAú U1HHdH%(   HEH^d Hx@ tHx8 tHEdH+%(   u$ɉH] HO 101X     UHAWAVIAUATIHSH8HudH%(   H]HiA  MnXMq  fL5 CAEPM}8AUQL3EM  LUUv  At$<LAH  ECCAD$;   A:  Hu1LG%H}CAt$;AHT  AL$0HǉMAL$4fMbHH.  H5 HEH}Ht  uUH}zOH}E.5Et
{   AE2M}Em3LsEM<  LL  At$<L@H]  ECCAD$;   A:  Hu1LE$H}CAt$;@HF  AL$0HEl$4MdIH$  H5 H	Ht  UALNLA74DkAt{ u71HUdH+%(     H8[A\A]A^A_] HELh HEAt$;Hx?H  HEl$0Et$4IH  H5 HVHt  DLAMLA3DkT ES   HڈCHExh;D  LHE    tT   H5b L5u<CIHu1L"CHEHI9C@ AA:D$;#  A:D$=I     LHL8EDkHS1CHExh#WfD  LHE    t   H5 L4  AA:D$;	  A:D$=IHu1L!CHEI9HCf.     LUuU@ LH   APЀ	AL$<AGIPЀ	8uf.     HEAt$;Hx]=H2  AL$0HǉMAL$4fM*HH  H5^ HEξH}Ht  UuH}BKH}A0D{D     H5 LT3Cf     L(t   H5ʼ L3uCAPЀ	At$<%     AGIPЀ	@8uf     L%<H  HEt$0El$4IH   H5- H螽Ht  ALDJLA/DkCIL;H   AL$0HE|$4M|HHt}H5 HE$H}Ht  UAH}IH}AL/D;*CAA!A@ײA@ ff.     UIHcHHHZ MXdL%(   LMIPLH)H HHHpI9t0IApIHp(Hu(HpfHPpHr(HBHuH9uHcIs I+   LHHEdH+%(   u
Ix: D  UHAWIAVAUIATSH   HV HHH8L@L3dL$%(   LeL!I9u  D  M6I9  I~LEuH]HHLHF  HH"tnMe    H5ɹ L0  A$puA|$o     H5E L牍4/  4rS  f     HHtIE 8l  I   I   fHE    EI   A   I   xLHfHn8hHXHrLPHH`Hhx)M} u
}   ;   I   H@ f    HPIH  HW AFUx(   H@X    IHtuLIFHt\8 tWHCLsIIFL0H9X AF@IHEdH+%(     HĨ   L[A\A]A^A_]L+HW @A|$pH@AFL%uV      xH]hEHJfHn8HhHΈx)E} E1} FxexaHTW AF@A|$eA|$tNf     HH4O{E{ ;HcC Hp%I  A   LMG@H@U-SL#HpHHt{tPHU AFUx( uII  MG@1IA   H@U{ t{(uAFL%T 1舭     UHAWAVAUATSH   H$ H   L%9U AD$IH@HIIϋNdL4%(   LuMH   H)HXI}(  A]|vHf~YwTLcˉN    ID M)LIT      ff.     ff.        H8_f(H9uH@f*Hf/ȸ.  ɸ   A9A D?  OÉPM   HXf))ǅ   )p))L90tOM9tJHL0HE11LHpdHXHH9tI9uՋH0HMdHcPHHk8  HKO LPIL0MHHI(  HH    I8M9tH I>HA|$   A|$ tI   HI81H M9uLPL0 L0L(H5    1OHXAO(HIE(PHB8HI蘽HIfɋPH5 f/r/f/F H5 w H5 Hϲ f/HFHHMHղ H81IM0LHX艺fHXH5 f/ry H5~ Hw f/HFHHHx H81Mt0ET$0EtM;t$   ƅ?At$4tM;t$(&  H@x    IWH   IwI?IMLlǅl    WIH@H   L;%P AL;%|P A!HwL z  EtxIT$8H5ӱ    1lH5ʱ    1XoX   HLUt!HH5e    17    MeHMtAH=Pf HtL<t)HHLHM HH811IEHHf 
   ,1HUdH+%(     He[A\A]A^A_]     t	   9~A|$҃MuHXH P$IE08   H H5    1V1u    ID HtK L0L(IMAHH)@ I   H H1@I8M9C   PA|$ PHHHH8u?A|$ uH H޸   롐I   H1H  I   Hz H1cHH    PEM8H5 1EG(<X1ZYIT$8H5^    1lE}    ID$HHV  fH* ID$8YH  fH*^f/
 ?   ID$PHW  fH*Y`       H5 ^nCEL$4Er  L     D@4HEtID$@H   fH*HG8Y H   fH*^f/N H5    1X      XH5ޭ HfHH	H*XHfHH	H*XHfHH	H*XVHfHH	H*XHfHH	H*X1H52    X	ID$HXHxZfH*BID$@Hx{fH*ID$8Y HxEfH*^f/ ƅ?lHfHH	H*XHfHH	H*XHfHH	H*XpUHAWIAVAUATSH  H   H0H   HH@ dL$%(   LeIH@HXH?K fH4K HHAHM H)Di zHLpELxMc$   AHx)A)HH8H$HXH   ,HPH  H8IHzL ID,Ix   HzJ x tM9$     H?L @HC  H| HH=AJ ILӕ  5  HD   RH5A DP1HHQJ H H5    L1H<E  B  HHBH9u<@ H@H9t/HH(HtHJ8H    1Hݗ -D  1H0HH   6HXjHHHL8L9!  A   E  LpE1ǅH    LXE1EfHJ MDLHX  #  A  Mm M?L9;tMMuHJ MDLHXLAą      MHM?E1L9;u DHHHPHEdH+%(     HeD[A\A]A^A_]@ AM?L9;tHI E1DLHpuAfD  L  Hz LED  M?L9;LGt&fHM?L;;(     MA   fHG H@@IHN I)Ic$   IIILJH+N   HHMHMD,E1L8IL9twI$Ic   LHzHhHH	tHhHtL MtH@       H5 HH1LI`L9uff.     HHL8D,M       1H H5ǧ @ LIA$   H   LL8HHH|L8E1     HE H A   H	    L8H81诜L8HtV M?L9;@AAKǝ    UHAWAVAUATSH   H$ H   H$ HH1dL,%(   LmIIHǠ   Hǅ    I   HM   H@ HÅ   LLHF x uML=D LL,AGI)I<$袥HEdH+%(      HH   [A\A]A^A_] PL=D HA I   HAWHHH)HHHHH   ް[f     H޹    Hg  HIt$-H1H=͑ 9"@ ff.     UfHAWAVAUATSHH  H|HHpdH%(   HE1B{BzHsE PH~	  FLǅ    HbC IxA$|ICHtHE y	ɃLN HNDL~Lv(LC(LXLN0HhHNL`Et}Itff.      H
	  HsPH  f.zDuBLfI#  D{fLMD        fA   f.@AE@  I    E1{HE1L   Dy4D  IUH5X L1AAD9c|   HC I8PH wIcHH)À   HLHA x ux   IU H5ע L1AAD9c|xHDDyD+|Hx   HsPH"  f.z  HV HH H   fD  LcHJL)H@    H8_f(H9u?f{fLD|H
 1LH5P HHDADHE)Hx    HCPHn   f.z[  E1DLZ      H5 AH=A HCPD	 4	  H[  HHHN  D1   LH5M AHA Dx }  E  LD+1LALAHC08 6  LK(I   HCHHFA x   HL   H LH HH81L~#z -  7   LhLL1A֋LhHCA)He  Hx Z  H.(  { !	  1HC(H9C@ƃ-H`LHL1AH=Y@ H   LH D@E@HLH5pe L1A֋HLHǅ       ǅ    A)1D"H? x    HpHPH   Hx HU  Hs(HiHH*  L@M  IBHw3L;< L;< !H8  	    @ HLDL1AHEdH+%(   v	  HĈ  [A\A]A^A_]fD  H HE  H0 HL% 1   LHLAH> DP	HCPE  E1H  L% HHLHHH L@    1DH 1   LHLAH/> Dx E  L% H LL1   AHC08 YH=H  HfHt,HHH  fH*H  fH*^PfɅt!@ffH*H*Y ^H      H $   L1HH5o A DCpE#  x   x   LHMH̜ H HB   L1Qz LL1A֋fD  H5) L   Af     HtHHHH   1LLAH`< x KXHS`Hs\LCh<LH   H5 AHzf.     HL]LH; @T  <HLL Hw H H@ D{fLDH9 H/ x ux H H HED|H5# 1LDHDAH DHHE)Hx vHCPHt fD.L%i 1   LHT LAH: DP	HCPE'  Ht_HHHtVH A   HL% EP  H     1LLAHR: x ;MH HIJ81H L   LL=   AAEtI     HLDD  Hc   +1HcHHr LSH  Hc,   fD  H5
 L1A@ HDC8H H@EtH9 x   LL`    1H L\ALL1DADHK0+HL1AfD  HL%2 Eu2L% H    H=  HHH    HpHPHpHLHpH8\IHpLX MH    LLLHHkLE1E1Hs(H1ɉPHn
L8D  H HHe HL<h+   fA   f.AEMADD+|fL%M HLHx	    LLH HA1R{spLXLL1A֋LhL   HcH )L1LHcDLAA   A_L   1H LA:DD+|HlHsPE1HHS HH	 Hff(^HуfHH	H*XH΃fHH	H*X͋fff.     UHAWAVIAUATSHXH3 ~]f dL,%(   LmIL%F5 HE   @HuH)HfHnHPIflfHnH)E~	f HEfl)EA|$    HHH9tXHEHEfD  A<$ tH{(t#HULLH@L
   E HI;uA|$ t	I}&HEdH+%(   uTHX[A\A]A^A_]     IE IuH   <IE H   Hx hIEIHH9G^ ff.     UHAWAVAUATSH   H$ H   H$ Hxf1dL<%(   L}IIHǠ   Hǅ    I   HxLI   Lp H))Aą  Hl3 I  y    L=t1       HHK&H43 M   LK-@H   Hc LH- HHHՒ    H8AV1؇H, HHH0OAGH)H;蟑XZHEdH+%(     HeD[A\A]A^A_]     HhH2 H- L=0 pI   @2AwHHpH)Hx4I   HpќHhD  H/ A   H@ H}    LxH81߆LxL@ Ag  Hx    HA蔙Hs-H1H=} чUHAVIAUATSHHHP  dL$%(   LeIf   HIHCH5 L)HH-1)L'   HH5 L#IH   H	/ x t	M9   tzHCHsMLHʐ H@ HN-   L   1蚅H{L1HL轋HHEdH+%(   uPHP  [A\A]A^]A   xL   LL\fD  먻]fff.     UHHdH<%(   H}H=C H=C HC     tHC     HEdH+%(   u UHAWAVAUATSH(L%d. H   dL4%(   LuL  L   A$Hd  HH    S  Hl- y B  H=;C H;x   LH   Hx \H=C HC H=C -HB H   HUI@H   ֪~   H, L   @LH)HHMHLhH9uQIEpLhH9tCI   HtIFI9uLtyIE8 upHEIHIEpLhH9uAD$f.     1HUdH+%(     H([A\A]A^A_]@ HB HAD$AD$H  L5A HEfD  IVLELHHuH  I    ~JH+ PH   H)H HHpI9t&IExLxHx(tYIGxLxHx(uII9uAD$L%G( Mm I$L9u
HHL9t@H{LuC    IU I7H}ȚtM,@     ^HHLJHCHt18 t,ID$I\$L#HCHCHwpHcނ ff.     UHAWAVL}IAUATSH]fHnflHhH* HUPHdL,%(   LmI)EfInH)flHH)EHL`H9u1V  @ ff.     ff.     ID$pL`H9*  I$   HtHBH9uL_1LH  LeHUI9   H]LxMM    IEHXH   L9u(   ff.     ff.     HL9   HJHyH;   |HIH;   IEIu LHFH0HELhIE MeLmLmL;mrMALeM9tCfo%( I$)eID$foUI|$HCHA$`LI%L9HuHEdH+%(     HhD[A\A]A^A_]     H=( MWI)MIzHWH(   H{pI9tZLeILIHtXIvH;u  M9V  LF  Lt"ILLe{A tzIEHXD  LID$pL`I9  Hp(D  I
LYL9HHWH(tK@ HJxHQHy(4I9uM H' PLH)H0HH9t_H{8HP'@ ff.     ff.     HBpHPH9t.H   H9uHtHHU襈HUH}LEH;H56 HIHpHpH9HCpHPHx(u"f.     H9HBpHPHx(tH}LܑMMH]L}ID$LxLpf     LMd$HGHHPHQH
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 LNL   H1L-d     UHAVIAUIATSH   H  H dL$%(   LeIH   @"HHsHpI$   裸I$   HsH@HI$   Hp|H= H@HHHH9t/H9t*LPI   1H,n LZ-     HKLC   1LPHn L+H@vHHvIuI} 1A   H MHUdH+%(   uHĠ   [A\A]A^]c@ ff.     UfHHH   dL%(   LEIHtH  BtuFH	     upHEdH+%(      H5^V LǸ   Z     HcHB 1HHxWfH*HxgfH*^Y4y f.     HEdH+%(   uRH5U LǸ   Y@ HfHH	H*XHyHȃfHH	H*Xjbf.     UHAUATISH(H  1dL,%(   LmIHcHtH@ HH=?B    H=  wdH]H   1Hl H'IuI} 1IA$   HϠ HUdH+%(      H([A\A]]     H]f   H*Hk H߸   ^ox Hx;fH*H]   Hvk    H^2x }Q     HfHH	H*X aUHH   dH%(   HEH   Ht	H@ Hu4HEdH+%(   uTHFH>Lj H H1D  HUdH+%(   u LNH>H L   1L`@ UfHHH   dH%(   HMHHt3H  HR HxdfH*HxtfH*^Yyv HJ     ukHEdH+%(   |   H5)S Hϸ   V HփfHH	H*XHyHfHH	H*Xw@ HEdH+%(   uH5R Hϸ   Vw_    UHAUIATSH(H  dL$%(   LeIHH H?B    H  w[H]H@i    1HAA   I<$1IIt$H  HUdH+%(      H([A\A]]fH]f      Hh HH*^u Hx;fH*H]   Hh    H^Ru W     HȃfHH	H*X@^UHH dH%(   HEHHtH   HE?HEHUdH+%(   u	H#] ff.     UHHH dH%(   HUH  H:HtQH     H1Ht=H-H-HMHUHMHUuDHrHAH9t'H)ff.     HUdH+%(   u    HAH+BfD  H/]@ ff.     UHHdH%(   HE1HEdH+%(   uHHs\D  UHAWIAVAUATSDHhHM]dH%(   HEH   H  HI   H~  ffHnI)[ )d )m )v fHnH: fl@3 I)I@H+  IHpH  HB HRH9T  H]MIEHE11Hx1LEIHE    LUHp5fD  ff.     ff.     AH]DL)H9w  HkxI7Jltؿ   HU誐IH  } HU  H}   貛H  I$   HUI  I   HML@HEH@H@(I4$H2It$IcIt$HrIt$LBMD$ rhAt$pDJlIL$hEL$toB(AD$(oB8AD$8oBHAD$HoBXAD$XHt:} t4MI$   LUH4HxAL$xMD$ EL$tLUM$   H}LH5K DMLE^H   LcMHE1II   LBHEHB pHpHtHEHfff.     1HUdH+%(   uCHh[A\A]A^A_]H    f     LnHE    YLfff.     UHAWIAVAAUIATSH   H}HcHx	  H`IMdH%(   H]L虙HPH  HIHEI9  AG  HDL~V4 L=} fHnIcH@ID flL  HX)UD  HEDeII(HH}  EHEL  E  IEHElHH]OAǅ   E{  L`LpLhHXMupMLe@ IFAU fHnflAV(AFfInflAwYIc4L>     HIFD  HcH2 foMLHHANH2RIv0IvAV,;IIư   I9gLhHuH}LprMtEM]Lxf.     HuI|$ALL9L衛IHuًE~f~xEAE A   tIAX  t<A  t/A  t"Ah  tA  uA  H}1IŸ	  JHEH HEH9EDLH@D#HEdH+%(      HPHĘ   [A\A]A^A_]     HIFpHiIF`HIFPHH5b IFH'IvIF*f.     HIFHIF HuH}spMSHUH H9H H9uU UHAUATSHdL,%(   LmI~/LcLMi	  Mff.     HHø	  pL9uHEdH+%(   uHL[A\A]]k6UfD  UHH dH%(   HEH@ DEtHAt"AHEdH+%(   u`D     H @ HEdH+%(   u9poH 11Ҿ   A   DU@ HS L #DUT     UfHHdH%(   HUH  HBhHuHEdH+%(   u}fHRHx/fH*Y~j Hx?fH*^ZfD  HуfHH	H*XY?j HyHfHH	H*XSfUHHdH%(   HEH H fff.     HtH;x sH@HuHUdH+%(   u H9x(sH@WS    UIHAWAVAUATSH(H! dH%(   H]HL(Mu)  f     ff.     IEM}Ht&IMu MM9rM9M(   IEM}HuLM9M(p  L9  MX   LMfIHA  1   LLMHHh LMML$ H5` I\$(ID$0M,$M'
  D  M9r   AE0           X   LMIH  LM1   LAu0AoE8HIAMp I@(Ap0A@8IEMM AE0   IE@    HM  D  HH@HuHBfIH5 LA@L BM|$(L9  M    M~(L9   ML9  LM褕IH8  HP H9+  M}(IL9tX   HUIH  HHU   1HMy HIQ(IVH  f.     HHRHuHPIH5 LL
kM~(L9CX   dHHJ  1   HAoFHEN4Iv8HHCBHfHB Lz(DJ4Hr8IFI^(AF4   AFHH   HH@HuHAfH
H5 HBHÛvX   ƑIH  IE(   LHP1HIV I^(AF4   IEHG       IH@HuIGM>H5 LL0KH H@LLHMdH+%(     H([A\A]A^A_]    IVL@ LLM蔓LMHH}Lp kX   LMHuِHuLMHI   1   LIHML$ Mt$(AD$0   HFHtt     HH@HuHFI4$H5 LL ZAE4   MIIFLQIEIELMHFYNE1E1E1fD  UHHdH%(   HE1Ht`HGHtiH RH)HPHtRHG8HxWfH*HB HxgfH*^HEdH+%(   uf    H fHx uNd @ HfHH	HB H*XHyHfHH	H*X^Mf.     f.     f.     UHHdH%(   HEHGHtH@ g  HEdH+%(   u1Lff.     UHHdH<%(   H}HH5U GDtj   &fD  ff.     ff.     HH't6LDu!HUdH+%(   uf.     1PLUIHH   HhLpLxt )E)M)U)])e)m)u)}dH%(   HH1I:HEǅ0   H8HPǅ40   H@Ht2IL0H   uHHdH+%(   u H0   LuKD  UH~HSHdH%(   H]HzH    tHUdH+%(   u.H]f.     H K
DtCDJfff.     ULHAVAUIATSHHPRsdL4%(   LuIy`H   H}IZHHML   HtHEH@ g  H}!HHE1j LLL   >L6[X1ZHUdH+%(   u1He[A\A]A^]H_ AM HX 101艏Ifff.     UHAWIAVAUIATSHdH%(   HE1 txI1E1HuEL9s=G&LI| 1H)L^ H   IHHAFI9rHUdH+%(   u!H[A\A]A^A_]fD  Ht 17I    UHAWAVATSH   H$ H0H fdL4%(   LuIHIHcS HEǾ   H)Hǅ    H1HHZxLLHtHUdH+%(   uH0  [A\A^A_]pHUfHAWIAVHuSH(dL4%(   LuI)EHE    xLLH} HUdH+%(   uH([A^A_]HULR HHAVL5R AUIպ   ATISHLHLx dH%(   HE1WHAV1H|^_t^ATLE    1AVHLHL"R 諔1HAZYt#1HUdH+%(   uHe[A\A]A^]D  H.G ff.     UIMHHAVISHH}HQ H HuH HdH%(   HE1x3HH9s1MuHEHUdH+%(   uH [A^]f     1F    UHATSH   H$ H1dH%(   HU1H     HHH菝H~%/   HƄ HH9r-E1H:HEdH+%(   u@H  L[A\]@   1[HI    E1EfD  UH0  HAWAVAUATSHH(dL,%(   LmIHEHuHE  H  tE  H@  HUH5  sAƅucH   D=ݛ HuNfD  HpHHt8H]LmHE  {tD}H  HUH5<  stAHEdH+%(   uH(D[A\A]A^A_]Df.     UHHdH%(   HE1 HEdH+%(   uxD     UHAWAVAUATSH   dL,%(   LmAHǅX    @  H    11HPHN i  11HHH  HPH5vAjIH  L`M  HvN E1H@HXHHE8  L8MD$HP1   H@HHC   HXH5miIH  LxMu2  fD  H`H)xLLmIH  HML$Aw1)   )      H`L9  ^_(~L8LHHxH1tLlHPоHEdH+%(     HeH[A\A]A^A_] 1{8@ L MD$HP1   H@HHF  HXH55hIH3  LxL`HuM  H(H0*@ A>/^  LLIH  HML$AwL)      L8 1)   ՎZY(   fL)E)EEbIHtH5L HkH0)   H=q H84|NH8L]L8?8+LHL(L 	 HP   HK IH E$01)A<$HXHHE1     HE)   LHH8e,LHHuL蔄IHL8x@ L(LHHmuLUIHL 9L L H    HXD 12HJ /L8?ff.     UHAWAVAUATSHdL,%(   LmI薙H(w2IHtXH LKt%     HH9t7Du1HEdH+%(      HH[A\A]A^A_]       VLIHtHXHtUE1fH{LL聽uMu8IHHHuMt I~ǍHL\k    1>    UIHSH(dL%(   LMIuEtM   E  Hn L-I 1IARH HI H}P   1ZYyHE    H+HEHUdH+%(      H]fD  H}HLLMLULMHM   Ht\ILN Hn dfD  1L3 EtLqH LLm :@ LLm 'f     Hm L D  Hm 1I    HtL IMLfD  L LM<f     UE11HATSHdL$%(   LeIHH1OHtWH5# HHbI$E1Ht,H贸HEdH+%(   u*HD[A\]f     {D AAF<fD  UHAWAVAUATSH   H$ H   HEH]HIEEH   H HdH%(   HE1Hǅ    pHAEIDH HIHCHH  HW    H躂  Lrl ED  HHپ   HH1HE E  H1tkER  H HtHn  HH|t/8t%H0L   ff.     E  E  LƔID8.        Hǅ    zIH  HHaE Ht   H~IHH    LH8  \IL   HH      H)I<IAPLE 1&H H #1LIDHZYHt   H莋&  H LM"  L貵LLn1Hپ   LD HD L#  H1   H HtH葿E  HLztd!8tZHL轑tGf     ǅHN  f.     HH=y }  E1H   L>Ht/   L   L  IIt  LpAE /H= oLLlAE ../.LAE.貈"  H    H HHIHtJH H .HLRH    LGcLڇ A1HHF 1   }H觳L蟳H藳L菳HEdH+%(     He[A\A]A^A_]    H4{   LS* EHB LEfD  8   ǅ xkFxo7    Lه L1HA    A1L|LcLxbH bL    H HL`   D    HLdH  Ƅ HL4L%ه HM1HD    A1E{HHLk ǅHE1    Hj    L؇ HHD 1   A1zNIHt+H1HH近x_LlpLL-MOm    ǅ1E1XH HL>_ǅHE1ǅ1
4Hׇ LH? 101yUIHHSHHdH%(   H]H]   DEEt31HULULMH}>DEL]LULMHH}2 HLULMHUH}H}L]LMLUHDEHtjSHLLAQEE1HUKHU^_H׉EǯEHUdH+%(   u2H]    SHL1AQEA   KZYƸN3 ff.     U1HS1H(dH%(   HU1ˍHHt1HEH}؅*HEdH+%(   uH]2 ff.     UHAUATSHdL,%(   LmI   g   IgHM   H      HL#H   1H@     LH蘉Hx{H/uo/   HLH7 HxHH)H   1dHEL#HHEdH+%(   uHD[A\A]]fD  A1ff.     UHAVAUATSHdH%(   HE1=  t%HUdH+%(      H[A\A]A^]D  HH=ۇ II־  6t
]8uSH0  LL֦H   AHt(    HLL貦HA	GuHHuA`V0fD  UHHdH%(   HE1HEdH+%(   u1H5  g0fUHAUDATDSHdH%(   H]HH@  AH   Ht/fff.     H  DHA	vtHHuHEdH+%(   uHD[A\A]]/ff.     UIIHH dH%(   HMHщH   ȃs;   tAA    AxHEdH+%(      D  IIpHI ITIT LLH)H)ȃr1AɃN
N9r    Hi҇ Hu   HQ> LE01tLMLE      3D  AAATAT = AD	fAD'.UHHdH%(   HE1HtWuHUdH+%(   u    1蹰Hl.ff.     UHAWAVAUATISHHXHuMdL<%(   L}E詯H:  LmE   H:  )   Huو11H}蜈HHt|H\   L^ EthH}HHo8 1L`xHI9sMtHE    HHEHUdH+%(   ujHX[A\A]A^A_]fD  1@ La8 } uL  } Hp8 LEp     H}HH9 1Lc- ff.     UHHdH%(   HE1HEdH+%(   ue  AEޗ,f     UHAWAVIAUATL:  SLHXdH%(   H]Hyq  Ag  uL߭W  Lϭ   I   Eb  HEAf     HCHECfEHfH}LAN     I]D@E    HI)EDE)E3EDu$   LuDEHuf fELC$DEfE#xHuIUHLHUdH+%(      HX[A\A]A^A_]    Ae  v`I   E`  HEAf  	H}1蔷HCHECfE    1pf     HH@0HHEI*UHAWIAVAUATE1SH   De  dL,%(   LmII:  HǅX    GI   HHjU  Eg  AC  Ae  \  AAMtA}  Mm(A}  V  E1A   Hǅ8    E1fL)pHǅ}    &I   H`xHHHpH0oH`@@H0L5  耇1L@0&)   HuI:  M   4HH}AUL8LDG@HH膣LAXZHX=HEdH+%(      HeD[A\A]A^A_]     IE0HHA}   Mm(A}  tLHHXL1HZ3    D@MaAąyHXL8D@HHEf   fD  ;,LA@EfHǅ8    E1Hǅ8       E1( UHHdH%(   HE tHUdH+%(   u@     'f.     f.     f.     f.     f     UHATISHH2dH%(   H]H薻uLcHEdH+%(   uH1[A\]/'@ ff.     UHAVISHH2dH%(   H]H6t"HEdH+%(   u(H1[A^]     HsHSLC0&fD  UHSH8dH%(   H]HHtHH׀: u;Hɇ L Hً0M   H5 11k   D  1HuHMUH}HMH? tiH5ʀ HEH}dHMHUЅtqH}H5U ydHMHUЅt]H}H5> ]dHMHUЅJ   @fD     HH1HUdH+%(   u/H]D     ֐   H5 11jo%@ ff.     UHAVSH dH%(   HMHHtHH׀: uQHjȇ L 0M   Hq4 11jHUdH+%(      H [A^]    Hu1HM衐H}Iƀ? tmH5f H}5ctqH}H5 !ctmH}H5= cHM؅P   @'f.     H3 11iS    LH1@    f        $$@ UHAVSH dH%(   HMHHtHH׀: uQH*Ǉ Lk 0M   H13 11HiHUdH+%(      H [A^]    Hu1HMaH}Iƀ? tmH5&~ H}atqH}H5 atmH}H5d< aHM؅P   @'f.     H2 11hS    LH1@    f        "@ UHAVSHdH%(   HE1H   H> }   IH5. Ha   H5- HatpH5 H`t]H5- H`t*H5 H`tH5U H`u4@ HUdH+%(   u@H[A^]        f     H}HL3x݋U1!ff.     UHHdH%(   HE1HǇ @HEdH+%(   u!fUHAWAVIH5, SHHdL<%(   L}I׺         H5, H  ;u      H5, Hǟ     H5, H諟     H5, H菟  
   H5, Hs  1HUdH+%(      H[A^A_] {ic{.YH5$, H赴uLHnH=ȇ @    H5+ H聴tmH5+ Hnk
   1LHć Nf     HEdH+%(   g  HLH[A^A_]     
   1LqHƇ v HEdH+%(     HLLH[A^A_]:D  HEdH+%(      HLH[A^A_]5     H5+ H聳~M   H=ȇ   Lqƀ   UH5+ HAtEH5* H.tJH5* HLmH|ć H@ HLm覫@ LHmHÇ @H HK* 101c ff.     UHHdH%(   HEH HtHUdH+%(   u!f.     H=G* kHm fD  UHAWAVAUATSH(HudH%(   HE1H>  HlHEHEH  H}H5; 趋LeIM   H}    HH9  Lxf     IG LxH9   I?L脱uMwIGI9?  HXf     HCHXI9  H;LDuK"H=| H,H}AGCkIHt@H{'RLc14H    HA H( 01bLĘ@ H}貘HEdH+%(      H([A\A]A^A_]fD  0   nQIHtLpLfInfl@MkIHbHCfHnIW HSfHnflAG Hf.     (   QHHJLjHHtXIGfInHSIWfHnflCHHݾ H@    H' 01arH Ht@    H' 01`HwfUHAWAVAUATSHHHHudH4%(   HuH5( H  H IIE1p    b     E    H\ H.' LuAŃ  
  /  Ht$  D8>  H& H9>  1E  H A d  A#  A;  A[.   U  HcUH H]HMDDjMcDIL- M	  L虤Aƃ  
    5E u)H5B A,  A-"  A_  AH]HEB( L- MtNA t
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  uL- A
       MuA t     A	Y  fD  1HUH}  H E1IHH      =G  tD  1LH3     HEdH+%(   
  HH[A\A]A^A_]    E4$   J  IM_Hῇ AH]@
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(  H$ H9    AąOL5 MtL1詢AŃ4fff.     L舢
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  H# H9u\ H A   I     H<
  H# H9f EHp L 1MH& 01\Lf.     L訡
w  l A
   D  LBHGZ  f.     E4D  D% EL5 M  H=  A
   MA 3>fD  L
tLqAH=  E D  A
A=uH]E1LE1L}E1E    ^ U  EtMtH$ B8 IA\  A"  H  E1F48IH H   H-Aƃ   
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A#HH A   Huff.     MH]L}I  MH56 B6 @ MB H]L}I  v     MH]L}    I  vZD  H 
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     b    n  tu	   H4 B9I       uE1@ AA
   H]    @ L5 M[ L>f     <     L5 LHHl[@ L؝
E   E1{Hi H]1HEIŐff.     L%y Mp  L舝Aƃ  
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 HM A   B!I        AofD  N DC > EwH2 @
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k]dAD$.   McEHEfB< HUDHS ff.     ff.     ff.     ff.     ff.     A@
HA    
A   uL辘
EL;9y E3AH]E*f     UHHdH<%(   H}H= {J   HtHH= [1҅HEdH+%(   uɉc UHHdH<%(   H}H= J   HtHH= [1҅HEdH+%(   uɉ UHATSH   H$ H   dH<%(   H}H=a IHtsIĀ8 tkdtbHL   1H3 xH[HH   HPHSxDlEu7H u
H腈1HEdH+%(   u<HĠ  H[A\]D  A9tH_ HH- 101QH< LH 101gQD  UHH=5߈  dH%(   HEH߈ uHtHUdH+%(   uÐHވ Huވ UHHHdH<%(   H}HH5ވ HUdH+%(   uHHO:f.     UHH dH<%(   H}   -@HHt+fHnfl H: H8Ht(HHUHUHEdH+%(      HHU9HUtHU   H{\HUt=HUbHUtHUHUHtHuHHU|HuHHUu]2
fUHSH(dH%(   H]H   )?HHtfHnHHHEfl HUHEdH+%(   u	H]H	D  UHAWAVAUATSH   H$ H   H$ H8HHHdH%(   HEHH9   LxE1IGMoI9teHXfff.     LsMt>ILHi 1    HGHLHAxQHCHXI9uIG LxH9y    HEdH+%(   uPH8   D[A\A]A^A_]@ H۫ 1MHH 01MDE1lff.     UHH dH%(   HMHH=ۈ Ht HEdH+%(   uKHH]D  HuHM{(HMHuHHqۈ HuHEdH+%(   uɸf     UHAWAVAUATSH(H}dH%(   HE1H   HHH9   LjHLrD  IM(fHnMeflHJHIUAE HL9t\HZHLzff.     Hs fHnHflHrHC<H{w<HL<IWHCLzL9uLS<LMIV IF H;Et
LrQHEdH+%(   u5H}H([A\A]A^A_]ڂHEdH+%(   uH([A\A]A^A_]    UHHdH<%(   H}H=و 諈Hو     HEdH+%(   u:f.     UH HHHV dH%(   HMH101{KHEdH+%(   uɸUHSHdH%(   H]Hw HtHH    1Hё; t,HEdH+%(      HH]   H=0 cH= DBHt?HIH 1Q   L H߹      pRXZƃ   D    H5B HWD  UHH   H`HhLpLxt )E)M)U)])e)m)u)}dH%(   HH1HEHfHH=bHH0HP) Hǅ@    ǅ(   ǅ,0   H8ki@HHdH+%(   uff.     UfHH@dH%(   HE1HuH}H=bEEEiHEHUdH+%(   u    UHAWAVAUI͹   ATSH(H U   DdH%(   H]LAI!L)IILA15?H   IHtzN4 D  t/IH)t^IO4'}LHLHy,8tM4LLÍHEdH+%(   u&H([A\A]A^A_] M11ǻf     UHAWAVAUIHATSH  HHdL4%(   LuIHǅ    PLH0IHtt9LLb~HEdH+%(     H  [A\A]A^A_] H1HH    跖"  L/   L;HH  H[H{HHPT .HAǅ  H`    8tD+HHLOL11գHAvsExL`11DDD+D+uHHBz HLH Hǅ     H OLH5R 豜H HrHHH5L0 膜IHu"   f     H LtdHٺ
   HH 衕HLH H|H D6D*D  LH |HYE1vLef.     UHHdH%(   HE1HEdH+%(   uHѺ  S UHHdH%(   HE1HEdH+%(   u1nf     UHHdH%(   HE1HEdH+%(   uɺ  }fD  UHHHHdH%(   HE1HG    HǇ       HH)   HHEdH+%(   u1pUHSHdH%(   H]HH`HC`    HEdH+%(   uH](     UHHdH%(   HE1H    u3HGpHHGpH   HHtHUdH+%(   ufD  HEdH+%(   u1UHHdH%(   HE1H   u3HGxHHGxH  HGHtHUdH+%(   uD  HEdH+%(   u1@UHHdL%(   LEIH   HuHH   HH   H   HtH   HGHtHMdH+%(   uLD  HEdH+%(   u1     UHHdH%(   HE1H~( u6H   HH   HF(HGHtHMdH+%(   uD  HEdH+%(   u1@UHHH   dL%(   LEIHpHG H   HtHMdH+%(   uHLHEdH+%(   u1     UHH0dH%(   HE1H~( uVH   HH   HF(HGHtHUHuH}H}HuHUuHEdH+%(   ul@ 1HUdH+%(   u@UHAWAVIAUIATISHH(LEdH%(   HE1H   HLLt%HUdH+%(      H([A\A]A^A_] LLe'HEH   LHLIuHEL}L8I9taLLHLL   KuMu@HuHLst-ef.     HtLLHL
=HH,HUdH+%(   u)H(HLH[A\A]A^A_]ƈfD  I9u@ UHHdH%(   HE1H    u;H   HH   H   HG(HtHMdH+%(   u    HEdH+%(   u1h     UHHH- dH%(   HMHH@H)H: u=H   HH   HHG0HtHUdH+%(   u#Hf.     HEdH+%(   u1     UHAWAVAUATSH(LEdH%(   HEHFH   HX HIIIIH8&YHLHWudH   IIL$HtpH9 HHLHMDpRTu.HMAH]H)HIU IL$IT$ H+QH    HUdH+%(   uMH([A\A]A^A_]fI|$ 1L 1{ID$HHtHvnIL$HX1@ ff.     UHHdH%(   HEHG8HtHMdH+%(   u@ HEdH+%(   u1PUH HAWAVAUL-҆ ATMSHXdH%(   H]H     IT$IHtA4$HntL= ff.     Eu A   A   ux   @   H}1ML @   CDHUH߁   0nuL   @   H}MLe @   CDHUH߁   muM}IM`HUdH+%(   uHX[A\A]A^A_]fff.     UHH0dH%(   HE1H~ "  HHH   Hy    LM   Ix u}I0Ht-HULEHMH}H}HMLEHU   H   HH   I@HGHHt)HULHMH}H}HMHU~   @ H   HH   HAHGHHt!HUHH}H}HUuB     H   HH   HBHGHHtHMdH+%(   uH@ 1HUdH+%(   uUfHAWAVAUATSHH(  HLdL<%(   L}M8HE    H`HhHpLxHǅ     )E)E)E)EI?H  IMTIHq  LHAt/HEdH+%(     HeD[A\A]A^A_]f.     LHOAuLL胀LLHL HHTA  H HHtH@(HEHMHULHH   LEHH   HEqAV  L[hM  Ip  HHB  H뚇 x   HH      H5 DLv(H5 F(    jE1E1jHHLLI^D_  HM  MNIF    Hǅ    MN Hǅ    Hǅ    I>   DL LMLIff.     MG  L/IGH0IOHt#Q(fD  rq(9t
BvH(HIH@[H H(HtH0   HHLHLIH{hLLH0}LIIF H@PIFIF DHǅ    Hǅ    Hǅ    II9FtGM~ fD  HC@HtH`HAHDDLLDLHٓ H(H9sht1Ht,HDH',HDHFHEH [LHMHUHLEDL^uQHC`DHHLMLDPHLMHZDYALD聀Ip  L[hDH AD  Hx H@H0H H(Zf.     UHAUATISHHHvdL,%(   LmI*u|I|$P uH   HQH   IT$PMt$IU HuH   HQH   IU IT$XHSPHt+HEdH+%(   u6HLH[A\A]]f.     HUdH+%(   uH[A\A]]UHAWAVIAUIATISHXFHdH%(   H]HHE    fEHE    RJAǅt+HEdH+%(     HeD[A\A]A^A_]fD  AvAVH0tHH4  x! "  xE u	HEHHuzHuLEHHLHE`HuH}EH   HuHMqH}hEHMtA:D  A}   H!} I$   HpHEI$   E   E1E1H  L@(1ID$XHD}H1AfA `@f	LRHAPMQLAH @ HA} zAuAUHrHH  E E1~!   VE u	FEHHu(yHuLEHHLHEHuH}EH   HMH}
EMHM  }    I$   HUHpHEI$   E teE1HtLH(H"  LB(     1A} sf     H   ILH(    1E1fH   LJ(LIH<fD  1E1;fD  AuAUHHMlqHHtuLmx! HHMD  H}      H Iͺ    1E1E111HMJ    E1LE1IHg|f.     f.          UHHHH7dH%(   HE1V4f;Q4tHUdH+%(   u4    f uV0I0      9r19     UHHdH%(   HE1HEdH+%(   u@ ff.     UHAWIAVAUATIHxSHhI<$HZdL,%(   LmIպ   lLx<   ID$ LsqH*  Aw:Lp@   >   LKqIH     L$8ID$A>I|$    Ht"S(D  JK(9t
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BvLmL;,   LSoAv9LHp?o<   LHC8I+oHpHC@I9sMuvH9sHulHtgLz1   LԈHC IHu^,   LnHS8H9sHuCHS@H9sHu5Ht0Hx   1芈HC I   1LqHC ILL6HEHHxLpH@ A}4 uIu IMIHI)H)H9HuL9	ЈC1I$H8=Qu H}Hu4 uHwH+73H;C tI1{1 uHEL)HC(   C0H}E\HEdH+%(   u Hh1[A\A]A^A_]D  HEHCUIHHHHLIdH%(   HEDMt*HUdH+%(   u!MH 1_q    LIfff.     UHHdH%(   HE1HEdH+%(   uHDHL Hhb 1pfUHHHHHHdH%(   HMDLEdL+%(   uL
L H 1po@ ff.     UHAWAVAUATIHSHHHdL,%(   LmEHy  w  Lq(Mj  HHEy1 	  L:,   HUL%lHUIHJ8HAH9sE1E   HR@HAL9sE1EuwE1MtoMH,   LELLMHUD]HMDUkH9ELMLEHUD]s} uH9sEuHHPLELEI@Ax LDM)AVDH LAWLEH1ToZYHUdH+%(      He[A\A]A^A_]HAHHUdH+%(   ubLEHeLH-DLHH7 [1A\A]A^A_]n    HEdH+%(   uHeEHHL[A\A]A^A_]";}fff.     UIHHHHHAdH%(   HUDHt2LI@Mt6HMH P1QnHUdH+%(   uLI@HAMuLI8     UHHdH%(   HE1HEdH+%(   uH6H?uD  UIHHHHAdH%(   HUDHueHA Ht|LILMt(HEdH+%(   uɉL1H }mD  HMdH+%(   uWILH 1RmfHMdH+%(   u/LLH-     HEdH+%(   uAHL9fff.     UHATSHHG@LgHdH%(   H]HHtLH HtDLH{HH{8H{HEdH+%(   uDHH{[A\]@ MtI|$8I|$@I|$I|$$@ UHAWAVIAUATSHL>dL,%(   LmIE'E  3LH)D  ff.     ff.     DcHEtIDB t L.IED#I}    Av9HgHt~HBI}H55 H;Ht^HHu   HSH}IE H9t<<   \gHt-HX>   HFgIHt  H#.IEA$>1HUdH+%(   uH[A\A]A^A_]L+fD  UHAWAVIAUATSH(H>dL$%(   LeI,   fH    M,$(   HLfHt0,I<$)   fH  x,  @ M,$HXLN-ID$8,I|$8H  E~;E1Et8Av<@%  E1     AHxDfHuAAEl$PH{5AAv9H{IeHEH  HXI9s5Hf     ff.     HI9tHIDA uD{C Lx,ID$D{I|$H  A^;E1t8Av<@g  D1    HxD9eHuAHEE|$2H   HS@I|$8H5 HX>9Ht[HHu   ~H}ID$HH9t<<   dHt-Lh>   LdIHt  L+ID$@A>I|$H52 8Ht\HHu   W~H}ID$ H9t=<   _dHt.HX>   HIdIHt  H&+ID$AE >1HUdH+%(   umH([A\A]A^A_]@ dHHfcHHf.     H{5HI|$8yf     UHHAUATSHH(LgHGdL,%(   LmIHI9thIIHI*I$H   Ml$HC   HH{HpHsHcCk1HUdH+%(      H([A\A]] MuHuFH   HMHHUHHHtILcHUHMH{HSRf.     Huȿ      HMHHt   ø_Kff.     UA1HAVSH dL4%(   LuI։uH5 fEf}Ht5Lޭ HIIKHf;x4      LHufD  f   Hf HH   H= H   HM5HMH   HEH}LLEH   HO H LHEL2 IHr   H5& iHEHUdH+%(   upH [A^]D  f u1DX0DӁ   A   D9tfHLIHHufr _   1댐H%    UHHW4dH%(   HE1ff>	HUdH+%(   ukff.     UHHdH%(   HE1G4fHUdH+%(   u!UHHdH%(   HEHGH@HtLMdL+%(   u      HEdH+%(   uk0fD  UHAWAVAUIATISHHdL<%(   L}EHy@ t[LDHf LL1cHKHLH{8AHEH)I4+DHUdH+%(   u5H[A\A]A^A_]ÐHEdH+%(   uHE[A\A]A^A_]/fD  UHHdH%(   HE1Ht HG@HtHMdH+%(   uD  HEdH+%(   u1     U1HHdH%(   HEHGHtPHEdH+%(   uɉ`U1HHdH%(   HEHGHtPHEdH+%(   uɉ UHHdH%(   HEHp} H9GHUdH+%(   u UHHdH%(   HEHy H9GHUdH+%(   u UHAWAVAUIATSHXH}LgdH%(   H]H+   HEx8   H]IcHEH[H]H   IfD  MLILHL<I7Tit(~INHItRI_@ MtCMfD  IGH  HUdH+%(     HX[A\A]A^A_]f     HEHX H   L.LxI   AtHHE\H   HUH]LHH-  1t	07   tD0fD7Ht07BD= H} tW    LeHEHMILHL<I7,h   IILetIGHE    HEH@HH   HUdH+%(      H}HXL[A\A]A^A_]D  HTHHEx8 HcpHxHú   HYcC8 MoLu1ƃMD5 L39rH<L1D  UHAWAVAUIATISH(HUdH<%(   H}ȿX   ID$HH   I<$I6Hǀ8    HXIDpEtAHEH}H!fD  ff.     HID3EtHIDB t Z!ID$8HtpID0I?Z1LIIt$8@ID$@HtFH@Ht1It$HHULЅx)f     HEdH+%(   uH(1[A\A]A^A_]I|$H@ ff.     UHAVAUATSH HGHby dL$%(   LeIRH@H)H Hcx$IHk8H   mH  HID$H   I|$ K H   AT$(   IT$0D   H   H  I|$u%HEdH+%(     H H[A\A]A^]fI<$H     #4HxII4IT$HAE z   D  3Hǀ8   LhLkPtCUHEUH}Hff.     ILkAU tHHDA tAE  U4HH  UHCH{UX   LHC4IH  H<HShL1H5 ChȉCh   fD  3Hǀ8 V  HPHSDhEtDHUHEHUH}Hff.     HHSD*EtHIDA t YHH   HCD(H{}WHCMl$M$$HH3L2HCH H@HHsHLLЅHC    @ t{Ha L   HIHt\H;HShL1H5ß b   LIHt%Ln;HShL1H5 ChȉChH   H]J11!UHSHHGdH%(   H]HHtH HtH{.f.     H{H7H{P.H{%H{ HH   H   H   H   HEdH+%(   uHH]Ic UIHHHdH%(   HMDu(H t!HEdH+%(   u:AHOLb!fHEdH+%(   uLOLHb 1LY UHIЉHSHXdL%(   LMIɅy/H@HH '  p  H HcH>    LLHEdH+%(   |  H]1fH   LL1Hz uX H   LL1H UX fo( H:  LMH:  LE)EfHE    )E)EeLELMH    Hg LL1W8D  H	 LL1W    Hq LL1W    H	 LL1W    H   LL1H( eWH LL1JWD  Hu)   H%LMLEHM f     UHAWAVIAUATISHHHUdH%(   HE1$H  IH@H  				LfLfn   HfHnIfp flD  o fHftfdfof`fhfofofDofqfifafofqfDofDafArfifofAbfEofAjfArfDoffArffofAjfAbffAofEbfAjfDoffArfAfDoffofEbfAjffofAffoffH9fofsffH~I9P  A<	m  HBL98  A<	}  HBL9   A<	u  HBL9  A|	l  HBL9   A|	c  HBL9   A|	uHHBL9   A|	uHHBL9   A|	uHHBL9   A|	uHHB	L9svA|		
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H&H  e  vHH  LHHhx&HHhH5/ Ƅ HI  H   f  t	9/   H9c Hx   H8  HHx     HL@7IV IFA4 u  H6^ Mf-   M1RH@ H PLx1J HM   H] L   H 0L$$1 e  ZYf  o  HAǄt  ƅg E1I} t$H^ H8HtH5 H  Hpx t	8 {  LhM   LpIFEdAtVA  AD  @HhLHx  H  HIFEdAu@    I7IOHHH)H)sS8BH    4HxHOHHx   HHhHhE5IvL$HxIV HI+VfHnAFHH$VHxH   E1Gƅg9 @ E   g    HEdH+%(   q  He؉[A\A]A^A_]f.     @HhLHxVtH}` H    JHN[ 011EoHxp蘵pg WHxCZx:     H:  Qu`HHxD  Le       HxHi    1    fD  Hx   e  ƃe  fD  LHx   HLLhc	  HhHx   Iƅg E    HxLLk1|    HQ^ Iv@fHIEHXHC HHPgIv HHXTIUHz( HH+XH$ 1HHHY    1HxuHHhHHIVLhH1HPHH9htH1uHXH1MHE    HXAHXIEIEAE(    I} LIE0    Lp>HtHxpHLH)H1HX"HhHH  DPLXH   H!LHE1I I4$HxpIO"M9t3MuI} 1   F3H HdVL>HuMDPLHL9htaHXL I$L9D  HHPfHnHxflHQH
 5I$I9u|HC01	E1uf.     f.     UHHdH%(   HE1   )  Hr HcH>H @ ff.     HUdH+%(     H H Hv H` HK H6 H& H H H H H |H pH dH XHy LHf @HN 4H9 (H  H
 H H H H H H Ho HX H? H) H H H tH hH \H PH DHf 8HJ ,H2  H H H H H H H H Hs H_ HK H7 H# H xH lH `H TH HH <H 0H $Hn H[ HJ  H6 H" H H H H H H H H Hv |Hc pHP dH> XH, LH @H 4H (H߿ H̿ H H H H Hl HZ HD H1 H H H H޾ H; tH hH \H PH DHp 8H^ ,HJ  H7 H$ H H H H׽ HĽ H H H Hy Hf HS H@ xH- lH `H TH HH <Hм 0Hv $H H H  H HW s UHHdH%(   HE1   wH HcH>f.     Hj f     HUdH+%(     H; H* H H H Hҿ H H H H Hr H |HϽ pH dH XH LHw @Hc 4H (H Hݾ Hɾ H HD H H H߼ Hɼ H H H~ Hk HZ HF tH$ hH \H PHλ DH 8H ,H  H Hq H^ HJ H7 H H H H Hݺ H= H8 Hp H} xH lH `H THp HHM <H: 0H $Hμ H Hq  H H| Hf H͹ H H5 H H H Hۻ Hǻ |H pH dH XHm LHU @H@ 4H& (H H Hݺ Hƺ H H Hv H_ HJ H1 H H9 H6 Hѷ Hb tHQ hH? \H, PH DH 8H ,H  Hη H H H H Ho H[ HH H6 H# H H H H׶ xHĶ lHU `H TH HHx <Hf 0HT $H H6 H$  H H  UHHdH%(   HE1   i  ~     wH HcH>fD  H f     HUdH+%(   F  H H H H} Hg HR H= H- H H H H |H pH dHl XHV LH= @H' 4H (H H H HT HA H- H H H H{ Hg HP H7 H! H	 tH hHڶ \Hö PH DH 8Hz ,H^  HB H* H H H Hе H HX H H H> H! H\ HG xH3 lH `H TH HH <Hд 0H $H H H  Hg He HH H6 H# H H H H׳ Hĳ H |H pH dHy XHf LH0 @HF 4H2 (H H H H Hv HU H H H H Hp H] HH H5 H# tH hHʱ \H PH DH 8H ,Ho  H\ HJ H6 H# H H H Hװ Hð H H H Hy He xHR lH? `H, TH HH <H 0H $Hί H Hb  H H Hy HO H m  H HDH BfUHHdH%(   HE1  wH HcH>f.     H: f     HUdH+%(     H H H HͲ H H H Hm H H H H |Hʱ pH dH XH LHl @HW 4HC (H/ H H H HѰ H H H Hr HY HB H& H
 H Hۯ tHƯ hH \H PH@ DH( 8H ,H  H۰ HŰ H H H Hm HY H H HǮ H H H Hw xHc lHP `H; TH HH <H 0Hw $Hd HR H@  Hѭ H Hb H H H Hy Hc HP H> H+ |H pH dH XH LHƬ @H 4H (H H8 Hޫ H H% H H H Hث Hū H H H Hx H2 tH! hH \H PH DHת 8HĪ ,H  H H Hx He HR H? H+ H H H H Hͩ H H xH lH `Hn TH\ HHH <H6 0H$ $Hʬ H H  H H ә UHHdH%(   HE1   A  HV HcH>HƬ @ ff.     HUdH+%(     H Hz Hf HP H; H& H H H H۫ H˫ H |H pH dH} XHi LHV @H> 4H) (H H H H˪ H H H Hs H_ HH H/ H H H Hҩ tH hH \H PHr DHV 8H: ,H"  H H Hݨ HȨ H H H Hx Hc HO H; H' H H xH lHק `H TH HH <H 0Hp $H^ HK H:  H& H H H Hڦ HȦ H H H HX Hn |HZ pHG dH4 XH" LH @H 4H (H֥ Hå H H H Hu Hc HP H> H( H H H Hդ H¤ tH hH \H PHz DHg 8HT ,HB  H. H H H H Hϣ H H H H Hq H] HJ H7 xH$ lH `H TH HHآ <HƢ 0H $HZ H H  Hq HG H W    UHHdH%(   HE1   Y  H HcH>HF @ ff.     HUdH+%(   )  H H H HХ H H H H Hn H[ H H |H pH  dH XH LH @HѤ 4Hg (H H H H Ht H HN H H. H H H H HС H tH hH \H PHp DH] 8HH ,H5  H H HD H H H H H Hz Hg HV HB H  H xHV lH5 `Hc TH- HHD <HƠ 0H $H H H  H H9 HO Hȟ H8 H" H H H Hۡ H¡ |H pH dH XHo LHX @H? 4H) (H H H Hˠ H H H Hf HJ H2 H H H H؟ H tH hH* \H PH DH 8H ,Hϝ  H H H H Hp H] HJ H7 H# H H H Hٜ HŜ xH lH `H THy HHf <HT 0H@ $H. H H  H H Hٛ H H
 迌@ ff.     UHHdH%(   HE1HEdH+%(   u{ff.     UIHAWAVAUATSHHHMLELMdH%(   HE1    H    lu-1HUdH+%(     HH[A\A]A^A_]f     I   ILU<IIHr  LUIJpIrpH9   L}HYILULe> H52 L   H5- L   HCHXI9toHLC1H    H}'    HEH5Ğ IIFL#LqyH{
   1HUHCHXI9uLULeABlA$H{
   1HUSD  H{
   1HU3D  L}LeI^M97t$@ ff.     HHHCI9uLӿA$    6\ff.     UHH  dH%(   HE1H t1HUdH+%(   u^@ HhHpHhtHBHu¸f.     HtHhHhHB軉ff.     UHSHLX  HHX  dH<%(   H}HH   HJ!fD  ff.     HPHpHtHHPR9r9sQHPHpHuHWfHGGHHL`     HUdH+%(   u2H]D  H), H    01T1L1Ĉ@ UHATIH   SH HudH%(   HE1ϼHuLsI$   AHEdH+%(   uH D[A\]S UHAUL   ATSHLHdL$%(   LeAmHX  fD  HtHC@A9s/H[HuL>HEdH+%(   u%HH[A\A]]ÐD9sH[D  H赇D  UHAVL   AUATISHLHdL,%(   LmIȮHX  LHt!H@ H{LAHHHuHEdH+%(   uHL[A\A]A^]s ff.     UHSHLh  HHh  dH<%(   H}HH   O$f     ff.     HPHpHtHЋP9r9sEHPHpHufHGH>L2p     HUdH+%(   u.H]ÐH) H    011L14@ UHATIH   SH HudH%(   HE1?HuLSI$   AHEdH+%(   uH D[A\]Å UHHdH%(   HEHh  HtP9s$H@HuHUdH+%(   uf.     9sH@aUHATIH   SH udH%(   HE1耬uLEI$   IeHEdH+%(   uH L[A\]D  UHAVAUATSH H}dH%(   HM1Hz  i  H1L,       H<HtrOtVE1fff.     HWJ<H}H  HI边HEHx豹H}訹HEH<D;wrH葹H}H腹HL9   HEo    H_H}HSHL9   HEH<HtWtE1@ ff.     HWJ<H}Ht0HHEHxHEHxH}HEH<ID;wrd@ H<ID;wH}觸HEdH+%(   uH [A\A]A^]&fD  UHSHHHHdH%(   HE1HG    HǇ      HH)  HH   HC`HEdH+%(   uH]观    UHAVAUATLc   SHLHdL,%(   LmIH   HtJMJ4    1EBf.     HH9t/IL HH   H< uH   tD  Dsd1HUdH+%(   uH[A\A]A^]UHAWAVAUATSH(dH%(   HE1H    t*1HUdH+%(   	  H([A\A]A^A_]fD  G,IE   D}A   IcǾ   HHEI   H   1E~x ff.     yA诟AEzH޺I   HEAIET7I   DHHHD42I   D2H9]uEAE,f.     EAE,'菀D  UHAUATE1S1H(dL,%(   LmI     AHwHHuE   Ee|DLeLy<   @ HS1H5 LxE   H5T Lx-HvHHu1LéI   1     LHUdH+%(   u5H([A\A]]H" H[    01øZf.     U   HATSH   dL$%(   LeIH`舾t"HEdH+%(   uFHĠ   [A\]D  I|$8\H`\HID$8u   ~     UHAWAVAUATSH(dL<%(   L}I  AŃ   H    HHE课HEH  E11fff.     HxHHtjH~HuMcHILMHNHVLNLF   H;LuIFH   HAHHuHEE   I  1HUdH+%(      H([A\A]A^A_]HH   HWxHEdH+%(      H(IOLMOTHI   [I   A\MGPA]A^A_]E~WLuE1IH}1L~HGH<H_H}L9HKH}J|'I 9M9uH}+|fUHH dH%(   HE1HtH}7tHL HUdH+%(   u H}HGY|f     UHSH(dH%(   HEG`tHUdH+%(   ,  H]D  H}7   H5 HHHM؅      H5 HHM؅      H5w H`HM؅      H5 H@HM؅      H5 H HM؅th   H5} HHM؅tL   H5i HHM؅t0   H5S HHM؅t1A`1     A`      zf.     UHH dH%(   HE1HtG,tHUdH+%(   u     H}H}蘉G,z     UHSHdH%(   H]HH躯H{ 豯HEdH+%(   uH{H]锯/z@ ff.     UH   HAWAVAUATSH(dL$%(   LeIHHE(I$X  HtFI LLMoI$X  HILH{-LMuAǄ$`      I$h  WHHt:@ ff.     IH襽LI$h  HLjHuAǄ$p      H}PLLpI|$fI|$\I|$RI|$0HI|$8>I$   1I$   $I$   I$   
I$   I$   I$   E$   E~%1@ I$   H<H軭A9$   I$   褭I$  藭ED$tE~01ff.     HHHI$   HxA9\$tI$   PA$   ~'1fI$   HHH<ǘA9$   I$   At$x~(1D  I$   H[HH|A9\$xI$   ҬA$   ~<E1 I$  LIHH襬I$  H{蔬E9$   I$  E1zA$   ~v ff.     I$  M1IL~&fD  HGH<H/I$  L9HIM$  I}E9$   I$  HEdH+%(   u%AT$,At$XI$   H([A\A]A^A_]釈RvfUHAVSHdH%(   HE1HA  H_H4  H5 HM
U  ;i,  H53 H-
E     H5{ H)     H5Ɖ HeU     H5q HI9  Aƃau
{r4  H5 H	'     H5 { H     H5t H     H5u HtAp   {p   {c   Hu UfD  =EJ  toH<J  {8{6ff.     HKs     Hoz HEdH+%(      HH[A^]f.     H=H dy1@ HRp     {mH D  Hy     HP {@    H5p Ht=;su{huC0	v2Hߺ	   H5,p }H p HD"Hqp H 
s ff.     UHSH(H  dH%(   HMHt HUdH+%(     H]@ MH}H5 HHjHU؋MԅH   H5o HEHU؋MԅH   H5 H HU؋MԅHtnH5hs HHU؋MԅHtMH5|x HHU؋MԅH>t,H5'q HH5MHU؅HHEfH  Or@ ff.     UHH dH%(   HUHW8HtHEdH+%(   u.Hf.     HUH}HUuH}HW8qff.     UHH dH%(   HUW|tHEdH+%(   u%ɉD  UH}UuH}W|wq    UHH dH%(   HUH   HtHEdH+%(   u.H    HUH}CHUuH}H   	qf     UHAWAVAUIATSH(fu  dH%(   HE1#  WtE11ۅS      HHI   Hx詮A9DLHA9]tEt$IcHH3I  H&  E~5 Et*    ff.     I  HH9uAEtE  ~vHE    fHU1E1AHI   HzI]H&    I  ADD4I5HID9HEHEA9Etf} x`EA;  }SHI  HUdH+%(   u=H([A\A]A^A_]ÿ   I  Ht A   1oUHAWAVAUATSHdH%(   HE1G|~WIIH   E14 H];:u9LH{tOH{AH|E9e|~1HudgHu1HUdH+%(   uH[A\A]A^A_]fD     |nff.     UHAWAVAUATSH8H}dH%(   HE1H  IH  HIXxHHc:IH   LcLHLLm	C,=H5 L%HEumLc   E   L   IE1Hc    IM9t|K|= HLGuLHEHMH   J8HDPHc   ~:HMHL  LHEHcHEI}Lyt5I L9muLS1HUdH+%(   u\H8[A\A]A^A_] IcE ~I]L4fD  HI9tH;HULuLHHMHDlUHHdH%(   HE1HtH    t.GPHtH    t2GTHEdH+%(   u,@ H  @f.     H  @-lfff.     UHHdH%(   HE1C@ tHUdH+%(   uE    H8Ht   H5j vt1?        k@ ff.     U>   HSHH  dH%(   HE1HHFH:HHUdH+%(   uH]k    UHHdH%(   HE1/? tHUdH+%(   uE    H8Ht   H5 ft1>        j@ ff.     U>   HSHH  dH%(   HE1HH6H
gHHUdH+%(   uH]j    UHAVAUIATISHdL4%(   LuI]At	<    uI4$L    u
Mt$   HUdH+%(   uH[A\A]A^]i@ ff.     UHATSHHHH3dL$%(   LeIu'Lc   HUdH+%(   uH[A\]fD  1i@ ff.     UHHdH%(   HEHȃttJ   : H(} H} HEHUdH+%(      HH}    1BgfHUdH+%(   udHHF<    1gf.     HUdH+%(   u4ɉHǾ   H| 1f     HEdH+%(   u1h     UHHdH%(   HE1Ho| VwHD H[ HHHDHUdH+%(   ug     UHSH(dH%(   H]HHuHuHHE    m~HEH1HUdH+%(   uH]øIgf     UHSH(dH%(   H]HHuHuHHE    Gm~HEH1HUdH+%(   uH]øff     UHAUATSHdH%(   HE1H~ tiII1%    H   H@AE8CHI;D$s:HLHHHtIvHuQH@AECHI;D$rҐff.     HEdH+%(   uNH[A\A]]fD  Hx AE@ HI	 HRz 101wkfH@AE \e ff.     UHMz LGHHG dH%(   HMHM: HEʋW1RDOHz H   /dHUdH+%(   uHge    UHy HAWAVAUATSHHH8LsKHuDC   EdH%(   HE1LucLcE   HE1f.     ELEwD;uDLkLMtepD   Hcy IH9 HP1AULMH}QcY^HIAuH}H&y    1-cHIfD  Hy D   IH&~ P1AULMH}bHIXZHEdH+%(   uHeL[A\A]A^A_]d ULGHx 1HHdH%(   HMHOH   bHUdH+%(   uHcUHHdH%(   HE1HEdH+%(   u	Hmxc     UHHdH%(   HE1HEdH+%(   u	HmHc     UHHdH%(   HE1HEdH+%(   u	Hc     UHHdH%(   HE1HEdH+%(   u	H=b     UHHdH%(   HE1HEdH+%(   u	Hfb     UHHdH%(   HE1HEdH+%(   u	HZHb     UHHdH%(   HE1HEdH+%(   u	H-b     UHHdH%(   HE1HEdH+%(   u	Ha     UHHdH%(   HE1HEdH+%(   u	Ha     UHHdH%(   HE1HEdH+%(   u	HHa     UHHdH%(   HE1HEdH+%(   u	H齃a     UHHdH%(   HE1HEdH+%(   u	H`     UHHGOdH%(   HUHW(f%  frRHu P1w wLODGH   _HUdH+%(   uHN` ff.     UHHHĀdL%(   LUIG@   GDLGHDYA@s浃x҃ⶃwHAPrWLV   RHt Pq8q0A,PA(P1q qLIDAD>^H`HHUdH+%(       W(Hw,H}H}LUH}VLEH})   LLEHMLEADLIHDYA@AQsWH}浃x҃V   ⶃwRHs ໃrP1APq qLIDADh]H@H%^     UHAUATSHdL$%(   LeIjH9s    I1L]HcMt9LLnxHLӱHEdH+%(   u1HH[A\A]]fD  HQs    L1\HH] ff.     UHHAUATSHdL$%(   LeIH    I1L]\HcMt5LLeHL/HEdH+%(   u-HH[A\A]]fHr    L1
\HHN] ff.     UHHdH%(   HE1HEdH+%(   u	H]     UHHdH%(   HE1HEdH+%(   u	H}`\     U1HHWdH%(   HMORDOH_q DGH   2[HUdH+%(   uHj\f.     UHHdH%(   HE1HEdH+%(   u	H](\     UHHdH%(   HE1HEdH+%(   u	H[     UHHAUATSHHVvdL,%(   LmInqKSH=mp sDCI1MtLL LhlHEdH+%(   uH1[A\A]]W[    UH H/ H/ L HHLOL_dL%(   LUIH5/ AHEAH1 HEH\ AHEH/ AVIEQ   LRHJp PLG1LcYHUdH+%(   uHZff.     UHao 1HHDGdH%(   HMOH   
YHUdH+%(   uHBZfUH#o 1HHdH%(   HMHOH   XHUdH+%(   uHYD  UHHGdL%(   LUI uY   GDOHn L߄ HHn    LP1@XZYHHUdH+%(          @u#tfGDOHVn Lsn     tSGDOHKn LPn @ H+n HL    L1WHx@ Hm     Hm XfUHW1HHdH%(   HMHORWRDOHkn DGH   JWHUdH+%(   uHXfU1HHODOdH%(   HU1DG
Hm H   VHUdH+%(   uH*Xf.     UHOHmm HAVIAUATI   SLHdH%(   HE1VHcI   tYE11 ff.     HD   LHHm MP  M  1?VHHAEII;  rHEdH+%(   uHH[A\A]A^]VWfD  UHAWAVAUIHl ATI   SHHhHOLdH%(   HE1ULcMt|H}*gHsI$`  yHEHtPH(dxDH}Hs4 uHwH+7HuHEHtLHuHyIff.     H}7KDC   1Hk LUsH{MLE   LcEHFHxnsMLEHHxH   ICE MHnHLHUdH+%(   uHh[A\A]A^A_]Uff.     UHak HAVATI   SHH(OLdH%(   HE1CTKLcftFft@ft:Hck    L1THHUdH+%(   2  H([A\A^]@ LEȋKHj 1   LSK   LAHj 1SLEIc֋K H   LH1N4Hj SK$   LHHoj I1pSK(   LHHQj I1RSK,   LHH3j I14SHK0   LHHj I1SHK8   LHHi I1RHK@   LHHi I1RHLT     UHi HAUATI   SHH(ODoLdH%(   HE1}RLcfAtSfAtLfA  KHi L1   GRHHUdH+%(   	  H([A\A]]    LEȋKHi 1   LRK   LHh Lc1QK    LHHh I1LmQK$   LHHh I1QK(   LHHh I1QK,   LHHjh I1kQK0   LHHLh I1MQK4   LHH.h I1/QK8   LHHh I1QK<   LHHg I1PK@   LHHg I1PKD   LHHg I1PKH   LHHg I1PKL   LHHzg I1{PKP   LHH\g I1]PKT   LHH>g I1?PKX   LHH g I1!PK\   LHHg I1PK`   LHHf I1OKd   LHHf I1OKh   LHHf I1OKl   LHHf I1OKp   LHHlf I1mOKt   LHHNf I1OOKx   LHH0f I11OK|   LHHf I1O      LHHe I1N      LHHe I1N      LHHe I1N      LHHe I1N      LHHme I1nN      LHHLe I1MN      LHH+e I1,N      LHH
e I1N      LHHd I1M   HIHd    L1MHLz    KHd L1   LEMK   LH~d Lc1MK    LHH`d I1Lm]MK$   LHH>d I1?MK(   LHH d I1!MK,   LHHd I1MK0   LHHc I1LK4   LHHc I1LK8   LHHc I1LK<   LHHc I1LK@   LHHlc I1mLKD   LHHNc I1OLKH   LHH0c I11LKL   LHHc I1LKP   LHHb I1KKT   LHHb I1KKX   LHHb I1KK\   LHHb I1KK`   LHH|b I1}KKd   LHH^b I1_KKh   LHH@b I1AKKl   LHH"b I1#KKp   LHHb I1KKt   LHHa I1JKx   LHHa I1JK|   LHHa I1J      LHHa I1J      LHHha I1iJ      LHHGa I1HJ      LHH&a I1'J      LHHa I1J      LHH` I1I      LHH` I1I      LHH` I1I      LHH` I1I      LHH`` I1aI      LHH?` I1@I      LHH` I1I      LHH_ I1H      LHH_ I1H      LHH_ I1H      LHH_ I1H      LHHy_ I1zH      LHHX_ I1YH   HIjI@ UHAVIAUATISH?dL,%(   LmIpxH    H1LGHcA<$TwA$H HcH>     H    L1GHHD  HUdH+%(   X  H[A\A]A^]LLHLL}HLL腹HLLUHLLEHIL$   L1H/^ %GHHk LLL蚎HRfLLUH=D  LLH%D  LLeHD  LL荥HD  LLHD  LL轖HD  LLeHD  LL-HGUHHdH%(   HE1HEdH+%(   u	HXG     UHAWAVAUIATASH(HUL7LdH%(   H]H趧IH{}HC    H;WH    LHU1Dc)HHS fK*MtyA   AtAA  H` 8    H C(gI`  D`%A       H 8    C(.HLqHCHuu1HUdH+%(      H([A\A]A^A_]@ H1 8    H C(kI`  D`%AHqHCHtEtH7SHCHS x4 uHPH+HS sf        C(HfS*VfD  Au1HK 8 tC(u!D      C(HfC*qEC(H     UHAWA@AVAUATSHH(dL$%(   LeIHMHH;I轥AHLMu9D8t4HUdH+%(   HMuBH(LH[A\A]A^A_]D  HEdH+%(   uH(L[A\A]A^A_]Df.     U@HSHdH%(   H]HHA    Ht-Hs H{xHCHUdH+%(   uH]    HC5DD  U@HSHdH%(   H]HHA    貔Ht-Hs H{PxHCHUdH+%(   uH]    HCCD  UHAWIAVAUATSHHHL-~ dL4%(   LuIA}$ c  Ht
T  AvL\IM  AT$LUBUH=Y H1qIHLA   BHCHtH@ HEHtH   ! H5X {(HHX HE    HD1H=X $qI    t L2BI   HaH  I   HtIct$TgH  I(  HtIct$5gHl  LTSHC    AFXC0C,HC    x"I  HtH   Ht
HC0E  L   A9ANąNHcȉC4HHIP  HH   IiF0  1H{HHC8I   H  Ht)HMH  H   Hx`H  H{Hs uHCI   Ht"HsH   H-<`Ht?    1HUdH+%(     HH[A\A]A^A_]@ fK* ?D  HCHtOLHHCx4 uLL+H    H}1    L^    I   Hu_HpI0  H   HCHtwLc x4 uL L+`LNeH5AL  tJI0  HzHt:Lc    HGI9rLI9薄HHu ff.     fK*fD  AVAvLUI     fK*fD  HifK*_D  HEH   H;   uH{fK*+fD  I   ^H{Hո=?fD  UHHdH%(   HE1uGuHUdH+%(   u     H1?UHHdH%(   HE1?uHWHBHHuHEdH+%(   uqHUdH+%(   u>f.     UHATSHHHdL$%(   LeIHRA$   9AD$XH{HC    C,HtHs rHCHEdH+%(   u	H[A\]F>fD  UHHdH%(   HE1HEdH+%(   u`>ff.     UHHdH%(   HE1HEdH+%(   u=ff.     UHHdH%(   HEHH}dH+<%(   uHzHH=UHSHH(HuHUdH%(   HE1GHUHuHdH
  ǃ  ǃ      Hǃ
  ǃ
  ǃ  ŚH
  fHnfl
  HEdH+%(   uH]<@ UHH dH<%(   H}   qHtH11HEJHEHUdH+%(   u~< ff.     UHHdH%(   HEH        HEdH+%(   u&<fD  UHATISHdH%(   H]H   L    A|$tHEdH+%(   u+H[A\] HEdH+%(   uHL[A\]A};ff.     UHHdH%(   HE1Hǆ      HEdH+%(   uP;UHAWAVAUATSH(H}dL,%(   LmL.L9   Iff.     M9   IU IEfInLflH}HBHAE HM>MM9   If.     IL9tGHIHLLtIIGfInLflH}IHAHAGI9uM.M9UHEdH+%(   uH([A\A]A^A_]M=:fff.     U   HSHHhH   fo)T sdH%(   HE1XHHP HPHPHt"HHG1HUdH+%(   uH]ø9U   HAUAATIHXSH   foS At$dH%(   HE1HHH=P H@H@ZHHt3H8`  H=yP D   ƀ  1HLH(  ?FHEdH+%(   uHĨ   H[A\A]]8f.     U   1HAUATIH=P SHdL,%(   LmAH5 HH= w3HǾ      HD   HLƃ  EHEdH+%(   uHH[A\A]]28fUHAUATSHdH%(   H]HH9tJII
fHI9t8{uH(  L#uHEdH+%(   uHH[A\A]]f17    UHAVAUATSHdH%(   HE1HtKIIHE1fff.     H3LEHtH   u6HSH  IHM9u1HUdH+%(   uH[A\A]A^]ø7@ UHATI̹   SHHHHdH%(   HU1H= w4L  HHD1HUdH+%(   uH[A\]     6@ UHSHdH%(   H]HH Ht赣HC     HEdH+%(   uH]C6 UHSHdH%(   H]H H sHCH   CuqHHCH;BuԋCps;s}kHHCHz FH{ fCHtUsHC    HSH   CtfD  HEdH+%(   u"H]HEdH+%(   uHH]Z5f.     UHAVAUATSHH H~ dL,%(   LmIAfCCfCL+C C0IE L9  HE    A      MeM   L  Me M9tl I$  tOA|$#  A$   u8H}no  AD$0   L~L9   f.     M$$M9uH}޲IE f.     HCI} 1葏H{ fCHtTHCsH   C   HEdH+%(     H [A\A]A^]@ I$   H}'HHEKmH}Ȅ   :I$   H}ɡM$$M90    I|$	H}Lc(LOuLc IE fD  SDHEdH+%(   uZH H[A\A]A^]}0D  I$   {HEf1LVf uH}ll2fUHAUATSHHXdL,%(   LmAHH}E9Eh  EuhH}/E9E}oH}H9   uH    t؃   u/@ H    tu/H}/E9E   H}H;   uf.     HH9uS     ƃ  HEdH+%(      HX[A\A]] H    tx   ƀ   H H9tH9   uf.     H	7 HH9u$ff.     ff.     H H9dH;   uH    tƀ        Hx	qsHH9$Ete1D  UHHdH%(   HE1HEdH+%(   u10f     UHAVAUATSHPdH%(   H]H@  AH}H	E9E   E1     H}-E9E~?H}   uH9   uH    t  A	D9uuȸfD  Et+At%HH}A   胷E9Eff.     HH9uQ     ƃ   HEdH+%(   O  HP[A\A]A^]f     H    tƀ  H H9tH;   u@ HH}E9E   E1E1     H},E9E}GH}   uH9   uH    tσ     A	D9uu讷@ Et#AtHH}A   kE9E HH9H9   t ff.     H H9H9   uH    txtƀ  fH	` Hx	ur.fUHHdH%(   HE1HEdH+%(   u1~9.f     UHHdH%(   HE1HEdH+%(   uɾ   ;-fD  UHAWAVAUATSHhdH%(   H]HH  IH}H3E9E   ǅ|    E1;     LLtA   u	M9   t.H}*E9E}ML}AuI	uf     I    tA  A	;|uuL踵fD  Et+|t"HH}vEǅ|   9E@ HIH9u'F LLEt
M;$   tgM$$L9tA|$uI|$	uM$$L9uD  HHH9uS H H9tHH9   uH    t倸   uܸ   'D  I$    AƄ$  | 1  HEdH+%(      Hh[A\A]A^A_]fD  HH}tE9E   E1E1H}G)E9E}?H}   uH9   uH    t  A	D9uu8fD  Et+At%HH}A   E9Eff.     HH9u$#     ff.     H H9H9   uH    tƀ  + UHHdH%(   HE1HEdH+%(   uɾ   *fD  UHAVAUATISHPdL,%(   LmIHH}E9Ez  Mu.j LHt	H9   t`H}'E9E}oH]{uH{	u@ H    tu'H}'E9E   H}H9   ufH    tuH'f     I$I9u'ED  LHUt	H;   tXHI9t {uH{	uHI9uff.     AƄ$  HEdH+%(      HP[A\A]A^]    H    tƃ   D  I$I9ufff.     HI9tH9   uH    tƃ   @ I$I9kMB(ff.     UHHdH%(   HE1   tH҆ HUdH+%(   u HY͆ (fUHHdH%(   HE1HEdH+%(   uE1   1Ea(UHHdH%(   HE1HEdH+%(   u	}((     UHHdH%(   HE1HEdH+%(   uA      13E' ff.     UHHdH%(   HE1HEdH+%(   u`v'ff.     UHHdH%(   HEH냵FaHH8HD`Huf     H HtH9puHUdH+%(   u,'ff.     UHHdH%(   HE1Ht xHtH@HUdH+%(   uÐ1&    UHHdH%(   HEH   @:   VLFHH	   Hc  H9   H)IHtIH냵FaHH8HD`Hu+ff.     H HtH9PuH@ ff.     HUdH+%(   u7    	uVLFHHHc  H9}	Ip1%D  UHAUATSHdH%(   H]HH  Ht3S0~lE1E1@ H  I   LARD;c0|H  Ht4C0~-E1E1D  H  I   LARD;c0|H  ZHEdH+%(   uHH  [A\A]]_Z$f.     UH=G< HHdH4%(   HuHu[HӇ    xE
)
1Ht	HPHuHUdH+%(      ÐHHH H|         H HHH9HCCHH9ЍqCHHH9H?HC֍qH9и   CH4    HCHH?)H[H0      Hx#D  UHHdH%(   HEH9t=1HuHUdH+%(   u1D  HWHuH҇ HGH@ Ha#UHATSH   dH%(   HE1H  IHH5I LAHG  H$҇ 
HHDHH!1HIM   ?   HH?qA   H9CH4    HCƾd   H?Hч IMHHMHHh~$Hņ M1HhH8 01gLH    D#1HUdH+%(      HĐ   [A\]f.     ID$ItHH    H       HH0   HHH8uHHH<HLHx
   lIHx8 f     HĆ H7 101g$x!w/   ?   WfUHHdH%(   HE1HEdH+%(   u
H\b'!    UffAnH+  fHnHHAUAATSHHxfnUfnMdL$%(   LeA)E)Efb)E)EfAnfbHEflE~X  fl)pHÆ    HC8H12H7 eHs8H}DAiHHUHpH@HUdH+%(   uHx[A\A]]'     UE1E111HHdH%(   HE1j j)HUdH+%(   uff.     UHAUATSHdH%(   H]HH9tbII
fHI9tPHX  HtHt"u@Hh  H9h  tI] HUdH+%(   uH[A\A]]D  1@ I] 5D  UHAUATSHdH%(   HE1Ht_HIIH9uKff.     HI9t8{uLH觇tHUdH+%(   uH[A\A]]f     1ٸUHAUATSHdH%(   HE1Ht_HIIH9uKff.     HI9t8{uLH7,tHUdH+%(   uH[A\A]]f     1ٸUHAUATSH(dH%(   HE1HtkII1H}Hj5    蜲xm1HI9t=EHMH}1H65    nH}ȅx6HEHHEI9uHEHUdH+%(   uH([A\A]]f苙1RfUHATSHdL$%(   LeIHH0HHLhHA=HEdH+%(   uHD[A\]fff.     UHATSHdL$%(   LeIHHv0HHLHHA͘HEdH+%(   uHD[A\]}fff.     UHH u   dH%(   HUHU_HUdH+%(   u0UHHdH%(   HE1   tD  1x8  x.HH9u:f.     ;  uH H9t ;  t1HUdH+%(   uD     @ UHHdH%(   HUH  Hu.HH9t&     ff.     HP(H  H H9uHEdH+%(   uH4@ UHHdH%(   HE1HǇ      HEdH+%(   uU%U1HHdH%(   HEHH9tfff.     HPXH H9uHEdH+%(   uHff.     UHAVAUIATSHL'dH%(   HE1L9u0j       ff.     ff.     M$$M9   AD$ZtA$@  LDpdD  I] L9u14D  CZtI$(  H(  &   HL9tI9uы      HcHiONH#)ȉk)AA$H  1ɅurA$I  m M$$DM9>A  HEdH+%(   unH[A\A]A^]fD  H  fA$H  J  A$J      AƄ$J   H/fAƄ$J   NA  fA$H  s1|     UHAVAUATSHdH%(   H]HLc0Lk(H9tHIM3     Hٻ L   H/ 01^HI9tLC0M9uHI9uI   AAAEHUdH+%(   uH[A\A]A^]2fUHHH?dH%(   HE1G:uHEdH+%(   u"1f     HEdH+%(   ufD  UHHdH%(   HUHHH9t,J:fD  H H9tP:1ʃt1f        HUdH+%(   ueD  UHHdH%(   HEH@:HUdH+%(   u$@ UHH dH%(   HE1t?Ht:H}hH}HtHP%fHEH}HUuH}    HHEdH+%(   uH@ UHHdH%(   HE1H  HEdH+%(   uh     UHHATSHPdL$%(   LeIH}赝E9E|; ӳH}E9E}"uH}u߀   tYuH}I\$I9tfD  H(HH[I9uLo)HEdH+%(   u	HP[A\]fUHATSH dL$%(   LeIH(    I$I9tfff.     H踅HI9uLVI$I9u]D  HI9tPH   H   HyLUj$U؉ىHEdH+%(   uqH [A\]Ð1@ I|$ V HHt:kHt(HHLHEzH}*hH2H%gvfD  UHAWAVAAUIATMSHH   HdL<%(   L}E1Ǉ  H )H(k)Y     Ea  1   B Z>,O>(   1   8H5+    1}$>(   HsPÃ@  蘡     Mt3H8   L1HH0
   L0E   yI}    $=(=    HOH,      1O,   8=1HUdH+%(      H   [A\A]A^A_]Ð      1G@ I}  PA}  EI} :H{(Ht`  15@ HH>艀Mx+-
   HډuA#H/ A  H
I Hc(    H81d(9<,.< #<$< ff.     UHH dH%(   HMH  y1HEdH+%(   uRɉD     HuHME jHM̵  UHM;HMUǁ  fUHH dH%(   HUH  x+HUA;HUHuǂ       |HEdH+%(   uyf     UHATISH dH%(   H]HHu4HtqHuHH(uHԸ 8 uHEdH+%(   uHH [A\]D  Hs HtLUaUHtŋH,   @0   밺 UHH HUdH%(   HE1Hu(4Ht HMdH+%(   HuHUuH(HEdH+%(   uɸX     UHAVAUAATISH dH%(   H]H˃   tI   +HZ HLD(1$HEdH+%(     H 1[A\A]A^]fL7HuH=& ExHcEI9F rEǨMHL    MF H& 1趚@ 蛨HT% HLD(1蔚AcIcHHr& H)AL1oAAFIcHH% 1H)LLH% AL 1HcH)I<DH) @ IcHH% 1H)LAff.     UHAVATISH(dH%(   H]H˃tGu诧uHێ L0H1覙HEdH+%(      H(1[A\A^]fD  Lw8HuH=$ \DWI
MH    EH% L1CMAD9~(IcHV& 1H)LHsf     HcHމEDH)H% L1DEAfUHAWAVAUATSH8HdH%(   HEHEfHnHEfl)EH9   IH9t}L;ID  M9tJILIHVLIVI9uHCHHuHAHHEH]H3HCHM9uHEH;EtIU HMLhIE HHJHEdH+%(   uH8[A\A]A^A_]D  UHHdH%(   HUHH9t3H"@ ff.     ff.     H H9t   tHHEdH+%(   uHS UHHdH%(   HE1   u'HH9t@ H9t+ƀ   H H9uƆ  HEdH+%(   u@ HH9u
UHATISH dH%(   H]蚩xtDLHHtHLHE%HEHUdH+%(   u2H [A\]f     Hx	utHLHE6HEK
ff.     UHAUATSHdH%(   H]HH9t+II@ H(   tLH{u
HI9u1HEdH+%(   uHH[A\A]]	ff.     UHSH(dH%(   HEH  Ht*  HAE  w3     fHEdH+%(   s  H]    u[uǇ     w0~1H  Hi   |x11	$@HMX[us0HMH9 އ    D  ffD  Ǉ     w0K1    H  Hi   |x$1   	$@HMZs0HMH9f     Ǉ          Ǉ          Hq uغ      H=0  H&DE݇    D  UHAWAVAUATSH(u@UdH%(   H]H  HD  Ht9LceMi   N<#HEdH+%(      H(L[A\A]A^A_]D  IHc0Hi   u<IHtAT$0~>EME1E I   UHHLLA=3E;t$0|ր} t A$  M$  tLC@ M$  fD     L}ff.     UHHdH%(   HEHH9u%fff.     H H9t@8 u1fD     HUdH+%(   uMfff.     UHSH(dH%(   H]Hn%tHEdH+%(   u'H]D  HHHEgHEƀ  @ ff.     UHAWAVIAUIATSH(UdH<%(   H}H-PH    H(  IH E$   01JM>M9tg   >Ljt*E tLEQ]LL"IAƇ  M?M9t"LM9uLrjÄt1     A$   uAǄ$       HEdH+%(   uH(L[A\A]A^A_] UHAWAVAUIATSHH(HUdL4%(   LuIHE     ?f      H5 HAą  C  <,  H{aSHH  ,   HXIH      1H誦  AE AA    H   fdYDgA:JL1HuLeAE LmM9   ,   HǋHt7I9   I1HuL'HMHEI9   8    HEdH+%(      H(D[A\A]A^A_]fD  1 Hx5AE A!I1 L蝥xLHMfD  HH< 1D H 01AAH@ ARH楆 LH 101H謜D A|AUHH dH%(   HE1: uHEdH+%(   u2     u,uxHEdH+%(   uɉ,
f.     UHSH(dH%(   HE1tOA   1ҹ   uH}H}؋uԅ
  xA
  
  1HUdH+%(   uNH]Hɤ H    01FH H Ǉ
  101FC UHHdH%(   HE
  HUdH+%(   ufD  UHATSHLgPdH%(   H]HtBHc
  11AHc
  fATHc
  fALǃ
  Hǃ
  HEdH+%(   uH1[A\]s  UE1HSH(dH%(   H]H
  t   H5 脛AtHEdH+%(   u5H]D@ EHF H 1
  01nEDE UHAWAVAUATSHH   Lc
  LoPdL4%(   LuIE1Ʉt$Od AD$ftu:  1fAD$HEdH+%(     HĈ   D[A\A]A^A_]fA    fE1)E)E)E)E
     H{<A@  {<
X  P  BD-IUI>  H H`0HE   Lr A?   HhH1H= (DHh   H5B @}  A   EE~vA%          EHUg  < y  H`H 101CAAPv  AD$sHDhxDh`f.     u"h    E1Ƀ   H⠆ H`H`0I?{
H L    LDHEH D\HhH1BMD\fLID  HY 
  H 10H`1zBDhSfD  Hh   H5 {  A   ;@ H`H    Dh01BADhjD  AwHDh?AD$Dh    Eƅ ǅ{    t=< f}-v  f}-g#  f}-F} ƅ{L+E1L9s H1 LH{HG5Mm L9uAE1 Hh   H5\ Hz   Hh   H5T (zuJA        EHUH(H`H 011@lHh   H5 y   A   }H`A      H 01[@UHH`H 0LjH߉hLH   hLHhH   HhL H(  H`H] 101?AE13Hh   H5@e xA   } ƅ|/NHhLx {} ƅ}H`LH 101:?AE1f.     UHAWAVAUATSHhH}HudH%(   HE1t01HEdH+%(     Hh[A\A]A^A_]f.     HEIԺ
   HLHEdHU:   HP   H9  H}G(uff.     A<$ %  MLeLmE1LH5 L}
    I1MHMLH	<  E9E  HcMHIT$H5 ; u(   LLeHU-HEH  H}   8HHEHxH  A<$ 5  HUH]E1H5D Lm   MIHx ILEHU1HML>;   EU9   fnfnHcEfbfC   uC9T   IH5 1A}  uHxL9}   H]      HS=C   H}   1҉A   HEH   H}H8H
  H@H} G(f.     HE@(     HEMHx;,MH}MrMV@ HѐH 1Hߙ 01M<M롋xM!M둹mfD  UHSH8dH%(   H]1Ht^HWf1B+HG    HcЉ)EHiMbH&)Hci  HM1)HUHHi@B HE_x!HEdH+%(   u6H]f.     ۏH 1H阆 01;    UHHPdH%(   HE1Ht!HHcW1HH@PHPfpu1HEdH+%(     ɉfD  LG H?HMLEA   ғLK 11H A1LMt:HMLELMHALHHPH9  IPHHH9oHqyfLMȋB+HQ 1HcЉ)EHiMbH&)Hci  HM1)HUHHi@B HEr^1LMȅLMkLMH 11A1ىM9MD  LT 11H A1LM}9LEHMLMIPHAHHH9D  yf11)EHUf)E]LMȅx   QfD  A1H 119~ ff.     UHH dH%(   HU1Ht8HH?Ht-HHE(HUdH+%(   u"H}(    HEdH+%(   ufUHSHdH%(   H]HH
  H
  諎H  (H  (HEdH+%(   uHH]fUHAUATSHdH%(   HE1H   I]LwL?HI<$I9t8H HGfHnflHCHHǇ      9I9HHuAD$    L}%HEdH+%(   u0HL[A\A]]n@ HEdH+%(   uH[A\A]]f     UHAVAUATSH  dH%(   HE1vH      IL5 yH
 LD1J     HL   1AV   L
    Hc>HL)ZYufHF]HHuLA}~&I] I9tff.     H10HI9uHEdH+%(   u#HeH[A\A]A^]    Lq1    UHSHdH%(   HE1_Ht2HHuHEdH+%(   uHH] Hxq1/@ ff.     UHHdH%(   HEHH9u5fff.     H H9t 9   uHUdH+%(   u    1@ ff.     UHAWAVAUATSH(H}HUdH%(   H]HH9Y  IA   E1   f     M9   M   A   ~}   LG{E   HEI;D$   A   ~{   L{HMMjHI"ILLE1H HH9]   H\9Iƃ{_H{	tM9X@ ff.     EtHEI;D$r(M9hzf,   LzHEI;D$sHEdH+%(      H(L   [H5 A\A]A^A_]3  Mt
A   !HEdH+%(   u<H([A\A]A^A_] HEdH+%(   uH(L}   [A\A]A^A_]yUHAVAUATSHdL,%(   LmL/L9   I    Mm M9tL8IL9tH(  HtH5 IHtL@ ff.     I9$  tL9   uHH"bǃ       HHuMm M9u    HEdH+%(   uH[A\A]A^]@ ff.     UHAUATSHdH%(   HE1HtcIHiIHtPI$I9t"@ ff.     HL}HI9uHEdH+%(   u0HL[A\A]]j@ HEdH+%(   uH[A\A]]9f     UHAVAUATSHdH%(   H]HH9   H  II+D  D'H  HI9   H;  uHtux uI$E1I9tC HL(HA	I9uEt%I$I9tff.     HrHI9uHEdH+%(   uRH[A\A]A^]@ HI9tH  HyHI9YHI9t@ ƀ  H I9u
f.     UHATSHdH%(   H]HH9tLI    HI9t8
      H6VtHUdH+%(   uH[A\]f.     1    UHAVIAUATSHV#dH%(   H]HtS HsH;IH   {" uxH{    L=*tiH{PgIM   H{ LLLAFPLhLl=1HUdH+%(   uiH[A\A]A^]fD  {# tK3IfD  H; q{  uH{Hn{! dOL<]fff.     UHHdH%(   HEHH9u-D  @8 tH H9txuHx	t@8 u   1HUdH+%(   uf.     f.     f.     f.     UHAWAVAUATSH(dL$%(   LeI   AuE fff.     A$
  E  AD$0   E    E1E1fD  EI   EA9D$0   I$  LH<u fD  H0  LHA   |H>HIHt>LLkHtH(  HuH H 1011-    HdS E} HEdH+%(   u0H(1[A\A]A^A_]þ  LcAT$0AUIHAUIATSHH(dL$%(   LeIF*tHsL%uHt`L(  HHL0  '1HUdH+%(   u=H([A\A]] H HuH6 101+,LEAH*됸@ UHHdH%(   HEHH9tS ff.     ff.     ff.     ff.     H8 @ @@   H(  H0  H H9uHEdH+%(   ufD  UHAUATSHdH%(   HE1H   H?/u<{eL#L9u        M$$L9   HS(HsLyHfHUdH+%(      H[A\A]]@ {7L#DL9t#@ ff.     LDE%M$$L9uH&Z    ǃ
      1H
  HH;V_1e    H3o<L#L9u멐M$$L9tLtUHSHdH%(   HE1Ht?Ǉ
     H1H
  t<HEdH+%(   u*HH]e     HEdH+%(   uH]&fD  UHHdH%(   HE1HEdH+%(   u1fff.     UHHdH%(   HE1HEdH+%(   u@ ff.     UHHdH%(   HE1HEdH+%(   uIH1H    W    UIAHAWI1AVAUDHATDI*  SHdH%(   HE17IƉǉEx:Ad$(HEdH+%(      H[A\A]A^A_]     AL$( 1ҿ*  1MADL7IƉǉ!EyAL$(@1ҿ*  1MADLY7IƉǉEZAL$*MD1AL*  1!7ǉ) ff.     UHAWAVAUATSH   H$ H(IAALEdH<%(   H}H=c H   HAUI      At$A$L> P1.H H5? H}HgA$MD$HHE1H    1DH H߾   1DH H߾   څ1AH H߾   1   HH mH1   HH HoA$1H H߾   &MAL$1   HHW *IL$1   HH= IL$1   HH' IL$1   HH IL$ 1   HH wAL$(1   HH PwAL$(1   HH 'NAL$(1   HH $AL$(1   HH AL$(1   HHq ЃAL$(1   HHX AL$(1   HHA U|AL$(1   HH& +RAL$)1   HH +AL$)1   HH AL$)1   HH ؂AL$)1   HH AL$)1   HH ]AL$)1   HH~ 3ZAL$)1   HH] 	0AL$(1   HHB AL$*1   HH' ށAL$*1   HH AL$*1   HH cAL$*1   HH 9`AL$*1   HH 6AL$*1   HH AL$*1   HH AL$+1   HH AL$+1   HHn jAL$+1   HHW @gAL$+1   HH@ =AL$+1   HH% AL$01   HH AL$41   HH IL$81   HH IL$@1   HH aIL$H1   HH >eIL$P1   HH BAL$X1   HH H(1HUdH+%(   uHe[A\A]A^A_] UHAWAVAUATSH8  HHdH%(   HE1
H"H  ǅ    IĐff.     LcH  xuP0	wHXH3H=   wHH    1HeLT   H1AǃtIH  @ L8cHK  x
uHp   HD!hHx̺   H5T HH9HF}WuHHK    HdL1H14ǃi   HrHHH0Ƅ t7HHff.     ff.     8 u  HH9u   HcHH1LH IH)HcADLLLaHff.     L(HEdH+%(   u?H8  [A\A]A^A_]HHH 1cIED1 ff.     UHAUATSH   H$ H(dH%(   HE1#H;H  H@ ff.     H`H   xuL`x.uA|$ t׀x.u!AD$.   9uA|$ tf.     H     MHH1bHHHSiHH= 	   THABRE9A   H
HEdH+%(   uH(  D[A\A]] E1E1f     UHHdH%(   HE1BHHH   tHHHQ @ǀtH@IIAAEHQX   tHHHQ(@@tHHHQ @tHHHQtH @u%H QAHEdH+%(   u     HȉH ff.     UHAWAVIAUATISHG8dL,%(   LmIը uAP	  IuI~k   1L= L`XAD$8  HcD           L=v Lu   L1H)Lo`AD$8@uHcLh   L1H)LJ`AL$8    AD$:	     A:HEdH+%(   o  H[A\A]A^A_]f.     @u      L= tfD  AL$8           LL9 1H)H L_AD$:uuL=m VHcL1H   LH)L[_AD$:/HcLG   LH)I<11_@ Hcku    L= t@ AD$:t.IuI~G   1H ^fD        L= 'eD  UHHdH%(   HE1HtH;=9 r2H=0 HtH5, HtH( 1HUdH+%(   u	øf     UHSHdH%(   H]HHtH HUdH+%(   u#H]ÐHEdH+%(   u{H]@ ff.     U 11HHdH%(   HE1D  ff.     ff.     HH@u    HUdH+%(   uUHHdH%(   HEHG(   ut@tyHHHƃHHHHH   HɃHDΉ    HEdH+%(   uD  1ҹ   պ^ ff.     UHHdH%(   HEHG(HtHEdH+%(   u( H	   HG(HEdH+%(   uU@UHHdH%(   HEHG(uHEdH+%(   u-fD  փ   H!Hw(HEdH+%(   u? ff.     UHH dH%(   HEHy x tW<@t⿈W<  x tW8   x tHgXx tHg0x    x tGl   x tg;Gl    x tH  x tg:H  Ht	    uVx tHgX?x tG8udx	 tg;߀x
 tg;x tHgX8 tg:HEdH+%(   unÀg:f.     G("W8 Hg0땐g<     @  H}BZH}   DHw H}@ ff.     UHSH@@   dH%(   H]HHt6   HYHK0HEdH+%(   uH]f.     Y@ UHHH(  dH%(   HE1HtH= aHUdH+%(   u2fUHAUATISHHdL,%(   LmA$H= E  HHǃ`  Hp  Hr Hǃ      Hh  H  H  H  HX  Hǃ      fHnHh  fHnflǃ  flX  h  j I|$nH߉   <ƃ   Hǃ      ƃ   Hǃ8      ƃ   ƃ	  Hǃ  
   ǃ$  HEdH+%(   uH[A\A]]@ UHAVAUATSHdL$%(   LeL&L9tpIIIEL+I]HCHM$$M9tM(   KHHtaAo$ AoD$@ID$ HC { tI|$vHt'HC 1HUdH+%(   uH[A\A]A^]HRGfD  UHAWAϹ   AVAUIATIH8SHH   ,dH%(   HE1HE    Hǅ4    Hǅ0   HǅH  H= H   L(  HM1LHC    L1_   LqH@  H   LYHH  HtuH0HH ;E   H,H HH8Hǅ@   HEdH+%(   umHĸ   H[A\A]A^A_]@ IL	H@  HH  HLE@ LL5iHIą__@ ff.     UHATSH dH%(   HEHn HHtmHIH%H1HtH9t(z,t"HUdH+%(   u?H [A\]f.     LHU#HUH,	 1@ ff.     UIHl HHHGdH4%(   HuHH	wHYl HH9 HHDHEdH+%(   uHW L1fT1U@H HHdH%(   HE1   HH#HUdH+%(   ufU@IHHHH=n dL%(   L]MHu;HEdH+%(   us@H LLHHn L@1S@ HEdH+%(   u8@L1HHHl H5n L
LH LYS$@ UHAVSH   dH%(   HE1H   H(  HHt'HUdH+%(     HĠ   [A^]     OwH HcH>      gH`   H H1IRfLH(  Hq     H ]@ DGDHOH   1Hy H`D\L`@RD\A  A  A9  Hcɺ   HH)I4]D  HGH HwHn HH HHDL`H    L1QH   HH)I4fD  H Hi    1H`L`hQ HG<   HH  IH2 IA  H    H`1L`QHc   HH)LPHOL`H 1   LPf.     H    H`1L`Pf.     L`   LO    HA 8@ Hc   H DXH)I<1\6P\DXfH   H DXH)I<1\O\DX Hc   Hn \H)I<1O\Hn xLPX\_Hb KPXH`A   \IO?D  UHH dL%(   LELP  MtHEdH+%(      L HuH@  LEHt/HH  HU+LEHUH= w'HP  I zHUHULEfLEHU\HUHP  H؉=He 1H12H LE: UHH HudH%(   HE1L=HuH0VHUdH+%(   uD  UHH dH%(   HEH  HtHUdH+%(   u9f.     H}H}H tHEdH+%(   uSb^ ff.     UH HHdH%(   HEH0  HHDHUdH+%(   uff.     UHAWIAVAUATE1SH(HudL4%(   LuI<ZA      LA   D  I9  tiL9   u`Hwh x) t
  tAH;EIcLIHa H HEH: H)1H}E1yLAHHuA   tDHEdH+%(   uXH(D[A\A]A^A_] H}HH} L1(LA2H}IcLH H)H1LAȿ     UHǰ  1HHdH%(   HEHH9tfD  ;pHDH H9uHEdH+%(   uHh     UHAVATISH   HdL4%(   LuII$  HHx8kHt&H Hf  Hv HcH>@ HEdH+%(     H[A\A^]fL   IĐ   ,1HtHpHSH   HЅ  H A0       HH  HDADIyA   DHHMHDǍyIADHHMHDǍyIADHHMHDǃHȃ HH?tHHH!   HEdH+%(     HH{LL[   A\A^]L   IĘ       L   If.     L   IHf.     L   IPf.        H A0       II  IDADIDIA   ADIIMIDDIIAADIIMIDDIIAADIIMIDt'HD  A   1j Ar     A   1HEdH+%(   u#H_ H 10H1[A\A^]<ff.     UHAUIATISHH  dH%(   H]HHx8IH   Hx    H f   H5\ HcH>fD  I$   Hx1fff.     HHEdH+%(      H[A\A]]D  I$   Hxw1 It$Hxb1fD  It$HHxJ1fD  It$PHx21{HT^ H 101 1VfD  H)^ LH_ 101T ͺfff.     UHHdH%(   HE1HEdH+%(   uɾ @  F膺fD  UHHdH%(   HE1HEdH+%(   uO@ ff.     UHHdH%(   HE1HEdH+%(   u@ ff.     UHATSHdL$%(   LeIHHt2I$X  H5I$X  1HUdH+%(   uH[A\]ø薹fD  UHSHHX  dH%(   H]HHtOI1H}   H N~QHX  m5HEHX  1HUdH+%(   u0H] HEdH+%(   uHH]!@ ff.     UHSHHX  dH%(   H]HHtOI1H}   H& mM~QHX  4HEHX  1HUdH+%(   u0H] HEdH+%(   uHH]!@ <ff.     UHHdH%(   HE1HEdH+%(   up4ff.     UHSHdH%(   H]H>uƃ   HUdH+%(   uH]詷f     UHHdH%(   HE1HEdH+%(   ukff.     UHSHdH%(   H]Huƃ  HUdH+%(   uH]f     UHAUATSHdL$%(   LeL'L9tfI$IfIn@ L 3fHnL9tBHIHID$flHCHA$A|$ tI|$L2fHnI9uHEdH+%(   uH[A\A]]eD  UHHdH%(   HE1H= HEdH+%(   u(     UHHdH%(   HEH  Ht^H@HcHcH;pZH;P ZH0oHPHT(Ho oAHP@Hq Hp oH)QfHEdH+%(   u臵    UHH0LOdL%(   LEDGA9I9    I҉tu-Et@At:uH  Htx tL9  fHEdH+%(   uLɉD  LUЉuH}؈ULMMCUH}؄uLUtDMM9u} t   谴U
      HSHdH%(   H]H u 1HUdH+%(   u.H]f     H5 H+tC)<ff.     UHAVATISHH= dL4%(   LuA HHtxDLH
      HXtI|$ ufo C 1Ҿ   H1tMHp  /H=N Hp  H Hh  HEdH+%(   u)HH[A\A^]       HuC UHAWAVAUIATSHHdL$%(   LeAA   L   L1,  A   #  IM0   I  HcHJH;A6  IcH;Q )  HHQHD(HHEdH+%(     HHDL[A\A]A^A_]Ef.     HEdH+%(     HHDL[A\A]A^A_]fHEdH+%(   V  HHDL[A\A]A^A_]fM  I  L@ ff.     H9tL9   u     H Hu݃LIHcM  M9     Iv8H  I   LcL;pu  McL;x h  H8HHIIH|(:  HuHuH  HIc   I  HELff.     H9tL;   u  H H)HuH;U  IE0HHMHNtHNHvHuHƃHutH1HHuU  E1  q    Hu~E H@     HpH  H@L;puUL;x kUHpHIIHD(AD;EA  I  HHqDEHMHH  H  HMDEH@L;p  L;x   HpHIIHT(HЀ   .DH}HMDEhH}H  H@L;pTL;x TH0HPHMDEIIHD("HEdH+%(     HHDL[A\A]A^A_]bfHIσGEA   A      Ic   DDLD  H9tL9   u  H H)HuDBTHc    HEdH+%(     HHDL[A\A]A^A_]Jf.     1f     A      ZHQHu~E HpHP H  H@L;pESL;x ;SH0HPAIIHD(D9E  I  HHqDEHMUHH   H  HMDEH@L;pspL;x sjH0HPIIHT(HЀ   6DH}DEHM@H}H  H@L;p|RL;x HMDE/eR1@ 1v[G HUdH+%(   uaHH[A\A]A^A_]f     f     %        1@ HHUHHtIF8HU>¬ff.     UHAWAVLcAULcATSHHdH%(   HE1H   HHHL;pQL;h |QMHAIHpDmIIHL(  H      L;h QQH0HHIIHHu|(H   UHMDLu1H}I$  H@L;pPL;h PL0foELhLBD((foEBD(8HUJT(H1HUdH+%(   ucHH[A\A]A^A_]fD  {E D  HUx*I$   HUL;p	_P     땸fff.     UHAUATSHD  dH%(   HE1E  G8  H     u	Љ  S8L-M 	H C8HES Au 8   11A} H S     L-Q LhR H 1   II} ΨIM       H= I} Hs1HSNI}    1LR H I} %	ЉG8E1HEdH+%(   u'HD[A\A]]        1!zf.     UHAVAUATISHHHdL,%(   LmIoAHR x t
C;   x uM   M   H      H'ukHǃ     Hx   tHǃ     HK1HUdH+%(      H[A\A]A^]f     {; w    DLHHx  HHHH  uf.     L%~ M*Ht~ IHUfD  H=H~  H1~ HfD  L DH߉cħ@ UHSHdH%(   H]H   u*HGHEdH+%(   uHH]鶬fD  HȩaUHHH!H?H	HHdH%(   HUHH=H	HH;H	HH9H	HH(% H	HH%   H	HH%   H	HHH%   <H	H      H!HH	HUdH+%(   u触    UHH`  LG(dH%(   HE1A   II҃>	}   H(   HAA:uHUdH+%(      D  A
  HHHHǅLǉBHLI1D     VHH9rGHFHA   HDAHFHEAHFHEHI1SD  D:@ ff.     UHHdH%(   HUHW(HHHE@HEHEHE   HEHUdH+%(   uUHH HudH%(   HE1HtHUdH+%(   HuuH+ HEdH+%(   u1蠤UHH HudH%(   HE1HtHUdH+%(   HuuHK) HEdH+%(   u1@UHSHdH%(   H]HHHtHp8P(H   @u"HcHHUdH+%(   u0H]fD  Hc<9   tP,f.     跣    UHHHcG(H   dH%(   HMыW,tR t[u>HfHDu#H HHHEHUdH+%(   u" 1@ ɉD  fD  UHAVSHHdL4%(   LuIHHt1HUdH+%(   u<
  HLH[A^]阿     HEdH+%(   uH1[A^]葢UHAVSHHdL4%(   LuIHHt1HUdH+%(   u<
  HLH[A^]     HEdH+%(   uH1[A^]UHAVIHAUATISHdL,%(   LmIH   H=w  Ht	H9w tH(Hw HtlHw LLLR   Bt-L%w E1DLHAEHH9rDAHEdH+%(   uH[A\A]A^] ?   4@ UIHAVAUATISH dL,%(   LmMŃ  D  H   WtFL.ALLHHc 1,1HUdH+%(     H [A\A]A^]fHGHuG   ~    IAHM ~    LH/ L1LM,LMI(     }    IG8 ?H}LMȃA&LTLMAA8/   HLMHE(HMLML}t H  1H}о   LMH }4LMȅI(  HELMDH LLI(  1+LMAI8`_qG:g  YH}/   HHEU'HMLMLs H   1H}о   LMH 3LMȅ I(  
HELMLH0 LI(  1*LMAI:`f     H~ Hp HD 1H~ f     HϾ:   &HMLML=y H>Lr A   Hy LEHϾ:   O&HMLMLx H?Lr A   Hx LE  UHHdH%(   HE1HEdH+%(   u1譝fff.     UHAWAVIAUIATSH(dL$%(   LeME    =  ~/=w*H HcH>    H~   D  LLL@t4ff.     HUdH+%(     H([A\A]A^A_]fD  7L)H LLH1(LHHs 1(HuH= AiuMą  i  IcLH H)L1(DH     Hd LLH1d(    HQ LH1D(    HA Hk LL1(     HW(HuE    t
x     @ t#x tHv LL1'@ AF;t!x tH LL1'bfx   x   x 3  x   LHu,x Hu~  H~ LaH LLH1*'D    I  Ho HtHH LL1&LHcHH)LfD  G( u8   U1H= W?H LL1&?    _G)e  ;        H     H fG9GHE ~  H~ #HL LLH1%    Hi @ IcLH H)L%Ao LL1Hq %QH LLH1t%/    H LH1T%    L`H LLH1)%ApH LL1%    HĻ LLH1$    H LL1$    H LLH1$W    H LL1|$7    H| LLH1T$H LL1;$UHHdH%(   HE1Ht(H  HtHx
  HUdH+%(   u
@ 1诗@ ff.     UHH HudH%(   HE1\HuHUdH+%(   u	H1[ff.     UHAWAVSH(dH%(   HE1: u#HEdH+%(     H([A^A_]D  HHUHu(    HA#LEHMA@fC|yW tK:@yX tK: A@&  t1E  Ax rC:@hK<@_f.     E7  1HLEHME   HAu"    Hh"HMLEH    r  ALEAI   >   HLHU}H;ELE/  ALEAIf   1HHH LH	C`H8 01(LEA@K:@Ch@ Hyx    C8LEHM   L8 H A111LEHMA@     Ly8 11LEH A1LMLMLEA1H$ 11LEK:@LEJfL)8 LEHv HMA1pfL	8     >   LE2LEH	C`D     H LEHMHCX A@uD  UHHdH%(   HE10HtHUdH+%(   uH HEdH+%(   u1     UHAWIAVAUATSH(H   H   dL$%(   LeIX Lډf   A   uI  Ht6xv-HEdH+%(      H([A\A]A^A_]f     I   HH~HP E1Dm~DmE1ff.     I9w8I9n8HHPLLIIHDDD(U֧x2I   IHP HHD9u9?Iy )跒    UHAUATSHdL,%(   LmIH  HtfHG Ht?E1    HWJHt HH[HuI  HG II9rHEdH+%(   u)H[A\A]]
HEdH+%(   uH[A\A]] ff.     UHSHdH%(   H]H   &  H.HHH  bHx  'HNH0  H(  H@  HH  HX  H8  Hp  H  HvH  
H[g Hǃ      Ht	H  H Ht$HtHEdH+%(   u5H]fHEdH+%(   uH  H]0H莐 ff.     UHH dH%(   HE1Ht(H}H}HEdH+%(   unfD  HEdH+%(   u"fUHATSHdH%(   HE1H   $  HIH  I$   XH   I$   DH   I$   H   A$      A$      A$      A$      I$(  Ht|H(  H  I$0  HtZH0  Hb  I$8  Ht8H8  H@  I$X  HtHX  H  I$  HtH  H  I$x  Hx  I$@  HtH@  H  I$H  HtHH  H  I$P  Hp  HP  I$  H  I$   H   I$  H  I$`  H`  uI$p  Ht#Hp  H+  I$  H  A$h  h  A$    A$    A$    A$    A$    A$    A$    A$    A$    A$    I$  H  I$  H  xOI$  H  HHUdH+%(   u:H[A\]D  H~1HH1@ H1跌    UHHdH%(   HE1   tHUdH+%(   uif     UHHdH%(   HEH   HUdH+%(   u*f.     UHAWIAVE1AUATISH   dH%(   H]HzHxID$H`A$  wA" tEw#AEL-M5 AT$:AE 	AD$:AG B  I 7  AT$8   L	AD$8AWZID$0   AD$;	AD$;Q   LDE$  E  ID$ A$     HtApuI   t$f     AdD  AL$9AGdID$ AD$9A  A< t	ID$     A8 tIL$0AL$9A>   AS twAD$:	AD$:LtAL$:@H  ;   A$   u  I    u5I   Ht)A$   uA|$&  I	D$`   LA  uI      LAC tA}    A= tA$   ?  AG   A? 
  A9 tAd$9AD$@   Ix tA$     AB 
  A$     wAD$9ރ		AD$9@  AEAT$8%  	AD$8AWaAD$<	AD$<H  {   ȀAD$<A`   AD$;A^   A}
   @AD$;AO tAD$;ff.     AP   A@   AA   AQ twAD$;	AD$;A    e	  AJ tIL$0I$   L9	  I 	  A$   tfAd$8A   4^ A    tAL$;A   AD$lA$   t	AL$8  AV tAD$8σ AD$8AU tAD$8σAD$8I$    	  IL$0H* M$  fI$  )E@)E)EE)EL9  Hǅh    1L5 ǅp    ǅx    fff.     A}  AEIcL>    HAd;  fD  HLLfI   HuA$   A|$e	  ID$p   LI   Hm?fD  LAƄ$   f1f     H{I!D$8A`    AD$;AD$;AO    AD$;AP u1    LAD$<	AD$<A@ Q  @ LAA D   L2I   ID$ AD$9   LfD  AD$;AD$;AO JAP M    AD$<A` _AU	AD$;߃	AD$;A^ GAD$;AO aAD$;T@ A: t)A  u"I uAuAD f.        LfD  xol  x b  HX   L萤HXf     Mm L9CpH  x  tufEHM HuHEר$  }AŋxtxCEH' 8   } tE  HULLHhH   1I\$(!&ff/  LxxI9  I$  x   I|$H`  H  @9B   G)    I   HZ  HG HI  fH*Y9 f/  H,ID$ g9   Ad$9   LH`LD  AG[A$  AI t   LAH y  A|$   LtId$(! Ad$8HEdH+%(     H`HĈ   L[A\A]A^A_]Zf.     IEMm HhL9 AuAD$;	AD$;Mm L9fD  IEI$`  Mm L9_fAEMm pL9A@ AuAD$8	AD$8Mm L9Y@ AEMm xL99@ IUMm L9f.     A} HX   LMm HXL9     A}  tApnIEHX   LAL$9ID$ Mm HXL9?fA}  tI   IEHX   LAd$9ID$ xMm HXL94    IEH8n   LHXI}It$X Mm HXL9    AuAD$;	AD$;Mm L9` AE   fEH]:n[zoQz GE E1E    T I|$	   L_f.        L31LHx   ~IL$0AD$8   L
IL$0       L
fD     L
fD     L
fD     L
fD  I$p   @ I? BA  7I ,L9#Aw(AL$9AL$8D  +fD  E1Hi        LH  @  L   ҝ    Lŝ   L	IGxID$XD  L   	L   v	   Li	@ AG: AE N<I|$	HH  L(  1Hp I$(  01gBI|$	H	  Hr 10   4       L   Lw AD$:	AD$:H H~ 101HG H   fH*Y| f/&  H,ID$ Ad$9   L5L   L#H$ Id$X@#H I$(  H 101:HfHH	H*XHfHH	H*XAH HC 101ID$ H   fH*^ f/slH,HG g9   Kb\H,ID$ I|$ ?'\H,ID$ I|$ ?H H, 01K&\H,HG H ?H HS 101HfHH	H*X1pzU   HAWAVIHAUL0ATSHH  dH%(   HE1Hǅ    Hǅ(    Hǅ   Hǅ   A   t=P  "  D HL41H8Hǅ4    LHE    H)   HAFM  X0IFH8M>
  A    @  D#AF)   A9     ={O    A~<?vH" x    AF8tAF(tH" z uqIVX   tH" y uWIN0
  AF+tH5|" ~ u6Av;@  L`" AxA~l  @	         HUdH+%(   @
  HH  [A\A]A^A_]fD  H<1AvIVHHE    Hǅ4    I)A   H0H8X=IN  Hǅ@  HǅH   1ҾLHǅx   藔  =N  M D#L1Ҿ@L[ufL= H9!    H= A7@11ҾLHH#Hǅ   HH  hM D#f1ҾLZLÓLu.HA IAƀ   H    01aLAƀ   ]D  LL CIM9H   D A   AoG1L)0AoG )@AoG0)PAoG@)`AoGP)pAoG`)EAoGp)EAo   )EAo   XM)E賒#  ;_tD#H @D#H5y ~ *f.     @A  tH=F  A~:@.    t	h  @ tH x	 @tH x
    tH x 1H  }     L=I H    H A7@1h1ҾLHǅx   ~H_ A7   H  @1%1ҾLHǅx   ;H A7H @H7  m  11Թp    H A7   H @1觹1ҾLfoU 貐H A7   H, @1Y1ҾLfo krHL A7   H @11ҾLHǅ   (/H	 A7H @H$  z  111ҾLHǅ  @ ׏H A7Hޠ @H DE8  11n1ҾLHǅ    }H^ A7H @Hy DE  11HH#1LHHH A7H @H DE  11请1ҾL?@轎H A7H @
H D EQ  11T1ҾL biHC A7H̏ @	H^ 8	  111ҾL׃	H A7H @H   11袶1ҾLǅ   覍H A7HE @H  o  11?   Lǅ    LSH- A7H @HH 8 ,  111ҾL H A7HҎ @H 8   11蚵H H A7 H 8   11f1ҾLHǅ   u|HV A7Hy @Hq 8   11If.     L Ax f     L Ax f     L(I  IHA@vfD  H x Zf.        1d     D#   1D~   13   1"	   1]   1    1   1޳7   1ͳCn   1跳   1観   1蕳*   1脳@ ff.     UHAWIAVAUATSH   HuHUldH%(   HE1E       X  HDͣAH3 x tAG;
  H x tA; 
  HEIH  H}   I      Li  IǇ     Ix   tIǇ     HEHHDBC HEHEHHD'C HHEEIx  HtP(IGUL5 MHxL,LA6   H| H1A>  HJ 8  L蘒	  LHP	  L_	  9l  HclCM)HMIHHXH}DD}tufj0	  dD}E1ED9}(  jD}Ef.     I$x     L9HA$	   f  M9$   X  LLHEutH}h  LX  E  H   HH;BL;z {HJHIHʋ\(  H I$  A6	  HH< A1PDE1MPXZMU*  AM$  Hx1蚿H}HI$   H;xL;x HpH8IHT('  A6H HpH MDMEQ  11讯H}EuH}藐A$     A$      }  HEDXA  ;]  E9  I$  ALL9   ] ff.     M9  uc  1f.     ILE9~i@ I   H;pL@ L9  HLPHLNT(IL9{HL@HEHLHHET (A9H9uM9tI$  M	I9IuH}M  MA6H 1>mD9mdHEH9X\  HHEIuDLLۡIx  H҉EHHI  EAƇ	   HUdH+%(   5  EHe[A\A]A^A_]M	L94M9tM	I9#M9uދUEEeL%B L= H 1   II<$yfI$      H=t 蟆I<$1HxHII<$1H?    ,f    E1-}   }ujL  L9 wDELpME-    D  HAٿ   PDEHP 1MnA[X   1ZA$    uH}:EH}QI$   uHMH   oF-H}La#@ E}E    I$(  A61MH    膫! EIHEMHADmL]M]]OHpH8IIHƋ|7(x HI   L;`g  L;x 
L LxLAD(sAx(EXI   LcMcL;`sL;x r%    L]]MA=l;    ^;   H A6MH
 DEo  11~ME$  E   H E    x \  x R  ID9}D  L-: MF;H: IH.E&@ H=:   H: HfD  L`DLSxLWH=} U4: MH$: 1D$@/8A6HED1H 1M,EL]@    1MdMMEIhM$  MLMkMLMADuIjHxMD]MD]   E] clHuLMّElHuLMJEzHEH9XtDeAH}DA	D9R    E&lHuLM赝EA61Ha 1ʧ   ff.     UHSHH(HUdH<%(   H}HHu#HuHUAHEdH+%(   uHH]1aD  UHH0dL%(   LUIʃtHEdH+%(   uJDBLH}HHuLUHuAHEdH+%(   uHUH}1fQaUHATISH HuЉUdH<%(   H}UHuLHHaHA萴HEdH+%(   uH D[A\]`UHATSH H}dL$%(   LeIXH}غHHL`HA6HEdH+%(   uH D[A\]v`fD  UIHIfvHAWAVAUATSHXLW(D
  HzdH%(   HE1HvH    Hǂ8      H)@  HHBBXHBB IA HB0A@   A@f   H!    HB`ǂ   A 5  	tPAA:u)1HUdH+%(   '
  HX[A\A]A^A_]D  A
  Iy(HL虉    A   AHHH9  IHIM< A     At
HHHAtHE  H rHBAtHHHBAtHHHBA@tHHHB A   tHHHB(AtHEHHEHBXA   tHHHB0A   HAI9   Iq0H9IH  AM  @  @tHAI9   HIH  H
H9   HHHHHI9rfH8I9r]H  fD  A    HAI9r=H   H1HH=u*H<    AA<@t
H  I9rH8I9sc fD  I@H   AxwI@H   AA: I@IHHB AD  A     A   F  HAII9vH   HH
H9YH@H    AAZ  H   HqEtkH9 te1f     H~HULELMD]LUMHu謘HuHUMLUHLMLEHFH   yD]HH;8rI9II9LLMHMLUD]LEHU蠦LMHMHLUD]LEHUt2I  Ht&  @  D    f.     A     A    t:HAI9H1L)f   Hv  Hǂ       Hf     A @ t?HAI9H	A   z  Hr8HH0H f   f   HA   tHAI9H	HJ`HA   tHAI9rH	HJ@HA   S  HBh    A   tHHHBhHǂ       A    tHHH   HBp    A  @ tHHHBpHBx    A   tHHHBxA   t=HAI9H	I9H4I9E  H(  H0  LHUËHUnH   HwJ\HpHHH9a0rprHpH9IL@LB0L@L94H   HXH4    H9LH9	Hp H2H@IHpH9H H   fD  HȉH RfD  HAI9H1E=  HΉr\HLELMD]LUHUHMHUHMLUD]B\LMLEI9ZHqHI9IH   D  @ub@tHAI9HIH  @ HHI9H8H  HHI9H@H    HAI9LqL   @tHAI9HIH  MtH|pHƂ   H   Yr\HHMLELMD]LUHU蠢HMIHqI9,HHULUD]HLMLEI   Iy`HUHuLMH}/H    I9HuHI9H}LMIvLUD]LEHUI~u     Ƃ   L[I9H<0I9{HOH   I9gHH   H9d=,  GH       H=u Hu,         HHHMLMD]LUHUHMIHqI9HHULUD]HI LM   IypHUHuLMH}LEH    I9HuHI9zLEH}LMLUD]HUIxIp@ HJ8H   H   H HI9)HI9HELMD]LUHM]HEHULELMD]LUHMXUHuHHULMHMHEHULMHMHEUHHdH%(   HE1H9   HUdH+%(   uTD  UHHdH%(   HE1HEdH+%(   u	HT     UHHdH%(   HE1H   HEdH+%(   uhT     UHH   dH%(   HE1tHEdH+%(   u"ɉ    UUHtPT@ U1HHdH4%(   HuH  HH9t,ff.     ff.     1H;  H H9uHEdH+%(   uɉSfUHHdH%(   HE1HEdH+%(   u1]Sfff.     UHATSHHdL$%(   LeI9L9t<u HEdH+%(   u1H[A\]     HHǃ       A$   Rff.     UHH0  dH%(   HE1   H   u:   u1~ tKBwuH  Htbx t\H  
tRfHEdH+%(      ɉf     Hu؈MH}0HUMHutƂ     ftH   uH  L L9u@ ff.     M I9tL9tI   uH  I9  tLHUMLEH}HHUjH  MLEtQ@ UHAVATSH(dH%(   HE1   tH   t#HEdH+%(   v  He[A\A^]D  Ƈ  \/   HI,HEH  L0LLLLHcHMȅtXH   IH}M)y/   HH   MQHo L1a^_?ƃ   D    HHAH}LLEH[ 1   M ~H(  pHEH(  L:   SH}HtJHHPAMRE)LH8o    1ZY\ HHMQf.     MLHo 1   #Offf.     UHAWAVIAUATSH(  dL,%(   LmI`IHt
x    iLHI軾LHHt9HHEdH+%(     HeL[A\A]A^A_]     H   LHHM   L@   LLL
Lѹ MtMH HM12PH} 1HXZC@ Hx0LE1ٽLHHH   LHHeI0L@   E1LJLb_N     UIHATISH   HXL`Lht#)p)M)U)])e)m)u)}dH%(   H81A:    H    H,LHHEH L   H(H@ǅ    ǅ$0   H0BeH8dH+%(   uHH   [A\]fH'    1LHKLHA cLUHHdL%(   LEIHUdH+%(   uHHD HH1L     UHAVIAUIATSHdH%(   HE1E~ 
  H9   t!HUdH+%(   S  H[A\A]A^]ÐE1䃿   ~.H0  H     LHm HHD1JAL.H    LH1uJI] AHuff     A      L
   uAD$J L9   uHHt    LH1JHAHtI9  u     HHH    LH1IAĀ{    ; t3AE9ME HuLHk Hl HEH	l 1AĀ{ .A}tyHuHk L1A
@ Hq    L1BIAf.     HMIuLHɘAĀ{ f.     LXoHtKHX(HtBHKHk D  HKH4 HuL1HAHu]    HuH.k L1A9IfD  UIHAWAVAUATSH   |dL%(   LUAAU  H      I      HYH9HA    HY H  D|DxA   PDLHdTD	HhML@8DcE1Lp<1     Hn  LcMtAD$+tT0  dHp1L HU    L{A;GAEu)|tHpHi    1GAE1MtL+A4 uMoM+/|  |?  |  M  AD$+     HK H  HpH[i    1FAM  AD$+   x   MAD"c  HhH8HX H@H[PHhHH^ HFH9HEdH+%(     HĨ   D[A\A]A^A_]Ð	   HH HEdH+%(     HĨ   Hrv L1[   A\A]A^A_]EHpHfh    1EAƋxHp1   H [EAMAD"cH@It$-ceHHhE1H8HX H@Hp8LLwA| fHK H<HpHg LL=AM=fD  xx(D  HEHHXVHpH 1   kDLmAMt(AW(f     JAO(9t
BvHHL}    tH;H9      |ujHp<LHX~AHXߘf.     LP   1HpHkf CAD  Lp<   LHX/BAf.     E1O     HpHf    1FCASfD  H- QwD    UHAVAUIATSLH dL$%(   LeLeMt-HEdH+%(   n  H MȉM[A\A]A^]ёAH}ȉ1L H    LBLUAu>   |    uOHEdH+%(      H D[A\A]A^]@ I
EHd L   14BDEA Iu I}LDEHd :DEA@ IU I}L	DEȃsDEA\     H7 L1DEȾ   ADEȉI}E4 tM   L=@E@ LLEB    UHAWIAVAUIATISH  H(dH<%(   H}ȋ>TE$IHt AH{ JcH>D  E  A  Aw1Hx{ JcH>H  IfIA   H  HLH9    1      HH(HH5k LAEL$$Eu@A$ML$t}   T  I  Hz JcH>f           H1L8    萎H(HLH5 A$A$ML$uLLLHI  H   H߾   PL}e    1Y^L{fu+AA  HNz HcH1>f.     LLL辜LH  HLe P      H1   虍XZH(HH5k LAD$ML$AM  IT$H
  IT$ H  EL$(DȃG  A  A  A  Ae  A   A@  E=	  EL$)Dȃ	  A	  A
  AU
  A
  A 
  A@-  EL$(A  o  EL$*A  A  A@  A  A   A@  E`  EL$+Dȃ  A  A0  Ax  A  A   A@P  E  EL$,Dȃ  A!  Ah  A  A  A @  A@  E  EL$0E  EL$4EL  ML$8M  ML$@M  IT$HH  ML$PM  EL$XE  McL$\E  ML$`M?  EL$hEy  EL$lfE  EL$pE  ML$xM'  AD$tAAa      HEdH+%(   a  HeD[A\A]A^A_]@       H1L4    xHH(LH5n AIT$AH12      H0HH ǅ0   H8H HHHYM HXH' HhH HxH' HH HH HH' HH' HH' HH&a HH%a HH!a HHa HHa ǅ@   ǅP   ǅ`   ǅp   ǅ    ǅ@   ǅ   ǅ   ǅ   ǅ   ǅ   ǅ   ǅ     ǅ   ǅ    H(H` H8H|` HHHu` HXH HhH]Q HxHU` HHV` HHW` ǅ0   ǅ@ @  ǅP   ǅ`   ǅp    ǅ  @ ǅ   ǅ   HHD$ILL0ff.     Ic$Lt7@H) MD$HHj    HB1 HE11HHII|$ uHLH5a LD$H(HAIT$ AH1   H8Hǅ4    Hǅ       HHn% ǅ0   H8Hp% HHH HXHO HhH% ǅ@   ǅP   ǅ`   ǅp   HxHD$ILL0@ Ic$Lt7@H MD$HH~i    H/ HE171HHII|$ uHLH53^ LD$H(HAEL$(ADȃIL0 H1A         ̅H(HLH5P AEL$(AArAL/ H1A         {H(HLH5b AEL$(AA+AL^/ H1A         )H(HLH55] AEL$(AAAL/ H1A         ׄH(HLH5\ AEL$(AAAL. H1A         腄H(HLH5\ AEL$(AA SALh. H1A         3H(HLH5]\ AEL$(AA@AL. H1A         H(HLH5\ AEL$(AEAL- H1A         萃H(HLH5[ AEL$)ADȃILr- H1A         =H(HLH5[ AEL$)AA:AL!- H1A         H(HLH5~ AEL$)AAAL, H1A         蚂H(HLH5 AEL$)AAAL}, H1A         HH(HLH5Z AEL$)AAcAL+, H1A         H(HLH5YZ AEL$)AA AL+ H1A         褁H(HLH5 AEL$)AA@AL+ H1A         RH(HLH5[ AEL$(AA  AL3+ H1A         H(HLH5pY AEL$*AAOAL* H1A         譀H(HLH5*Y AEL$*AAAL* H1A         [H(HLH5X AEL$*AAAL>* H1A         	H(HLH5X AEL$*AAxAL) H1A         H(HLH5YX AEL$*AA 0AL) H1A         eH(HLH5X AEL$*AA@ALH) H1A         H(HLH5W AEL$*AEAL( H1A         ~H(HLH5W AEL$+ADȃ^IL( H1A         o~H(HLH5UW AEL$+AAALS( H1A         ~H(HLH5W AEL$+AAAL( H1A         }H(HLH5V AEL$+AAAL' H1A         z}H(HLH5V AEL$+AA@AL]' H1A         (}H(HLH5BV AEL$+AA AL' H1A         |H(HLH5U AEL$+AA@AL& H1A         |H(HLH5U AEL$+AEhALh& H1A         3|H(HLH5jU AEL$,ADȃ&IL& H1A         {H(HLH5"U AEL$,AAAL% H1A         {H(HLH5T AEL$,AAALr% H1A         ={H(HLH5T AEL$,AAPAL % H1A         zH(HLH5GT AEL$,AAAL$ H1A         zH(HLH5T AEL$,AA AL|$ H1A         GzH(HLH5S AEL$,AA@xAL*$ H1A         yH(HLH5wS AEL$,AE0AL# H1A         yH(HLH56S AEL$0AE      H1L~#    \yH(HLH5 ] AEL$4AE      H1L6#    yH(HLH5R AML$8AMz      H1LT    xH(HLH5sR AML$@AM@      H1LS    xHH(LH5@R AIT$HAH1*      H0HHO ǅ0   H8HR HHH$ HXHQ HhHQ HxHQ HHQ HHQ HHQ HHQ HH HHQ HHQ HH{ HHQ HHQ ǅ@   ǅP   ǅ`   ǅp   ǅ    ǅ@   ǅ   ǅ   ǅ   ǅ   ǅ   ǅ   ǅ     ǅ @  ǅ    H(HQ H8HQ HHHP HXHP ǅ0   ǅ@   ǅP   ǅ`   HhHD$ILL0    Ic$Lt7@H MD$HH>Y    H HE11HHII|$ uHLH5MP LD$H(HAML$PAMo      H1LP    uH(HLH5P AEL$XAE5      H1Lq    OuH(HLH5O AMcL$\AE      H1LSf    uH(HLH5M AML$`AM      H1LP    tH(HLH5OO AEL$hAE      H1L    wtH(HLH5O AEL$lAfEM      H1LO    -tH(HLH5N AEL$pAE      H1L    sH(HLH5N AML$xAM      H1L    sH(HLH5mN AAAD$tAAAL} H1         LsH(HLH5%N AAAD$t[      HAL#    1ArH(HLH5M AAAD$t      HAL    1ArH(HLH5M AAf.     DA	s  H^ HcH>fHF E1fD  H      1RHLdI    H$r_AXIf     HyF A   I ff.     HF A   I ff.     HNF A   nIff.     HVF A   NfD  A|$H%E$A  H^ JcH>fD        H1LL    @q LyL       H߾   q~D  HyT    MtAQL.H A68f.           H1LL    p$ HE A   VHF @ ff.     LH  H  H5iG HfLH%   DHJHS ;M  QLG VPA6      H1   pH lHdF gHF [HF OHF CHF 7H@F +H4R @ MPLF A6HQ HD HtD HD H<R HD HR H*D HD HD |HD pHR dHD XHpD LH:E @HE 4HR (HD HD HD HQ IHB E1T@ HYHIE@ H5Q @ H5E    1HLE QVP(!     UHHdH%(   HUHHt'G tH9t:fHUdH+%(   uF    HW1HtH9u  t1fD  G!G   G!G v fD  UHAVSHHH HsdL4%(   LuIHtH}3H}HHttC HsHt3HCHt1HUdH+%(   uUH [A^]LCH0S H&Q    LL:      H=-Q >LCH     UHHdH%(   HMHH   1(ff.     ff.     H@HH9   HHt   H 0       II  IDDI~A   DHHMHDǍ~IADHHMHDǍ~IADHHMHDǃH HH9HGHEdH+%(   uHf   1c@ ff.     UIHHHdH%(   HE1H   1#    ff.     H@HH9   IH#t   H 0       II  IDDIЍpA   DHHMHD֍pIADHHMHD֍pIADHHMHDփH HH9HGHEdH+%(   uH       1]g    UHHdH%(   HMHH   1(ff.     ff.     H@HH9   HHt   H 0       II  IDDI~A   DHHMHDǍ~IADHHMHDǍ~IADHHMHDǃH HH9HGHEdH+%(   uHÐ   1dO@ ff.     UHHdH%(   HE1H9sUIHHHHI#uQHOITH%f.     ff.     HHHu4H@H9rHEdH+%(      HHHff.        H A0       HH  HDADIzA   DHHMHDǍzIADHHMHDǍzIADHHMHDǃH HH9HG=     A   1j ff.     UIHHdH4%(   HuHH9sSIHHHHII#H!uJHOH#fD  ff.     HII#u2H@H9rHEdH+%(      HHHf.        H A0       HH  HDADIzA   DHHMHDǍzIADHHMHDǍzIADHHMHDǃH HH9HG?     A   1j ff.     UHHdH%(   HE1H9sVIHHHHHIHH!uKHOIDH ff.     HHHu3H@H9rHEdH+%(      HHHff.        H A0       HH  HDADIЍxA   DHHMHD׍xIADHHMHD׍xIADHHMHD׃H HH9HG=    A   1j.f.     f.     f.     f.     fD  UHAWEAVAUIATSHXUMH}dL4%(   LuEqLHEqHHEHcMH    HH]YYHHEMYHIBYHUMHuD]HÅ     fAnA   Lfp fofo0 Hfs fAnLfp @ ff.     ff.     ff.     fofofHfs fffpfpfb@H9ut+DHcA9~DAD9DAD   D3DE1DBE1Ʌ#  HuD  HEE҉MEB<1.f     AT4DD9O9OщTI9tWHAT D@8AEALHt} tHuB:TuA:|uHuUT9~T    ML9Ut/HEDLeII܉HCLLeH]HD  HELDl近H跑H}讑HEdH+%(   uiHXD[A\A]A^A_]11HMH~DH9t&DHH9t!IDHLA$MH9uHMuLeIHfUHHdH%(   HEHHt.Ht H    HEdH+%(   u1fD  HwfH7fD  UHAWMAVAUATSH8H]LmH]dL%(   LEE1E1MHE    AE!LM^3E   H}H     H1L$@IHL9   HTHuLIHEHH8HtpeHHLLH}tH}Ht21fH}HIH}H|HIL9uH}HE    HEdH+%(   uZEH8[A\A]A^A_]@ H}Ht1 H}HHH}H|HHL9uH}HH}@ ff.     UHAWIAVAUATSH  HpHǺ H`HvD`HBdH%(   H]HLpIF LHP`Hǅ    Hǅ    IHCHǅ    Hx(   HHLLPHpLLHP&HHXZYHD  =  7  H;5~   H\: H=e: HEH11L9HhHh   HCHx0HtH5<:   Hh   LY$L1LL`H<     MG-襝HCLs HHCC(    HC0    LxʚH  M)HxpI7L8E1~HH8  HH@   D  HHp  L{H@HL=H`E1C(    HC HCE1HS0HC0    HpLHHHK(/HHF  H8HxpEMMH1}H{0葌HI9q  HXL)MLHhfA   J48)prIą  L=jHHxHHpHP@HHHx   H  HHH)I<1ߛHHHHxʋHHf.     HpHP=Hx   H7 HH1H)I<HnHHH>Hc   H1HxHc H)L8HH,    x+&_<XL4}9Au蕪P%kF\twX]賀|D/d N0(蜂%BtRNIFtk/!ag;薞衤<WRdW3dZFo誋uf@H; Q1HH 6 @   HH1詙H11LgH4HhHh tfD  Hh%HSHGHEdH+%(   uOHe؉[A\A]A^A_]        1@ Hh   f@ U  HAUATLSHLH  H?dL,%(   LmIsoHHH4 Ƅ H    0AT1LKMQXZHEdH+%(   uHe[A\A]]f.     UHHdH%(   HE1HEdH+%(   u`8ff.     UHHdH%(   HE1HEdH+%(   u1fff.     UHHdH%(   HE1HEdH+%(   u_@ ff.     UHHdH%(   HE1HEdH+%(   u@ ff.     UHHdH%(   HE1HEdH+%(   u
@ ff.     UHATS1HdL$%(   LeIH   ӆI$   YA$   F[     LI$   HH<4I$   H    A$   H9~I$   H< uH9I$    tI$   u?I$   h?I$   [?I$    t$LXI$   H訔IǄ$       HEdH+%(   uHI|$`[A\]K;	fD  UHAWAVAUIATSHHHdL$%(   LeA06  EEE   H 8  IcEH   HC8Au  A}t     HIuH{`DAǅ'  AE      HEdH+%(     HHD[A\A]A^A_]AH   Hȃ?H   HcHH   HB  AE  HCH      HHHH	H 8@ ff.     H   H5- %     Lc   LPHH   H#     L3HH   H     LHH   H     ܐ   HED}E1E1LmKf.     H       B0EH   D)HIBD2Iƨ   D9     HN,    蟙E1E1"      H1L   BN    IE L   I:7  HED{@]ȀOH   HJHE(DI}   p@EHcFMHIp  Lcٸ   H}E1LHMCLHLLUI	Һ   L]"LUH   LgfH蘘E1E1"      H1AH   HH18    H# 01ZK1H   AD  HULM1LUH먅 AN*HH9 01KH}赁D}    [	AE{|E\tHHHEWrH}~kDeILmEA ff.     LDu`AK|9EuH   ID   HHH	AE9uLmDeL__H I       H7 01J譞H6    H 01I腞H6    H 01Ir]H6    Hh 01IJHN H?7 101|I'H6 H)    01[IH6 H.6 @ UHAWAVIAUATSH(HudL,%(   LmI2LM>HEH Aą   IV(MF LIcvILH!M)HH!NI9t7HuHLHcH)IMF AՅxeIV(IN IcFIH!I)IV HuHLLAՅx7HELIF袗HEdH+%(   u+H(D[A\A]A^A_]ÐtA A    UHHdH%(   HE1~!FH@ HȉGH9uHEdH+%(   uJf.     UHHdH%(   HE1~4FHf     ff.     HHHHGH9uHEdH+%(   uf.     f.      UHAWAAVIAUATISHhHEH}(HuLm H]LEHEHE0LMHxHEdH%(   HE1;EM  IEL(M9u+  fD  I  x t{ u Mm M9  H3I  XtH蕖A    CH{0E`rHHEt:\  E4`  Hx4rHEE]  HEL0蹎IHm  H} tH}OI(  Hl  H} tH}}OI  HL  HE HEI   HEI   1HtCA   ELA   +JHUI  A   HEM  I  Ht8HH9t0I  HrfHnI  flHxI  HHqMtID$M|$M'IGL8E4E  HEdH+%(   l  HhL[A\A]A^A_]H}pHEELpD  IvHU1HL* _&Iv8HUHL'    C&Iv@HUHL'    '&I   HUHL'    &I   HUHLn'    %@ AHE    U@ ff.     {mHEfHu3L3vIHtHE1PHxL@ E1H}|H}|E1H}|H}|I(  C3I  73Lyfff.     UHAWAVAUATSHdH%(   HE1HE    H   HIAH9u-   @ IH}LkL{HI9tD{$uC H{tIHtNx tHx06uYI|$0nI@ HEHUdH+%(   uIH[A\A]A^A_]fD  H{zIHcEZkIMD  1@ ff.     UHAWAVAUATSH(  dL,%(   LmIH  HIIQ  Lf9GDqVAIcփ     LHH@+HDE1IE9}..  Ƅ fL-3 1H$ D)H$    I} gtCI} KM   LI Hv$ 1?LMtI} Hh$    1 HEdH+%(      H(  [A\A]A^A_] DKH  HIcDIt HF*D..  DfIHE)f.     HEdH+%(   u8H" MHp. H|#    H8H(  1[A\A]A^A_]I@ UHAWAVL5u4 AUATSHH(H}dL<%(   L}L?L9        AG$wqIcL>f.     (   MgEo1=/HEHH  fHn@   Dh flD` fHCHSHHBHH}   M?L9}v1HUdH+%(     H([A\A]A^A_]f(   MgEo1.HEHH}  fHn@   Dh fl MmLHUqHHUHBH,  BG    (   MgEo1=.HEHH  fHnM@   flDh  @f.     (   MgEo1-HEHH  fHnM@   flDh  @f.     I Aſ(   Eg1-HEHHh  fHnB   flDb DjX     I AD  (   MgEo1=-HEHH  fHn@   flDh L` D  (   MgEo1,HEHH  fHn@   flDh D` D  I Aſ(   Eg1,HEHHx  fHnB   flDb Djh     I AD  E   Mo(   Eg1F,HEHH  EfHnDb flLjB    E   (   MgEo1+HEHH   EfHnDj flBE (   MgEo1+HEHH   fHnM@   flDh  @rfE   MoE    MoE
   K@ E	   ;@ E   +H}k+ff.     2UHHdH%(   HE1Hn HwHAڄ HHUdH+%(   u    UHAWA1AVAUIATSH8HUHMdH%(   H]L/AH  HAE =  4  CH{0EfHI.  D4   1fHEDLIH  H} tH}CI(  H  H} tH}CI  H  HEM   I   1HtCA   ELA   >AI  A   IǇ  
   IǇ      '  HEdH+%(   =  H8L[A\A]A^A_]fLeHE    LeIu1HLQ L,Iu8LHL~    Iu@LHLk    LH߹   I   LP    LHI   L: 9D  LHkHH AE E1U&@ ff.     ;bI
 1L覃H}qLqE1H}qLqI(  5(I  )(Ln@ ff.     UHAWAVAUATSHXH}uHUdH%(   HEHG HE    Lp@ff.     M~ff.     M'Mt-LpLI9~H}HcL*ADIM9u˅HEI@H}u=H}Hc$LHMHDHLHEHMH9rIHEHMHـu$1HUdH+%(     HX[A\A]A^A_]HEHMH H	ˋEE    EHט H@HEIĐff.     M|$ff.     M7Mt-LpKI9~H}HcL*ADIM9u˅  EI@}uH E1L`@fMt$ff.     M>Mt.L K9}H}HcLHE
D]IM9uʅN  AEI@A   uE1E1@ HELp     M&Mt/LJ9}H}HcLHEI
D]IL9uuɅ   AHE@AuDeAE	IcHE2u}而DuHEHcۋMAHDD	HEMH;EspH E    Lh@M}fD  M7Mt-LII9~H}HcL	ADIM9u˅tEI@E   uHcEHE{HEHcHDHEH;E}D誋DAEEA	IcHE*DeADeIcHEfD  UHHH0dH%(   HE1Ht$H6HUdH+%(   ufD  1@ ff.     UHHdH%(   HE1HEdH+%(   uɸ   Jf.     UHHdH%(   HE1H wHф HHUdH+%(   ufD  UHAUATSHdH%(   HE1H   HIIH9uG        HS{2    H5 Lx_HI9tW,   LyxFC tuHSHtq1H5 L@xHS1H5V L'y HEdH+%(   uFH[A\A]]fD  HKH5 L1cfD  {$wsHzfD  UHHdH%(   HE1Æ HEdH+%(   u     UHATSHdH%(   H]HH9t<IHHH0  !L0  HEdH+%(   uBH[A\]  uHw )      H= H
X    D  UHAUATSHHdL,%(   LmIH9   I1$fD  ff.     ff.     HL9tNH(   uLugH(  HtoHI9t-H(   tIHI9tH(   t7H   L9utF1HUdH+%(   u?H[A\A]]f.     L8:H(  HuD  L(gUfHAVAUIH}ATSH`dL4%(   LuIHu)E)EE  )E)EÅt,H}HEdH+%(   uH`[A\A]A^]D  HuLHuH}I HuLlHuLH}uHEHH9tIM H@LjIU HHAi UHHdH%(   HE   +   HUdH+%(   uD  UHHATSHH dL$%(   LeIԀ   ub?   H   H9t=   A$   tMA$   9ta)HUdH+%(      H [A\]Ã          A$   u9uZI$   L9      9uI$8  H8  +}uHEdH+%(   u|H LH[A\]3D  LUHM"U؄tHMЋ	;    H}H"HM؄Of     A$   XW    UHHdH%(   HE1HEdH+%(   u1fff.     UfHAWAVAUEATSHH   H GD0dL$%(   LeLeEEEEEEH`HHMfInLE  flDEHUEH)E4  ǅ`LzjÅp  L}M9h  ǅL    E1퉅8efD  IHXHX26I8  Hr  1L9PE   A]L`  M?M9  ALQ1LHPB1LH'HH   HHX6uH0ZH`'IH  L6,   )LuM9D@M6M9  L9tL0H9uL&IH   LV6uLD@HHXf     RHH$LaH    H12H +     HEdH+%(     4H   [A\A]A^A_]D  1QIH     1yQIH/M6M9D@@ L(HP   `M?M98HHLD=LuM9  ƅK E1E1Hǅ@    HǅP    ƅ8  D  LLeYM6M9   AL1.I8  E1HXA  `t  E9   Aǆ       @E   @KM$  tLXLP*  L@I8  D(x  I   H@ HP"(8  L@ML9XM6M9LmM9t-ff.     L-1L9   Mm M9u9LAD
KD"0H LwEt
} d  4jH H@ƀ  S J     H`H1H`LH/H`HAǉ47eH`HH`EL9e   ǅ4@ I   H9PT  `t8    N  L@M  I   M98HPVf     A   MLPI8  udI   L;@M8HP     LH(H(A  A&I6L9-LL8MII*ff.     ff.     M?M9  I$   I9   uLtLL8MI    L9@8:D  I   HPL9@M8L H5 L@Hǃ 11H 3%cLfL   H )`LHp3Hp1H    %L7P
LPML@ƅ8bLMIƅK ǅL    H $      H= H    B     UfHnflHHdH%(   HE1HEdH+%(   uS UHAUATSHdH%(   H]HH9t>L#I@ H{wH{ nHHCHLHBH%[M$$I9uHEdH+%(   uH[A\A]]fff.     UHAVAUATISHdL,%(   LmIH   HH   (   AHtKDpfHnL`Lh HfHnHBfl HHEdH+%(      H[A\A]A^]@ Ha ML4 LMEH 101~#L&ZHEdH+%(   u9HL[A\A]A^]Z H! 2      H=8 Hf     UHAVAUATSH   H$ H   H$ HdH%(   HE1HtmIH EHtHl H| HEIHHѺ    OH4,HI),LDLHHEdH+%(   uH   [A\A]A^]@ UHAWAVIAUMATISHLH8WO-LEBdL<%(   L}L}GHptHH=    MtYH]LHEfHnHfl)EHU}   HEH9t$H  HuH  HxH  HHqIFIVL2HBH1HUdH+%(   u4H8[A\A]A^A_]ÐEGH}LHډE(Eĸ    UHAVATSHHdL$%(   LeIHwL H1҄u*HEdH+%(      He[A\A^]f.     HCH5 HIHt5HEdH+%(   uTHeHL[HT   A\A^]:f.     C8HHsLH;s0LLK(LC XYXfff.     UHAWAVIAUIATSH8HwHdL$%(   LeI	Gu%1HUdH+%(     H8[A\A]A^A_]ÐIE AE8LME(M}0HEIE I]LEPH-rpLrLEH= IwzMtMLeLfInLfl)EauuHEL9t$I  HMI  HpI  HHJHCfHnLkfHnflAE L(D  EGH}LLEEif     UIHAWAVIAUATISHHHMdH%(   H]DEu   I<$I9|  DUDmDփ@uD@u@AH 
H M
MUE>  LMLufD      A  DE1   A  DMA   1EAAD  D		ʋO8D		p  	ʉщW8D  	ʉW8tƇ  tO8t
Ǉ       H9   9   tƇ  @tƇ  AtƇ  A   Ƈ  H?I91HUdH+%(   +  HH[A\A]A^A_]D  E  E!E1At1A_  T  D"E1EEEAA  AD	D	D		w8p  	W8tƇ  tO8t
Ǉ       tH;      tƇ  @tƇ  AtƇ  A K  Ƈ  H?I9   DO8w:DEAAAA@AAуAD	D	DD	ɄAk  } EuAE1Af.     @A} u~EEƅ} :  }   Au1EqfD     A   } \  E1A  A      E1} /  1ɉE1   D	D  H?I9    H;   cO8WO8NfD  A   E1A   DE   1fAubA   DEEE1ۺ      1w@ E!EIEA1>    DA1ɃE?@ A   DEE1E1۹   1D  1EA   E1} E1\Af  DEE11E1۹   1D  H| DD
11EAf.     E1E   E1} t1`D  E11EE1} s1?@ O8w:AȉA@AAAAEƃAA	A	E	EEۄ  A  D!EuDE1At^ED"M1EfD  H?L9Tf    H9   
O8f.     @A} uyEDME>} u:DMDE1ۃA"fD  DE11Ҁ} u2E    E1} tu@  DME1AD  E1E1DE1A   D	E  D!1A A~   AlDE11n    } tz1A      AJ>fD  } E  A؉1mO8    D1A   AfD  A   1E11fH5y DME1D
DA    LMLuLMgLH}   H' H1e~LMAv1HUIyA     1E11<@ E11E1E1} s1?@ DE   A   1   GH}H=q LMAv1HIy~wTEAu$E1DAuA11E111fD  UHH HMdH%(   HE1HEdH+%(   u&EMA   HH	MHH	\    UHH HMdH%(   HE1HEdH+%(   u#EME1HH	MHH	Zf.     UHAVAUATSHdH%(   H]HH9tPHS IIHs{LoHI9t/L5Xv I6
   HS HsL{@HI9uHEdH+%(   uH[A\A]A^]    UHAUATIH}SH(dL,%(   LmIHHM1j LA   E1LkZYAątHq  -H}4JHEdH+%(   u#HeD[A\A]]    LH}Gfff.     UHAUATSHdH%(   H]HH9tBII
fHI9tH{L,*Ht   HUdH+%(   uH[A\A]]1@ ff.     UHAUATSH(LgH}dL,%(   LmII$HE1IT$HMA   H8j L[jZYAąu*H}	IHEdH+%(   u@HeD[A\A]]@ LH}E+   H8t    H=4 HD  UHSH8H_dH%(   HMHH: tG@uHUdH+%(      H] HEH:MHEH     MHuH}HU,HUH}HuȋMHHH8 uHrs #      H= HkfUHAVAUATSHdH%(   HEHGL(AU  I]E    H   I`@ HHtHHMHe 1H5 wEԅ   LHabxBH[L9td   u[E    {uH5 L'HuLHyHlr (      H= H@f     1HUdH+%(   uXH[A\A]A^]Hn H  1019fE    Hq B      H=I  HyfU   AL       HSH  HH dH%(   HE1HH   H`H1VH 1H`1eÅtH$p  ~.H=  1@HEdH+%(   u3H]f     Hq 5      H=X  Hf     UHAUATSHXdH%(   HEHGL(AE~dI]HuUY     K@   H}L A@   1   gHuHxkH[L9t^   uU{tHPp ;      H= Hf.     HUdH+%(   u7HX[A\A]]fD  1Ho (      H= H|D  UHHdH%(   HE1G$HUdH+%(   uD@ UfHAWIAVEAUATSHhH}HMdH%(   HUHUHE    )E)E)EM   E1MtEiE1HtDb8   	H   L}foE]HM@HuDmDefoEDuHU@ fHnflHP0HHH 1HUdH+%(   uOHh[A\A]A^A_]fD  LpHxHSLpHxI4UfHAWE1AVAUIATSHHXudL$%(   LeIHE    )E)EMtExE1MtEq8   lHtpfnM   HUHfnLmfbD}fEfoEDu@foEHP0@ fHnflL` 1HUdH+%(   uHX[A\A]A^A_]ø+ff.     UHAUATISHH(udL,%(   LmMHuHUdH+%(   uH(MMHH[1A\A]] UHAUATISHHoHF0dL,%(   LmIH~)EoFHE)EoF E )EHtxHEH   A] Mm   LSIH   8   H   foEHU@foEHP0@ fHnfl@1  u%LhI$1HUdH+%(   ujHH[A\A]]ÐH@֐8   fHt5foEHM@foEHH0@ fHnfl@1  H}]fff.     UHSHG dH%(   H]Hu,H{HEdH+%(   uHH]7@    H{WUfHnflHHdH%(   HE1HEdH+%(   u UHAUATSHdL,%(   LmIH?I9t.H@ HGfHnflHCH$I9HHuHEdH+%(   uH[A\A]]:f.     UHH dH%(   HE1Ht(H}'H}HEdH+%(   u?fD  HEdH+%(   ufUHAWAVA   AUATS1H  HHdH%(   HE1ƅ`  h  LH`E1ti=Ø  It HsMtA?<tH`lLIaIDH=g  wEu,   fB-`|@ HHHXHtM1L`   HW VxMHXHUdH+%(   u;HĘ  [A\A]A^A_]    1H`   H ^Vy1UIHHSH8~$dL%(   LEIЃ  H HcH>fv MH  =  txMtCLM誽H}   H2 H1UxHUH}1ɾ     HUdH+%(   L  H]f~ K  fD  1@ MH~ iMtLMH=; }   D  V MHQ  ~ 6HuH=N LM     kHMH}Hq,1VQDN Es M@M3H= LEHMf~ M@uك~;HuH= LEf.     D^ EuHFI   ff.     y$MHP  H= LMH}1ɾH     ^ EHFI        F H~A  LEHuH}HMLEHH9EjLEHMH= &HMLEHq,Ix1     MHDF E  H~HuH= LM`F HFIB8     F eHFIB     F EHFIB@     MH~ HF8n  IrHHLEHM!_HMLEЅaH= D  ~    H~Hu1LEs`fHMf/Z  HMWHMLEЃ8"f1LEHMqHMHËy$"HHMLEHq(IxHM@H= MKrf=   H1I@ M7LMH=     LEHuCHMLEH2Hy:HMLEHt=HLEHM\;HMLE    xoix cZAx, uH={ qwH= `ff.     UHAWAVAUL ATfInSflHH8H   HELuHHʹ   HdH%(   HE1HE    Hǅ4    ) H0L8EtH  ?  MM  M>M9uL@ M?M9t@HLH0tHEdH+%(   4  He؉[A\A]A^A_]ÐLL  II9   Hff.     HI9   z$uLz     H I9   x$uLHs,LL 'HHsMj
H0   IPAUL HH0LH79LL    I M	L8ME1E1dfD  E1VE1D9f     UHAWAVAUATSHH8HuUHMdL$%(   LeMEtxIAńtlE E1E1DmL&IH   LH}9uEGAVLHATMLMHu;ZYu@MuHELpfD  DuDTMj HE1ATHuDHLM^_HUdH+%(   u He[A\A]A^A_]    } t1!UHAWMAVL AUfInIH0ATflSH   HHHʹ   dH%(   HE1) HHhH(    <w  <x  <r   ǅd   J      w  x  r      Rd   w  x  ruqumdM   fff.     Lpǅ0   Hǅ@   M   II9uqHI9thLHH06tHUdH+%(     He[A\A]A^A_] ǅd   MuA   jf.     LLżT  II9u[ H I9tPx$uL@HIuE1ɹ   j
H0j j AVj HAH0H   1@D  E1 ǅd   J      wSRdef.     ǅd   J   Rd MGY3I1vdD  ^dMBMtUHAWAVIAUATISLH   HEHH(LH dH%(   HE1M   M9M9u2   f.     
v/LLH0uUM?L9t]AW$vԍBvH= (J(H謱H4Aw(I|$HH    fD  HLH59 Hǅh    L0H8H(L@HHHHXHPH H`iHtDH0H5h   HUdH+%(      He[A\A]A^A_]ÐH(H5 HtH0HZLBHILLǅh    H(HL	Y^aH H(L   HD@?蝳fff.     UHAVAUATISHF$dH%(   H]H  t=      HEdH+%(   z  HH[A\A]A^]D  C Lr1  HCH= 6  ԃ*    D/1fD;o   HHuH= s,1LHHUdH+%(      H[A\A]A^]     HCID$AtA$H I	D$A$    1D  LrS ueH{	wsD/1    D;oteHHuO     HCID$AtA$H I	D$A$   1:fH=s MH= 躱f.     UHAWAVAUIATISHX  HHOHLdH%(   HEHHHǅ
   ƅ fHnHH}T fl)8   1   H0HID$(HtH0LAD$0M6  M;m ,  HHծM} H HM9u9Y  f     H HHHHHHM?M9%  HL#tHUdH+%(   4
  He[A\A]A^A_]1H0"	I$A|$ tMt
M;m 	  H5s H01H0L/   H0<HCW H@   H) H81~H0D  HE1E1   HH0j Hj ATH蹭H0H	  1D  LI9u   @ ff.     Mm I9t|A}$uIuLdI}@  sH=i 'IEI   1     IEHxPI}I+HY M}AE2 IE Mm I9uLI9u=D  Mm I9t/HLH0tH LHLHH LuH~Q 8   tLI9!  ff.     HHq  HH9  E1I,    ff.     ff.     MDHH9tQB$uHrLHHuHrL HI	HH9u ff.     M  HH9p  E1I*D  ff.     ff.     MDHH9tQB$uHrLHGHuHrLHI	HH9ufff.     M  HH9  E1I*D  ff.     ff.     MDHH9tQB$uHrLHHuHrLHI	HH9ufff.     Mw  HH90  E1I*D  ff.     ff.     MDHH9tQB$uHrLHHuHrL?HI	HH9ufff.     M/  HH9   E1I*D  ff.     ff.     MDHH9tQB$uHrLHgHuHrLHI	HH9ufff.     M  H1HLH0L@t  HHp,ݬHIHH9  H ff.     HH9  z$uLJ     H H9  x$uL@HHH0Q   AUHATHBH0LI(M  I$(   t	AƄ$  I$  I$  H9u<  ff.     H H9$  xu@A$  HI$p  %H I$p  A$h  (A$  )A$  f(1A$   A$      Mm I9HLH0UtW@ 3IEAE2IE     IEIE   q1HHH裺HO I$H L   H81H%f.     (   fH  fHnH@   fl@   HLhHHHPHfD  (   H}  fHnH@   fl@   HLhHHHPHfD  (   H%  fHnH@   fl@   HLhHHHPH7fD  (   ^H   fHnH@   fl@   HLhHHHPHfD  (   HtyfHnH@   fl@   HLhHHHPHE1@ ff.     E1N     1f     E1$HH5 H011JH&fD  UHAWAVIAUIATISH]HHhHMLEdH%(   HE1H    أMtzM>M9trLxMM#@ HEHMHEHHHHM$$M9t9LH}tHUdH+%(   H  He[A\A]A^A_]    LxLqHEH  H   H1j LMH}A   ZYO  HEHU   HEHHPHIH,  fHnHE    E1ǅt    fl f.     LLEIHtMLLb$uLL
tLEHLLLtFH} uIFHED  A},    Hmt   HEL01HE1HHxHxHLMMLH;G HY    01fHxtXfD  H}HE1LfBLEHLHL)1H}SHuHwHF LELH    01H}[HS)f     UHAWAVIAUATISHH8HULEdH<%(   H}ȿ   IH  fHnLfl HtI6HME1HH   {,   E    E1E1f.     LLuIHtELH""uI6HMMLHuEC9MuILh    Et)1HUdH+%(      H8[A\A]A^A_]D  LPLEHULLH6t1H}L   Ha 6x_L}H=0 HMH{HqLLa@I6HME1HH8HE    J!UH~HSHdH%(   H]HzHEdH+%(   uHH].f     UX   HSHdH%(   H]HHt3oHSP oCHPP@oC @ oC0@0oC@@@HUdH+%(   uH]w    UHATSHHHdL$%(   LeIHv4u-HEdH+%(   u6It$ H{ H[A\]X4     HUdH+%(   u	H[A\] UHAWAVAUATISH   HdH%(   H]HHx  HPHhHk  ff.     H5+ HhH   H   Ml$HpH1: H   HbfInfHnflHpHEHttH}HX<HXIT$8HP(IT$@HP0IT$HP8IT$ HP@IT$(HPHI$HPP; LfInfHnflyD  HpHHpHHw@ HP1HUdH+%(   u%HĈ   [A\A]A^A_]f     I|$~1f.     UHAWAVAUATSHH  H1HdH4%(   Hu1d$Hl     I.HH  LhM   H ff.     I}1蕮HtxLpHXI9tcHff.     MN Au   1Av   L    HHL1M6XZI9uHHL`IHdHHE1,I\$HuSK   H~ j j j Qj E1ɹ   1j 1HHH0HHH   H{@   E1$Hǅ    Ht  LpMtL{LL0t:HLkHtwLx@   LCLLL)HuQMLIHt;HKIH1MH    0yHǅ    L MHLH@MHP LCj j j R HEdH+%(      HeL[A\A]A^A_]/+HEdH+%(   ujH> H"    0He1[A\A]A^A_]Q5HUdH+%(   u,HY> H    0He1[A\A]A^A_]vU   HAUATHHS1H   dH%(   HE1HE    HǅD    H1@HHhIHtLH@1IĻ   (IHt&1LHɘxE   LL`LHEdH+%(   uJHĨ   [A\A]]f     AM8 1LLnyAM:L1LXЉڙf.     UHAWAVIAUATSHHdL<%(   L}IH}HHH~5~ fHnHUH5flH5zHEE荺H]HtL@ HsLK8HLLC0HK(HS sPsHs@AVHH lHH}HM2HuHEdH+%(   uHe[A\A]A^A_]D  UHATSHHdL$%(   LeIHf j 1j E1LQ 1j    Pj j LSLHH0/$H[ j 1j E11Lj L*    Pj j SLHH0腷HEdH+%(   uHeLH[A\]f.     f.     f.     UHSH   H$ H       L dH%(   HE1HIHV   1H1>:ZYx(!1HUdH+%(   uH]f.     d@ UHATSH dH%(   H]HlHxH   ILt4/   fff.     ff.     <:DHHBu/id L1yHHtHEXH}؉LHEdH+%(   uH [A\]1蒖f.          UHHdH%(   HEHf>t6wTft.OfwmHMdH+%(      HH~fD  HMdH+%(   unHH]4D  f u!HMdH+%(   uGHHfD  H9 H    01AHEdH+%(   uɸ   覕fD  UHHdH%(   HE1f>   w!Gf%wXH! HcH>@ f U  '  f t`f u!HEdH+%(   H  ɿ   [ HQ8 HG    01yHEdH+%(     1fHEdH+%(      ɿ   fHEdH+%(      ɿ   fHEdH+%(      ɿ   rfHEdH+%(      ɿ   RfHEdH+%(   usɿ   fD  HEdH+%(   uSɿ   fD  fHEdH+%(   u(ɿ    HEdH+%(   uɿ   >ٓf     UHHdH%(   HE1f>   w!Gf%wXH HcH>@ f U  '  f t`f u!HEdH+%(   E  1鎫fD  H6 H    01HEdH+%(     1fHEdH+%(      1D  HEdH+%(      1D  HEdH+%(      1D  HEdH+%(      1D  HEdH+%(   up1f     HEdH+%(   uP1f     fHEdH+%(   u%1fD  HEdH+%(   u1qff.     UHATSHdL$%(   LeAf>   w#AD$f%wMH HcH>@ fA       fA tffA uyf     Hu)H4 EĉH?    01H` HUdH+%(      H[A\]fD  f     f     kf     vfD  ffD  艕T@ fAI:f.     Y&$蟐@ ff.     UHHdH%(   HE1?   L  IILHubIyHsbt11HH9uHcHIAIHcM  H0IDI 1HUdH+%(   ufD  HcIDڸڏf.     UHHdH%(   HE1f>   w!Gf%wPH HcH>@ f -    f tXf uHEdH+%(     `H2 1HM 01HEdH+%(      1D  HEdH+%(      /    HEdH+%(          HEdH+%(      O    HEdH+%(   un HEdH+%(   uVk HEdH+%(   u># fHEdH+%(   u`HEdH+%(   uK6fD  UHHdH%(   HE1f>   w!Gf%wPH HcH>@ f -    f tXf uHEdH+%(     PH0 1H 01HEdH+%(      1D  HEdH+%(          HEdH+%(          HEdH+%(          HEdH+%(   unc HEdH+%(   uVۙ HEdH+%(   u> fHEdH+%(   u0HEdH+%(   u薌fD  UHAUATL%]c SHHHb dL,%(   LmI  HME1   HLHMHMudDeD+eAIc@IE H  HcuMH1HI )L3Ic"1HEdH+%(   p  HH[A\A]]E1   HH=^b I  EA   tDeA)AMcLIE H	  U   MHcH1L3L)H ]       H5< LԹu>   H5: H=a 趹ua     LEMfH). H    M01QMjHH L1    H- Hٿ   H
 01   }h     U   HATI   SH   fo dH%(   HE1@HPHƅx!Le)`uT   Ϳ  @ HEtjH.HEHPM*  E11AHP1ǃu3H   HUdH+%(   u%HĠ   [A\]fD  L9t또HEpUHHdH%(   HE1.wH HcH>D  1fD  HUdH+%(   !   Hv     HU     HU     HU     HU     HU     HU |@ HvU l@ HaU \@ HMU L@ H9U <@ H%U ,@ HU @ HT @ HT @ HT @ HT @ HU @ HU @ HT @ HT @ HT @ HT |@ HT l@ HT \@ HT L@ HT <@ HT ,@ HqT @ Hݶ @ HeT @ H]T @ HS @ HS     UHHdH%(   HE1HEdH+%(   uɸ    躆f.     UHHdH%(   HE1HEdH+%(   uɸ   zf.     UHHdH%(   HE1HEdH+%(   uɸ  :f.     UHHdH%(   HE10  Hq HcH>f     HR f     HUdH+%(       H)N     HR     H=     HR     H
     H     HXN |@ H( l@ H \@ H L@ H <@ H ,@ H~ @ Hr @ Hf 1ЄUHHdH%(   HE1HEdH+%(   uɸ   蚄f.     UHHdH%(   HE1HEdH+%(   uɸ   Zf.     UHHdH%(   HE1HEdH+%(   uH?   D  UHHdH%(   HE1~       t"$wH HcH>f.     1 ff.     HUdH+%(   1   HQ     H L     HK     HuQ     H[Q     HAQ     H'Q |@ HQ l@ HP \@ HP L@ HP <@ HP ,@ HP @ HwP @ H^P @ HEP @ H,P @ HP @ HO @ HO @ HO @ HO @ HO |@ HO l@ HtO \@ H]O L@ HFO <@ H/O ,@ HXL @ HDL @ H0L @ H= @ HN @ HN @ HK g    UHHdH%(   HE1HEdH+%(   uɸ   *f.     UHHdH%(   HE1HEdH+%(   uɸ   f.     UHHdH%(   HE1HEdH+%(   uɸ誀f.     UHHdH%(   HE10  H HcH>f     H f     HUdH+%(      Hm     Hˬ     H     H     H     Hw     Hb |@ HM l@ H9 \@ H% L@ H <@ H ,@ H @ Hի @ H @ H @ H @ H @ H٫ @ Hī @ H @ H @ H |@ Hp l@ H \@ H L@ Hm <@ HX ,@ Ha @ HL @ HF 1@~UHHdH%(   HE1HEdH+%(   u1~fff.     UHHdH%(   HE1HEdH+%(   uɸ   }f.     UHHdH%(   HE1HEdH+%(   uɸ}f.     UHHdH%(   HE1  H HcH>f     H f     HUdH+%(      Hn     HZ     HF     H2     H     H
     H |@ H l@ HΩ \@ H L@ H <@ H ,@ H~ @ Hj @ HV @ HB @ H. @ H @ H @ H @ H @ Hͨ @ H |@ H l@ H \@ H L@ Hn <@ H[ ,@ 1!H ?{@ ff.     UHHdH%(   HE1HEdH+%(   u1zfff.     UHHdH%(   HE1HEdH+%(   uɸ   zf.     UHAVATSHHdH%(   H]H?i  Q IL%Q    HME1   HLHMHM   DeD+eAIcSIH  HcuMH1H )L3Ic61HEdH+%(   ~  He[A\A^]@    H59 Ll   H H    M01#Mx)    E1   HH=P 	teD  H Hٿ   Hڲ 01Ѿ   C       H5ܲ H=mP ȧ   6P    1Ƀ}UE+U+EЍL	+DdMIcMIHt_HcULcEHHNLRU)H1RDEH; MA)IcX1Zf     LEMonx ff.     UHHdH%(   HE1HEdH+%(   uH  %xD  UHHdH%(   HE1:  H5 HcH>f     HB f     HUdH+%(      H@     HT     H-D     H$D     H     H     H |@ HC l@ HC \@ HC L@ H <@ HC ,@ H @ Hף @ H£ @ H @ H @ H @ Hm @ HW @ HA @ H+ @ H |@ H l@ H \@ H L@ H <@ H ,@ Hأ @ H @ H̣ @ Hƣ @ H @ H~ @ Hi @ HT @ H? @ H* @ H |@ H  l@ H \@ H֡ L@ H <@ H ,@ H @ H @ Hm @ HX @ HC @ H. @ H @ H @ H @ Hޠ @ Hʠ |@ H l@ H \@ H L1EtUHHdH%(   HE1HEdH+%(   uɸ    sf.     UHHdH%(   HE1HEdH+%(   uɸ   sf.     UHHdH%(   HE1HEdH+%(   uɸZsf.     UHHdH%(   HE10  HQ HcH>f     HĠ f     HUdH+%(      H@     Hd=     HP=     H<=     H(=     H=     H = |@ H< l@ H? \@ H? L@ H: <@ He ,@ H@ @ H @ H @ H @ H3 @ HS? @ H<? @ H%? @ H? @ H> @ H> |@ H< l@ Hd \@ HL? L@ H2? <@ H{> ,@ H? @ H @ H 1pUHHdH%(   HE1HEdH+%(   u1pfff.     UHHdH%(   HE1HEdH+%(   uɸ   zpf.     UHHdH%(   HE1HEdH+%(   uH   5pD  UHHdH%(   HE1!P  H HcH>f     H f     HUdH+%(      HΝ     H     H     Hԝ     H     H     H |@ H l@ Hp \@ H\ L@ HI <@ H6 ,@ H# @ H @ H @ H @ Hל @ H @ H @ H @ H @ H̜ @ H |@ H l@ H \@ H L@ H <@ H ,@ Hq @ Hz @ He @ H @ H 1mUHHdH%(   HE1HEdH+%(   uɸ!   zmf.     UHHdH%(   HE1HEdH+%(   uɸ   :mf.     U11HAWAVAUATSHH   D dL,%(   LmIE    fEfUE tt,   HHu$   HH|   H Hٿ   H& 01A   HEdH+%(   \  HeD[A\A]A^A_]f   H5< H==D (  D    ]HME1   HH=
D A^HcEU)L}Mup}lhx9tHcM;M#  MHMHPHXL<E1LcD`H=0 H[P f     H{HAH  LL uIcH"P D`   HHXHtHEDLHH`LDLLPDXL?L`IL-U+UHx+pDh+lDLcLIE H  LHpLHxHH& HHcEIHPED)PAWLxAPHcEMHHPE)LPHcEHSDMHpA)1lDXH@@ xH[    H> 01膯Dxcf.     HEL   LD`HH`HXDLDL9ptHME+HPHEH    D`HPH1MHcEUD`xM)pMhMlrA#i U   HSH   dH%(   HE1@HPH!Hǅh   fxH    HEu( HUdH+%(      H]f.     Hǅ`   KHP*  E11AHP1LǃtH @ 1yHH       HtBH H	XhfUHHdH%(   HE1?wH HcH>D  1fD  HUdH+%(      H     Hx     Hc     HN     H9     H$     H |@ H l@ H \@ H L@ H <@ H ,@ H͕ @ Hٕ @ HÕ @ H @ H @ Hܔ @ HȔ @ H @ H @ H @ Hy |@ Hf l@ H \@ Hlx L@ H| <@ H ,@ H @ H< @ HI @ H @ Hc @ H+
 @ H? @ Hu @ Hi @ H @ Hih |@ Hh l7e    UHHdH%(   HE1HEdH+%(   uɸ   df.     UHHdH%(   HE1HEdH+%(   uɸ   df.     UHATISHH   HXL`Lht#)p)M)U)])e)m)u)}dH%(   H81HEIL H(HLHH@   ǅ    ǅ$0   H0L9sEHf;./uH{/u
H8/tH8dH+%(   u)H   [A\]f     LH5ٓ H>c    UH HH: dL%(   LEL8 LEHEdH+%(   uI1HHDn n9cf     UIH7 H5 HH9 dL%(   LMIHEƀ: APL7 HPLEHm 1LHUdH+%(   ubUHH   dH4%(   HuH`u$x%   =   HUdH+%(   u1gb    UHSH   H$ H         Ll dH%(   HE1HIHV   KHPHHZYu2h%   = @  HUdH+%(   uH]f.     1a    U1HH   dH%(   HUH`u*x%   = @  HUdH+%(   ufD  1Oaf.     D  UHAWAVAUATSHXH}HudH%(   HE1H  HMIMHE   I   HH   /   ?   H  LHL9H IBCIH9qCIH9LBHQL9CLHL9H?LCʍQL9ȸ   CJ    LCI?DHHELHLMLL11AԉH}   HELME1HLMHEpD  LL   ADLLÿ   DuALL   HEB40AH} x  HEHL9t>IL9u%  LEM!tHELELL   B40ALEL9EuLDuHH#EHEt,LuE1fLL   AIL;uuLuLuL   ALELmM!M ff.     HEHML   B4(IAM9sHELmHt5LuE1IfD  HMuL   AIM9uLuLmLL   AIL9uLL	   AHUdH+%(   u8HX[A\A]A^A_]D  HE    I       J1^    UHHdH%(   HE1HtXtTF1Ҁ< u3t'NHfHQ t+H9tHu   HEdH+%(   uɉ 1]f.     D  UHAVAUATSHdH%(   HE1f       II1E1D  A   Hq L1   [AA   )ڃ-H9IcHUdH+%(   uGH[A\A]A^]fD  H L1H   v[AA   9s묐1\    UHHdH%(   HE1HEdH+%(   u	Hh\     UHAUIATSHHH(I@dL$%(   LeIHtmH@ Htdg     ATL   Lj j 3D   1gH HxxHUdH+%(      He[A\A]]f.     H5o H}H}Ȅt   느H5W H}H}ȄuH5Ha lH}YHEdH+%(   uHeLH[A\A]]sG[    U   HSH(dH4%(   HuHuXtHEdH+%(   ugH]    Huп   HeHe yfoEHuп   fs)E yH H    01 Zf     UHAVSH0dH%(   HE1?v1HUdH+%(   u|H0[A^] H}gHuп   HuȋIpu6HUHEHuȋ
t
H  HEؿ   HUHE>HUȅtA널   AuYf.     f.         UHATSHdL$%(   LeIH?Ht"LfD  HHC    H;HuHEdH+%(   uHL[A\]SY UHAVIAUATSHdL$%(   LeI?   1@ ff.     {HǄuq{Hc   AIH   MtA$LA> tL;H uqH    HEdH+%(      HL[A\A]A^]    H  C@ WHt t? tuRfXf     H I@ AFIt tLH)rQHtHHC7   1	LLSE1:{HcWfUH1IHH@dL%(   LMIHPH9tnJ  HJHt	  HrHt	&  HH  HwHEdH+%(     @ HHHHPH9uHPH  HJHt	X  HrHtuHNIHJHVHpHtHzH9LEHHELUHuHULMALEHELUHuHULMHNIzHHHFH:HtHHHHHH8H  HH;B  LRHUdH+%(     HALRHHLPHBI
HH
HH   HH;At8HQLEHHHELMLUAHULEHELMTfD  HQfLRHHLPHBI
HH
HHvNHH;AtLHQLEHHHELMLUAHULEHELMZfI\     I HQfHH@ HNIHJHVHpHtHzH9LEHHELUHuHULMALEHELUHuHULMHNIzHHHFH:HDKIHHM]LRTIHHTff.     UIHHdH%(   HEHH   Hu\HQH9toHt	   HPHH9   HQHHHtHyH:HHH1HvfHH;J   HrHEdH+%(          HQHtt2HPHH9   HQHHHtHyH:@ I0 HqHH2H0HHHHHD  H   p@ HWHPHGHtHpH2H8HWHHHQHHHD  Hr#    HWHPHGHtHpH2H8HHWH,SUHHHWdL%(   LMIHwH;  H  HFIHHu  fD  HHHPHuLPILQHpHHHHWHPH2LH2HH  HHH;~  LFM'  H0HtLHA1H9tl   HpHt	  HPHt	Y  HH6  HwHEdH+%(      HHHHAH9uHA p  HpHt	s  HPHtuHrHHpHBHQHtL@LHHL@LWLAHHLMtIHIHHLH  HHH;H	  Hx2fHHI
!HpHQHqHHHHHHHvNHH;J   HBH@ Mx     LVH2@ LFW    I HHv/HHH;y   HqHu!1x     I1HdH\@ HpHQHqHHHHHHHvaHH;Jt+HBHXHHHvHH;xtFHPHBI HBHqHUqIHHHPHrHHpHBHQHtL@LHHHPLGHQHHLHtH2HH2HHLHvHH;JtHzPHI9CHHz2Hx)$O@ UHIHH0H?dL%(   LEIH   H   HQH9tuHt	   HWHH9   HQHOHtHAHHHH1HvlHH;H  HpHEdH+%(   T  HHAD  HQHtt2HWHH9   HQHOHtHAH@ I1 HAHHHHHHHHD  H    HEdH+%(      @ HPHWHxHtHwH2LMHHMHLEHEAHuHMLMLEHVHHQHOHfHp    HPHWHxHtHwH2LMHHMHLEHEAHuLMHMLEHVHM ff.     UHHdH%(   HEHHt/@ ff.     HH@HuHEdH+%(   u	H1L    UHHdH%(   HEHHt/@ ff.     HH@HuHEdH+%(   u	H1WL    UHHdH%(   HMHH9tHHWHt9fD  HHRHuHUdH+%(   u" HHH9xuHHHw1K ff.     UHHdH%(   HMHH9tHHWHt9fD  HHRHuHUdH+%(   u" HHH9xuHHHw1^K ff.     UHHoHdH%(   HEHHwHpLGMtI0HI0LGMtI0HI0Hv2HH;ytHAHEdH+%(   u HAf.     HJfD  UHHdH%(   HE1HtNH1HvHHH9xtHEdH+%(   u+H@ HBHt    HH@Hu19Jf     UHHdH%(   HEHHt8@ ff.     HH@HuHBHuHEdH+%(   u	H1If.     @ UHAUIATIHSH(dH%(   H]HHHt)H9HCLLHBHMHHyA HMHEdH+%(   uH(H[A\A]]>I ff.     UHATIHSHdH%(   H]HƊHHtHLH HHEdH+%(   uHH[A\]Hfff.     UHHdH%(   HE1H|   ytM~N   H      HHu=H      HunH      HuLfHEdH+%(   uWɉD  G<ft8><Ft2<Nt fD  f     0t1u1     1롐<ntGD  UHHHU dH%(   HEH t@ PH uHUdH+%(   uGff.     UHSHdH%(   H]H莡HtQHDH9r!H fD  HH9r	 u@ HEdH+%(   u+HH]~fD  HEdH+%(   u	HH]Fff.     UHHdH%(   HUH
fHH< tuHEdH+%(   uFD  UHHHdH%(   HMtff.     @8t#PHuHUdH+%(   ufD  PHu#F UHHdH%(   HMHH2  ȃtp@:1  tU@:q  tF@:q  t7@:q  t(@:q  t@:q  t
@:q     )HH)HH   H@HH   H!HHH9   H99t@:17  @:q5  @:q  @:q*  @:q  @:q  @:q  1HA@8qHDff.     HUdH+%(         HHfD  HH9   @:0tHf     tk@:0uta@:puktV@:p   tG@:p   t8@:p   t)@:p   tHP@8p    HED@ 19HA0H'HAHHAHAHAHAHHHHCf     UHAWIAVAUDn?ATSH(dL4%(   LuADIDEtsI1LdfD  I} IM9uA?u&HEdH+%(   u;H([A\A]A^A_]fD  DmDHHK#<1B    UHcH?HHHdH%(   HE1~eAvnHH)HtbHH)HtVA1AIf.     oofHI9utHHHHEdH+%(   u9É1fD  ff.     ff.     LLLHH9uB@ UHAWAVAUATSHHuH}HUHMdH%(   HEȍHHE~9  EAAE1E     HEHuDHn4 J<8L)1HIE9rnD;m   E]EHuH}AVU/F;E9EI    } uHEHuH( J<8L)1EHIk HEHuDHs J<8L)1HID;mmHEdH+%(   u/HHL[A\A]A^A_]     ]>    E1@fD  UHHdL%(   LUAA
  AB   HH)H   HH)H   A1fAEIf     oofHfL9ufoG	fsffH~E9tNN#NL	?t$EJ4J#4HHHH!JH	HHUdH+%(   u=    EE11I@ NN#NIL	M9ufD  1W?    UIHHdH<%(   H}HtZDH   +f     ff.     ff.     HpI9t'HHLI9Lt1HEdH+%(   u1ɉ    ?tI4H34HHH>UIHHdH<%(   H}HtJDH   @ ff.     HpI9t'HItH#tt   HEdH+%(   u+ɉ1?tI4H#4HHH>@ ULǉHH?dL%(   LUAHHFDExpDLAK|@ ff.     H	HHH9uOLA)EtA2HHH!I	HEdH+%(   ufD  EF=fD  ULǉHH?dL%(   LUAHHFDExpDLAK|@ ff.     HH!HHH9uOLA)EtA2HHH!HI!HEdH+%(   uE<fD  UAHHAdL%(   LEI  AB   HH)H   HL)H   A1fADHff.     ff.     Ao ofHfH9ufoC	fsffH~A9tMIL#LL	?t$EHHKJ#HH!JH	HHUdH+%(   u9 EE11I@ KHJ#JIH	M9u 17;    UIHHdH<%(   H}HtZDN   +f     ff.     ff.     HFI9t'HHDHI#Dt1HUdH+%(   u1f   ?tډHHHI#HH~:f.     @ UHHdH%(   HE%UUUU)ǉ33333333%HUdH+%(   u:fD  UHHdH%(   HE%UU  )ǉ%33  33    HUdH+%(   u9fff.     UHHdH%(   HEU)ǉ33ЃHUdH+%(   uA9HUUUUUUUUUHHdH%(   HEHHH!H)H33333333HHH!H!HHHHHH!HHHHHHHH HHUdH+%(   u8f     UHHdH%(   HE1=  t HUdH+%(   uE@ HuH=h  x}_ Y fD  LHJ8ff.     UHSH(dH%(   HE1@uHEdH+%(   uFH]fD  @}HDU߄tKHUdH+%(   uHH]H87 UHATSHHdH%(   HEHGHT0H9r7H9sUHDI0HIHH9HC1Hu2H*0Ht8ID$I$1HUdH+%(   uH[A\]fI|$Ǹ6fD  UfHHdH%(   HE1H߄ HGHuHEdH+%(   u1 HEdH+%(   u{6 ff.     UHH dH%(   HU1H? uHEdH+%(   u3fD  HHHEkHUdH+%(   uH}16     UHS1HdH%(   HE1H? tH_HtHGH1赎HEdH+%(   u	HH]5     UHATISHH0H7dL%(   LMIH   HH+GH   AoIغ   HEIAHEI|$H)I|$P_x>HcI$Ht	HI+D$H9jI\$I<$    HIT$ID$ 1HUdH+%(      H0[A\]f@   LLMyuI4$LMLfD  HLyuI|$I4$LMIغ   HH)I|$^HcI$Ht	HI+D$H9@Hׄ Hn    01y>@ 1LHU*yHUȅ4@ UHATSHHdL$%(   LeA   xu HSHKHrHsD$HKHS HUdH+%(   u	H[A\]3 UHAVIHAUATISH dL,%(   LmIoxÅt!HEdH+%(   udH [A\A]A^] I|$LI|$LCIT$I<$ tJ*IT$ID$  1LHUxHUȅtӉ2UHH   H`HhLpLxt )E)M)U)])e)m)u)}dH%(   HH1HEH0ǅ0   H8HPǅ40   H@HHdH+%(   u=2fff.     U    HAVIAUATSH HLgL/dH%(   H]؉HEHvt.jf.     IF~   H¾    LIVvu>IvHIvHInHHyMtYI> teIFMfB  @ HcHEdH+%(   uXH H[A\A]A^]fD  IV IVL)    LHETHU1LHE vHUȅt1f.         UAHAUIATSH(DDdH%(   H]؉Eux  @ A?tNA[  1A\IAM    H ؄ AD8u~DWEEHIE  EA* AtEEtHׄ AHc uhA REEIUIEt	A*u A*  1HEdH+%(   5  H([A\A]]@ A8SD  DWHE  AtD  AU!  IME1HAA8~   Q]AA u)  @ HA8t[ʄ@ƀ]@ a  H-u׀]   DhE8@A8@ u7A8PH@ I]@!tf.     HH]uE8DWD@LhHEF@ ff.     A*t%E@fD  HA-   E1E1fEEIA*t   ELEtLAщDEDMH}!Ƅ#H}DEDMDWHEum    AUIMEThfEVA*'L-    UHHdH%(   HE10	   Hu
   \HuH~H}HtAJ2w\Lyp IcL>     HHԄ t~bu) u#HUdH+%(   u]f~Btf.     H    ~ t     H
f.     Hf.     H({,fUHHdH%(   HE1HEdH+%(   u
11lg,    UHHdH%(   HE1HEdH+%(   uɹ   1)$,@ UHHdH%(   HE1HEdH+%(   u1ɺ   +@ UHAUATISHdH%(   H]HIH܅EMcPA)HHcI)H)K<,H4 xDH8u#Dy1HUdH+%(   uH[A\A]])G+    UHAWAVIAUATLkSIH8H}LHMdH%(   HE1lH   Iń   H@[ L<[ M~   1MLEHMI%fHMLK|5 1L)H! ӶLcMHELELK|5 HML)HZ D1H蠶I9tHIM9uL艦E1HEdH+%(   u*H8L[A\A]A^A_]D  HZ LZ @*     UHATSHHdL$%(   LeI@ x\u2HXx\t(LH3HtH9tHSH9uҀ;\tD  HUdH+%(   u	H[A\]) UHA"   A'   HY    HSHH}H(dH%(   HE1HE    y'   @ "uUHxH5 賳HXHt:HuH螳Ht)'uHxH5pY 聳HXHu     1H}HEHEHUdH+%(   uH]     1(    UHAWAVAUATSHdH%(   HE1wIHtv\   H蒰IHtaL`x u)~fD  ILLM)LcLM{{ tWI|$\   HHHuL8LLHPzHEdH+%(   u!HL[A\A]A^A_]     AE  '@ UH5-X HAWAVAUATSHdH%(   H]HHf  HvIHG  H	D  tTHH5W 51HHt= <"t^<'tZ<\uH{eHsHHPz<\uCHufHEdH+%(     HL[A\A]A^A_] LcDLLHDxMcLIyL9s~A9uO    A9tCM9sfISHLЀ\uA9uLLIL)PyA$A9u@ H{臀HsHHP'y    A9tL[E1 HEdH+%(   uHH[A\A]A^A_]kd%fD  UWHHdH%(   HE1@ǀ	v)aP7@FHUdH+%(   u     0%fD  UHAWAVAUAHATSHH8HUdH%(   HE1HIAŉƉEvH   E~E1fD  uHxAPHuEAMcH8J< fHEIHtsuHIHtUMcfff.     II_LHLL)ȜLHuLL)J<!貜uHN$0ìIHuHLTHEdH+%(   u$HEH8[A\A]A^A_]fD  A   =H$     UH~HSHdH%(   H]HzYHEdH+%(   uHH].#f     U    HATSHdL$%(   LeIeHt7LHrHtHCHHUdH+%(   uH[A\]H軟1#fUHHdH%(   HE1HEdH+%(   u
H錷G#    UHHdH%(   HE1HEdH+%(   u鐃#ff.     UHAVAUATSH  dL4%(   LuIHH5|0 ۾H   I@ ff.     L   H|Ht_H|HtHLƄ oAątLP'HEdH+%(   u+H  D[A\A]A^]fD  E1ND A!"UHHdH%(   HE1HEdH+%(   u0!ff.     UHHdH%(   HE1HEdH+%(   u@!ff.     UHAWAVAUATI8   SH(dH%(   H]H.cH&  IH  LsLJiHSA]0~G	 fHnHflIE(AEM   L-pHEH   HMuA
   1r  A}0 V  HL˙H}uuI\$,   HڨIH>  A$    H5	Q HHE    -   H}IL   H+ 1(H}\wLoE1ff.     HEdH+%(     H(L[A\A]A^A_] HLH}"uI\$,   HIHtt     H5AP HHE    euHsLU=tU@ HsL<=D  H}觛+fE11fD  ; u+H}肛D  HuL<lD     H5O HHE    ĝtvMt7H}IL   H) 1辳H}x>1pthA}0 uJHLɗH}H}}aӚH}NHsL><H}豚H}訚,HuL<^ ff.     UHHdH%(   HE1HtHEdH+%(   u+ HEdH+%(   ufUHHdH%(   HE1HEdH+%(   uЇf.     UHSHdH%(   H]HHt(H@|t&t!t(wGfff.     HHEdH+%(   u\H]HD  H5Ą  t	 x\uHt|t&t!t(tۀ)u@ pVvfff.     UHHH dH%(   HMHHt@HrHt7<&   <|tX<!t<HEdH+%(      H     1HUdH+%(   upD  HzH|    H:HHUHM]HMHUuHRc     H:HHUHM-HMHUt
f.     UHAVSH dH%(   HE1H  HHwHHw  <&   <|   <!   A   1H   HJH	HzIc1HH    (HsDEkDE؅xH   D)BHEdH+%(      H [A^]ÐHHuTuHtHuHPH߉EMD  H:H    Hte(HsHUHU؅xHDAD)A"Hz1H HމUDEDE؋Uԅ;< A   HHUvHU؉AD@ E1ѹD@ UHAUATSH(dH%(   HE1H  HGHHt <|<&t<!  L#M  ID$Ht <|<&t<!w  M,$M  IEHt! <|<&t<!tI}N IE H   HPHt|@ƀ&@t	!  HHtRHJHt	|@ǀ&@@t	!  H:HEHUHUHzH}6HEHPHtRHJHt	|@ǀ&@@t	!a  H:HEHUHUHztH}۔HEHϔIEH   HPHt|@ƀ&@t	!  HHtRHJHt	|@ǀ&@@t	!  H:HEHUHUHzH}EHEHPHtRHJHt	|@ǀ&@@t	!  H:HEHUHUHzH}HEHޓL֓Ml$M  IEHt <|<&t<!t
I}LIE H   HPHt|@ƀ&@t	!  HHtRHJHt	|@ǀ&@@t	!<  H:HEHUHUHzH}HEHPHtRHJHt	|@ǀ&@@t	!  H:HEHUaHUHzTH}軒HEH诒IEH   HPHt|@ƀ&@t	!  HHtRHJHt	|@ǀ&@@t	!k  H:HEHUHUHzH}%HEHxHEH}LLLcM  ID$Ht <|<&t<![  M,$M   IEHt% <|<&t<!tI}J    IE HtIHPHt|@ƀ&@t	!  H8HEHEHxH}>IEHtIHPHt|@ƀ&@t	!  H8HEHEHxH}LMl$M   IEHt- <|<&t<!tI}I@ ff.     IE HtIHPHt|@ƀ&@t	!0  H8HEHEHxH}NIEHtIHPHt|@ƀ&@t	!   H8HEHEHxH}LLHEdH+%(   W  H(H[A\A]]Ǐ    HEdH+%(   +  H([A\A]]fHHL#MqfD  I|$HzI|$HHxHEHHE<f.     HxHEcHHEf.     HxHECHHEf.     HxHE#HHE^f.     HxHEHHEjf.     HxHEGHEf.     HxHEGHEf.     HxHEGHEf.     HzHEHUGHEHUfHzHEHU_GHEHUAfHzHEHU?GHEHUfHzHEHUGHEHUfHzHEHUFHEHUwfHzHEHUFHEHUFfHzHEHUFHEHUMfff.     UHAWAVAUATSHXH}HudH%(   HE1H  fHuHE    )E6HEH   <)  LmHMHMM        <!  <&   H  MuM     EIHT  M7H@ LuIGIG    M}M HuLHEH   <)  IW<(tbl<|   LmH   M     $EIH   HQ@ M/LuMIGIG    L}rfH  HuH{zH]IGHt}H  ;)  Ls2fH     DH  LufHHEH@     LIGH)LEI@IGHx @ Lm1f.     HEHM  IEHt <|<&t<!&  I] H   HCHt( <|<&t<!tH{Df.     L#Mt>ID$Ht <|<&t<!  I<$<I|$2L蚊LcMt>ID$Ht <|<&t<!  I<$I|$LSHKI]H   HCHt% <|<&t<!tH{GC    L#Mt>ID$Ht <|<&t<!0  I<$lI|$bLʉLcMt>ID$Ht <|<&t<!  I<$%I|$L胉H{LsE1HEdH+%(      HXL[A\A]A^A_] Huc   )BHt$H fLuHH IGIfIG    1LmD  I}Bf.     Lm    LmI qHEHEI|$AI|$AI|$AI|$AHEH8     UHAUATSH(dH%(   HE1H  L'HM  ID$Ht. <|<&t<!tI|$/A@ ff.     M,$M   IEHt <|<&t<!  IE HtIHPHt|@ƀ&@t	!  H8HEHEHxH}oIEHtIHPHt|@ƀ&@t	!_  H8HEHEHxH}LMl$Mm  IEHt <|<&t<!  IE HtIHPHt|@ƀ&@t	!  H8HE9HEHx,H}蓆IEH   HPHt|@ƀ&@t	!  HHtRHJHt	|@ǀ&@@t	!  H:HEHUHUHzH}	HEHPHtRHJHt	|@ǀ&@@t	!4  H:HEHUTHUHzGH}讅HEH袅L蚅L蒅HEdH+%(     H(H[A\A]]mD  HEdH+%(      H([A\A]]f.     I}g>qfI}W>=fHxHEC>HEUf.     HxHE#>HEYf.     HxHE>HEf.     HxHE=HEKf.     HzHEHU=HEHUfHzHEHU=HEHU3-fff.     UHAVI   ATSHdL$%(   LeI=HE    HHtBHuLHHt.HEЀ8 u%HEdH+%(   u/HH[A\A^]     MtHEI$H16fUHAVAUATSH dL,%(   LmIHE    M  HH  HuIH]IH  ; u_   Mu 1<HHtQfInfInHX7 flHC1I] HUdH+%(   :  H [A\A]A^]    MtIID$Ht. <|<&t<!tI|$;@ ff.     M,$M   IEHt* <|<&t<!tI};ff.     Mu Mt;IFHt <|<&t<!  I>I~L,MuMt;IFHt <|<&t<!  I>I~LLMl$MX  IEHt) <|<&t<!tI}:ff.     Mu Mt;IFHt <|<&t<!e  I>I~L\MuM   IFHt <|<&t<!  IHtIHPHt|@ƀ&@t	!   H8HEHEHxuH}܀IFHtIHPHt|@ƀ&@t	!   H8HE0HEHx#H}芀L肀LzLrHtL ?fD  MtIfD  I~g9fI~W9!fI~G9fI~79fHxHE#9HEf.     HxHE9HED  UHAVAUATSH dL,%(   LmIHE    M  HH  HuIH]IH  ; u_   Mu A8HHtQfInfInHn3 flHC1I] HUdH+%(   :  H [A\A]A^]    MtIID$Ht. <|<&t<!tI|$7@ ff.     M,$M   IEHt* <|<&t<!tI}7ff.     Mu Mt;IFHt <|<&t<!  I>I~L<~MuMt;IFHt <|<&t<!  I>I~L}L}Ml$MX  IEHt) <|<&t<!tI}6ff.     Mu Mt;IFHt <|<&t<!e  I>I~Ll}MuM   IFHt <|<&t<!  IHtIHPHt|@ƀ&@t	!   H8HEHEHxH}|IFHtIHPHt|@ƀ&@t	!   H8HE@HEHx3H}|L|L|L|HtL ?fD  MtIfD  I~w5fI~g5!fI~W5fI~G5fHxHE35HEf.     HxHE5HED  UHH dH%(   HE1HtHHHt@HHrHt4<&   <|tU<!t9HEdH+%(      HkD  1HUdH+%(   uxD  HzH$    H:HHUHMHUuHEdH+%(   u/HzHuH:HHUHMHU{f.     UHAVATSHdL$%(   LeL'M   HI|$H   <&   <|   <!ufA   I|$1Lg8xd1M<PDHc?IHtH;HHEdH+%(   uVHL[A\A^] Xǅyfff.     E1 I<$1Lwx1MDtP[f.     @ UfHHdH%(   HE1  HǇ      HǇ          HEdH+%(   u0UHAWAVIAUATSHHH  H dL$%(   LeI8H  @  ff(f(H  LL  f(L8 H        L  ILcM9MGH H`  xu[  HMK<.H L, Hc LJ    HEHM)HLP1jI^_HL9IGIH  MM)ZwK<.LH H1.Hv, HL9IGMI1M)K<.L{.Lp  LL, HL9IGMIM)K<.M  1H   LHHL9IGIH`  M)HxhH  K<.Hu  L H\ HLMHL1RL+    ^HHL9IGIXZH9HEdH+%(     HeL[A\A]A^A_] Hc  H1HH   fH*H  1HHz  fH*H  fZH9  fH* YH   fH*^ZZ@  f.z  ZYf^ZZKHfHH	H*XCfLx  MtDL* J     Hx     1Hw Lq,HL9IGIL8  LS* M1HK* L8,HL9IGI    HfHH	H*XfHfHH	H*XfHfHH	H*XqfffHc  Q f((H  1HH]  fH*(H  1f(\H^ZY\H  fH*(H  1\f(H^ZY\H  fH*D(ź   LLD\^fHL4    D^f(f(ZYEZDY\f(A\BELcM9MGo H ALH L( HMHH1R   D(\@ HfHH	H*XfHfHH	H*XfHfHH	H*X=f^@ UH    HHHi dH%(   HMHH81   -fff.     UHHdH%(   HE1UE1HHdH%(   HEHH9rHH9rHEdH+%(   uDH)A   HHQif     UHHdH%(   HE1HEdH+%(   uH=O 驕$@ UHATSHHH   dL$%(   LeIL   HEdH+%(   u	H[A\] ff.     UHHdH%(   HE1Ht0d  t$H: HUdH+%(   u     !   d@ U  HHe  dH%(   HE1   HFHUdH+%(   uUHAWAVATSH   H$ H   H$ H dH%(   HE1>  IHIH[9 LHcH>fD  H I   LLH8  E1HEdH+%(   w  HeD[A\A^A_]fH9 M   HHLH8  -o I   LL1H9 & H I   LLH8  8HLI9uff.     HI9t8/uL)H   LHIH"HLƄ J  A@ 1HLL)HE@    f     H) LLH$ LH8  iL   LB HHH)M   I<1H5@hHɚ H# LLLH8  	LHI   H)I<H 1HQ%@ I   LHLHH	   H5J# qH- H # HLH8  tLHI   Hb M   A`  LL9u @ ff.     HL9t8/uIH H} HLLH8  L LLLcHI   LL)H)HH9K<H 1LL}HHE" HcH1H)LHh} I:  HLH)   LLKH̘ HLH H8   H   L HHH)I<HPLH1=XZ    HL\zLAL؃ HDH1AWMHM   LLp=LFYD^LH؃ IL9ulfD  UHHdH%(   HE1d  HUdH+%(   uUHcHAWAVIAUATSHH8HUHIfo	 LEdH%(   HE1)EH-XXXXXX HEHV L$AT$}   H},Aǅx|HAT$u7Mt}HUHuLMHEdH+%(   uYH8D[A\A]A^A_]ÐHED nH}AD  1H^AԈHu H}Lf.     UHATSHHdL$%(   LeI	t5T  t+HEdH+%(   u9HL\  L1[1A\]HEdH+%(   uH[A\] ff.     UHAVAUIATISHHdL4%(   LuIotKT  tAL\  LLLÉ3HUdH+%(   u H[A\A]A^]fjf.     UHAWIAVAUATSHH(H}H߉UdH4%(   HuȾ/   蔅.   HI脅MnMfLDAA} [   IH   LpL=߁    H5 Iw0IHtLuHEIXM9   A$.uAD$ku	AD$oH}G} t=   DM   D)H  tmHE_   -   H8%*1HUdH+%(     H([A\A]A^A_]Ð   H5 LjuX} tL
;HMHHu    } tH}1LHѺ    耀\D     H5 L<jt   H5r L$jt   H5v LjX	   H5c Li<
   H5Q Li AG	f     UIHH0dH%(   HMwmu 1t#HUdH+%(      @ 1t1H}LLE
EtH͍ HMH' 101/   럋 uH H}HT'    MH81LEЋM    O'    UHH H   HudH%(   HE1e~HuHUdH+%(   uɉ|D  UHAVIAUATI   SH dL,%(   LmIa+AE  H   A   HLLA$e  H3uH?u0~8uiI$    t^HLHtNHHceLuGHEdH+%(   ucH H[A\A]A^]     A$\  He1@    HUHL\;xAE HuHUHAVAUATISH0dH%(   H]He  t@I$   Hu6LgFLH5 HtHs(HULsIH          L1Å   HP HD    01{-H=s    8  H {x\HCHCHC     fHnHBflHH HS  HH S 蛁ۀ}   LeELcA$e  t	H}Yy%HEdH+%(     H0[A\A]A^] HQ I$   H: H H3 I$   I$   HHY H   HtH9K rL% A|$p@ID$I$AD$ID$     fInHBflHH A$H   HH待 } L@  H "      H=# HH m    i@ Hu   *iuHEHt=HHJ H H 1014+   H    H J HҌ "      H=" HQHڽ     FfD  UH   HAWIAVAUIATMS1HhHudL4%(   LuIHEDMM   f     MtI@I9  M@Mu(  IH  Ae  MI      F  H5/H= LEL]H= /Hh E   L]LEHEA     Ae  g  H]H]LxMMLeL]LED  IAe  |  A$HLAe  8A  xML]MLEH]LxAǇ     Ip(Lٺ   LEL]uL]LEHH5,H= LEHUL]H= hAHULEHV  L]HMXLI@ L]LEI   LEL]Hu4  f     ff.     ff.     HBHJHt(HHBI9rH   I9   HBHJHufIHuLA@LLE\.L@LEIPLH)IP L)L9IGԀ} trIt (LHUZHUHxrtHIII)TIHEdH+%(     HhL[A\A]A^A_]@ H   I9yM@ I| (LHUZHUHyILLEHU?H}^LE/A   I   HEL]4"LEHu  HL]He  A I9@     L)Hq(H9HGIP(Lމs:  
AH(tft
f.     HIH(H|H|
Ix0HH)H)HLHUH]!]HUL]HLEIHuLL]LEA  AǇ  LEL]zLEL] HcML]MLEH]LxHM1>:tt
Ls\I2AǇ  LO\fff.     UHHdH%(   HE1Hb     HEdH+%(   u@ UH5dHSHdH%(   H]HH=  H= T  y:H5#H=䷅ HEdH+%(      H=} H]S= 	H   H   ǃ  Hǃ      fHnH   flHBHH    H~HHs dfD  N uH/ "      H=V HH7     fD  UHAVAUATSH dH%(   HE1     HIH=ƶ IH5
H=h H< E   HEȋ  yLLuȀe  th     Ie  thALH߈e  ?  xǃ     A$   HUdH+%(   uYH [A\A]A^]fD  LH  yH= H5-ǃ  A$	H= n;1eD  UH= HHdH4%(   HuH5	HEdH+%(   uH=> ; UHH  dH%(   HE      u
	1ɉ  HEdH+%(   uɉfff.     UHAUATSH   dH%(   HE1H     H    e  R  H=ô IH5H=e  H9 ǅ8   H0  y>L0e     LHO     ǃ         H@2k   HpE1H  H= H5KH= 9HEdH+%(      Hĸ   D[A\A]]fD  Ie  t3AE LH߈e    xǃ     UD  ǃ  AuD A]fD     H   ~HtTH HtL@ H  E1E    tH4 1D H ~ 01A4 ǃ  ǃ  Aff.     UHSHdH%(   H]Hu"H  HUdH+%(   uH]fD  H*f.     UHH@dH%(   HE1  tdHuH}LEHMHU#uGH}HUH9  r6LELHr*HEdH+%(   HuHMu+A   _    HEdH+%(   u	H{ff.     U1HAWAVIATASH@dH%(   H]HfEHt    1Hu   DCkH   }ELF   Eă<   }   E<   <      A   Mt    Af  E	Af  Hu      DjHueEfADfEf=wJf= uFHtA}0   HD$      HDmjHuE    ff.     1HUdH+%(   uH@[A\A^A_]f   A   ,ff.     UHAVAUATSH e  dL$%(   LeIԀ      H   ?    HIH= H5+H= :Hs E   HEȋ  yOLuȀe  t   @ Ie     ALH߈e  s  xǃ     HLBH5H=Z MH= 4    MtA$    1HEdH+%(   uaH [A\A]A^] MtA$    >   @ LH  ^ǃ  MtA$    1YT@ UHHHHdH%(   HML~4 uHVH+HudH+4%(   uMHVUHH@dH%(   HE1  t\HuH}LEHMHUu?H}HUH9  r.LELHr"HEdH+%(   HuHMu#E1BfHEdH+%(   u	Hc UHHHHdH%(   HML~4 uHVH+HudH+4%(   uMHEUHAVAUATISH DnLw(dH%(   H]HEt08         C$  HCƇ8  H(  CtA$9   t9H{nuQMt
EtAFH HEdH+%(   uvH [A\A]A^]ÐHSH{AAƄ$9  I$0  ?ntI$:  E+nuoCDmA$:  HC'I$G  w E1L UHAVSH dH%(   HEH%} H9tYH9tTH ujz t$~ tHJHFH9   H9s   $HzHuHZHU{mHUHuЄu_1HUdH+%(      H [A^]Ð~ t9rb9rOF9rT9rHOHFH9rCH9`}D  H~HULvHultHUHuR.:V.tHifD  HEdH+%(   uH LH[A^]nf     UHAVAUATSHHdL$%(   LeI8   tqA$8   tf   A$   9   9   $  A$$  9   9   H(  I$(  H9   H9   f     9   t$A$9   tH0  I$0  H9r\H9rcH:  ku#1HUdH+%(   }   H[A\A]A^]ÐI$:  ktN  A:$N  tsD     f     HEdH+%(   u HI$:  H:  [A\A]A^],ff.     UHAVAUATSHdH%(   HE1H   Lw(HIAMt{Lg      L   LA*f`  DDg  AA	Dg  AFH HEdH+%(      HL[A\A]A^]]@ g   ugL   LAAx*f`  g  D	g  HEdH+%(   u5H[A\A]A^]fH   4L1    H   LD  UHAVAUATSHdH%(   HE1H   Lw(HIAMt{Lg     L   LA)fb  DDg  AA	Dg  AFH HEdH+%(      HL[A\A]A^]\\@ g  ugL   LAA8)fb  g  D	g  HEdH+%(   u5H[A\A]A^]fH   J1    H   JD  UHSHdH%(   H]HHtztp      d  ~ tFu;f  H>lHUdH+%(   uAHH]   HE     d  FT                UHAVISH dH%(   H]Ht,1HLHEDEHE؉كf  	ʈf  HUdH+%(   u	H [A^]|ff.     UHHdH%(   HE1Ht8Hp  b  HUdH+%(   u `      	   ff.     UHHdH%(   HE1i  HUdH+%(   u     UHHdH%(   HE1h  HUdH+%(   u     UHHdH%(   HE1Ƈh  HEdH+%(   uH     UHAVAUIATSHdL4%(   LuIE&Hq  )HH2  Lk  LLKMt&Ao   AoF0  AoF @  Lk(M  Lg   >  L   L%g  Lf`  AEH XL1HBd  HL%_ HC@    f%  `HCH    @C0d  1fh  L  ƃj   HǃP     CPC`Cp|jH   ǃX     Hǃ       L  H   H   HEdH+%(   umHH[A\A]A^]@ g   u'L   L$g  f`  	D  H   Ff.     H   FJf.     UHHdH%(   HE1HEdH+%(   u1	f     UHAVAUATSHdL$%(   LeIH( t!Hm I$   Hx 1015I|$P2I|$`1I|$08I|$@ID$H    I|$pzI|$xA$g         LI$   "I$   LHHt0D  IHeLI$   HbL*EHuL&LuOL}CI$   0I$   LIǄ$       HEdH+%(   u\HL[A\A]A^]D@ I$   A$g  A$g   I$   A$g  ?@ ff.     UHHdH%(   HE1Ht+X       JX  9t
BvHEdH+%(   uHff.     UHHdH%(   HE1Ht,X       J9rX  9tuHEdH+%(   u uHEdH+%(   uweBfUHSH(dH%(   HE1H1HtH1HHEHEHUdH+%(   uH]UHHdH%(   HE1@t_@t1f  Hi @1H 01fD  f  f  1HUdH+%(   uff  f  FfD  UHHodH%(   HE1:  HFHG  HEdH+%(   uf     UE1HAVSH N  NdH%(   HE18s t;HEdH+%(   uxH D[A^]8uH:  PA     L:  H:  MDEH E1uMߺ   1I<)HcGHAy/@ ff.     UHSH   H$ HHfdH%(   H]H)Hǅ    HtFuHEdH+%(   u[H]LF(HH( 1      HVfHHH,HHHffD  UHAVAUATSH   H$ H0fH   HXdL4%(   LuIIH)Hǅ    5S      L     PH1MHHvGHLHEdH+%(   uHe1[A\A]A^]@ UH HAWAVIAUI   ATSHHH   LdH%(   HE1I   LcI;   tHs    L1HILH    LH H HE1I:  )   HuHcHM   1Hؑ LiH    LHH1NLLcII^8Ht*ff.     HLu!HIHHuHEdH+%(   uHHL[A\A]A^A_]<ff.     UHSHUH(dH%(   H]HE#u1HUdH+%(   u&H]     }8H߉EE UIHH0dH4%(   HuH֋\  yG'  wlHcH LHH 1M1HUdH+%(   uCf.     Hu؉ULE`[UHuH}HB 1UM @ UHH5 HHdH%(   HE1FHUdH+%(   uf.     UHHdH4%(   HuHu.HUdH+%(   u     UHAWAVIHAUMATSHHXHuHqLEdL$%(   LeLeHMYHMHIHq FHHEH     IE     A$ Ae  B  L)  HUI   L}HHUHE    H}11^bAYH}HED81E   HMM   DH貺   H2IH   HMHHDtQDHEHED8HUH9u8HEL IU HEdH+%(      HXL[A\A]A^A_]     L(;HED8E1@ A$A   I   PHt;H I] L`(fD  X _    D0HE    @ X ~DHE    v    UHAUATS1HdL,%(   LmIHUH5ْ LUIHtHHÀ} u4LL,:HEdH+%(   uHH[A\A]]    L耻ɽf     UHHdH%(   HE1g  HEdH+%(   u1膽fD  UfHAWAVATSHH@dL$%(   LeI)EHE    > t	g  t|H:  0Wt,AD$HEdH+%(      H@1[A\A^A_]@ H   Hu@H   HuH   V8t.H}/ ;>tH:  Vw롐H    tH   HGRHHt.HuHHE/HHU~HuHAD$HUHy8v@ HHuAD$H}u.ff.     UHATSHL&dH%(   H]HI$   H   PtHUdH+%(   uRH[A\]fD  I$   H   贽uHEdH+%(   uI$   H   H[A\]OpUHAWAVAUATSH(HuHUdL4%(   LuLw8M   HH    [@H   @ IH}IO,M} I   BOt.~HH   Mu    Mt{LfD  H}I   мuHEdH+%(      I} H([A\A]A^A_]KftTw@HrL   JCHLs88     E1HEdH+%(   uMH(L[A\A]A^A_]@ HkHUHuH߹   HI;GHSff.     UHSHuH8dH%(   H]HH   7'tKM1H}H    yNxHu   H$1HEdH+%(   u[H]    H   HtHHEHsH}HEHEr5HuHt   H0%D  UHATISHPHFdH%(   H]HHt	sЄuEHMI$:  )   HHMH;HM1M$   H    ]HHCHEdH+%(   uHP1[A\]舸     UHSHdH%(   H]HH6HCHEdH+%(   uH]1;ff.     UHSH(dH%(   HE1f  u1HUdH+%(   u9H]@ HH   H1HUHDuH}HH   輷ff.     UHSHdH%(   H]H HC@    HC8    CHHEdH+%(   uH]`UHATSHdL$%(   LeI|AD$@t$1ېID$8H<HHG(    A;\$@rI|$8eAD$HLID$@    DHEdH+%(   uHL[A\].ʶf.     UHAWAVAUATISH(_@H8dL4%(   LuIA;\$D&  A|$H P  ؉]Eq  I   E1HEf     C]I|$8ED9}|=UI   D)B:HcL,I   VJtzyI|$8D{D9}}AT$@+UHHc]HH4H|AD$@LI\$8FHMf(1HUdH+%(      H([A\A]A^A_]    HuI   蘷nI   I   IV     uT      =HHtYA\$DA\$@ID$8A|$H CHLAD$@FHGfD  4HH@ 1!fUHATSHHdL$%(   LeIHLN5HAAHEdH+%(   uHD[A\]胴 UHAWAVIAUIATSHdH%(   H]ȉ   E}@1Eu' ff.     1T@ E}@@ HD9sIE8LL$I$   ?HuH=L] I$   uLDHL HEdH+%(   u2HH[A\A]A^A_]    H\ 1LL$H芳f.     UHAVIAUATISHdL,%(   LmI   LLLHt:LHHVLT@HEdH+%(   u=HH[A\A]A^]D  LLHHtHHLz3Ӳ UHAWAVIAUATSHH8HuHUHMdH%(   HE1Dc@M.E   E1IE9   HC8LN4I   FuH=[ I   UuAL9CIHtAHY?HEdH+%(      H8L[A\A]A^A_]@ Dc@IE9r HEL(1LIHtHHUHuLH} L   H6LHA$f  A$f  $2Nzf.     UHAWIAVAUIATSHdL4%(   LuIAG@tXE1 IE;g@sFIG8LJ<AՉÅtLZHEdH+%(   uH[A\A]A^A_]f.     1װ    UHHdH%(   HE1HU@H5'fENEHUdH+%(   u脰@ UHH0dH%(   HE1HuH5:HUHUHE    E    MHEHUdH+%(   u!UHH dH%(   HE1HUHuH5vHE    HEHUdH+%(   uϯ@ ff.     UHHdH%(   HE1HEdH+%(   u1H57肯fUH5DHHdH%(   HE1HUHE    HEHUdH+%(   u3f.     f     UHHdH%(   HE1HEdH+%(   uH6H?H-H-"Cݮfff.     UHAVIAUI(   ATSHdH%(   H]HH   LII\$ ID$IH   I] LHu.D  HCHt_HHsLByHCHuHCfI$LLAD$L 1HUdH+%(   u'H[A\A]A^]D  HCL*ޭ ff.     UHHdH%(   HE1H9tkHUdH+%(   u蒭fUHAWI   AVIAUIATSHdL$%(   LeIHtsI4$LHHCHtSL(IT$LhHCfHnLpID$HXfHn1I\$flHUdH+%(   uH[A\A]A^A_]H)Ԭ@ UHHdH%(   HE1~tHEdH+%(   u1@ HEdH+%(   u3~ ff.     UHAUIATSHdH%(   H]Ht#1HUdH+%(      H[A\A]] LuLuLuLuHHtHIE L    t&H[Ht-HsL@yH[    HC I9E _fU葫UHAWAVAUATSH   H$ H  dL4%(   LuI8   L%R I$H  HCO H= ILc+D(B(KM<$K< /  H=B (KDI$J|   HR H8  8    M   IFHHL5$ H(M      1LH(   Lc;I$H(N,D$x$IE I$J< tiIHݒ L9u1HUdH+%(      H  [A\A]A^A_]    H0xSHH+x I$HcH< PyL    q蔩@ UHHdH%(   HE1HEdH+%(   uH\ff.     UHHdH%(   HE1HEdH+%(   u`=ff.     UHHdH%(   HE1HEdH+%(   uɉ'٨f     UHATSHdL$%(   LeIH-H1Hv,A|$-StEH	v_
   H5 I|$-)'HUdH+%(   u6H[A\]f     A|$.yu   A|$/Stf     1'    UHAWAVAUATSHdL$%(   LeLgM   LA6HH  E  Ml$ M;l$t(D  HIH   Ml$ HM;l$uMt$-[   L/H{-[   I/MH8   M  I HJ ML$ MHb H    I܋01HrHmf     HCH9C tfHEdH+%(      H[A\A]A^A_]@ H(HtIHID$I9D$ uHCHID$  Huf     H  H% H   HC      MtHL:LK    L@Kff.     UHAWAVAAUATSH8H}LHuUdL,%(   LmM5 HM    HXH]ZHt13IHt{HEfLMLEALeHMH MMOH D	Mg    A_*H]CfAG(HH 0AT1HI-LrXZHEdH+%(   uHeL[A\A]A^A_]:f.     UHH HL dH%(   HUHAfty uHMdH+%(   u/H)H! HHUH)q8HL HUA軤ff.     UHAUATSH8dH%(   HEHkL x u:LgIMt.LHHtID$H;Ct6ILHHuHEdH+%(   5  H8[A\A]]D  IL$ HS H)H)u?H~:S*
uAL$+I;]f  HLKHefD  At$*HuMH~H<
uK+ff.     LHM;e  LLLIES*1t@teЉ<     << z   <#`I|$-A|$-_   H@ H8_tH)LC-H{-_   LH9_tL)HcH9
U@uLEH}HEHMUH9H9sFEƃ HIE     %-<6(HL4AD$*u     LC-1{-_,ILcIEo1" ff.     UHAUATSHdH%(   H]H_HtII@ HLHmMt(LHII;]uHIEfD  HEdH+%(   uH[A\A]]aUHAWAVAUATISH   H^dL,%(   LmI^  IE-IU.A}-.~ HDH=y HIH fHnH flfHnH (fHn~| H fHnH flfHnH 8fHn~M H fHnH flfHnH HfHn~ H flX~ flh~ flx~ flE~ flE~戃 flEfHnEH   迾HAE+	AE+I$H~      ff.     ff.     HHHH;XrHH1HHufIE AEL)@uEHEdH+%(      Hĸ   LL[A\A]A^A_]fIE     AEM,$Ml$@ 11L %H5 Hw H@ ff.     IvIH=tw HuLʞf.     UHAVSHH0dL%(   LMIHF 4B@DB<ww $ Hsl;$tgI@u׉ULM#uH}Iȸ   }WE1ӟHt@[   HHEM&1HuI~0H1HUdH+%(   uH0[A^]øfUHHdH%(   HE1HEdH+%(   u1n詝f     UHAWAVAUATSH   H$ HxHHHdL%(   LEIHt"AP( JAH(9t
BvH V  LHLMf8H5 HHxHM  ~HIF0ǅ    HLflǅ    ǅ    )`;  HiD z
     IW LpLH   H0   L9y  Hf  <u H  LHL賣IH  I 莙tHxH  P  IEA4 uIGI+IEIE A4 uIGI+IE L9  HMw H;X8Q  HHI~0LF.M  LLMLs-	   LId#H tH5 LS/  L9  IEH tfHnAE f`AEHH;r
H;A3  HDLL@ f  <tL7 L      1   LKLI@M  HLf  AƆi  Af  	Af  I}IH/  @4HH  LL9=MmL9tHf  <  LmHEdH+%(   ;  Hx  [A\A]A^A_]fD  HxM   H HH(H< 01H t,HQ(rq(9t
BvLHH;X8   HH@Lt HHLeIHHxM   HC HH(H; 01Nf.     HHHA8i     HxH$Ƃi  fHxHHA8     H /AoEf`AELL<f     HTH@IG ƀi  LhHQ(@ rq(9t
Bv胅LL1:f.     UHATSHH dL$%(   LeIuYH5 mHtHLHEHMHcH)H9ʉMHEdH+%(   u=H LH[A\])     HEdH+%(   uH LH[A\]N艖f     UHAWAVAUIATISH8HUMLEdH%(   HE1MtI M   E1D  IM9s-K.UHuHM<IHx-t4LsM9rE1MHEdH+%(      H8L[A\A]A^A_]HEHtHM7MtEuHtH} uA     HEHHtHMM4Iu-I~-<tfD  HoHMM4Iu-I~-tQfD  E1C3 UHHdH%(   HE1HǇ       HǇ       HEdH+%(   uf     U1HATSHHf  dL$%(   LeIH0iH   ID$H9rIL$ H9tH9sL   HEdH+%(   u	H[A\]eD  UHATISHdH%(   H]HH;w8t8HIt$0HHEdH+%(   u#HL[A\]@ HHID$8ff.     UHHdH%(   HE1H;   t\H   HG0HtHPH9s"H@HuH   HUdH+%(   u1ÐHH H9r
H9tH9uH@    H   HuMfff.     UHHdH%(   HEHG0 HtHPH9s"H@HuHUdH+%(   u#     HH H9r
H9tH9uH@ҒfUHHdH%(   HEHG8HUdH+%(   u蝒fff.     UHHdH%(   HE1HEdH+%(   u
H0|W    UHHdH%(   HE1HEdH+%(   upff.     UHHdH%(   HEHHH;GHs"HHW@HHUdH+%(   ufD  1近@ ff.     UI1HAUATISHHHwHH@dL,%(   LmILHtHUdH+%(   uAH[A\A]]D  HEdH+%(   u"HsHH{@HM[L   A\A]]f.     UHAVAUATSHdL$%(   LeI訍Lpt,HEdH+%(      HL[A\A]A^]D  I|$8H   1HHHuH<    BIHtmI|$8IHt!fff.     I>IHHuLH"   H Ml$@LI\$H%BfD  111ID$@%UHAWAVAUATSH   H$ HXHH5} HdH%(   HE1Hǅ    +Hi  IHHHL
   H$H   HH   D Hx   'HtHx   H<1H    HDIHx  H1H    HI}1H肇HH < t<	)HHHÅH L1uH
LQHEdH+%(   uHX  [A\A]A^A_]9fUHSH(dH%(   HEH5 x tH1HHu1HUdH+%(   u'H]HHE"H}ЅE	E躍f.     UHAVAUATSH   H$ H dL$%(   LeIH=HtDL   HI /   H%IHtHxH5J x!t4AHEdH+%(      H   D[A\A]A^]     H5 Hmodules HHǅ    ID$C
uLHLHukLLH51lLAqHHt8f     IHLLHI~LHuELHHIHtLLHvI}mL5HufD  UHAWAVAUATSH   H$ H   HpHIHhdH<%(   H}HgHthHI7HHXtJHL   IHH`/   L#IHtH5T Hx~t2AHEdH+%(     HĈ  D[A\A]A^A_]@ e   HAD$kcorfAD$%IHtH Ht4H0Ht,HhHuI$HH9HnHhHWLH`1~pfInLfl),|  s,LHH@XAŅ  Hpg  P	Јg  L9  HH5
LHXHhHH5u ƀ   ʏHu_L9tZHHE1E1     L9r%H L9t+HpHNLH9sL9rL)MuH IIL9uMu LBS(    JK(9t
BvHLLP覩LPHLI HI@HCI@HCA@4C4HA諿ELP+  LM9tvHPLMM@ ff.     HHCfHnHsflHAHI9tL   H{4H|HL9uHPHXH5- & -  LpL`Af  Lp<Ae     LHh|]H+ 0C,   LH    1$k    AfHL9t;@ HHCfHnflHBHH{=HHL9uɋ|αf     |A诱f.     H`HȺ    1vHhHH5W HXƀ  H) H`   H 01Z菆@ ff.     UHAWAVAUATSHH(dL,%(   LmIH5% HE    HE      H]HuHq  H5 Lz  LuH'LL<$  H}LIHMuFLfD  HC I9E    HsI}   LHIHMtHuLHLELHHt3@ IHLLHI螺LfHuH}HHt0IHeHuLHfI~]L%HuHEdH+%(      H(D[A\A]A^A_] L	FLHHt/IHLLHI}L HuAEH}MHHt0IHHuLHI}袹Lj HuA:%D  UHAWAVIAUIATSHH8MdH<%(   H}HH5 LIHM?  7  I|$ +  HHL  I$H  H0H  HUL蜉  I$HUH+PIH{0   H}#H}f  <d  } uLLH3AŅt<HEdH+%(     I|$H8LLH[A\A]A^A_]H     ID$oC0HE)EH5  Lc8fC0M   HEHE    HuLM7I-	   
Ht  IwH}IH   IOHHH+Hx IOIO HpH9sIw HHtINI+IO H0LALMt.LMMPIL;uSL;HEBff   HEdH+%(   uBH8D[A\A]A^A_]     E1C     LX A胁 UHHdH%(   HE1HEdH+%(   u1鎾If     UHAWAVAUATSH   H$ Hx  HhIIAdH%(   HE1:/  H( LL   LH8  Af  1LLHp<(   LAL!Af  LHhHpHp<E1Ae  HpAXE~'H|# LAƇi  H
    01HEdH+%(   u\Hx  D[A\A]A^A_]     LHѾ   HN L育D  EuALff.     UH HAWAVAUATI   SH(H}# dL,%(   LmIHH" 01~WL5& E1fD  ID9;~?I1LLJA~HEdH+%(   umH(D[A\A]A^A_]E1H& x u111LDEADEHtHUdH+%(   u!H(LL   [HA\A]A^A_]鈾~ UHAWAVAUATSH   H$ H   H$ H   H$ Hh  HIdH%(   H]H   zHyM   AHHE   M   LgtoL      Lx A   H1HL   HH   LIHh  LHMxLL	L    HA      1kM   @ HLA   [Lz  Af  AAADy	  Af  E     DmHH"  I:  D  Hǅ    L5 E"  HDL% Hǅ    Hǅ    HfAD  IcL>     LN  DLHADHEQEAe  uEe      HAHILDDA	  EtEIcHiP  HPLAAHiP  H)IfD  LIP  QM9uHdE  AƇi  LH_HEdH+%(   Z  Hh3  D[A\A]A^A_]    H5 HHǅ    IHS	  HLE1HfL  HHL
      HH  XHHc L   LHHHL)P9~Dx   HIcHHHDHD+P99D@      HMcLU{H
  HAH~0HuLD  HLLU~AAd  "D  HDL% Hǅ    Hǅ    HAd  IcL>     Ad  9@  HA   LHsM R  LcHMiP  L  8   CI    l  HLHT  HHxH   HxHxK   HLLzwI   H(x.H   H Lf.     IH I9|HHDDH	H  HAIk  H5T H    DED  Af  <0IH I9k    Af  <fD  HA   LHkK JLcHMiP  LHq  8w  I   H    Af  uffD  HA   LHJ 貿u>LcHMiP  L}  8W      IH] I9;    Af  <hfD  Af  <fD  HA   LHJ uLcHMiP  LH  L8K  I   H`+ M   @ HLLd    HLLDH V  H   L CI      HL*
H  HHxH   HxHxX K  HLL臃6I   H1fD  H I   fH߾   )H8  Hǅ    ؂HHIDHLʚDD      AHHH5' HHLHG{fIHp I9Nf.     fD  L  I       H ?  LAADHHH@ L0   H L貶Ae  uAe  Hǅ    L I    {Cp@ I    CC@ L0 LLuDADOEHCL   AI    C  H L褵  Ae    Hǅ    L H (LRAe  uAe  Hǅ    L AE%M   HQHH I   L趴)  Ae    Hǅ    L]HH I   M L5 1Mn8MT  HLL蠞Aą   HHH<HHX8IH/  LHLLOAąH} Hٿ   H 01襴Ae  AƇe  Iu01LLÃL;HLgH L   H 01/HAe  SAƇe   1H5"y L
HH;HA~ w  IV0H+  A~ j  H H8 tHLAąI8  8 HfI:  )Hǅ    HHd  HH=2x ak  LHߺ)   LHkM   HH1 Lt Hx 1H5H赓HHd  LhHLHM:  LLLHLQIH  MEHHxw 1   LL IHtH Ht+H0Ht#HLruIHH9puLLyH   LHLHHHiIML@   ME(      1HH HLLAADHHA~ E1111LHt"H   HL蔫AąYA~ SuHb HPXHu^HX`H!    H    LH   HLtH  HCIH1LALLHHH uOL5ȫ  tLIuL5 HL   H tHH Hk    HHH(1H~IAe  0Ae  6HLnAĄ{11H= xb虔H-IHtGH H.H0H"L5ʪ HLouIE HH9pDiH t@Hu;HHAIH LH 101خHH uuHhHmHLLxHLLxx UHAVSHdH%(   HE1Ht#HH1I=HHt%H @1HUdH+%(   u,H[A^]H LH 101hh     UHAVSHdH%(   HE1HtHHIHHt1HUdH+%(   u,H[A^]HF LH 101qgD  UHHdH%(   HEH x ux uf@@1HUdH+%(   u"H
 Hr 101sg UHAWAVAUATSHXdH%(   H]H' { t)1HUdH+%(   U  HX[A\A]A^A_]D  CIfC{   HCHHt	8.  H   H   IH  HHP  @   1HLHǃP     E1LP  A= AD$f=!  IDALHHDHI!ALfA9|LHsxH   H? v  H   H   H v  H   H   HT 螝  H   H(  HT |x  H   H   H" JvJ  L   L}M7  1'H0  H  MwMQ  LE1蟩IgIHEHEHf.     H0  L   H}LAYM   LMEIAE     Hu   I~]IAE uINHUH9t: tHLMHMHU׾HMHULMHDH9]H5 @ HH9C uH91MX     E7  H   H  H t  H8  1nHH  8/   x    H8 H8  H9tH5q H= Hu"   IcAM  L   H}H   
   1H}E   MLA^h	DkC@ H 1AH̣ 01軨Lf     H8  *@ H0  H!Hǃ0      LXD  LIgcAEA	EfD  Lg;AE	A     H8  ?/ nH   H0  hH(  \H   PH   H   HL H] 101zH. H 101\afUHAUATSHdL$%(   LeL%	 A|$ u#HEdH+%(      H[A\A]]D  I$  3I$   &I$   I$   I$(  _I$   RI$0  EH& L- x& ff.     IU HH<QyL    :fAD$ IǄ$       IǄ$      A$   `D  UHHSHdH%(   H]HHE    蓯HL H8  HtP1H}Lk HHj    x+H}H}Y1HUdH+%(   uH]f`@ UHHdH%(   HEH Hx0Ht   譱u\H Hx8Ht   菱u1HUdH+%(   u:Hq HH8H H 101HF HH0[_ff.     UfHAVAUATSHPdL$%(   LeI)E)E)E)EHx  f  k  H @s  LHu褻H}c  HEHI  HD HH   /   ?   HA   H  HH9HCCH H9qCHHH9HHCƍqH9CHHH9H?HCƍqH9CH4    HCH?II    1fD  I I w;HLIVHH      LH}Huf     HEdH+%(      HPH[A\A]A^]D  Hi @1f     H  1L @Ɖ襀HHuLufHHy   L|Hd@ H       cLE ]UHW-Ag   HHG*dL%(   LUIt<EAAwHHO   1RLG H LL[HHUdH+%(   u\@ UHAVSH0dH%(   HE1HHugtCt?HN HҐ L1   ZLcHEdH+%(      H0L[A^] H-f    L1ZLcD  HuAHO-H* H}о   LLEyZLcEttLUL]LEIK I;J IBrISHH)H L1   LM/ZLMHI?l[ff.     UHHdH%(   HE1HEdH+%(   uIй   1X![UHHdH%(   HE1HEdH+%(   uI1HXZ UHHdH%(   HE1HEdH+%(   uI111XZfUHAVAUATSHdL,%(   LmLoHMtHII1E1ff.     IF@H    LH1HH-XHII;^HrHEdH+%(   uHL[A\A]A^]Zf.     UHSHdH%(   H]HH?jH    H{諐HC    HEdH+%(   uH]Yf     UHHdH%(   HE1HEdH+%(   upkYff.     UHATSHHH>dL$%(   LeIHIL$Ht!Q(@ rq(9t
BvHKID$HCHEdH+%(   u	H[A\]X ff.     UHATSHHdL$%(   LeIiWID$HCID$ HC AD$(C(ID$0HC0ID$8HC8HEdH+%(   u	H[A\]_Xf.     D  UHAWIAVIAUATISH(Hc  dL%(   LMIɋxu;LLE1m        LELMoLMLE      A<$ tLLL1H& LELMLLELMHcIH)LLL萱AŋtA<$ uPHEdH+%(   uhH(D[A\A]A^A_]    LELM]LMLE]    IcLHR H)I<H,& 1>AW@ UHAUATISH(H dL,%(   LmI3xGuk   LnAtA}  uxHEdH+%(      H(D[A\A]]    HMHUtnHUHMtX   A}  tLLHMHUWHMHUn L      DEH=Q uDEbfHMHU[HUHMu    U    UHH   LpLxt )E)M)U)])e)m)u)}dH%(   HH1HEL0ǅ0    H8HPǅ40   H@HHdH+%(   u;Uff.     UHH   HhLpLxt )E)M)U)])e)m)u)}dH%(   HH1HEH0ǅ0   H8HPǅ40   H@HHdH+%(   uT@ UHHfTn dH%(   HE1f/j H\ sf/j H҈ H( HFHUdH+%(   uTff.     UHSH(H}dH%(   H]HE蕁EH}HUdH+%(   uHH]HƸ   xS UHSH8H}HudH%(   H]HE1EHuHUdH+%(   H}uHH]H¸   PKSff.     UHH   t)EdH%(   Hx1EHEǅd0   HhHPHpZlHxdH+%(   uRUHATSHH   HXt)pHpHDXdH%(   H81HEH(H@ǅ    ǅ$0   H0EHHHH¸   H8dH+%(   uH   [A\]Q@ UHAVIATSHHdL$%(   LeAHtBH5X H5   H5G H   tTH56 HtHLtcExfEtIH=! =HtHH5 HHUdH+%(   u9H[A\A^]    Vu    1@    hAPf.     f.     UHHdH%(   HEHFH9GtHUdH+%(   u    1P    UHAVAULn(ATSHH^(dL4%(   LuIL9t?L#fff.     H{觅H{@螅H{8蕅HLZM$$L9uHEdH+%(   uHL[A\A]A^].Of     U8   HSHdH%(   H]H艑Ht.oHH( oC@oC @ fHn@  fl@(HUdH+%(   uH]|Off.     UHHodH%(   HE1oGBoG B oG0B0oG@B@oGPBPHG`HB`HEdH+%(   u1OUHAWIAVAUATS   HHFdL4%(   LuIH8A@ IHUHA uIF   H8TAfD  ٨I~HUH蹹A uDD)HUdH+%(   uH[A\A]A^A_]1NUHH HdH%(   HE1Ht(H5 HUlHt@tHU09rHEdH+%(   u	1ÐM    UHAVAUATSHdH%(   HE1H tgIH0 t]II1H=DHHtEHsHtI|$0tHEdH+%(   u=IUIE HL[LA\A]A^] HEdH+%(   uH1[A\A]A^]Mfff.     UHATISHHvHHzHdH%(   H]Hu-HEdH+%(   u6It$ H{ H[A\]     HUdH+%(   u	H[A\]L UHATSHH dL$%(   LeIMt]H5} L   H   LeLHHcHU#ft?;   HBHtHXMu@ 1HUdH+%(   uUH [A\]fD  HU;t       f     H5d L!KD  UfHAWAVAUATMSHH   HhHM@DHH0dH%(   HE1H H    )EHE@e  El$Ev  Et$E  Et$E  Et$E  Et$E  Et$E@  Et$Ei  Et$E  Et$	E  Et$
E  Et$E  Et$E2  A|$   A|$ =  EuH;H.   HHE    HE    Hp H0  ƅD A   1LeH(L-~ HPH<H  L=' H8L`IfD  H`I   H~ 0H1.HO&  E  H   @   HH  HHLHXH)Z{   /   LU   HX@   HXLHIH)HqH{      H5} Lzu|   LXLP7!   LuOLLL)r0u:CH   DLDIHuDLt@ HUdH+%(   	  He[A\A]A^A_]ÿ   褢H\H3  H;HA|$    rH*H  H;H趘LXLP   H5Xx LyVMt I~IvLHy1Hh t&Hh軡HhLHyyE1MMH(H8H Hp HH9@At"H t1H5&| LVD      LmA|    Et_IHILLHxXHCH  A|   HH  Et E  ,   Lt ƅDDD  :   HIHt{HH)HL:x   H5{ Lx*,   LsfD  {   LSffD  HH{H:胿HoEl$E   H讔H  H;H:Et$Ed   HyHP  H;HEEt$E;   艟HAH  H;HEʕEt$E   QH	H  H;HE蒕Et$E   HѓH  H;HEZEt$E   H虓Hp  H;HE"Et$E   詞HaH8  H;HEEt$En   qH)H   H;HE貔Et$	EE	   9HH   H;HEzEt$
E
   H蹒H   H;HEBEt$E   ɝH聒Ht\H;HEEt$E   蕝HMHt(H;HEړH=w )HfD  Le:H`HHG  L HM1Hw Lp   A2LX%LLP[H1E1j D@LHHuZLXY  H f)EHMH`L1L9'  DH]L-&w LHLX ff.     I      H}   HEHE      M  A7L@uB   A0HH  At HLau)At$IL$@   @!tHItLXn  M6L9`PDHLXhehH`H0Hǅ`    H HPhH`BLh    M  L	H}I  H   I(  H5u H4I(  uL}@   LH*   ff.      /Hx@   HuHh t&HhtHhHH2rL}L>I(  HLXH߉hhf     1HքLXLHL11H LXA2H路mHpHPUHuHPhOh4Hh  :   LiH:   H3H}h'hHHf     HG> UH H5zo HAVAUATISHHL2dL,%(   LmIHLHDtLH    uI]I|$H   t%HUdH+%(   u(H[A\A]A^]f     I|$H>f     UfHAVATSHHdH%(   HE1)EHE    Hu)E)EHtoHAHtH  HtHEHuH8Ht#HUdH+%(   u8HH[A\A^]f     EtHuHHuH뾐1W=    UHSHdH%(   H]H.H7~& fHnHflHC(CHEdH+%(   uH]<fff.     UHHdH%(   HE1HEdH+%(   uP<ff.     UHAVAUILuATSH]H0dL$%(   LeIHuH}LeHEH;HtLLuHL9uHuH=rtHUdH+%(   uH0[A\A]A^]<ff.     UHAWAVAUATIH5	q SHH   E HHL}Lm( ED D(dH%(   HEH`HE    HǅP    HE    fHnHfl)`H߉mHH  LpfInHX1fInfInLflfl)0)@H5 HXIH,  :   L1Ht  HP fo@HUH5L  fo0HUE EHE    E(LmL}E)p)U[AHpEt`L@L9t'H`HxH`HHpHHJA   HD@0D@   @ } t4L9t'H`HxH`HHpHHJL@L9t'H`HxH`HHpHHJH܃ H@Hz 101~H臵AH`LHL9taL#ED  HSfHnH{PflIT$L"onH{H{(]nH{`4HLLM$$L9uEHEdH+%(   H  HeD[A\A]A^A_]HH@Ҵ=;  uY:  H1H  tNDE  H`H;    f.     Hyۃ Hy 101}H`LLeH;   -  }    }    }   } ,  } Q  } v  }   }   }   } 
  } /  } T  } y  HL9  } h   辑H{LH蟢GE} C   菑H{LHp"E}    `H{LHAE}    1H{LHE}    H{LHE}    ӐH{LH贡E}    褐H{LH腡iE} e   uH{LHVDE} @	   FH{LH'E} 
   H{LHE}    H{LHɠE}    蹏H{LH蚠E}    芏H{LHkE}    [H{LH<fHEL9bIH   H`LL9u   ff.     HL9   {X uH{( uHCH HP HtE1HHN<MuWD  MMt>I?oH	  HLAtLD@D@HCH HP II9r`ID$    LLHAI>蜭HuL贍LHHPE11PLML1	L@{AXAYD@E&HPH@Y  H`H;  L@IڅMtAzX t\    Mb(HIB`IRLML@EBXL PNZL@AYyMr`IBH H   IBH5]c L@HHL@  vL@  HL@3L@(HL@   HxH hrL@HI  M.M9  LH@L0E1(u6I   t,LĎt I  HH8  fL(AHE  H@AFILd    IM9  I?@HHuMm L90[LLL0L@H;   E1H  trL@fO$AƄ$  LM$  s@HM$$M9t,L_@HHuKI$  M$$M9uIL9 uL@IH Hy  HL@@H`L@IHH9  L0E1IH@ IF1LH8ƮM6AI9uIcL@L0H(H L@&VMoL@M   I_L0H@LLLD  L8?L`HM9  E1fIG1HH8M?AM9uMc䀽0 a  L;(sLUL(0L H@H@LhMpLLLHH    L@H
  P   HpL@HIK  IBPL@ID$@IB0IBP    ID$MB(IJ M  1H}   HVK LL@mHEID$H  AzY   IB8HS(LPfHnID$ IB@M|$8ID$(IB@AD$HIBHID$0C HC(fHnL`flA$Lc(ML;L@MtH@HH<HH`LL9  Hs`H  H;HL9uE1%fD  HHUH	L蝨Hٿ   Heb IHtЃ 01rH@IFN,H;   I    L(SMm L90D  H] Hǅ(   sE1=H{L@ID$.IIWHtfD  Hƀ  HBHuII9H  Ht   tƀ  H I9uH`H;L9Mb(LMRHt@L=u4I}HsHtYHt""uIuH{l   Me(HL9t"L9tH{` tHs(MuHtHL9uMHuLL0I`HL9Hǅ(    LH  LLlAHo΃ HK Hm 1LC0D@01pD@HH1mH!΃ IM Hm    LC L@01=pLs`L@M@ H@ E1AKz*L袦LqLA!ALH>1L贂H`L9A=    UHHdH%(   HE1HEdH+%(   uɸ   )f.     UHAWAVIAUATESHXHEHNH}HUMF   H^ HEHE LMDmHEH̃ 01dL<%(   L}L}(nI~?   脱H   LsR   ALuLuEEAԉ]1ff.     HAكAWuuAUAVDEMHUHuH}  H0A9~tHUdH+%(   uRHe[A\A]A^A_]    HAE1AWELuuPuHUH}R  H0@ 1o(@ ff.     UHAWAVAUATSH(dL,%(   LmE1H    HJHHIH: IH5X HHHMHDHU;tHuH}*uQHCI|$HIRt^   {( tsHSH;C+LAVj j C*PLK DC)H AHEdH+%(   uKHeD[A\A]A^A_]@ I|$LE1tf.     I|$HLx6'fD  UHAWAVAUIATSDH   HEHLu(L~H H(EHE DHdL$%(   LeLe0LPLXMuafD  MvMtRI6LԺuHɃ LHi 101kHUdH+%(     He[A\A]A^A_]H t^HHxPH  H7H     I!f     HHI4H  HL0u1vh   ZH0IH  IGIH   IE HƐ HHDHF IGIEIG IEPIG(    HHDIGHH  tH tH0HA(HtWIEH0HA0IE HA8IE(HA@IF    LqH( t_H(0tIFH0LpI~ u=H0H{PJZH{~H{(8ZH{`HNH0A^H@H   1H0AXAE`HAP    AYHA`    I} H7   tI}HY HPH01HP艹   H0HH{PvYH{}H{(dYH{`;H#HysLIHcHHHAPHIUH1HJ0IUHAPJT0HAPH    HAPHD    HQHI}ǸH0I} Ht	?   1芏IH0HxHHp H  E111D  HHL,M   H`H8H@LH IU L@LHkHH=t|AHIcLkpLHH  fo`HUBD fopJT BD foEBD foEBD foEBD foEBD IU JT MmMOH0H8LHHxHHp HH9E  IcHHL0IHkpL<L@@ I~HshHp诸I9uHHLPDH8LMAĉHfD  HpH9@tzAUDHAV0ATL(DHH HxH tH8H^HH D  E11۾    )H8%H HH0HHHH1HyHRImAE\        +tyHÃ IMH4c 101e H0AXAE`HAP    AYHA`    I}  I}1HB   nu u*   t&H Ã IMHb 101Jec 1H0AXAE`HAP    AYHA`    I} H9^H,{ff.     UHAWAVEAUEATSHHH}L}HuDeHUMdH%(   H]ȋ] ygIuJEMAPEj EATAWHUHuH}HUdH+%(   u8He[A\A]A^A_] HEH Ha    018dLEfff.     UE1E11HHdH%(   HE1VH52O jj j jHUdH+%(   uT@ UHATISH dH%(   H]HyfHUH5NLeHH]>?HUdH+%(   u	H [A\]ff.     UHHdH%(   HE1E    	f1HtHUH5wHoUHEdH+%(   uɉ@ UHAWAVAUATSHXHUAdH%(   HU1҅X  E    IHHMuH}0LIH@   軼IH  H}   H螸IH+  E$   M$(  H HtHK H H_    LU012bAE LUIU(AB M}(I9  IB(HUMHEH]LUP   3^IH  ID$IGID$ IG I|$kkIGHw  ID$(IG(AD$HAGHID$0IG0ID$@H]  IG@    ID$8H8   H1HAՃHx uA}   Hc&\IG8H   A1McIf.     IW8HHL9tgID$8LH   (HuI8PI@PL虗@ HUdH+%(      HX[A\A]A^A_]fD  HMHA(LxfHnEALy(M$$L;eH]HMEE;A1두      1[IG8HuI@/PL]D  H8 tR   1IHvJ<( uHc   ZIG@Ht.It$@LH]f.        E1QLy    UHHdH%(   HE1HEdH+%(   u1fff.     UHHdH%(   HE+HUdH+%(   ufff.     UHHdH%(   HEH+HUdH+%(   uff.     UHAWAVAUATSH   H$ H   H$ H   dH%(   HE1D¾   H\ IHT识H# L   HH1+H0H8`   t/HEdH+%(   D  H   [A\A]A^A_]        HHHM LHRu3   HHHM 菤IuHtb   HHHM QIuHu¾   HHHM IuH讍uHM    HHIuH(HIANIUH( I}H5M    HIEH1茣IEH(HHH   IUH( I}{HL    HIEH1&Iu H(Hu:IM H( I} IE LLVHKLK= UHJL HATISHHdH%(   H]H   H`1HHEdH+%(   u%I$H߾   HL HdH1[A\]	f     UHK HAWAVIAUATSH(HdL$%(   LeI      XlL  1L_I   LHK    1@(  CIDHE(@ ff.     ff.     IL9m   IE HtHrK L1   IE    LH]K H1IE HtE1L@ HKHpK L1   HK   1HhK L|IE HIA9XHPJHtHJ    1LCI   vHKHJ L1   h     HEdH+%(   uH([A\A]A^A_]=fff.     UH   HAUATIH=J SHdL,%(   LmI   2I$   ~@1 Hؾ   LHHHP  HJ HL@1aI$9   HEdH+%(   uH[A\A]]fD  UHPJ HHdH%(   HEH,  D$  D0  HJ HDHEdH+%(   uHHV    1fUHHdH%(   HU1HUdH+%(   u(HHV H   H H@  HH01nf     UHHdH%(   HU1HUdH+%(   u(HH`I H   H Hi    1Yf     UH   HAUATIH=4I SHdL,%(   LmI   1I$   ~j1 L      H=I 0I$HLH   HH  HHH LHL@p 1YI$ZY9   HEdH+%(   uHe[A\A]]|ff.     UHHdH%(   HE1HEdH+%(   uH      H=^H 0'    UHHdH%(   HE1HEdH+%(   uH2      H=T /    UHHdH%(   HE1HEdH+%(   uH%      H=T |/    UHAWAVAUATSH(L/dL$%(   LeIAElE   EE~DI   E1ff.     HHiG L1   AH;jH\E9uE   E)    I   E1HH1G L1   AsHiH\E9uE   E~DI   E1ff.     HHF L1   A#HiH\E9|A      I  H&  u~NLc1@ I  HHپ   HLHHHNS DHD@ P1XZI9uHEdH+%(      He[A\A]A^A_] E   E     I  HtRu~Lc1fD  I  Hډپ   LHHHH"S DD@1I9ueHEdH+%(   uaL5      H=S He[A\A]A^A_]-HEdH+%(   u+L=      H=qR E   EBfff.     UHHdH%(   HE1HEdH+%(   uIH1H!E    <    UHHdH%(   HU1HUdH+%(   u$HHD H   H H   1-fff.     UHHdH%(   HU1HUdH+%(   u!HHD H   H HHx1UHHdH%(   HU1HUdH+%(   u!HHYD H   H HHp15UHAD HATISHHdH%(   H]H   Hh1H
HEdH+%(   u%I$H߾   HD HlH1[A\]
	f     UHHdH%(   HU1HUdH+%(   u!HHC H   H HHX1e
UHHdH%(   HU1HUdH+%(   u!HHC H   H HHP1
`UHHdH%(   HU1HUdH+%(   u!HHFC H   H HHH1	UHHdH%(   HU1HUdH+%(   u!HH	C H   H HH@1u	
UHAVAUATSHHdL$%(   LeIL`  L1H  __HHtW    HINAN   LHHB 1HuHEdH+%(   u"HL[A\A]A^]pH=WB tP
fff.     UHAWAVAUATSHHdL,%(   LmIL`  Lc@L1H  ^HHtQHIMILLHHOHuHEdH+%(   u)HL[A\A]A^A_]D  H=A OM	fff.     UHLN HAWAVAUATSH   HL/H   Ic   MH  dH%(   HE1M@     H[IHfff.     IAwIMH  蘪2   H I
IAwd   H`xIO1HL`L    H@ L9uHEdH+%(   uH   [A\A]A^A_]fff.     UHAWIAVAUIATASHc1HHH7dL4%(   LuM#tH   !   H HHHPHt-fE    I>LmDeEEx  u4HH}HEdH+%(      HH1[A\A]A^A_]    A~ uHHHL    1Hi H? 101L HI IAHDL    01nLn@ UfHAVATISHc1HHHGdL4%(   LuMHuH7EEE    MHuHErHti!<H} HHH@HtBH}LHUdH+%(   u[HH[A\A^]ÐHy ٿ   HK 01K1fD  HQ I$AHKK    01uK1ff.     U    HAUATSH8L/dH%(   H]HHuI(  H
  6HM   1H.> H6I(      HuH
  z6HM   1H> H I(  H
  H+
  xIfH*HK    H߸   ^ HEdH+%(   u+H8[A\A]]D  HfHH	H*XUHAWAVAUATSHdL$%(   LeL'I$(  HH9   IE1L56 H9   tME   HH-    LH1A   I$(  HH9tmH9   u   ~HsH0     LIH< HID1   HDxI$(  H9T ff.     HEdH+%(      H[A\A]A^A_]fD     pHH9tH9   tHH9tE1H9   uۃ   9@ L      H=4< 7"I$(  HH9cH9   u UHAWAVAUATSH(HdL,%(   LmID   E   H   HEL5; HEL= ff.     Hu1eH];:ulALLC   H; L1M9H{\H|AuL
   HBHEdH+%(   uoH([A\A]A^A_]f.     L      H=DH !D  HEdH+%(   u'H(L      [H=G A\A]A^A_] D  UHAVAUATSHdH%(   HEH   ~uIIE1f.     L   LIHH8  1LKHG LC Hk: 1   L H{Lj	ID9   HEdH+%(   uH[A\A]A^]fff.     UH   HAWAVAUATSH(H}HH= : Lc   dH%(   H]H   E   J    E1HEff.     HEH H   N4 LOIH   I%D    LH9 HLx   1 '   LsHuHLHl 1   LM|IL9eoHEdH+%(   u6H(H޿
   [A\A]A^A_]?LH H1   |D  U   HATSHL'dH%(   H]HL}   H{ uRHLpÅx!1HEdH+%(   u[H[A\]D  H HE    01DfH HF    HE H81 U1HHdH%(   HE1yH?HUdH+%(   uUHAUATSH   dH%(   H]HH9tkIIHu   ff.     HI9tH{uHP   usLmpIH   H(   t7LP  HI9u     1HUdH+%(      He[A\A]]HLHHpHP      H@1L    HHKHHLL@HH(  ZYgDff.     HI9d{uHP   uH H6    01B0H K   H D 01B8     UHAVAUATSHHdL$%(   LeILc   E   H      1LH h H&6 E~FN4Hr L- @ ff.     LH L1   HCLL9uHEdH+%(   uTHL
   [A\A]A^]C< HEdH+%(   u)HLHag 1[HC A\   A]A^]# UHAWAVAUATSH   dH%(   H]HH7$   h  H  D   HSZ/D HH	HHHS㥛 HHHi ʚ;H)HHH  H HHHH	HHHHHi ʚ;IH)INH  H}H @   H4 HL@d<@   L1DHH4 0DE   HHHo4 1DHLHPHA    1AVATDLTH HEdH+%(   unHe[A\A]A^A_]fHEdH+%(   uNHeHٺ      [H=3 A\A]A^A_]:f.     H<error> L@H@# ff.     UHH Hw dH%(   HUHJxHEdH+%(   u(ɉ EH H@ 101,?MfUHH dH%(   HE1H uVHH@  蜙xHEdH+%(   uZɉ EH H@ 101>M    Hy H"@    H~? H81     UHAVAAUIATSH   HL% dH%(   HE1    HP2 A4$'>EtZHtHڸHH9u AEA4$1H@ 1   =1HUdH+%(      H[A\A]A^]@ 1HP   H       PH9t   HX   H       XH9u/AEA   A4$H?    1m=z        H`teH       `H9t   HptKH       pH9tHxt"H       x   H9z   @ ff.     EEbaUHHdH%(   HE1H uHEdH+%(   uIFNfD  Hq H=    Hv= H81HEdH+%(   uɸUHHdH%(   HE1HEdH+%(   u1fff.     UHAWAVAUATSHH   HXdH4%(   HuȋwH0  [H   ICf	     f   f   E1HXLIH   A   f{ yDs HsLHpLHpL=Af  @E   I:  )   HuPH    MI   LEHv= 01;Le>HEdH+%(      HĈ   [A\A]A^A_]fu&D  A   D  A   	D  HXf   H`)`u	l u0Af  D	Af  H`qf.     LH`L    UHAWAVAUATSH   H$ H   H$ H   H HH(dH%(   HE1H0H94  H`IAHH8L-@ H8LL~fHH;0  H8$   D*H$y  A~   fLDLzL*L9L  Hnel.kallI9$xHallsyms]I9D$cH(1Dǅ0    _H   H HH(H9   H@H8   FHDLbL)I9   H@oHHHHHLH f؉HXHHH;(sDH8    Df)H u A~ EH8Y4@ ǅ0HEdH+%(   uC0Hĸ   [A\A]A^A_]    H8I    ǅ0    @ ff.     UHHHWwdH%(   HMHO H?$uHEdH+%(   u'1D  H H9    017D  UHAWAVAUATSH   H$ H   H$ HH	  HHdH%(   HE1^H*    HH1U}  	 H1貓Hǅ      Hǅ    1E1E1fD  H  HJHzHHJH)Hz.u tĀ?.u.u	 t 1HH5Q* 3  L;r%Iu   LHh  HIDL]MH8    HH1A|  	 H1螒HǅH    @c  KDm E1HXM41H~{HPJHzHHPJH)HHz.u t     ?.tsH1H5S) 2HHA9ACԃDDH@ @1`  Hڿ   &DH   HPHZfD  .u 8x H1`  Hڿ   CH  HH    @IAHD  At$@   Hc.IFHa  H11IAD$@IFZ1HǅH    ff.     H   HPJHzHHPJH)HHz.u
 t@ ?.   1HH5' B1u!   HHH%IFH	HHHuff.     @1`  Hڿ   vBHHPH>fD  .g X    E1   LLHHaL(HL8_}HEdH+%(      HH)  D[A\A]A^A_]H  H1AHJ5 01A2FMt"KDm I_Md H;HhL9uLhsH H1AH55 011H LHZ3    Hf4 A011@AfUHAWAVAUATSH(HdL$%(   LeIHp@HE   Hu   E1L- @ HULHHX  HH   LxH$ 1L   &~7LcH K@ MH6 L1   ILL9uL
   +HEID9   iH} H5 HAt=HEdH+%(      H([A\A]A^A_] H1    L1rH}H5$ tH}HL H5U Ht1
   HQVuHEdH+%(   u'H(L{      [H=U3 A\A]A^A_]7	BfUHH HwLdH%(   HMHHtPHAHQ H)H~xHHHALHUx HHHE1I   HUdH+%(   uW@ yHu   LEHM HMLEHt!HHHIt     HHUrfUHH HWLdH%(   HMHHt`HqHA H)H   H2I  HAHx u1HUdH+%(   ud    I  HI  D  yI     LEHMHMLEHtHHHItUHH dH%(   HEHL@  Ax!    HWHHtVHwHG H)H   H2I@0HGHx u1HUdH+%(      @ I@0HI@0 Ip0   LEHMHMLEHtHHHHЉЅu H! A  H! H!    H81Vc    UHH0HwLdH%(   HMHH   HQ HAHH)H  H<HHAH}Ax ueH)H   HHHAHUH	HHȀy HMHEI(  H
  I(  H
  1HUdH+%(      HH}HA yHu   LEHMwHMLEHuyHHqx    HuCyHu   LEHM:HMLEHt,HHHIt[HQ n    HU    HHHIupHEHHEl@ UHAWAVAUATSHxHOL7dH%(   H]HH  HCHS H)H  HHLHCHU   He  HKH  HS HCHH)H@  H4HHCHu 0  H)H  HHHCHUHx "  H<RH)IH  IHEE1HpH}   LhLmfD  HKH  HS HCHH)H  H4H;HHCHu tHHuHCHH)HQ  H4HHCHu tHHuHCH)H#  L4HHCLu tILuAv?   Hce$IH  IF?H   LeMLxA       LsMC  HCHS H)H  IHHCI$H; tI$HI$HULJ?IM9  M3  LILeL[HcLxLS Hf.     HHCLH)H(  It IHHCH tHHHL9rLufoEIILmAGHEIGHEI9LhLmHUM@  A   1IH  HUdH+%(     Hx[A\A]A^A_]f     {   LPHHHHIxNHUHB?HI9a  II\@ HHHItHLmLJ^UMLmL1^    {Hp   HuH;HK   Hux{Hu   H}   H;HK   HuW{Hu   VHt HHHIDf.     LuH;@ HS     HS     HHHIhD  HHuHCHHUkHHULeLxI{Hu   HtHHHIH;HU	{Hu   [HuQHHKx ucHu6{Hu   2HtHHHI,HUHS +HHHI1?HEHHEHEHHE\HEHHE UHAUATSH(HOdL,%(   LmIH   IEIU H)H   HIEUIE x uyAL>!HH   IuHtiIMIE H)I9HLHHMWWHMIIEHEdH+%(      H(H[A\A]]f.     ʉUf     A}LHI9tHHHItH[1fD  A}HuԺ   HtHHHIűUUHATSHHdH%(   H]HHxxZL#HzID$xHHxx t1HUdH+%(   uH[A\]ø%D  UHATSHHdH%(   H]HHxp%ZL#H
ID$pHHxp t1HUdH+%(   uH[A\]øD  UHATSHHdH%(   H]HHxXYL#HID$XHHxX t1HUdH+%(   uH[A\]øED  UHATSHHdH%(   H]HHxPEYL#H*ID$PHHxP t1HUdH+%(   uH[A\]øD  UHATSHHdH%(   H]HHxHXL#HID$HHHxH t1HUdH+%(   uH[A\]øeD  UHATSHHdH%(   H]HHx@eXL#HJID$@HHx@ t1HUdH+%(   uH[A\]øD  UHAWAVAUATSH8HHOdL4%(   LuIHEHG  IVIF H)H   HIVHUEĀz    Hu   IV H|HEH   EčxHpHEHtiEE1E1uL   D  HEDHMHHMJIA5H}HHPFl(SH$WD;es^LHHuH}WH}V    HUdH+%(   uzH8[A\A]A^A_]fȉEfD  HEHuH   HuH   1fA~Huĺ   .HtHHHIvIE2fUHAWAVAUATSH8HOL/dH%(   H]HH  HCHS H)HM  HHCLUx c  h  A      H}2  E     fD  HCHS H)H   HHCUHx tEȉEHtIH   UHH}1H51        H5ȭ H}xmH5 L@mu
EA   LUm   HKHC{   HuHKHHHI5H}H@ HUdH+%(      H8[A\A]A^A_]fD  ʉUH{ H-    011 {Hu   HtHHHIrHU+I   $T1H}I   1KfD  UHAWAVIAUIATSHHHMHuLELMdH%(   HE1    H    HOH  HGHW H)H  <HIF}Ix tω}u+1HUdH+%(     HH[A\A]A^A_]    H5IE H  E  E1V     H5r H!k   H5m H
k   LIRHREA9r  LHH   LIH   IH}1HH7    -k   IE HUH5 HJzjB
   1LAHM(     
   1LAHM4fD  
   1LAHMfD  LQHQA\$HEtfIE H<HQHuI} QHEIE          +@ Hu   /HtHHHIuɋ}1fff.     HM UHAWAVAUATSH(HHOdH%(   H]HHEH  HSHC H)H  HHSHUEĀz       H	IH  uą  IIE1EAA9snI IOIWLHMOMG   HeIGH   AuHjw H   1A2H EA9rHu   LX  1HUdH+%(      H([A\A]A^A_]ÐȉEąHv H5    01'D  ME1tPfD  A$1ۅ~fD  ID$H<HOA9$I|$AI OI|$|OD;mrLnOA{Huĺ   	HtHHHIuHE@1f.     UHSH(dH%(   H]HH   H   H   L   L   u
H    tHEdH+%(   u0H]@ EHu H'    01MG    UHAWAVAUATSHHHHwdL,%(   LmIHEHW  IEIU H)H  <HIEHE}x   HHEHH  u  IIHEE    HE   f     IEIU H)H   HIE]IE x tˉ]ĉHIHF  IuH  MMIE L)H9  HLLLM%IH]I]M<$L!uID$Ht[EI9u  I}HFA}Hu   H   HHHI   uI$    1ۅtI>ILI~L;]rH}L     HUdH+%(      HH[A\A]A^A_]fD  A}HHH9HHHIL2LI$    uYf]{     ω} 1@ HEHM   HP  1T@ A}Hu   nHtHHHIIE }g    UHH HWLdH%(   HMHH   Hq HAHH)H,  <HHA}Ax uWH)H
  HHAH	fnMȀy E1fnfbfA@hHUdH+%(          ω}f     yHu   LEHMWHMLEHuiHHQx    H~   yHu   LEHMHMLEHtHHHHЉЅTU)     HHHHЉЅ,z Hq HAEȉE_    UHATSH HOL'dH%(   H]HH  HCHS H)H  HLHCU܀~ 	  h  HKH#  HCHS H)HF  HHCU܀~    A$   HKHq  HCHS H)H  HHHCHUHx    I$  HKHr  HCHS H)H   HHHCHUHHHȀy AƄ$$  HE1I$  HUdH+%(   O  H [A\]D  ʉUfD  ʉU fD  HHUU@ {Huܺ   HtiHHHItW@ ff.     mfD  {Huܺ   HtHHHIuH3UA@ H3UuD  {Hu   WHt!HHHI{ff.     HUs    {Hu   HtHHHI3 HUzfUHH HWLdH%(   HMHH   HqHA H)H/  2A@`HAL	Ay uQHQH   HqHA H)H   2AAdHAHx u21HUdH+%(       A@`A@`L	f     AAdAAd@ yIp`   LEHM HMLEHRHHHHЉЅ}5     yIqd   LMHM HMLMH:HHHHЉЅ-     UHAWAVAUATSH(HHOdH%(   H]HHEHW  HCHS H)H  <HHCHE}Āx   H;IHg  Eą<  ME1
  f     HKHC H)H)  
A$HCHx t
A$A$HSH/  HKHC H)H   H
ID$HCHx tID$HID$HSH!  HKHC H)H   H
ID$HCHx tID$HID$HHIHtnHXELID$;DI|$ tQEAI A9/  HSH{   LHHHHILCHUdH+%(      H([A\A]A^A_] {It$   >HHHHIuD  {It$   HHHHIdω}fD  {Huĺ   HtHHHI)H}1fD  Hu   1L8  f     UHATSHHWL'dH%(   H]HH  HKHC H)H  
A$(  HCHx   HSH1  HKHC H)H]  
A$,  HCHx P  HSHb  HKHC H)H  
A$0  HCHx i  HSH{  HKHC H)H   
A$$  HCHx   HSH  HKHC H)H   
A$4  HCHx   1HUdH+%(     H[A\]D  A$(  A$(  HSH{I$,     HHHHIff.     ufD  A$,  A$,  HSH{I$0     <HHHHIu A$0  A$0  HSH{I$$     HHHHIDp    A$$  A$$  HSHd{I$4     HjHHHIO    A$4  A$4  >{I$(     +HHHHI1UHAWAVAUATSH8HOHdL4%(   LuIH  IFIV H)H  <HIFH؉}Āx           IH  ILx1$f.     AAE9   ILIGHA  INH  IV IFHH)H  4MHIFAwAx t
AwIFH)H   HIFAAx cEă9kI(  HE    1E1L2L9u]  @ EIMAOA9       HuLLEDMv6LEEDMI(  M6I9tA9ruM6I9uff.     D9uE1t-H}d HS    01     EA1ۅtLIa;]rL$=HEdH+%(     H8D[A\A]A^A_]    A~Iw   HupMINAx   HuIA~   LXHt"HHHILff.     MZ     IV *    HHHI
uD  ω}ĉ   PHFc H    E101nf     Lfff.     M6I9tA9GNIA9   uLLLEDM4IH5 HHUSDMLEtHUI0  I    AWEA   A9
ZLuAI(      A~Huĺ   Ht HHHItA I}E1оAGAG#UHAWAVAUATSHHdL4%(   LuL7A~   HOHH  HGHW H)H  HHGLUx p  IF@E1HEI`  HHErHEHEE   @ ff.     HKHB  HS HCHH)H  4H;HHCu t	ΉuHCH)H[  D<HHCD}Ā tAD}EI} UIH&  fnEfAnHsHx fbf@H%  L{HS L)I9   LLV5OD= LCH}LRtMAD;e1E1H}AJL99HEdH+%(     HH[A\A]A^A_]D  LA9D;esHKH{Hu   H   H;HK *  H|   {Huĺ   KHt%HHHItE1<fD  D}H;@ H{LI9HHHI뱐HS 8    HHHIuCf     EȉE H	_ H 11ۋ015Hu   oHt!HHHIttD  HkEȉE ff.     UHAWAVAUATSHHOL?dH%(   H]HH{  HCHS H)H[  HLHCUĀ~ +  7  HKHu  HSHC H)H  HHSE~   H<HIH  E]  ME1Q      HKHC H)Hy  
A$HCHx t
A$A$HSH  HKHC H)H1  
AD$HCHx tAD$AD$HSH  HKHC H)H   
AD$HCHx tAD$AD$HSH  HKHC H)H   
AD$HCHx tAD$AD$HID$HtuHvID$HtcHdUID$ HtQAI(A9  HSH{   LHHHHIUt/I]E1H;AH(4H{4H{4D;erL4HUdH+%(     H[A\A]A^A_]@ {It$   >HWHHHIe<f     {It$   H[HHHI%@f     {It$   H_HHHIDf     ʉUfD  ȉEfD  {Huĺ   _HtHHHIH3Us     {Hu   HtHHHI H3Es1 M  1A   efD  UHAWAVAUATSHXdL4%(   LuL7A~    HOIH  HGHW H)H,  HHGLUx   IF@HEI`  HHEU  HEE    HEff.     IOH  IG IWHH)H  4M'HIWuA|$ t	ΉuIWH)H  HIWEA|$ tEȉEDmA   U  }IH   {HH  Iw    DpHP  IG IOHIH)H  HHIOHSA|$ 	  HHSELcIOIH)L9  HLLHMLU:-HMLULA   ION  DeIwH   I)M9c  LHHM,LeMg(   IH6  H^I$H}LID$    蕱5  EE;E=H}A1fHUdH+%(   N  HX[A\A]A^A_]fD  ELc @ AHp   H  IDmIwx tHCHHCELcH  ALLI9tHHHIF  DmA   w9EfD     K4L);  R    f.     IwDeH   H   MW IOl H/L/EE;EIOHAHu   H   M'IOA|$ tEȉEH  AHuĺ   HtHHHI   M'     HALI9HHHIfH.H}?D  HzH    HD    H1H)H@ HHHI1fD  HHHIzD   d1fD
VfD  EȉEC H	U H 101710Hu   oHtHHHII HT H 11ۋ01         D
     IG "    IG f.     UHAWAVAUATSHHHWdH%(   H]HH  HK HCHH)H  4H;HHCu   H)Hp  D4HHCDu   DHHU9HEH:  D}  AHUHI  E     HsLmIA9AFE1E   AǃEHe  HKHC H)I9  H}HLHM'HMLHKHx _  IEA1  A  EtHuAUA  A}<     fA}~   A     IM(H  IE0H6  tIMXH _  HKH  HCHS H)H   HHCUHx tEAƅ
  ȉEHI(  HtsDUEv  AD;u+  HsI  DeE   H{HuLjI9HHHIff.     LmAEI(     f     Lx*E1H}l*HEdH+%(     HHL[A\A]A^A_]    ΉuWfD  ADul@ H)Q H 1Lm01SAEI(  pHH{H  uIf     HuHJT>JT8MHH}fD׾   DUHDUDuII   E   LmE1LsM   HCHS H)HIHHCI$H3~ tI$HI$AE9)  IMtLDuEL[LmH{ .fIHHCH~ tHHAHE9HCHH)H    {   L(Ht"HHHIff.     DU3    {Huĺ   HHHHILmzfD  {Hu   H}   H;HS 2  H  {Hu   jHtHHHIuPfDuH;@ HN HJ 1Lm01{fD  HHHImHE    D  HYN H11Lm2H5 ( HuBT>BT8DHN HK 1Lm01DH}BT?fBT8LmDuLmOHK HC肪EȉED  UHAVAUATSHdH%(   H]H8H   L3II@  x     AE   Mf     I$(  HtAI(  HH9t2A$   f.     HH9t;   uH(      A$  I  uI@  x  u<AMt,I(   HH{H  uL%HEdH+%(   uHH1[A\A]A^]Lk(A}I@  x  uf     ;H(  M
f.     UHAWAVAUATSH(H}Lw(dL$%(   LeIMr  EFI^Eu@*       H1HԚLH  L
   hK   H  L   1H    t   L   H= -   tSL   E1/    KL    L1Ha I豦D;   sEtL,   @ L      H= fAVt*I(  HH{H  uL#HEH@(    HEdH+%(   uZH([A\A]A^A_]@ CIH}HEdH+%(   u'H(L.      [H= A\A]A^A_]ff.     UHAWAVAUATSH8HdL4%(   LuI{lDkhHHq  H  INIH  IFIV H)HE  HIFUIx X     INH  IFIV H)H  HIFUIx %     E  HEE    HEINH  IVIF H)H  HIVEIz      IHEHIHf  INH  IFIV H)HB  HIFUIx   E}IHHQHyHCEIHx    Eą  1   IFIV H)H   HIFUIx tEȉE    IH   UMIHRHʉ}vLHtqIGLHt`IGLHtOIG;]m  INHPA~Hu   >HWHHHIAHUdH+%(   n  H8[A\A]A^A_]    ʉUfD  ʉUfD  ȉEfD  ʉUqfD  A~Hu   HtHHHHЉЅgU#     A~Hu   ^HtHHHHЉЅ'U&     A~Hu   HtHHHIfEA     ED;m1 A~Huĺ   Ht HHHIf.     UFâ U   HAWAVAUATSHXL7dH%(   H]HHE    Ic~lLu}I  H   HKH  HCHS H)H   HHCUHx    HELu   L      MA      E1L}IHHEHuLHPx9H}ALH@HMdD;mshHHEHuLLH}H  HUdH+%(     HX[A\A]A^A_]ʉUfD  1L6HMH   HKH  HCHS H)H~HHCUHx    HEI      E1L}O HHEHuLHPH}ALH@HMdD;msdHHEHufD  ʉUlfD  {Hu   HtHHHIU 1LHMH   HC I9P  U  EE1M,HEHE,    HEIʉUH  B8M9   IHsH   HCHS H)H
HHCUHx tʉUHEH  BT8HsH   HCHS H)HHHCUHx PHEIH  B8M9UHC I9   1     {Hu   HtHHHI<U8 {Hu   wHtHHHIUN{Hu   BHtHHHIUOHKHb  HSH)HHHSEHz tȉEHME1L}   u8eD  H LLHPBLA-D;es/H߽HEIHuHH  1&L1E1DuHMH   LIuWm@ HCHS H)HHHCUHx tʉUHEH  BT(IM9HKHu{   HuHtHHHI]U뚋{Hu   HtHHHI;E襜D  U   HHHdH%(   HEHcHH	T HEdH+%(   u[ff.     UHHHHdH%(   HEHcHH!T HEdH+%(   u	f     UHHdH%(   HEHcHHD H HHUdH+%(   u躛f.     UIHATISH LGdH%(   H]HM   HOHH=     Hw HH)H9Hs     HHH)H9r  H9HFH9r1I<HL2I\$1HUdH+%(   uxH [A\] LHLMHUݓIHtVHUIL$ID$LMIT$ @ HLEHHHHHH9HDE냸y菚jD  UHATSHdH%(   H]HHx
  Hu4Hu   EH誑u   HuH蕑HUdH+%(   u	H[A\]     U   HATSHuHdH%(   H]HE   <xXH   HuHߋ   Ex7H   HH   xH   HH  D  HUdH+%(   u	H[A\]S U   HSHHdH%(   H]HH(  菐tHUdH+%(      H]fH   HH,  YuH   HH0  >uH   HH$  #uHEdH+%(   uHHH]   H4  @ ff.     UHAWAVAUATSHHdL$%(   LeIL`  L艿H     L蕏Aǅx
  u,L\HEdH+%(   u\HD[A\A]A^A_] H  H/    HSHsLIH"AǅxLHu蜗ff.     UHAWAVAUATSHHdL,%(   LmIL`  L詾H     L赎Aąx
  u,L|HEdH+%(   u{HD[A\A]A^A_] H  HK    H8H{IDgxHsLI$   4H{AXE{LHun蝖fff.     UHHdH%(   HEHH@  ~! t'HEdH+%(   uXH0   鹍f     H= A  H H    H81ƔHEdH+%(   uɸff.     UHHdH%(   HE1HEdH+%(   uH   H  !謕ff.     UHAWAVHuAUATSHXdL$%(   LeIH=h HE    HE   HE    Åt-HEdH+%(     HX[A\A]A^A_]f     H}Hu胣ÅuHu   LlHMHM      HuLK      HuL2HU  H
  HEHE    LhHEHED  Iu   Lxx   LLۋxdIE Hu   LM}HE躋xCHEE1H?Hus HEIIH?HI9sW   LLwyHUHt*HEL`HRM,     I<$IM9uH}sHEHUIH9U몉릉蚓f.     U   HATISHdH%(   H]HHƈ
  ͊x1HEdH+%(   u:HH
  L   [A\]鞊fD  HUdH+%(   u	H[A\]ff.     UH5 HAWAVAUATSH8H}H=) dH%(   HE1HE    HE    .H   I!    	   H5 L<ÅtVLHuH}
   'L}HȻLLCHEdH+%(   uJH8[A\A]A^A_] 1HUH5 L{tL}H}   Hun ff.     UHSHdH%(   H]HT   EHxCHu   H߉ExHu   HHUdH+%(   uH]D  \ff.     UfHAWAVAUAATISH_ H   Hh   HxdH%(   HE1H}HE    UEE2Aǅu/HEdH+%(     HĘ   D[A\A]A^A_]    Hc   H`H  ID$A1DIcH4HPHH   HA=     HEL`HpHx   LXDDf.     H}D   H9 McKD L$M,  H}    }   1&IHxH Ht*H-  HxHUDHMHpHMЅuHhHpAԅ  }   1II+FIFAW   HHc2A=   $DDHH1D|HPH`Hp肆AǅO  H}.H`"D  H96 H    H> H81tHXD%"JLxDXfH}DttnIcHH7 HL!IM   H} ux}1   HhHpIAԅ   }   1IzI+FIFAW   HHcA=   `DX@ HA5 H    HF H81|HxD-! H0 H    01    HEHpCH6 KD    H HLH0 01I6}1}Hz0 IM   H 01I6}1dC
A@ ff.     UfHAWAVIAUATSHHx  |dLhDxdH%(   HE1Hǅ    E+  #  HGHWHu	HY  HD|HLIFHhDAǅ   D   1pII(  L(L9  HH&f.     A   Mm M$M9(    A   M  I   HHAǅyH. H&    01HHEdH+%(     Hx  D[A\A]A^A_]     |1Ҿh   Ah   I(  L(L9E  xd ff.     A   M  Mm M$M9(  uHH9  E1    ff.     y     A   H	IŠ   H9uIFIVH   HINxt4d t+Hh|HL
AǅIFIVf|HU1Efo 1Hǅp   )`AoF LxEAoF0LmEHE?Hh   H`GAǅ$|   1E1&fH	IŠ   H9IFIVH HBhIFh   IFh   +fHH9  HE1HHHp H	IŠ   H9   y   wA   oAHp   HH)oA )oA0)oA@)oAP) oA`)oAp) o   )0o   )@   ~  HfHnfl)PHAH+ H    01E1@ IFIVHx KD% IFxH=+ H> 1A01eTHH9txgd UMnIVMLE1蘇     UHHdH%(   HE1HEdH+%(   u
H~W    UHAVATISHHdL4%(   LuI~t HUdH+%(   u?H[A\A^]fD  HEdH+%(   uHLHL)[H5 A\A^]B~͆fff.     UHAWAVAUATIS1HdH%(   HE1D  EH߉E?}HHuHu   L}xrfH}HH|   Hs   L}xGL3L\   HuLIǍ@@E}xMAWLLYyD  HUdH+%(   uH[A\A]A^A_]f1ǅ    UHAWAVAUATSH(dL$%(   LeIFH!     HLI|   HEI^E1HEAu;       LEMLLAP   AH E;.      HL|xgHs   Ll|uRHs   LW|u=DHM|LHu   LI@@LEE|VLE EHUdH+%(   u$H([A\A]A^A_]f.     1Ƹ`UHAWAVAUATSH(dL,%(   LmIH     HLI{   HEE1HEAur    LEMLLAPB   H[HHu   LIǍ@@E!{x^MAWHLxHAE;&snDHLL{LHu   LI@@LEEzWLEEHUdH+%(   uH([A\A]A^A_] 1͸U   HAWAVAUATSHH8FdL$%(   LeIHuEDz   Hu   HE   $z   M<$HEHEM9uO   fD  MAULH   A   I   HHyxvM?M9   UIwHyxWA   Hu   H߉Eyx8LbHI7Huĺ   HIō@@EZyRHUdH+%(   uH8[A\A]A^A_]@ 1跁    UHAWAVAUATSH(dL$%(   LeIH  HIR   Iul   Lx   IUpIupHuH9   HZqfD  MAULL~   L{L:   HuLIō@@E]xxTMAULL7x>HSHZH9Ut0L;L   HuLIō@@ExeHUdH+%(   uH([A\A]A^A_]økff.     UHAWAVAUIHATSH(dL$%(   LeI耟Hu   LEw   I$I9u   fD  HI9   H9   u닃   ~L0  H    EMULDLHuĺ   LIƍ@@E
wxFMAVLLx0Hu   LvxHu   LvRfHUdH+%(   uH([A\A]A^A_]f1'    U   HSHuHdH%(   H]HE@   ^vxMH5`(    H3HUdH+%(   uH]~f     UHAUATSH  dH%(   H]HHPxlHTHL   HIō@@LuxLAUHTHHUdH+%(   uHĨ  [A\A]] ~@ UHAUATSH  dH%(   H]HHPxlHHL   HIō@@LuxLAUHHHUdH+%(   uHĨ  [A\A]] T}@ UHAUATSH  dH%(   H]HHP xlH@HL   HIō@@L]txLAUHH0HUdH+%(   uHĨ  [A\A]] |@ UHAWAVAUATSH   H$ H8   L'dH%(   H]HHH   IA$   Hs   LS   HIǍ@@HHHfs   AWLH9xwA$   E1-   AULHxIIE9$   ~aI$   N<LH   HIō@@ryHUdH+%(   uH8  [A\A]A^A_]D  1/{@ ff.     UH5 HAWAVAUATSH8H}H= dH%(   HE1HE    HE    HtNI 
   H5s HdtXLHuH}
   H]HHLrHUdH+%(   [  H8[A\A]A^A_] :   H{Ht
x   
   H_Ht  |   L-! ID  ff.     AtXMIAD  tLQAF HI9t1    ff.     ATHuAu    HH}Hu   Iƍ@@Epx6MH}HAVH}L@~۸IH}gL~f.     HPx HE
yf.     UHAWAVAUATSH8HdL$%(   LeIHEoH     HLH#pxoDE   HEE1HE%fD  MAULLx:ID;;saHCN4LHu   LIō@@EoyH߉EwEHUdH+%(     H8[A\A]A^A_]Hs   LooxHEDCLh@EthHEE1HE&D  MHuAVL%x?ID;{s5HC NLLMHu   LIƍ@@EnyL:2HMyl~\E1@ LuM   LII  Jt>nI     LLnIE9nlsHs   L_nKtoHEE1HE( MHuAULuID;{s:HCNLLEHu   LIō@@Emy1HMQl"E1@ ff.     L}L   LHI  HmIE9olv    UHAWAVAUATS1H(dL,%(   LmIE    fHlHHt3H;H5 	tH~H߃EUlHHuHu   Ll0  EI  f     HlHH,  H;H5` }	tH~Hsl   Ll   HCpHspLuHuH9   L`LuyLEMLLAP:   M|$L   LLI@@LEElx]LEMLLAPxCID$L`H9Et`M<$L   LLI@@LEEkTHUdH+%(   udH([A\A]A^A_]fD  1@ L#L=   LLIǍ@@EakxMAWLL;ssff.     UHHdH%(   HE1HEdH+%(   u1sfff.     UHSH(dH<%(   H}H= 8HtcHkHHtS=K  tHEdH+%(   uLH]HfHY H߭    HM؋01耸K HM HHurf.     U   HAUATISHXdL,%(   LmIHH};uwE1H}HMк   LH}AEt&   HUdH+%(   uXHX[A\A]]    LpHE+EHH9f.     HY LH 101脷qfff.     UHHdH%(   HE1HEdH+%(   uɸ&   qf.     UHAUATSHhdL$%(   LeIH~ @   H}uZH}HuL   E@   IhxMAUHuLHUdH+%(   uHh[A\A]]D  qff.     UHAWAVHEAUATSHh}HuHUdH%(   H]1HEuH};W      HED0E7  EDME1DUDeELmE;M    E;U   E;e   EA;E   IuH}DxD|zD|DxuxIuH}[D|DxuYIu H}<D|Dxu:E9tFH}ِ1HUdH+%(   ucHh[A\A]A^A_]AI(E9HMEKHfoEHU foEHP @HE HEWo    UHAWAVAUATSHHdL$%(   LeIuH☍    HHHH H)H9tH   H$   H9u%  H)H  E    HE1E   E    KuDEupAE9tgHUHDȱtUt)E1f.     H߉EAH(mD;eErHUdH+%(     He[A\A]A^A_]fuĺ(   HH.TuvHu   Ley   HuLleU`tHEIE1HE   f.     MHuAQL!MGLLEHu   LI@@LMEdLMMHuAQLM LHu   LI@@LEEdLEMAPLLrUvAI(A9e   LLVdJIu   L=d1Iu   L$dIu   LdDHL<MGLLEHu   LI@@LMEcLM{fD  HL Z0lUHAWAVAUATSH   H$ H   H$ HxHH=Ҧ HhH5y dL$%(   LeAHǅ    H  DHHϠHH  E1ff.     Hٺ
   HH H\  L   H5> La  A>cukA~pudA~uu]1HH5 L}uL   M4IHIH  >D     H5ϥ Lt,LAw|HIHxcH{      LIHB茟IHP  HHH@N4HLH8veHHMHpH1H5 d   D|_    HH5Ǥ L2=D  1HLH5Ҥ uHhA9sL譸IFHttHLHHpHpIFHtFHH|H<    HpDIFHl    H4HmHEdH+%(   u=HHx   [A\A]A^A_]H H~ 101;1Hhff.     UHAWAVAUATSHXdL$%(   LeIE    E    ȞHuH}DDDu HEHD     HuLI_HuLE   _E  DMIHMHMHM%ff.     ff.     IL9m  Iu Ht   L1*_IE    LHp_IU Jtf.     HBL   L4    H4^}   IE H@J0LxLHu   LI@@LEE^xLEMLLAPvIE H@J0LpL.Hu   LIǍ@@EQ^x-MAWLLH'IU ;Z*D  IU H;Zf.     IE H@HLxLHu   LI@@LEE]LEMLLAP@ ËUuH}OxHUdH+%(   uHX[A\A]A^A_]ûe Uf   HH`dH%(   HE1)EHu)E)EfoT }H})E]x H}1HEdH+%(   u*ɉfEH HG    01MWe    UHHdH%(   HE1HEdH+%(   uE1E1'efUh   HHdH%(   HEHH9tf.        H HH9uHcGHHHHUdH+%(   udf     UHHdH%(   HE1HEdH+%(   uEIȹ   t_d@ ff.     UHAWAVAUA   ATSHH H8HUdL<%(   L}Iu-HEdH+%(   0  H8[A\A]A^A_]f     Hc   E HEIH  UHsDA1IcLDkH  { (  H   HS H!   !  H     H ALeDLEDHLA׉xPANA!tDHH   HH#S H!t'Iu7H     H A    1H}U
UfftS   1HHHDDHƍJDHHHHDJHƃDHHHHD} H           H}D    fuSH      HHHDDHƍJDHHHHDt'JDA       1    Htaff.     UHAWAVAUATISH   H@  dH%(   H]Hx# l  DhH0DH (   HEHHHZ    HH1_A$   1HL H_IL$H1HJ    _IL$H1HG    {_IL$H1HD    `_H DLHXI$@  x  t)1HUdH+%(     H   [A\A]A^A_]f   Hپ   H= 7IT$ H    H	H  HЅ8  fb  HA      C  HuAHuAHI   AHI   I       DDEu)LH	H   HЅ   E1LAA H5 IcHV HHDHƾ   HH1^DAHA!t,f.     HIT$ HL!HH	HwH޿
   @ Hx	A{ H A    f     f   H   A   HHHDDDtS   EHtcH Mcɾ   HKHU DHHH1]DAHHAtEf     AAH-    HHDHHH@U HH1\DAIf.     AA]   E1AA   1     U   HHdH%(   HUHPERFFILEH9t"H2ELIFREPHPERFILE2H9H9	HUdH+%(   u;]ff.     UHAUATI1SHHdL,%(   LmA1DMh   HD轓Hd  HPERFFILEHH9   HPERFILE2A$   H9   H2ELIFREPH9  AD$H   HHKHCH9  HS(H9  H9   HC H9   Hh   HH   fLkHCHAEoCHAD$ AoEAD$0HC(ID$HC0ID$HC(ID$1HUdH+%(   E  H[A\A]]fH{1Lb   A|$ 0     HS0H9JH H 101
f.     vfD  LkHA|$ ,   LHCHtKHCHfCHAEHKH     HY Hɖ    01脠fL   s   LH H 101KFH H 101-(Z UHAWAVAUATSHX  L@  dH%(   H]HA|$#   E|$KRH(  H  Hx
  HC@H@     H8  HHHǖH  HHHPERFFILEH9tiHPERFILE2   H9tqH2ELIFREPH9  CHHun1AD$ HUdH+%(   G  HX  [A\A]A^A_]    Hھ   `  H{ t I|$fAA|$  uH`DH`  { tA|$$   H}   HpH  HE1HxDH1H)  ǅ    H1   H@   HDlH  { DHtH     H@  HP   D"H  {      1DH1H;IH=  CLA
  H(  5eHX   LHHʉh\Aą   HP1DL3if     H(  D1LLAkD9t8   LD(H   { t   Lf.     H1Do9EDHHP  HPmHP  H(  XH(  Hǃ(      H @      Hi 01 fHXHHHXHPHHPD  H D	@ Hi IL$H 101蒛L-F Au H    1oH IL$H* 101G	L- H    1Au H Hp   H{ 01H H 101ܚUUD  UfHAVAUATSHPdH%(   HE1)E)E)EVk  H^HCH   H H H}HL4    D HFHEFHHEIHDHtH}1H}AHUu1HH  X     HX 8 O  E   E1LeMtDAT$t3I$(  f     H訉H{H  蘉uLVHEdH+%(   ;  HPD[A\A]A^] H I|  unH 8    H IJHBH   Ht H}H28fD  H HҢ 1E101a    uH, HL   H H81	R@ H5>(    1Z     H5(    1HRH5    1H5 H& 1A01]R UHʎ HAUI   ATISH(HOLdH%(   HE1BQHcID$H   wNH   AD$   L   Hr QHHHUdH+%(      H([A\A]]fHuZHh    L1PI|$HHIH   LHZLHHEHEf     H'    L1jPHH`IL$Hڍ    L1EPHH; IL$H f.     H bQfU1HCHHdH%(   HEHHwH菟HUdH+%(   uHQ    UHAWAVIAUATSH(H L"dH%(   H]HӀ8    M   I~1IH   HL]A^A+^L   ,UE   t+AVE1I ODD1LLIgdL9uHEdH+%(   uKEH([A\A]A^A_]ÐH LH0^^MI HHIH5EO UHATSHHH dL$%(   LeIԀ8    M%  I<$H  HsIH  HCH   w3Ht~CA$h  1HUdH+%(      H[A\]ÐHuH{HH   I$   I$   fD  H HH0膆CI$p  #H{
I$p  nD  I$(  H{I$(  FD  H H 101#fNUHAWAVAUATSH   H$ H   H$ H(H@  DrdL$%(   LeIx#   Dhx     A$  I$P  DHDHXHHII)L谄HH  A$   umL9   I$P  I$(  NHUdH+%(      H(   [A\A]A^A_]1D   1DHp賹>fD  L   HcL9uvHt H͓ H 101蛒lHxAI$@      H) H H 101PH H` H) 101.L    UH0  HAWAVAUATSH   rdH%(   H]HH   ICf     f   f   E1HC$LHHXdIH   A   f{ yDk HsLHpHCHpL9sAf  @E   I:  )   Hu蓦H    MI   LEHr 01	LaHEdH+%(      HĈ   1[A\A]A^A_]f.     fuD  A   D  A   D  HXf   H`)`}ju	l u0Af  D	Af  H`f.     LH`LoJf.     f.     f.     f     UHATSHdL$%(   LeI萤   H5u H9HHFL      H5 LH9HFtk   H5 LH9HFtl   H5 LH9HFHuZH @   1HUdH+%(   uBH[A\]fH @   H @   H @   봸tI@ UHATSH dL$%(   LeI耣	   H5f H9HHFL      H5- LH9HFHUHU؅tcH5- Ltp   H5U LH9HFHu^H @41HUdH+%(   uIH [A\]f     H @0   H @0    H @0   뭸dH@ UHAWIAVAUATSH   H(dL4%(   LuIO}HHIH@IEIEHEIEIEIE IA+GAEh  II9G.  Mg    D  HO   AD$0tHCh   AD$0tHCp   I$IT$8It$0H{`聱IE~EI]fHnflHIG L`PIGHMg IGI;   M      a|HHI$It$H{HCEID$ HC0A|$) yHC8   HC`I|$8 Ht8 t  AD$0HCHIcD$@HCPID$HHCX.    IEl   fInAExHEdH+%(   uUH(L[A\A]A^A_]D     {HC`H@@ H HZ 101ǋO=Ffff.     UHAVLwAUATSHH_dL$%(   LeIL9tOL+H@ IHSfHnH{flIUL*ՓH{`,{HLIU LM9uI\$Mt$HL9tNL+	fD  IHSfHnH{flIUL*uH{`zHLIU LM9uIXL)HHt/HLk腉HLH臎LLGHuHEdH+%(   uH[A\A]A^]DUH= HHdH4%(   HuH5<  4uHEdH+%(   u H H9 101Dff.     UHAWAVAUATSHHXH(ELg(dH%(   HE1HG    #H   IM   fI*YEZ Z f(fTf.v3H,f(f%Z fUH*fTXfVf(Z f/  L,     IFLMHEEH}IAoGPfofsffI~M9sOMuHEdH+%(      H([A\A]A^A_]     LAfHL	H*XHS`Hu       ff.     HoB8HJfofsffH~L9HBHCHHuIfIWHs`AG H8b>D  \L,I?D  HC`1B UHATIH~SHA^X dH%(   H]HHChI$HEdH+%(   u	H[A\]#B UHAWAVAUATSHHXH(dL$%(   LeIHG    ˖HtGIIGLMHE H}LIAoFPfofsffH~L9s,MuHEdH+%(      H([A\A]A^A_]D  HS`Hu2   f     ff.     ff.     ff.     HoB8HJfofsffH~H9HBHCHHuI~fIVHs`AF H8袌ID  HC`1@ff.     UHATIH~SHdH%(   H]HHHChI$HEdH+%(   u	H[A\]}@fff.     UHXHAWAVIAUIATSHH(dL$%(   LeMH   IM   IGLL}HEdH}HMLLILMIAIIH9t@ff.     HP8IMtHPhIU HtHPpHMt;HPHI$H H9uMzHEdH+%(     H([A\A]A^A_]H H9uMGD  M  IGLMHE蜃H}HML1IIFINH9t}HPhIU Hu05 ff.     ff.     H H9tMHPhIU HtHPpHMtHPHI$H H9t$HPhIU HtHPpHHPHI$H H9uMC    ff.     ff.     HHHI$H H9t'Htff.     HHpHHHHI$H H9uMLM腂I1MH1IIEIUH9tHt.HHpHMt|ff.     HHpHH H9uMVH H9tH H9ux=ff.     UHAWAVAUE1ATSH   dL4%(   LuIHX`H7  IMI0E1EH  LeLMILuI0"1IH  L}II|$01IH$  LmHxLpII0E1ԑHH  LhL`H{0E1讑IHJ  I0虑HE    H   H]L}MILuMI}0E1gHH   H{0R1HHtCHyHPHXHXHPHHX脀HXHHuHKPHsXHH    H)HHCPIOHHxIUPMeXLH    H)HHEIEPIH-MMH]L}LuIWPHuLH    IwXH)HIGPIIHHSPLsXHH    H)HHCPIHHlLhL`IWPMoXLH    H)HIGPIbIHLLmHxLpIT$PIL$XLH    H)HID$PIIHL}LIOPIwXLH    H)HIWPH~IH8LeLuMIIWPMoXLH    H)HIGPI~IHMIVxM   H    H)HIFxHUdH+%(   uHĈ   [A\A]A^A_]9ff.     UHAWAVAUATSHXH}HUdH%(   HE1H  HFL&IHEL9  H~    LwXLXM	  LML}HMl$Mt$M9  ff.     L}M1ML9  fD  Ls M  Hd܂ @0q     I}0Iv HHA#  E  MHULE"LEHUM  M   j  LMIHH+EI^HEHAF@H9}  W  HULH   HEHM@pH   1HUdH+%(   (  HX[A\A]A^A_]IE IvH7  H@ H  H;F   MJJID$Ml$H  IL}Ml$Mt$M9z '  `fHu   IvHcI}(HVG+  F+  IE MNH  H@ M  I;A BHFHwH9   f     A~) t`IE8IE`I~8   H   AF0t
IEhAF0tIEpIIV8Iv0LEI}`ՠLs L{LEIFPIL{HC Mm M9  H1   L9iLMIلf.     H   IIuH9'MH9LID$Ml$HLL}MIHUH}LHQHx(fLp(L@0I} 豁@ HxH~  mM@ HEMfD  H-H-MLEHULEMPHUMofD  Ht8 t  AF0IEHIcF@IEPIFHIE@IEXLs L{b I9HEAFDIFPD     LMHU&jIHLxHH@LxI|$XLxID$ID$ IF0ID$XIF0    袉HULMHHt+HULMf.     LgxHHuHULMI|$(fIF0LMAD$0HID$(    I~0HUHEIFI}fInHMLMH0fHnȋUflH7I}H~AD$M}L8IFPID$xIvXHI$   IFXAF@)AD$hAFDAN@AD$lAvHAt$pAFHI;   IFP    HMAFD    INXAFHII9A  II HUHLHM(HHHւ Mf0HM@0Ml$     IE HQH  H@ H  H;B     fD  ID$H{(fLc(HuC0H8~f.     LMI.fHEAFD   IFPT MeIy  HFHwH9c7fD     LEMgLEHIE`ZI}0Hq HHtutqHM   y) IE8IE`Hy8   H   A0t	IEhA0tIEpHHQ8Hq0I}`H؛HuHuuMHqHlI}(H_G+u
F+   H-H-HMHMC`ID$[HtHz  uHIUH9H91    HyHFHwH9H 1|Ht8 t  A0IEHHcA@IEPHAHIE@IEXIU HAH   HR H   H;P HFHWH9gKHׂ       H=+n HuO'	    M8   HMeIE`HdHM.HtHx  zHl"0fUHAWIAVIAUATSH   HUdH<%(   H}H~X̄IHJ  LM%tI|$0I訄H  LxLmILMsI~0IzH  LL}LpMMILLmsLEIIx0>LEHHEH  LhL`HUHHUsHUHEHz0HUH  LXHHLPILM>sI|$0IIMt  LLusHMIHy0虃HMHHE   LmLeIHHUHHUrHUHEHz0YHUHt~HUH]HHIrI}0H.Ht8HpHH8rH8LLH@H@HuIUPHt	L9O  HuH]HUHrPHt	L9  H} ;HLmLLeHqPHL9HHHu	@ HHxHPH9p8HBH:HuHyfHAHQ H:yMID$PHt	L9I  MLLXLPHHHzPHt	L9  H} LhL`IHPHt	L9  MpMMLpIINPHt
H;MF  MLmLxIL$PHt
H;M  MINxHt
H;M_  HEdH+%(     HĨ   [A\A]A^A_]fD  I$LHu%f.     HHxHHH9p8HBH9HuHzfHBLJ H9w%HHHuHHrHJH9B8HBH1HuI|$fIT$HAd$ H9nwkf     I$LHufHHHHpH9P8HBHHuI}fIEA] H>LweHHHuHHpHHH9x8HBH1HuHzfHBHj H9vHHHuHHpHPH9H8HBH2HuIxfI@HAp H:vILHu!fD  HHpHPH9H8HBH2HuI|$fID$LAD$ H:6vILHu/f     ff.     HHpHPH9H8HBH2HuI~fIFLA~ H:u]ILHu2ff.     ff.     HHpHPH9H8HBH2HuI~@fIF@AFHH:HEdH+%(   uHĨ   L[A\A]A^A_]Yu)@ UHAWAVIAUATISHdL,%(   LmIH    H~`E~HHtHmHsLLH#HuI   HtL9s%HEdH+%(      H[A\A]A^A_] I$LHu5@ ff.     ff.     HHpHPH9H8HBH2HuI~HfIFHAFPH:HEdH+%(   uHL[A\A]A^A_]<t(    UHAWAVIAUATSH8dL,%(   LmIHE    {L`LiHs  HLLH5HHUH5 HHDHEHǀ8f   xp   x    AE   HUH5 1=IHtH5te Hn  AEE1HΣA} tA}w  HEdH+%(     H8D[A\A]A^A_]    H5e H}萻H}AtUH5G y   1HUH5) ~H   HOʂ H x 101}l        H= HUH5 1IEH̂  9~IH1HuH_HU:    HHH=     AEfHɂ LHw 101kAf     AE    LHu1IJI9vfEelHNɂ Hww 1A01vkeM  1AHɂ Hv 01Jk18A,% UHHdH%(   HE1HEdH+%(   uPJ{%ff.     U   HATSHH dL$%(   LeIH50    HH5b Hbj  H5b HK   H5b H4l  H5b H  H5b H  H5b H   H5b Hظtl@ 1HEdH+%(   8  H [A\]1HuLEHU:   HHH=    M܍PHiǂ P@ HuLHMǂ H,ЉPL9esLHu 3    HuLtHǂ @L9e'LHu HƂ 1012i]HEdH+%(   Z  H5Ƃ H L[A\]PfD  LHƂ LHAa 101hf     Lh}   H51a LH9HFHʡtnHH5a L贡uoH1Ƃ @(   @,Yf     Lh?HƂ LHft 1013h[fD  Hł @(    @,Hł LH` 101gHł   M1Hs 01g1ҹ>" ff.     UHHdH%(   HEGtOw-t8u(H,HG 1HUdH+%(   u4D  t@ H)HG  H9HG ! ff.     UHAWAVAUATSH8uL%Ă dH%(   HE1HOɂ HE    A$@H  E E1E f.     HUH5: xHH  HL{   H5__ HH9HF豟  Hq1tcH{   H5^ HH9HFIu   LH5^ H[u'AD$(   AD$,E11NfD  E1@HtHz   H5^ HH9IHF      H5 HI9IF۞      H5 HI9IFH赞u%AD$8   [ AD$(    AD$,DE"E   E  Hu} tq1H_AD$H9]tqE1Yf     AD$8    fLH8   1HUdH+%(     H8[A\A]A^A_]@ HAD$H9]u@ AD$8   f.     LH߈EC.A|$U1UA	HƂ A$ AD$    @ Rf1HuHbHU: u<HHH=  w,HAD$H Hp 101c:H Iع  1Ho 01cBfUHHdH%(   HE1HEdH+%(   u1n	f     UHHdH%(   HE1HEdH+%(   uɾ   +fD  UHH dH%(   HE1Ht^H> u1HUdH+%(   uN    HFHF    HHHMHF HultHuHMHH9sH머6fD  UIHAWAVIAUATSHHLmH]HUHWMDML:dL$%(   LeLe Mt}MILEH}jHuH}ELEMoHMg AG)EAG@MtIIW0I_8IGPIIF1HUdH+%(   uKHH[A\A]A^A_]D  Hu   X   LEHU\IHtHULEL]HL,D  UHAWAVIAULjATSHXHGLzHudH%(   HMHHEHHEM9   HMIfInǐff.     HE    foIffl)U)MKIO HEHt&Q(f     rq(9t
BvHIwHME1Aw0E11HUj Lj 蠲IGIH fo]H}HBHAiIiI`jPLI/HfHnL9tH*f.     HMHyx t-IFH}LHMIF    IF HQxHMt`HYXH|oIHt;LMl$^LHIcHuLLJuL莖Mu1LcmH]M.I^HUdH+%(   uHe[A\A]A^A_]%D  UHHdH%(   HE1HEdH+%(   uHH UIHHH    dH%(   HUHH tPy uy uH @(uy tI jHAQMMHضZYHUdH+%(   uD  1y uQUHAVAUATISHHLndL4%(   LuAMtI} yIH{OIL$Ht'Q(f.     rq(9t
BvHKID$HCIT$ HSI$HS HtuHI`  H8gAUuCtnH? 8f%fufC(   HUdH+%(   uMH[A\A]A^]D  k  g  EfC(f1EuH{fD  .  fC(     UHAVIAUATISHHH% dL,%(   LmAHO(@0   H   LG0L:9 A+HW LDM   H-HU L1H趣Et5IV H HtHR H   HLH8 H)H<1|HEdH+%(   urHH[A\A]A^]D  Ht;L8 A+H LDH-MLH H1"gD  INHe? L1H EfD  UHSHHHH޹ WldL%(   LEIHOxxt
H   Wp@8   u6HHeO 1苢HEdH+%(      HH]    fMt(HxZfH*Yq, MxdfI*^H[ H߸   #떐HA H1f.     HȃfHH	H*XD  LAfHL	H*X@ ff.     UHHH HOxdL%(   LEIwlxt
H   wp@8   u5HEdH+%(      ɉHN    L1f     fHt(HxrfH*Y9+ Hx|fH*^HEdH+%(   u~H5 L鐘HEdH+%(   u_H    L1:f.     HȃfHH	H*XyfHЃfHH	H*Xo=fff.     UHHdH%(   HE1HtH    HtH    HtH    MtI     HlHEdH+%(   u1@ UHAWAVAUATISHH  HLo8dH%(   HEHG`Ht~M5  8 tyHOhHLwp   HHHzcHA   Hcи   H<D)L9@  MP  g)   f.     M   LwPLW@H_XHGHMAMHA!L9'  E  Hƅ MtCHH L1   BHUdH+%(     HH  [A\A]A^A_]D  HcHH1He y    HHP    1HSnfD  L9  MOP  fI*YG( M  fI*^}h Z/8     HHEC Z  @ M9L1HE1   HHC IL=O IH HLO L1腝1Ҿ   HAHLO D)IcIHcHLI1JAž   IcHK 1D)HHc(ET E:.D  H  fH*' YM  fI*^HcH ZZL HN    D補DAM   IcҸ   H<D)M  fI*YMz  fI*^f Z/wEHcH  ZL HaN    DDA¸   IcD)HHcH  1DߛDA1HLt    ILDHM H@ HII1茛Aŀ 5LM9%Hc1L   ID)HHcIH7 HHf.     H   fH*>% YMxmfI*^¾   HHQ@ ZZ@ LAfHL	H*XpLAfHL	H*X:LLfHH	H*X{    HȃfHH	H*X<f.     LLfHH	H*XO    HʃfHH	H*Xf.     LAfHL	H*XLAfHL	H*XH߸   @ ff.     UHHdH%(   HEH0 x uHEdH+%(   u$f     HEdH+%(   u
HfUHAUATSHdH%(   HEH˴ x uHEdH+%(   ugH[A\A]] IH`E1aHHtH{HIPHHuI   M   H    H)HI   jf.     UHAWAVAUATSH8H}L7dL,%(   LmLmfInfl)EM%  fff.     M~MfM9   @ ff.        MHHs  AoIwHx AoG@AoG @ AoG0@0AoG@@@AoGP@PAoG`@`AoGp@p@y ;
HEL+H]HCHMM9lM6M@HMHL9V  HuHQH}HfHn,     ff.     ff.     ff.     HH1foHVH2Hw HG fHnflHHHHrL9uHHXfH~H9t-HEL`@L@H      CyHEH@@y 1HUdH+%(      H8[A\A]A^A_]H]HL9tIL#IHSfHnH{flIT$L"2XH{`?HLNI$LM9uLSNH^HGfHn!HEHfHnHE	@ ff.     UH=\ HH dH4%(   HuH55=> 9RIHtHEdH+%(   ugLD  (   ~>IHt=  LLELEfD  HEHm    HP HG 01NLE	fD  UHSH(dH%(   HEH x tIH    t?H}H^0H}HUdH+%(   u<HH]HP  HY     x uHEdH+%(   uH]1n ff.     UHSHH_dH%(   HE1HGH    HGHtff.     H{VH[PHuHEdH+%(   uH]@ UHATSHdL$%(   LeIqI\$HtfHH[PHuHEdH+%(   uHL[A\]ff.     UHATISHdH%(   H]HpHtvHCHC    HC H; t` ff.     HtMHDH@H)HPH0p L@0Lp8pHcH uHC H{H@PHWHSHC H9u1HUdH+%(   u	He[A\]@ ff.     UHHdH%(   HEHp x ux tdHH0H tb   u*@      f utHL      @   HEdH+%(   u-     HQ x@   H       UHAWAVLwAUIATSHH_LfdH%(   HE1I9t~L~@ M9tH{0HtbIt$0HtXәt'1HUdH+%(   uHH[A\A]A^A_]    M$$   HL9uMtIM9!@ M$$11UHAUATE1SHdH%(   H]H_0HtJfD  H  YHHt E1f     Lo8'IHHuMHIHHuHEdH+%(   uHL[A\A]]f.     UHE1HHdH%(   HMHH9t,     Hy0 tHq8HtHAH1HIH	H9uHEdH+%(   uL# UHAWIAVAUAATMSH8H}HuDEdH%(   H]H]H   DEE1LHIAPE1AUHUH}AXZEuDI~IF    I~ I> t.fHt'HAԅuAIF HxPIFHI~ IFI9uHEdH+%(   u"HeD[A\A]A^A_] AA. ff.     UHAWAVAUATSH8H   dL<%(   L}IL1I   L   IV   HMHUM,$N*IxLE
CLEHUHHMHtjL HqHxHzJ<It$J    zI   1HUdH+%(   u#H8[A\A]A^A_]D  AƇ    <AƇ    f.      UHSHdH%(   H]HG   @   C@   HCC   HC6HC(H{ tKH{ tDHt?       C   hCHC HtbC    1HUdH+%(   uEH]ÐH HS    01FH{6H{6H{(6=Hv HS    01FH{ x6fD  UHATSHOdH%(   HE1t{WItq~#1f     ID$(H<H6A9$I|$(6I|$6I|$5HEdH+%(   u3HI|$ [A\]5f     HEdH+%(   u	H[A\]S  UHAWAAVIAUIATASH8LEdH%(   HMȋ~xHGHc1fff.     HH9tWD;$uIuD;<uAMM} G  Hc1HH93  M;4uHxtIU(HMHH1aA9M~   IE(Ic}HcىMHHHU4HUMHIE(H<   IED$IED<AAE XHEdH+%(     H8[A\A]A^A_] I}HcىMH4    HuI}HuHEI}(H4    HELEHUM@H@@z  HMn  AMAM MEIUIE(A;MtAHcAEH    M4	LEHHHHEDIH   AE E1:| UI<1LE)H   	IE(LENIE9e ~DJ    HuHEIE(J<IHtYIcE9EIE(HuIL0E9e EAMM} AE!H䠂 HP    01CFH HwP    01BLyH(P H    01B<LHUHE\yH}SyH}JyHO 빐UHAWAVAUATISHHdL4%(   LuI  E>E  1A   A   fD  IF11L H   D1I   Ln HA9DLIF11D1IAA9DLH9AFDmD}  1A   A   f     IF H<swHKVLR    HA9DLIF 11HD   1'IA9DLAFH9DmAEA   t  D]LeE1䐅X  N,    1 ff.     IF(11L H   J(L1HA9DLAFH9AT$A;  I    Ic~IH<HH  E1E~'@ IF J<SvH+UBIE9nEE   E1E   E   Leff.     IF11L H   N$    F1GULh H9Mº   11EIFF1GUEV9ME1EE~Lf.     IF(11L H   J N1VGB;  BIE9~IE9.1LeHL   E1Hs L PDMH8 1MjEN_AXE~B ff.     IF J<tB   LIHo8 1I"E9nL
   ?9A6   HE    ff.     L}IFHLH"8    FIFN,    BE1PM1DMANXZ~5D  IF(B   LH7 J(N1IvE9~L
   8HEHEA9aHEdH+%(   +  HeH[A\A]A^A_]t     IE9~"IE9._D]LeH   LH6 L PH6 H6 AWPHm ASD]PEPHq PDM1MAH@   D]AFD}1LeMD]ff.        H    HUE1MHEH    f.     HUIF(HN$IF J<ID   rIvHH+6 DATuV   AWMQPEPIFPDM1MH}AFH@D9HUMJA;}	H@HEdH+%(      He[A\A]A^A_]EnE   E   E|E   A   A   cE   A   HEdH+%(   u'HeL6      [H=I A\A]A^A_]S^f.     f.     f.     UHSH(dH%(   HE1	mIщH= IHcH>fHEdH+%(     H H]H5W L18HEdH+%(     H H]   L1RfHH 1LMо   HM2LMH}HH H5 1AI8HUdH+%(   $  H] HEdH+%(     H> kHEdH+%(      H4 H]H5u L17fD  HEdH+%(      HG	 f.     HEdH+%(      Hh HEdH+%(   ulH D  H @@t@y.   HEdH+%(   u-Hj BfD  HEdH+%(   uHHf ? UHHdH%(   HE1H=̃ HEdH+%(   u     UHHdH%(   HEHp @8HEdH+%(   u    UHH   HhLpLxt )E)M)U)])e)m)u)}dH%(   HH1HEH0ǅ0   H8HPǅ40   H@HHdH+%(   u@ UHHdH%(   HEH˃ HtHUdH+%(   uYf.     H H8s˃ tHp˃ fD  H H1 1017=˃    ^ ff.     UHAWAVSH   dH%(   HE19|iHR HI΋~
ʃ t<qIH 8 u`E1qLHھ   H	D     HHED  1HUdH+%(      Hĸ   [A^A_]D  H@1H8#uHPH8HH0DHaH0H}@   Ha0 H8v2L   1LHH8HB0 AD  UHH   HXH`HhLpLxt )E)M)U)])e)m)u)}dH%(   HH1HEHH0H8   HPH@H ǅ0   ǅ40   0HHdH+%(   u5D  UHH   HXH`HhLpLxt )E)M)U)])e)m)u)}dH%(   HH1HEHH0H81HPH@Hܒ ǅ0   ǅ40   0A
HHdH+%(   uh     UAIHHSH   L`Lht#)p)M)U)])e)m)u)}dH%(   H81A9}#H8dH+%(      H]    HELH(H@Hǅ     ǅ$0   H0nHHHSZ/D HH	HHHHi ʚ;H)HS㥛 HH   1HIHz- 'nH   H H,UHSH   HHHPHXL`Lht#)p)M)U)])e)m)u)}dH%(   H81HEHِ HH(   H@H 3H0ǅ    ǅ$0   31H    2H8dH+%(   uH](     UHH   HXH`HhLpLxt )E)M)U)])e)m)u)}dH%(   HH1H : uHHdH+%(   uW     HEH   ǅ0   H8HPH0H@H ǅ40   H8U> ff.     UHHdH%(   HEH 8 uHEdH+%(   u>f.     HEdH+%(   u#H wIH   Lnf     UHH dH4%(   HuH5[ u7H 
wAtDuW   E2E@ ff.     HUdH+%(   u=           EEfD  ~ƿ   EE@ ff.     UHHdH%(   HE1H=Z  tHZ @ HPHH8 uHu Ã          H      H9      HEdH+%(   u1c UHHdH%(   HEH H8HHEdH+%(   uH5HHfff.     UHAWAVLIAUIATISHh  HdH%(   HE14LLx1LHpHP  HǉډoHH8  M   H1LeD  MLH-Hپ   H( L1HLHHHǽ L
   (L<H9tpM<LHL   LnHt#HHHHUMHH' 1   L@T HlHpHx4*HEdH+%(   uGHh  [A\A]A^A_] LH\L(Hp<Hx)	f     UHSHH  dH4%(   Hu    R\HHcHy H8HEdH+%(   uH]@ ff.     UH50 HSHdH%(   H]s.1:HEdH+%(   uH]|:f.     f.     fD  U1HHdH%(   HE1Ht5D  ff.     ff.     HHHH)HHuHEdH+%(   uHfff.     UH5D   H=mHHdH%(   HU1^Hc HEdH+%(   uUD  UHHdH%(   HE1pzHUdH+%(   uD  UH5dHAUATSHdH%(   H]HH=Ѿ <H=; HUH`dt-H} AHEdH+%(   |   HD[A\A]] H߾   k7HHE    A4HHtH5H=O AE1LEH=@    HaH}baq(f.     f.     f.     f.     UHHdH%(   HE1e  HUdH+%(   uff.     UHHdH%(   HE1HEdH+%(   uHHVHFHpUHSHdH%(   H]HH6+HCHEdH+%(   uH]1+ff.     UHAUI   ATSHdL$%(   LeI%Ht?LH蒆L#HCID$I\$HCH1HUdH+%(   uH[A\A]]øfUHAVIAUH}ATISHPdL,%(   LmIHM   LLMl$HEH}ID$ EAD$(I$HEHMID$Ht Q( rq(9t
BvIL$fH}AD$06HEdH+%(   uHP[A\A]A^]@ ff.     UHAWAVAUATSHhHEMHEHEHEdH%(   HEHh x! ^  L~IIHVMG  H>  IwILHULELI+7DM]0MW HHxIzPLUHp[fHULEHDMH  I<$DMLE袄fInAW(LEfHnDMflfD  JAO(9t
BvHE    H)EHH9   HPMHL`L}HUpuu'     HBHLbE1E11HErj j LLLxH u IT$H9uLE&/E   HUdH+%(   u[He[A\A]A^A_]D  H}HxDMLE0HHtHpHDMLE   L}ff.     UfHAWAVMAUATSH   HEH8H}LX]HHHE(HPLe H(H0H@dL,%(   LmDm0)`Hǅp    ILXE1ffDM)EM  I   A0H8HMLEQ  lFHEHQ  H DB(EtH(H?   H 8tH0 3  H\ x tH}   Mz  A$Md$XH}HMH`Ht"Q(D  rq(9t
BvfHnEDLhH`D@HATDXLHHPY^9  Hh1HtGH=끂 W0t9HA HuH8H(H`HH0H <zH  HDHLP@ATDXLHHPuH AH}1H+,HEdH+%(   9  HeD[A\A]A^A_]fD  I&  wTI  H)  H L   H[1 A   H`015#HPFh@ IuA H`E1K    cHEHHG x H`@ HEH= E111Hp-LH0Hu HPaF@ H8AHML @ ǅX    f     A H`E1D  A H`E1iD  H=y E111Hp-LHEH(HfD  H H8E1HpH0x0AH8DN*L01DH8H(HiH0H HH8H8lf.     UHH   H$ HX	  L}  dH%(   HE1HIHHj1nHUdH+%(   un ff.     UHATSHHdL$%(   LeI	HtHxH5 dot HEdH+%(   uJH1[A\]fD  HsI<$H9tHSx4 tHSHAD$HPH+fUHAVAUATSHdH%(   HE1H   HcHIIHkXH9F  HF H   H@PIE I$`  H|X(IU I$`  oH oB@oB @ oB0@0oB@@@HRPHPPIE M$`  HxI|IFIE I$`  HHHHt"Q(D  rq(9t
BvHOI$`  D(IEHEdH+%(   u1H[A\A]A^]fD  HF    H`  D( eD  UHAWIAVAUIATSHHLMDMHMH   LEdL4%(   LuDuH  HxHH    HEEHI    tDME IE     MEMt/IEAIE E~1ff.     H@PIE D9uE  L
M  HHuHLELaLELHAuVLPj ATjHMHUH0   I    t'IEI;E tIU H  HRPHIU IEE1.6  fD  I   DLAI6D9  EHML$LLPHE0j ATjLEHMHUH0tD  HUdH+%(   -  He[A\A]A^A_]fD  AA   HcHMEH[HUH\HEHE)f     I   DLAHvAt`HLKLLAVHE0j SjLEHMHUdH0tG    LIL    1)f     HUHML
MuLIHHuHHLHLAVPj QjLEHMHUH0f1tIUBkff.     UHAWAVAUATISH(H!~ dH%(   H]Hx tH    IT$j 1E1j E1LHDZY   IL$It$Ht=Hy @0t}HA HqHMH+1Hx`ILh`I{qHt^It$HHE1E1LQH1j j lH HUdH+%(      He[A\A]A^A_]@ 1@ 1@ H}IT$E1LHzx HUx0ADEM#DEHU1MHLbLLHHE3It$HMGUHAWIAVAUATSHH  HHHdH%(   H]ȉ.  	 LI1BwHǅX    P  I    HM|$B /1!  HhLH0f.     <   A<$.  A|$   HXH  L`AVMfLH`AVH)HXAFuMfP1HLDIu0%   = @  Z  AF<efff.        LLMÅ   tL-IH  A  L#@ HhE1H*D  <   A} .  A}   HXL`HC  AVMnLH`AVH)HXAFuMnP1HL-Hu)%   = @  S  AF<ffD  L   LLAą   tL},IH    L%    A<$.  H5S LNfH5 L7fL,IH  HHHJ;      HH   Åjff.     A܋PHEdH+%(   
  HH  D[A\A]A^A_]f.     A} .uA}.uA}     LH+IH  HHHJ>      HHSAąD5D  LP1`     L%H	L`f.     HP1`     B%HHH`I) A|$.A|$  HHHJ>p    tA$?  HHxHnHHHHL  Lq Hƺ   HL*H5& LiHt$Ad  r   uAT  Ad  HHJ9HHX  K  tAE M  HHHHHHHl  Li Hƺ   L8)H5M L	iHt$Ad  r   uAT  Ad  H<    AFfD  AFfD  IE LHI|H|HzHH)H)H!    I$HzHHItHtH)LH)H    IE LHI|H|HzHH)H)H    I$HzHHItHtH)LH)H|    AE bADfD
PfD  A$kADfD
YAE ɉADD
A$ɉADD
-A$ɉADD
AE ɉADD
ADfD
ADfD
Ho LH H"    01APHA"LD  UHAWAVAUATSH   H$ H   H$ H   H$ H  dH%(   H]HHtsH  LK(      1LL    LH5z LI  LH,7  H#Aą  LC(      1LH= LLmH5 LMgIH  HH¾   VLIM  HH5
 f'H  Lh    LSHt  LIHV  H         PLK(L
 1LLLFH`  LH$  	 LH1 mHǅH    @ZY  L{HE11Ƅ/HhL`DL,fD  <   A<$.   A|$    HHH  HPSLcHHPSH)HHCuLc@1H@L?u#X%   = @    C<iL   LLAƅ   t Lm#H`HH    L}'     A<$.uA|$.uA|$ D  H5& L!]H5 L
]L"H`HH  HHH
  I$HzHH
ItHt
H)LH)HH"H  	 H1jHǅ      HCHXƄ/E1HX1Hx0f.     <   A<$.  A|$   HH
  HSLcHHSH)HCuLc1H@L<u#X%   = @    C<iL   LLAƅ^   t LM!HXHH    L]'     HX@1`  Hڿ   H~HPfD  @DL6E3  HEdH+%(     HeD[A\A]A^A_]     HHH1HH  I$HzHHItHtH)LH)HHHIHHH  I\$ Hƺ   Hp H5 HA`t!d  J   uT  d  L~tf     Him L`h  A$
ALfL      A$ADfD
D  A<$.uA|$.uA|$ $D  LHXHH  HH1HH     tA$  HH  	 I1gHǅH    @  I\$HXE11HpHBƄ%/HP+    <   A?.   A    HHH  LPAT$M|$LHPAT$H)HHAD$uM|$@1H@L)9u%X%   = @  
  AD$<aL   LLAƅ^   t L}HpHH    L     A?.uA.uA      L(HpHH  HHH    tA  H  	 HI19eHǅ      ID$E1BƄ%/LH1*D  <   A} .   A}    HH  LAT$Ml$LHAT$H)HAD$uMl$1H@LX7u$X%   = @    AD$<`   LL Aƅ]   t LHHH    L%    A} .u!A}.uA} @ ff.     LXHHH  HHH3  	  tAE 	  H
  	 HI1hcHǅH    @
  HMeE11BƄ-/&@ <   ;.   {    HHH  LPAUI]LHPAUH)HHAEuI]@1HH5u$%   = @    AE<i   HL`Aƅ   tHIH    L1fD  ;.u{.u{ ff.     HIH  HN!HH    tA  HH   +Aƅ@DLH,b @qf@[ff.     3Hg    1+	fD  Hx@1`     HoH   HPI	    Lh1`     L/H   LM    LP@1`     LH  LPM    @H^EDLf     H1`  Hڿ   H  Hf.     HLHIH|I|IxHH)H)H
D  EDLHV` %HJ!HHX    t  HHzIHHHs  I] Hƺ   H%H5: HVt!d  r   uT  d  L3fD  IE HzHHItHtH)LH)H5    AE~fD  @EDLH_ f     HHH_      HHKIH#H
H  Ml$ Hƺ   LH5 LUt$Ad  J   uAT  Ad  L    ILHI|H|HzHH)H)H5     AD$D  UEDLH] f     H;HH:LD;LD:HzHH)H)HHHH3'      HHIHHG	H  M|$ Hƺ   LH5 LjTt$Ad  r   uAT  Ad  L    I$HzHHItHtH)LH)H    Co    AD$ED  IE HzHHItHtH)LH)H    HHH1HH  I$HzHHItHtH)LH)HHH~HHHH  Lc Hƺ   L)H5> LRt'A$d  J   uA$T  A$d  H1G@ CW    ILHI|H|HzHH)H)H  A$ADfD
D  AE ADfD
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CH]Y L1HM H    DL3sxHY L1H Hy    DL32@7,@!HX L1H H"    DL3uHX L1Ht H    3\HUX L1HE H    DL3k@pLDLL$IHW 訴HDLyLHW LDLKL@@H{W vLDLL@LDLLXr UHHdH%(   HE1HEdH+%(   u
H@跳    UHSHdH%(   HE1@wH  Htf_HHuHEdH+%(   uH]VfD  UHHdH%(   HEHt?H  A1Ht. ff.     JHrD9}*HrHDHHuHUdH+%(   u    Hβ ff.     UHAUATSHdH%(   H]H  HtIIHLAHHHuHEdH+%(   uH[A\A]]X     UHSHdH%(   HE1fwH  Htff_gHHuHEdH+%(   uH]D  UHAWAVIH@AUATASHdL<%(   L}A蚬HH   DHMI~@D;#Iǀ} tBLH   LHEdH+%(      HH[A\A]A^A_]    PA9uAtEgE;gtDLL/  D  PA9uAtDcD;cuDHL  bfD  HT DH 101<I~@LL'螰 ff.     UHAUIATASHHHHhdH%(   HE1HG    HǇ      HH)  HHH`  H  HH  #H{@jDcfLC    Hǃp      Hǃh      ǃ        HC(H   A  E   Lk01D   H L_D   H{0    DH,IH   H}EL 1@      @   H}xHuL11(LHǃ      1HUdH+%(      Hh[A\A]]D  H=5 HC0H[    Lk0H`   H{(LD  H=A HC0HoD  HC0    벸ao@ ff.     UH5 HSHdH%(   H]Hf  HEdH+%(   uH]fff.     UHAVAUAATI  SHdL4%(   LuIH  DLHH#   I$  I$     H   fff.     D9h~HPHt!HD9hHPHt_H1     fHCHXtI$  HL  HEdH+%(   u[HH[A\A]A^]    fHCHX    fH    I$  C    H(1跬    UHAVATSH   H$ HdH%(   H]؉I,Ht	9X   CvvH?T L@pMtf   Aپ   1H HM   HHt/H= H   HHt71 H L:HUdH+%(   ufH  [A\A^]fHN HH  101 H= H$1f     11Hz HbeD  UHSHdH%(   H]HHtHUdH+%(   u(H]@ HEdH+%(   uHH]1fff.     UHAUIATSHdL$%(   LeIHHttH8HtYI$H9t&HtH#tI<$fH;n0I$HEdH+%(      HH[A\A]]UD  L8HHHuHM AL$HR 1ED$01     HYM AL$H 1ED$01}Y UHATSHH@H dL$%(   LeA裤HuHUdH+%(   uJH [A\]fD  HA9uAtD`D;`tHDHHE{HE`UHAVATSHhdH%(   H]HH  H   AҼHDIϾHH   H8{u'HEdH+%(      HhH[A\A^]fD  DL /HtdEH}HE@      @   1H}L Hu11HLUH;I2LUH}APE`H?1QC UHAUATSHHhdL$%(   LeA»HIDH   DH諽HH   H8Wu#HEdH+%(      HhH[A\A]]fLD-IHtXEH}L 1@      @   H}Hu11H`H;Iu LA9EmH(1^,ff.     U11HATSHdL$%(   LeI踼HHt11H5p Hݶt9HJ AL$H 101;HEdH+%(   uHH[A\]11Hdu艦f     UHHdH%(   HE1 tHEdH+%(   u(H    HEdH+%(   u	H# UHAVIAUATSHH dL$%(   LeIԋVv謻KIf  tAFHJ 8 uMMthIT$fHsL谵ÅuJL蒶HEdH+%(   uHH [A\A]A^]@ H1I H߉MH0MfD  H= 1FfD  UHAUATSHHdL,%(   LmIՋVvѺIHCH   HvrHI 8 uNM   IuHLÅ   L贵HEdH+%(      H[A\A]]@ HQH HH0~@ } uHK a      H=v HNT}    U    F} @HK `      H= H
HC}        H=q 1= UHHH HH dH%(   HUH8 u5HrH  HHHUdH+%(   u-    H1G H}HHUH0
HMHUW    UH= HHHVHvdH%(   HE1qHEdH+%(   u1	f     UHw H= HHf~ dH%(   HEHH HHHVHp 1HEdH+%(   u1蟢@ ff.     UHHdH%(   HEH@G 8 uHEdH+%(   u 1     HF HH0N7    UHHdH%(   HEHF 8 uHEdH+%(   u 1     HE HH0~+ס    UHHdH%(   HEHF 8 uHEdH+%(   u 1     HAE HH0>?w    UHH VH)F dH%(   HMHf  8 u/f  HEdH+%(   u01f.     HD HHMUH0HMUf     UHAWAVIAUATSHHE dH%(   H]H8    C   HsI`  C   IH   Hx L{j1IŋsA|$4    I<$11MH  HL1L
LHEdH+%(     H[A\A]A^A_]fD  HHt$I;h  >  I`  HoH1 HqC HH0^f     I|$BfD  H{L{cIH  f  L1Af  IH   f{uAƅe  CAƅi  I  HSLI$CHID$I`  *;   Aƅi     H5 Lt   H5 L~_Aƅe  1H5as L=A     L` x4 t&H0L9HHLfHp׻.[ff.     UHAVE1AUIATSH H`  dH%(   H]HHvIKHtLp HB 8    f{ tPuxM   CLLDLEHKLELDKLLO/S9    LxHEdH+%(      H 1[A\A]A^]fD  H@ H    H. 01 H@ LH߉MHpM1     HY@ HK   H	 01[ H1@ HK   H 01X3Μ ff.     UHAUATSHH  HdL,%(   LmI`H  IHt#H  LAHIHHuHEdH+%(   uHL[A\A]]<ff.     UHHdH%(   HE1HEdH+%(   uH  鹔@ UHAWAVIAUIATSHHdL<%(   L}AH  IHt2 ff.     HDLLHIHHuHEdH+%(   uHL[A\A]A^A_]VfD  UHHHdH4%(   HuHHt<Wu5HUdH+%(   uKHB H1HJ`Hj )'f     HUdH+%(   uHO(H H1&ƚfD  UHAWAVAUATSH   H$ H8HI   HHdH%(   HE1Hǅ    !H5T H   HD L9IMu   D  M}IM   HLH)uHHM>HH5 HHu;HHH1HUdH+%(   uHH8  [A\A]A^A_]    HH5Z H议t     d@ UHAVIAUATSHH:dL$%(   LeIH   HID$HHCID$HC<3It$   LhLI`  HAąt0HHEdH+%(   uIHD[A\A]A^]f     LKLL   H; H 01
A{ff.     UHHdH%(   HE1HEdH+%(   u1=fff.     UHATSH dH4%(   HuHh  HtTHHHu)2H`  HuI膸MtI<$Ht3L+Hh  Hǃh      HEdH+%(   u	H [A\]藗    UHSHdH%(   HE1HtHH`  +H  Hǃ`      HL8H{(H{0H  ~H{8uHEdH+%(   u+H{@H]8     HEdH+%(   uH]֖fD  UHH dH%(   HE1Ht(H}藜H}HEdH+%(   ufD  HEdH+%(   urfUHHdH%(   HE1HEdH+%(   u0;ff.     UHAVAUATSHH  dL,%(   LmI董Hu+Rf.     HI  AHMt,LHII;  uHI  @ HEdH+%(   uH[A\A]A^]臕    U   HATSH Hh  dH%(   H]HLb L~AƄ$i  H`  EݹEHUdH+%(   u	H [A\]fff.     UHSHdH4%(   HuHh  H^ H~ƃi  HUdH+%(   uH]讔 ff.     UHHdH%(   HE1HEdH+%(   u1mfff.     UHAWAVAUIH}ATSHH8HUHHMdH4%(   HuHu`      HH}L}胳   I  HHULIHtmHLRHH   I`  HAǅ   LH}HUHUHSH{ Iu(-HZ     1IH}AHEdH+%(   uNH8D[A\A]A^A_]f     LH}D  HLH}_     UHAVAUATSH0HG0dH%(   H]HL5: 8  IvX   H HHHD	IAM  I:  {,S  HHE    HE    HEHh  'L1Hh  H  @4Hh  H`   Aą  A~
 8  HMHUHHu,   HuHtHh  HU+  Lh  LeLEMt(AV(f     JAN(9t
BvH`  Lh  LLEHh  LEL Hh  L`M	uHh  H@H`  L LAEx*LHv   H}   H`  觵LHEdH+%(   g  H0D[A\A]A^]@ HH3 K0
  Hc    1f.     Iv0   HG HHHDIf     H3 HR    01H}&    HLuHh  H`  HHh  HUHHHh  H	HNuHh  HBH    HA2D  H!    1A~pUHAWI  AVAUAATSHdL4%(   LuAHt~HHIH5c Eu7L  DH5uAHEdH+%(   u?HL[A\A]A^A_]HyH
f.     HؓE1讎 ff.     UHHdH%(   HE1HtHUdH+%(   uHsHEdH+%(   uɸH     UHAWAVAUATSH   H$ H8HdH%(   HE1H5 Hǅ    HxX   H1H5 E1HxpHJ  11H藶  HHE1H    HHl Ha5    M   HHU L@p1/   H*  HDCHIL9   J<2G0	wH
   HHIHN2Mi8 uL9t&8"AH0 H LI   01&HL9wE1HDDHEdH+%(      H8  D[A\A]A^A_]D  Hxh YHx` NWD  Hc/    H H01HDaAl@ UHATSHdL$%(   LeI  wHtRHHǺH5L` Hx'L  HEdH+%(   uHH[A\]D  H1W    UHSHdH%(   HE1-Ht:H5 HH舚~HEdH+%(   uHH]@ H1    UHHdH%(   HE1HEdH+%(   u
H@觊    UHAWAVIAUATSHHdL,%(   LmIՋVvSsLIIH/ 8    At$9st7AT$H= 1yLLLSsLȟIMtLLLݚSsL蟟IHtwMtrKIULHvxR1L蘚L萚HEdH+%(   uFH[A\A]A^A_]H1- HH0,#f     H= 1蝷FfD  UHATSHH VdL$%(   LeIvSHH- 8 u\  HtH0 x& t+B HϙHEdH+%(   uDH 1[A\]D  HHHUQHU HY, LHUH0+HU臈    UHAWAVAUATSHHxdL$%(   LeI'IH   HI<$H蘤oKhHCH}El$)M<$)`Hx>AHMLLxLEH}fInEAFXAFh*HMfo`IF@HEHIFPt Q( rq(9t
BvINHH}ANp6HC`I   HEdH+%(   uHxL[A\A]A^A_]UD  UHAWAVAUATSH8H   dH%(   H]HHMHX  HALq    IDHEHL(L      LL}2HEH|   MtwE1E1M   HMKvH;L<HMKHIWL$It$@IH;LIWHEI$   JEuHEMI$   L;0rHEdH+%(      HEH8[A\A]A^A_] E11ff.     HMH@L<H;IL}DEL$Iw@IT$SI$H;LDID$DEHMI   A@IH;rfHE    H誅f.     UHHdH%(   HE1HEdH+%(   u
H@,g    UHATIH@SH dH%(   H]HHuHE    IH%    H1HHUH5LHcHEHUdH+%(   u	H [A\]ׄ    UHAVAUATISHHdL,%(   LmIAƅu8H  Hu*D  HHHtLLHztAHEdH+%(   uHD[A\A]A^]?@ ff.     UHHdH%(   HE1HEdH+%(   uHH5۟UHAUATSHdH%(   H]HH9t5L#I@ H{觔HHCHLHBHM$$L9uHEdH+%(   uH[A\A]]vfD  UHHdH%(   HE1x1HcH;  s%H  HUdH+%(   uf.     @ UHSH8dH%(   HE1E   AIAHcH;  sFI  DLDDuHtkXH蕓1HUdH+%(   u]H]fD  MH  LE   H  D]LMHUHULMЅD]DUw뛸2fUHH dH%(   HE1Ht!H  Hu0HuH4HUdH+%(   uفf     UHH dH%(   HE1Ht!H  Hu`HuHHUdH+%(   uyf     UHAWAVAUATSH  EHHHEHLLdL%(   L]L   M!  ICIS    HDIHH   ƅHGXHk     M	
  H# Hx4 e  ǅ    Hx(  H.fff.     ff.     HLdI 	  y  ǅ    LZ1LHtPLHJ# HD`(HH   Hǅ     9Nȅ  HFE1!D  ff.     AHD9  H8 uD9  HD   E  A  DLL AUj LHHHH٥AYLAZv  HH McLHH   ƅHLxN4MLp@ HMOLAUSj j j HHHHH0  IM9uf1HUdH+%(     He[A\A]A^A_]@ MtH! Hx4 tǅ    IHx9щNHHcHvIH   HH H)H9tH   H$   H9u%  H)H  IHHILH H)H9tH   H$   H9uL%  H)HtHL HhH  E  11H  LE1JD  ff.     ff.     HHI;H<I<oHH|HHH9tQAy(uAoI|H|IcH|H 
  L$I9sHI9AHHH9uDLhL1HI냵FaL}HfvMHE1)EHHp)@)P)`)p)E)EE3@ @H@H<    H;>  IHIE9
  HHIHH9HiH ))ǉ)H@@uD@LHLxMtHx4 Vǅ    H@ ff.     9LLcE1MDA}(t{DHcL\I 	  Hc"ff.     HHLH Z  yfD  AF9D;I-A}(uN\AVIA   D  HD   E  AE1ƅLDpAHHLxE1HNLLATj j j j HHHHeH04IE9}DpHL LxDATjHHLHH@^L_ HL   Me M9MILM6M9HENPIvIVAN9Av0MF@AvHAvXHH tIL\@ ALxHcLH|   HMAWj j j j HHHHH0    OD  fH HH)Hǅ    萈H1ff*HH)  N  H  H  HT I0H    1|H@LHG    HLLH8MH5s HLLHHLL血LLHIgI9^HLAWj j j j HHHLHaH0LL@fHƅzHf     H ǅ    H L fHǅ    L)蛆1ff*)IH    I$  H  Hl L0fƅH#ƅHE1HNHL   M$  HIE H   H'	  M   HqHM	  A    IxIpHDHH1HIHyHH)LIHM HL)HxHH)HI9LxLCIQI9  Dɍ~ ʈ`  HIcHRHHHHRH10HBH9Au.HBH9Au$HHA9	  9	  HH9tH  ApA9p  HLHkXDXHhLxADpMI`  Hـy(    HH   HPHH9J  H
HBfo HAH
I`  HoHPBoAB oA B0oA0B@oA@BPHAPHB`I`  H|THPHBI`  HtHtN(y~(9t
AvHr As  IE fInfHnHPflIU AHXE9LHLxDpHhHHxHHHH8  H8  H)@  H)HAD  HL   Me M97HHDMMD  M6M9  HENPAN9HIvAv0IVMF@AvHAvX	H tHMILƅHHL 3 A    HLpE   IcLyDH@IH HMOE1AUAwj AWjHHHHH0ttkHx    HMOE1AUj ATAWjHHHH蒐H0tuIIL9PT  D)HxeD  ED9  EIE1H9A)I)$D  HH)J4H92HD9t	B4 D9|DAA)D)^HcLHHRHLHhHF    L`t+HE1ɐff.     BHILNL9uLcLHPLLXHH`KdHHLXHPH H 101DHxǅ    &1,HDML7     HHI;H<I<oHH|HHH9tAy(uAoI|H|ǅ    lLƅH
LƅHuHL1oǅ    E1DD)ALIB    H`qp  DxL蚣LDxHHHH     X   HpzI脮HpLDxH`  HH   H`   t{Dh  HH   fHnfl H   HHfHnfl@L   HH   IE H(  M       HqHDLHE1LDL   H 1H DL01褲HALDƀ    HH   wIEfInIUfHnflHh   HPxHPHHLHLxDpDXHhIU I9   L9   LDpHHDxMIH{6HL9uLMLHIU DpDxI9t)IMIuI}fInHJflIUH7H~AE HHxHHHH8  H8  H)@  H)HAH HD`H   ikIML_fff.     UHAWAVAUATSH8H}DmLELMdL$%(   LeDeH  HIHIPH1 E܃x(   HC(H0tGHEdH+%(     D]LMLHLEH}DmHe[LA\A]A^A_],@ I   HtHx tI    tE   HUE1ELLH=D]btD]gHUdH+%(      He[A\A]A^A_]@ ASLHLAULMLEH}ZYuHS(HҀ0uI   HtHz tI    tEtnHEdH+%(      HUHeEL[LA\E1A]H=;A^A_]sH H    D]01D]    H H    01Įq0iUHHdH%(   HE1Ht HEdH+%(   u$H  tt@ HEdH+%(   u1h     UHAWAVHAUATISHX  H`  dL,%(   LmIH50Hǅ    HI uA$   t-1HUdH+%(   ~  HX  [A\A]A^A_]fD  L@mHHufD  H(HHtC*<uH5 H{-5t(H5 H{-!tH5S H{-uL{MWLD   LcHI `   Mi  KMHHHD  I  L;tp1H߹#      HHS HH5 HL LLHHLLty    A$  mffff.     H       UHATSHdL$%(   LeLh  Hp  MtGHLstHUdH+%(   u-H[A\]H5[z HQuI$Hp  f17f    UHщHH0dH%(   HE1  t$Hp  Ht>@v(@w	H9HEdH+%(   uIɉ @tH9HM؉u@uH}lH}uHMUHp  @wef     UHHdH%(   HE1HEdH+%(   uH  IDe@ UHHdH%(   HE1HEdH+%(   uHg ٢e@ UHAWAVAUL  ATIH5SHHHHU1dL4%(   LuLw0Ll  AD$LEӾHEHP{   M|$LA   L;  }/   H[kernel.I3D$HkallsymsI3T$ H	z  }[   H53x H);  H5 LR$  Hh  Hp H  HEdH+%(     HHLH[A\A]A^A_]zqf.     M|$LA   Lj   }/V     I$Lu   LLHE[  LLHL苈IH/  H}HéIH  H`  H  LLpID$I+$IE H}IE  Lƙ1HUdH+%(     HH[A\A]A^A_]f}/&LIH  Af  H߃D	Af  pHh  YL1Hh  H  @4Hh  H`    I   H5 蝾Ht1H5[ LLh  MD$M$Mt#AV(@ JAN(9t
BvH`  Lh  LLMLEaHh  LMLELHh  L@M	uHh  H@H`  LQLEVU   H}b   IT$H   CuHh  LbLCf     1Lq#    Hs0HyIHFfD  I} Hu3fD  HE   A   D  HuLE    HuHh  L4LXLЕZ L@L8L谕:L#-9`f     UHAUATISHHX  Hg	 dL,%(   LmIo )o@)o@ H )8   C@b  HC(oC0H  fA   <   <   SsL9uIH   HHK HSLHsPHCHLPCDPDK@H HH  HL腬   LpHfff.     HEdH+%(      He1[A\A]]oC1#   HsHH   HfoHC HfsfHfl)2HHL|tH= 1趌aS(Hs,HU    H HH0]f     HL oH= 1R]     UHHdH%(   HE1HEdH+%(   u	Hma]     UHAUATISHH(  H_ dL,%(   LmIՀ8 F  A   <   <   SsLsIH   CHK HH(HSHsAULSLt j D    wH HH   HLL   LmH贓@ HEdH+%(      He1[A\A]]oC1#   Hs(H   HfoHC HfsfHfl)1HLQyH= 1苊ffD  H HH0f     HLlH= 1B[     UHHdH%(   HE1>w@HH HcH>f.     HEdH+%(         HEdH+%(     ɸfD  HEdH+%(     H@ HEdH+%(     H4@ HEdH+%(   u  '    HEdH+%(   U  He@ HEdH+%(   5  Hd@ HEdH+%(     HT}@ HEdH+%(      Hd@ HEdH+%(      Hԩ@ HEdH+%(      H$o@ HEdH+%(      H@ HEdH+%(   uyH8     HEdH+%(   uYH]     HEdH+%(   u9^ HEdH+%(   u!Q HEdH+%(   u	HY UHAVAUATISHH6H`  dL,%(   LmIHU'HHt,LuLutOHU1IE HCz4 t+I$H-HEdH+%(   uqHH[A\A]A^]@ HH+B    LyuLpuLpuuLHUЄ    zHB H   jX ff.     UHH dH%(   HE1H}H  HuH5sHUHUHUdH+%(   u<Xff.     UHHdH%(   HE1HEdH+%(   uH`  ɽW@ UHAUATSHHHx  dL$%(   LeIH|   HtRI9r   L;  rAL;  r   L;  r*H  HL9  H  HL9  1HUdH+%(     H[A\A]]@ H`  HUH5{ H  HUH@z4 uHH+BHx  H`  HUH5R HUH@z4 uHH+BH  H`  HUH50 ZHUH@z4 uHH+BH  H`  HUH5 'HUH@z4 uHH+BH  H`  HUH5 HHt4HHHEЀx4 uHH+HH  HR x4 uHH+PH  H`  HUH5 HHt4HHHEЀx4 uHH+HH  HR x4 uHH+PH  Hx  f        L;  &7f     L;  Hǃx     kUff.     UHHdH%(   HE1HEdH+%(   uH  陠$U@ UHAWAVAUATSH   H$ H   ELeHE HHHHLDHdH<%(   H}ȿ8   ÉH     H5[ LH3A     H5W LA      H5G_ L   H5F L牅HL   i  LQIA   Mt  E     HHL虑IM  HHLHHHCHHCC(   HC C,C0E  C4 L PLLLMHH=  LHEdH+%(   X  HeH[A\A]A^A_]     LXIHtLMMLHH蚇Hǅ    I       H5 LL{H5 LdLIEsV@    H50 LE1AfD  	   H5 L   H5
 LDE    /   LKHǅx    HhHtHHxH=˓ 艎IHHū   H5V LHp*B  HpHuHxH=y HDHx#H  HHp[HxLpHtH   hL   1AUL L   !_AXf     C4WAƅi  JfH1LH  Htf  @  H^Df     LLL    LA      1~Cf        H5  L'H=I H=F HXՌHXHH`HHH`HPPHAHp EM Aa=  A}r2  A}m'     H$ HPtHcHxHH   KHh   LP   L1`APL  XDP6H0 D  LIH     1f     H:  LH
vAf  @HfD  Hx   HhM1HxL   L    L艛Y^U   H5J LHHDpDDDpHHt4DxA}8A}6   HzL v   HJ eMfff.     UHAUATI   SHf  dL,%(   LmI<HHHH  赍HHt/H@    fInL EC(   HC HC,    C4 HEdH+%(   uHH[A\A]]Mff.     U   HHdH%(   HUHW e  t$H   1Ht	   H5 fHUdH+%(   uLff.     U   HH dH%(   HUHW e  t,H   1Ht   H5 H}   uHUdH+%(   u&     H}   H5Ɍ K@ ff.     U1HHdH%(   HEHG Ht
e  HEdH+%(   uɉKf.     UHHdH%(   HEHG H@0HHUdH+%(   ucK UHSHdH%(   H]HG(H HEdH+%(   uHH]KKfD  UHHdH%(   HE1Ht!W( J9rO(9tuHEdH+%(   u!fD  uHEdH+%(   uVJf.     UHHdH%(   HEHG H@8HtH@HHEdH+%(   uMJfff.     UHSHHG dH%(   H]HHx06SHtH@ HCHEdH+%(   uH]I@ ff.     UHAVATSHHH_ dL$%(   LeIHL   LGt(1HUdH+%(     HH[A\A^]     LHJxYuL藣HH D H
vI|H5Z}    LH D1   袎rH:  H	tjHߺ)   HuԣLEL1H$ H9    3Q3HT    1<MKH͡ D    yH L   1H 3uHD  UHSHH(HudH%(   HE1Ux$HEdH+%(   Huu(H{ H]c HEdH+%(   uH]1H@ UHAUATISHHdL,%(   LmI$Ux8H[ HnHEdH+%(   u9HLLH[A\A]]靇D  HEdH+%(   uH1[A\A]]wG    UHHdH%(   HUHUHUdH+%(   u8G     U8   HSH(dH%(   H]H_ Htf  <HHHH  薥HHt@(   HHEHUHB HEdH+%(   u	H]HFfD  UH> HHHG dH%(   HMHHk  PLO1LGH   EHUdH+%(   uHCF UHH H dL%(   LEIHHcD  FHHII L)H9tH   H$   H9u%  H)H   IHO HtHG HtH   Ht6z	 t0H u7   L1>DHHUdH+%(   uH Hk  H tL1LELM4HMLEH\  HL c0EUHAWAVAUATSH(HUdH%(   H]HH  IH @  H  /AHev H1I   sCH5 HAċD  BHHHH H)H9tH   H$   H9u%  H)H  IG HHN HtH   H  ~	    L=R    L   H1BLAE   HN    H1BDHHUdH+%(   t  He[A\A]A^A_]D  E1     E  k  [te    t/    L= Hc1H}LXHM<    Hx    H1BLAĐff.     HMHw H1   AAfD  Ht H1I   AHAH D  BHHHH H)H9tH   H$   H9u%  H)Hu7HE1HL [D  Hk  J@ HL D  HL kBff.     UHSHdH%(   H]HwC    HEdH+%(   uH]Bfff.     UHAVAUATSHHLo dL$%(   LeIM   Ef  At>HHH5?u u*H{@Ht!MHtHh  HtHEf  LA t$Aj   u>AtH{4 uL#L+cLH+CHUdH+%(   u@H[A\A]A^]     H+Cf.     I       D4%f  AUHH0dH%(   HE1HtHHUH}HuH}HUHMdH+%(   u;H LM   HA   @ Hy H HUdH+%(   u@     UHSH(dH%(   H]1HtRH  tKI1HMLUVH HEH;t HMH}I   H6 1>H}-RHEdH+%(   uH]?UHHdH%(   HEHG f   t>j   ut)HGHHUdH+%(   u9ÐH4 u'HfH+   H4 uHH+G    HGe?D  UHHHdH%(   HUHW f   t$j   u6t>HG4 t$ff.     HUdH+%(   u"    H+HG    H+   >f.     UHHHdH%(   HEHF4 uH+GH1H9rH;GHEdH+%(   uɉ}>fff.     UHHHG dH%(   HU1HtH8f  HHEHUdH+%(   u$>@ UHHdH%(   HE1t1Htx HEdH+%(   uɉ=f.     UHH dH%(   HE1tHHtHEdH+%(   u,H@ HEH H. 101HMh=     UHHdH%(   HE1pHtH@HtHUdH+%(   u ÐHY H 101臂1< ff.     UHH HO dH%(   HE1f  tH}HWHUH9h  HUdH+%(   u< UHHdH%(   HEHH7HHHH9t#H9HUdH+%(   u)    HFHQH9u1H9tD <ff.     UHATSHHdL$%(   LeL'HC H   ID$ H   uI9tI$HH9t-H9HUdH+%(   u/H[A\]f.     ID$HSH9u1I9D o;@ ff.     UHATSHHdL$%(   LeIHvID$Ht\HH}tDI4$Ht.Ht&S(f     JK(9t
BvH   fD  ID$    1HUdH+%(   u	H[A\]:UH_} HATISHHH>   dH%(   HE1(9H3LHHC觋HCH݁ 8HEdH+%(   u?H1[A\]D  H3I|$ 2HCH;1H'C    8HHC:@ UHHdH%(   HEHGHHUdH+%(   u9fff.     UHHdH%(   HEG\HUdH+%(   u9 ff.     UHATS1HdL$%(   LeIID$@ڃH<-pLeR9rI|$@nAD$i HEdH+%(   u	H[A\]9@ UHAWAVAUATISH8Lw8Lo@dH%(   H]HQAD$`DyD9k    E       LMHu1IHu  DEHuID$8LIMN   LMLMLEX1LELMHMI  ID$@EAD$`H  S(fD  rs(9t
BvIHC Htf     MM  S(fD  rs(9t
BvIE|$\A   AD$htAIH@H91AD$hAT$iHH9Cr^1HUdH+%(   M  H8[A\A]A^A_]f.     AIOHI    MoMd@ AD$j     4 uHZH߉MLE1LEMH   L`MME|$\E1AM   I|$@ tLMLMLE#MLMLE1ID$@EAD$`HD1E1IfI    (Hف 1Ht MLE01{LEMMM>L'6fff.     UHAVIAUATS1HLg8dL,%(   LmIh t`M9,t-LN9rHف H{x 101+{HEdH+%(      H[A\A]A^]f     NHtMF8I} f.     H9r;HHtHHIHHH9uIULIL9u!L9t4I9~    HLCH I9sHLCHfD  L)HA4    UHAWAVIAUATS1H8Lo@dL$%(   LeIi tffD  M9d t-LM9rHׁ HBw 101yHEdH+%(      H8[A\A]A^A_]fD  cMAMtID$ LmH   HE"D  I$H1H9tdH9rHMMsHEMH}IJHHA HMH   u	HML9ut1~IWHCHHEI ID$HqH9uI9 L)H3    UHAWAVAUATSHH(Lw8Lo@dL<%(   L}IoLHD`LL},EM<I?jEDL)HI4Mt:HuHAƉM| E)I?iAFJ    LIt 豅k\HEdH+%(   uH([A\A]A^A_]2f.     UHAWIAVIAUATSH8uLg8dH%(   H]HHO@HMKA   Eo`HMEHADA9ŉEsmE     A    LD]HMHu	+IH  HMD]IG8Ht$HuHD]*D]HH  IO@Eo`EUHMM,ċEL)D؉HI<茄MHM  AV(f     rAv(9t
BvMu H  EAV(H<D  rAv(9t
BvL7H   ES(I<@ rs(9t
BvHHt+ES(H4JK(9t
BvHEAGi AG\MtIF Htf    HC Htf     1HUdH+%(   +  H8[A\A]A^A_]@ Ct- IH2    HEAGi AG\IF Htf  tLYHuqH]Ӂ 1H4 01uHTeD  IE     HtKEH    HEAGi AG\.fD  HHt=Lxf.     HdD  LH[LxHҁ H 101tS/I@ bLD]HED]HMEUHAWAVAUATISHHdH%(   H]HHEA|$h   LMl$8GEAxUIE H;E    H;xrA1D  H;:G  HA9!1HcIT H;zrӍp9~DEELG9EJ  EMt$8M,HCM} I9-  ID$@HEHrс 0HYԁ   ~+Hp    1sHuH;HuL/H} tLLEHI9   IGH9C  LFI} AǋED9  I4HH  HKH9u  Hu\dD+EHuPLHCLuMt.EM,I} *dMDL)ȍPAHI4Al$\L>F9EHEdH+%(   _  uHHHL[1A\A]A^A_]D@ LX/IH  HIFHρ 8~Hҁ (  IGE1H9C   I} LMjcMu IF LMHtf    H} q  EMuHLLLMH}c      HC Hm    Hk  1qD  E1Lu.IH  HCII+IAHρ 8~Hс  V  MI} LMbS(LM    JK(9t
BvI] HC Htf  a  H}Ht?ELML,I} )bS(LMJK(9t
BvI] AD$i uL1LLMgH}ak      EHMLML,I} aAV(LMfD  JAN(9t
BvMu EfD  LLMH;  L`fHuL{    HuLLM{MLMfD  LXCI|$8   HpAD$h.D  `S(fD  JK(9t
BvI] HC Htf     H}Ht7EL,I} `S(JK(9t
BvI] AD$i 1HEdH+%(      HH[A\A]A^A_]     E     H́ Hb 1LM01nLML`HCHt'L`7HLM)LMHt'L`H ́ H 101NnH́ Hۂ 1LM01,nLM=( ff.     UHHdH%(   HE1HUdH+%(   uHGX[(ff.     UHHdH%(   HEHGPHUdH+%(   u(fff.     UHHdH%(   HE1HwPHEdH+%(   u'ff.     UHATSHdL$%(   LeIp   \HHt?HfHC8fInCH6       HC\    Cd    fChHEdH+%(   uHH[A\]@'UHH dH%(   HE1Ht/H}76H}H@ r19t
BvHEdH+%(   uH&     UHAVAUATSH dH%(   HE1Ht1I5Hf.     Z9r9t/uHEdH+%(      H [A\A]A^]     uID$8HEID$@HEG     AN4    LuI>\I    HEHtN,I} \IE     L	?9rH}<[H}3[LkPLH HEdH+%(   uH L[A\A]A^]͡%     UHATSHHdL$%(   LeIYHLNHA胲HEdH+%(   uHD[A\]3% UHSHH(HudH%(   HE1HYHuH|H$HOHUdH+%(   uHH]H$     UHATSHdH%(   H]HKH=HA6EHUdH+%(   u	H[A\]f$fD  UHHdH%(   HE1H9HUdH+%(   u)$f     UHAWAVIAUATSHHdL<%(   L}ID H86H X{h u#H<H{8   H2ChH߰HJ{h tE1 @ HS8DLH<AAąuAH<A9rE1H5HEdH+%(   uHD[A\A]A^A_]># ff.     UHAWIAVAUATIS1H(HUdH%(   HE1;WE Ml$8L
<9s$HuMt I>AׄuAL;9rL} u4HEdH+%(   uUH([A\A]A^A_]fD  I6LELMHUdH+%(   uH(LH[A\A]A^A_]鐙K"ff.     UHH dH%(   HE1HUHUHuH5HE    ՇHEHUdH+%(   u!ff.     UHH dH%(   HE1HUHuH5HE    yHEHUdH+%(   u!@ ff.     UHATSHHdL$%(   LeIUHL.HAsHEdH+%(   uHD[A\]#! UHAWAVAUATISHH8HudH%(   HE1-UH5HHH[89LEA9   E1EtKff.     H;(#IHtpHLAH}LAbWEuD;}r    H}2L菭HEdH+%(   z  H8D[A\A]A^A_]f.     1AW뱐LmA}`L<    ILaHEH   Mm@MtLaIHEuMl$@E1Et$`ID$8HutN J<7"IH   HEN4IF Htf  }   Mu8AGIAD$\L9}uE1HE@hAD$i AD$d    AD$hAV(f.     JAN(9t
BvOt 1UA럐L8HtL`mf.     H) Hy 101WdEfff.     UHAUATSHHdL$%(   LeIKf.     H0HR{h u#H7H{8   H諮ChHHE{h tLk8HU7M|   txHHIt HL;"rSL;bsmJ(ID  qr(9t
AvH00HEdH+%(   u>HL[A\A]] HHu     HE1/ HLnH ff.     UHAUATSHH(dL,%(   LmIHIHtWH*xKA|$4 t3HLQMt:Me HUdH+%(   u9H([A\A]]D  I\$I+$D  1MuLHESHEf.     UHATISHdH%(   H]HHvH{H;7rH;wr&MtfqSHsLHHCHHtIHs4 t/Hs PHHCHUdH+%(   u$H[A\]@ HwH+7    $@ UHAWAVAUATSHH8HudH%(   HE1D  H8CDkdH4A9   HC@HtzN,IE HtmH   HuuYAU( JAM(9t
BvH-HEdH+%(   m  H8L[A\A]A^A_]f.     H߀{i    -HvO{i u+Lk@Mt7H?4H   LYCiH-     {`H\IH4  HLs83Lk@t1L         I>HtQ(frq(9t
BvIL= HI9uND  3AM  HC@HEHE HEMH}IN4M>IG H   kt7~II   IFHEfD  M   Mf.     MMt)Aw(f~A(9t
ƍFvHC@HELH+MHHKd+%H̦H@HLs82M$f.     M>IG HtH   Hu蔭t IM9ufHE1+AO(f.     qAw(9t
AvMxf.     UHAUATSHHdL$%(   LeI@{h uPH+HL{h u#H1H{8   HۨChH该H?{h tLHE1SHDhw1A9s4HC8N$Mt'AT$(fD  JAL$(9t
BvHf*HEdH+%(   uHL[A\A]]@ UHATSHdH%(   H]HL{h    HLc80AvnAPLI|fHHpHJH6HtH9sHrHH9uA@IHx t<Cj HEdH+%(   uaHH[A\]yf     tf.     H@fD  H80H{8   HxQCh6 UHAWAVAUATSHH8dL,%(   LmIGfD  H)HJ{h u#H/H{8   HۦChH诣H={h tHLs8/AAăxNII} E1H;xr>1@ H;:  HA9| HcIH;zrԍp9}EHLs8/HA9sDIMIH9r61(HEdH+%(     H8LH[A\A]A^A_]酄D  'HI{h I  HLc8.EAxWI$I} E    H;xrB1    H;:7  HA9 HcIH;zrԍp9~DEHLs8=.ME9  H    HEIHMIMH9|  EK`P9EǉEHVIH  HC8ChH{@ t8E1D  HC@DAH<tKH-A9rH{@ICi E1C`EtAff.     I>HtQ(frq(9t
BvI?HH9}uʋELHMC\uL}F+EHEMMlfff.     I7HIM9uEM,D  I<$IJID$    M9uLE1ڏHҠHEdH+%(   u{H8D[A\A]A^A_]ÐAn     HLUHA芠     Hh,H{8   H聣Ch     EHA5^UHSHdH%(   H]H.:H+u"HEdH+%(   u!HH]%fD  HC8H8f.     f.     f     UHSHdH%(   H]H<   tGHtfXHUdH+%(   uH]1UHHdH%(   HE1HEdH+%(   u0ff.     UHHdH%(   HE1f? HUdH+%(   u     UHH DdL%(   LMIAf.     BI9tt@fuHEdH+%(   u~H IHY 1H(T 01VD  AfD9rfEHEdH+%(   u8ÐH    ALM)ItI<HcHcLMAD@fD  UHHDdH%(   HE1fD;Gt*DMcfJtHEdH+%(   u:     HEdH+%(   u!H HX H`S 101UKff.     UHHdH%(   HE1ftHHDHUdH+%(   uf1f.     f.     f.     f.     f.     D  UHHdH%(   HE1HEdH+%(   u@ ff.     UHHSHdH%(   H]H1NffCHUdH+%(   u	H]2fUHHdH%(   HEHGHHGHGHHGHEdH+%(   uff.     UHHdH%(   HEHGHHHwHt211D  ff.     H@HHAHHABHH9rHEdH+%(   ulff.     UHHdH%(   HEHGHHGHEdH+%(   u&fD  UHHdH%(   HEHGHHGGȉGGȉGHGHHGHG HHG HG(HHG(HEdH+%(   uD  UHHdH%(   HEHGHHGHGHHGHGHHGG ȉG G$ȉG$G(ȉG(HEdH+%(   uH     UHHdH%(   HEGȉGHEdH+%(   u	f     UHHdH%(   HEHGHHHUdH+%(   uHp@ff.     UHHdH%(   HEGȉGGHUdH+%(   uHpjf.     UHHWdH%(   HEHGffWHHGGffG@uHEdH+%(   u>fD  HDHHDHUdH+%(   uWH4H)Rfff.     UHHGLGdL%(   LMAȉGGLHHwȉGMtnHG1@ ff.     ff.     ff.     ff.     ff.     HHHHHPHPHHPH9rIH IEuHEdH+%(   u.D  IIHEdH+%(   uwLD)Q
ff.     UHHdH%(   HE1HEdH+%(   uwHɃ
UHHdH%(   HE1HEdH+%(   uVK
ff.     UHAUATSHHH  L(  dL,%(   LmIH= H9xPT  H= H9xX  H= H9x`j  A$X
    A$`
     A$\
     A$d
     I(  HH9t*    ff.     B;H!H9utA,  u>I$  !A$p
     HEdH+%(     H[A\A]] H=Qg 1r\H=f 1b\[D  A$	  H=9f 1B\+D  H=e 1*\D  H=e 1\D  HEdH+%(      HH=f 1[A\A]][D  I$  H  I$   (  I$  HeA$$	  H=`d 1[J@ I$  A$	  HH   fH*H   fH*^f/ Y/ H=c    &[IH  f.     A$ 	  A$  H=b 1ZIH  zfD  HуfHH	H*XH\HHfHH	H*XDD  HuH=b E t} Ha H HEH=b 1A$$	  I$  HZIH  H=ꬁ H9x`x A$$	  H=!b 1ZIH  H= H9x`3UHAULo0ATSHH(dL$%(   LeI( uA|$       A   D     A   HcC@I| Ht$Hs8MDUHcC@MDUID     H 1D10HC`HHHCXHs8HS`HCXIDAHtHcS@HCHID oCXC@    fofsffCPA$   u!1HUdH+%(   u\H([A\A]]D  I$  HCXI$  f   A   H H]H 101JR '    UHAVI   AUILATISHH DDFH5H dH%(   HE1ZtH2;	   Mt"LH;	u\      ;3IHEdH+%(      KH L   [H5G A\1A]A^]s    LHE|yHMȄuH       H=wG H#fI
  HGLHL7IUH5    1isB@ AUX   1HMH5{ EsHM    UHHdH%(   HEHGHHGHGHHGHGHHGf vHG HHG HG(HHG(HEdH+%(   uC UHHdH%(   HE1GffWf= e  f= +  f:  G
ffw
f   fA   DEAf  HHHf.     ff.     ff.     ff.     ff.     o@HfofqfqfHH9uA   ȃ)Qv)P~WfofqfqffWt_ȉTOffTOP9sCLWffLW9s.TGffTGfD  GffGGffGHEdH+%(       GffWf= t4f= tnHEdH+%(      H Ha 101FG
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fI1@ HTHHTH9r&1 f.     UHHOWdH%(   HEGfnщɉOfnGfn؋GfbfnȋGfbȉGHG flGHHG t HG(HHG(vGpȉGpGtȉGtHEdH+%(   u, ff.     UHHdH%(   HE1?uGȉGGȉG@uHEdH+%(   u,f.     HEdH+%(   uGHɍp0}ff.     UHHWOdH%(   HEGfnfnfnGfbfnHGfbflHHGG@uHEdH+%(   u$fHEdH+%(   uGH ɍp|ff.     UHHdH%(   HEGȉGGȉGHGHHGHGHHGHG HHG HG(HHG(@uHEdH+%(   u'D  HEdH+%(   uGH8ɍp{kff.     UHH dH%(   HEGȉGGȉG@uHEdH+%(   uIÐHHHUH}<XH}HUHHHHEdH+%(   uBH4)Z{D  UHH GdH%(   HUHȉGGȉGHGHHGHGHHGHG HHG G@u&B(ȉB(B,ȉB,HB0HHB0HB8HHB8@uHEdH+%(   uFÐHzHHUH}_WH}HUHHHHEdH+%(   uBH4)}z     UHH dH%(   HEGȉGGȉGHGHHGHGHHGHG HHG @uHEdH+%(   uHHH(HUH}VH}HUHHHHEdH+%(   uBH4)yED  UHHdH%(   HE1HEdH+%(   u@ ff.     UL HAWAVIAUATASH(HH^dL,%(   LmAHwH LH1Hٿ   H5n[ !kH  IFHEH؅     E1HH  HDDDHAW   DDHHHHDAWHDDHHHHDAWHDDHHHHDHAĉEA E1fff.     HuDDDL4Ƌu75L   H55> H1>jAOA?   HHH!   A   H 0   A    HH  HDDDHAW   DDHHHHDAWHDDHHHHDAWHDDHHHHDHA     HEdH+%(   u6H([A\A]A^A_]fH 0   A    O@    E19fD  UHAWAVAUATSH8L   dH%(   H]HI   )  1H5=    hI?    E11L5< L-<= Z    H   L< H tL H MDŐDH5w=    1zhAD$II;smILHtOvHt7LQ< HtLo H MDfD  L<     L-<     L< t@     {  HEdH+%(     H8[A\A]A^A_]ÐL   Mq  ID$IL$    HDHEH1E1E1#f     ff.     EnMLI9sK| uH9dI$HWAVH5;    UHT11gE   H; E1IHE@ KLHuD1   LEfLEIM9uHEU   AHuE1HH1f1I<$ t9ff.     HuH@C.   HHu1fAEII;$rI HEdH+%(   u7H8H=d; [A\A]A^A_]/=HE    H; HEKfff.     UHHdH%(   HEHGHHGHGHHGHEdH+%(   u[ff.     UHHdH%(   HEGȉGGȉG@uHEdH+%(   u#ÐHEdH+%(   uGHɍppsff.     UHHdH%(   HEHGHHGHGHHGHGHHG@uHEdH+%(   u"HEdH+%(   uGH ɍprkff.     UHHdH%(   HEHGHHGHGHHGHGHHG@uHEdH+%(   u"HEdH+%(   uGH ɍpprff.     UHH dH%(   HEHGHHG@uHEdH+%(   uNfD  HHHUH}NH}HUHHHHEdH+%(   uBH4)qUD  UHAWIAVAUMATILSHHHuIX0HULMdL4%(   LuMp(A    HEM  U     A    HEM1IIrD  AwUHHEHtfIUHMIW IU H+IW0IU HHIHt?I0 tHELELHuHuDMA;  }3IuLWDHuA$`
  MA;  |f.     1HUdH+%(   N  HH[A\A]A^A_]@ I  LECHH   UAwHHtuI  IW I  HH+IO0HHKHtMI0 rHEdH+%(      H}LEHOfIuLUqCHHuQf     A$`
  "fHEdH+%(   utH}LELHHuHHL[A\A]A^A_]@ UAwH(HtIUIW IU H+IW0IU HHKH/w     UIHAWIAVAUATSH  HhL`dH%(   HE1V     L
  H
  I9  M,$LHxMHXM HHSpHQH
H{;mH3mp   IU LL;x   IHsHLM   A9L$uHhH H9ptjƅ HLRHSLL`HXIH 3H@pylpfD  LHU    HEdH+%(      HĈ  [A\A]A^A_]    H' HO 101U5 HpHq Hx)RLpHHEdH+%(   u6L`HxLHhIBHĈ  [A\A]A^A_]1LeD  UHAWAVAUATSHx  HxdH%(   H]H(  L
  H
  HhI9   H0  M&HpmHHaQIVHLpHxIH}IAIFHBHI~jLjEuJI$ML;htfIIvHHPKAǅuH HON 1013HEdH+%(   u"Hx  D[A\A]A^A_]     E1&fD  UHSHdH%(   H]HH(  uHUdH+%(   uH0  H] @ ff.     UHAWIAVIAUIATSHh  HxH@  dL$%(   LeLH  x#    @t   HAQtZH 8 u&A@H5 HcH>fD  I(  LxLLHfD  Luf.     Hx`t^@ LLxLLLA$@  LcM1  Hj 8 t%I(  LxLLHUD  HdHEdH+%(     Hh  L[A\A]A^A_]@ LLLA$  LcfLI(  LA$   LcfD  LLLA$0  Lcw    AoLLLA`  AoFAp  AoF A  IF0I  A$   Lc# LLLA$(  Lc    LLLA$   Lc    LLLA$  Lc    LLLA$  Lc    LLLA$   Lc    LLLA$   Lcg    LLLA$   LcG    LLLLLA$   Lc@ I@  x    LLLA$H  IfD  LLLA$   Lc    LLLA$   Lc    I@  x    LLLA$   Lc~fD  LI(  LA$   LcMWL菂I(  HH9u   ff.     H H9   @;t   I0  M\fff.     E1     LLLA$   Lc    LI  LA$   Lc LLLA$8  Lc    t1L@U Avt1L#UW1>fUHSHdH%(   H]H0  HOyHUdH+%(   u(H]fD  HEdH+%(   uHH]需W    UHAUATSHdH%(   HE1H   IUI$@  RI$0  0I$x  Ht HHHwrHuI|$@)I$0  UI$@  Ht(tZmI$P  ~HEdH+%(   uPHL[A\A]]c    HEdH+%(   u(H[A\A]]fD  I$(  hI$@  <ff.     UHAWAVIAUAATISH  H(dL<%(   L}IH   ID  H`  L`Mn@I  Ix  I  I@  fHnI0  flHHEA@  uI  1H5O  eLRH   H~  I@  {(  I(  HtLx
  I8  YAP  C(   {  u!MtA$Q      fff.     HEdH+%(   B  H(L[A\A]A^A_] I(  M8  H   Lx
  I8  X ff.     AP  LhH HS* 101*J LP1H H"* 101*f.     A$P   !I(  5ZH=>E AAƄ$P    Hhts@ LEuLcu@ LW L     Lk@tH` @&{  tFI(  Lo{! uL-: I}8 I}0 H IE8    L@u8I(     I(     I(  [tt{  gL|I(  HH9u%@ H H9t@;t   H}tV)1HC HȆ 101(H:( H( H'      UHHdH%(   HEȉGȉG  HWHHW  HWHHWw  HWHHW c  HW HHW 0`  W0ʉW04   W4ʉW48vsHW8HHW8@vcHW@HHW@HvSHWHHHWHPvCHWPHHWPXv3WXʉWXhv&WhʉWhlvWlffWlpvGpȉGp~O(fnfofp fqffofnȸ????fqfp fffnȸfoffp fqf~ ff~ fffnfofp ffqf~ f~ fffO(HEdH+%(   uÃ((`UHATSHdL$%(   LeIHBAD$At$I|HEdH+%(   uHHL)[A\)]^@ ff.     UHH dH%(   HEH 8 u#HEdH+%(   u2ɾ   H^fD  HY 
   HUH0p HUD  UHHdH%(   HE1HEdH+%(   uHǰ  `D@ UHH dH%(   HMHHt7H    HHMHMtHEdH+%(   uH    N/A ff.     UHAWAVAUATSHhdH%(   HE1Hy E    8   Ln(I1IfuHA  9  KAT$s1s0H5?    LDCNIF(ZY   I~XHIF(  A9  {  A     A     A      A @ w  A   J  A     A  @   A     A   v  A   Mn0H=^$ $Ab  A8  H  L  A  H5o$    1M  ~cAL5a$ A      ff.     I$IT$L1   IAM
   D;  |fff.     HEdH+%(   -  He[A\A]A^A_]fD  A8   hxH   H  HPL`    LEH   M~XHHuA   f  HW" H5a"    1LH   H8   LxLpD  A|$ML5 I  LED$M$H5O A|$IH] HN HN EL$AHEAH7 HEH AHEHN AL' IEHAIMD$AVEASW   VH5R= QLRLP1KH   H@L;8LxLpH} 
LE1J`HUHuHrH   DEH5(= M   H1fKH   H: L}LxIH  KLH޿   1I&KI   L; rLLxA   uH    gHDeI&Hx PUDHH=  H5 qH}raHuHUHfEf     @I    HH
  H5 1   ZJH   H8 IL$M$1ҿ   A   H5t; 1%JH   H8dLxIIA   H f     I$IH޿   L1III   L;8rLLx    HS@H5    1In@ H{xHuoH5    H1mI5     H{pHunH5S    H1=I     HShH5    1I@ HS`H5    1H@ HS81   H5 HA   L  
   VD     H   H5: 1   HfH    HDejHx UDHH=  H1L   H5 7HA   
   sfD  I$IT$L1   IAGIT$H5 1   G
   &D;  |h     H  H5,    1GH   H5    1G   H5H    1fG   H5. 1   LG{E1BH   H5    1%Gff.     UHAWIAVMAUIATISHH(H9| dL%(   LELE8 tLHL%Iw L9IH 8 tA   <v#;  H  HcH>    A   utF
tAAwH~ LULx$ tT<LUI 3LUIf.     s HEdH+%(     IFxH(LLHL[A\A]A^A_]D  HEdH+%(   p  IF0    HEdH+%(   P  IF8    HEdH+%(   0  I   @ HEdH+%(     I   `HEdH+%(      I   @Hz 8 tKAOS   1M   EGH5Z LU
ELUAB( u
A8   tIzXLHEdH+%(   u}H(MLHL[LA\A]A^A_]     HEdH+%(   uDIFp     f{   IFXH;{ ,  @ HUdH+%(   \     HEdH+%(   uIFh7     IF`H;z uHCtI  HCtI  HCtI  IF`zf.     CtAp
  HEdH+%(   bIF fD  MS  Mj  LLHLLU9A    LUtAV   U  HEdH+%(   H(MLHL[LA\MA]A^A_]eD  Hyx 8 tdLLkLUNKS   IMH5 1BLUMt,Mj0A  Au  AG  A  HEdH+%(   PIFH(MLHL[LA\A]A^A_]f.     HEdH+%(   IF@c@ HEdH+%(   I   @HEdH+%(   I    HEdH+%(   IFH@ HEdH+%(   IF(@ IFPH;Uy _HCI  IFPK HEdH+%(   HIFAX
  HUdH+%(   H([A\A]A^A_]D  HCI  IFXA`
  1HCI  IFXAd
  LH1L1뉿   NIH   DsL5ID$H   LHHiII
  I
  M
  fHnfHnflA$L 1HS0   1LUH5 @LUHS(   1LUH5 h@LUHS    1LUH5E D@LUgHSH5    1$@LU=LLzf     UHAWIAVIAUIHATSHh  HpLxdH4%(   Hu1jI(  HL,Å   LHLLeR   uKHLMI(  xLpI0  H:XHt Z8 ubf.     HHEdH+%(   uUHe؉[A\A]A^A_]@ Hr HP 101 @ H} tHL;ff.     UHHdH%(   HE1HEdH+%(   u#HNHFH  LFHH  Hc ff.     UHAWIAVIAUATSHH(HMLH  dL$%(   LeL(   uM3VvvC  H=0 1!CHUdH+%(     H([A\A]A^A_]     LhCH HHHtHf     I$  :;?wnAP   tDHUHLHEPwLEHULHLt
HI LELLHLH*@ HEdH+%(   u-HMH(LHL[A\A]A^A_]HO@ ff.     UHAWAVAUATISHHL(  6dL<%(   L}ILH  I  9A<$?wBHLLE1j H0  MLAZYHUdH+%(   u!He[A\A]A^A_]Ð11LHf.     UHH   H$ HP	  dH%(   HE1IHHHHH@      H~      o1LoFoF oF0oF@oFPoF`oFp(o   H8clHUdH+%(   u'fHn Hz-    01x     UHHdH%(   HEȉGffGGffGHEdH+%(   u# UHAWAVIAUATISHH(LEdL<%(   L}Mπ   t
 K  I$@  x    x# O  DhI  1D6H      HD]H   A|$    Cf   I9   LpHsDLL9   A|$ u<Mt;?vbHEH1HUdH+%(      H([A\A]A^A_]    I$(  #?Hj HHtH    I$(  LH&tf     f     Hxi H  H+  H>f.     HxHus=HuARfUHAWAVAUATSL$  H   H$ L9uH8HHIIdL4%(   LuMHHL$Hf     LE1LHH   0u/HLLHAׅuHJI̓:Gt)M9rHUdH+%(   u$H8  [A\A]A^A_] LjM9{T@ UHAWAVAUATSHXdH%(   HEH  LxM   I_ Mg(L9   IG0H}MHEHEHEfD  Hp  EċEą   HCI9ryHEL<HEx    EOIMI9  Hv 1ҋHHLH)L9s2HEIؿ   Hj H{) H 0AT1XZ1HUdH+%(     He[A\A]A^A_] LgEOJMI9sLLMfLM]fIF  IFMnHEHEH(  LH  x    A7VvVEoA  H=X( 1LMAGLMH   I^ Mf(LI^ L9fD  H  LM2A??LMB  A$P      HULHLMHE8LMP   HH   fff.     Ie     HLM;AHZ LMHHHLA7LMfA7I  IFMnHEHEH(  LH  HMHUMLH}LMLMulff.     HMH}MLLLMLMHHLI^ M0Dh3@ HUH}LL=LM    H@ I^ MHh IOA1EH.' 0H1:
[LI^ M0M     UHAWAVAUATSH(HULG`I@dL$%(   LeLg8I99  LoHHIMŀ~    EuK0MI9   H:s 1ҋLHLH)L9   HFg HEH& HH    0AT1AZ	XZHEdH+%(   >  HeD[A\A]A^A_] LLEcEuLEK0I9~   EI wI   HKHSPLLS HxrIoS`LsPLfInflfC`Aą   H}LIA   =D  LLEDubDMLE AAA]Hk% 1D0oCXH
f EM foEEfs01ffH~&AA   AfUHHdH%(   HE1HEdH+%(   uɉH0  =fff.     UH0  HSHdH%(   HE1?HHHHUdH+%(   uH]fff.     UHAWAVAUATSHH  dH%(   H]H  L@  Eu E  A}! tAE@k  L    1LHA}#   AE IEoCH(HcH@f)0AE$fH~ֈHHs  H   H LH  HHL  fo0foEfsffH~H  ƃ  fօXLm1HǅP    L  HELmH  LLHLĹtQafD  tHh   fo0fofsffH~H9p   LHLayHx  LH  kAT   '  LMHQDLeMt*A@ ff.     LM$$Hw@JMuDLƃ   HEdH+%(     HH  [A\A]A^A_]fD  HǅXsHx  LH     LLH/<LHZH0  1H5 k@ HHD  IE LH  8-t  x j  H   IHj  L  E1Hƃ0  ǅH  HLL0 H  Hf      H@     LwIH
  { Y  AMIf  9K  t IuH@  H'H  HH  L(  H{ ?  Au Vj  EEA
  H= 1AEMHI@ HH  LHH   H HHIcU@y  IE8HRA   HH ff.     H8AHH9uIcHi   HIH  H@  x# 3
  Pp$L@L1   oCHHhAv(1fAAFMFIF LAoFIF0    M~xLfoAF`fsffAF84e  M   HHL  /  AU@C  E1DMA   IL$8KvHHpH   McDXL   Mi   HH@  DH$1LHHHkHr1DLRHB DJ(HLoBHB0    HJxHHfoB`fsHffB8/Y
  HHHH   HL 	  AT$@AID9DDL5c A@ A  uLMcHMi   Lp   oGfofsffH~H9GP  GpuL     Lu,HHuH0  1H5R蝻`HT   b  LMcE1GHx  ƃ   DH  Mi   @ ff.     LMI$   Htf     HHHwDHuI|$xIŨ   kM9uHDc     IuHH   H HHH  wIH  L  HDE1ƃ0  ǅH  HLL? H  HLH`    >  H@     LIH  {   AMIf  9  t IuH@  HxH  HH  L(  H{    Au V  EEA  H=% 1
AEMHID  L0W LHHH  HHpIL8,AU H} HHHLAu VI  \#A} ?>  HP   taHLLHǅPvHHx\MiHLLHL? Hu&     HLLHL HH	LLLE1Au EEHEY AH1H^ 01mL
2EW  A$T     L讹HV:N I})L@  3HU LLH7f     L8UQ LHH%H7  HHpIAf     I  !A} ?  HP     HLLHǅP   HHR  M<L)AU H HHHLH   HHH  S  0  LI}h IEh    AGAAHLLHL u @ HLLHL THHXLLDL H߉ZLLL/	H0 LLHrHLLE1LLLIE1M     LLHyLH$0H0  1H5*uMLLE1HU H 1L01wLLLy.tLLE1.Hx0&H@  HHLpL  LLIE1HU 0M   H 114LLDL:LDILeMLDL   A   HtT H@ 1L01(HP 11LyLDL|LDILDL  Hx  H  DL  ǅ   LLLD$4MLLE1HYS H 1L01MLDLIff.     UHHdH%(   HUH(  HH9ufD  H H9txu   ! HR HHw 1011HUdH+%(   uD@ UHHdH%(   HUH(  HH9ufD  H H9t@;t    1HUdH+%(   uUHAVIAUATI   SHdL,%(   LmIHtbLHHHtG]   H6Ht  LkLHHtH1HUdH+%(   uH[A\A]A^]Hv*:f.     UHHdH%(   HE1HEdH+%(   uH0  /@ UHHdH%(   HE1HEdH+%(   uH0  购@ UHAUIATSHdL$%(   LeI   b	H    H H HD1LI(  LHcH  HHUdH+%(   uH[A\A]]fff.     UHAUATSHH0  HdL,%(   LmI H   IHtHLe HI
HHuHEdH+%(   uHL[A\A]]萬UHAVAUATSHH.P HO dL4%(   LuIH8D+D	   L%S    H= I$#I4$I      OD+HEdH+%(   uH[A\A]A^]f     UHHdH%(   HUH(  HH9u&fD  H H9t9puHUdH+%(   uf1藫    UHSH(dH%(   HE1HtoHHtgAH}H      H= DM3UH}H
HEdH+%(   u9HH]      H= fD  HEdH+%(   uH]fD  UHAWAVAUATSHHdL4%(   LuIRHHHIFHEH9b  HH@IHH9L  1I(  HEH@O 8   E    IA   H}     fD  H}WIH  IFAE IFfAE$IFAE(HM  HAE,HKEfAM0   ;E  I0  HHE`HH  AP  HHMA m'Hd  H茺I@  umHMHA8AE,EH'R  AVuH}Lk H  DhH;HI L;e  IHM I68 L-L HH 1   I} 豧INI} 1H    薧INI} 1H    {I} IN1H    `I} H   HH    1=I} HK1H    "I6H}IH   IFAE IFfAE$IFAE(3@ HHHH9  HHI\D  I0  HE     H
   I6H}HtZIVP IVfP$IVP(1I L;esff.     1HUdH+%(      HH[A\A]A^A_]@ ӐH!K HM   H= H81f.     HH5    1{HH5 H1   f     UHATSHdH%(   H]HH0  Aąu-H   HuHHHtHtAHEdH+%(   uHD[A\]qUHHdH%(   HE1HUdH+%(   uHG@;ff.     UHAWIAVAUATIS1HdL,%(   LmIDp,LHt
@(   uL#IH      LA9DO11A9     AD9}gID   HHLI	T  AL91L#HEdH+%(   u}H[A\A]A^A_]f     HiH 112H fD  HAH H 101oH!H H 101OȤ     UHSH(dH%(   H]HHE    H   H}9H}HHt}@ ufHUH0  H5HM+EftrfnMHMfnfbfA HtUHUdH+%(   uRH]f.     Ht܋A$A ҐHUH0  H5n蹥EfuHt    >   ɣf     UHHH`  dH%(   HE1HEdH+%(   uHG胣 UHHH`  dH%(   HE1HEdH+%(   uHD@ UHHH`  dH%(   HE1HEdH+%(   uHG UHHH`  dH%(   HE1HEdH+%(   u
H   UHHH`  dH%(   HE1HEdH+%(   u
H   耢UHHH`  dH%(   HE1HEdH+%(   u
H   @UHHH`  dH%(   HE1HEdH+%(   uHG` UHHH`  dH%(   HE1HEdH+%(   uHGpá UHHH`  dH%(   HE1HEdH+%(   u
H   耡UHHH`  dH%(   HE1HEdH+%(   uHG8C UHHH`  dH%(   HE1HEdH+%(   uHG( UHHH`  dH%(   HE1HEdH+%(   uHGxà UHHH`  dH%(   HE1HEdH+%(   uHGH胠 UHHH`  dH%(   HE1HEdH+%(   uHG@C UHHH`  dH%(   HE1HEdH+%(   uHGh UHHH`  dH%(   HE1HEdH+%(   u
H   UHHH`  dH%(   HE1HEdH+%(   uHGP胟 UHHH`  dH%(   HE1HEdH+%(   uHGXC UHHH`  dH%(   HE1HEdH+%(   uHG UHHH`  dH%(   HE1HEdH+%(   uHG Þ UHHH`  dH%(   HE1HEdH+%(   uHG0胞 UHHH`  dH%(   HE1HEdH+%(   u
H   @UHHH`  dH%(   HE1HEdH+%(   u
H    UHHH`  dH%(   HE1HEdH+%(   u
H   UHHH`  dH%(   HE1HEdH+%(   u
H   耝UHHH`  dH%(   HE1HEdH+%(   u
H   @UHHH`  dH%(   HE1HEdH+%(   u
H(   UHHH`  dH%(   HE1HEdH+%(   u
H   UHHH`  dH%(   HE1HEdH+%(   u
H   耜UHHH`  dH%(   HE1HEdH+%(   u
H  @UHHH`  dH%(   HE1HEdH+%(   u
H    UHHH`  dH%(   HE1HEdH+%(   u
H   UHHH`  dH%(   HE1HEdH+%(   u
H  耛UHHH`  dH%(   HE1HEdH+%(   u
H   @UHHH`  dH%(   HE1HEdH+%(   u
H   UHHH`  dH%(   HE1HEdH+%(   u
H   UHHH`  dH%(   HE1HEdH+%(   u
H   耚UHHH`  dH%(   HE1HEdH+%(   u
H   @UHHH`  dH%(   HE1HEdH+%(   u
HH   UHHH`  dH%(   HE1HEdH+%(   u
H@  UH= HHdH%(   HE1HEdH+%(   u1聙UH= HHdH%(   HE1HEdH+%(   u1AUH= HHdH%(   HE1iHEdH+%(   u1UH=V HHdH%(   HE1)HEdH+%(   u1UHHdH%(   HEHp= 8 u+1H= HEdH+%(   u"1f.     H!< HH0^W    UHHdH%(   HEH = 8 u+1H= mHEdH+%(   u"1f.     H; HH07    UHHdH%(   HEH< 8 u+1H= HEdH+%(   u"1f.     HA; HH0.3w    UHAWAVAUATISHH8HMLEdH<%(   H}HD   H  LXMe  MS(M+S E11Ol0A"      LL]LULUL]HI  HEMoIG     IGHEIGM   A$Q   SU  It$Md$H  MKL0LHxIH   IG(H  H8 tH@L8H  LH    LxHq9 011HUdH+%(      H8[A\A]A^A_]@ IC LI0LUIt0LUMW(A$Q.It$Ed$I-fD  Mn0E1A1"      LwIHtRHEMoE1IG     IGHEIGLL/ H8 H 101Hu8 HF 101ff.     UHHdH%(   HEH9 8 u+1H=D -HEdH+%(   u"1f.     Hq8 HH0n觔    UHHdH%(   HEHP9 8 u+1H= HEdH+%(   u"1f.     H8 HH0辕7    UHHdH%(   HEH8 8 u+1H=d MHEdH+%(   u"1f.     H7 HH0NǓ    UHHdH%(   HEHp8 8 u+1H= HEdH+%(   u"1f.     H!7 HH0W    UHHdH%(   HEH 8 8 u+1H= mHEdH+%(   u"1f.     H6 HH0    UHHdH%(   HEH7 8 u+1H= HEdH+%(   u"1f.     HA6 HH0,w    UHHdH%(   HEH 7 8 u+1H= HEdH+%(   u"1f.     H5 HH0    UH=V HHdH%(   HE1)HEdH+%(   u1UHAUATSH   H$ HdH%(   HE1H~3AH H)H~    HDH9HNeHHEdH+%(   uH  [A\A]]> ff.     UH= HATISHH dH%(   HE1PI$@  x  tHsx# u(x HCHUdH+%(   u"H [A\]@ HxHuHu؉覐fD  UH= HHdH%(   HE1ɾHEdH+%(   u1aUH= HHdH%(   HE1艾HEdH+%(   u1!UHH~|4 dH%(   HEHƇT   ǇX      ƇV  fHnHfHnHfofHnHxfofLnflf@f fAoHflf~P  foflflO fAl~ O0foO@flfl   ~^7 2    ~@7 'fHnHflWfHn~6    5 HWP~4 6 W`~x2 I5 Wp~ fև   fl   @tH6 ~ H   H@   fHnHMfl   fHnH   ~    fHnHfl  fHn   ~ fl0  ~z fl@  HEdH+%(   uUHHdH%(   HEHH9@  HUdH+%(   u谍UHH~ dH%(   HE1H`  P  P  Q  Q  R  R  S  S  T  T  X  X  V  V  HefHnHflfHnHfHnHz~j~ fHnH&flfHnHVGfHnH~>~ fHnHflfHnHG fHnH~~ fHnH~flfHnHG0~} flfHnHRG@~} flfHnHGP~} flfHnHZG`~} flfHnH>Gp~} flfHnH"   ~} flfHnHC   ~t} flfHnHd   ~]} flfHnHE   ~F} flfHn   ~6} fl   ~+} fl   ~ } fl   ~} fl   ~
} fl  ~| fl   ~| fl@  HEdH+%(   uˊf.     UHHdH%(   HE1@u f   HEdH+%(   u7@ HWHH    HǇ8      HH)Hׁ@  HJf.     UHSHdH%(   H]HH   GHEdH+%(   uH   H]'fUHH dH%(   HEH   HtHUdH+%(   uPf.     H}   ¾HMH   HuH, H 101HMH   g    UHH dH%(   HEH   HtHUdH+%(   uPf.     H}   2HMH   HuH;, Hd 101iHMH   ׈    UHSH   dH%(   H]Hƅo H; t
f    tHEdH+%(   #  H]HH1HPHXHXHPf>Az  fvdH 0  -  L   fA  fA>  A   HH   Lo']f   Qf.     A
   ftwf   fuL   HLoA   LLX'LXf   oHpLމXxM;XSf     f= fD  A   L   HLoDPLLX'`fP>f   LXY?     f=wRf= A  A   Hz    A   yD  A   SD  A   f=&T3^f.     @ UHAVIHATSHdL$%(   LeIHL	HtTHH=ы IBt^HH= /Mt*u&   H5 Lt> ff.     HEdH+%(   u=H[A\A^]fD  H)/ I
  LtH. I
  of.     D  UHHdH%(   HE1HEdH+%(   uH,ff.     UHHdH%(   HE1H9HUdH+%(   uf     UHAVSHdL4%(   LuIH~PHt.HH5P HtHHUH5? 1t1HUdH+%(   uH[A^]HcUI;uHSIVX     UHATSH0dL$%(   LeIԃ x,w7H HcH>@ =     fff.     HcHE    H]HE    Mp  L9%\ tgHUH   LH}HV HHDH\ HEHtPI9t|HUdH+%(   0  H0[A\]    H=q\ HUHtH}`fD  H5H=H=    L%2\ H#\ HEH{HHE    Ht'H=[ E1HHLMȹ   HH}HE6f            D        @     yf     1f     Hi[ HE;ff.     UHAWAVAUATSHHdH%(   HE1>	t'HEdH+%(     He[A\A]A^A_]D  IhIHtEl$\EtI$   HtH@H=  I  H=   -  HR H=   uA	  I      ME1I        C&I  LUAzK\&fDHDL IDHIH$ H MEH5 L]H81H}!ID$LUI9rI
M9vHEdH+%(     Ht$ HT H5* H8He1[A\A]A^A_]VA~mI  El$\I$   @ H. @ I  HEH  D10D  H;f8y  @fHDH9`  HH9rH 1D  H]L-# IHU ff.     HEI} J8f;  SCH56 fH fDEDAL1NM5  L}ME1ff.     HU}DL NLLHI} IH LEH5 1IILPM9uJ   L}IL;}"D  HEdH+%(     H" H 10He1[A\A]A^A_]>fD  H1H)HDH! H11H) 3
HEdH+%(   s  3HeH* 1[1A\A]A^A_]       7LCILS
D[L{HsI8fH[ DDfHHuAv8HH]I^0DMf(EAIHH]f<DIԃL<D҃݃C<AӃMAEAAAEHAWAASAQENSAPEBTVH5 RHS P1#H@I} PH M1uLEH5 HMXZ&H= qyI  El$\HEI$   |f.     D  UHAWAVAUATSH  dH%(   HE1>	u	Dr\Eu+HEdH+%(     He[A\A]A^A_]f     HHtċ@;U HtM;U uL   ESDШ  HEdH+%(   %  Hr HC 0?    L   EZ
DШtCHEdH+%(     H1 H 0Heؿ   1[A\A]A^A_]NfD  H; =T IZ~n fHnH+ fHnH. HH* flflHH fHn)foH flfHn)f)~ n )Efl)E)Ee  E1AtHH5LŠHH3LŐHE=T  Hc  ALwO tHL H8H LEHHHLH9IH8LH7LЃH%O MMHDH4EЃMLDHI AAAQEAW   VH5U RLSPLH2AVPLH1PLH0P1}H`   1LH5 IRLTLAB
  IRHEdH+%(   
  HeH5M 1[   A\A]A^A_]fHp=R  I[HHǅp    )EHǅv    E  HE=dR  HE  HH IH H    LxAHEHHIHARHPHH	H5 PHHPL1%LxH0AC@   ISHIIHH(I'I&H AHAH%@   @H=A H- HDLJ @H=1 IDLK H58 LELxH5_ SARAPAPA1QW   aH0=Q Lx  =P   AC&!  1MS$ƅ  fHǅ@    Hǅ`    Hǅ    f)p)E)0}E)P)) )=lP   HLHpHH0Hh!  LHPHHx    =P @k  HHXH HPA     LLHLLH0MHDH`LЃHHMЉLЃI HEALHAALHAALHAALHAAHA@HDHDIH`AP1AQhxSpPAVASAWATAUVH5 Q   RLXLLHHĐ   AC&h  6  AC IS<HHEdH+%(   6  HeH5    1[A\A]A^A_]IS=HN    HIHIg ILAHI <  1H5    LxNLxfE1Ƀ=M ƅ  MS$fD)p)EHǅ@    Hǅ`    Hǅ    )0}E)P)) )Mѹ
      
   HIL` L`HHp1ALx?Dx   1H0      AL Hh	L`Lx=L A  HE1H5LH*H HIfHHDxIH=I;LLE A*      PHؾ*   H<P1dA\A]DxL6IRH5    1uL'HHHIH?DpI;Lּ LxA      P   1AZDpA[Lx^IHL 1I         ADxL蓿DxLIS4H5    1LLIS,H5    1LwLAC&iLA      1HL-    H߃LXL`A   LXL`ISH5    1LxLHMѹ   HLHIL? L`A   PH   1`      H`L`L    HI$HA1      L`HLE    IHHX1A߽      L`H L    IHHP1A袽ZY=I LHL`H  Ht HEDIIA	ȃ   Hb HcL&   HrHD LLHMHH   LHI   L`AL 	к   LHPH1轼HcHa HLLٹ    1      苼^AX=iH L`LHLC L7E1E1&o@ ff.     UHAWAVAUATSH(Hx
  dH%(   HE1耔HIELA
EtuHALm     HH\ArM1LHUHH5e ձuA} ibs_   Hibs_fetcI9E uA}huErG H5 H5 LJHtHG H' H5 L(Ht%G H H5ϧ LHtG G 1F uJHEdH+%(      H([A\A]A^A_]fD  fA}op1EF D  F t       LPHF HF HH5j 1衰tHu H]    01蠲mf     UHHdH%(   HE+   ;=.F tD   H_ F    HF yT1HUdH+%(           HE Htu=  ~HcЉHiMbH&)i  )Q9~HHH     =E tWHp_ ~E    HoE gf.     >uS   HRH_ =ME HH:E aD  H)E HH	_ HE 
k   뫐UHAWAVAUATSH(HudH%(   HE1+   ;=D    1   H@Hm^ =D HHD XH   L0Lx     IH}IO,gAE I4dt(~HHtEM}    Mt3LfD  AE HUdH+%(      H([A\A]A^A_]Ðf     HC HT1-# =C t%      fD  >u   HC HYjf     UHHdH%(   HE1+tX;=rC t81uaH@H] =XC HHEC @HUdH+%(   uPH)C Hu1t =C t      렐>u   @ HB Huifff.     UHHdH%(   HE1+th;=B tH1uqH@HV\ =B HHB H@HcpHUdH+%(   uYf     HYB Hu1t =JB t      됐>u   @ HB Huhfff.     UHAWAVIAUATSHdL<%(   L}I׃+   ;=A    1   H@Hm[ =A L$L%A AXAD$9   LcMAD$I9~oID$LB(I$H<tAID$B(HUdH+%(      H[A\A]A^A_]fL%A Mt1M3 f     =@ t%      fD  >u   	L%@ Migf     UHHdH%(   HE1HEdH+%(   uZ%gD  UH HAVAUIATSHGtL&dL4%(   LuIH_`Hw`D@H
 LDGt   01ɤH  IU(L;#raHC H9t! ff.     HXL;`rvHC H9uIE0fHnIN IM0fHnflAF HMegD  HXL;`svHC(H9uIE(fHnIN fHnHHflAF IM(*     HPfHnIN HHfHnflAF H
HEdH+%(   udH[A\A]A^]fHfHnIN fHnHJflAF HD  IE(IM(IV fHnfHnHPflAF IU(MeefD  UHH HN HF(dH%(   HUHV HAHHG8HO8fHnfHnflHPF HW8otHF    tHuHF    HEdH+%(   u PH)W HHuHudUHAWAVAUATSHxudL%(   LMDOtE"  IV  @  W  .  Hw(HG(HO`H9HU  HFHGHH)HHHW EH惀    LH Hw 01LpH IWH    01IG`MgHǅh    Ht
H HhM   IO(HM}   IG(H9  HL5S LhH KM;e V  LLAWhAÅa  LL膨IE IIHC HK H9E  HYAEċEątMgIGL}uIGHEE1AGxH EOtD]H Lp   01H IH    01ݠD]J    < u6H
       H= H薁;    ff.     E1HEdH+%(     HxD[A\A]A^A_]     }   HWE f     EIGH     IW    HEAwt1H HHxmIG(H9E   HXH L5|
 LhWfD  L;#   HLAWhAÅuHL賦H   LHxIIM IE H9Et{LiAEċEątD  E IW E     HEI;G(tVL;hIG0H IG`} 讔f     HEI;G(tL;hrIG`    ΐIG`    MgIG`    }`fff.     UHHdH%(   HE1HEdH+%(   u1y`f     UHAWAVAUATSH8HMdH%(   HEHBH,  HIIMH;   Lc8       M  HC8MI9   HHPfHnL`flHQH
 M\$LHM4$HEM|$ID$1HUdH+%(     H8[A\A]A^A_]f     L%Y H    1A4$rA4$H1DCxHN    Lc8PC|    )HCH9C suAuLؽIH  AEHC HC8I9	fD  HKXH   HcSpHHRHCpLd=U  HCX       Hc    V  M  HC8I9  HHPfHnL`flHQH
 Ml$LHM4$>f     HK LKH   L9      LMHML]LMHMHHCXL]R  H H A      L]01cHCHHKHHSXfHnHC    L]fHnHPflHCXHSHCp   L`fD  Ha Lɿ   H 01   H    @ ff.     HCH9C sFAuLHt4AUIHS    Hƕ    ufff.     ;fD  HKXHt7HcSpHHRHCpLd=U  PHCX    CD  Lc LKI$   L9      LMILMHHCX   HA  L   Hr A   01ӡHCHHKHHSXfHnHC    fHnHPflHCXHSHCp   L`fKH Lɿ   H( 01g[    AELI)Lc     1ACLH)HK UHHdH%(   HE1HEdH+%(   uH   xS[ UH(HHdH%(   HEHH9tH@HUdH+%(   ufD  1[    UHHdH%(   HEHG(HwhH   fHnHG8fHnHGHflfHnflW(flO8GHfoQu GHEdH+%(   uZ    UHAWAVAUATSH(LHdH%(   HEHGHHEL9	  HWXIHtyH
HBfHnflHAHLoX    tEGpt>I](H@HMtXff.     H;HtGI)D$ 
H0L9uLM|$HfInL9}tyM/fD  IWflIUL*AA$    t1I_(M      H;HtWI)T$ H0I9uLMIU fInL9mtIfHEdH+%(   uH([A\A]A^A_]Yfff.     UHAUATSHHLohdL$%(   LeE1\H{HH    Hǃ       HH)   LHHEdH+%(   uHLH1[A\A]]Xf     UHAWIH5f AVAUATSH8H}HHUdH%(   HE1HE    HE    FH   I]     H]H5j H}Ht)H߾	   k
   1HHMH]AH53 H@HuSLHuH}
   &HuL\H}1HUdH+%(   uSH8[A\A]A^A_]    H߾	   1
   HH)AHEHH9HE 뒸6WfD  UHHdH%(   HE1H4K wHv HHUdH+%(   uVfD  UHSH(dH%(   HE1Ht_HWHHHzHUǋHHt!HUHxHsHEH@HMHEdH+%(   u+H]HfD     vHHtH@?V@ ff.     UHHdH%(   HE1HEdH+%(   u0Uff.     UHHdH%(   HE1Ht W JO9t
BvHEdH+%(   uHU    UHH dH%(   HE1Ht*WI     J9rAH9tuHEdH+%(   uwD  uA@u&IxLEwHEdH+%(   uHH}.L. uHE       H=? LEHsLE.    Tff.     UHHdH%(   HE1GHUdH+%(   u{Tff.     UHHdH%(   HE1G HEdH+%(   u;Tff.     UHHdH%(   HEGHUdH+%(   uS ff.     UHHdH%(   HEGHUdH+%(   uS ff.     UHHdH%(   HEHUdH+%(   uS@ ff.     UHAUATSH   H$ H   H$ HH  fom t   dL$%(   LeIfHǅ    )yH   Hs 1   HH!   HH@~   HHH9tHAD$Hǅ    ID$L      L A   H1蒟IT$It$I|$H HOHEdH+%(   uHH!  [A\A]]ÉQ    UHATSHdH%(   HE1tnA       HHtTfAn@   HD`fpf CC H{t*HEdH+%(   u%HH[A\]    1@ H IQf     UHHdH%(   HE1GHUdH+%(   uQff.     UHAUATSHdH%(   HE1H   I       HIHtz@   LL!LC[LCLC JI|$CHt莟HCHtHEdH+%(   uHL[A\A]]H KE16PfD  UHHdH%(   HE1GHEdH+%(   uOff.     UHAWAVATSH   H$ H dH%(   HE1HtHIHHt	u*HEdH+%(      H   [A\A^A_]    H   H~HtHoIHt1H=ۭ 1AǅxXI|$11Aąxk   ?xLsD;DcY L DxyDpy9 HEdH+%(   u.H   L[A\A^A_]fLD0yNfD  UHSHdH%(   HE1HtTH?tJ{tDH{ t=   ~H{HtuLH{蓃;xx{yHEdH+%(   u_H]fD  xCf:' uH7 AN  H H7C '       H81bLqM     UHATSH dL$%(   LeIHHuś1LWH}I诿HEdH+%(   uH L[A\]?M@ ff.     UHAUATIHSH(dL,%(   LmIHuPLLEH}A9HEdH+%(   uH(D[A\A]]L    UHu HH dH%(   HE1HUHuE H}	EHUdH+%(   ulLf.     f.     f.     f.     @ UHHdH<%(   H}H=% 蛴      HJc H% NH% HEdH+%(   uKUHAWAVAUATSH8dH%(   HEȋt+HEdH+%(   	  H8[A\A]A^A_]f     HH5FH=$ wH=$ t7HEdH+%(     H8H=$ [A\A]A^A_]jf.     Lc%$ H$ HKHMDeHEMnIfD  MH}IKL+Iu&t2~IL{Iu3fD  M$Mf.     MtEAU D  J9rAM 9   uL4$ EH"$ HEHEUH)ÃH9~yHcHHDHʍC# S9~ZH   f     ff.     ff.     ff.     H=y# HW8H4
Ht
w@HVu9|؉# fD  >Lr# EH`# HE9If.     UHAWAVAUATSH(H}dH%(   H]Hc'# H   L=#     IH}IO$It$xt$~HHtiO|fMt[LfD  LMt!A$fJA$9t
BvHEdH+%(   uH(H[A\A]A^A_]fD  1H    UHAWAVAUATSH(dH%(   H]HH=" |HIHtSH=! A$JA$9t
BvHEdH+%(   Y  H(L[A\A]A^A_]f! 9!    H6Hx轉HEH      HxH>x! L-! AǉEEA   E1f     E~DuE9-DHD)F4"IcI| HyEfE9~DeD+eIcHLcuJ    I|It ,LeH  H=    N$ZD  H=     HcPHt  H  1H=e  FfD  UHAVIAUI0   ATSHdL$%(   LeA{H   D` H5IHH= LprH= mLH= IXMt&L#HEdH+%(   u@HH[A\A]A^]@ LpHtHfD  H8     1E    UHAWAVIAUATISHH(HuL?H5H= dL,%(   LmArH=! lHH= HWHtpMt,AfD  J9rA9tnuLoI$Mt$Eu!1HUdH+%(   uNH([A\A]A^A_]ÐAD$      H}WHH{@ uLDfff.     UHSHdH%(   H]HH?Ht(    J9r9t/uHEdH+%(   uHH]    uPDUHHdH%(   HEHHHUdH+%(   uDf.     f.     fD  UHHdH%(   HE1    HEdH+%(   u1C    UHSHH dH%(   HE1HtHHVH6ffCHUdH+%(   uH]eCD  UHHdH%(   HE1H= HEdH+%(   u(C     UHHdH%(   HE1Ht W JO9t
BvHEdH+%(   uHB    UHAVAUATSHH8HdL4%(   LuE1iLc(H{8H(I9MDTHEdH+%(   uHL[A\A]A^]UBD  UHAWL8AVAUIATSHLH(HUdL4%(   LuE1UvLc(HC(H}HEL9MDHtSHS(HBfHnE HC(MtMtH Lh1LHEdH+%(   uH([A\A]A^A_]ûAD  UHAUATSHHHdL,%(   LmE1hHSpH   HpH9HBLESHEdH+%(   uHL[A\A]]"AfUHAUATSH(dL$%(   LeIHFhID$pIT$pH9   HX1+D  ff.     ff.     HCH9t7HHX{  tI$   RHEdH+%(   uPH(H[A\A]]I$   HMRHMHtH{ uAD$A9D$HDI$   1R9@f     UHAWAVIAUAATSHHH(HudL<%(   L}E15tHCpLCpAHxI9ID{! uHHuLAŅuC!E1H   HEdH+%(   uTH(D[A\A]A^A_]ÐH}LLE^HHtHHHCpHHfHnEBHKpAJ?f.     U@      @   L  HATSHhGdH%(   H]HHE    PDO1H}0HUHuH}ovZYu9HUHE1HD Hu1NHUdH+%(   uHe[A\]@ >@ UHATL   SHdH%(   H]HLeH{pHpH9t5HNHLPHEdH+%(   uHH[A\]fD  1>    UHAVATSHdH%(   H]؋_$t#HEdH+%(   u^H[A\A^]    IH   	eI|$pID$pH9tH!NHtHėAD$$I$   Oy=f     UHAUATISHdL,%(   LmI<AL$   H! I1L;I<$LHcHHUdH+%(   uH[A\A]]<     UHHdH%(   HE1HEdH+%(   u	H?<     UHAUATISHH8dL,%(   LmÀ~! t*HHU;H  HU1HL]Lu9CAD$CA9D$twH3I<$;   Eu.1ff.     HUdH+%(      He[A\A]]fHEdH+%(      H3I<$He[A\A]]Gq    H f1)E: tI<$HUH5H}rEzf.     Hހ HAL$HѦ    0CPDK1ED$ހX1Z5+F;fD  UHAWAVL}LuAUI   ATISHdH%(   H]HEu-HLLH{ u@IM9t7A7f     HLLbH{ uIM9t
A7@ HEdH+%(   uH[A\A]A^A_]:D  UHHHdH<%(   H}Hv;wtAt$HUdH+%(   uBɉHzf.     HEdH+%(   u1D  HEdH+%(   u9 ff.     UHAWAVAUIATSHHxHxHp  HpDldL4%(   LuMH   E1H}H9AIHMHAwHx薿H   H}L M   A     F   HEx4 t_MtAg  AH}ȌHLLLclHpL^HUdH+%(   uMHx[A\A]A^A_]fD  HXH+    HIp  @ H}W8ff.     UHAWAVAUATSHdL$%(   LeL   M   I$IL9t<L3@ ff.     H{7HHCHLHBHNM6I9uI|$M|$L9t"H@ HGHCH L9HHuA$h  1ۅt*    HkXI$`  HH跅A;$h  rI$`   mI   ĳIǅ       HEdH+%(   uH[A\A]A^A_]f7fD  UHAWAVAUATSHdL$%(   LeI6{I<$HtI$    I|$8Mt$(QkI|$(HL9t9H
    HHWfHnflHSHHHHL9uI|$8I\$pI$   jIT$pHH9tCHzHLz	D  LzHOfHnflHJHGIGIWLH9uI$   I$   1I$   IǄ$       I|$8I$   խL荟H Ht
I$   HEdH+%(   uHL[A\A]A^A_]5fff.     UHAWA   AVATSH@dL4%(   LuAjH'  fAnfAnH@fb(L @1f   HC(H{8fHnHCpƃ    flIC(fHnflCp覝H   蚝H}E1LO            H}2H}11ŔHHtmHHHCpfInDfHnHHflBHKpC   輚Hǃ       H   ǃ       HEdH+%(   u%H@H[A\A^A_]ÐHx     1W4    UHHdH%(   HE1Ht!W J9rO9tuHEdH+%(   u!fD  uHEdH+%(   u3f.     UHSHH(dH<%(   H}Hs9st8t3\IHtH8HEkH}HoDHf.     K?HHHUdH+%(   uH]H3     UHAVAUIATSHPdL$%(   LeI   E    HE    Hufu{HH_  EuE;utHDDHHH   I} HUH5臘UEf   H  H   H      1>   lMt   A$HEdH+%(      HP[A\A]A^]fD  HUHHEH}UCEUfA   fA   MtA$f     EL H}1         1H}1oÅ<HU1W߉U<\UfEt     H?(H{1f.     UHHdH%(   HE1HEdH+%(   uH<1ff.     UHHdH%(   HE1H9HUdH+%(   u0f     UHATSHdH%(   H]HL  f.     H1HH5=諨H{8HxHC    L9uHEdH+%(   u	H[A\]q0UHAUL  ATE1SHdH%(   H]H_8@ HWH{HHxIpBL9uHEdH+%(   uHL[A\A]]/f     UHAWAVAUATASAHMkxHdL,%(   LmANt'8L WJ|#pEAHt
D;o   HE    HUIcJ<#}   LALeMt/MkxLcJ|;p>@LLJD;piLeHEdH+%(   u@HL[A\A]A^A_]@ HEHupD  H}HEq.UHAWAAVAUATISӃLkxH(HMNl78LdH%(   HE1 HE    bDWUHEHtUK<&E1E11HHcH}ug
HEIHE MtHkxI|p&?LIDpLQHEHUdH+%(   uOH([A\A]A^A_]    >HUHcK<&HE    rL}tL{HEIs-f.     UH  HAWAVAUATSH(dL4%(   LuLw8HE@ ff.     LI^E1aI~8H>1IF8IFHtG@ IVN<Mt- L1HMH0HMmH}=MuIFII9rLIx!L9uwHEdH+%(   uH([A\A]A^A_],@ UHATSHdH%(   H]HHL  rHfHRH{8Hx;I9uHEdH+%(   u	H[A\]Y,f     UHAWAVAUIATSHDvdL<%(   L}IAMkxNd78LO`K|5pL9uHuHIcw1HMK|5 AH}<LHEdH+%(   u'H[A\A]A^A_]D  <1\KD5p+UH  HAWAVAULo8ATISH(dH%(   H]HHELRIEHE    HtoIUHML4MuQD  MvMt?I~HAAǅtLf=HEdH+%(   uAH(D[A\A]A^A_]D  IEHEH9ErLIx%=L9mbE1*UHHdH%(   HE1.HUdH+%(   u*D  U1HAWAVAUATSHH  dH%(   HE1Hǅ    Hǅ    HHd  Lp1E1M  HHHHfI~
   1f  LA   1H%    L|HL1HRAŅ  AHDH   HAE1H
   1J< H%HރLHLI^D9uHDxHCL[mIHH賸HHHt    HHHEdH+%(   uSHHH  [A\A]A^A_]1fHH<H]A9H諤H]ke(D  U    1HAWAVAUATSHH  dH%(   HE1Hǅ    HIH  H=x W2HIH  G    H        HHfff.     LرH?  H
   HxjH: uA     ALӧ   H1tH1HH(PAŅ  HGD9)@      9~sH   HMcE1fff.     H
   1J<H襒HwDI-JM9uIE1HLI[M9uH輢HLDh虰HLZLHEdH+%(   uxHH  L[A\A]A^A_]D  Hqɀ D   H 01kT1fHH<H\[A9HH?[j% jff.     UAH       HAVAUHE1ATSH   dH%(   HE1Hǅ    -H1HH1N   1AMcIHt>1H
   1H<HLHuHI9uEuAE    I1 ff.     HHH-ZL9uHHEdH+%(   uH   L[A\A]A^]$D  U   HSH(dH%(   H]1HtH1HEGH: HEHHUdH+%(   uH]+$ff.     UHHdH%(   HE1tHEdH+%(   u k HEdH+%(   uɉk#ff.     UHAWAVAUATSHdH%(   HE1HE    H   1IH   HXE1HuNsf.     EnH}DHtKHDDHEFHEHDhygHHt*EH{
   1ގIčvH}WXL诲L}MtA   L}HEdH+%(   u&HL[A\A]A^A_]f.     yI"UHHdH%(   HE1Hu8uHEdH+%(   u:HM@ HEdH+%(   u HEdH+%(   u." ff.     UH L% H HAWAVAUIATSHOdL4%(   LuI   LL1Lz LcAE~S1LL= 1,HHQ ALHLAH- L1   ' HIA9]H5    L1 HLHUdH+%(   uH[A\A]A^A_].! ff.     UHAVAUATSH dH%(   HE1G   I1H@ H}HĀ DH 101CfHEHHHIDA9\$   LGHE    AŃtjHEH    HH}18tH}HUHubHUHE H}蕨H}\d    H=@ 4oP    HEdH+%(   uH [A\A]A^]    UHAVAUATSHwdL,%(   LmI1IHtkIEE1AFI} tRf     DDLAH[HATBH[   I| HH؉HITI;]rA   HEdH+%(   uHL[A\A]A^]ff.     UHHdH%(   HEHcG~'HHfD  HH9t9wu    1HUdH+%(   uUHAVAUATSHdH%(   HE1I9G~bLcHAIJ|/SCDpE9}D)Jt+ J|+PHH$qDs1HUdH+%(   uH[A\A]A^]øf.     f.     fUH    HHH=ŀ dH%(   HMHH81{   UHHdH%(   HE1HtBHGG      HG@ HGG(   HGG8    HF(HtHVHH;8tHEdH+%(   u1D  WV4HHRHV@H   H H HFF0f     UHHdH%(   HEHHUdH+%(   u ff.     UHHdH%(   HEHG(Ht&HWHHt@,HUdH+%(   uD  1@ ff.     UHHdH%(   HEHG(Ht&HWHHt@0HUdH+%(   uD  1@ ff.     UHHdH%(   HEHGHUdH+%(   ufff.     UHHdH%(   HEHGHUdH+%(   ufff.     UHHdH%(   HEG8HUdH+%(   u^ ff.     UHHdH%(   HEH   HUdH+%(   uf.     UHHdH%(   HE1H>HEdH+%(   uff.     UHHdH%(   HEHF(Ht!HVHHtx,HEdH+%(   uH=f |ff.     UHHdH%(   HEHF(Ht!HVHHtx0HEdH+%(   uH=. !ff.     UHHdH%(   HE1H~HEdH+%(   uff.     UHHdH%(   HE1H~HEdH+%(   uff.     UHHdH%(   HEG|HUdH+%(   u^ ff.     UHHdH%(   HE1~|HEdH+%(   uff.     UHHdH%(   HEH   HUdH+%(   uf.     UHAWAVAUATSHH(H}HdL$%(   LeA\HII譲1L     ID臺Au0I  HUdH+%(      H([A\A]A^A_]fD  HEH}MDHJw    HE    Lp1       HLmyHA	D1L)LHUHHdH%(   HE1H   HEdH+%(   u     UHHdH%(   HEH   HUdH+%(   uZf.     UHHdH%(   HE1H   HEdH+%(   u     UHHdH%(   HE1HEdH+%(   uXff.     UHAWAVI@   AUATAHSHdL,%(   LmI蘗H   D`A|$LHHcxHCH   C    LHD8IL3C4   IE(Ht
IUH;tHC,   1MtL*.C$E<$HEdH+%(   uHH[A\A]A^A_]H= fUHATSHdH%(   H]1H   I1   蚖I$H   HxH     fHǀ       HH)   HHI$H@(    H@@    H@H    H@T    H@`    @@1HUdH+%(   u5H[A\]    #       fD       ff.     UHAVAUATISHH0H   dL,%(   LmE12H   H0   ~HH   HxH     Hǀ       HH)   LHLH31HfH@(    H@@    H@H    H@T    H@`    @@1HUdH+%(   u8Hİ   [A\A]A^]        fD      fD  UHHdH%(   HE1HEdH+%(   up{ff.     UHH dH%(   HUHH(HtwHB HHH9JsHEdH+%(      @ HHHUH4    HMHUHB(HteHr HMfDD D0HJ D  Hֿ   HUǓHUHB(Htfo- H     BaH=~ UHAWAVAUIATSHHF(dH%(   H]HH   HSL$M   eHLD8IԔM,$AD$4   HC(Ht
HSL9$t	ID$,   1MtL)AD$$E>HC(HSHH@C4HH@HC@H   HHHS C0HEdH+%(   uRH[A\A]A^A_]HHSHC( @  H{L$H[/I$HC(HɷHSL$H     UHAWAVAUATSHhDbHdH%(   H]HH   H   EusD[LCH   E8  H{ ?  H{ M  HC(HS  HSHHH?  RS4HHRHS@H   H H HCC0H)KH@(=  }  =  0  q  Hs@S0EIHMLl L= Le Lw} HL% L5 H]MՈARLHcA4@H=ƛ <fA<G tAUhI]pHcA4I9tJff.     ff.     ff.     ADf~HcA<>HA@HcfA;IuIKHA4@HfkLIHAGuHcChLkpAGHuLH)H   S8AU S0AE  Lk@?tHcHc DE   LmC  H5a HcH>CL   A(    HKHS(HB0    HUdH+%(     Hh[A\A]A^A_]CL   H{ H紀 H HCH{ H> H HCHHSHC( @  H{L$HE,I$HSHC(HHCL   =K81H   <
tH9<
uHsHK(HHA,HsHK(HA0    K89H   HMPPHsHS(H   HR0PHSHC(HЋS8P0HEdH+%(        HhHH[A\A]A^A_]H   HߋPPHKHS(H   HʋR0PHSHC(HЋS8P0eQHIH2\I$  *H   HMPPHsHS(H   HR0PHSHC(HЋS8P0HEdH+%(     
   -H   PPHKHS(H   HʋR0PHSHC(HЋS8P0,   H   IڋPPHKHS(H   HʋR0PHSHC(HЋS8P0H[@AR0H   HߋPPHKHS(H   HʋR0PHSHC(HЋS8P0 PHIHZI$  EH   HL}LmPPHKHS(H   HʋR0PHSHC(HЋS8P0CL   OHI]HIrZLI$HSHC(L$jeA)D$0S81~H   <
  H9C0AE L{@L   C8    AC0  A L{@HuH}C0LoIHFI9r A} 
uHKHS(Hʃj,IM9uHC@L   C8   AWS0AG HC@H   PPHKHS(H   HʋR0PHSHC(HЋS8P0   CL/   [H   HߋPPHKHS(H   HʋR0PHSHC(HЋS8P05N      H   HߋPPHKHS(H   HʋR0PHSHC(HЋS8P0M    H   HߋPPHKHS(H   HʋR0PHSHC(HЋS8P0M    cH   HߋPPHKHS(H   HʋR0PHSHC(HЋS8P0RM    H   HߋPPHKHS(H   HʋR0PHSHC(HЋS8P0M    H   HߋPPHKHS(H   HʋR0PHSHC(HЋS8P0L    H   PPHKHS(H   HʋR0PHSHC(HЋS8P0   HuHH+   EC0HCHS(H4Hy8u/AHSC4HHHSHC(H@8   HCHS(HLQHc{4Hs@M,:LUL   LxI9  LmI|=H9  Di4L)HuE  H  LULxLUSLLk@HcL9mLULmUA@  H5 HcufA<w tshLSpApHAA;Uu2   HcHv HcApHE,AD9l  H p  @H   PPHKHS(H   HʋR0PHSHC(HЋS8P0}   ICL   H[@AR0=H   H]PPHKHS(H   HʋR0PHSHC(HЋS8P0HK   Hcs8H   $LULCs L[ L IZ@AR0H   HߋPPHKHS(H   HʋR0PHSHC(HЋS8P0IHIHxTI$  H   HߋPPHKHS(H   HʋR0PHSHC(HЋS8P0IHI:HRTI$
  JC0HuH}HFHC@C8   H   VS0F HC@H   PPHKHS(H   HʋR0PHSHC(HЋS8P0  C0HuH}HFHC@C8   H   VS0F HC@H   PPHKHS(H   HʋR0PHSHC(HЋS8P0  `H   HߋPPHKHS(H   HʋR0PHSHC(HЋS8P0:H     H   HߋPPHKHS(H   HʋR0PHSHC(HЋS8P0G 	   H   HߋPPHKHS(H   HʋR0PHSHC(HЋS8P0G 
   jH   HߋPPHKHS(H   HʋR0PHSHC(HЋS8P0YG    H   HߋPPHKHS(H   HʋR0PHSHC(HЋS8P0G    H   HߋPPHKHS(H   HʋR0PHSHC(HЋS8P0F    H   HߋPPHKHS(H   HʋR0PHSHC(HЋS8P0xF    >H   HߋPPHKHS(H   HʋR0PHSHC(HЋS8P0-F    H   HߋPPHKHS(H   HʋR0PHSHC(HЋS8P0E    H   HߋPPHKHS(H   HʋR0PHSHC(HЋS8P0E    ]H   PPHKHS(H   HʋR0PHSHC(HЋS8P0{   CL   )H   PPHKHS(H   HʋR0PHSHC(HЋS8P0=   H   IڋPPHKHS(H   HʋR0PHSHC(HЋS8P0L   HK@AE EC0HSHC(H<H7HVHBH9ssHcFH\AB4HHH9s#PHHIrIR(H<H7H9FrH)ËFHcAB4H7HщFIrIB(HH@HH9  IEHYA<
uIRIB(HЃh,M   QIZ@AR0ABL   yH   PPHKHS(H   HʋR0PHSHC(HЋS8P0  CL   |ILmH]ABL   LLUwCH}.LUHIJIR(LUHHU>YHULUL?l LT L )B0AJ81~I   <
  H9AB0LMj@M   AB8    AE AB0AE  AR0Mj@lLmC0AE LkpHcChH   PPHKHS(H   HʋR0PHSHC(HЋS8P0CL   H   PPHKHS(H   HʋR0PHSHC(HЋS8P0:   H   HMHߋPHMPHsHS(H   HR0PHSHC(HЋS8P0AHI 1E f}HIW1HHj  HME1H5_Q C&D<1wYHcH>*  H=\ LqZLIHt(HJ^HA?qD1L)LD*.  &H   HߋPPHKHS(H   HʋR0PHSHC(HЋS8P0 AHIHHVH{HpI$ILmH]I   LLUPPIJIR(I   HʋR0PIRIB(HAR8P0ABL   |@H}3LUHIJIR(LUHHUCVHULULDi LQ L )B0AJ81I   <
  H9H   HߋPPHKHS(H   HʋR0PHSHC(HЋS8P0?    H   HߋPPHKHS(H   HʋR0PHSHC(HЋS8P0|?    BH   HߋPPHKHS(H   HʋR0PHSHC(HЋS8P01?    H   HߋPPHKHS(H   HʋR0PHSHC(HЋS8P0>    H   HߋPPHKHS(H   HʋR0PHSHC(HЋS8P0>    aH   HߋPPHKHS(H   HʋR0PHSHC(HЋS8P0P>    H   HߋPPHKHS(H   HʋR0PHSHC(HЋS8P0>    H   HߋPPHKHS(H   HʋR0PHSHC(HЋS8P0=    H   HߋPPHKHS(H   HʋR0PHSHC(HЋS8P0o=    5H   HߋPPHKHS(H   HʋR0PHSHC(HЋS8P0$=    H   HߋPPHKHS(H   HʋR0PHSHC(HЋS8P0<    HKHS(HHʃj,S89CWACIEHEI9
IHcEIJIR(HHʃj,AJ89@UIJIR(HHʃj,AJ890      CLCP    LS@P@uDnE  V  HEL)HH  f  D1HAoHuHH9uA   DHH<0EHxI2)Ѝpv-EHxHuMLEtmEHHBA9~RAGBA9~CAGBA9~4AGBA9~%AGBA9~AGA9~AGHS(HCHHy8  qD)   DHC@IIډjI}H)HÍ6FIAELHcMLUNLUMHIEt5IrIR(HcHIB@L,Au)ʃ!A} uIE    H=b D  LLAŸ    I$9OЅ  IcDmH1HEIHytHx%HxtLb LAK L}   
  LQHy(J<HB/I9uDmHˉS4HKHC(HȉP  } J  MIL9UEfAE EAE	  E  EE    EEn  EE  EE@  @EnES  EWEV  E@Ed  E)E    EE  EE  EE  EEuIE1LqH}LB Huu   1HR    }L}jE1LqH}L L}D       C4    H @    S41Ʌu$Eq  HSHC(   H@8   S4HsH{(AD H4LA;Bl  C4HHHR HC(HSHHcC4HRD HSHC(HHLRL   LU   HcEIAMLII]@I9   H]A   H5P~ HcfA<w tAMhMUpApHAA9uJafff.     ff.     ff.     HcH} HcApHAA9tHv p  @ACIL9UJH]HEHE      AHHcC4HBIHEHEJIzxHLUHcE蠏LUxL^ L8G Ly IBHSHC(HHz   EBC4HsHS(DH4H=^ *1DmH}LHx1D1AHuHH9u@H=] H{H!S4   L	^ LF Lx |H=g] HcEHcSLLUM,Lk@M9   A   tH59| HcfA<w tShLSpApHA<A9t6H
u p  ~HcH{ HcApHA<A9uIICM9uHcfA<G tShLkpA@HcA4I9t Lt IRAPHcA<I9uAK  tuHuHu7H=\ HI]HX@IH΍SHcHEH~HHv(DmH4HF
HyDm]H   ULs\ LD LEw U8Hx     HcEHEIcHE)f.     Hx8        H{1,HSHC(   HKH}HHUHxvL[ L]D C4Lv GH{@L[ L2D Lv sS4H=N OE1LqH}LM LmW   oE1LqH}L|a LMR   O1LqH}L]M HEI   01LqH}L HEG   Lq1H}LF HMk   E1LqH}X   LEL7M E1LqH}LpC LUb   1LqH}LR HEH   1LqH}LL HUh   t1LqH}LL HES   UE1LqH}Lj L]e   51LqH}LgL HEP   fD  UIHH0H~(dH%(   HUHH4  HB HJHpH9   H    HL9   Ht<HB@J0HJHB(HHJ@HHHJHB(HȋJ4HHz(HBHLHB(HJHH@B4HH@HB@H   H	H	HJ BP   B0HEdH+%(      fHHHUH4    LEHMӉHUHB(H   Hr fHMLEDD D0Hz(HJ HuTM8    Hֿ   LEHU[lHULEHHB(t*H     fo Hz(BHtHJ H=yW @ UHSH8dH%(   HE1H   H|>    |>    H}Hֿ@   HHMHUkLEHMHtqfInfHnHflL@fnHuH@     @(   H@4     fpf@HE[HEHUdH+%(   uH]f17H=W +ff.     UHAVAUATISHcHDkMcHLdL4%(   LuIjHX  Hǅ   Kڃ  L)HH    1HAoHH9u؃9   )rvI4H4t{HcAP9~dHcAP9~RHcAP9~@HcAP9~.HcAP9~Hc҃A9~
HA1LLfY>Hta@    HUdH+%(   uFH[A\A]A^]Ð1 ff.     AHH9u11H=5V xsH=6H g    UHSH(dH%(   H]HH}jBH}HUdH+%(   uHH]X UHH0dH%(   HE1H   HH~(HHY  HF LFLHJ4    M9   H7H<7 t[HB@r0@0HrHB(HHr@HpHrHB(Hr4pHrHz(H    HtHH8 tHFHBHHHB(HJHH@B4HH@HB@H   H	H	HJ BP   B0HEdH+%(      L@HUJ4    HMLEHUHB(H   Hr LEfHMDD D0HBLB H4    Hz(HH9f.        HMHungHUHMHHB(tfo% H     1BAH=R 5D  UHHdH%(   HE1HEdH+%(   u0bff.     UHH dH%(   HU1HtpHV(HHtHNHH;:t'P u.HUdH+%(   uRH{     H    P tHxHEHu{HEHu    HEdH+%(   uJf.     UHH dH%(   HUHW(H   HOHH<HtuHHEnHEHP(HHH    HPHtHHPHH(Ht;HH
Ht/IH4H
HIHH@H   HHHP@P   P0HEdH+%(   u@ ff.     UHSHdH%(   H]HH(Hu:   D  HHHSHC(HH    H{(H   HCHHuHzHC(    H{`HzHC`    HfHC(    HHC@    HCH    HCT    CCyHEdH+%(   uH]1Ð1    UHAVSH dH%(   HE1&wfH7s HcH>D  HEdH+%(     H>H [A^]U_D  HEdH+%(     H>H [A^]MD  HEdH+%(   _  H [A^]@ HH8IHH9tGH@ HOfHnHHEflHHHHEHHH I9uff.     HEdH+%(     H L[A^]^D  HEdH+%(     H>H [A^]D  HH8IHH9tHff.     HOfHnHHEflHHHHEHHH I9uVfD  HH8IHH9;H     HOfHnHHEflHHH
HEHHH I9ufD  HH8IHH9H     HOfHnHHEflHHHM
HEHHH I9ufD  HH8IHH9{H     HOfHnHHEflHHH	HEHHH I9u6fD  HH8IHH9H     HOfHnHHEflHHH	HEHHH I9ufD  HH8IHH9H     HOfHnHHEflHHH-	HEHHH I9uvfD  H>Hu\HuHEdH+%(   G  H~@ HH8IHH9+H     HOfHnHHEflHHHHEHHH I9ufD  HH8IHH9H     HOfHnHHEflHHH=HEHHH I9ufD  HH8IHH9kH     HOfHnHHEflHHHHEHHH I9u&fD  HH8IHH9H     HOfHnHHEflHHH}HEHHH I9ufD  HH8IHH9H     HOfHnHHEflHHHHEHHH I9uffD  HH8IHH9KH     HOfHnHHEflHHHHEHHH I9uUHH dL%(   LELFMtM; tHEdH+%(   uC     H}H== LEL,HUHMdH+%(   urH}1H'fUHAWAVAUATSH   H$ H
  fon E1HxHL HpdH%(   HE1H HLIHHHǅ   ǅ    ǅHǅ   ))HHE7HI98  HH'  J  H'  H9HNIHHI|H  HMMd$I)HHI_HSHHLHHLIHHIILSLHHHL@HLIIK< wSHH;HItHqWHLHIMlHHHI9e  LI\LHA j  McHo B   
              A_b  HHam <   HPn B      
  DP  =  <        _  HcHl < K  ǅ    H"m D4DE}  foǅAEfoHI  fD  HcH5n <9A_
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fnhfn`HfnXLPI  IE LLHf~PHhf~Xf~`IVHhfInfn`fnXfHnIFfnPflLHHIEI} Hy  HPfHnHxfHnflH:MuMuLP1f~Xf~`Lf~hKfnhfn`fnXLPAU AuHKIHLPf~Xf~`f~hIfnhfn`fnXLP(I0I@ IM Au1IHLCLPf~Xf~`f~htfnhfn`fnXLPI} A   LPf~Xf~`f~hfnhfn`HLPHIfnX
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HsLH}I}ef.     f.     UHHdH%(   HE1t^H5b ff.     ff.     HHHH)HȄuHUdH+%(   uD  1跺    UHHdH%(   HE1HUdH+%(   uuD  UHATSH dH%(   H]HHHuyHuHIH81҅umJ<#   t]La HE11@u0	@BHJtRHEu<_uAHHA   @ A	Du1HEdH+%(   u+H [A\]f.        @tH)H腹D  UHAWAVAUATSHdH%(   HE1H   I   H5p I7I\$LH5Y    IEMe7,   MEL:AH   LIH   HUH5[ HJIHtgfLLHHIg7utLPЀ	wD  CHPЀ	v<_HUH5[ 1HIHuL4; HUdH+%(   uCH[A\A]A^A_]Lg41HEdH+%(   uHLH[A\A]A^A_]fD  UHATSHHH?dL$%(   LeIHvLtHEdH+%(   u3H1[A\]@ HEdH+%(   uH{HCHL[A\]臷    U1HAWAVAULhATISH8  dL4%(   LuA։PHHǅX    Hf     HXH`  L`AWI_LH`AWH)HXAG   <t(   IHP  HIGH)  ID$@IL$8M|$@fHnfHnflAL8E^1H1ǅF  H5 耮HH  Hbu/HH'HLHAG"HfHP1HY+%   = @     AGP1`  L   
H~qL`MyL1f.     PHEdH+%(   u@H8  [A\A]A^A_]D  AGf     17Off.     UHHdH%(   HE1fw HHGHEdH+%(   uĴ@ UHAVI1AUI   ATSHdL$%(   LeIHHHtYH5    LLVA$E1   HHq0HEdH+%(   uHD[A\A]A^]AD  U   HAUATISHXdL,%(   LmIHH}{uGE1HMк   LH}E1L#EtOH}HEdH+%(   uLHXD[A\A]]ÐHV LH  1E101    LHcUH9AN ff.     UHHdH%(   HU1HUdH+%(   uHHHH3  HV     UHHdH%(   HE1H t&HEdH+%(   u(HH=3      HEdH+%(   u蒲fUHHdH%(   HE1 tHV H   HEdH+%(   uKff.     UHG8fHnHGpflHSHdH%(   H]HG8fHnwflGpHHHt51H55H=J*HCHHt1HUdH+%(   uH]ø譱fff.     UHATSHdL$%(   LeI   H   H= H HH   CC   S 1H5H=HC0HC8HC8HC@)H   HCHHCpfHnflCpID$IT$L   H   HHEdH+%(   uHH[A\]H,@ 1跰    UHHdH%(   HE1HUdH+%(   ux     UHSHH?dL%(   LUI1He  Hz     1HH  HDDH֍H   DHHHHDэHHփDHHHHDэHHփDHHHHDуH 1E1HD@LIHB?   HDHH!   A   H 0       II  IDDIJA   DHHMHDJIADHHMHDJIADHHMHDt`IDBW   DHH	D    HEdH+%(   u=H]H     H 0       zD  B   1!菮@ ff.     UHAUATSHdH%(   H]HH9tBII
fHL9t0H{L|BuHEdH+%(   uHH[A\A]] 1@ ff.     UH8HHdH%(   HE1,1HtHxHu,ff.     HEdH+%(     H     HU     1HA   H  HDDHƍJ   DHHHHDJHƃDHHHHDJHƃDHHHHDH 1LHJH	ƃ?AHHH!.   H 0       II  IDDIJA   DHHMHDJIADHHMHDt`ucJLHJH	HHH!tf.        1l@ H 0       D  tLHJH	fD  ff.     UIHHdL%(   LMIфuI11f     HHsIHBs   HI	HHH@uHEdH+%(   uO11A   !     HHI#ILHH@tHHsILVLsHI2fUHAUATLg8SHdH%(   H]H_8L9t%IHL9tH{L,?u   1HUdH+%(   uH[A\A]]迪@ ff.     UHHdH%(   HE1GHUdH+%(   u{ff.     UHHdH%(   HE1    uHUdH+%(   uf     + ff.     UHAVAUATSH o_dL$%(   LeIfH~)EfI~̈́tpHtLH >   MtLL=   H5	 L=HEdH+%(      H [A\A]A^]f.      t*LmI} HtLuAIHEL9tfHtLH`=tMtLLL=vf   jUHAWAVAUATSH8o_dL$%(   LeIfH~)EfI~̈́tnHtLH<5  MtLL<  H5 L<HEdH+%(      H8[A\A]A^A_]fD      HML)MtdL   H5C HM&H53 LMt$IEҺ   LD&LME迣LHE賣HUHMH9tNHHEH9K HtLH;t;M)LL;fD  LLHM&HMu   RfUHSH(WdH%(   HE1uL u& u Gw@@ ff.     HEdH+%(   uwH]f     1@    t΃tHH5 UH:   tH5+s H:   tH5 H:zuD  UHHdH%(   HE1Ht HUdH+%(   uD     $@ UHAUATLgpSHdH%(   HEHGpI9tMIHX@ HCHXI9t3H;L:uHEdH+%(   uHH[A\A]]    1蟥@ ff.     UHAWIAVIAULcATSH   dH%(   HE1"   HW8L_8   I9u   @ ff.     HL9  fz wG!HJHtDJ   A   1HH  HDADIʍpA   DHHMHD΍pIADHHMHD΍pIADHHMHD΃H ILHJ4MIIHHL	H4ύH?   HHH#B     H A0       II  IDADIDAA   ADIIMIDDAIAADIIMIDDAIAADIIMID  HHH	HHH4HHH#BHHML9UG"! tJ   HL!HXu@HEdH+%(      He[A\A]A^A_]fD  H A0       !@ HXd   H`@   LHAMHm[ H IEHL`1HHF 0AV1LH6XZW    A*A   1j莢 ff.     UHAWAVL}AUATLeSH(odH%(   H]HH5 )EHLk   H5T HI LEI$HtEHߺ   H5+  LHCHDHwuCMt1HLAt-IM9u1HUdH+%(   uH([A\A]A^A_]@    蔡@ UHAVSHHdL4%(   LuIHt4HUdH+%(   u?HHLHH [1A^]f-fD  HEdH+%(   uH1[A^]UHAWAVATSH   H$ HdL$%(   LeIIIH   NHHu'1HUdH+%(   u`H  [A\A^A_]fD     MMLH)H1H  ,11H	Ct   QUHAVATSH   H$ H(dL$%(   LeII   HHHu$HEdH+%(      H(  [A\A^] IM$   HH)H?  1+H11SBǃtIt$8   HHx$A|7
tAD8 eAD7 YAD$8 IPUHAVATSH   H$ H8  dL$%(   LeII   HHHu)HEdH+%(      H8  [A\A^]     IM$   HH)HI 1*1H1KAÃtH-xJHP   HHuHx(O
Ht'ƄP IT$X1Hh3@ ƄO )f     UHAWAVAUATISH(HZdL,%(   LmIՀ{| t
{}   LKMt$M<$M6  MtLLLM:  LKMt$(M  MtLLLM  LKMt$ M  MtLLLM  AD$XCxI|$ t*I}A}   H(I|$I]?HC(I|$8Ht`IEHuHPX Åt*HEdH+%(   q  He؉[A\A]A^A_]fD  IEHM    Hk Hx81aI\$@HtZ1   M}HIH  H5    1H>   LAG`L}I\$HHtZ1   M}HKIH  H5s    ~1H>   LAGhaLMd$P1M1   Mu9HIHZ  H5	    1L*>AFpL    Lf.     H I|$I]yHC 5Mu HLHLH3I>HZ H3HT CxI>CyI] H9> HL   L5n H?	 0AV1LMPH{'LHCI]_M<$LKMt$(AXMMLHCI]M<$Mt$ LKM@ ff.     MLoHCI]fHy= HLH L    0AV1LMH{gLHCXI]ZH)= HLLu H4    0AV1LM@H{LHCYI]M<$^@ MLHCI]M<$q1   aUHSH   H$ HdH%(   HE1HtEH   H1HN 1%   H1;HUdH+%(   uH]ø͘fff.     UHAWAVAUIATISHH(dL4%(   LuILcMt(LLHEHHEIDHH9r%HEdH+%(   uQH(1[A\A]A^A_]D  HEdH+%(   u,H(HK<<M[L)A\LH A]1A^A_]-$     UHSH   H$ H(   Hy dH%(   HUHHHHH9x5HHD HHUdH+%(   uH]fD  1W    UHATSH   H$ H dH%(   HE1~" t$HEdH+%(      H   [A\]D  HH   H HBtH/   fHHsHH)H   )H5H H2IH`H訥tL\C    HL1HHBHFC"L UHAUATSHdH%(   HE1  t"HEdH+%(      H[A\A]]@ G IuI\$8Ml$8L9u    HL9tHLMDK fAvHEdH+%(   u+H8 I$H  1LC0H1[A\A]]RfUHATSHdL$%(   LeIH8xHt*HHLC HUdH+%(   uH[A\]øfff.     UHAWAVAUIATISHHxMDELMdH%(   HE1  L#k  L;L9  ID$8LeMHxEdfA|$0    L,t  }    HEA|$$   AD$$H) HcH>I   HpAD$   A|$2   It$I~Hh*Hh  ?A   III9sH}   dHpI~kff.     M$$L91HUdH+%(   [  Hx[A\A]A^A_]    Ax %  L;L9t0D  AW uIHtIt$U'm  M?L9uH>6  ~IT$H5    1`efD  It$HxIH;  H}HWfA~ wAF H( HcH>f     HEdH+%(   j  HMHxHL[LA\A]A^A_]m-D  IE@HpAD$ ;GMD$A8?HQ5 M0r  H]HH= Aw,1HHD  IE8HpIEHpI   HpID$IE tHE@H I	EAE    M$$L9fID$IEb tHE@H I	EAE     M$$L9D  It$MI   H}M$$L9D  It$MI   H}M$$L9jRD  It$MIU@H}M$$L9=%     It$MIU8H}ZM$$L9     It$MIUH}*M$$L9     E1w     HEdH+%(   
  HMHxHL[LA\A]A^A_]魻D  I~&H]HH= At$,1HHfD  AG0IwIL$H_ 11tH18 MLe1fHEHEMl$8HE)EL;x   LeLxMm M9   H IUH}H5$^ HE1yLeH]HIOM$1H    H#yHE    L茑H}HUIHtjAw(HL
IN1H}   H ME#x\Aw,HU1H}~yLeH}1JIHH{1 Hѿ   H 01H}J
uH= )HE ff.     UHAWIAVIAUAATISH(LEdH%(   H]H_(t!HEdH+%(   uMH(1[A\A]A^A_]ÐHEdH+%(   u,1HLMEH(LL[LA\A]A^A_]%PUHAWL8AVIAUATISHH_8dL,%(   LmIL9uVfD  HL9tHHLS HsLHKAՅtHUdH+%(   ujH[A\A]A^A_]f     1L=׬ A~ t"I41Hv$1LAՅuHHu1f.     LAՅuHif     UHSH   H$ HH&y    dH%(   HUHH胢tH裣HUdH+%(   uH]fD  UH5 HSH(dH%(   H]H    tH5 H߈U   uHEdH+%(   uH]@ H t@ UHSH   H$ HHdH%(   HMHH   蓡t/H賢tH5Ę H'f.     1HUdH+%(   uH]@ UHATISH   HXL`Lht#)p)M)U)])e)m)u)}dH%(   H81HEǅ    H(H@ǅ$0   H0HHtCLHH HAH8dH+%(   uH   D[A\]D  A UHSH   H$ HHdH%(   HMHH   u1HUdH+%(   uH]     H}fff.     UHAVAUATISHH   HHdL4%(   LuAH   E  {h   L1L  LH -L%Ht/H=q0 LL QHHQH9uLHu]LHtAH=&0 LLfff.     ff.     rH7tk HJH9uLH艕tE{h toH{HHLt(HHUdH+%(   uLH   [A\A]A^]f1@ HH9{LH uf.     H  чUHAWMAVAUIATSH8  EH1HHD dH%(   HE1Hǅ     Ht+1HEdH+%(     H8  [A\A]A^A_]fIM|  IG(Mw0HIG HIG8HAGXAGYMtLH5 %MD   HH1  ~ CXfC8 CxCy CzChIW@Htl1   HHHH  H5    H1(H   C`HTIWHHtl1   HxH HHL  H5D    OH1a(H   Ch+HMPHCXHMt`1   HHH  H5    L1'L   CpLLk -  H{ E1QL1LLLH&f.     HcD@IA
D  M9   EE EE*     uI   LDHDH{}H  fo@ID   DB8foPBD8fo`BD8 fopBD80foBD8@foBD8PfoBD8`foBD8pL1fD      HH~0DLLEEfff.     HcLLHJ:HLHpH J|Hg  HJ<8H@HCHH  HK H    H"HHHtHHHHCHHtHHHHCHHtHHHHCMtLIHLs0Ht9HHz  HH{8    1HPQ U  4  C|I}PH  L HLHML Hǅ0    H(uAEdA}   AEXH3I}HHME1   H H$HH{޶H{նH{̶H{0öH{ 躶H{(豶Hy@ HTH V  H |
D     HHC  AE`L     AE\L        εHH
  HCX~v CXfH1E1C8 fCxCz Hǅ    Hǅ    Ch    L A} .ƅ0HMLHHQKAEdALHLL1HS  HH 1H" 01);1   %HH{ݴH{ԴH{˴H{0´H{ 蹴H{(谴H߻s9f     UIAHHIII1dH<%(   H}HjIQ)HEdH+%(   u1~UHATSHdH%(   HE1H t?Hw0HHt3H:I$uHs0I|$tIt$H{ uHEdH+%(   u3He1[A\]fHHSHKIH3jALnXZ5~D  UHAWAVAUATLhS1H  HHdL,%(   LmAPHǅX    ff.     HG  H`PLxHH`PH)HXx.uA tA?.uA.uA t@ ff.     LIHvI|H5 vIt`K|7H5 WIvAK|7H5U `8I	t"K|7H5? Af     1LD1聋Ã   H11E1j HHALZYxY:HXHf.     P`  L1   fHH~nL`L    H L   H 01    Hi L   H] 01HX%D  HH@hHEdH+%(   uHe[A\A]A^A_]{fUHATSH   H$ H   dL$%(   LeIHHHu!HEdH+%(   ujH  [A\]fD  I$   HH H)1~   H1ÃtL賥됐AD$h{ UHATSHdH%(   H]H   H   H\  {h    Dc`DcX{i    H{PH  H蓲IĀ{   CdI)H   CLHUdH+%(      H[A\]D  HEdH+%(      HH[A\]%D  HEdH+%(      HH[A\]-D  C\HI:rmHI)c HDc`DcX{i @ HEdH+%(   u9HH[A\]{ KHHpIcy UHAWAVAUATSH   H$ HX  HI   HHdH%(   HE1LHHh LH  L  LZ  A|$h v  It$PH  A|$i   ID$HHH H  LE1HPN$MU  L   H{0H2  H tHx   ]Hǅ    HH{    HL   E1LL0HHǅ    CX{8 uf. zt;LK8         LD H   HLI| H)HC      L HHCH H1s DHC    LH HCH1HXDkzZ{{    C{E   L{ H5 LgH  HtLHC[  HE1L   HHA辯ES  0  DkzD(HHugMd$M#  HI\$H;ruH{0HHH8fHHL蚻HUdH+%(   *  He[A\A]A^A_]     H5y L1HL{(M+H5< LHH5< LHfD  H A   L12H κHbCzA    qHǅ    HH{ HH8x upI@ HH8IH{ H5S >H   3E      HL   L L01A[A^L0HLx tLHHL   LxK|= L)UfL0L1rHs LH  QHE   L      0L- L1&L0_AAXM9tuHLA    A uE   1MOIcD)      A  HcL HMHAwLY^AM?I9uEIHLDpDA    ƅ HLH@HHH II9L1A|$ M$      1HL&    H	I$fƅ( H)HH)) D  H8TCzAfD  HHLKD     HHHnI$   HHq H)12   H1Ã  LcfD  LA|$    AD$if     IcƄ/ACOHƄ @ H LC A11L2H ѶLi3E   HL    L   01[AYAZfA|$ \c    HHLB訽LHAD$hp     UHH dH%(   HE1Hu1HUHUHMH|WHUdH+%(   uapUfHAWIAVAUATSH  H HHLLdH%(   HE1 1H    fJ(BBJ  Hn6  H?  HHH9,  L0L+fInfl)D  Hh  C E  {2   HHsHx8觀H  HCHHH   IH+  LmIv L  H0HL9t@     @1H L9uL9t'HH8HZfoHHHH)0LЧH  K(A~| tkA~} udHL0HL!HI6H H8HI6H AFxHH8+AFyI? tA~8   ffA.GztffA.FX    A) tA~y   A~8 tIF8IAFXff.ztAGA~y tAG)I~(    1   LHIF(HH HHkHHܽd  HE1   LH膫HT  0uH8HfHnflA~x tAG(AN`HAOANhAOANpAO HHCHBHzqIE LL9t'IfHHLHs~I?   ffA.GzuHD IGE1HEdH+%(   3  H  D[A\A]A^A_]D  mH{H5 藪UHCHH@ LAxi ,IxPHHLqt;LA~ 聸HMLHmHpHH1IHI    AH I1MF H D01趰LNH= Bs(H1H.DfAH6    HEH D01PHDDH= f.     HHL誊I? H%? IH=L H1HhAH=h AiH=) jfUHATSHdH%(   HE1Ht}HI2tLubHuvHޡ   H>      LH&Ht   f.     {i    fD  1HUdH+%(      H[A\]fHEdH+%(      HLH[A\]vf.     HEdH+%(      HLH[A\]f.     HEdH+%(   u|HLH[A\]ޱfD  H{PHtOE11LHmC-fE11LHHmf     { u`hUHAWAVAUATSH   H$ H  dH%(   H]Hj t.ClHUdH+%(     Hĸ  [A\A]A^A_]fD  Cl    HH    H6~A    	 H1[
,  H1Hǅ    H f     HHX  LAUMeLHAUH)HAE   <t,1L1uAƃtH5t >_IH  H¾   H@H      IH   LIH   H@H@Hp_IGH   HCxHspIOLfHnHKxfHnflAGHClPk 1H0LH%   = @  tgAED  L 1`     LH~BLMzL;L LjC AE6fD  ,5Cjv@ Cj1j`DqeUHAUATSH   H$ HdH%(   HE1AIAHo HH   PDHD.HUdH+%(   uH  [A\A]]dff.     UHHH7dH%(   HM1yx%HUdH+%(   u)H5Jr \    HEdH+%(   u1xd     UHATISH   L`Lht#)p)M)U)])e)m)u)}dH%(   H81HEǅ     H(H@ǅ$0   H0BiHHtBLHH HAhH8dH+%(   uH   D[A\]@ Acff.     UHAWAVAUATSH(dH%(   HE1H  IkL  ~  Mf8Mn8M9tIfo} I$)UfD  ID$foEI|$HCHA$PLII9HuI~HH   HG H   E1HWN$Mti I\$H*  HH{H{H{ߗH{0֗H{ ͗H{(ėHMd$MuI~HHG II9rIFH    IFpMnpI9tYfo| HXH )]L`HSfoMHHPHKTH{KHLID$HSL`L9uI~0eLI~I~HEdH+%(   ubH(L[A\A]A^A_]衝I@ Md$MHEdH+%(   uH([A\A]A^A_]L?5aD  UHAWAVI   AUATSHH(  HdL<%(   L}AH   HھHI?  1MD$LH H T   HfH=} ǅ<    ,ǅ   ǅ(   ǅ8   m  HH= stWHH=i \B  AD$   LE1HEdH+%(   D  H(  L[A\A]A^A_]ø   HAD$H   H exA׉LY  ~s H^L HH@fHnfl)9foHǅ     AD$AHHLDDLL% )fD  H1L  E1E1IIL"fD  IcAIA
  M9   E.DE   A   uHI$   LDPWH  foHA   LB foBD foBD  foBD 0fo BD @foBD Pfo BD `fo0BD pI1	f   H譚H~ILE.DEIcMLN<*HIwL\VIH  HJ<(HYC> ɇMxLlLIQM  HHL MLLLD tHIT$0    H HHn  /AD$HID$LL1HSO Hr ǅLH` AD$$aHǅ     Hǅ    HH2  H H
   HrH  tH |
   H`H ID$L9LID$P茿IFI$   LIVM$   I$   HAEI$H   1H11   HiÃtdLǅ2L"AD$ LLLD)D H_1AD$h1   LL>Z@ UHAWAVAUATSH   HHdH%(   HE1HL  h p  HHpPHu  H{i   HH@HHP H  Hǅ    HHHL<M   H R    HE1   HH0
HAߒEuHH98   MMtc1   H0MwHHMn |WHLtH AL   12H ˞HcMMuHH@HHP HH91fIHUdH+%(   u~H   [A\A]A^A_]@ HHpPHx H{i H{ uH@icaHHҐ{Xff.     UHHdH%(   HE1?uHGHUdH+%(   u-Xf.     f.     f.     f.     D  UHAUATSHH_HdL$%(   LeIH;_   HkXHIHI|$HtҦHH{I|$Ht輦HH{I|$Ht覦HH{I|$ Ht萦HH{ I|$(HtzHH{(I|$0HtdHH{0I|$8HtNHH{8I|$@Ht8HH{@I|$HHt"HH{HAD$XCP1IEHUdH+%(   u4H[A\A]]ÐHMD$HQ 1H 01/   V UHAVAULoATSHH G0dL$%(   LeIG0   H   H9   HHHIփ   LLH5ɹ 1	eA1{0   f.     1҅OEDIHEdH+%(      H D[A\A]A^]    LLH5$ 1dA1{0LH5$ H1d Lo,   HML{0HM	,   HpHM    LLH5 1,dA1{0-LLH5ָ Hd LLH5 HcTUHAUL- ATSHHu dL$%(   LeIL9thHX/f.     H{HtLtH   HXL9t3H;LuHEdH+%(   uqHH[A\A]]    Hᇀ L-ڇ L9tEHX,    H{HtLgtH   HXL9tH;LHuf1S    UHH dH%(   HE1H  H~  8t!)HUdH+%(   $  @ IHv8HH8Ht]HH/( HDLEHMHMLEuHIH   pHt.@:r   @z H5' Huf   @YIp@Hy@HtuHH' HDLEHM*HMLE!HEdH+%(   uIIpHyD  Htٸz fH9uf     H55' Hu}Rfff.     UHAWAVAUATSH  dH%(   HEȉ##, 9tk@   L% L-Ʌ 1H  L蘪t+   t+   u?H  L1^	+ HEdH+%(   q  HĘ  [A\A]A^A_] + uL߫D  WL% L-% Aǅ  PHǅX      1LhL% L-鄀 f     H`Hp  HHpHH`HH)HXx.u~ tĀ>.u~.u	~ t HHHH@HHHu=* tH@HHHHH@  HXH=2 g* EH1DxHX,@ Dz.M9m $LHHu H 101裕fD  HH H   L   H H   H
    LfPL`  1   薤HH2L`L[ 1LhL% L- H~hH`JHrHH`JH)HXz.u~ tȀ>.tcHHHtHH$HtWHXHP1`  L   ٣HxL`Lm~.u~ PfD  =( tHHHHt(H=1 f( uH1DwcfH=     H=遀 ON@ ff.     UHHdH%(   HE1Ht8 uCH   H HBH9ʺ    HDHUdH+%(   u>    nH= H   Hi H9tHfD  H= Mf.     UHATSHdH%(   H]H謧ILc~gGMcD1H8JL0D  ff.     ff.     fH	ƃt HGuA9tHcHA|_tLHUdH+%(   uH[A\]@tA)A~Lff.     UHAWAVAUATSHdH%(   HE1H   L'HE! DwHMLDLbHAE   H   L= L5! HXL9   H;HID%HA9uH3IcLHID   HEdH+%(      HH[A\A]A^A_]fD     L%  E1tH~ H   L=o L9tLHXL5k  H;HIDGA9uH3IcLHIDFkH   HXL9uH~ fH   HXL912PKUHAWAVAUIATSHdL$%(   LeIGILFLLI9HHIFI9u<u8Mt3LM~E1I9r>LHH9ø    rHL9HUdH+%(   uLH[A\A]A^A_]ÐK|=    1If.     1I<   I9s_J@ ff.     UH HHdH%(   HMHHrHHDHyHHDHEdH+%(   u2Ifff.     UHATSH Hz} dL$%(   LeL%f} L9tZfoc HxH )UHXf.     H   foEHPH   HH   H   HXL9uH| L%| L9t]foLc HxH )]HXfff.     H   foMHPH   HH   H   HXL9u"     HEdH+%(   u	H [A\]HUHAVATSH(dL$%(   LeIHHt"HEdH+%(   6  H(H[A\A^]Ð=U" tLOAƄ   9" uMH={ 1Lu@}HrHu   H5 L      H5Ы LtdH5« L-tyAhHEdH+%(   upH(L[A\A^]    +MH=4{ PD     LHH        f        TG@ UH5z HH Hz dH%(   HMH9tRH,fD  ff.     ff.     H   HBH9t ;HuHUdH+%(   R  fD  HYz LRz L9t=H'ff.     ff.     H   HBL9t;Huf     =U        wfMHy MH5y Ly H9}   H'ff.     ff.     H   HBH9tP;HufD        =  v   =  pfD  1f     HIy L9tH ff.     H   HBL9t;HuEUHHdH%(   HE1Ht8H   Hx H9tHHUdH+%(   u5     1@    Hx Hx H9tH EUHAVSH dH%(   HE1HtM    H   HUx HBH9ʺ    HDHUdH+%(      H [A^]f     HuHE11HUHuGxLM؄uwA      LLM舞HvHuغ   H= ADމH=Iw H   Hw H9tHXD  H=w )@ A      CfD  UHAUATSHdL$%(   LeIHtr    H   L-2w HXL9u   @ H   HXL9   LH!tHEdH+%(   	  HH[A\A]]@ LH5 M   HtoH=Cv H   L-v HXL9u:f.     H   HXL9t LH蕻to@ 1dH=u @ L   HHwH=g    LB   VHt$H=O    L,   "LBff.     UHAUATS1HdL,%(   LmIfff.     H8HHtpL#LL2t^   H5
 LuI|$L	t5   H5 LauI|$Luff.     HEdH+%(   uHH[A\A]]nA ff.     UHAWAVAUATSHxHhH}HudH%(   HEHHP AĄuH8 E1E1LxALIHuMcIkXvHEH  HEL}HE    D  HUAHL著LIHuH}HX   LEP  EAh  E    E1D|Du   @ IV@Iu@HHUHUtAIMNMIv8HAv0Av(Av AvHAFPPAvHEH}PLuH0II~RuH}H|DuH}H|6uH}H| (uH}H|(uH}H|0uH}H|8tH}H|@tH]H{HtEM9M}_HELN4 IXN, M~IuHt'MH=o IEIV@ LH5o Mu@ D|AIcLeL}HkXHEAHHLHL@Hp8JHP@p0p(p pHxPWLpAT$H}H0H|tH}H|tH}H|sH}H| sH}H|(sH}H|0sH}H|8sH}H|@sH}H|HHXsE94H}sHEdH+%(   u.He[A\A]A^A_]@ HA HҮ 101o=     UHAWAVAUATSHhH}HxdH%(   HEHHP HHUuH HE1m@ H5i H}1fLH5[ H}1TLHi 11KuE1j AVPj j HELEHxPH}H0HH}?HUHH   H fHE    E1)E)E)EHEHEH;8{ HH}AHέ H5 LED1KHDH}H5 1KHHuH}H5a H}1ZKD  HEdH+%(   uHe[A\A]A^A_]=<fff.     UHSHdH%(   H]H^8Ht)HUdH+%(   u1HH]H*f.     HEdH+%(   uH]1;@ UHHdH%(   HEu u)1f     [ §HǋM HuHUdH+%(   u^; ff.     UHS1HdH%(   HE1-6fD  s1H tHFHHu޸   	    1 HEdH+%(   uH]: ff.     UH= HHdH4%(   HuH5Ife HUdH+%(   uw:    UHHdH%(   HE1HEdH+%(   u1~9:f     UHSHdH%(   H]H?@@tIHtHUdH+%(   uTH]    u/HEdH+%(   u/H]FfD  Huu@ {xHu9ff.     UHH dH%(   HEH  HtHUdH+%(   u)f.     HHHUHUH  9 ff.     UHHdH%(   HE1HEdH+%(   uH   H=dl 8f.     UHHdH%(   HE1HEdH+%(   uHHHH=l {8ff.     UHHdH%(   HE1HEdH+%(   u	Hj 88f.     f.     f.     f.     f.     fD  UH    HHH= dH%(   HMHH81{6   UHHdH%(   HE1HtBHGG      HG@ HGG(   HGG8    HF(HtHVHH;8tHEdH+%(   u1D  WV4HHRHV@H   H H HFF07f     UHHdH%(   HEHHUdH+%(   u6 ff.     UHHdH%(   HEHG(Ht&HWHHt@,HUdH+%(   uD  16@ ff.     UHHdH%(   HEHG(Ht&HWHHt@0HUdH+%(   uD  16@ ff.     UHHdH%(   HEHGHUdH+%(   u5fff.     UHHdH%(   HEHGHUdH+%(   u5fff.     UHHdH%(   HEG8HUdH+%(   u^5 ff.     UHHdH%(   HEH   HUdH+%(   u5f.     UHHdH%(   HE1H>HEdH+%(   u4ff.     UHHdH%(   HEHF(Ht!HVHHtx,HEdH+%(   uH=f |4ff.     UHHdH%(   HEHF(Ht!HVHHtx0HEdH+%(   uH=. !4ff.     UHHdH%(   HE1H~HEdH+%(   u3ff.     UHHdH%(   HE1H~HEdH+%(   u3ff.     UHHdH%(   HEG|HUdH+%(   u^3 ff.     UHHdH%(   HE1~|HEdH+%(   u3ff.     UHHdH%(   HEH   HUdH+%(   u2f.     UHHdH%(   HE1H   HEdH+%(   u2     UHHdH%(   HE1HEdH+%(   u t[2ff.     UHAWAVI@   AUATAHSHdL,%(   LmIxH   D`A|$LHHcXHCH   C    LHD8IPL3C4   IE(Ht
IUH;tHC,   1MtL誥IC$E<$HEdH+%(   uHH[A\A]A^A_]H= WR1fUHATSHdH%(   H]1H   I1   zI$H   HxH     fHǀ       HH)   HHI$H@(    H@@    H@H    H@T    H@`    @@1HUdH+%(   u5H[A\]           fD      ^0 ff.     UHAVAUATISHH@H   dL,%(   LmE1^H   H@   ^HH   HxH     Hǀ       HH)   LHLH3{^HfH@(    H@@    H@H    H@T    H@`    @@1HUdH+%(   u8HĠ   [A\A]A^] {       fD  c    6/fD  UHHdH%(   HE1HEdH+%(   u'.ff.     UHH dH%(   HUHH(HtwHB HHH9JsHEdH+%(      @ HHHUH4    HMHUHB(HteHr HMfDD D0HJ D  Hֿ   HUHUHB(HtfoI H     Ba.H=v UHAWAVAUIATSHHF(dH%(   H]HH   HSL$M   HLD8ILM,$AD$4   HC(Ht
HSL9$t	ID$,   1MtL茡uEAD$$E>HC(HSHH@C4HH@HC@H   HHHS C0HEdH+%(   uRH[A\A]A^A_]HHSHC( @  H{L$HdI$HC(H]HSL$,     UIHH0H~(dH%(   HUHH4  HB HJHpH9   H    HL9   Ht<HB@J0HJHB(HHJ@HHHJHB(HȋJ4HHz(HBHLHB(HJHH@B4HH@HB@H   H	H	HJ BP   B0HEdH+%(      fHHHUH4    LEHM3HUHB(H   Hr fHMLEDD D0Hz(HJ HuTM8    Hֿ   LEHUHULEHHB(t*H     foE Hz(BHtHJ+H=i @ UHSH8dH%(   HE1H   H|>    |>    H}Hֿ@   HHMHULEHMHtqfInfHnHflL@fnHuH@     @(   H@4     fpf@HEkHEHUdH+%(   uH]f1'*H= ff.     UHAVAUATISHcHDkMcHLdL4%(   LuI5Hh  Hǅ   Kڃ#  L)HH  ,  1HD  ff.     AoHH9u؃9   )rvI4H4t{HcAP9~dHcAP9~RHcAP9~@HcAP9~.HcAP9~Hc҃A9~
HA1LLfy8Hta@    HUdH+%(   uFH[A\A]A^]Ð1 ff.     AHH9u11H= XS(H= G    UHSH(dH%(   H]HH}JH}HUdH+%(   uHH]X' UHH0dH%(   HE1H   HH~(HHY  HF LFLHJ4    M9   H7H<7 t[HB@r0@0HrHB(HHr@HpHrHB(Hr4pHrHz(H    HtHH8 tHFHBHHHB(HJHH@B4HH@HB@H   H	H	HJ BP   B0HEdH+%(      L@HUJ4    HMLECHUHB(H   Hr LEfHMDD D0HBLB H4    Hz(HH9f.        HMHu讼HUHMHHB(tfoA H     1B!&H=z D  UHHdH%(   HE1HEdH+%(   u%ff.     UHH dH%(   HU1HtpHV(HHtHNHH;:t'P u.HUdH+%(   uRHx2     H    P tHxHEHuQ2HEHu    HEdH+%(   u*%f.     UHH dH%(   HUHW(H   HOHH<HtuHHE>HEHP(HHH    HPHtHHPHH(Ht;HH
Ht/IH4H
HIHH@H   HHHP@P   P0HEdH+%(   u_$@ ff.     UHSHdH%(   H]HH(Hu:   D  HHuHSHC(HH    轼H{(H   HCHHuH0HC(    H{`H0HC`    HfHC(    HHC@    HCH    HCT    CC0HEdH+%(   uH]1Ð1g#    UHHdH%(   HE1HEdH+%(   uɸ   *#f.     UHAWAVAUATSHXdL$%(   LeIH   ~H^  ML$@AD$0LMHS L LL-B L L=\ MEL$LHIIcsfff.     HF fA<r tENhI~pHATE A9tJfff.     ff.     ff.     Asf~HcAHsHfA;TE uH5 HH4FsIfhH}ArMMuIApHEIcAhABH}M   LuHL)MAQ8AQ0H Iy@

  H=׷ HcH>AD$H   At$Lu	AD$L   I|$ 2  I|$ A  ID$(HtFIT$HHHt5RAT$4HLJML$@M$   H H ID$AAD$0*LIT$ID$( @  I|$HLXHIT$ID$(HHHUAF0MH1HUdH+%(   D  HX[A\A]A^A_]MH}LuAA0IApHEIcAhABL貓LIIo
   1L     HH¸  qI  d  Z,   PINIcv8   MI   >L L ID$@HEAD$0HMH}HI+   EAF0IF(IVH<L'AD$8u5AD$IVAF4HHIVIF(H@8   IVIF(H<L'It$IcN4IF@I   LLEI9d  HLH9	  EL$4H)Ej  H  HUMLHIA@IcQLIL- H9+  A$3  H= HcfA<r tAQhMapsHEtE A9uN  f     ff.     ff.     HcH HcsHEtE D9u  Ap@ָ-   :   ~Hs H ID$I|$ H H ID$ID$(HAFP    LUL L   AFLI   HIV@
H  D@A  HH)HH  AF  A1AIo:>HI9u   AAD)DD@H}L$>HAvLEJJtyAIHA$AA9~^GAD$AA9~MGAD$AA9~<GAD$AA9~+GAD$AA9~GAD$AA9~	GAD$IVIF(H<L'A|$8a  At$)ʃ   MIF@MkI|$H)Iƍ6FIAD$LHcLE谺LEHID$t;IP(IHMcL}I@@L$At$)!A|$ uID$    H=Ј  MƸ    At$$9OЅ   MUѵ     IHcEHEHcEHEE> I~GL@ L   A<$[  A$    I~XIVIF(   INH}HHUHxL La AF4tMvHcUME1H}IMIxLEJLEL L v  
A  MHIx(AJ<HB7ID9euUMMAV4IvIF(HPAV4E1u%n  IVIF(A   H@8   AV4I~Iv(H4LA;@  AF4HHHR IF(IVHIcF4HRD IVIF(HHHRI   AHUMA  HcEENLHHEIF@H9   IL A$   H=h IcfA<r tENhMfpsHATE D9ubp ff.     ff.     ff.     ff.     ff.     HcHް HcsHELE D9tAp@H= IGAL9e2LeH}=H= IGHcL;eARLuLe            IxMDLLEIcDMLEDML& ML I@IVIF(HHz   AABAF4IV(INH4AF4    H@    I~LMA   wAV4ML L" HIcF4H}HBHEMAV4HMARH}1DDHH9uIpI@(AT$McH}MMHHxB'
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uHX1H0DHu͋H%   =    uHXHHHH   % 	=   uHH0	H HcpH8~#HcHH     9XHH9uH 9p   H FB,ty,HH     ,E7L=A1HUdH+%(      H  [A\A]A^A_]fD  ,uL@HHZp    1H|(1   Hj,9   HcHH Ht@HcpH8H8HcpD`6UHAWAVAUIATASH8dL4%(   LuIHE    3HH/  HEHEA    HEuuD  HxIH   xuIWH DPtHE    #'LEIOLLLeLetA}f.     HIHt`Au$IWH DPtH&LEIOLLLeDLeuH贔IHuff.     E1L襆H>HEdH+%(   uH8D[A\A]A^A_]E1B
fUHAWAVAUATS1Hh  H1҉|dH%(   HE1+  H@ƅ E1HHIL Hǅ      E1E1fIcAA
   LI9  D(LxDE   A   uHI$   DDHv  foHA   B foBD foBD  foBD 0fo BD @foBD Pfo BD `fo0BD p1I쀈A
ƅ MIcHMt HIvwIH  J<(HLLqC4 M  HwbHLHHކ  HA<:  _HIHID    ff.     ff.     HH@HQuC|4
r  H
   Hǅ    W LHMQ  IIu HFt>IFf     ff.     ff.     HHIHHNu勅|   uRA>HuA~z5  H5Ck LR	  H50k L;?  Hi@B ff.     L]1HEdH+%(     Hh  H[A\A]A^A_]D  L  LCH   I\ L   wCD4 M1\TH52j Let,H5#j LRw  H!Hi  H
A~ @ ƅM#E1E1HfD  IcAA
   I9   E'IDE   A   uHI   HPH  foHA   HB(foBD(foBD( foBD(0fo BD(@foBD(Pfo BD(`fo0BD(pI1HӈH LHh 101JH̧ LHh 101ILMMLE1芀1Hǅ     HcЃDA
   L9   Eu IEE   =   uI$   HHHH  foH1B foBD foBD  foBD 0fo BD @foBD Pfo BD `fo0BD pL   HcHM<HIw-IHt`HHJ< .{C> MHHL誁HA<:{MMHE11~f.     UHSHHKdH4%(   HuHHCHCHEdH+%(   uH]1c UHHdH%(   HE1HtG   =  HUdH+%(   uf.     U1HAWAVAUATSHh  HxHdH%(   HU1v*  L@E1ƅ LLǅ    Hǅ    Hǅp    LA    } Hǅ    	  IM1@ IcAA
   LM9  D(LpDE   A   uHH   DHo
  foHA   foDfoD foD0fo D@foDPfo D`fo0Dp1H뀈A
"fHMLIIcHN<2HIw&IH	  HJ<0H#xC< M	     LH=@d ~     LH=0d ~W     LH= d i~     LH=d M~B     LH=%d 1~     LH='d ~     LH=*d }     LH=d }     LH=d }     LH=d }D  
   LH=%d }  H
 D0A1   LH=b Y}   LH=c =}	   LH=c !}LHwp D1   C L  L.;HT  M| L     C|<
uCD< MH0ID$DF      @ IHHDV uDqsT HxMcK4HHH9%  HE1HILpLhD  LtI} H訑   AEA9DBI   LhI9uHLpE  E~Ad     32HHtWHDHe>LN  1IF0HHpHx0 6HJf.     Lx-'HEdH+%(   j  Hh  1[A\A]A^A_]þ:   L虄IHH   DpIcHHHcHH5m H@HA    HqLLL)HFHHHDDHHDDH3:   LIHH   DpIc(HHHcHH5_ H@HA   D:   LvIHH   DpIcHHHcHH5_ H@HA   :   L
IHBH   DpIcPHHHcHH5:_ H@HA   lA  S:   L蓂IHH   DpIcHHHcHH5^ H@HA   :   L'IH_H   DpIcmHH5HcHH5^ H@HA    L :   L讁IHH   DpIcHHHcHH5j H@HA       H:   L8IHpH   DpIc~HHFHcHH5j H@HA    :   L̀IHH   DpIcHHHcHH5] H@HA    .:   L`IHH   DpIcHHnHcHH5i H@HA    HƅLMIeH-H H1Hh 01=E1LIcADA
   H9   D+HEE   A   uHI   HH   foHA   HB8foBD8foBD8 foBD80fo BD8@foBD8Pfo BD8`fo0BD8pI1MI1HE1rHpHHHxH   H      HGHWH   H   Hpff.     UHHdH%(   HE1HEdH+%(   uH  i@ UHHdH%(   HE1HEdH+%(   uH   q@ U   HAUATSHH=FY HdL$%(   LeIt1҅uBHc   ~7H   H@L,f     HI9t7H;L3u   HEdH+%(   uH[A\A]]    1    UHAWAVAUATSH(  D   dH%(   HE1EI  H@HZ 1IfHnfHnLHflHLL%e HL=Y IH)@ HA9      H1MHI      LL~Y HH[fo   H¾   HHPIHH@   L H 1)L(SH@HHAZYAHUdH+%(   uHe[A\A]A^A_] 1W    UHHdH%(   HEHc   HUdH+%(   uf.     UHAWAVAUATSHHH}HuHUHMdL,%(   LmL*L9tdfD  AE$EuuHEHc   ~fMeL   E1fD  III9tCI>LȆuHELxMm L9mu1HUdH+%(   upHH[A\A]A^A_]fH} t@}I]H~d H}IH   1HUxAu,H}1)#H=W AHff.     UHAWAVAUATSH8HMHUdH%(   HEHH$HEM      ~wL`L   E1E1@ AID9tSK<>L觅uCL>H HHMHH HQHUdH+%(   uxH8[A\A]A^A_] H} tGHE}HXHJc H}   HI1輅HUxHEH}1ɋp,!H=MV ?HD  UHHdH%(   HE1HEdH+%(   uHH5k   lff.     UHHdH%(   HE1HEdH+%(   u1-fff.     UHAWLcAVAUATISH8  DdL,%(   LmL  H   YID$H@I   HЃ  H0@H   H13Aƅ  HAٹ      LG HHH   1<HHH HH   H1T{D   H1Aƃ  O#IHd  H ǅ    ǅ    Hǅ    Hǅ    ǅHLxH  x
uHXH1DHdu͋8%   =    uHHHHHH   % 	=   uHыLcH0	~4HLcHJ ff.     ;HHH9u9F  HB  HHދ[HD    Hǅ    I$  I$  HcH@HpH   HIH;Qd  L;y Z  LHyLII|8(HH9L;x HLxJT:(HHHHHqHVHPHQHHPHEdH+%(     H8  1[A\A]A^A_] fH51Hǅ    ) H@H H HH    H9L;x ؒHLxJT:(HHH@HHXHS:     uUL} HhfgH9jL;x `LxHIT(Hf.     )뢋H   LDHIcDDLHDDHDDHNHHHO 1   :wH1   8'f.     f.     @ UHHdH%(   HE1HEdH+%(   uHff.     UHHdH%(   HE1H9HUdH+%(   uIf     UHHdH%(   HE1HtG   =  HUdH+%(   uf.     UHHdH%(   HE1HEdH+%(   uH  !@ UHAWAVL}AUATSHӺ   HhH}HuHLHMLxdH%(   HE1HE    GE   1$f.     <_  AD?   HPЀ	wD= HuH}
   HEHE8_uHEHEHEff.     } tzH} t	HE8 tjH A
   fff.     MLIN4I6|   ~yIUHI  I^ HEHEHuff.     H HM   HZ 01-1HUdH+%(     Hh[A\A]A^A_]@ M?  MW    H LH)HEHH}    LxLuA$ LAHH   L=Z
 +   fff.     IH}IO4I6{tN~HH   M~ѐM   LfHED= HD8HEHE_    H	 LH)HEH       I|H5L ?{>HS   LLL}A$L}H	 LELHY    01-,h     Hى LEH&Y    HM01+7rfU  	 HAWAVAUATSHHH  H   dH%(   HE1وHǅ      H   1HD  ff.     H   HJE1HHJH)HzuLbHHHLLs   fDHHHI I	Lc   H    HPHDHHH%H	4   HHL1`  L   9H  LLf.     H	 L   HJ 011*HD      HHt.HE1E11HL`H`  f1L1AǅL@   L!+D  ff.     ff.     A|
  HH뀽@   LL2ID$H  HL   PH LI    Lк   10
   LkZYHt  L@MEt0@ AH==I kH  AE _MeIEuLLE2ID$H  Df.     H\HuH( H   HH 01P(H   E1H  HL= H     H   JHu   ff.     M   LHLhHH@HH    uDH HHҿ   M׋0HU 1'HHHHWaHHxRHHxBH^MVH   II9Ch1ۋ8HEdH+%(      He؉[A\A]A^A_]IH BAEMe E)Ƅ@ @ jH HMH<T    01&Dg
HC H,T    01n&f     UHAWAVIHzAUIպ
   ATSHhHx1dH%(   H]HND  A  HEIH]@   Hǹ@      HpLnF 1-
   H~hHt  D}Et6ff.     AH=F PhH  _D{HEuֿ  HH,  HpDHIK!  Hx.H   H   L.HCH   1HC0H   HC8H1fHnHCpH   flH5C8fHnflCpSWIFH   IVL   H   HHEdH+%(   uyHhL[A\A]A^A_]    3IHH CD;EH LHgR 101D$E1    HE1=dx UHAVAUE1ATSHH   dL4%(   LuIHtZ ff.     I   JHt3HH[L`I|$I|$LYZHuI   II9rI   VHEdH+%(   uHI   [A\A]A^]Aff.     UHAWIAVAUATSH  HHdH%(   HE1h &  I   H;  H@HGA E1LfHnfHnHfl)H   JH  HhLHHHHH H`H H(@ H(HH   foLn HLp1H`HH@   IFHp)HhHHHa~ HHHxH HHHHeB HH?  L\   @   LPP1\)HhAXAYHX  IFLB    HHDº   PHHPHHU~ H L   1(H     	 Lc   L)H@19~H^_A  H  IH!   Hȅ8  H   HA(   H(  AJAIDIHǅ8    H0LHCHv|H~ HL @   L,H    LPLA @   AU\PLP1	(H1LH 1SAÅ   H+.  IHKHHH  H!H!    HH   Hȹ(   H(W  YEH~ H@   L,غ   @   Hˮ PL LI@ AU\LPLP16'H1LH 1AÅ7Dߺ@   LDD%f.     ff.     A|
  HHDH+f     L8   H0L)H@HH     	 1{ǅj  H  IVH!N  Hȅy  H =  HA(   H(  AJAIDIHǅ0    LHHLMAHCHvvHD~ HL @   L<HM>    LPL> @   AW\PLP1%H 1LD1AÅ  H+tiIUHKHHH  H!H!tE   HH   Hȹ(   H(  DQIDH+fD  HHDQH      1L(L=    A6LH$H HZYu2IFH(HnLH   II91HUdH+%(     He[A\A]A^A_]fD  fH  H      HHHDDΨHH0W  1   @   HL \HO~ @   LL<H`< L< PAW\PLP1#H 1LD1
AÅ&@ ff.     Dߺ@   LD89D8 D  ff.     A|
   HHD fD  DѨ\@ fH  H      HHHDDΨZHDQtYAEP@     f     1\        pfD  qDQIDH Ƅ  1L
   D8L0fL H*H"G HH@ML/;    ^ LDHHL)I<H~ H 4Hu:    P   AW!D8H HIDL0< Ƅ  1L
   DL8fHH*L1 HSF H@MK<'Lc:    LDHP~ HL)H 4H    P   ^ AU!DH HIDL8O7f.     HpHǅp    HhffE  H   A   HHHDDDѨoHH0   AHA Ebf     f   H   A   HHHDDDѨHH0t|AHA ED  DAIDI A    ND  A         HAHDDAIDIE HAHx1O   E1*   E1   1c   1fff.     UHH dH%(   HE1h uH}vH}HEdH+%(   uH   KUE11HAWAVHUAUATISH(dH%(   H]HHuHS   AA|$h    uDu1I$   HfDOuyfA   I$   HEH   I$   D}E1HEHEN4Muo    MvMt_AFD9uIFHpHtHXuDHUdH+%(   u;H([A\A]A^A_]fL841@ IL;et1UHAWAVAUATSHXH}HuHUHMdH%(   HE1h   HEHMHML8L9   f.     AG$   IHUE11Hu   U   HEH@    HEH   HEH   Du1HEH   L,MuZf.     MmMtGMe LHD9uIEHpHtIuHEL`HEH   HE HH;]rHEHx tnM?L9}1bEHMHfHAH} tAA$I_HB H}IH   1cHUxAAw,H}1HUdH+%(   u/HX[A\A]A^A_]5[H=4 HD  UHSH8dL%(   LMLAy$u{IyHE11HUHut,MHt~ HH	w8  Hs-H HC1HUdH+%(      H]    H1 HC HtLIYLMHUZHA H}IH   1}bHULMȅLUxAq,1LuD  H=3 LULMHbfUHAWAVAUATSH   H$ H  HdH%(   HE1:HH  HH   1Hu3 HH Y  	 H1{oHǅH    @U  HX1E1H ff.     ff.     ff.     ff.     H  HPJHHPJH)HHz
uH HB   HIH1H2 HLX   H1nAǃ  1H5 1(  L1LE1GDLH8 D  IcIA@
   M9  A$х   A   uH8H   ,0EH  ,fo@H8A   0IfoPDfo`D fopD0foD@foDPfoD`foDp1H뀈@
IcIH8DN*H0IqHL8nIH  H0J<(H@kBL8C M~C|
~  HH LH1(DHHH ff.     H@1`     HH~JHPHK (   HHLL@ LE@HEdH+%(      H  1[A\A]A^A_]fD  Hyl LH#=    H01HHf.     H9l LH=    H01VD^HHBfCD wH8DHE1DYfUHAWAAVAUATISH   H  LoH`  	 H   1dH%(   H]ȉj|0  H`TxA9G  McD)J3HP  AHID\EHhH~ JMAHpE1D  H@      1AVLpL>. H}@   |11HuY^I$   L;hnL;x nH0HHIIHT(x5IL;htIL;PU  D\O    +aMD\   pDEYf     HPH8IIH|(x!QI$   L;h   L;p TmL(LpLAD(Asx5xDxI$   McLcL;hsL;p r%         p|HEdH+%(   urHe؉[A\A]A^A_]D  H`Dh     `HPff.     II9t	IVH9u|1QalfUHcHcHAVAUATSH0dH%(   H]H  Ht/H[H;C   H;S    H3HKHHHL(HH  HIH;A   H;Q    LHqLHIt0(L$1H   H;AkH;Q kHHuHQH|
(1ɺ    VH   D HtzL3
   1H}'LI$HCHID$HCHID$1HUdH+%(   udH0[A\A]A^]     1f     E1@     
   1H}ID$ID$I$ID$ f.     f.          UHH   H$ H dH%(   HE1h1=  t HUdH+%(   uY    HI   1LP,       HH1TN B [ff.     UHAWAVLAULLA   ATSH(  dL4%(   LuI1/D  H0H  ~H	w8I6E1H4HTrIH9uκ   LH  ILE     H9  8(  H   H)t&H9u   L_H\  ILH9  8 A  HH9  8+  HH9  8   HA   D  1A   3fD  HHpHЅxazЃ	  IE1HHTPHIH9u˺   LH   ILHHpHЅyfff.     }   1A   1D  HI>HЅxZDJHA	   HE1HDPIH9u̺   L%H  LII>HHЅy    HI>HUdH+%(      H(  [A\A]A^A_]E    uD;tAHD  EuHI>1뢺   LH~IL   LhHeIL   LDHAIL   L HIL1I    UHAWAVAUATSH(  dL4%(   LuIf  LDALLft8H
t_H9u   L{H~ILu    HUdH+%(     H(  [A\A]A^A_]fD  AE9uH9  8cuHH9M  8puHH9  8uuH    tH t&H9u   LHZILHcE1H1A   0fD  H0H!~H	w=I6E1H4HTrIH9uκ   LOHILD  E IL9u1L   LHIL   LHkIL   LHGIL薽fD  UHHdH4%(   HuH5E& HUdH+%(   uPUHHdH%(   HE1HEdH+%(   uɸ   f.     UHH dH%(   HEGw?HF~ HHHU[HUuHEdH+%(   uHf.     1觼    UHSHdH%(   H]HZ    C  H5. HO  H5.% H?  H5!% H/  H5% H  H5% H   H5$ Ho   H5$ HX   H5$ HA   H5$ H*   H5p$ H   H5$ H   H5$ H   H5$ H   H5$ H    tHUdH+%(   uhH]ø      ݸ   ָ   ϸ   ȸ      뺸   본   문	   른
   랸   뗸   됸   貺fUHHdH%(   HE1HtHUdH+%(   us UHHdH%(   HE1HEdH+%(   uH  4@ UHSHdH%(   H]H>tCHUdH+%(   uH]f1    UHHdH%(   HE1HEdH+%(   u	訹     UHAWAVISHHdL<%(   L}A$6u/H   t<1HUdH+%(   uUH[A^A_]f     H5uH   uLA&   DH  Huf.     UHAWIAVAUATSH   H`hdL,%(   LmAc5   DhA  Ix  ǅLHt	@(LH`DhDhAE9}6AFv]E~(ED  1Ix     AE9u    1HEdH+%(   5  HĨ   [A\A]A^A_]    IcE)ID H0E  1AMcDPLhMIߍt D<LTHEHHXME1       I|$  ,  $  Aٹ@      1HXL  @   }HX11YAƄ$  AI$   L;x]L;p ]HHPIIHDD(E  I$  L;z  L;r   H
HBIIHD(H  TDLuXIL;h  EI$x   A$    H`DI|$  f     DPMED<Dh@PDhHH`DpD+HXDMTD`Ea@ HxL HMHA|8(x.HhII   HhL;x  H;P Z\L8HPLD(sA  A\$I   HcMcL;xs
H;P r%    f     1H= 1WA     A    uH`A9    1҅<I$   PH@DL5H@HL
fD  I     Hp   Hip ʚ;HxI  FfD  D`HXTD+&DPMED<DhDNDhHÅ
f     MIL;0DPVѳH0     HH9HSH9ucZUHHdH%(   HE1HEdH+%(   u1mfff.     UHAVSH dH%(   HE1
  IHM LHcH>D  @HLHfD     HUdH+%(     H [A^]    H	I      H @H MtI   LM+LM؄  HHnfD  LMo!IH#  LMM   I   LMLM؄   I   ^LM؄  I   Ls!HHEH}HH0t    @H HHHD  cH     kH LHHL0ffD  I   LM؄u#I   `HH6fD  1.I   LMLMI   !HHI   LM_LMI   ʰf.     UHAWIAVAUATSHHdL$%(   LeAA-I  HcLnIcI;UF  I;M <  I} IuHHHt7(IM  Mt/MvI;V  I;N   I>IvHHHt7(I  wk  1D	  IE MM  IFHIEIFHIEIF IE 1HUdH+%(     HH[A\A]A^A_]f     LHUHM@,HUEI   H;PFVHMH;H 8VH8HpHHHD(EI  H;P  H;H   HHHHT
(HHE}11eA       1}}HU@ƃv  HEH]H+   7H  fH* ^Hb  fH*Y f/+  H,f     E1TP
   D	HE    t[1M  IIE G@ E1     Hu   rHiE ʚ;HEI+   f.     HAS LELHJ R(%   IE HE    nf     HE     IEIEIE     f     Et{HEHH@ fD  \H,H?KD  H؃fHH	H*XfHfHH	H*XKfI   b1҃}}HMƍTfHE~    IE 1IEIE覬fD  UHSHdH<%(   H}   HtOH= HHu,H5 H HCPHEdH+%(   uHH]ÐH11f.     D  UHHdH%(   HE1HHEdH+%(   u1٫f     UHAWAVAUATSH   H$ H   H$ H   H$ H      dH%(   HE1IH8IHǅ     HHID$HH0H HpH HxH  H   IIH1H :7HH'  H IL1   H6L;H(H HM(u<H H(HXHt"1fff.     <	   HH9rHLM1S   L% L      ~I<$H0L8AT$H I&XZHEdH+%(      He؉[A\A]A^A_]  H(HH9kH L@ &      &   DHL4 HHH`dvfD  UHAUATSH   H$ H(dL,%(   LmIHtdHMH# Hþ   H1F5H9HHDHUdH+%(   uH(  [A\A]]øɨf     UHAWAVAUATISH  HHdL4%(   LuI)H  HHþ  	 1KHǅX    Pe  HHh69LX@ ff.     M   H`PLhHH`PI)LXx.uA} tA} .uA}.uA} t ff.     H5v L<tH5k L;vHHLLAAǅuZLXMX@ ff.     P`  H1   FIH~H`H    E1PHEdH+%(   u@HĘ  D[A\A]A^A_]fD  AD8A AHD8A7֦fD  UHHdH%(   HU1HUdH+%(   uHHHH苦ff.     UHHdH%(   HU1HUdH+%(   uHH;HHp;ff.     UHAVAUATIH=R SH  dL,%(   LmI+Hb  HHþ  	 1HHǅh    `G  HHx6     HhH   HpJLrHHpJH)Hhz.uA~ tA>.uA~.uA~ t     H5 L9tH5 Ln9vH5 LW9_LLAAƅK`HEdH+%(      HĀ  D[A\A]A^]f.     `1`  Hڿ   H~AHpHf>D0A >HD0A]5x     E1]S UHHdH%(   HE1HUdH+%(   u     UHH dH%(   HE1HuH5H}H}HUIHUdH+%(   uã UH54HHdH%(   HE1H}HE    HEHUdH+%(   us UHATSH dL$%(   LeI:   Lt+HtWLHTHHtDL)HE HtBH}؉<HUdH+%(   uH [A\]D  1ߢf.     f.     f.     UHAWIAVIAUAH5s ATASHdH%(   H]L>H H  HH Haw̫IHBzՔHHi H)H݁ HHE H9}ACD-ff*A*XY[ K f/Y  H,He '      H=d I   H;    H=o L+ 1H= H    ?/   H    H= b)   Hހ    H= Em   H    H= (m   H    H=H m   H    H= m   Hj    H= ѿm   HM    H=A 贿m   H0    H= 藿m   H    H= zm   H    H=: ]m   H    H= @m   H    H= #m   H    H=3 m   H    H= m   He    H= ̾m   HH    H=, 课R   H+    H= 蒾R   H    H= uR   H~    H= XR   H~    H=0 ;R   H~    H=k R   H~    H= R   H}~    H= V   H`~    H= ǽHEdH+%(   uNH9~ H      [H= A\A]A^A_]鍽D  \H,H~ H=} ?uHEdH+%(   uHE L   H% H8H1[A\A]A^A_]     UHAWIAVAUIATASHHHg DEEf/dL%(   LMDMw/I f/w!  fTfUfVH+} H  H@ fL58} *(H%} L)l  fH*      eH=r m]DEDM>DMDE1MH=|    H ٛfL)]A*meYn H| YO   fH*YL^L)T  fH*YH5@ ^\f*I)  fI*H/| YH)   fH*^LH={ H4       HEdH+%(     H{ HH      [H=? A\A]A^A_]    HfHH	H*Xf.     HEdH+%(      HH[A\A]A^A_]fD  HЃfHH	H*X)f.     LAfHL	H*XHуfHH	H*XfHڃfHH	H*XZ=fff.     UHAWIAVAUIATASHHHg DEEf/dL%(   LMDMw/I f/w!  fTfUfVH+z H  H= fL58z *(H%z L)t  fH*      eH=r m]DEDM>DMDE1MH=y    H ٘]fL)A*meYn Hy YO X_ \  fH*YL^L)H  fH*YH5= ^\f*I)   fI*H#y YH)   fH*^LH=x H(       HEdH+%(      Hx HH      [H=3 A\A]A^A_] HfHH	H*XwfHEdH+%(      HH[A\A]A^A_]fD  HЃfHH	H*X5f.     LAfHL	H*XHуfHH	H*XfHڃfHH	H*Xf=fff.     UHAWIAVAUIATASHHHg DEEf/dL%(   LMDMw/I f/w!  fTfUfVH+w H  H: fL58w *(H%w L)|  fH*      eH=r m]DEDM>DMDE1MH=v    H ٕf]L)A*meY^ n Hv YXf(\  fH*YL^L)T  fH*YH5 : ^\f*I)  fI*Hv YH)   fH*^LH=u H$       HEdH+%(     Hu HH      [H=/  A\A]A^A_]    HfHH	H*Xof.     HEdH+%(      HH[A\A]A^A_]fD  HЃfHH	H*X)f.     LAfHL	H*XHуfHH	H*XfHڃfHH	H*XZ-fff.     UHHdL%(   LMAH=ut H   H=8 IfHwt * Htt H)   fH*H)   fH*Y^HMdH+%(      fA*Yܫ H)   fH*YL      H" ^ \@ IʃfII	I*XH)eHfHH	H*XPHEdH+%(   u'    HЃfHH	H*XXœD  UHAWAVAUATSHdL$%(   LeIHs H  HAA   H=    MYLr  H=xr H)H=  vAH=?B   H   fH*P      H>    ^ 4H=}r 1Lr DH    蘑MtH=Tr L   1H vH LHD HEdH+%(      Hr H      [H= A\A]A^A_]c HEdH+%(   ubH[A\A]A^A_]fHfHH	H*XffP      H*H.    ^ 3f.     UHAWAVAUATSH(}dH%(   H]HH9q H  H8 MIAII)L5 H Ho  H=       LEeLEp  H=p I  vBI?B m  M  fI*P      HJ    ^ 2H=p 1L(p DH.    褏MtH=`p L   1H' 肏L=4 Hdp ffHMp *UY  A*'H)  fH*LH)  fH*YH^H)  fH*YL      H=o H U^ \֎Ho fHo UA*'H)  fH*I)_  fI*Y^H)p  fH*Y^\A	~Y * %
 d   ]	 @ ff.     Y܃  f/rf/ե ?  HEdH+%(     Hn H(      [H=A A\A]A^A_]L9L5c Hf LCwfD  HуfHH	LH*XH)VHуfHH	HH*XY^H)FHЃfHH	H*X1LAfHL	H*XY^H)H؃fHH	H*X{    HуfHH	H*X*fH=m AM} H~       X\ f(藌ffP         H I*^ t/    HEdH+%(   uBH([A\A]A^A_]f.     LAfHL	H*X&f(RfUAHAWAVAUATSH8udH<%(   H}H=l H8  IHIMI)I   HS l  L5l HEI  n  H0 fH\l *HYl H)   fH*HH)  fH*YL^H)  fH*YӸd   ̢ ^ \] fD  YӃ  f/rfɾ      UA*Ye H 豊I  Uk  vOI?B   MF  fI*UH ^ P      L   b-UM1   UH=j Lj HQ $MUt'L   1UH=j H UH. fHj * Hj H)  fH*I)  fI*Y^H)a  fH*YHMH=Qj H
       U^\# ^Uf/ k  HEdH+%(   a  Hi H8      [H=} A\A]A^A_]MD  H ji  L5ci HEM~  fI*DMHB ^ LP         +H=ti DM HЃfHH	H*X]fHуfHH	H*X fHуfHH	H*XfH؃fHH	H*XfLAfHL	H*XOHуfHH	H*XfH=h Lf(HS	       輇l    fH I*^П * HEdH+%(      H8[A\A]A^A_]fD  LLfHH	H*Xj    LMfHAL	H*XfD  I?B fDMHd I*^'  f.     f("fUHAWAVAUATSHx  dH%(   HMHlg H  H5lg Lc   H= H^g    账H-g H  Ic% fҋhD *YL5* fHg A*H+g *  fH*f      H=f YH Y^^ \ԅEP   1H    Hp(Hkf H  IcfɋD *YhffX0 A*HTf YH+Qf K  fH*^H=f HpHI       X "H5 H= }d  h"IHu$   H5 H赌H  L   HHuL=,d LH5 H= "IHu+J    1
   H'H9Le .  L   HHuL荊He H  BfɍD *YhfXhfHd XƜ A*\ YH+d   fH*^LH=d HJ       X 賃   Hod    H= ֣HEdH+%(     Hx  [A\A]A^A_]Ð5 CD-f*hYf.     Hd @ L=b H   LTHfHH	H*XfHfHH	H*XfHfHH	H*XfCD-f*YhqfD  CD-f*YhL=a 赃D  UHAWAVAUATSH8MLEdL%(   LELb M  H`* ILcHIMI)H H  L- I9  Hb H  BfɍD *Yr Hc& Hb f* HH)  fH*Hb YH)  fH*^LǾ      Hj ea  H=a I  vBI?B   M(  fI*ƺP      H    ^A $LEM1Lla H=a H    MtH=a L   1Hg H[% fHa *Ha H)t  fH*LH)  fH*YH^H)  fH*YL      H=a H ^\ -H$ fHa *H a H)G  fH*I)  fI*Y^H)  fH*Y˸d   ^u \ ]m  Y  f/rf/E   HEdH+%(     H-` H8      [H= A\A]A^A_]遟H% L- H0H4H}DUL- LELcULEHH LDH_ HCDf*Y{ fD  HƃfHH	H_ H*XYH)HfHH	H*XD  HуfHH	HH*XY^H)HЃfHH	H*XD  HуfHH	H*Xwf.     H؃fHH	H*XfLAfHL	H*XHуfHH	H*XfHM      H=S^ Ht  }f.     fP         H I*^ T 3    HEdH+%(   uJH8[A\A]A^A_]f.     LLfHH	H*X    f(R*~f.     UHAWAVAUATSH   dH%(   H]ȉHj] H  LcIH= Iվ      躜      HK 9þ   H@O1A^H] H  Ic%۔ fҋD *YH  fH\ *(H\ H)J  fH*LH)  fH*YL^H)  fH*YH=|\ H H@      8^h \{H  HY\ f8*HJ\ H)A  fH*I)  fI*Y^I)   fI*YȒ d   ^ \Y] f     YӃ  f/rf/ /  H[       H=	 HEdH+%(   x  HĨ   [A\A]A^A_]D  % CD$f*Y:f.     LAfHL	H*XLAfHL	H*XHуfHH	H*XfHfHH	H*XfHfHH	H*XfHfHH	H*XfHIZ HtDBfD *f(YXʉf(ž   H=Z H    EyCD$f*f(Yf     f(JbzfUHAVAUATSH dL,%(   LmIHY HM  LcHIԾ      H=  HY fHt0M  fI*Hs  fH*^Y^ H7Y H  B
 fҍD *YX: L5 fH(Y HY A*&XX \H)  fH*I)  fHI*Y^H)  fH*Yľ   H=X Ht L%-S    U^f(w1   LHMHu L      I  U  L;-DX   V H?X fA*XH)Y  fH*HX YH)  fH*^LH=W H       vHEdH+%(   E  HW H       [H=! A\A]A^] P CD6f*Y@fHEdH+%(     H [A\A]A^]LAfHL	H*XHY^H)^HfHH	H*XI@ HfHH	H*XfHfHH	H*XfH؃fHH	H*XfI  H    LHS㥛 HH1HIк   I` U	M   fI*HR       L   X9 U^d ?UD  HfHH	H*XxfLLfHH	H*XC    >P Turbo   f6P _D  LLfHH	H*X5ufUHAWAVAUATSHHdL<%(   L}AH,U H  IH   AH=    MLMuHٞ MH=T IHB    MEMIE1tLMMtH=T Lɾ   1H sH=T E9|QE  E  HEdH+%(   J  HmT HH      [H= A\A]A^A_]E  EtH = L HE-X }H4T fHfA*A*Y]H)!  fH*HS YH)  fH*^f(HULE\;      Mf(rMMLEtnHS HfA* H)e  fH*H}S YH)  fH*^L   LEH=0S H    WrLEEfA*YeX% @ HS fA* H)w  fH*HR YH)2  fH*^H=R f(H[       q    HEdH+%(   K  HH[A\A]A^A_]fD  58 fHL" A*HfR fYuA*f(EX% H)  fH*H"R YH)M  fH*^f(f(LE      e- H> XmHUf(pMemLEI  щ HQ HfA* XH)A  fH*HyQ YH)  fH*^L   LEH=,Q    mH eIpEeLEm  H=P fD  L fHfHP A*Y% A*H),  fH*HP YH)o  fH*^f(f(LE      e\ H=`P H f(oMeLEFH_P Hf(f\| A* H).  fH*H&P YH)  fH*^L   LEH=O    eH neLED  L fHfHO A*Yj Xz A*H)  fH*HO YH)O  fH*^H    v    LEXMf(SnMLEHMfH#O XC A* H)  fH*HN YH)  fH*^LH=N H       mfD  HfHH	H*Xf.     H؃fHH	H*XtfEEE>e4@ HfHH	H*XfHfHH	H*XfHfHH	H*XfHfHH	H*XfHfHH	H*XfHfHH	H*XfHfHH	H*XAfHfHH	H*XgfHfHH	H*X|fHfHH	H*XfHfHH	H*X_fHfHH	H*XfHfHH	H*XGfHfHH	H*X#fHfHH	H*XZfHfHH	H*Xklfff.     UHAVAUATSH dL4%(   LuIHK H  HAAԾ      H=` >MtH=K L   1H j| ffHL5b HK fA*A*YH=jK YA*H)  fH*HhK YH)   fH*^E90  X% f(ef(f(¾      H{ .jHK feA*H)@  fH*HJ YH)  fH*H=J       HR ^f(iHEdH+%(      HsJ H       [H= A\A]A^]ɉf     HfHH	HQJ H*XYH)HfHH	H*X^E9X f(e    HEdH+%(   uOH [A\A]A^]@ HfHH	H*XfH؃fHH	H*Xifff.     UHAUATSH(dH%(   HMHCI H  IH   AH=    蓈%   HI    H= vMtH=H L   1H hL% fHfHH A*Y A*$H)   fH*HH YH)  fH*^¾      H=lH H MgH|H MfX; A*$H)  fH*HDH YH)   fH*^¾      H=G H %gHEdH+%(      HG H(      [H=W A\A]]+ HfHH	HG H*XYH)HfHH	H*XD  HEdH+%(   uWH([A\A]]fD  HfHH	H*Xf.     H؃fHH	H*X}gfff.     UHHH=F dH%(   HMHH   HF LEdL+%(      ff*He
 Ye~ Xm~ * H)xDHF fH*YH)xTfH*^¾      H oe    HfHH	H*XH0F YH)yHfHH	H*X@ HEdH+%(   uZff.     UHHdH%(   HMHE Hw        H=# q} H=zE 1L       f(H dO} 7} H }       H='E H Sdd      | H=E LV    Hg f(d| | H$ /}       H=D Hg c      | H=D L    H f(cm| U| H |       H=ED H qc,     | H= D LS    H f(<c{ { HO ]|       H=C H  c  { H=C H%       f(LY b{ s{ H6 {       H=cC H bHEdH+%(   u1HAC       H= 颂fHEdH+%(   ucf.     UHHdH%(   HMHB HW        H=c Az H=B 1L       f(H az wz H z       H=gB H ad      9z H=BB L,    H f(^az z H oz       H=A H "a      y H=A L,    H6 f(`y y H z       H=A H6 `^     Wy H=`A L.,    H f(|`<y $y H y       H=A H @`&     x H=@ Lp    HT f(`x x HM Dy       H=@ HT _     ux H=~@ L]    H f(_Zx Bx H x       H=2@ H ^_   	x H=@ H       f(L )_w w H rx       H=? Hr ^HEdH+%(   u/H?       H=(  HEdH+%(   u_f.     UHAVAUATSH dH%(   HE1H=>?     HY? HJ? H9  H!"Kgf(Ha*   HHH9  w A   I!"KgHm.:BGH	K   HH	H9rgw A   Ia*   f/scHÀ H9Y  Hvu A   IHI9sHm.:BGw H	K   A   HH	H9rf/rIa*   H= HN> Hf*H)j  fH*YH)4  fH*^HeEAPv H    H= H==    HÀ f(\H= ZeYH9s_H<v A   IHI9Hm.:BGsoH	K   HH	H9 u A   f     HEdH+%(      He[A\A]A^] t A   D  H	K   HH	H9s A   +f.     HfHH	H*XfH΃fHH	H*X]fff.     UHHdH%(   HMHX< Ht-      H= {H=6< aH&<     HEdH+%(   u\     U   HAWIAVAUATSHhH}EgpdH%(   HEȋG(HchDe}Ix蒜Ic   HEH~HEH  H  xA   D9DNI   HEE8  I   HE    HEHff.     IH   Lu1H!I	AI13 AA9~wID   HHLI	AL9|LHMHEHE9Ah   H}mHMH]HDHEHT@ LHi #      H= HyH}JH}AHEdH+%(     Hh[A\A]A^A_]DapE   HE         H}LuIHoHE1L1H	IA7 AA9;ID   HHLI	觵ALL9|LH}GHMHEHDHMHEHE9ApTIcH<    HE蠛HI9 IH  x~D   HHZEE1Hǅp    L  HpH}HuH	HHx蔖EA9       U   HcEE1HHH?HEu@ff.     ff.     ff.     ff.     ff.     ID9~lH}LHEH	MHHH HsHuA9~.D  HcH}IH߃8tjHuHc~]A9׋UID9UHuHxH}HcN]EA9HpHp9E1P D0HuHcA]A9bUHn~       H== Hv W UHAWAVAUATSH   H$ HXHdH%(   HE1HH  ff.     HH  xuLhx.uA} t     x.  LIHtHaIH
  fLXH  xuLxx.uA t     x.  HLuHML   HՂ HH11bǅxH   HH藓H]  H1
   H;#LKLHۊ   aHHtYHM1   HyE       1H{M   HRE    yHHH1HEdH+%(      HX  H[A\A]A^A_]fD  A}.?A} 4HHf     HfD  A._A TLrHf     LȉL UHD/@ ff.     UHAWAVAUATSH   H$ H   H$ H(   dL,%(   LmIH=a4 1Hǅ    1HI18  AM   Hfff.         HD`<M   1D~HEdH+%(      H(   [A\A]A^A_]fLc=3 HLLUL9tf     =3 HL+L9Nw     =b3 HLLpHLH~ H    01끐H~ Hٿ   H 01|
NS ff.     UHAWAVAUATISH   dL,%(   LmIǅ$    Z]HH   ff.     HH   xuLxx.uA t     x.  M
MvMtIvLu1H(MLH)    G  H(H0謙H(A}ETH߃$UHMff.     =1 H$   YHtsH<~ H    A01aHiHEdH+%(     Hĸ   D[A\A]A^A_]ÐA.A D  H     HH   xuLxx.uA t     x.   M
MvMtIvLku1H(MLH       H(H0<xH(   AƅuKH(HHD E1     A.OA 
?H(AH~ L   Hʻ 01ʕeD0Aa5PD  UHATSHdH%(   HE1HE    HHtWHL@H}1Hl    xSff.     IH[I|$LLHuH]HEdH+%(   uHH[A\] HE    yOf     UHHdH%(   HEHH9u%fff.     H H9txu    1HUdH+%(   uOUHAWAVAUATSH  HdH%(   HE1H 5. HH9O  LIE1ILH   f.        覃:   HIHMV  HM  HHHH)GLIE LIxMIEI}     H   MoAMM$$L9  A|$uI$(  HPI|$IGIHuH~ H    01.HHt(fIH[I|$LLHu1   LȂHHx踂H謂LMoM'I$(  :   VH=N     L8IG    fD  EDDgHHW@   臎HH=D`H     E    LmED=8, fu
   LEtracEcingH
W  =	,    H5 H.  =+    LE H  =+    LE^H  H5 =+    =H  H= wIH  H LHH<  =L+    H5a H|  H~ HH 0   1LUǅEtFD%* L   1D艷DIE uD5* tff.     Hd@ IH[I|$OLGLHuHHUdH+%(     H  [A\A]A^A_]fD  foe Hx	@	G FE  H   Hx	14  Lm  
   LEtrac) fMEDEcingH
ǅ E   L   LH= 脅IH*  HHS  =c)    H5k H     LW  LsH=| IH  HH LAǉ/EH=yr ǅ    `HH  HhSIH}  ff.     LH   xuHPx.uz tـx.uz.uz tH5 HHtHIMHMtI7HHuڃnH~ L   H 01ύL7H{~ Hس    01覍HJ1@HL~ H 0=' H   7Ht5H~ Hd    01ELM|HGL@ LH   xuL@x.uAx t     x.uAx.uAx tff.     H5I LLztHL     H3LU2  H[HuHXǅLv{HqH   =b& Hǅ     H  H= ļIH  HHɍw     LdL6  H=p lIH  HHq  L   LEH)~ H2 0bHH1MHvP    LHyHH ތxEH讟H=% LxLI9  H H  H iHHs    HH	HV~ 01荊H11'=$    Hǅ     )LH   EXH~    H 011{ǅ!=$    HHǅ     LHth,E3ǅHm~ H 0HN~ H/    01yiEEH~ H    01:Ha H~    01H   H  ؉H~ 01݈rHX H sLwHHc~ H    01莈EǅBUHS1H(dH%(   HUH u#HHEdH+%(   u0H]@ Hz	1HUH}H}؉:@HUB@ ff.     UHHHHdH%(   HU1HtHUdH+%(   uH;xHEdH+%(   uɸBUHHdH%(   HE1HEdH+%(   u1Afff.     UHHdH%(   HE1HEdH+%(   uA@ ff.     U      H= HHdH%(   HEH~ HG`HEdH+%(   uɸ<Aff.     U      H=: HHdH%(   HEHW~ H_HEdH+%(   uɸ@ff.     U      H= HHdH%(   HEH~ H_HEdH+%(   uɸ|@ff.     U      H=2 HHdH%(   HEH~ H'_HEdH+%(   uɸ@ff.     UHHdH%(   HE1HEdH+%(   u1?fff.     UHAUATSHH8t dL$%(   LeL%$t L9tOIf.     HL9t8H{L}uHtH[HEdH+%(   uHH[A\A]]f1G?    UHAUATSHHs dL$%(   LeL%s L9tGIf.     HL9t0H{HsAՅtHUdH+%(   uH[A\A]]    1>@ ff.     UHAWIAVIAUMATSHHH(HUdL$%(   LeMcHUHtH HH   LsHCHSL{ Lk(Lc0HEdH+%(   uH([A\A]A^A_]">fUHATSHdH%(   HEH~ H8   Hlr L%er L9u+fD  HL9tH{H5 @|uH      iH   H!r HB~ L @PythHH@hon Hq HPHHq L9u"HL9tH{H5 {uHu|   ~Htmpy  H~ @ fPHq HHHq L HPHHEdH+%(   ujH[A\]     @   ~H~ HHH~ 1HK 01*HEdH+%(   uH=~ H[A\]q<fUHATSHdH%(   HEHu~ H8   Hp L%p L9u+fD  HL9tH{H5j zuH      }H   Hp H~ @Perl@ HHHdp L HPHHKp L9u%@ HL9tH{H5@k (zuHu|   U}Htmpl  H~ @ fPHo HHHo L HPHHEdH+%(   ujH[A\]     @   |HG~ HHH\~ 1H 01芀HEdH+%(   uH=~ H[A\]Gp:fUfH HAWIAVAAUATSH8   dL,%(   LmI)EuHC A   Hܦ HEH	 LL1!mÅ   D%f    	    C  E      !  c  =     =    AHh =      D  DuLmMt
A  1L9b  At	AcHL9J  At	ArHL92  At	AoHL9  At	AsHL9  A t	AyHL9   A@t	AiHL9   Ey	AAHL9   A   t	ABHL9   A   t	AEHL9   A   t	AxHL9snA   t	AgHL9sWA   t	AhHL9s@A    t	ADHL9s)A @  t	AtHL9sA   t	AmHA   tL9s	AnHA   Q  L9?  EyL9  A?HL9   A    D  HU HcLH 1H)LjADDuL%\~ L   LmDAE1     A#$tDEHuIc   H L` HLDH)1L蓄{AAML$IMuEDDuLmA  A d    BHEdH+%(     He؉[A\A]A^A_]fD  A?HL9A   t	A?HL9A   t	A?HL9yA   t	A?HL9^A    t	A?HL9CA  @ t	A?HL9(A   t	A?HL9A   t	A?HL9A   t	A?HL9A   t	A?HL9A   t	A?HL9A   t	A?HL9A    t	A?HL9kA   @^A?HP    L
 HE   LcAQHǹ      AQLǡ HE1DUnH}ULK<'AXL)IAYI   Hu   1HA   Ls D+MZYÅfD  Ab   H fD  Hi @ HcLHe H)I<1-gALLMLU H1   荁kH  SH GH ;H /H~ #H Hm Hh H= 3    UHAWAVAUATSH   H$ H8dL<%(   L}II;oL5d Hǅ    H   HH HM   H1荿HEHHH۰t'HHUdH+%(   u[H8  [A\A]A^A_]@ HHMLHHH  H2fD  UHATSHdL$%(   LeI<yHt7HH,gI$ID$1HUdH+%(   uH[A\]f     T2@ UHAUATISH=  dH%(   H]Hu?H= g4ucL-    L81LE1L; HEdH+%(   uDH= HLH[A\A]]@f     HEdH+%(   uH[A\A]]1ff.     UHSHH7dH%(   H]HH'HEdH+%(   uH;H]61fD  UHAUATISH=  dL,%(   LmIu?H= G3uSH    H71H%1H HEdH+%(   u6HLL[A\A]]HEdH+%(   uHH[A\A]]z0f.     UHATSH=  dL$%(   LeAu?H= 2uXH    H61Hj1H` HEdH+%(   u9H= HD[A\] HEdH+%(   uHH[A\]/f.     fUHH0dH%(   HE1HtiFHHVt1҃tHEdH+%(   6  HfD  LF MtA@   t%HQ(HtB   tk1    HuIp LEH}[H}LEHHMHt
H;xoIp(HMH},H}HMHHtH;xuCHr HUH}H}HUHtH;xt_Hr(H}HH1H}H;zHEHBH9z    HDf.     IPI9xH0.UHH0dH%(   HE1HtJHB  1ɃtHEdH+%(     HfD  HJHtًAtt*1fD  H;yuf.     HJ f.     LA MtA@      HI(HvAtuHq HUHMH}H}HMHHUtH;xtHq(HUH}zHH H}H;xHU\1D  Hr HUH}H}HUHHHR(Hf     I;x5Ip HUHMLEH}H}LEHHMHUt
H;xIp(HUHMH}H}HMHHUH;x:,f.     UHAUATSH- L/dL$%(   LeItBHc5 It$L謨IЉHEdH+%(   uGH[A\A]]@ L訽HtH5P H蔰HtHcp(X,5  +D  UHAUATSHu L/dL$%(   LeItBHc5[ It$LIЉHEdH+%(   uGH[A\A]]@ LHtH5 HHtHcp(X,5
 
 *D  UHAUATSH
 L/dL$%(   LeItBHc5
 It$LLIЉHEdH+%(   uGH[A\A]]@ LHHtH5 H4HtHcp(X,5:
 0
 %*D  UHSHdH%(   H]H~e1HtHUHH舏HUHEdH+%(   u	H]H)    UHHdH%(   HE1HEdH+%(   u	H?M)     UfHAVIAUHpATSHpdL$%(   LeM)E)E)E)EuMHUPvI>1HUL4 H0 Hp!HpLHpҐHEdH+%(   uHp[A\A]A^](UHAUATSH(dH%(   HEHGHX8Hn  I@ HHY  C@  uLcMtAD$   uIT$ HI  B3  4  HJ HtA  N  HR(H	  B      Hr LHU<HUHtL;ht-Hr(L!H   L;h    ff.     Lc M   fHn )g )p I|$11" 1Ҩuff.     HtID$Hc M$$MuH HEdH+%(   E  H(H[A\A]]L;jXMd$(MbAD$   KIT$ HtB  K  Md$(MAD$tLIt$ LHt
L;hIt$(LHL;hfM;l$Lc M HS HtB   t&Hs(LIHnqf     LbMtAD$   uIL$ HtA     Md$(MtAD$   uIt$ LHUHUHtL;ht(It$(LHUHHL;hHU:Lb M(Hr LHUHUHIHr(LIHvL;iRfL;j2AL;i!@ M;l$pHq LHUHMHMHUHt
L;hHq(LHUHUHjL;h`Hr LHUHUHt
L;hHr(LH}L;hsHq LHUHMnHMHUHt
L;hHq(LHUGHUH%L;h{#fD  UHAWAVHUAUATSH8dL<%(   L}IHH5m HE    HE    zH   IHEHETf1   HqIHEHxqr1HUH5 HzLLHI2HSMt1HUH5 L{zHuH?~ H 101mhHEdH+%(   uH8[A\A]A^A_]"f.     UHAVAUHUATSH0dL4%(   LuIHH5_ HE    yHHu$X     1HUH53 yHHt61HMHUH5 euˋUHuL<f.     HEdH+%(   uH0[A\A]A^]!@ ff.     UHHdH%(   HE1HEdH+%(   uH J!@ UHHdH%(   HE1HEdH+%(   upJ{!ff.     UHSHdH%(   H]H0	\  HH= u-  HH=k ^  HH= G>  HH= 0.  HH=   HH=ލ   HH=؍    HH=э Դ   HH=ȍ 轴   HH= 覴   HH= 菴   HH= x       HUdH+%(      H]ø   fff.     HHE~ HHD@ HEdH+%(   uWHH]11      뺸   본   문   른   랸   뗸	   됸
   뉸   }f.      UHAWAVAUATSH(udH%(   HE1   D5n IAfD  MA)tXIcLD\HÅ~s=,  LctLL   G~9tH(~ He    13Sd8E~jHcEH HUdH+%(   uKH([A\A]A^A_]H~ A3MH 1   c@ H~ E1_DEH~ fUHAWAVAUATSH   H$ H   H$ H(E1dH%(   H]H fD  AHC   =    HZIHx   =  t   H   HcL9uH~ H0    01c1HEdH+%(      H(   H[A\A]A^A_]     H~ HY    01bfHi~ H    01bfMcL%. L^HHrLHHHX UHAWAVAUATSL$ H   H$ L9uHX  H   dH%(   HE1= HfƅD t,f9tWH~ H    01aH@ HEdH+%(     HX`  H[A\A]A^A_]     8u   H`ttract'H~ H    01#asfD  ßcingu7HHL   H;  HD  H   HH!AHn1Hd   H   L   DLnty   LH艗AƅtbAH֘DH諕   H*t5Hheader_pH9trH~ Hj    01_fD  HtH_HHl    Hi~ H    01_fȿage ~   LE1t   LH蛖IL[IHdDHI  HhLLH߉e  L踕   HHheader_eH9t+H~ H\    01^f.     Hr_event H9ſu¾   Lt<   LH軕AŅt%@ A    HE9ENDdE)u߾   LR     LHiH   E1HD  LLHr   L蜔AD9      LE1t   LHILYIH  DHmH6~ H3 0   1a]L	t@ H	~ H" 0fD  HЧH߉ƕ   L#     LH:Hk  ǅ    HH   L     LHH   E1BfHLLHkvAŅ   LEukAGA9      LE1Pt   LHkIL`XIH  DHpL訒H蜒    H~ H΄    01[Llf.     HT9ff.        Lt1   LH螒tAŋ=    LL-    L@t^   LH[IƅtGxLWIH DHDEHLCD5  usL}H1Ϸf/o- s$N  HO HF   Ltʺ   LH译IHtHxVIHtmDH[t~HHDLA 1RLِoHݷ~ H 0Hȷ~ H    01YiH~ H    01YH~ Hт    01YLTf.     f.     f.     UHHH   dH%(   HEH   @+BHUdH+%(   uHff.     UHHH   dH%(   HEH   @+BHUdH+%(   uHkff.     UHH"  dH%(   HE1"  1u("  H)HUdH+%(   u "  H)UHHH  dH%(   HEH  H@H+BHUdH+%(   uff.     UHHH  dH%(   HEH  H@XH+BXHUdH+%(   u[ff.     UHHdH%(   HE1HEdH+%(   u1fff.     UHHdH%(   HE  +  HUdH+%(   uH UHHdH%(   HE  +  HUdH+%(   uH UHHdH%(   HEH   H+   uH   H+   HUdH+%(   uC UHHdH%(   HEH   H+   HUdH+%(   u UHHdH%(   HE  +  HUdH+%(   uH UHHdH%(   HEu1x19  HUdH+%(   ut@ UHHdH%(   HEH  H+  HUdH+%(   u3 UHHH  dH%(   HEH  Ht4Ht?   2   	ЃHUdH+%(   u!     HH        @ UHHH  dH%(   HEH  Ht4Ht?      )HHUdH+%(   ufHH        4@ U1HHdH%(   HEH  HtHPXH  1HtHAXH)HUdH+%(   uf.     U1HHdH%(   HEH  HtHPH  1HtHAH)HUdH+%(   uzf.     U   HHdH%(   HEH  Ht
   H     Ht
   )HHUdH+%(   u    U   HHdH%(   HEH  HtH   HH     HtH   H)HHUdH+%(   u@ ff.     U   HHdH%(   HEH  Ht   ?  H     Ht   %?  )HHUdH+%(   u ff.     U   HHdH%(   HEH  Ht   H     Ht   )HHUdH+%(   uUHHdH%(   HEH   H+   HUdH+%(   uS UHHdH%(   HEH   H+   HUdH+%(   u UHHdH%(   HEH  H+  HUdH+%(   u U   HHdH%(   HEH  Ht
   H     Ht
   )HHUdH+%(   ug    U1HHdH%(   HEH  HtHPpH  1HtHApH)HUdH+%(   u
f.     U1HHdH%(   HEH  HtHPxH  1HtHAxH)HUdH+%(   u
f.     UHHdH%(   HEH   H+   HUdH+%(   uc
 UHHH  dH%(   HEH  Ht,Ht/   2   HUdH+%(   u HH   	@ UHHH  dH%(   HEH  Ht,Ht/   2   HUdH+%(   u HH   	@ UHHdH%(   HEH   H+   HUdH+%(   uC	 UHHH   dH%(   HEH   HtDHJ H+J1HtHP H+P1H9HHLHUdH+%(   uf     1HufUHHH   dH%(   HEH   Ht<HJH+
1HtHPH+1H9HHLHUdH+%(   u 1HuJf.     UHHH   H   dH%(   HMHH   H   Ht~4 t5Hty4 tH)HUdH+%(   u!fD  HH+A    HH+Vf.     UHHdH%(   HM1HMdH+%(   uHHHH   H@jf.     UHHHdH4%(   HuHH   HBHtHUdH+%(   uH@ HBfff.     UHHHdH4%(   HuHH   HBHtHUdH+%(   uH@ HBfff.     UHAUIATSH   HHLPLXt&)`)p)U)])e)m)u)}dH%(   H(1HEILHH   LH0Hǅ   ǅ0   H /Hí~ AHCHE~HHu2AEE9ALH(dH+%(   u'H   [A\A]] .HCH0HHufUHAVIAUIATISHH   dH%(   H]؉   LL9CHDBH HDI   HEJPHs 1gHUdH+%(   uHe[A\A]A^]fD  UHHHHdH4%(   HuHHUdH+%(   uL  H
 1@ UHHHHdH4%(   HuHHUdH+%(   u H  AHs L   1:f.     UHHHHdH4%(   HuHHUdH+%(   u H  AHr L   1?f.     UHHHHdH4%(   HuHHUdH+%(   uL  H
 1@ UHHdH%(   HEH  LH-HHr LDHEdH+%(   uIAHLHq 1@ ff.     UHHHHdH4%(   HuHHUdH+%(   uD  AHq 1&UHHHHdH4%(   HuHHUdH+%(   uD  HA 1t@ UHHHdH4%(   HuHHUdH+%(   u H   L   Hp H1fff.     UHHHHdH4%(   HuHHUdH+%(   uD  DAHp 1%UIHHH  dH4%(   HuHHte   t:H! H,6 IHEdH+%(   uCAHp L1D  tH H5 If     L5 "fUHHHHdH4%(   HuHHUdH+%(   uL   Ho 19 @ UHHHdH4%(   HuHHUdH+%(   u!D   L   Hdo H1| ff.     UHHHHdH4%(   HuHHUdH+%(   uL   Ho 1$ @ UHHHdH4%(   HuHHUdH+%(   u!D   L   Hn H11ff.     UHHHHdH4%(   HuHHUdH+%(   uL  H`n 1t@ UHHHdH4%(   HuHHUdH+%(   u!D   L  Hn H1ff.     UHAWAVIHm AUATILSHH  dL,%(   LmA%  LHXp1L   HBn LcI1L)K<<LL> H%| Hc1LELH)I<H)HHI9sC< HEdH+%(   uHD[A\A]A^A_]9f     UIHHH  dH4%(   HuHHt]   u<H H2 IHEdH+%(   u=Hn{ L1*f.     H> HZ2 ID  LI2 f.     UIHHH  dH4%(   HuHHt]   u<Hm H1 IHEdH+%(   u=Hz L1f.     H6 H1 ID  L1 f.     UIHHH   dH4%(   HuHHt-HUdH+%(   uFL@ L+@H; 1L@ HEdH+%(   uL! L1Hi; kff.     UIHHH   dH4%(   HuHHtHx  u.HEdH+%(   uGL L1H: ffD  HUdH+%(   uL@L+ H: 1L8 UIHHH   L   dH4%(   HuHHtx4 t(HEdH+%(   u"Hkj L1    L L+@bfUHHHHdH4%(   HuHHUdH+%(   uH(  Hx L@81uU   HAVAUATISH 9H   dL,%(   LmIBDwYD;w   H?`[DDHHHtbHEH}HEHEHtCHAADPH+i 1LLHUdH+%(   u)He[A\A]A^]D  H     ,ff.     UHATISHH MH   dH%(   HE1m
MIHEdH+%(   uH LHA[H|h A\1]@ UHATSHH   dL$%(   LeI
HI$   	HH認HUdH+%(   uHH[A\]Kff.     UHHdH%(   HEHH   H   Ht)Ht,H-H-?HHUdH+%(   u@ HH   @ UHHdH%(   HEHH  H  Ht)Ht$H-H-όHHUdH+%(   u@ 1H	tHHH_@ ff.     UHH dH%(   HMH  H    tHEdH+%(   u)D  HQHq HMHyLHMH   f     UHHH0L  dL%(   LMII    t@M  I   HteH  H   ʋHHUdH+%(       IPIp H}IxLMLEcKLELMHMI   fD  IxIPLMIp HMLE+KLELMHMI   I  H   XUHH dH%(   HMH  H    tHEdH+%(   u)D  HQPHq`HMHyHJHMH   f     UHHH0L  dL%(   LMII    t@M  I   HteH  H   jHHUdH+%(       IPPIp`H}IxHLMLEJLELMHMI   fD  IxHIPPLMIp`HMLEILELMHMI   I  H   XUHAVAUATISHHPH   dL,%(   LmAHG  H0~ RH)H@H   HfHt,HHH   fH*H   fH*^PfɅuiLc @      @   H}   B1LEDH_r LHHUdH+%(      HP[A\A]A^]f.     @ffH*H*Y
 ^qf.     ff(Z H΃fHH	H*XHHуfHH	H*XHEdH+%(   u*HPDLHL
 [Hq A\1A]A^]7fUL
 Lb HAVAι@   AUH}Iպ   ATI@   SHXdH%(   HE1AQ@1LEDHq LLHUdH+%(   uHe[A\A]A^]AUHP  E1HAVAUIHUATIHuSH@dH%(   H]؉1"HEfHt4HUH   fH*Y,	 H   fH*^L-1            H}   ?HLa 1LMALLHUdH+%(   uVH@[A\A]A^]ÐHуfHH	H*XY HkHfHH	H*XV UHP  E1HAVAUI1ATIHuSH@dH%(   H]؉HM LM    1L?0        H}>1LMLHS` LA؉HUdH+%(   uH@[A\A]A^]lff.     UHP  HAVAULEI1ATIHuSH@dH%(   H]؉1@ LMMtHE1II       H}1Lv/     *>H_ 1LMALL-HUdH+%(   uH@[A\A]A^]ff.     UHATSH dH%(   H]H   HtqL   H   HLHU>HH{ 1ATHUA   HA   BHXH~ ZH9t:   HMxHt; u3H;lH HEdH+%(   uHeH[A\]f       fD  UHHH dH%(   HMHH  Ht%H  HtIԃHHUdH+%(   u^ÐHMH}HUHMHH  H  HuD  HHUHMHMHUHH  H   UHHdH%(   HE1HEdH+%(   u kff.     UIHT HH0H   dL%(   LMIHu.HEdH+%(   udH LL1f.     H   LMLEH8HuOHuH  eLELMH HtHH 6fD  UHAUATISH]HHHH~ H  dL,%(   LmIՉM    8 t:U?MH
 1ILL+HUdH+%(   uHH[A\A]]ÐMUfHAUATSHx  dH%(   H]H)EEH  )EHEH  Hp)EL@)Ea:LIHt)H~ z tO  H  HHp|HppHUdH+%(   u4Hx[A\A]]@ H8HU1Lw Hػ Hp ff.     UHSH8dH%(   HEH  H  H  IHk  H      @8y  @8H  LHHHqHLH	   MS  H"  HF Iy LMLEHH}HHUwKH}LMЅLEHU        AA0u{8   H   H   LEHEHUHyHM蝅HMHUЄLEu=y t1u1Au*f.     I   H   @9A   |\@ H  I  H~ HX`HM2@u%} HMHH HEHH!H#A`H9r6H9    HUdH+%(   uH]fD  H@ HfUHAVIAUATSHHL(  dL$%(   LeI%@   EHEdH+%(   u1A  LHߙIM8HH_Y [A\A]A^]A1<ff.     UHAUIATI
   SH8MdH%(   HUH  H}9M1LEH8
 LL9HUdH+%(   uH8[A\A]]f.     UHAUIATI@   SHhMdH%(   HUH  H}M1LEHf LLHUdH+%(   uHh[A\A]]:f.     UHAUIATI@   SHhMdH%(   HUH  H}M1LEH~f LL9HUdH+%(   uHh[A\A]]f.     UHAUIATI@   SHhMdH%(   HUH  H}nM1LEHe LLHUdH+%(   uHh[A\A]]:f.     UHAUIATI   SH8MdH%(   HUH  H}dM1LEH8
 LL9HUdH+%(   uH8[A\A]]f.     UHATISHH@MH  HxxdH4%(   HuHuw|MLHIHd 1HUdH+%(   u	H@[A\]@UHATISHH@MH   dH4%(   HuHu|MLHIHd 1QHUdH+%(   u	H@[A\]@ UHAVAUATSH   H$ H H(  H;ۍ~ H;!~ dL4%(   LuIIuH;~ tvL  I   LHLVL   HK8H\U 1LE$  LHUdH+%(   uqH   [A\A]A^]ÐHEdH+%(   uQHK8H   L1[LH A\A]A^]*f.     LHT    qL`ff.     UIL- HH H  dH4%(   HuHc   @ 9uLHt+HEdH+%(   uDIpI8HS 1ISq H   HLELMp8ULELM UIIHH0Hc   dL%(   LUIHt*HEdH+%(   uOI   IQLI1H@  H   HuH}I  p8LULMLELU_@ ff.     UHHdH%(   HE   tHUdH+%(   u@ H   Hp8Uff.     UIHH0H   dL%(   LUIA8u4y(Q,I  HI  hHHUdH+%(   ukD  H  H}HUHLULMHMIHUHMLMLEA9LUtA,A(A9   zA   n'    UHH   H$ H   H$ H0HWH;~ dL%(   LEIH   H;~   H;Ȍ~ tvH;W~ Q  H;J~ \  H;m~   H;~ Z  H;~ e  H;F~ t,H;%~ t#H;D~ ^  H;~ ufff.     A@,   HQHz tA@$   1HUdH+%(     fD  H~ H0H)HH=׊~    LHL	  A@(   HQ{    H~ A@,   HQ8XHUHBHQD     A@8   HQ+    A@0   HQ    A@4   HQ    A@<   HQ    H~ @'HQ@ LHHnHHLkLH5~     LLNH~ L1HO HH~ 01%rfUHAWIAVAUATSHHHuHUdH%(   HEHc   HEH   A    ulHEH  H  I   L`L.:If       I^    HhLLHIv^Muх   H},HEI   H}H  %H]HEHMIHN H8HpI1kHA[HEdH+%(      HHD[A\A]A^A_]fD  Dw|Eu7H   H{O9E   S,A9DLC8DDA9DLEw|IcHE@ H9L4J|+LH)HH/HEdH+%(   u\HEHMLc HM HpH8HHI[1A\A]A^A_]j@ HII  HHIPUHHdH%(   HEu1Ht1H9   HUdH+%(   u@ UIHH"  dH4%(   HuH֨tfH <w.uzHEdH+%(      HM L1D  HEdH+%(   ubHL L1    HEdH+%(   u:H L1    HEdH+%(   uHL L1"fUIHHH  dH4%(   HuHHtUH@HL
 HtH@ HtH~ ~OL   HEdH+%(   uBAHgK L1@ HEdH+%(   uL      L   rfUIHHH  dH4%(   HuHHteD   A t-HEdH+%(   unAHK LE1l@ HEdH+%(   uAL
 L1HY @HEdH+%(   uLL L1H
 g UHH H  dH%(   HE1Pu%IH  HHt[I  HtoHHUdH+%(   uZ    LHULELEHUHI  H  D  LEH}kHULEHH  fUIIHSH   L   dH%(   H]AB  L`ƅ` LAI  AS  Af  AuUA ufA@  AusM   HW 1MȉLLHUdH+%(   p  H]@ RETRHGRY  A tCON H A@  AtHCAP-READH	HG    fGA   LH dI       1H!I LHLPLXY{LHLPLX    HcL`ǅ`EL  ATX  HA    SYNCHfWAASYNHGNC      HNEITHER G HHGD  HCAP-WRITH
HGGTE  D  UHATSH dH%(   HE1Ft1HUdH+%(     H [A\]ÐI   UH-MH   HSHpXHxh~-} fHnHH   Hfl@x HHfHnH};  H@|    fl   @fHnHK@fHnH~} fHnHHXflfHn@(~} fl@8~} fl@HfHnLfl@hpLHfu*C   qHz~ HF 101 ff.     UHHdH%(   HE1HEdH+%(   u1fff.     UHHdH%(   HEu=1Ht6H     Ht%HyPHtH-H 3H    HUdH+%(   uf.     UHHdH%(   HEu=1Ht6H     Ht%HyHtH-H2H    HUdH+%(   u
f.     UHHdH%(   HEu-1Ht&H      HtH-H)2HHUdH+%(   uf.     UIHHH   dH4%(   HuHHt=HUdH+%(   ucL   L+HL@-1%  HD LfD  HEdH+%(   u&%  L   DAHD L׉1S ff.     UHHdH%(   HEu*1Ht#H     HtHIHHt	1H9Q HUdH+%(   u~ ff.     UHHdH%(   HEu*1Ht#H     HtHIHt	1H9Q HUdH+%(   u ff.     UHHdH%(   HE1uHc  HHHH HHUdH+%(   uf.     UHHdH%(   HEu!1HtH      Ht	1H9Q HUdH+%(   uG    UHAWAVAUATISHH8H  dL,%(   LmAHE  HP`DPhLxHLpPH-v~ HU ~sMb  IW HU  HDUHU=HUDUDf  HUI,   $  A4   IIM+G
       HE1LAH@A 1LELLcLML)J<M/  M&  AF*<F  DMF-Hd
 1L)LMbLMHN,AF+   DHUdH+%(   m  H8[A\A]A^A_]     HEdH+%(   C  H8EDLHL [1A\HC@ A]A^A_]fD  LEA!   LH߹   1HA DULDULcL)J<f.     LJ<+H
 1L)xHI!fD  LE   1LMH@ MLMHN,fD  IN-H 1LM"LcIFLmA4 uII+GHMLJ<+H9@ L)H)1LcM    IA!   eD  UHHdH%(   HE1HEdH+%(   u1-fff.     UHHdH%(   HE1HEdH+%(   u Lff.     UHHdH%(   HE1HEdH+%(   uKff.     UHAVAUAATISH`dL4%(   LuAH3  HX(H&  ~=X} HA	  fHnHe8  fl)}fHnHA)}fHnHA~=!} fHnfl)}fofl)}~=} fl)}   H   H   HphHHXfoUfo]foefHnL   fomfouflǀ       HSfHn@x HflH=hs~ PHH@|    D   D   X`(h8pHHX@hHHJ1HUdH+%(   u0H`[A\A]A^]HUq~ H=    01@ UIHH0H  dH4%(   HuHփPu1L  MtUHEdH+%(   uxH
 L1@ HEdH+%(   uSL L1Hk
 Y     MHuLMH}H}MHuLMIH  y)f     UHAWAVAUIATSHH(H  dL%(   LEAH   Lx L`LDE%  LpH1H; LLcL)J<M   M   AF*<   MMF-Hѻ
 1LUL)LULLcO$I+N   DHUdH+%(     H([A\A]A^A_]fHEdH+%(      H(LHD[L A\1A]H: A^A_]QM   1LUHm; 6LULcO$ofD  LJ<#HT; 1L)HIGfD  IN-H 1LULcIFLEA|$4 u	I$I+D$LLJ<LEH)L)H: 1LELcO$/@ ff.     UHATSHH   dL$%(   LeIuHI$   eHH_HUdH+%(   uHH[A\]ff.     UHATSHH   dL$%(   LeIHI$   HH^HUdH+%(   uHH[A\]Kff.     UHHH dH%(   HMHH  Ht%H  HtID^HHUdH+%(   u^ÐHMH}CHUHMHH  H  HuD  HHUHMHMHUHH  H  UHATISHdH%(   H]HH   H   HtCHtVH-H-]HHuI$   H+   HUdH+%(   u+H[A\] HHtf.        @ UHHH   H   dH%(   HMHH   H   Ht~4 t5Hty4 tH)HUdH+%(   u!fD  HH+A    HH+Vjf.     UHH dH%(   HE1H(   tHEdH+%(   uFf.     H}G]H}HtH(  D  Hq~ Ǉ      H(  UIL
 HHH   dH4%(   HuHHtH@ HtHj~ ~0L   HEdH+%(   u#AH06 L1D  L   Zf.     UILe
 HHH  dH4%(   HuHHt&H@HHtH@ HtHEj~ ~/L   HEdH+%(   u"AH5 L14@ L   fUIHHH  dH4%(   HuHHtUH@L
 HtH@ HtHi~ ~OL   HEdH+%(   uBAH5 L1餿@ HEdH+%(   uL~      L   fUHH dH%(   HE   tHUdH+%(   uR@ G|uL   H}IxLEHMLE苑   Ap,9MA@8T6D9LƉA|    UHHH0L  dL%(   LMII    t@M  I   HteH  H   jYHHUdH+%(       IPIp H}IxLMLELELMHMI   fD  IxIPLMIp HMLELELMHMI   I  H   XUHHH0L  dL%(   LMII    t@M  I   HteH  H   zXHHUdH+%(       IPPIp`H}IxHLMLELELMHMI   fD  IxHIPPLMIp`HMLELELMHMI   I  H   XUHAWAVAUIATS@   HL(  L(  dL$%(   LeIEMtfM   Iw8I~8WHHu!A  HcA$  HcHH)HUdH+%(      H[A\A]A^A_]fD  LXIHt@I(  MuM$(  q    LWIHt0I$(  V L5!l~ Aǅ      M(  D  L=l~ AǄ$      M$(  [ff.     UHH0L   dH%(   HMHc   Ht4HEdH+%(   u{HFH>HP1 MHIH1%ND  O|HuDIxHuLEHUHULEHu   Ax,9LA@8D?D9LωJ|HcvD  UHATSH dH%(   HE1Gt1HUdH+%(     H [A\]ÐH   UIMH   HSHpXHxh~} fHnHH   Hfl@x HHfHnHM$  H@|    fl   @fHnH@fHnH~} fHnHHXflfHn@(~~} fl@8~v} fl@HfHnLfl@hLH6u*C   AHzc~ H/ 101 ff.     UHH0H(  dH%(   HUH(  Ht,HtgHq8Hz8THHUdH+%(       HuHMH}TH}HMHHuHtKH(  HuH(  fD  HHUHuTHuHUHHt0H(  m@ Hh~ Ǉ      H(  fD  Hh~ ǆ      H(  ,fD  UHH0H(  dH%(   HUH(  Ht,HtgHq8Hz8SHHUdH+%(       HuHMH}SH}HMHHuHtKH(  HuH(  fD  HHUHuSHuHUHHt0H(  m@ Hg~ Ǉ      H(  fD  Hg~ ǆ      H(  ,fD  UHATISH H(  H(  dH%(   H]HHtKHtvHq8Hz8QHHuA$  +  HHUdH+%(      H [A\]fD  HMRHMHHtCI$(  HuH(  D  HHUdRHUHHt0H(  f@ Hf~ AǄ$      I$(   Hyf~ ǃ      H(  %ּfD  UHHH   dH%(   HUH   HtdH@ HtSHR HtcHt^H_~ H   H   	HN   HN   PHHUdH+%(   u1@ HHHt1Hz  H	tHHH1@ UHHH  dH%(   HUH  H   HRHHtwHHHH   HB H   HQ H   H   H^~ H   H   	HN   HN   OHHUdH+%(   uLfD  HtHB HH    HtHHHHt1Hy  fD  HH1H	tHHHD  UHSH8dH%(   HE1H   tHEdH+%(      H]ÐH   IH   H   H   H}HHUHHMHUHMHA   A   HHz QH1LUHXH'^~ ZH;8t1:   LUH}gBH}LUHt? u%LUL6LUH= I  +D    fD  UHHdH%(   HEH   H+   uZH   H   Ht\HR HtkHI HtjHteH\~ H   H    HN   HN   MHHUdH+%(   u8@ Ht1Hy      HHH	tHHH!UHHdH%(   HEH   H+   uZH   H   Ht\HR HtkHI HtjHteH\~ H   H    HN   HN   LHHUdH+%(   u8@ Ht1Hy      HHH	tHHHQUHAWAVAUIATSHH(H  dL%(   LEAH   Lx`L`HLDE%  LpPH1H& JLLcL)J<M   M   AF*<   MMF-H
 1LUL)LULLcO$I+N   DHUdH+%(     H([A\A]A^A_]fHEdH+%(      H(LHD[Lo A\1A]H% A^A_]遰M   1LUH& fLULcO$ofD  LJ<#H& 1L)8HIGfD  IN-Hԅ 1LULcIFLEA|$4 u	I$I+D$LLJ<LEH)L)H& 1ԯLELcO$_@ ff.     UHHH  dH%(   HUH  H   H   HHHBHtZH@ HtiHQ HtoHtjH,Y~ H   H   	HN   HN   JHHUdH+%(   u=fHt1Hy      HH͸   H	tHHHr1 ff.     UHHH  dH%(   HUH  H   H   HHHHBHHtZH@ HtiHQ HtoHtjH<X~ H   H   	HN   HN   IHHUdH+%(   u=fHt1Hy      HH͸   H	tHHH肴1 ff.     UHH H  dH%(   HMH  H   H   HAHrH   H@ H   LF H   M   L<W~ HUH   I   HMAIN   HN   HHMHUHHuHBH+AHUdH+%(   uF@ HtH~  t׸   D  HHHtHL	tIHH[ff.     UHH H  dH%(   HMH  H   H   HAHHrHH   H@ H   LF H   M   LV~ HUH   I   HMAIN   HN   FHMHUHHuHBXH+AXHUdH+%(   uF@ HtH~  t׸   D  HHHtHL	tIHH;ff.     UHAWAVAUATISHH8MH   D%  L   L   dH%(   HE1HU~ HU !  MtLM~ MtCLDU7HUDUDAf  IШt$ t A~4 uIIM+F@ IA!   LH߹   1H! DU躪LDULcL)J<;AH!  1薪LLcML)J<M}   MtxAE*<   MME-HN
 1LML)LLMHN4AE+   DHUdH+%(      H8[A\A]A^A_]fHE1LZfLE   1LMH  LMHN4f     IM-H| 1LM躩LcIELEA~4 uII+FHMLJ<H L)LEH)1~LELcO47fD  LJ<3H~
 1L)PHIUHAWAVAUATSH(dH%(   HEH  HVLpHLhPIԉMHPXHR~ H%   HUM~^M   M~ M   LLEDAf         A~4    MM+F   f     HE1LMH 1eLLcML)J<;M   M   AE*<   MME-H
 1L)HN48AE+   DHUdH+%(      H([A\A]A^A_]D  IA!   LH߹   1H 辧LLcL)J<;5@ LE   H 1葧HN48|fD  IM-H,} 1nLcIEMA~4 uII+FHMLJ<;H L)H)17LcO49! LJ<3H>
 1L)HI衭UHAWAVAUATSH(dH%(   HEH  HOTLpLhIԉMHPHP~ H%   HUM~^M   M~ M   L蠭LEDAf         A~4    MM+F   f     HE1LMH 1%LLcML)J<;M   M   AE*<   MME-Hٛ
 1L)ۥHN48AE+   DHUdH+%(      H([A\A]A^A_]D  IA!   LH߹   1H ~LLcL)J<;5@ LE   H 1QHN48|fD  IM-Hz 1.LcIEMA~4 uII+FHMLJ<;HF L)H)1LcO49! LJ<3H
 1L)ФHIaUHAWAVAUATSHHH  dH%(   HE1%  EHRLsHM  IF Hx  H   HEHwQ~ MIIH}D8HC`HEYEH}HH HEHH#EHE   0  M0  AF,  EL{PEHM~   I^ H[  HHUDf  IШ  LL   1H 蘣LHcH)I<MH 1zLLcIL)K<M   M   AG*<   MMG-H.
 1LML),HcH]AG+  HUdH+%(     HH[A\A]A^A_]fD  HR~ HEMHL~ .  LLX   1H6 譢LLcL)K<LE   1LMH 腢HcH]_f     IO-Hx 1LMZLcIGLEA~4 uI+FIHMLK<Hq L)LEH)1HcH]fAF0	HEx    8   EEHK~ L{P LL18  A~4 IIM+FfD  L{PLEEX   A!   fD  LEA!   f     LI<Hv
 1H)HHH$fD  HK~ L{PEs   D E:ED  pD}s   AEǉE萧UHAWAVAUATISHH8H  dL,%(   LmAHE  HP DP(LxLpH}J~ HU ~sMb  IW HU  HDUHU荧HUDUDf  HUI,   $  A4   IIM+G
       HE1LAH 1LELLcLML)J<M/  M&  AF*<F  DMF-H
 1L)LM貟LMHN,AF+   DHUdH+%(   m  H8[A\A]A^A_]     HEdH+%(   C  H8EDLHLi^ [1A\H A]A^A_].fD  LEA!   LH߹   1HT DULDULcL)J<f.     LJ<+H
 1L)ȞHI!fD  LE   1LMH 蝞LMHN,fD  IN-H4t 1LMrLcIFLmA4 uII+GHMLJ<+H L)H)1:LcM    IA!   赤D  UHHH dH%(   HMHHttHtoH9   G+tHHz-Hq-HUHM8HMHUuwHrHyH9q r1H9z s;H9tLHH).@ A+uHwHyH9t- 1H	tHHHHUdH+%(   u#D  HA H+B fD  H@ 1ϣ@ ff.     UHH H   dH%(   HMHH   H  H  p0u|H   H   H   H@ HtLF H   M   LF~ HUH   I   HMAIN   HN   R7HUHMHHu/HEdH+%(   uyH   Ht@ HtHHUdH+%(   uJ H    H   H+   fHtH~  t   L	tIHHvfD  UHHH  dH%(   HUH  Ht\Ht_HzHpHtHEdH+%(   uJD  HuH@H+Bff.     HUdH+%(   u    HH   ԡ@ UHHH  dH%(   HUH  Ht\Ht_HzPHpPHtHEdH+%(   uJD  HuH@XH+BXff.     HUdH+%(   u    HH   4@ UHATSHH H   dL$%(   LeIH   H  H  H0uyI$   H   H   H@ H   HI H   H   LC~ HUH   H   AHN   HN   4HUHHu$I$   HHuH   I+$   HUdH+%(   umH [A\]@ I$    #I$   H+   HtHy  t   D  HHH	mHHH˟ff.     UHHdH%(   HE1HEdH+%(   uH   H   H   vfD  UHH dH%(   HE1H   tHEdH+%(   u"f.     H}GH}H  D  UHHH dH%(   HMHH  Ht%H  HtI3HHUdH+%(   u^ÐHMH}HUHMHH  H  HuD  HHUHMHMHUHH  H  `UHHH dH%(   HMHH  Ht%H  HtId2HHUdH+%(   u^ÐHMH}#HUHMHH  H  HuD  HHUHMHMHUHH  H  谝UHHdH%(   HE1HEdH+%(   uɸ    zf.     UHHdH%(   HEHH9GHUdH+%(   u3 UHAVSHHdL4%(   LuIuHEdH+%(   uCH[A^]D  H;HUdH+%(   uH   Lp8H[A^]讜 ff.     UHAVSHHdL4%(   LuIYt5H   H@0Ht%HUdH+%(   u.HL[A^]f     HEdH+%(   u	H[A^]# UHATSHHdL$%(   LeIٶu1HUdH+%(   u,H[A\] L谶tI$   H9   賛 UHSHdH%(   H]HntH@~ H9   HUdH+%(   uH]_@ ff.     UHSHdH%(   H]HtHS@~ H9   HUdH+%(   uH]@ ff.     UHSHdH%(   H]H讵tH+>~ H9   HUdH+%(   uH]蟚@ ff.     UHSHdH%(   H]HNtH+>~ H9   HUdH+%(   uH]?@ ff.     UHSHdH%(   H]HtHK=~ H9   HUdH+%(   uH]ߙ@ ff.     UHSHdH%(   H]H莴tH;A~ H9   HUdH+%(   uH]@ ff.     UHSHdH%(   H]H.tH?~ H9   HUdH+%(   uH]@ ff.     UHSHdH%(   H]HγtHA~ H9   HUdH+%(   uH]还@ ff.     UHAWAVAUATSHH  dL<%(   L}IHH9   IAHZA     H8t.H   H@(HtLDLЉ1EAI	ЅDIHCXHXI9  uHEdH+%(   uHD[A\A]A^A_]@ A UH  HHdH%(   HE1H9   HUdH+%(   u螗 ff.     UHHdH%(   HEHH9G0HUdH+%(   uS UHATSHHdL$%(   LeIu1HUdH+%(   u,H[A\] LtI$   H9    UHAWIAVAUATSHdH%(   H]Hsu'HEdH+%(      H[A\A]A^A_]D  A    uL  M   M   MmLIfD  t;Lc    LkLLLHHuՅnLEIKD4H)A   H9JA   >D  H@H  IHfÕ UHSHdH%(   H]H~tJ   H=HHXHPhfHnfHnflflHX@hHUdH+%(   u;H]fD  Ht   HD     Hff.     UHH dH%(   HEH @tHHTtHH8Bt1HEdH+%(   u|ɉfD  Hz   HUNHtHHXHUHǀ       fHnHHhH=W9~ fHnHCflHHPflHX@hB   ,s9f     UHAWIAVAUATSH   HMH}HUDEdH<%(   H}H= ,(H HMY  H}L(  L%	 1MMu MD  LLLH薭&  H[LH= M<'  H[IH2H   H=u HuHp'HuHp1  H=3 e'H[  I4H}L'ugH[H}MdI$H=
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 AIA:LL%g~ E1MHIu HL誥  AI AuH} ]  Hb3~ L@EIH;  .   HIH    LpM/   LgHt"  LxH5G L\E  H5
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 L@@ HA(~ H  H1DMHI
 L@e@ H(~ 1H   HdfH'~ 1H   HFH    UHAWAVIAUATE1SH(H}HUdL<%(   L}L=I~ MLIu LH菙ÅuiH5
 L   AUtHS)~ 8u>IMAG   HEdH+%(     H([A\A]A^A_]    AI AhHEL-~ 1MMM<$M   LLLHј   HEdH+%(     H[It UH}H([A\A]A^A_]ӥ H=y     HEI   D H   HHXD   H}HfHnHHhfHnHflHHPflHX@hAG   D  I"L%Q~ 1MM} Mt]LLLH͗uCH'~ 8   HEdH+%(      H[I4f     ;IuL-~ 1MM'MtJLLLHPu0H5'~ 8u:HEdH+%(   uHkIt t}Iuff.     UHHdH%(   HEH~ H0  f          H0@    H9uHS~ H  fD  ff.     ff.          H`@    @    H9u~     ~     ~     ~     ~     ~     ~     +~     9~     G~     U~     c~     q~     ~     ~     ~     	~     ~     %~     3~     A~     O~     ]~     k~     y~     ~     ~     HEdH+%(   u?{@ ff.     UHHdH%(   HE1Ht?+HUdH+%(   uz@ UHAWAVAUATSH   HPH`dL$%(   LeL%.~ I<$H  4I<$    &  Ho~ LGH=#~ H H}HEH!~ HEHW!~ HEH~ HEH!$~ HEHP t-HPHH9uf.     H H9  xtH#~  HLŐ1H{
    H}
  H}I<$H  IHh
  L=~ I?@u<H#~ 8t0H5
 LL%j!~ A|$+   HN  D  ƅn LE1E1ƅo ǅh    ǅx   LHL@    H5
 HIHtYoD xAE <{  <}!oIEAE  Hp; u$DxHp@ ;    HpHH=
   HH=
 "  L=[~ LXM0  ff.     IM9  M/MtHsLHH5uLXDhEƅn H=~ H`HHPAă  \  M
 ff.     HHL@E-  H%!~ H~ H9t2H`HPAH5I
 H=g~ jAą   :HS!~ 8tzIH  HeHxH  H轗Hx<H ?   HUH5L E    pIHy  L5~ *   HUH5K 1=IHa  HULLuAăuH=
 L1詆HxAHEdH+%(   7  HĘ   D[A\A]A^A_]    ƅoc@ HL=~~ L-~ bID  I M9Iu LHuLXn   h1D;xAȉxfH`脫H=_t
 HI	tLH=Ev
 	mH5
 H	H5
 H	?@ H`H=s
 HI	tLH=u
 o	H5/
 HX	H5
 HA	r@ DhEƅnHu  H5h
 L2H  A|$ =H5
 LH  H5
 LHH}MH
    H
 .	  L~LmMH Hs~ 101訹AD  L=~ I?虔MH~ H=~ H H}HEH~ HEH~ HEHS~ HEH~ HEHP t$HPHH9uH H9  xtHw~  H|ŐHxL5P~ HPLHvAąLcLHL`AH~     H~ x H
 HDHH=
 1HxNLHOu"HH5B
 HH豌  HH=0
 1訂LLHH='
 H1胂LAHxELH=;
 1EHxYH5oe
 LHL5
 H]A|$*   1MHA
 L   HyHE    LLmA|$ nA|$* a  MbH5
 LHMH
 LH߾   AHE    H}MH
    Hƚ
 L   LmYMO1H}M   HUd
 H
 yHE    LLmA|$ M      H~     H~ x H`
 HEH=I 蜀LL1MHc
 LH߾   (xHULHxqHxHH5
 HLxHA|$ A|$* WH5c
 L[H?MHH
 LH߾   y1HELLmH}MH
    H
 ^yHE    LLmM'H=
 lH MH8oHq~ Hb 101蟴H;  ff.     UfHHdH%(   HE1H~ @$H~ H     H9~ H     HEdH+%(   uH=~ n@ UHAWL=~ AVIAUATSH8udH<%(   H}L,  H}X(LpLH}M  H*2     LH5
 H}1|L3\I M9t.M/MtJ~ɺ   H5
 H}   ϟD  L=~ M0  2     LH5"
 H}1|L\IM9t.M/MtJ~ɺ   H5
 H}   _D  }   EumL-~~ M  /D  LH5
 H}1|LC\IM9t.Mu MtJ~Ⱥ   H5
 H}   ޞ@ 1H}͖H}HHEdH+%(   uyH8H[A\A]A^A_]L5~ M  .LH5
 H}1k{L\IM9M.MtJ~ź   H5c
 H}   ;4lf.     f.     UHHdH%(   HE1HEdH+%(   u1kfff.     UHHdH%(   HE1HEdH+%(   ukff.     UHHdH%(   HE1HEdH+%(   uHP  鉠dk@ UHAWAVAUATSHH(udL,%(   LmL   M  L%~ A|$ !  1E1AU IH'  J   HHHfD(  A|$   I   I   I   Ht#Q(fD  rq(9t
BvI   I        AI  H  H  o oB@oB @ oB0@0oB@@@oBP@PoB`@`oBp@po      o      M  I>II  HOHt$Q(    rq(9t
BvHOM  I~@\IF@I  HOHHt Q( rq(9t
BvHOHI   tH  ޺I  H  fA(   t_A|$ tWI`  fIǇX      I`  Ih  Ip  Ip  Ix  IǇ      IǇP      A  I  HtA  |I  H  I  Ht!H~ H;8t迷I  Hq  Ic$@  t   ɨI   H?  IG0I   fHnflAG0
fI   A0  A@  A|$    HEdH+%(   }  H(L[A\A]A^A_]       A   AU IHE1     P   膩I   H  AoG@ AoGP@AoG`@ AoGp@0Ao   @@} fAG@AGPAG`AGpA   q AƇ$   Hɩ~ H   II  ~I  rI  Ht!I  Hx@I  EI  HtIǇ      I   轴I   LE1AU~I  Huf@ ff.     UHSHdH%(   H]HH(HC(    H{0詛H{8蠛HC    HEdH+%(   uH]1fff.     UHSHdH%(   H]HHZHtHC(1HUdH+%(   uH]øe ff.     UHSH(dL%(   LELG0M   W19 HEdH+%(      H]D  H>HULE>vHcULEHHIIx@LEH{HLEIHHHtQ(rq(9t
BvHKI@P   HCI@XHC Zf.     1Id@ UHATSHLgdH%(   H]HLoHt2C    I$   HHC01HUdH+%(   uH[A\]øRdfUHSHdH%(   H]H>pHtGHPH@    HP H H<   ɥHt"C    HC81HUdH+%(   uH]øcfD  UHAVSHHdL4%(   LuIoHt<HH9Ht3Hp Ht*HEdH+%(   u5SPHL[A^]    HEdH+%(   uH1[A^]Icf     UHAWAAVAUATISHL  H
~ dL4%(   LuIփ2       H    )  I$  HHXH9u    D  HCXHXI9$     HAքtA$&  Dr9Mt4Df.     fA!&  M  Muff.     HEdH+%(      H[A\A]A^A_]fD    HP  9D     DA$&  MthfA#&  	fA$&   H    uD  H    ]H    H(   <@ 	fA$&  (a UHHdH%(   HE1HEdH+%(   u1Mafff.     UHAWAVE1AUATSH(dH%(   HE1f&   Af&  IM   HGH_H9}   IILxtZH  HELLLAW8HuMIGhLxH9tCLiatHuL蹖u IGhLxH9tLLLAW8HtIHEdH+%(   uH(L[A\A]A^A_]H`     UHAUATSHdH%(   HE1HtIIII] D  Ht%I$  1LHHx9t?H[HuL.IHuHEdH+%(   uiH[A\A]]@ H[fID$8IL$0HS0fHnIT$8H0  fHnflC0HI$8  4L輣IHGY_f     UHHdH%(   HE1HEdH+%(   u1_fff.     UHHdH%(   HE1HEdH+%(   u1^fff.     UHAWAVE1AUATSH(dH%(   HE1f&   Af&  IMusHGH_H9tfH  IILxHM#@ LLLAW@Hu6IGhLxH9t,Ax uL^tHuLJu@ IHEdH+%(   uH(L[A\A]A^A_]]    UHAWE1AVAUATSH(dH%(   HE1f&   Af&  IMukHGLgI9t^H  IIHXHM"@ LLHS0Hu/HChHXI9t%H"^tHuHru@ IHEdH+%(   uH(L[A\A]A^A_]]@ ff.     UfHAWAVIAUATSH8L?dL$%(   LeI)EM  HA   D  HCHHt6II$  IWLH  HHHCHE1HuI|$fM|$AD$ H;E   LA$$   upfA$&   udI$H  HEM$@  HEHt9HqII;$H  ttLHiH}HsMtLffoEA$@  HEdH+%(   uHH8[A\A]A^A_]@ I|$AD$ ID$    I>I~;HI$H  w[fD  UHHH H   dH%(   HUHHtH   HtH;F tf&  HAxHtH;   tf&  H   Ht*H   Ht}H-HUHMlHMHUHt_x  x;  u=Hc  H   HHHH Hs	f&   HEdH+%(   uÐf&  @fD  f&  ZUHHdH%(   HE1w   HUdH+%(   uEZD  UHHdH%(   HE1fw   HEdH+%(   uZD  UHAUAATISHdH%(   H]؉%f9r 1HUdH+%(   u$H[A\A]]@ DLd   YfD  UHATS1HdL$%(   LeI@ ff.     1Ld:uHEdH+%(   u	H[A\]/Y@ ff.     UHAWAVATSH dH%(   HE1H   t$HEdH+%(   M  H [A\A^A_]@ H   HIH  H} P(9BHN1L5n ~ I$   葔   HAΟ  I$   HtHx 0   H蠟I$  HtP(   H肟I$  H  H@Hd  H=} P(Hߋ1B   N<I$  H@Hx    HI$  H@PH  H} P(   Hߋ	BNڞI$  H@HHx E   H赞I$  H   Htl$   H茞I$  H   HtC%   HcI$  Hb  H@PH%  H(   HߍQM+MȾ    HߍQI$  H@H  P(!   H߃I$  H@HHD  Hx K   H軝      H詝      H藝      H腝      Hs   	   Ha   
   HO      H=      H+      H      H'      H      H      Hќ
   *   H远   +   H譜   ,   H蛜   -   H艜   .   Hw   1   He	   7   HS   8   HA   9   H/A> 5        HHߺ      I$  Ht3迮HEH} H8謮HUȾ   HH9HBI$  Ht   H蟛I$       I$  HtN&   HnI$   H	I$   HuH8艴HuH     HtHx HEdH+%(     H H߾   [A\A^A_]          Hޚf     AW   H^    "   H蛚fD     HsfI    I~H I          H0^    !   H&8Hߺ             H          Hޙ!   Hߺ   ̙   H~fI    I~H I          Hl]    1   d   HG~fM  H} IH    GHxH <H    .      H\D        H/   Hߺ   ܘ   H}fI    I~H I          H|\p          Hn0   Hߺ   \   H?}fI    I~H wI    i      H[R    L5y} P@ ff.     UfHAWAVAUATSH8HuHMLEDMdH%(   HE1HZHH  IHI~HHEL0MK  A    II  IVLH  #IVHIVE1HHuIfMwAW H:E  HueI  HPHLbH9u&8 LLI  IT$hHH9tLbIT$HuIT$hH9uH} tH}   nIEHfA&      A$      } t)HW} x   HUIP  I0  HP HHEdH+%(     H8[A\A]A^A_]fIfIG    AG H8HEHx IEPLLnA$   ^DMLEI@  I0  HuLefH9} z uCIW@@^d HxTfH*Yxd f/s"H,HM@ I   H@ \H,H?HMHփfHH	H*XMf     UHH&  dH%(   HE!Hp} f&  x    H  H   @ ff.     HV@HP@HVPHPPHVXHPXHV`HP`HVhHPhHVpHPpHVxHPxH   H         HVHHPHf!&  uMƀ5   ƀ7   ǀ0      H  Hu&  ft9HEdH+%(   u~     H  H@&         Ɔ5   Ɔ7   ǆ0         HGPHF@H   HFHH   HEdH+%(   ul7L    UHAVE1AUIATSHH_0dL$%(   LeA^HuG    H8HHt0AE9~'f   uHsLlH	HHuѐHEdH+%(   uH[A\A]A^]K@ ff.     UHATSHH0dH%(   HE1Ht)A1f蛏HHtA9uHGD  1HUdH+%(   u	H[A\]KUAHAWIAVAUE1ATISH(dL4%(   LuIHt+LnMt"AU( JAM(9t
BvI_DMVIDMMHIW H[Å   IG@LLÅ   IG@LLPÅ   I t*IGHHt!L   LLЉÅu[ff.     IG@LLPtwIG@LLPÅu,I tIGHHtL1LLЉÅtf     IG@LLP L蛀HEdH+%(   u%H([A\A]A^A_] IG@LLP IfUHAUATSH(HH} L   dH%(   H]Hx   H   +ZH   Hǃ       $L  Mt5LI}@I   [I   [H  C~H  Ht,ҖH  Hx@H  Hǃ      H  Ht]H  Ht6W(t#fD  J9rO(9  uHǃ      H   }H   }H  TZH  Ht8 u[HP  H  k}H  _}H   S}HEdH+%(      ID$H(H[A\A]]@ H  }f.     H@  蔨Ht<LhI}Ht"LHEHELhI}HuLHǃ@       s9Gf     U   HAWAVAUATSH(dL4%(   LuLv@Mu$HUdH+%(     H([A\A]A^A_]f   LnHIHJ    L)HHF@    )HVp   H    H)HVxHHFpH    H)H   HHFxH    H)HH   J    L)HHFHH&} x k  HP  萝A$  1*   ff.     L   HHHIMJ    L)HIL   IMHJ    L)HIPL   IMHJ    L)HIPL   IMHJ    L)HIPL   IMH J    L)HIP L   IMH(J    L)HIP(L   IMH0J    L)HIP0H   L@8J    L)HHP8A9$  !   u,HCHHS@L)L)I$   I$   f&      $      LH  M   LMwMLLIUtI   H/  H0  H@  HEL;v;  L讍HEL;h>  HuL蔍Il$HfA   uIl$PLe[Mjff.     1H{@ H{H I$   I$   H   H8H    H)xHHH    )Hx0PHH    H)Hx8HHP0H    H)Hx@HHP8H    H)HxHHP@H    H)HHPI$  It$8@$uIt$ ID$(HELHu_HuHFLJHMHAB     UHAWAVAUATISHHXoV@Lw MHUfoM.fsdH%(   HE1E)U)])UMu)\  @ ILqxE LqIH;  II  LLH  WHu}   H} x tI   @Ho fE I$  WI$  Ht'W(D  J9rO(9  uIǄ$      H  @,txI   I$   H9tdI   HtHrHuI   I   ZxI$   Ht%Q(     rq(9t
BvI   M} b  H} x tGHEI   @)<  j  <  <u~BfEfB@ ff.          M$  I    <  E1~dD  H  I   B<iI   L~MHHIH~ffH  ~ffD9  HEdH+%(   4  HXL[A\A]A^A_]@ uLIH  }   fHCHM/AGM>Hs } tL~L茋} HE@)<j    <t(<A~GXfEfAGXff.     A~GPfEfAGPFf.     ~BfEfB|@ ID$@IE@ID$PIEPID$XIEXID$`IE`ID$hIEhID$pIEpID$xIExI$   I   A$   A   ID$HIEHfA(   H} x I  ~u~m~BXffBXI  ~BhffBhfA&   ^I  ~B`ffB`I  ~BpffBp/f(   LH+} x ;I  ~m~}~@Xff@XI  ~@hff@hfA&   I  ~@`ff@`I  ~@pff@p    <A~GhfEfAGhvf.     <~B(fEfB(@ Hc@   }I   HtM  @ A~G`fEfAG`f~B fEfB LQOGLbTE1=D  UIJ   HH`  odH%(   HE1HHHFHULHHLpHP)@HUdH+%(   u<    UHAWIAVAUATSHH  EH8H>LuL@LHLe HXldH%(   HE1H`KJ   A~F0HpIHH`AG8HPA~AOHA   I?)A~F8)ǅ   fHnA   fl)A~GAH) _MHPLHH0L@H8)  IExH8A~   A   L-} HA   A~W A~NxAV@AN8fHnA   I   H(IN)@fHnAG4)Pfl)`AG))pA~G,A8  fpህAG(fօA"EfAG*fIGHHXH0HtH1HH)I   H8LHlLeH`AF\H@LHHǅP    LXhIĀt   uMHtf(   tƃt  A@  u<HEdH+%(      HĨ  L[A\A]A^A_]@ HtA@  tA$  9l1Af     D9r1IFHcHI$   HAFXBAFBmf     Hǅ8    f@ BA$  9fD  UIHHLMHSHLMLUdH%(   HEE H]dH+%(   uL] H]ELU%8UHHdH%(   HE1Ej PuHUdH+%(   u`8UHSHdL%(   LELG(MtYHHG   HKH  HA8HHDE1HA0HS jQ1ZYHt"HC1HUdH+%(   uH]ø7UHSHHcGLO0dH%(   H]HHHLɀP tHHAHt_HAPHtVLCHCI@0   A   H      HDE1I@8HS jAPE1IZYHt$SHC1SHUdH+%(   uH]ø7fU1E1E1HSHHW HGdH%(   H]HjH  sҡZYHtHC1HUdH+%(   uH]ø6@ UHAWAVIAUATSHH  HOLdH%(   HE1Lo8~FHpH8J   ~NHH>)) ZH8H0IF HPAF,IFHHC H(I  H@H0H   H`A\hAH  o H@)@H  o@r,)PHP H`HH HPH)@HHHIPHHH HP{   E1       ID9{   Kt HpH  H  HuHC    1HUdH+%(   
  He[A\A]A^A_]fH   H9PuH  HpH  HtID9{~7Kt H H   H	tH [HuKt     HS j 1E18H0E1LMZYHtUHcSHCJKID f(   H} z H8H@HP  HS0f3fUHAWAVAUATSH(dH%(   H]H_0H   I@ ImPLJMtkLHLcwIH   HtpH0  L@  L;ft|L|I;_   LH|ImHf   tLpJMuHEdH+%(   umH([A\A]A^A_]D  I  Iu8@$uIu M}(L;fuLHuwHuLHF|I;_pfHvIG]2f.     UHAWAVAUL  ATSHdH%(   H]HLLH  Ht5L  LvLLH  {LwIH  HuH  L  Ht=     L  LAvLLH  ?{L'IH  HuH  L  Ht=     L   LuLLH   zLHH  HuH`  fHh  HH  fL+L9   IEMeMu I9tu@ ff.     HxH LxD  HW`HPH@LIGXHWXLxL9uIU IELMHBHII9tIIEMeI9uLD  HEdH+%(   uH[A\A]A^A_]0fff.     UHAWAVAUATSH8UdH%(   H]H_0H   I@/  } u"D      Il$PLGMt}LHLkntIH   H  H0  L@  L;n  LKyI;_  LH6yIl$Hf   tLGMuf     HEdH+%(     H8[A\A]A^A_]fD  H0  H@  L;v   LHUxHUL;j   HLxIl$HfA   uIl$PL|FHsHLsIIasHÀ} t
A  .uLLtI   HWI$  It$8H$tSIT$(L;vLLHUHurHuHUHF+ LHUrHUHB)    It$ IT$(@ H0  H@  L;v   LHUwHUL;jF  HLwIl$HfA   uIl$PL\EHSHILsIArHA  .tLLtI   H]I$  It$8P$   IT$(L;vNLHUHuqHuHUHF-D  I$  It$8@$uIt$ M|$(L;n]LHuqHuLHFvI;_If.     HhqIG.    It$ IT$(Qf     LHU4qHUHB,fUHH dH%(   HEHH  HxXH9  tMHHuPMHu9|HEdH+%(   uOɉD  LH~Hc)IH)LH~HUdH+%(   uɉH1LW
 H̩
 LZ%,D  UHAUATSHdH%(   H]HHǠ   (Lk HSH   IEH9HBHC ЉHEdH+%(   uHL[A\A]]+ ff.     UHAWAVAUATSHhHpdH%(   HEH  DP$Eu'1HUdH+%(   
  Hh[A\A]A^A_] HGH    H}_HL`IMtHMLEMHA8Hxfff.     H}  EċEĉEuL2oHEHEL;p	  HuL$tH} Lx@L}  HE   L`8Mu]      IGI1Ht9II$     LLH  HtRM?yIGIHuHEfH@HM&AFM7  HxLuH}L  IF@ID$@IFPID$PIFXID$XIF`ID$`IFhID$hIFpID$pIFxID$xI   I$   A   A$   IFHID$HHs} x   HE1ҋ  Hƅ   fI$   HI   HHHH<H9I$   I   HH|HyI$   I   HH|HyI$   I   HH|HyI$   I   HH| Hy I$   I   HH|(Hy(I$   I   HH|0Hy0I$   I   HHD8HA89  fA(   tHQ} x O  L?HpHt   HGH} Lu2fH@HI    AFLp8HELp@@ HUL  H  H]I9tEMHE    @ ff.     EOPE  AT   HEI_L(M  De!D  IMxIME1HH  I1LLH,HuHuIF@IE@IFPIEPIFXIEXIF`IE`IFhIEhIFpIEpIFxIExI   I   A   A   IFHIEHD  E   1D  I   HI   HHHH<H9I   I   HH|HyI   I   HH|HyI   I   HH|HyI   I   HH| Hy I   I   HH|(Hy(I   I   HH|0Hy0I   I   HHD8HA89  LmLUH0  H]!  BEM?L;}HMHiƁ$  f(   TH} x CHM1IH  HݎHMLIP  HP  ?L   De   LHMIH|  HEHMH@HHEI$  I$  H} H      IGH9  HMHX@ HHZ  HMA$&  u1HUHt(     f&  H  Huff.     H} 1LHMKH}    L7H }    L#I$  LIG IW HMHUH9HX   HM0Iǆ      H}'tXIǆ      HChH9EtYHXH~  Iǆ      H]uIǄ$      H%'uIǄ$      HChH9EuHMHEHc  "  @   HMcI$   HH  LEHMA     1    I$   I   HHHH<H<I   H|I$   H|I   H|I$   H|I   H|I$   H|I   H| I$   H| I   H|(I$   H|(I   H|0I$   H|0I   H|8I$   H|8A9  "fM,$AL$L!} tHEL`HuLmLeL7 H HHCXHXI9$  "HMH} 1  HE&  fA	$&  G    H"IǄ$          L fHUHB I   I$   H2H0HrHpHrHpHr Hp Hr(Hp(Hr0Hp0Hr8Hp8Hr@Hp@rHpHHRHPH    )H(       #-IHHOI$P  LIP  H;LA-8EufA$&  #L8LHEEFL7L7 ff.     UfHHdH%(   HE1GH      HEdH+%(   u9 f     UHHdH%(   HE1f&   uHGPHF@H   HFHH   HGHHF@H   HFHH   HEdH+%(   u@ ff.     UHAWIAVAUATSHXHMHq} HuUy LEH} A^5 dH%(   HEHG`HDGXH  fH*Yf/5   H,HEL胞L{wH} x 	  I  @$  IG HHfAG(H  IG(HMHEL} ff.     H}cIH} tHuH}U  LuLe} t-H} HUx  H} IP  I0  Q HELh(MF  H]A   fHCHHt5II  IULH  FHHHCHE1HuI~fMnAF H;E   HuiH} HPHXLzH9u-fD  LLIGhH9tLxIGHuIGhH9uH}L%fA&      HEHt   H<MHEdH+%(     HX[A\A]A^A_]D  \x3 H,H?HEIG8@ I~fIF    AF Hx(HEHx0fMtL#aLeI    H}L=9    H} x usIF@Hȿ} A^2 HxbfH*Yf/2 s(H,HfHH	H*X\2 H,H?I   H HfHH	H*XDMLEIO(LHuIW8dfIG0A   A   ff.     H`HH_HS(I   HS0I   f   uHS(I   HS0I   Hug    UHAWAVAUATSH8HuHUdH%(   HE1H   HIf     Mg0IG0I9tsMt$M9u   @ MF0MpM9   I9  uA$   u"I8  I0  LHc   L_IHu1    HEL0M  A         IVxIVE1HHt{II  1LLHuHEIv0fHnI  IF8Mf8fHnflA$L 7D  HUdH+%(      H8[A\A]A^A_]Ð   LHUHtHUfL0I@HEuyHuHHE`eHEfHƀ#  HH  H@HPH`Hp   $   LHEHMfH     @HHMIHAw2fUIHHH} dL%(   LEIPHtu-HMdH+%(   uB
PH  L(     HuG( u8       UHHdH%(   HE1HEdH+%(   u
11$g    UHHdH%(   HE1HEdH+%(   uH} E11Ppff.     UHHdH%(   HE1HEdH+%(   uH} HE1Pf.     UHHdH%(   HEH   uHx耿5   uHUdH+%(   u"D  H@   Hx耸   tX     UHSH(dH%(   HE1   ut   u]tXH}_[H}HHu%H_D  H{?[Hu:H  HuHEdH+%(   u$HH]fD  H0      HfD  UfHAWAVAUAATSHH8dL4%(   LuIHGP    Ǉ       HǇ       HǇ       )EnLc0Mu9  fD  W  It$DHWL   'IMt^LDI|$R?yD   fLAL$(   fA	$  AL$8AL$HAL$XAL$h\'IMuHC0f      H   D  IHYIT$(H   IT$0H   fA$   uIT$(H   IT$0H   HuLc0M   HEL{(HE*f     LLe^H}It$MtbML7YIL;c0uL&YHC0DL   fA	$  e&ID  f      fD  foEC(HEdH+%(   uH8[A\A]A^A_]d@ UHSHdH%(   H]HJHu)H   HPHHEHUdH+%(   u$H]fHUdH+%(   uH]H@ ff.     UHATSHH} dL$%(   LeIx t4HEdH+%(      IT$xHL   [A\]    AǄ$       LID$P    IǄ$       IǄ$       kI\$0Hu9HEdH+%(   uOH[A\]     f  H`WHHtID$xHt	H;   uHs   L$fff.     UHATSHH} dL$%(   LeIx t4HEdH+%(      I$   HL1[A\]    AǄ$       LID$P    IǄ$       IǄ$       jI\$0HuKHEdH+%(   uXH[A\]     H   HtH;B t%f  H>VHHtI$   HuHs1L@ UHATSHH} dL$%(   LeIx t4HEdH+%(      I$   HL   [A\]@ AǄ$       LID$P    IǄ$       IǄ$       iI\$0HuPHEdH+%(   ucH[A\]     H-gmHt:Hs   L!H)UHHtI$   HtH   Huf  f     UHATSHHj} dL$%(   LeIx t4HEdH+%(      HI$x  L   [A\]@ AǄ$       LID$P    IǄ$       IǄ$       khI\$0HuAHEdH+%(   uPH[A\]     ;   t$f  @HTHHtA$x  yHs   Lff.     UHATSHHZ} dL$%(   LeIx t4HEdH+%(      I$   HL   [A\]@ AǄ$       LID$P    IǄ$       IǄ$       [gI\$0HuBHEdH+%(   u`H[A\]     Hs   LHSHHtHc   I$   HHHH Hsf   |ff.     UHHdH%(   HE1G8D8HEdH+%(   u4@ UHHdH%(   HE1   HEdH+%(   u     UHHdH%(   HE1   @u   HEdH+%(   uff.     UHATSHLgdH%(   H]HMtcHC1fA$&   @H  >HsLLAH{(pHC(    HC    HEdH+%(   uHD[A\]A     UHAVAUATSHLodL4%(   LuI~AE1KIHI^0HZH{@ZH   H   E9&IFHt1f&   I  @=I~0AAIF    A9FHUdH+%(   uH[A\A]A^]. ff.     UHAVSHdH%(   H]H_HtSHG    HG1f&   Lw@H  =HEdH+%(   u4HLH[A^]鯦    HEdH+%(   uH1[A^]f     U1E1E1HAWAVAUATSHLHGdH%(   H]HHW Lw8jAWL  L@vZYHtrIHCHcCLLPSM$	HtHPH@    HP 1LfA$&   @<1HUdH+%(   uHe[A\A]A^A_]ø
ff.     UHHdH%(   HE1   HEdH+%(   ui
f     UHHdH%(   HE1   HEdH+%(   u)
f     UHAUATSHH} dL,%(   LmIx   H  P$   H LgMtr@ ff.     I  @$   I]8f.     Ht.H     LHH  =HxHtVH[HuLMIHuHEdH+%(      H[A\A]]H8^fD  H[f.     ID$8IL$0HS0LfHnIT$8fHnflC0H@MIH$fIE H4HEdH+%(   uH@HIu8[A\A]]nf     UHAWAVAUATSH(H}dH%(   HEHS} x   H  P$  Hv L~Mu   D  LLIH   I_0I;_0uHUH  @$l  HB8HEIM.A   Mu*   fD  MMpxMpE1IH   II     LLH  kHuIE8IM0I]8LfHnfHnflAG0HKIHD1HUdH+%(   &  H([A\A]A^A_]@ H8       L˛H   HMH5} fH@H  HPH`Hp   ~ uofL(XIEtHMHAHuHHEtRHuH}WyHEƀ#  I@ HB HEIfD  H   	II I0I@rHEdH+%(   uHN@H(HW81[A\A]A^A_]0UHHdH%(   HEH  @$tYH8HHt9ff.     HG0HW0fHnHG8flHBHG0JHHuHEdH+%(   u
1H D  UAHAVAUATSHH0H   dL%(   LUMHtHHH    HEHtH; u%HEdH+%(     H0[A\A]A^]D  @ tHLMD]LU{IHtHAA   DLU1D]L$LMIMM    ff.         LLLUA$   M$   D]LMEHEALUIt$@A$   I   LMD]IAuHE11Ht.    L$IK|&@.RK<&%RAEIH;rHEdH+%(      H0L[A\A]A^]"fEu[ff.     LLLAA$   M$   LMMT$@LMI   AuEf     A$   L1LM$   ALMI   ALMuJf.     UHAVAUATSHdH%(   H]HH9d  IIE15f     D  E   D  E   HI9  ~  fɋ  fbfofsffH~HuH} x) uH}Hx
    LH1)D  HIEdH
 H	 L1    D  HIEBH
 Hp	 L1    D  HIE H%x
 H>	 L1    HHII9HEdH+%(   uHL[A\A]A^] E1fD  UHHHm} dH%(   HEH   z HD   HUdH+%(   uW    UHSH($  EdH%(   HE1   HH  H   HWf.     KEHHPHtuf&   uH  HZ@HU}HUH   H} y t
H   HHxPfH*Y Hx`fH*^Z/EHEdH+%(   uZH] 1@ HڃfHH	H*XY HyHfHH	H*Xf ff.     UHHHͧ} dH%(   HEH   z HD   HUdH+%(   u    UHAWAVIAUATSHH  H  0D  HHL8  L  dH%(   HEH@  D H@8  H(<zfH} H()D I)y ))fo )`fo ntD   L   y tH9 z  y tTH5t
 LL([L(Ht20   H_L^cLHH`0 0   H_L,cLHHIp
 8AUHs LPH
 AQL
 ATLHLL1D_LL   H AMt)HcL1HH)L	t
 L   JAMtKH  AW!@8   EGH1
   HHIcHs
 1H)L菉AH@Ht(HHIcH   1Hs
 H)L[Aċ<x!HHIcHs
 1H)L0AHEdH+%(     HeD[A\A]A^A_]     Hu
   HHIcHs
 1H)LӈA? LH`Hs
 1LϾ@   L0L(薈H(H_CaL0HH`n
 D  8yL   L(LH 9tH@L(Hԣ} H9y HHH uh.D  H;     L  H IHH9uD  H9     L  H IHH9uD  LH`Hq
 1LϾ@   L0L(^H(H_`L0HH`D  LhH/LD0QD0HUfff.     UHSHdH%(   H]HH5:q
 HԎu(Hi} @1HUdH+%(   uRH]fD  H5q
 H虎uH.} @ H} Hٿ   Hp
 01?fff.     UHSHdH%(   H]HH5p
 'tHEdH+%(   u,H]1@ HEdH+%(   uHH]114 UHATISHHHHdH%(   HE1HǇ      HH)  HH[ H   oC还H} ǃx  L  HP  H   H  H  H  HEdH+%(   uH1[A\]fD  UH  HHH5} dH%(   HE12HEdH+%(   u1f.     UH5p  HH dH%(   HUHCAuHEdH+%(   u2D@ EH} (      H= HDEfUfHnflHHdH%(   HEHGfHnflGHEdH+%(   u@ UHAWAVAUATSH   H$ H   1ۉ$H0IHdL4%(   LuIH(O0ugLI@K  IH  LbHt#uHXx.uW{ uQL1?HuL+x
LHEdH+%(   ?  Hĸ  [A\A]A^A_]D  x.u{.u{ tfD  Mt7I6H   M~f     I7IH   HctLIL1H#
    L葂H(L2/ÅxnH%   = @  u:$$LLpX @ LLs*H} L   Hl
 01?;LG* UHSH   H$ H@H&
       ~z} fHnH@5
 L 
 fldL%(   LMIVH   )fHn1)dBH1HOHUdH+%(   uH]D  UHATLfH5v
 SH]H ~} dH%(   HEHk
 HE    fHnfl)E    HsHHtLatHUdH+%(   u	H [A\]bfUHHdH%(   HEHؚ}  HEdH+%(   u'    UHHdH%(   HEH}   HEdH+%(   u    UH=j
 HATSHdH4%(   HuHu*L%} uEA$HuH=_ *uH} UA$HUdH+%(   u	H[A\]aUHH f~ dH%(   HE1tK~ HEdH+%(   u6ɉHuH=,j
 U-*UxҋE~ ~ f     UHHdH%(   HE1Hf} G   8 tH} 8 uO*HK} 8 tHEdH+%(   uD  O*uD  UHAWAVAUATSH   dH%(   HE1?/   AH0I~9L    H;/t    /   H3zIHt|A$ H0LI\$29uA$/A|$/uH;/tD  DLHtA$/    HUdH+%(   u:HĨ   [A\A]A^A_]H0L8u1DLMHRfUHAWAVAUATSH   H$ H8HIdH%(   HE1AK  ILDh1*D  ff.     ff.     LwLA9~1?,uD   Lw)LHA9HNЃCLA9LJHH  Lc   L0HH   HJHcHff.     A      HD9DNHMcL)M<LL.   1BƄ5 HA LHCJHcH;uH   H討HHHEdH+%(   uGHH8  [A\A]A^A_]kf     HEdH+%(   uH8  [A\A]A^A_]:f.     UIH5Lf
 HHHC} dL%(   LMAщ   H1Qq^XZHEdH+%(   uf     UHHdH%(   HE1HEdH+%(   u1Ҿ@ UHHdH%(   HE1~.HUdH+%(   uX     UHAWAVIAUATSHdL<%(   L}IsH   11ItIH   MtqLxHHt)HLAׄtHsLfLwHHuLL"HEdH+%(   uBHL[A\A]A^A_] HpLfLwHuD  蓇    fE1륐UHd
 H5]fHnHAUATSH(~L} dL$%(   LeIHE    fl)EoHt2HXIHuL@ H@1HHt8HsL<tHU1L
HUdH+%(   uH([A\A]]Lh|UHHHdH%(   HE   tff.     HHuHUdH+%(   uPUH=c
 HHdH4%(   HuHuG#DEHUdH+%(   ufD  UHATSHuHdL$%(   LeA   3uA} t)dAD9HUdH+%(   u(H[A\]fD  Hu&   tŸ   fUHATSH dL$%(   LeIH    H=b
 HuHuHE   qHtyHË@u/E1HzHEdH+%(   ubH D[A\]f     ]KHHHyNHDb
    LHH1yA ۄD A ff.     UHcHHSHdH%(   H]HH=a
 A~%H HEdH+%(   uHH]    perfC 7    UHSH(dH%(   HE1 tfHH}a
 HtH5a
 HHM,~u`H&HUdH+%(   u\H
} H]H   12HCa
 -/D  Ha
    H5A
 HG Huغ   HGpUHAVATSH   H$ HHH`
 dH%(   HE1IHHǅ        Lu  HHT@~`HƄ f/tLH5
 HIEHu4HMH   Hl	 }xHD  1HUdH+%(   uHH  [A\A^]|ff.     UHAWIAVAUIHATSH(H}Mu LdL$%(   LeMMu/   H?w$HY?1HHH)H9r HH   H9sI9tSLH>(HEHteMupMt&LIHMHLLI_J8L9uHEH}H8I] 1HUdH+%(   uKH([A\A]A^A_]fD  f     HLHEIH0j_MtI9qED  UHATSH   H$ HLs    dH%(   HE1VAIԾ      H14LH\HUdH+%(   u	He[A\]D  UHATSHUH dL$%(   LeIHu8d   HUHE H}HE$fff.     ff.     4VԀvTHHHEuHLH5	 1)~?A$H}QbHEdH+%(   u0H [A\]    HMH    뿻fff.     UHAVATSH   H$ H(   dH%(   HE1   f~ f~ SH   HILq 1         H2=     HHzunIٹ   L\
       Hf?~ 1B2=  sHH(u  vf~ %D  H} ~ 311H=q (*HEdH+%(   uTH(  [A\A^] H}    11Hp 3)     H} Hp 113)@UHHVdH%(   HEG9u
GV9t)HUdH+%(   u:ËGV9uGV9uًGV9uϋGV9uŋGV9u+ UHH   H$ H dH%(   HE1~    QH   HI   1L-p       H0H=  )H5r~ }uiHEdH+%(   uc     LY}    11HIo A0Lz(LA0~ 11Ho Z(     L	} fUHHNdH%(   HE1f~tJG?I19|HEdH+%(   uOɉfD     HHH#T
f.     GI19}   H#T&fD  UHATSHdH%(   H]轸IHt~Hx   HHEdH+%(   uHL[A\] ff.     UHAVAUATSH dL$%(   LeIfp  ftzfA  A|$[IH   fA|$    1+f     f  fALPAT$9   ALTfuйf     AT$AD$)AT$|[IHt1A|$   AL$fA9L$rf)1D  ff.     ff.     fAL@AD$91  ~H} LEHYX
 011%H}^E1HEdH+%(     H L[A\A]A^]fD  Hi} H2m 101%D  A\$  E1E1 f.     K|
vIAD9~fA|$uC|f.     DYIHPAT$E11f  K|
H  H  H A0       AII  IDADIDXA   ADIIMIDDXIAADIIMIDDXIAADIIMID˃HHc΃ MH  Wf     fAKH?   HHH!      H A0       II  IDADIDiA   ADIIMIDDiIAADIIMIDDiIAADIIMIDŃHȃ I  2{D  ID9AT$fDCLHtHA   1R   fA@@ A   1 Hр} LEHVU
 0A   1HEdH+%(   uH 1[A\A]A^]pWKff.     UH53U
 HHdH%(   HUHUDEHUdH+%(   u     UH5T
 HHdH%(   HUHUDEHUdH+%(   u     UH5T
 HHdH%(   HUHU4DEHUdH+%(   uX     UH5iT
 HHdH%(   HUHUDEHUdH+%(   u     UHHdH%(   HE~ tHUdH+%(   u@ ~ fD  UHHdH%(   HE1f=ü~  t~ HUdH+%(   u d@ UHHdH%(   HE1f=q~  th~ HUdH+%(   u K@ UHHdH%(   HEH~ HtHHUdH+%(   u( H	~} HR
    014      UHAVAUATSH   H$ H   H$ H dH%(   HE1H=~    HHh~ H  f~Ӿ   HHGHX  ILbR
 1         H)'=  q  H"HH  fD  HcH   xuLhH1H5f
 L~H      1AULL	    H&ZY=     HIHs LHcHtFx
uHxH1H5|Q
 d~ЋH~ LcHuLeHbH@ HH1HUdH+%(   }   He[A\A]A^]fD  H{}    Hd 101H{}    Hd 101H{} H*u H|P
 101!UHAWA   AVAUAATIS1H8HuHUdL4%(   LuE1sA   LA93EHk
 Lz
 LEʘHHUHuP1HJ<2L6|
    L)$Y^HI ff.     LD95  LuD9mL2A   A@ DL2sA9   L2DLЉUp2UEHuH
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sA9UDL1EH
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 01HEdH+%(   uHeL[A\A]A^A_]fU   HATSH  dL$%(   LeIHH_w
 1H   L@HUdH+%(   uH  H[A\]n ff.     UHAWIAVAUIATSHH(HUdH%(   HE1:fEMQ  HH  f;  fH
IH  1LE1P0I@ ft.fۍCIfffH)Ѻ   AALD0LAD9]LfE    ff.     ff.     ff.     ff.     t<A,LaLHAEp0PW<	GtLayA LPHEAD LL)f     A 1HUdH+%(   uH([A\A]A^A_]    UHHdH<%(   H}H=~ HtHEdH+%(   uDfD  Ht~ HJf.     UHHdH%(   HE19tHUdH+%(   uMfD  V9WuV9WuًV9WuыV9WuɋN9OuN9OuN9OuF f9G  ff.     UHHdH%(   HE1?tHUdH+%(   u=    uu܃uփuЃuʃuăuf ?@ ff.     UfvHHdH%(   HE1fG GHEdH+%(   uH     UHcHHAUATSHdL,%(   LmAH<   kIHt,D(E~$1f     HcÃHI|A9uHEdH+%(   uHL[A\A]]UD  UHAWAVIAUATSHXH}HuHUMdH%(   HE15>qHH        1LE1Le[,H}A=D9~of.     HEHUDLЋ   LsE1D  AI$D9;~{LL[tH}AD+H}A=D9H}D#=A9uhI܀}    LHEdH+%(      HXH[A\A]A^A_]D  foEHcЃHDfoEDML$fHcHHH4   IHu} xIc4$I|$$   Hp_YUHATASHH0dH<%(   H}H}DEȋEfoEC foECHEdH+%(   uH0H[A\]3 UHATSHHpHUdH%(   HE1u1HUuH}AoEEH})EoEE)E
u1EDHDefoEEfoEЉC CHEdH+%(   uHpH[A\]D  UHATSHHpHUdH%(   HE1uHUuH}A^ooEEH})EoEE)E	u1EDHDefoEEfoEЉC CHEdH+%(   uHpH[A\]D  UHATSHHpHUdH%(   HE1uHUuH}AoEEH})EoEE)E-	uDefoEEfoEЉC CHEdH+%(   uHpH[A\]. ff.     UHATASHH`dH<%(   H}H}oEEH})EoEE)EufDefoEEfoEЉC CHEdH+%(   uH`H[A\]@ UHATASHH0dH<%(   H}H}DCEċEfoEC foECHEdH+%(   uH0H[A\]# UHSH8dH%(   H]HH}1foEfEEfoEЉC CHEdH+%(   u	HH]UHAUATSHdL$%(   LeI*      9LAŃX?AHcI$HtNIcH1&MHc   ID$Ht"AD$ 1HUdH+%(   uH[A\A]]Lu 	f     UHATLcSHH dH%(   HE1gAt   9LƃD9HEdH+%(   uVH [A\]fD  D   ICHIHc1HHCHMLH	HSbHMLcHI!$Lff.     UHSHdH%(   HE1Ht7H{ uAH{hHEdH+%(   uIHH]L@ HEdH+%(   u)H] Hp   9L1Hcff.     UHAWAVAUATSHdL,%(   LmI      9LAǃp?AHc	HEHtl1LE1$7fD  ftHUHÉپ   HHH	4ALDi$L6D9HU1IcH}3HEdH+%(   uH[A\A]A^A_]UHH   H$ H  dH<%(   H}H`    xdx86_t#ds390tg1HUdH+%(   uc@ fh64u5HE1H_U H   1HXATHX1 hxt1fD  UHAWAVAUATSH   H$ HHAHIdH%(   HE1Hǅ    Hǅ    5   HEHHT 1HS1H9  HH5	 McIH  HHH
   \LIM  L
   LOHt
  LIFE.HE  HE1AHE9  H3LZuE9o  E1I~    4H   DHHS 1HRH5	 H^bIH   HHH
   [LIM~tH
   H3NHt
  HIFEnHEn  IE1@ AIE9?  I4$HYuE9&  E1.3HD   HHaS 1HQ1HM|  HH5	 aaHHH   HH
   ZH~nH
   H=MHt
  HIF EfHE   IE1fD  AIE9tkIu HXuE9tVE1HH@HEdH+%(   D  HH  D[A\A]A^A_] AD  HJHHHHǅ    AFy    HJHHL Hǅ    AHǅ    VD  s1D   HHHQ 1OVf.     ;1D   HHH6Q 1O2fHJHHHHǅ    AFHǅ    ?@ ff.     UHATSHdH%(   HE1H   Ht&E1fff.     HCJ<I?D;#rStE1HCJ<ID;crCt)E1@ ff.     HC J<ID;crHEdH+%(   u2HH[A\]>f.     HEdH+%(   u	H[A\]C UHAUATSHdH%(   HE؋GtZH_ L,-   L3JHuHL9tL#,   LJHtи   HUdH+%(   uH[A\A]]1     UHAWAVAUATSH8H}dH%(   HE1H   HH>IŋC   HE    HEHMH@ H<>1HHH߉ƉuO.~suLE1AAHD{HA .A9}CDLD8tH?L{?1HUdH+%(   u?H8[A\A]A^A_] HP?HUHEHE;B<L2?   fD  UHAWAVAUATSHdH%(   HE1DwH   IEÿ   HpIIH(k IH   H@(IFL|   IF E   A1    LƾtLtSE1A9uLP>EuCHEdH+%(   u_HL[A\A]A^A_]f.     IFLx@ L>L E1Hb} H7
    018     UHHdH%(   HEHH~ HtHUdH+%(   u;f.     H~ HuHb} H7
 101FAO輾ff.     UHAUATSHdL,%(   LmItMe1 LI A;] rHEdH+%(   uHL[A\A]]z:ED  UHAWAVAUATSH   H$ H   H$ H   dH%(   HE1Hǅx    Hǅ    v+   HH6
 H1IH5n	 HYH  HH
   IHxRHZ  Hx
   HEHt
  HxH:HPH  Hc*ǉLHHHKIH    LxHL@HXL8ǅd    dD  HPDHǅ    Hǅ    A_`<*Aؾ   HXHHJ 1HHHH5+	 XHHb  HLHhLfHٺ
   LLQH   H:   SDHtHhH1HH54
 [J  HMemTotalH9   HMemFree:H9   I iI ^H1)HX   D`HHJ 1HGHH5	 {WHHS  H
   LLPH   L
   L_CHtz  HIHdd9L   I f:HIGf HIG M' HL@L86HvLVE1ff.     Hx6LLHP8HEdH+%(   uHHĨ   L[A\A]A^A_]HǅP    E1L@L8L@L8sE1@ ff.     UHAUATE1SH_HdL,%(   LmIt!fHAH{HE;e rHEdH+%(   uHL[A\A]]5kff.     UHAWAVAUATSH(dH%(   HE17  HcHH<IH   L`E11   HE    HE    H;I$H   H5
 HIH   HuH}H
   NH~dH}
   @Ht  LAIpHEID$H$HHcHEdH+%(   uAH(L[A\A]A^A_]L*McIK|7H}P4LE1f.     @ UHAUATSH   H$ H   H$ H(H0
   dL,%(   LmIH賱   MHHO	    HC1H1ZAăt!HEdH+%(   uJH(   D[A\A]]ÐH^} H   HE0
 H81ܵf.     A UHAWAVAUATSH   H$ HxdL,%(   LmIH/
    HIð  H1ɺ   H5  HlI\T  KD% L%} Hp    I9ukI$@Lk,   Lz>HHuL;p   H} @HEdH+%(      lHx  [A\A]A^A_]    HL)L:HxHH   L   Lc   M<$M9t4fKt7>/u~HE111L%u3AGM?M9uLHx1H2@ M?M9ufD  HpGHx`1ǅlff.     UHH0dH%(   HE1t1HUdH+%(   udD  H}HxHEHtGHUHu@ HxHEH,HMH=} H5.} H/} H1HAHv@ ff.     UHAVAUATSH   H$ H   H$ H@H2-
   dL,%(   LmIH   ME H1H	    H@E1HHHǅ   bFHHIIEHEdH+%(   uH@   [A\A]A^]@ lff.     UHSH   H$ H     dH%(   HUHH#tHUdH+%(   u4H]D  H`HMx1H`prgcҲfUHAVI0   ATSHdL$%(   LeAHt}@,   LHHC HtKEu-C(HEdH+%(   uKHH[A\A^]f     LHC(uH{ H_.@ ff.     1    UHH dH%(   HE1Ht)W,H     r9rq,9tuHEdH+%(   uFfD  uy(xHM,HMHy HMHEdH+%(   u
H}-mfff.     UHHdH%(   HE1Ht W, JO,9t
BvHEdH+%(   uH    UHAVAUATSHHdL4%(   LuIH9t*IfLx  MtI|$ LDt3HI9uHEdH+%(   uEHL   [A\A]A^]C L,HtHUdH+%(   uH[A\A]A^]RfUHAUATISHHdL,%(   LmIH9t@ Hx   t&HI9uHEdH+%(   u(H[A\A]]@ LH,Hx  HL9uүfUHAWAVAUATSHdH%(   HEHGHH;  HI	M$@ ff.     ,   L7IH   HI9   L)L蠨IH   HH/HH   HH9tmL=~T} 1A    H H9tM9uHx  L"+AAMtrMu[ H1T}  @ M9tCL` DL*HUdH+%(   uvH[A\A]A^A_]     HS} t1H3H9tHx  H6H9tHx  Q,Bwzy,9t؉LV*vHmU} "      H=< HL    UHAWAVAUATSH   UOdH%(   HE1}  H}I蟥H藥H`H.  H%  HuHHMo
  A    H
  HHP)Eo
  )Eo
  )E
LH5t&
 LH  L5} _  L=} HMM9[  HUHLuL`HpHxHHL@A %  HxI|?/uHu_HhH  L+L9  LXMI>@ I  Hx  MBL(LLI$x  肹M?L9   L1ܧIHuLuAHR-H`F-Hp躼H=} L9t) ff.     HHGHBH'I>L9uHEdH+%(     HĘ   D[A\A]A^A_]D  L+LXI9   MfLM$   HtLLH  D I$  HtH  I  I$  H   H  I  M$$I9uHH9tf     Hǀ      H H9uLhL@H7P} LLHpHP >HHLAF    M?HEI9HHL@IH;	  HcN} E1 FM$$L9=yHMLhMHxM| L5} Hp,   LC2HHIIDI9   L)LBIH1  IL9u4@ HL9t(H{L>uL%MtcMeD  LHxHESHUHHu  @ HxHL!IFL3LI^HCH%MuL=} HpLhHxLM9        @H L9u1D  IL9tx/u
x 8H L9u   Ht$/   @ fPIVL0IFHPHHxHEHp~HEHpHO} L   H!
 H81I   HO}    H=x!
 AH3y"   HO}    H=6 AHNLHx/$HEHp@ ff.     UHAWAVIAUIATM  SHx  HH(dL<%(   L}IM  Mu   fD  IEH   IIEI9twL9rIEHuIELmHE0   IH   LWIE H   fMuLLHU AEIE(HEIE HEL(H 4HEdH+%(   uHH(L[A\A]A^A_]    IELmHEbHE    LeQL"E1蔦@ UHHdH%(   HEHHt&@ ff.     HPH9tH9s"H@HuHUdH+%(   u     H@Hu UHAULx  ATSHLHdL$%(   LeI=H  HtHCI9tL9s2H[HuLHEdH+%(   uHH[A\A]]@ H[Hu营UHAVAUATSHdL,%(   LmIHx  I  Ht7D  I  $I  HHH;I  HuHEdH+%(   uHIx  [A\A]A^]'2fUHAWAVAUATSH   H$ Hh   HHdH%(   HUH
 裞t/HEdH+%(     Hh  [A\A]A^A_]f.     H1ɺ   H5FHHxL=} H} I9tHHHHxHIwHHxILHb	 A9 ǅ   LDE1Lo6LHLIL(Mu   f.     IEH   IM9et|rIEHuIEH0   LpIHtMHp_IF H   Hk fMfLM.HIF(HAFL0M?I9M?I9GL HHGHBHH;H9u!IEHLH@蟢LD  UHHHWO#dH%(   HEHH   HGG H tLHG       G  H   HG    tG# fHUdH+%(       udH   HG    u     H vHthH tIHG    ufD  HpG  H\if     tG# NfD  u1=D    uH tG# 8     UHAUATSHh  dH%(   HE1H   L   HHHNBHHHt#@HUdH+%(   upHh  [A\A]] 
   HgH: u;L   HHZHHu ff.     D@ UHHHdH4%(   HuH΅yC'  wHHcH&| HHHo
 11HUdH+%(   ufD  HH- 輟f.     fUHAWAVA   AUIATISHH(UdL<%(   L}L?Mu=fD  HHCHHt'ILLAT$tXHE1HCHHuـ} tcLLAT$ IHtPfL8@HEtID$LLMAD$HEdH+%(   uH(L[A\A]A^A_] E1ƞfD  UHAWAVAUIATSHL'dL4%(   LuIM   HA   HHCHHt*ILLAU   HE1HCHHuLLAU HHt{fL @HEuQLAE1HUdH+%(   uQH[A\A]A^A_]LW HHt-fH    GI}  I}f.     맸譝fff.     UHATSHHdL$%(   LeIH;wt8HLkHEdH+%(   u(HC(HLH[A\]fD  LHC-fff.     UHHdH%(   HE1HEdH+%(   u1>f     UHHdH%(   HE1HEdH+%(   uɺ   覜fD  UHHdH%(   HE1HtG    fHEdH+%(   u\ff.     UHAUATSHdH%(   H]H_Ht$IfD  HhHLHJ5HuHEdH+%(   uH[A\A]]fD  UHH dH%(   HE1Ht(H}WH}HEdH+%(   ufD  HEdH+%(   u肛fUHSHHdH%(   HE1Ht;    HHt uHEdH+%(   uH]H@ 1    U   HHdH%(   HEHGH9rH9HEdH+%(   uɉ̚ff.     U(   HSHdH%(   H]HYHtHXH@     HUdH+%(   uH]n ff.     UHHdH%(   HE1HEdH+%(   u	H](     UHHdH%(   HE1HEdH+%(   upff.     UHHdH%(   HE1HEdH+%(   u2諙ff.     UHHdH%(   HE1HtHEdH+%(   u HEdH+%(   u1PUHHdH%(   HE1HtHEdH+%(   u HEdH+%(   u1 UHHdH%(   HE1HtHEdH+%(   uۑ HEdH+%(   u貘fUHAUATSHdH%(   H]H0   EH   HIqH~| fHnHflID$(AD$HuPLu0HEHX8 t7Huк
   HHHE <,tȄtL-E1f     HEdH+%(   uHL[A\A]]Η ff.     UHHdH%(   HE1HEdH+%(   u苗f.     UHH H dH%(   HE1HtLH   :/tHUdH+%(   u5    HH6HMi"HMA     1    UHSH(dH%(   HUH   HtzH: u2z0 uCz` uTHEdH+%(   ulH   H]fD  HzHUCHU؀z0 tHz2HU,HU؀z` tHzb    HEdH+%(   uH]FfD  UHAWAVAUATSHH   L   dL4%(   LuIM5  I>L0H5tHǅ8    LH08  uVL     H5	 LHHtV HEdH+%(     H   H[A\A]A^A_]     L     H5S	 LHHuH<	 HI>LH5Hǅ8    H0H   LwHH[I\$A<$   A|$   H5	 H=
 0IH4  H@f     L   H H  1H(LHL$H5t
 ǅ$uHc$xHHߺ   uL+H(L0I)LIHtJI\$Hǅx%LLF/I9   rL
   fA$1)f     L     H5	 LHHH	    LHHH3HHHHH(νLf   fA$ff.     HHHhHLHH1HuH9f        H=$| oH   IH1D  L舗1茒H9}       H=\
 H\1D  UH5J	 HSH(dH%(   H]H   Hp&   tH56	 H߈UU&   uHEdH+%(   u#H]D  H5	 H!&ՑD  UHAUATA   SHdL,%(   LmAHt](   DDH:Ht.HC   DD!HtHC(fD  H{H@ ff.     1HEdH+%(   uHH[A\A]]ff.     UHSHdH%(   HE1Ht7HHsH{jHEdH+%(   u(HH]fD  HEdH+%(   uH]螐 ff.     UHSHdH%(   H]HHHEdH+%(   uH{H]H     UHHdH%(   HE1HEdH+%(   uH  驫@ UHAUATSHdH%(   H]HIH   LADVH  HHUdH+%(   uH[A\A]]臏    UHSHdH%(   H]HH  跏Hǃ      HEdH+%(   uH]2f.     f.     f.     f.     f.     UHHdH%(   HEHUdH+%(   uώ@ ff.     UHHdH%(   HEHH9HUdH+%(   u舎     UHH XdH%(   HE1Hx`fH*gf(\f(^X\OYXGGH9wsHwH;w sHw HEdH+%(   u"fHHfHH	H*X͍fff.     UHHGdH%(   HE1HEdH+%(   u芍f.     UfHH dH%(   HE1f/vHEdH+%(   u9f(f.     f(\ģ G^^f.wf(QHEdH+%(   ufff.     UfHHdH%(   HE1f.zuHEdH+%(   uf(@ Y f(^艌f     UHAWAVAAUIATSHdH%(   H]HH9t0L  MtEt$(0   IcID$0Ht(HI9u1HUdH+%(   uH[A\A]A^A_]ø@ UHAUATSHHdL,%(   LmIH9tZ    L  MtI|$0
I|$8 H  HH  Hǃ      HI9uHEdH+%(   uH[A\A]]N ff.     UHAVAUATSHdL4%(   LuIH   H   IHQ  I9   D(]  E   @ @   IHJ  H  Ic0   Dh(ID$0H
  H  fo fH@     PH  Hx0HtHc@(1H@HOH'  HI9c1HUdH+%(     H[A\A]A^]ÐII9tՄu|@ @   &H}  fo fH  H@     HH  Hx0HtHc@(1H@H訊H(  HI9uX E1D  @   覾IH   H  Et&Dh(Ic0   ID$0H   L  fo` fID$    A$A\$H  Hx0HtHc@(1H@HHxyHH	H   A
DpHtKH  HI9(p I9dHǃ      L    L8-if     UHATSHHdL$%(   LeIH9t^f     H  foA fH@     HH  Hx0HtHc@(1H@HۈHHI9uHEdH+%(   u	H[A\]辇 ff.     UHATSHHdL$%(   LeIH9t4f     H  Hx0Ht8Hc@(1H@HMHI9uHEdH+%(   uH[A\]D  HI9u)f     UHATSHHdL$%(   LeIH9t"f     H  Ht,HL9uHEdH+%(   uH[A\]    HI9u詆f     UHAWAVAUATSHdL<%(   L}L?L9  I@ ff.     I   脼   HcE1fD  E1fff.     LH@D9   I  H@L;hsvL;p spHHHIIHT(H4I  H@L;h,L;p ,HHHoIIIHH@(oF@8HV HPHbf1@ IL9;M?M9HEdH+%(   uH[A\A]A^A_]Lff.     UHAVAUATSHdH%(   HE1?uaHIH9tVI       fH,HHI9t8L  Lf/) IF0r\ H,HL1(HI9uHEdH+%(   uH[A\A]A^]藄    UHAWAVAUIATSH   L  dL4%(   LuI     I   uLHS  Hc˅  HE    E1MHxH`LXMK@LpE1HHh    H   I$   DLu+LLA   HEx(   H]LA   LuE1H   H}Lv  HMKvIH]HHA0@(A$   u7I$  :t*A?p  H{ tH{ ^   ff.     x, uH@    f@,     IL9x  I$  EHXL;k  HpH;C   HCHHIHD(HI$  LHEI$  HE.DHHEfEA$      H}S   H}   H{    H{    }豠Ec  }={R     EHH9  UHcEHuH}H H	H1c Hu   H}E1E11ɺ   '  fA$      Aw1HHEH@0A?H; uA( oHh@(HIHHSHPHSHPL9xNLpIL;`   DE@ HH^b~ )A$   YUHDL	C@ 1+f     x, bHEII$D9p(If1H5H=HEH=    I$  MLXMA} t*1HUdH+%(      He[A\A]A^A_]fD  I_0LH3HJ#} ~L{LLcHAHI}0MAWHH	 Iؾ   1{~XZz@ LbH"} H 101H1ff.     HH9"HPH9u`UHAUATSH(dH%(   HE1  HII A}   HI9   H  Htx uL  LM9u   ff.     M M9tI9  uH  M  HG0HtxW(A;S(   11+ff.     ff.     ff.     HG0H0IS0HȃHDR(DP(LLLRLPHRHP;w(|c I{0 uT@ HEdH+%(   ujH([A\A]]fD  HL  LM9LH!} H 1LELMȋ01DLMLE}fUHAWAVAUATSH   dH%(   HE1  L>L9  H@HH(HEH A   r  I  I   1HHǅ    ǅ    HpHI   9  HHH@0|-   H(1E1E1Ňo@`1I   EI  )poPH )Ef)0    H H(1҉Lh0Uo@`HH)EoPE)Et$KdHIAoM fԍ0Mu)0I   At$IDI   D9]I   1L E1E1    H H(1҉L`0荆o@`HH)EoPE)EItH fo0CD4-KD4C4I   AI0DI   !A9`I   OH0M?L9pHEdH+%(   uH   [A\A]A^A_]zf.     UHAVAUATSH H(  dL$%(   LeIAoD$It$I\$()EH   Et$HIHDZ   I  HHRH;Bs[IcL$H;J sPHJfoMHHD(H\1Aƅ	  HUdH+%(      H [A\A]A^]f.     LAL$ED$1IH} H+	 01H} H 101LAL$H	 1IH} 01跾0yUH	 HAUI   ATSHHHODOdH%(   HE1DGLwHKLK(LLC Lc   1H uwHLHUdH+%(   uH[A\A]]xUL	 HHHOdH%(   HU1HHH5	 LEH	 1   wHUdH+%(   uH<xff.     U'   HAUIHATHSHH  dH%(   HE1HH   L1HK
 v   LHcHJ	 1gv   LLcH<	 1GvIܾ   LHcH,	 1L"vHHHUdH+%(   uHH  [A\A]]Kwf.     UHAWAVAUATSHHH}Ln@HMdL4%(   LuLv8I>H  IcLmIE1H@HuHHEf     1wKHEH  H   C  H$1ff.     H$9!  f8 u   K<E1H  Mt8M  Mt,M  M  M9tHMLQ8OM;    H   	      H@0@   HcH4vHHHx    H H  fH*Y2 E   f     EVHH  H}EDHID$I<H   I     E1 H} H    1ۋ01Һ        1۾   @ HEHx tH H   fH*E7EmK<EA@ LmAM   I}     H]fD  II}     LHVtHUdH+%(      HH[A\A]A^A_]M  MM92M;  tM M9uE1@ M;  uI  A   HƃfHH	H*X5HƃfHH	H*XDOE1	=sf.     UHAVATISHdL4%(   LuAHE    HtZ11EHLHExIT$H}Hpu<HTEHEdH+%(   u*H[A\A^]D   fD  HE    !sUHAWMAVAUIATSH(  I1HdL4%(   LuMHH  HH
  _LH  HMs  HQ(I9  Hǅ    ƅ HLHDD  HO  H fI1H1LL)M?L;1  A} ubHX tSHIw0HHDHH2z     H   	  f     HP~IFHtHLIFI_HIGHIG HIG(HIG8HAGHIH IH I} Ht
KID$LLLDHAD$AE(AD$HHH<    A~  fHsE
 cfH=DR~ AHtH  H@A~HH  HT  HH}?
 @   1HHHHLAVHHQ~ HH  HQ~ MD  HH LH txHH0Lʈu^0f.zPǅ   f(fT" f. w:f/ s0ff.zǅ   tǅ   @ ǅ    HHtHu} H|  IH	 H LH@ HH(  D  1HUdH+%(   {  H(  [A\A]A^A_]ÐH(H8x Y( H?   H8H@H   DIؾ   1H+	 HH IH	     Lx(    L HH	 1@   H,HHHjO~ H9  =H1LAVHeB
 A~  rHH(  _IHe	    1HH$fLrcm UHAUATSHH8LaL)dL%(   LMIE     uFHME1HEԅufE111LHAHEdH+%(   u+H8[A\A]]ÉULLMHuxELMHulff.     UHHdH%(   HE1  tH  1HH
  HHUdH+%(   uVlf.     f.     fUHHdH%(   HE1HEdH+%(   ulff.     UHAWAVAUATSH8LndL4%(   LuIMt>~ F AHH@
    L   L=U@
 H
 IEIjEu4A~    HEdH+%(      H8[A\A]A^A_]    HG	 { ~| H;@
 fHnC IEH{flH	    )EfHnH	 ~œ| HEH	 1fl)ENDiA~ ZHEdH+%(   uH8L}   [A\A]A^A_]陪j@ UHAUATSHhH^dL$%(   LeIM   H   H}   @   MŸ   Iȹ@   H}蒷H}I PЀ	v<.   LPHJЀ	v.t  LLE|HIL$XHPLEHt	 1Iɾ   hXZHEdH+%(   u\He[A\A]]f     IL$XHEdH+%(   u4HeHIȾ   [Hu`	 A\1A]]9hf     L]si UHAVAUATSHPdH%(   HE1M   HH=
 IHHE   Ln@   @   H}I   MH}tH PЀ	v<.urH@ ff.     PHJЀ	v.t  MD$XHLH_	    1ZgC HEdH+%(   uHP[A\A]A^]f.     HvhfD  UHHpdH%(   HE1M   MA8    HIH}   H<
 @   LUHE@   L]H}I   BH}iLUL]I PЀ	Lv <.u2fD  ff.     ff.     JHq@	v.t A9 Mо   H	 H<
 I{LDA{ AC H <
 HEH	 1fHEdH+%(   uLgff.     UHSHdH%(   H]HHt^H{0I1H	        eHUdH+%(   uKS@H{0J4)H]L;
 Hƥ	 1ɾ   ueD  HEdH+%(   uK@H~4fUHHHFxdH%(   HML t:H  H  H  H9  tHEdH+%(          H   H9x  uHtπ uHF t+HUdH+%(   uJLGXH\	 HǾ   1dHUdH+%(   uWDIHǾ   1Ho	 rdefff.     U   fHAVAUIATIHPSH   dH%(   HE1)0Hǅ@    ƅ@HHPI|$0H HHXH(A|$ umA|$   AL$8  A|$ x  A$H]| H;@t=It$0@,  輤{H@u@ ff.     A|$ $  I$(   tIE Hx  HEI] I9u!O    H;  tHI9t7    A|$ uA$uHH 1LH](HI9uA|$    HEdH+%(      H   [A\A]A^]ÐH    ݣ 0A$H H;	} uI$(   tI|$01Le8
 H	    XbA|$ ff.     L踮 It$0
   Q8IL$XH	    1b;    I|$XHd;@>i$c@ UIAHAWAVAUATSH   oEDM0 D$f~oE (f~D,D0dL,%(   LmD4    t0H_XLw0H?	   L IcL>D  H_0 H	   L IcL> Hd$DH@Af~$APL	          1H7_DHAXHLc IH ARA      HBH	 1[`XZHEdH+%(   #	  He[A\A]A^A_]    ?	wҋIH Nc4L>D  HEdH+%(     HEDH	 HEIHeL   1[A\A]A^A_]_D    u
 ,  fEJHEdH+%(   m  E      1HHeH	 [A\A]A^A_]__    HDA1AW      H@AT   APL^	 H詭HDH lfDH@AVAPL	 H   H 蕆H AH   gIHEdH+%(   t  D}      1HHeA   H	 [A\A]A^A_]`^DH@AL	          1H軬HD     HDH@AAPLJ	 )D  DH@EL0	 fD     t
   fERHEdH+%(   u  LHeL1[AA\   A]H	 A^A_]i]f     HEdH+%(   *  HEH)	 HEINHEdH+%(     HDULH	    HEHeI1[A\A]A^A_]\    HUdH+%(     HDUAHU HUH	 HeL   1[A\A]A^A_]\ HEdH+%(   Z  DU EL   HD}H(	 HE(HEHe1[A\A]A^A_]?\    HEdH+%(     HDUAH	 HE HES H   H 赃H މH   dDHUdH+%(     LHeH1[LA\   A]H	 A^A_][fA{ AC H1
 Hd1
 HEHEdH+%(   .  I{EEH
 Heؾ   1[A\A]A^A_]&[fD          A{ AC H=1
 H0
 HEHUdH+%(     I{uEHF	 AHHeؾ   1[A\A]A^A_]Zf     A{ AC H0
 H0
 HEHUdH+%(   N  AI{EHH
      A{ AC H0
 H540
 HEHudH+4%(     I{DUEAf~EHHT
 Heؾ   1[A\A]A^A_]Yf.     A{ AC H0
 H/
 HEHUdH+%(     I{DU E   D}AH
 HDeHe1[A\A]A^A_]wY    A{ AC H/
 HT/
 HEHUdH+%(     I{EDUAȉuHH
 H   L H΀HމH   aL H/
 DIH.
 A{ AC HEHEdH+%(     I{HeH9	 1[   A\A]A^A_]~XfD  A{ AC H.
 H\.
 HEHUdH+%(   &  I{EDUAH
 Hi@ fEA{ AC HR.
 EH-
 HEHEdH+%(      I{HeHr	 1[   A\A]A^A_]WHEdH+%(      HALH	    HEHe1[A\A]A^A_]WVH@Aɺ   AP   L	 1   HL   1H   Hgf	 *WY^nX ff.     U   HATIH=	 SHHNdH%(   H]H   wCAD$8uOoCTH0KPHHSxL$oCdD$CtD$ H0HEdH+%(   u4He[A\] C H{LC1H_,
 HN	    RVWff.     UIHHdH4%(   HuHր tE   HEdH+%(     Ð tjEtLW0LOXH9  Hkd1HH:  fH*HEdH+%(     ILɾ   H4	 L׸   UfD  H9qAgHEdH+%(   k  HA  fH*Yl H  fH*^H0   H	 ɸ   U    H9tkHkd1HH   fH*Ay AA H,+
 H*
 HEHEdH+%(      IyI   H
 ɾ   T Hl fD  HfHH	H*Xf.     HfHH	H*XZfk z HȃfHH	H*XfHHfHH	H*XJUf.     UHAUI
   ATSHdH%(   H]HHvAU8u~oCTH0KPHHSxL$oCdD$CtD$ CH0~"E1     HsI}XA?VD9cHEdH+%(   u$He[A\A]]    HsH{VpqTUHAVAUIATSHFdH%(   H]HH   IE1~@ HsI}XAUD9cIu0LUHs
   ߓAU8uoCTH0KPHHSxL$oCdD$CtD$ CH0~#E1f     HsI}XA/UD;c|HEdH+%(   uXHe[A\A]A^]D  HsH{TofD  E1~     HsI}XATCA9|-Sfff.     UHAVIAUATISHH0dL,%(   LmÀ ^  G83  M6H   IcHHH0I  HH$oHo@HRLHHF0ML@()M)EL$ $D$_H| H0I$   H9     L@ { uGH{0{ A  HEdH+%(     HKXHI	 He   1[A\A]A^]P A|$ AD$ H&
 H&
 HEHEdH+%(   :  I|$H#	 f     H(   YHEdH+%(     He[A\A]A^]fHw0{   bs8{    A|$ AD$ MD$H&
 HC&
 I|$   HH	 HE1OJD  t\Ix  HL%
      HEdH+%(   uTHe      1[Hr	 A\A]A^]}OD  H(   uf     Hs0I|$2RP     UHAUATSHdH%(   HE1H   ~ F IHHG%
 L-$
 H~IIEH	    NHK      H=X	 oCAD$8uXoCTH0KPHHSxL$oCdD$CtD$ H0HEdH+%(   u9He[A\A]]f.     C H{LCLHzF	    1>NO    UHAWIAVIAUIATSH   HhGDdPXdH%(   H]H^x 6    HgHHx     H=AFM,  Hh   H  A   >  HMHUH}LuE A      ,       AoFTH0LLANPIVxE1$AoFdD$AFtD$ 8HEH0ǅp    HHHpHPALtdf.     H  DXA   A~ H"
 H"
 AF HEI~   H	    vLHhLLLA   MHLLHHPdIHh  ǅp    INA         H=	 >lAFAW8  AoFTH0LLANPIVx$AoFdD$AFtD$ H0AL/D   tBH=SK  1HbMf     	     E1 H=a!  1H    H1jf.     AVtAoNTLLAoFdH0ANPU)p)ET$ H$D$	  H0A   h  b %b f(f(fTf.K  IG0A HHu  f.MGXz	H5k	 tH5[	 HB	 H-	 HEE  PHHLH      L@#JL@Hp  HtHHH2B	    1IHHHHLH| u
I(   tUHx  L
 HtL@ A >  A~ H
 H
 AF HEI~   1H 	 sIALtZH  XcA (  A~ H8
 Hz
 AF HEI~   H	    IHhLLLA   A u   t   dHMHLyA uCALt$H  +X设A   HhE1LLL;HEdH+%(   D  He[A\A]A^A_]f     H  H0H8H@HHxHHH@H8H0tnL&L9tfHHH@H8H0HL(ME1A      Mm L9uHHH@H8H0L(AGP   )@ Afɺ   f.EI0      H	 HG H)HD  H1H  pD  L	 H	 LEA !  f.  H	   E!           PHHFLp  MtAO@HHHU	 1   FH       HHIHK	 1ZFvD  H,f%/^ fUH*f(fT\f(fV}     Hο
   3AG8
IvI~HD  A _IOXI0   H=	    E<fLI9M>  HHH@H8H0L(fD  I0A i  IOXH~=	    1BED  AF I~MF1H
 HK=	    E@ L	 H	 I~LEAVH)
 H
 AF HEEy  P      H	 DLp  Mt3A~ H
 H
 AF HEI~   1H	 lDHA~ I~AF IH
    H<
 H	 HE1.DJf     A IOXI0   H}	    Cf   H	    1C` f.zH	 HMN	 HH   H?N	 1   C@ HHH;	    1LPgCLP? IHw	    1=C     H'	 JoD@ ff.     UHAWIAVIAUATSH   dHG0dL,%(   LmIH  HXHcH   H@HHHQ0HwoH@h)po@)E@$EL"AMTAEdAEtB(MuxAEP?t8LHP詠HP:  A /  @ ff.     HBLHHPHBHHO=   H   M  fI*̀h usA   AG8<  A   A   A   MGXHX1HN	 H9	    h~Ah  H  fH*AYh  LLDdHPHHHEdH+%(     HĨ   [A\A]A^A_]I   uH| uA     A A?h  I    I    L,h  HE1LHH@A   H@Hp:lf.     H؃fHH	H*XfAEHX{   hRAW8hBA s  A} H
 I}MEAE H(
    H8	 HE1?hHxofH*AYh  LLDdHPHH]HX
   謀B    LAfHL	H*XeH؃fHH	H*X|fA	   =D  I   1ʛL@H8A1L0?fD  LH}DA   HpHuusI   rAI   9|ef.     HXI}hXAh A( #     L@H8L08?UHAWAVAUATSH   dH%(   HEH   H  D E  IHpE1HMH@I:LtA}    I$      I   ID98f  I$  O4IM0DXILr0IcHPHAMHoH_)po@)E@$EI6CtKTCdAF(H`CPLcxAu CILHhIFMvHH28@Hh <  H`H  fH*Ȁ_    A}   AE8  A} d  HhH-  fH*DXLHLAY$h  HHI!HP
   p}I   D98HEdH+%(   G  Hĸ   [A\A]A^A_] HhH   fH*DXLHLAY$h  HH@ HHfɃH	H*XfH)| uA$     A} A}   I    I    vLb  HE1LHH8A   H8Hpec,     HHfH	H*XfCHP{   `{AU8`A}    { H{C LCH
 H
    HEH2	 1o:Hh`HHHfH	H*Xf     A} A} MEXHP1HiG	 H/2	    `9`LA$	   M"@ A}( O     HPH{`x<` I$   19L(H0A1L8?D  LH}DA   H@HuuCI$   AI$   聧9|L8H0Pf.     L(L8H0!:UHH0~b| dH%(   HEHlB	 fHnH/	 flfHnHon	 )E~b| HEfl)EHDHUdH+%(   u9    UHAWIAVAUIATMSH8H}EdH%(   H]H^EtA MV  MM  Iƀ}    H|	    H17ELAM   LH߸   {AHEdH+%(   J  %   MHr	 D)HeH߾   1[A\A]A^A_]i7f     Iw
   xHEP8   H0AOPIWxLAoGT$AoGdD$AGtD$ H}>HEH0 |   HEIL
 H*w	    H@146       H߸   6AfD  HEdH+%(   uKL
 &   Hp	 IO      H=	 VeIwI397f     UHAWAVAUIATSHH(  LDgDdL4%(   LuLvrLIMtL`DPH9DBM   LBHEdH
 HDLHLLǾ      LѰD   LLH
@	 1a5AE HEdH+%(   u,H(  [A\A]A^A_] L=-
 HIDLDrl6ff.     UIHAWAVIAUIATMSHHH  HNDxdH%(   HE1g   LHHF0LƅHBA~ L  II  EF8E  Hj| LH8蓒A~ L  #~ uhA~ u4A~ u-A~8M~0O  A
p  H HcH>1A~ t+   LLL|~ L1҃tP~ A>	   AH HcH>g t  MM9t|HpMMMƐff.     I   A   	  Ht78~1HpE1fD  DHLLI   AD; |M6M9uM@ I~`wZAv8M~0>  A~ 3  A~ (  ^yK A~   A~L   I~`2i^JK pA~ o  p   LH
    H
 g2pbA~ umA~tffɺ   f.EtOI~0      H	 23   L   H~	 H
 1A~      L   H	RAVP
  M~0LHEdH+%(     He[A\A]A^A_]    AF8MEIM A~ U  A~ LH 	  MNXH	 @   1蹾LD  I   I(   1  HI    M:M9LMfD  HHx  H9p   HpD(E   E1@ ff.     ƅA~ tDHLLM'M9t'f     HpI9$x    M$$M9uA~ t2Mf0A~ t C  L}   VqL
   IqI   AD;(eHH	HI9A~   I(   $	  M*MM9    ff.     HpIx  H9trANHtF  Mf0A~ t   L}   pL
   pIx  ANHpƅt1HLL[I   Ht0DE~(E1@ DHLLI   AD; |Mm M92Hp A~ I^0A~ t   H޿}   oH޿
   oH=Y	 6vh~ L:A~ A~ t A~ \A~ A~ L
   UoZIz1LΊHpHǅh    A H{W9hgL;L9u  M?L9N  LM  rDH-tI   e  H$E1ff.     AH$D9tfD9 uIcH@HHx1HDDLhEo DDodTt1ƅA~ t#HpDHLDDHxIE0HHHPH H  fH*AYh  xD LHpIM?ƅ L9 u9A~ t2Mf0A~ t   L}   amL
   TmhH{hΈAH ILLLLwHI    D EE1Mf     ƅA~ tDHLLM'M9t#f     LHDL_M$$M9uA~ t2Mf0A~ t   L}   jlL
   ]lI   AD;(iH H	 @   1LsL~H0T| HLL	 4H    DH	    L1*LY^A~ HL   LHI	 Hy	    PEN@La	 1X*A_Z7~ Lt LHDLM$$M9D  HƃfHH	H*Xaf.     L      H=M	 JfHI    8A   AGgIG0HPHH?  I   Lǅ    DE   LhLHxLXE1fIcLE1Ht$15DE   HxLcLpKI I$L9toLL4tHAH   D;(|LhLXLHx(g |HP
   ifD  HpHhDHSHxKfoDfoDT$@Hǅx    E1HpE1ff.     DHLLI   AD; |L
   LhL      H=ʺ
 GHLH	 HHH     L1l'LL'   LhANLL~H	    L1+'LL      LH=v	 DGA~ L  	~ 2L      H=
 GHpƅ~ƅA~ tL1HLLLM*M9I   H  IE I9H I9usH	 @   1贳LH	 @   H}   膳} I  HEE1D  HA8 tDL	 L1HE
    %ANL   DhE1fff.     I  JH   fH*^> f(H^	    \L   xF%xY< ^,HcHigfffH!)ЉHE1fD  L#   AfA9uL
   I	fE9nL/DhL	 DL1H	    $HfHH	H*XMfDE~)E1D  DHLLOI   AD; |Mm M9umL      H=	 hDHH	 LA   PL	    Hܢ	 >HHP
 LLPA      H 	 jL	    H	 P1#LH A~       L1LA	 Hr	 Li#Lx  /  HHHl  LHr	 L      H=	 ZCff5; I*FpI*VhH	 L   ^H߾   XfI~fI*   ^fI*NxXfI~BfInLHC	       "fInľ   LH6	    p"1vL      H=	 BHP.      H=v
 iBL      LH=6	 DBLHٺ      H=U	 B)HH@H	Ht6HtLH	 8E1LHH	 HuM   I$1Hؠ	 L   Lf!xLMD$LMLMdILHHC	 L1   H!I9uLMLL<"LH:	 H5	 WfUHHdH%(   HE1HO(   HEdH+%(   u!    UHHdH%(   HE1O;HEdH+%(   u!ff.     UHHdH%(   HE1O;HEdH+%(   uk!ff.     UHHdH%(   HE1O<HEdH+%(   u+!ff.     UHHdH%(   HE1O<HEdH+%(   u ff.     UHHdH%(   HE1O<HEdH+%(   u ff.     UHAWAVAUDATSH(dH%(   H]H5HE]H   HHIYÅuHI$D=G} HELpLM*  DDAL1uǅyXAu
-8t8L;HEdH+%(      H([A\A]A^A_]    G}     E1널KJHEDL*  AH<LM1F} tǅxJ@ 蛹8eecYf     UHAVAUATSH0  dH%(   HE1Z+H  1HHzHA詝H5	 DZAƅu+   HUdH+%(      He[A\A]A^]fD  1IH   ~}G| H/?	 Hǅ    HfHnfl)XfHHtXHMM H   PL	 1      HkHDAXZE7At@ 1+@ UHAWAVAUDATSH(dH%(   H]H63HEH   HHIVÅuHI$D=E} HELpLM*  DDAL1~rǅyXAu
蝷8t8L諞HEdH+%(      H([A\A]A^A_]    D}     E1널GHEDL*  AH<LM1^D} qǅxG@ 8eecf     UHAVAUATSH0  dH%(   HE1(H  1HHwHAH5	 DZAƅu+   HUdH+%(      He[A\A]A^]fD  1qIH   ~D| H<	 Hǅ    HfHnfl)XfHHtXHMM H   PL	 1      HhHDAXZE7At@ 1+@ UHAWAVAUDATSH(dH%(   H]H0HE=H   HHISÅuHI$D=}B} HELpLM*  DDAL1oǅyXAu
8t8LHEdH+%(      H([A\A]A^A_]    A}     E1널+EHEDL*  AH<LM1A} aoǅxD@ {8eec9f     UHAVAUATSH0  dH%(   HE1:&H  1HHduHA艘H5	 DZAƅu+   HUdH+%(      He[A\A]A^]fD  1IH   ~]B| H:	 Hǅ    HfHnfl)XfHHtXHMM H   PLi	 1      HgfHDAXZE7At@ 1+@ UHAWAVAUDATSH(dH%(   H]H.HEH   HHIfQÅuHI$D=?} HELpLM*  DDAL1^mǅyXAu
}8t8L苙HEdH+%(      H([A\A]A^A_]    n?}     E1널BHEDL*  AH;LM1>?} lǅxfB@ 8eecf     UHAVAUATSH0  dH%(   HE1#H  1HHrHAH5g	 DZAƅu+   HUdH+%(      He[A\A]A^]fD  1QIH   ~?| H7	 Hǅ    HfHnfl)XfHHtXHMM H   PLٕ	 1      HcHDAXZE7At@ 1+d@ UHAWAVAUDATSH(dH%(   H]H+HEH   HHINÅuHI$D=]=} HELpLM*  DDAL1jǅyXAu
8t8LHEdH+%(      H([A\A]A^A_]    <}     E1널@HEDL*  AH;LM1<} Ajǅx?~[8eecf     UHAVAUATSH0  dH%(   HE1!H  1HHDpHAiH5ד	 DZAƅu+   HUdH+%(      He[A\A]A^]fD  1IH   ~==| H4	 Hǅ    HfHnfl)XfHHtXHMM H   PLI	 1      HGaHDAXZE7At@ 1+@ UHAWAVAUDATSH(dH%(   H]H(HEH  HHIFLÅuHI$D=:} HELpLM*  DDAL1>hǅyXAu
]8t8LkHEdH+%(      H([A\A]A^A_]    N:}     E1널{=HELMD2:} *  ALHH(   1gǅxB=zD  ì8]][UHAVAUATSH0  dH%(   HE1H  1HHmHAِH5G	 DZAƅu+   HUdH+%(      He[A\A]A^]fD  11~IH   ~:| H_2	 Hǅ    HfHnfl)XfHHtXHMM H   PL	 1      H^HDAXZE7At@ 1+D@ UHHdH%(   HE1HEdH+%(   uff.     UHHdH%(   HE1HEdH+%(   uff.     UHHdH%(   HE1HEdH+%(   uff.     UHHdH%(   HE1HEdH+%(   u Kff.     U   HH   dH%(   HE1HhHǅd    HE    Hǅ`   M Ht`1HHPGkHP\e*  E11\AH`dǅx":    1HUdH+%(   upU   E1AHH   dH%(   HE1H`H`H*  E ǅd   E   cy#&8HUdH+%(   u    q9   D  UHHdH%(   HE1HEdH+%(   uff.     UHHdH%(   HE1HEdH+%(   u[f.     f.         UHAWAVIAUATSHH(F]HHu1dL$%(   LeIԈEoifyAF:萊L3AL95  HuLLQA   t	E~  M6L9uL+I9   f.     L(XIƋ     LXHI$5\  L;L9uo      M?L9\  LWI9uLWL9tM9ttI  I  1H9   f     ff.     H   H HcH	H9uH%   uAe9IE     H   IG(IF(IE(Mm L9HExK u@F   ^L#L9tDD  LDLM$$L9uHEdH+%(      H(H[A\A]A^A_]M AN;M6L9OtAe9IE     Ae;N L蘊LHaM{~2L#L9jIL$(LHH94H;J("fD  } :L#f     UHATSHDgpH   dH%(   H]HA   H   AtDcdH   H   Cd   H   HuH=#
 6BuCCdMA   9s/H7| 2{\    AAH
 11UPECd1HUdH+%(      H[A\]ÐCd    ~@ HDH   If.     9sH| A112H˟
 OECdH| H]
 101OcHi| Hr
 101OH
 11O	 ff.     UHAWAVATISH dL4%(   LuIH1H   LHlB   L{MtI|$葟   E1IHt1HdDLA   IUU̿*  DIAL1^ǅyhAt=A   8t21H߈EEEHUdH+%(   u>H [A\A^A_]D  1@ I|$1<dD` K3   @ ff.     UHATSHdH%(   HE1H   HLgH5p	 HFt/
   1H tAD$p1HUdH+%(   u]H[A\]ÐHuH= 
 @?HY| 2uMH)
 11MEHԝ
 11kM뛸     UHAWAVAUEATMSH8H| H}HuLuHUD   HMdL<%(   L}L}EuH ǃ      H        9             ?     j                        1HUdH+%(     He[A\A]A^A_]HLMEAWHUHuH}mZY   1AWEMAVHMHUHuH}/AXAY@ AWEMAVHuH}HMHU/^_@ AWEMAVHMHUHuH}AXAYr    HMELAWHuH}HUl^_   AWEMAVHMHUHuH}./AZA[-     HMELAWHUHuH}lAXAY   MAWEMAVHMHUHuH}.ZY%HMELAWHUHuH}lAZA[1   AWEMAVHuH}HMHUd.^_%HMELAWHUHuH}kAXAYfD  AWEMAVHMHUHuH}xAZA[    AWEMAVHMHUHuH}HZYAWEMAVHuH}HMHU ^_f     AWEMAVHMHUHuH}ZY>@ UHAUI    ATISHdH%(   H]H8Ht}H˦| L(HHL`z(tBHSHsfHnfHnHJfl@HK1HUdH+%(   u9H[A\A]]@ HSH{HKfHnfHnfl@H
뽸UHAUI    ATISHdH%(   H]H7Ht~H| L(HHL`z(tBHSHsHKfHnfHnfl@H
1HUdH+%(   u;H[A\A]]D  HSHsfHnfHnHJfl@HK뻸PUHH dH%(   HE1HtpH1| HA8 t61H}   H>	 זxCHEHUdH+%(   u4fD  u/   H}GHMDEHPHHEf1    UHL	 HAVAUATSHHHdL4%(   LuIHEIHt1HHHLEMtkIv-LM茕t/AV*I~Iv H)MIHtH+HA}HEdH+%(   uHL[A\A]A^]f1111 UHAVAUATSHdH%(   H]HH5	    HW  HOIHC  HHUH5	 WHH   E1f.     軈H5	 HI>   H5	 L>   H5q	 L>   H5	 L>   H5| LH@	 101`E1HUH5آ	 >WHHt
I\L{1HUdH+%(   uaH[A\A]A^]fD     Hd| B   IfD     f        f        뾸=fff.     UHAWIAVAUAATESHHHHudL4%(   LuLuHE    E    f   xrE   H  EHK-H}Hj	 H	 HDL+sM1   p   HEHUdH+%(   ]  He[A\A]A^A_]fH   H0  ?[t;H}DMHu*SHMHUMj DMHuH}ZZY   AP  AP  {$Af  L膄Efff.     Ht;Et6HEdH+%(      s(HeH{-[A\A]A^A_]     Hq| H uH}OH}HEyHEHJAǇP      f.     I   LEH}H|	 D  I   @ ff.     UHSH8dH%(   HE1HE    f      HH   Hth?[t{H}HuHU
Gufj HMHUA   HuH}j IZYt>ǃP      HEHUdH+%(   uTH] H   ?[uff.     P  P  {w1     f  H豂1     UHH dH%(   HEHH?Ht H| H;:tHExHEH     HEdH+%(   ufD  UEHHdH%(   HE1AQE1MHUdH+%(   un ff.     UHAUATI(   SHHdL,%(   LmIO0H&HHLhI$H      f.     H;XsHPHt!HH;XrHPHtOH1     HyfHAAHx@tI|$HEdH+%(   uMHL[A\A]]AFHyfHAAHxf.     HyfHA    AI<$QUHHdH%(   HEH@ HtHPH9s"H@HuHUdH+%(   u      H9sH@D  H@D  UHAUATSH(H_dL$%(   LeIHu&d@ CHEHxH}.Ht@HCHHE=LHHEHxI;|$uH}=H}LID$@ HEdH+%(   uH([A\A]]1UHAWAVIAUIATSHL   dL$%(   LeIM   A?[!L3C0   -HHH@L31A   fHnM1LflLCATSXZHEdH+%(   u!HeH[A\A]A^A_] L   o_@ ff.     UHAVAULoATSHHWdL4%(   LuIL9thHHZHLbHL5tID$IT$L9t>LbHKfHnH{flHJHC	H;HtG+t~D@ HEdH+%(   uHL[A\A]A^]sUIHHI dH<%(   H}HH   H   fff.     H;HsHPHt!HH;HrHPHtOH1     HWfHGG HP@tIPHEdH+%(   uMLHB     HWfHGG HPf.     HWfHG    G IfUHHdH%(   HEH@ HtHPH9s"H@HuHUdH+%(   u      H9sH@D  H5D  UHAVAUATSHH_dL,%(   LmIHuBfLLU?LMnHt(HLsI):HM;euL:IEfHEdH+%(   uH[A\A]A^]f.     f.     f.     UHAWAVAUATISH   HdH%(   HE1H=  H1fff.     ff.     HHHH)HHu?H HH} L<Mu   @ M?M   Iw LuIOIWIGHQH
Hj7} Hc7} H\7} HBIWIODAE;w8  IG(JHt$IW@IW0
   HH)&yHH)؉HEdH+%(     H   H[A\A]A^A_]f} H6}    fD  LsI6IFfInMnflHFH0IFIvAHHtHpfo Iv0I~ H)5b} AN~I~)I~(Lo0} '} @H=}    ~	H9d1L1 AŅ%  H0观  H   4IH   LABIG H   H!} E1E1H`IW@HHT
   H!HHӺ   .DIG0ZMw0I  Mg@E  McLE1MM9r[AG8       12IG(H   HLB}I 'Ln1f     HxAL9sL
   H)wHuAEo8Ic   i2HIG(HtL0LH    D9}LLpIMqM9s8L
   LL(L)vL(HuHLcJ    H`4} IGHU4} HN4} HBHC} IOH IWHIHtLxH H} } L<HIGIG@H}  Hi| L   1Hp	 016f.     Hǅ     H f     AG8       11IG(H=f.     H| L   H0p	 016    UHHdH%(   HE1G0	HUdH+%(   u?@ ff.     UAIHo	    HATIԺ   SH`H   dH%(   HE1譑HH`*7ufoA$HEdH+%(   uH   [A\]f     UfHAWAVAUATSHxHܘ| dH%(   H]H)pHǅ}    o )Eo@)Eo@ )E  IC@  HC(  oC0fuHEEI$  HUHsHBIHtL:  L   {TH`HI=H{HHp{zH`~P`LM$:  [E1fK @fopC) C<EfS*C(C,M   E1@ `L{H/	  L!7HEdH+%(     Hx[A\A]A^A_]    Ao$:  I$G  1C) fK @)pH}EfopfK*C<EC,C(LǇvHpLb S(Hs,H}yfHpH= E1*qEfopC) fK @C<EC,C(1fC*@ Hy| HKH   HɃ
 012fD  UHAVAUATSH_dL4%(   LuI   tX   IF(1f8IF(AVfPEFE~af.     I>HIN(HcӃfDQA;^|6    IF(   fIF(AVPIF(AVfPIF(AVfPHEdH+%(      H[A\A]A^]f     IF(      E1fIcFIV(HHfBIF(fpI>1fG5ffۍCIV(Iþ   AfH	tI>D/GI>XA9|RfD  UHAWAVAUATSH   H$ H8IHLLdH%(   HE1A   HHA1V   Lj	 H߹      R8XZ1H1褍Aą  Ǻ  H'DIoM  HH5j	 BƄ- .GH5I	 HHIHDGH5j	 HHIHDFH5|j	 HIHEHFƅ H  Mj  IM
   HHqrHt  HaD   H9HG   HHIHtItIvLHH)H)r1ANN9rD  A M   
   I}1UHM  
   I|$1_UHH1HUdH+%(   p  He[A\A]A^A_]fA      1HLG	    Hf6   @A2TfAT H)|    H
 01N.MH|    H
 01#.MHӋ|    H
 01- H5hh	 HDHfATATkHt| Hٿ   Hg	 01-HK| H~
 101s-ff.     UHAUA   ATISHHdH%(   HE11fD  HBHCHHЅxbJЃ	wUI$E1HHDPI$HSH;Suǀ{$    S uNSHs;X$H~gHSHHCfD  EutHEdH+%(   ulH[A\A]]    H}о   E   E~HHu n   C$릐~En    ۺff.     UHAWAVAATISHH@HWHGdL<%(   L}IH9  HJHK:o&  H9E  HQHS9m  H9  HJHK:a   H9  HqHs9i   H9  HVHS>n   E1^fff.     ff.     ff.     ff.     ff.     HJHKHr@	  K4LDrHH9uր{$    S   SHsLE;o"LEH  HSHHCC$Hxa     1HEdH+%(      H@H[A\A^A_] {$ uҋS G  SHs;!H   HKHHC$ uW u#SHs;!H~[HSHHC9   H}E   EHHt~(Eu~    f.     ~ n   C$@ {$ S u'SHs;9!H~HSHHC@ H}о   E   EHHt~EukfH}о   LEE   ERLEHH  }LE n   HKHCC$     fAulH9tHQHCHS9 tSHH9u{$ 
  S 
  SHsLE;T LEH
  HKHHCf.     HH9tHAHC9 tKHKHCH9u{$ uS   SHsLE;LEH  HKHHC멐   LELEA    V   H   fDAE1fAfDqLyHSfA(  fAuA  f.     HrHsHHЅ	zЃ	  KE1LDPHH;SuȀ{$ S   SHsHM;DMLE	HMHHSDMLEHHCs {$ S   SHsHM;DMLELEDMHHMFHSHHCHrHsHHЅ)zЃ	  KE1LDPHH9Sus {$ S   SHsHM;DMLE!HMHHSDMLEHHCHrHsHHЅzЃ	  KE1LDPHH;Sus H}о   E   E&HH+0EfD  {$ 6S    SHs;]HHKHHC@ {$ S   SHs;HHsHHC@ FEoLEzLE    $     H}о   E   E6HH;@E0fD  H}о   HMDMLEEE   LEDMHHMH  HMiyHM n   C$fD  H}о   LEE   ELEHHs  yLE n   C$ H}о   HMDMLEEE   BLEDMHHMH  HMxHM n   C$>fD  H}о   E   EHHE(fD  E @ƃ
@DAA   HCE18fD  HpHsHHЅzЃ	  KE1LDPHH9CuȀ{$ ~S 3  SHsHM;DMLEHMHHDHCDMLEHHSpE' @ƃ
@DAA   HCE18fD  HpHsHHЅzЃ	  KE1LDPHH9CuȀ{$ S   SHsHM;DMLEHMHH|HCDMLEHHSpH}о   HMDMLEEE   
LEDMHHMH*  HMvHM n   C$fD  E @ƃ
@DAA   HCE18fD  HpHsHHЅzЃ	  KE1LDPHH9CuȀ{$ S   SHsHM;DMLEHMHHTHCDMLEHHSpH}о   HMDMLEEE   LEDMHHMH2  HMiuHM n   C$fD  H}о   HMDMLEEE   LEDMHHMH  HM	uHM n   C$fD  Ew @ƃ
@aDAA   HCE18fD  HpHsHHЅ1zЃ	  KE1LDPHH9CuȀ{$ S   SHsHM;DMLE1HMHHHCDMLEHHSpE @ƃ
@DAA   HCE18fD  HpHsHHЅizЃ	  KE1LDPHH;CuȀ{$ >S   SHsHM;DMLEiHMHHHCDMLEHHSpH}о   HMDMLEEE   LEDMHHMH  HMsHM n   C$fD  H}о   LEE   EBLEHHs  rLE n   C$HSHC ELErLE    t     E @ƃ
@DAA   HCE18fD  HpHsHHЅzЃ		  KE1LDPHH9CuȀ{$ S .  SHsHM;DMLEHMHH\HCDMLEHHSpSEeHMqHM    1H}о   HMDMLEEE   LEDMHHMH  HMIqHM n   C$fD  sE5HMqHM    Q     H}о   HMDMLEEE   :LEDMHHMH"  HMpHM n   C$6fD  E' @ƃ
@DA A   HCE18fD  HpHsHHЅzЃ	  KE1LDPHH;CuȀ{$ S   SHsHM;DMLEHMHH|HCDMLEHHSpE_ @ƃ
@IDA A   HCE14fD  HpHsHHЅzЃ	wmKE1LDPHH;Cù{$ S o  SHsHM;DMLEHMHHHCDMLEHHStE t	
DA$HuHL}HMHM t	
cHELH߉A(HMHM t	
;HELH߉A,HMHM t	
HELH߉A0HMmHM t	
HELH߉A4HMEHM t	
HELH߉A8HMHM t	
HELH߉A<HMHM t	
sHELH߉A@HMHM t	
KHELH߉ADHMHM t	
#HELH߉AHHM}HM t	
HELH߉ALHMUHM t	
HELH߉APHM-HM t	
HELH߉ATHMHM t	
HELH߉AXHMHM t	
[HELH߉A\HMHM t	
3HELH߉A`HMHM t	
HELH߉AdHMeHM t	
HELH߉AhHM=HM t	
HELH߉AlHMHM t	
HELH߉ApHMHM t	
kHELH߉AtHMHM t	
CHELH߉AxHMHM t	
HELH߉A|HMuHM t	
HELH߉   HMJHM t	
HELH߉   HMHM t	
HELH߉   HMHM t	
rHELH߉   HMHM t	
GHELH߉   HMHM t	
HELH߉   HMsHM t	
HELH߉   HMHHM t	
HELH߉   HMHM t	
HELH߉   HMHM t	
pHEȉ   DaoH}о   HMDMLEEE   LEDMHHMH
  HMiHM n   C$ EHMWiHM         EMHM'iHM         E @ƃ
@DA A   HCE18fD  HpHsHHЅQzЃ	KE1LDPHH;CuȀ{$ &S [  SHsHM;DMLEQHMHHHCDMLEHHSpH}о   HMDMLEEE   LEDMHHMH  HMhHM n   C$~fD  H}о   HMDMLEEE   "LEDMHHMHb  HMgHM n   C$fD  E]HMogHM    aE t	
DA$HuHL}HM1HM t	
HELHHMA(	HM t	
HELHHMA,HM t	
_HELHHMA0HM t	
7HELHHMA4HM t	
HELHHMA8iHM t	
HELHHMA<AHM t	
HELHHMA@HM t	
HELHHMADHM t	
oHELHHMAHHM t	
GHELHHMALHM t	
HELHHMAPyHM t	
HELHHMATQHM t	
HELHHMAX)HM t	
HELHHMA\HM t	
HELHHMA`HM t	
WHELHHMAdHM t	
/HELHHMAhHM t	
HELHHMAlaHM t	
HELHHMAp9HM t	
HELHHMAtHM t	
HELHHMAxHM t	
gHELHHMA|HM t	
?HELHHM   HM t	
HELHHM   kHM t	
HELHHM   @HM t	
HELHHM   HM t	
HELHHM   HM t	
hHELHHM   HM t	
=HELHHM   HM t	
HELHHM   iHM t	
HELHHM   >HM t	
HELHHM   HM t	
HELHHM   HM t	
fHELHHM   HM t	
;HELHHM   HM t	
HELHHM   gHM t	
HELHHM   <HM t	
HELHHM   HM t	
HELHHM   HM t	
dHELHHM   HM t	
9HEȉ   f.     {EHMw`HM    Y     ELEG`LE    t     H}о   HMDMLEEE   jLEDMHHMH  HM_HM n   C$ffD  EUHM_HM    i     EHM_HM         EeHMW_HM    EHM/_HM    #EHM_HM    H0EUHM^HM     UIIȹ(   HHP  fo
 dH%(   HE1HHFHLHHǅHǅǅFAHUdH+%(   uff.     UHAWIAVAUIATSHHhH}HHxLpdL4%(   LuMHEL)L`AtJ;    IBD  AuE1HMHUHIE    AE    AE    AFE   BD fAEUk  HEI}LIEHxH4AV1J< H}LLHpF  H=IHU  E    f.     LLH   xuLxx.uA t؀x.uA.uA t@ HLHEHuHDH=  wHE|/t	/   f3LHlH}MHLpHxL,Ex%HEL 5LHMff.     LHEdH+%(   uXEHh[A\A]A^A_]He| Hٿ   H8	 018EHd| HA	    01Hd| Hٿ   HA	 01ff.     UHAVAUIATSH H^dL$%(   LeIt%1HUdH+%(     H [A\A]A^] LuLuLuL.uMu Hh| A`   z#    H
   HKH1fCID$HHMPuID$H}@fCIU HSIEH)HCID$@CA`  I   HPN8fc1HC<    fC( C,It$vIL$IT$HI<$    (   HK(1fCID$HHMPID$H}@fCIU HSIEH)HCID$@CA`  I   HP7fw    UfHAWAVAUATSHHHH}UHMdL<%(   L}MFEpA   E   DsH{   8AW1L`IJ|#߿AGLHHMH}BD fCEChuTHEdH+%(   uMHHD[A\A]A^A_] HMHS1LMLEuDuVf.     Ac UHAWAVAUATSH8H}LELMdH%(   HE1H   R   u&HUdH+%(      H8[A\A]A^A_]@ AAQH1HAE1H   ƾDc1HC   DkLkHDMt O
LDHqAWIH;SrHU   HHMH}BfEf fC
C1;T@ UHAWAVAUATSH   H$ H   H$ H   EHpIlL`LkdH%(   HEHc| ǅ    HXHtHHHtD`E  L    L<	        LPPHLH(1	11L1^ZY  Hi@B    LMAE 
   MHHHHxhƅ Hi ʚ;HH        AFH 1A   @ IFHcHH	HE1IFL9  HK@  PЃ	vȍP  IVWHHH	Hـ   MnH   AFH 
  Hx   莼Hi ʚ;HH+H9  HAV@IF8    xD@fAFuk  fAFA~H   tHXHcLH9  LHIVHHHI)VHI| PHH)fAVV1H?HFfAFlAFAFHb| x# Z  H`HLHpe   E1䋽jHEdH+%(   ;  HeD[A\A]A^A_]D  PwhIV7HHH	     L}H  LM<HK ff.     Hh     Eu-uH1A   HfD  IFHcHH	HE1IFI9tSHZxxPЃ	vЍPwIVWHHH	fD  PwSIV7HHH	fD      LHx  LM<HZyfHHHE AF@    L9  HAr  -   L9   HH w   -L9  HAx  -   L9  HP su  p      AFDL9  HJ: aH1   IIF HcHH	L1IF M9   LjO  PЃ	vɍPwdIV WHHH	HHfAN@(AN@L9    LH~8M<LHHP6  IV 7HHH	JLƅH    LHHH2  M<LG    LH  M<LAN@r       LH@HH  M<LLƅH    LHM<L    LHM<LLb YL1MI̹       HHcH	L1M9t?L` xgPЃ	vٍPwWHHH	͍PwL7HHH	뷋    L$H   M| LLMLM:A^(HI1۹   HHH	L1M9t?L`xBЃ	vڍBwBHHH	͍BwOBHHH	뷋    LjH~M| LLƅMLM A^,H1Hƅ6HXH H~  HЃ	IF0ƅ HHTBHIV0I9u    LH~GM<LHV| L   Hy3	 A01至ƅL(AFH Hƅ    LQH,M<LHX     HI9u    HDHsJ
 1HH(H>V| E01rfAN ƅA~H %P AFHP AFK1LP AND   AFHP AFK AHAFH (HمLPLMILh xKHڅtS
tNHZHL)H  ;CLM9uˋ    LH~-M<LLPLL MLPƅLPL{ff.     UHAWAVAUMATSDÉH8LuLeHuHMu(M uHLMLdL%(   LEMtxHuMMLAOx[D9u6} t0EHDMMLPHuPDZY
     1HUdH+%(   uHe[A\A]A^A_]ø@ UHAWAVAUATSH   H$ H  HELe HHEHHHE(H E0DdH%(   HE1E  IMtEL$E	  H   L0	       HPML$(1ZH  	 1RHǅH    @_AX  HX1HD  ff.     ff.     H  HPGƅ/ HHPGH)GHH0	wH8H
   <IH88 n  fDCE|$ǅ4A  E:  D{H{   H;	HAT$1HHHHHկAD$1LHDkD4fCAT$H 蜯E9fAnL⋍fAnǾ    A   fAvHLAEfnHfbfbflAFAD$ fAF   LMDDHH   HHLH   D9tKHHH$L@`  1   LHH~bLPL /t  tHDMPLHH@ZYgf@HEdH+%(     He[A\A]A^A_] HSH0DL/L4YD0D  LLEHMDLL;ÃkHMMDL薿IA9@  3HEdH+%(   u=LMዕHEHHe[A\A]A^A_]\?'    UHAWAVAUMATSHXH}DrHuHc]HUI~ MDEdL$%(   LeDeHEH  IH  }HEH  I~ gIH   I   OHH   E~HEA    I| G0	wS
   HHuHU: u8UHA   ARURLuuuHMHuH}0H0HA9HMH1%'L'H}'H}'HEdH+%(   uHe؉[A\A]A^A_]û诪볻봻f.     UHHDG(OdH%(   HE1HWHwHAPDG,APLO DGH)HEdH+%(   u11UHAWAVAUATSH   H$ HHELJ(I   IHӾ   H   EdH%(   HE1L8*	 HH1HH+J  A  A|     D9DNIcHHHH  H0   HH  AE  AOH  ELHH	HL	HH	HL	HH	HL	HH	DfHnHNH<fD fDHfDL\>f@ LiH   LXLiLiL0L`LaLaH8HhHYHYfD@fDpfDAfyHHHxHAHAL9uDA  HcDDGHIHL,LdH\D\DtHD E9  DGLl0Ld8H\@D\HDtIHDPE9o  DGLl`LdhH\pD\xDtyH   E9A  DGL   L   H   D   D   H   E9  DGL   L   H   D   D   H   E9  DGL   L   H   D  D	  H  E9   DGL   L(  H0  D8  D9  H@  E9~hLP  LX  H`  Dh  Di  Hp  A9~0L  L  H  D  D  H    JD@  fAnHF(   fp fofnH<fs fp foE
 HH|>(ff.     fofofoH   fs ffffpfpfbfofbfjf֠@pfHHH9uAA   IcEQH<@DAHDD>(D>,D9~_DEQDD>XD>\D9~JDEQD>   >   D9~/E AAD>   D>   9~CD>   >   A9  ALcLDEH<@A)HA@HEH  EKILc(O
HO[H(IM9}H,H9  fnEH   Afo
 fnfp fnOIfp fp fn(IfIfp fnfDp fofs fD  fofDoH   fffofs fffpfpfbfofAfDbfjfDֈ@DpfHHL9uAtiABLcOIIB\(DG(AFD,D@E9~5B\XA)DG(AFD\A9~B   )G(B   LHIIMI\ @ II0L9   1LHKL3tMAfD  I?1IL9uLHLc1LItD  HHHI9uHHEdH+%(     HeD[A\A]A^A_]    11E1Ʌo@ MAMD  HLELPj LAXZ<D  T   *A0fD  KIDHHT(1fD
DG(H0DHADBL9ubcU1bE1E1H1E1A>AA     UHAWAVATSH   H$ H   H$ HpdH%(   HE1H   HS   u)HUdH+%(      Hp   [A\A^A_]fD  II׾   H	 H芚xmH      H5 H)HHxMMHHxHH/V    1HHRC| H7
    01}" ff.     UHATSH0HG| L`  dH%(   H]HHURx#H}HHE     HuH(  HEHtLH1{LH5D@fBHU$H}؉yHEdH+%(   u.H0[A\]HhB|    H7
 01    UHAWAVAUATSHHXH}DqHUHMI~ DEdL,%(   LmEzH  IH  IbHEH  I~ LHEHk  I   3HHL  sUAE1-  MUHED  AD9{
  DHLAEPEPuuLMHMHUHu>H Aƅ   El$DH_A9tC~& El$DH@A9wAD9s݋ELPEPuuLMED$HMHUHuH 6fD  H}H}H}LxHEdH+%(   uHe؉[A\A]A^A_]H}1벻봻붻@ ff.     UHHdH%(   HE1Ht BuHEdH+%(   u&1fD  HEdH+%(   uEd菜@ ff.     UHHdH%(   HE1HEdH+%(   u1Mfff.     UHAWAVAUATSH(H}Lh  dH%(   HEHC| x#Hۃ M  LII6IH8   AGH(  HH{  1AHC| D@fCIE MO0H y#    H   H{(HPLV    1   AWHHHD(fCIE H@HC I$HSID$H)HCAGCXZH}LLH貼HA7E   HEdH+%(      H}HeLL[A\A]A^A_]ާfD  HH{HH   PL    1
   AWLHHHHDHfCIE H@HC I$HSID$H)к   HCAGC謪Y^!H~=| H/2
    01f     Af.     HEdH+%(   uHeD[A\A]A^A_]f.     UHAWAVAUIATSH8H}HUHMdH%(   HEȋF@   HcHEH    I   HfXIcEHAAE~ULaE1L5n	 fDLDLHIDAH輿L   HHIID$E9}LuH}1HMLUL-HEdH+%(   uH8[A\A]A^A_]ûјUfHAWIAVAUATSHHhHMH}HdH%(   HE1EHuHE    1LAĉELfAEDDmLDDuPDD)UD)9   HIcHL|	HHHPI9r5 u,HE   HLxLIMu%XfIIILIMtAJ   IFH}fE~HEL}胪H}HM1LLHEdH+%(   u:Hh[A\A]A^A_]f.        E   A   YIx,ff.     UHAVIAUIATISH HMdH<%(   H}ؿP   	H   fo
 HL1 K   P   HMHfCCA$HC    HCAD$8HC0   HC(AD$HC@   HC8AD$HCHAHAHEdH+%(   uH D[A\A]A^]A@UHH@Ao dH%(   HEHL     0 HMHMuHuU1EHEI@HEAHUdH+%(   uؕ     UHH dH%(   HEHHuHuHM      HMLHU1HUdH+%(   u}fff.     UHH%   HH0HdH<%(   H}HHHH@HTHBHE@HBHE@HBHE@@HBHE   HBHE@ƀHBHE   HBHE@tEHBH@HD@HBHEHZ  HHHHH  H@ tH   H HT   tA\HT   tH   H H@HT   t(H   HHtH8     ff.         tH   HH|HHEHB @ HE   HBHE   HBHE   tH   HHtH8    D  HB   HE    HBHE  @ HBHE   HBHE   tH(  HTHEdH+%(   uwHHzHHHD@ HxHuHMHU)HUHuHMHfD  HxHuHMHU)HUHuHMH.ْf     UHAVAUATSHH dL$%(   LeIHO   tID$ HOHGtI$HHAtID$HHAtID$HHAtID$HHA@tID$ HHAtID$(HHAÀtAD$XHHAtID$0HHA   I$  HAH1    I$   HA#  I$  HHAA$  HMII~uI$  E1EHHQIHHJDJDHH)I)Dr1AOt N4
9rLLAE;$  |ff.      W  y    t`I$   LiH  H H  HI$   Hx'LH    I$   HHMHpHML tM$   HLiM   @ tID$8   !  HHǀtID$`HHA   tID$@HHA   tcI$   LiH  H H  HI$   Hx&LH    I$   HHMHpHML@    tID$hHHA    tI$   HHA  @ tID$pHHA   tID$xHHA   ]  HEdH+%(     H 1[A\A]A^] HA$   H H	HA$   H0H	   tI$  HAHAI$  HHHI$   HHHP f     I$   HHL,   LJ(AT$\HyI$   HAD$\HaI$   HHH@L,   LTJ(6 H    LYf     H    LqI$(  HyHI$0      I$   HLN,(JL(E    t[I$  HA@ ff.     H    I$   HA}I$  HAHAlfD  HS UHHdH%(   HE1H@tHBHHG@tHJHHH@@tHJ HHH   tHJ(HHH@ƀtJXHHH   tHR HHP)HUdH+%(   u謌ff.     UHAWAVAUATSHxH}L"HuHMdH%(   HE1L9  L1f     ff.     ff.     H9rA$   HM$$HL9u1H  HQ/| H|	    HM01xHMT  H9HMHFH<vHuHHIH!  HUHM E   HPM$M9  IHxMLIHUE1IEME1HEH1fEH9sXM?HI9uHx1MHΉHHEDINH}1fAFHMLUM  f.     A   tHpE1HMHhX@ Hcp HrHp$Hr Hcp(Hr(Hcp,HA	LIHHUIt H@0IDA;      L;ur>1EEfE}HM1LH}fAEU   HEH)xE1E1I   LH}HH4LHUHrJHUH5LEHUdH+%(   ufHx[A\A]A^A_]fHpHMEHhnfD  MLEED  1H1HHh薉fD  UHHdH%(   HE1HEdH+%(   u	E1*X     UHAWAVIAUMATISDH8ED}HuHMEdH%(   HE1   I|$ tAHEdH+%(      HuH}H8EDL[LA\A]A^A_]D  I<$ uA|$  u1I|$ u)1HUdH+%(      H8[A\A]A^A_]D  HEdH+%(   uDMH}H8E[LA\LA]A^A_]AHz+| Hk 
 133H 
 113H 
 113H 
 11tKD  UEHHdH%(   HE1AQDHAPL/| H1(HUdH+%(   u菇@ ff.     UHAWAVAUIATSH(HUH}dH<%(   H}Hp  wII   Mg0IL0LJHøHtGN   IWH{fDcHC    LsIp  H}11HUH߉E	EHUdH+%(   uH([A\A]A^A_]賆 UHAWI0   AVIAUATSH(H   dL$%(   LeIL(葻HøHtD0   N   11fCHLHC   LkAh  CAH߉ESEHUdH+%(   uH([A\A]A^A_]fff.     UHAWAVAUIATSH(HUH}dH<%(   H}HHII   Mg0IL0L趺HøHtGN   IWH{fDcHC   LsI(  H}11HUH߉EuEHUdH+%(   uH([A\A]A^A_]@ ff.     UfHAWAVAUATSHHhHUL   H}LdH%(   HE1EHE    L}1LAŉELfAEDDuLDDeDD)UD)9   HIcHL|	HHHPI9r1 u(HE   HLxL=I     IIILIM   IFH}L}AN   fE~IF   HEH   H IF詖H}11LULHEdH+%(   u8Hh[A\A]A^A_]Ð    E   A    艸IhUD  UHAVAUATSH dH%(   H]HH9l  IIIքt5  fH    tLHL؆V  HI9*  	   tHp  Ht8 tLHL:9  H
 f.h  ztLHLntH%| H
 1M̋01M   LHL2xH    tLHL   LHL輡   HI9tT	   tHp  Ht8 tLHLdxgv
 f.h  hv]D  1HEdH+%(   uuH [A\A]A^]H$| H
 1M̋01MH$| H
 1M̋01M렉EH$| H
 101M|-fff.     UHAWL<    AVIAUIATM   SH(H}LLEdH%(   HE1H   AoHLLA@AoF@AoF @(AoF0@8AoF@@HAoFP@XAoF`@hAoFp@xAo      @H|a@   fDcI  v-HeHEdH+%(   u1H(D[A\A]A^A_]@ H}11HUAAUHAVAUATSH dH%(   H]HH9t`IIID  HI9tH   HsMLH   $t؉EH"| H7
    01M@ 1HEdH+%(   uH [A\A]A^]C UHAWAVAUATSH   H$ H   HHH׺   AdL,%(   LmIH   Hǅ    I1Hǅ    HHǅB   H   fHZHI߉I)1AL蚴f11HPL)P)`DX)pu#HUdH+%(   uHĘ  [A\A]A^A_]ø$~@ UHAWAVAUATSH   H$ H   LPLEIH`LhHxHXDLdL4%(   LuLuLH  1HHX,IHHHpJLh   HpA@8HGH   .  tA0@7  Lf$  LIWHǅC   f fAE貄HPHt1  Hp(HxH x-   fHxH`LHXHUdH+%(      HĘ  [A\A]A^A_]fI0HIt HtHH)I)ȃ
1ɉσM8L>9rfD  A0At tf     At ftH)| 112Hc U4{fD  UHAWAVAUATSH   H$ H   D]DUHE H]0Lm8H0}@HxHu(\}HL8DDDHDLH(H HhH`XHpdL4%(   LuLuPL<1H  HL`PHLHHPHpAMǅ
   DDHPHDHDLHhfA @H`fDfL8DDHHvƅHs/>  tOAU t?ATfT2D  IU HLHITHTH)H)H\   H9ӉHGڋXHs+   t9At*ATfTHLILHLKHA  Ip(HxJ%x1   fH(HHxH0 HUdH+%(   umHĸ  [A\A]A^A_]AU ATT     AۉATTRH | 112H: ,xUHAVIAUIATSHH dL$%(   LeIEtLLHDEDE̅   ALLHIu(1LH~xRIu1LH9x=1LLHuE1ɅxNHEdH+%(      H D[A\A]A^] EH| H
 101<DMfD  EH| H[ 101DMfD  EH| H 101DMe^w ff.     UfHAWAVIAUATISHhH}HxdH%(   HEH&&} )E)E)E HG  HH!H诸HEHl  LeI H   LH]=      HEL-| HE[    HE1H}H@     P   LxHUfP1Hux   S   LHc5{=   |LcKID x! tBHE   H}LuH}zHS| H    01~@ H1| ٿ   H
 01ZmD  HE   H}1fP1H@"    P   HuxH}EEHUdH+%(   uHh[A\A]A^A_]øjuf.     UHAWIAVAUIATSH(HUL(  HLdL4%(   LuIÅxyLLLL   Lut)HEx#    pLLLoÅ   HEdH+%(      H([A\A]A^A_]D  H| H2 101D  EH| H
 101]    Hx_g     Hw| H
 101襹Wtff.     UHAUATSHdH%(   HE1H   H}E1H5	 H}HH   H5 H5   H5 HtzH5P H   H5 HuAf.     H5 HѱuAd@ H5ϙ H豱u5AD@ E1HEdH+%(   uHD[A\A]]A   Arff.     UHAWAVAUATSH   H$ H   H$ H   H$ H  HHHHdH%(   HE1褚L]    HI   1   H芿11H1  Lƅ4 E11fInML ǅ    flǅ0    Hǅ    "f.     IcA@A
   LM9  D0LhDE   A   uHH   DejH  fo@HA   foPDfo`D fopD0foD@foDPfoD`foDp1H뀈@A
"f.     ƅ ILIcHN<2HIwiIH  J<0HL@LC< M   Aff.     HEdH+%(   k   H1  D[A\A]A^A_]D  H     H]  H L<HL BfD  H5 L  H5 L  H5 L   ǅ   f  L Hǅ    	  LMIE1E1      IcAD@
   LM9|  LxAم   A   uHI$   gH  fo@DHA   B foPBD fo`BD  fopBD 0foBD @foBD PfoBD `foBD p1ID@
 LLLEMIIcHN:HIrLgIH  HLJ<8A LC MoLrfǅ      f(D  H     H薪H  L4HL Nf.     I|$

   1/HI9s  IuH(    AE <ct&<d  A0    H   H HHt U   H   H fCHHCH H9   LnL(>p   I9  A} u   IE1A   /    IM HʅxtqI	<  KE1L|JL9uӋ0   LL(H~#LH 2 n   ff.     H( ǅ      fH0D.  HDH 褨H~H HH H8   8 ǅ<   HH@Q> Y    .fD  E E1f  fH    u-   Iu U  ~I	{	  K1LtNL9uӋ0D  LDL萧H  LH 둋0D
  LDLNH  LH Iu   ~I	  K1LtNL9uHE| HMD$1H A01a   L     L赦Hu  LHH H(XI     HHL贂HH2LEMtDL.ht$H11HH߅   FH(4H; t/HpH(    <c<duX        0uHHHH 营H~TH HHqH H(H8   8ǅ<   ɕHHu1] n   E1PE1<F~>P    D  0D  LDLäHLH 
Iƅ4LƅH8   D8ǅ<   HH    n   UH    (Iu   ~I	  K1LtNL9uӋ0D  LDLH
   LH H8   D8ǅ<   6HH    n   >     x     LLEMƅ4LIƅH	| H1AH 
 01衫H  
DsE1   (Iu v  ~I	   K1LtNL9uӋ0D-  LDL葢H  LH H pH8   D8Dǅ<   ǒHHY    >D=H      H  
DsE1   (Iu   ~I	  K1LtNI9uӋ0D  LDL}H  LH H \H8   D8Dǅ<   賑HH  v  >D)H         H8   D8Dǅ<   GHH    >DH      H |H8   D8Dǅ<   ӐHHh    >DIH         H  
DsE1   (Iu   ~I	  K1LtNL9uӋ0DO  LDL腟HD  LH H dLE1E1HfIcAD@
   I9   A] IAޅ   A   uHI   HZH  fo@HA   HB8foPBD8fo`BD8 fopBD80foBD8@foBD8PfoBD8`foBD8pI1LHH C 
/DsE1   $Iu %  ~I	wxK1LtNL9u׋0D  LDL˝H  LH >     H  
mDsE1   +IM Hʅ  qI	  K1LtJL9uЋ0  LLHu  LH H H  n   H  
Ds E1   +IM Hʅ
  qI	  K1LtJL9uЋ0u8LLDH  LH H #H8   8ǅ<   |HH  Y  >uH     D  H  
DsE1   'IM Hʅ%  qI	wsK1LtJL9uԋ0  LL8H  LH >H  n   H  H  @ƃ
@Ds M   E1+IU Hх  rI		  K1LdQI9uЋ0  LLoHi  LH H NH8   D8Dǅ<   襊HHi  T  >DcH     f     H  n   H8   D8Dǅ<    HH    >DH     d@ H8   8ǅ<   蹉HH
    >0H     fD  H8   D8Dǅ<   OHH
    >DH      H  @ƃ
@kDs M   E1'IU Hх   rI	wPK1LdQL9uԋ0V  LLH  LH 딄LH M 
{$E1   +IU Hх  rI	9  K1LdQL9uЋ0u;LLaH
  LH H M=H8   8ǅ<   薇HH	  	  >zH M         H H8   8ǅ<   HH	  n	  >_H M    _LH MJ 
6{(M   E1+IU Hх  rI	  K1LdQL9uЋ0#  LL˕H  LH H MH%H  n   H8   8ǅ<   ؅HH  /  >OH M    f.     +H  n   H  @ƃ
@Ds$M   E1'IU Hх   rI	wPK1LdQL9uԋ0  LLlH}  LH 딄LH MB 
.{(E1   +IU Hхw  rI	   K1LdQL9uЋ0u;LLʓH  LH H MH8   8ǅ<   HH    >zvH M    AMH / 
Ds,M   E1+IU Hх  rI	W  K1LdQI9uЋ0   LL诒H;
  LH H MH8   8ǅ<   HH   	  >[H M    &H8   8ǅ<   HHf  Q  >H M    H M n   H LH M 
r{$E1   'IU Hх   rI	wPK1LdQL9uԋ0  LLH  LH 딄LH M 
{(E1   +IU Hхy  rI	   K1LdQI9uЋ0u;LLlH  LH H MHH8   8ǅ<   血HH    >zH M    LH M 
{,M   E1+IU HхK  rI	  K1LdQL9uЋ0n  LLOH?  LH H M+H8   8ǅ<   HHt  _  >H M    fD  H MH  n   H  n   H M n   iH  n   RH8   8ǅ<   ~HHtK   >&H     @ H  n   H  n   H H H H H H zH nH bH MSnH M n   9H M*H H M*H M n   H MH MOH H MH M n   H MH M n   tH MeH MVHE1Aq]H 0H M!<H M n   H MH8   8ǅ<   Q|HH  s  >GH M    LH M~ 
jH{0E1   +IU Hх  rI	   K1LdQI9uЋ0uFLLH~LH H MH MH8   8ǅ<   /{HHn  Y  >oH M    qLH M\ 
HH{8E1   5IU IuH(Hх;  zЃ	   KI1LdQL9uƋ0uFLLىH~LH H MH MH8   8ǅ<   zHH      >ozH M    EH M6QH M n   MH 
 t	
Ls@D{fCH MH MH M n   H H H MH M n   kH M\H MMH M>YH M n   $H H M	H H MLH M 
H{0E1   +IU Hх  rI	   K1LdQL9uЋ0uFLL`H~LH H M@H M1H8   8ǅ<   wHH  q  >oH M    H H LH M 
H{8E1   5IU IuH(Hх   zЃ	   KI1LdQL9uƋ0uFLLH~LH H MH MH8   8ǅ<   FvHH      >oH M    H MyH M n   _LMH I=BH M3H M$?H M n   
LH M 
{,E1   +IU Hх	  rI	Z  K1LdQI9uЋ0uFLL}H~LH H M]H MNH8   8ǅ<   tHH    >oH M    H MH H MH8   8ǅ<   tHH|  g  >H M    ZLH ME 
1H{0E1   +IU Hх  rI	  K1LdQI9uЋ0uFLL̂H~LH H MH MH8   8ǅ<   rHHs  ^  >omH M    8H ,H  H M,H M n   LH M 
H{8E1   1IU IuH(HхxjzЃ	KI1LdQI9uʋ0   LL_H~|LH H M?H M0H M!<H M n   H MH M n   H MH8   8ǅ<   (qHHt/~G>H M    rH M n   XH MIf     UHAVSH   H$ H   dH%(   HE1(tHH?HPOt+1HUdH+%(      HĠ  [A^]f.     H tL1      HL    ߏH蓯u@H;HtH{ HL1Hj	 01هVH{ H2tH	 11誇H	 11蘇BUHAVSH   dH%(   H]HH{(tH  B 1wA|   DC1HUdH+%(     Hİ   [A^]    s$%   HPǉLDL   {" tDHEHc  HC념H{ HKH 101賆H{vZltDHL@9LDHtH.{ HKH	 1DL01QDLDRkHKH 1D0H{ 01H{ At,11HQ	 E>EAfD  H{H5 LtLH		 11谅 L1H| 1蒅HK{ H	 101yH-{ HKHJ	 1DL01PDL?@ ff.     UHAUATSHLo8dH%(   HU؋W@~@HcH@HMdI\BH@HI)@ {iHHtL9uHEdH+%(   uHL[A\A]]V!?UHAWAVAUATSH(H}udH%(   HE1E    ! 6  HcƉH<@HsIHU  IE1~{HEE   LHI H1ly$   HË ucH}tTI<$1  B  xE    AIAD$D9uuHEME1H@0   Lx8H@WfD  AEt=IcH@HMlI\AFH@HI)ŋ{xhHH<sL9uLHEdH+%(   uWH(D[A\A]A^A_]H{ A+   H1 H2    AH81.<AXAd=@ UHAWAVAUATSH   H$ H   dH%(   HEHG0H  I! 7  Ha  H?SGIHC  ǅ     Hǅ(    fLH  HLx1   AWM$   LcG    H݉H0HڃZYuH%   =   u   H5 Lv H($HH@HHH5H  HHH(L|IH   H11   AGH`L$IG HL8pH(H   ID$8 AD$@1HEdH+%(   %  He؉[A\A]A^A_]úL$o$Hc H(H@LaH@ ff.     {$eHHfpL9㋕$uH($$XH/{ Ag   Ha H/0    H81d9$H{ H0 Ak   H&    H8109  LnXI:f     U1HSH   H(dH%(   H]HHs  8-   C  C# HE  {(  C!H   1H{   Hs   S(uH;  莐   H~   1HUdH+%(   v  H] x \{#    {(HF ׉LH5i HDa1LHHC(  C      C! Hf     HHCH  HEdH+%(      HH] KSC /D  C(    HPLLuh%   =   HC  C# HVH HGH;HPh%   = @  C!2fD  H; V7SC# \UHSHdH%(   H]H! uMH{m{# tHEdH+%(   u9H{H]<HEdH+%(   u{H]b@ HXa7UHATIHSHdH%(   H]HA|$# tKIL$   HHuHHUdH+%(   uGH[A\]I|$FHfD  HEdH+%(   uAD$HH[A\]m6fff.     UHHdH%(   HE1HEdH+%(   u	nx6     UHHH dH4%(   HuHր# t;HO   HHu&UHHHDEHUdH+%(   u&D  HUdH+%(   uHHH15ff.     UHAVAUATSHdH%(   HE1(  MAHHIIH
 L   ^   I4$H;u6EtVDcHEdH+%(      HD[A\A]A^]f.     HM$1H Hi{ 01zEu{_H;Aąx{1LGHuL   H D H{ 01AGzUfAHD  A84UHHdH%(   HUHWH0 t(HcO@~ HG8HIHH@ HHH9uHEdH+%(   uH;4ff.     UHATSHdH%(   HE1! t\LIHL    HHL%HcH9s-x)HEdH+%(   u7HL  [A\]饊D  HEdH+%(   uH[A\]3 ff.     UHATSHdH%(   HE1=HtcHD  HhHt#Hx	   H5) ޱtA   fE1HgHEdH+%(   uHD[A\]2E1UHH   dH%(   HE1! t\HH´    HXx=HXH`yHXuHUdH+%(   ufD  H蠮1g2    UHH   dH%(   HE1! t\HA   HXH9 x:HXH`WyHXuHUdH+%(   u H11    UHATSHdH4%(   HuH5Y? HtQH}H   Hþ   E1wHvH}`AH]6HEdH+%(   uHD[A\]E1H1     U1HHdH%(   HMHvH+y	HHHH1HHHHHUdH+%(   u0     UHHdH%(   HE1~! tHFH)H#~HHVHHH!HHHH~HHHUdH+%(   up0U'  HHdH%(   HUW
D  tlG4FG2fHG@HFHGPHFHGXHFG(F G(F!ЋW9uu~  t61HUdH+%(   u,H{ HY	    01;u̸/     UHAWAVATSH   H$ HĀdH%(   HE1IIH	  HHO     8 HM   ILH`InR   t)HUdH+%(      HĀ  [A\A^A_]fD  H1{ H	    01\tdL1ohHLH`HHxHfA^    1Pl.ff.     UHHdH%(   HE1HEdH+%(   u1-.fff.     UHD HAVAUATISH   HHOHdH%(   HE1,IL$   HLcH 1r,IL$   HLcH 1T,MLcMfA|$ w*HEdH+%(      HL[A\A]A^]    IL$    H1Hѯ +IL$(   HHү Lc1+AL$0   HHH̯ I1+M   HAL$1LcH 1M+LcO4(K,     U   HAWAVHAUATSH8  dH%(   HE1Hǅ    Hǅ8    Hǅ    譬1҅IADA   ڿ*  AH1/IAA!DIEN  1ۃt   H߾H   E1ɉڿ*  1ADHL踀LAHAE*D    1AtAAt   1HUdH+%(     H8  [A\A]A^A_]f.     } RH@   LX   H 	 IH^{ H81)L}    fD  xgUD4    EDGU   .D  b} t@ H@   DWD   H	 IH{ H81	)}    H*     UHHdH%(   HE1=}  tHuQ| HUdH+%(   u/@ +tHKQ|     1} H9Q| )fUHHdH<%(   H}h   ^Ht+HP(@  fHP(HPHH@@    HPHHPP @HUdH+%(   ug)    UHAUATLgHSHHGHdL,%(   LmII9tBH H H HH  HPH=HH H  H H  H L9uHEdH+%(   uHL[A\A]](f.     UIIHHAVATSHXdH%(   HE1L9AHHDIM  IR@IZ@Hu   H9s+HBHJHt+HHBH9uHBL9M  I9rHBHJHuIAXI;A`   IyPH H  L`fMaXLIHN$J|(It$    LEM$HID$    MD$E\$ ID$@    IT$(AD$0H9[sHUdH+%(     HXL[A\A^]f.     H  HuLULMLEHUD]HMz\HMD]HHULEHLMLUHu3  L H  IAPMqHfInMaPfHnfl H  L IAXIA`   D  Lb<HGXH;G`spH_PH HHfHn1IIXHfHnHHflLEL$

HT
(ID$    MD$E\$ IT$(ID$@    HBH}H  HULED]s[HHtMLMH H  HuLED]IAPIYHIIPfHnfHnfl H  HIAXIA`   ,E1K%UHHdH%(   HE1HEdH+%(   u1N%f     UHHdH%(   HE1HEdH+%(   u%{%ff.     UHHdH%(   HEH{ 8 tHEdH+%(   u!1     HEdH+%(   u,%fD  UHHdH%(   HEH{ 8 tHEdH+%(   u!1     HEdH+%(   ud$fD  UHHdH%(   HEH({ 8 tHEdH+%(   u!1     HEdH+%(   uKV$fD  UHHdH%(   HEH{ 8 tHEdH+%(   u!1     HEdH+%(   u+d#f.     f.     f.     f.     f.     @ UIHATI̹   SHH}HpL^HdH%(   HE1H]HHFPHHEHH4HF8HEHFLeHEIB H+FHEIB(H+F HEIB0H+F(HEHF0HEHFLEHE~@ td         E   Et}Ȁ~B tEH1H}HHDISASHUdH+%(   u$Hp[A\]f.              "f.     UHAWIAVAULcATISH(MH   GdL4%(   LuEHt|SXt=U  H;    HEdH+%(   S  H(H[A\A]A^A_]fD  wu	EB    AT$uE~D;kXsMkxL u4Gu	E  x      bHHu$1kfD  x      aHHtA   DAXHHM賝HMI$   HAL$_H; fff.     }   E  I<$H  ˁH
  I<$蹁L1HI`AIp  H  HC8fA>tfA   C\      @ 1LIcH A  g  HH8  HH<  HA   H>u0   f     HA   A   IOIHMIHt	D9HDǾx   UDE`HHsHDEUuK    H       HC8L{Hx      U>`HH%UA   HkxHHDE֗DEH'f.     DH@H<   THC`HDshIfD  HCL   K| H'aHHLkfHȿ   H0u	   HHH<uHHH>   f     L踯Ip     UHAUATIS1H   dL,%(   LmIH~H uD?            EЀ~B tMHHHpIPHDAP   IUH  HH}   HHIEPHIUMM@MEHLpHxIE H4HF8HEHFLMHEIE H+FHEIE(H+F HEIE0H+F(HEHF0HEHFHE~@ ,      'D  lH{ H 101!cIE    lHEdH+%(   u8HĈ   [A\A]]@ IE`IE    AEl    HtH     1G    UHAWE1AVIAUIATISHxdH%(   H]HIFH  HpIHHHB8x     L   IvMFHHpL`HIFPHhHB8HpHBLeHxIF H+BHEIF(H+B HEIF0H+B(HEHB0HEHBH]HEz@ um      EzB tMHHrH`IPIDAPfff.     HUdH+%(   u%Hx[A\A]A^A_]f1@           UHAWAVAUATSH   dL<%(   L}L   ǅT    LXMZ  AGXN  IE11fD  IH uAd  @       E~B tMHHH`IQHDAQ   IWH   HHع   MW@HpIWMOHHL`HIGPHhIH4HF8HpHFLUHxIG H+FHEIG(H+F HEIG0H+F(HEHF0HEHFHE~@ $      D  TH{ HP 101_IG    HXAIxD;pXHEdH+%(   uCTHĈ   [A\A]A^A_]f     IG`IG    AGl    HtH     f     UHAVAUATSLH0LUDedH%(   HE1DE Dm(H  I΋OAӅ)  W  H   Ht*I;AXs HHkxHH9   fff.     A1DMD]LUDEDELUHD]DMH  LPDhpE        AlHQ`uAhD߉AlH@
H4D؃HF     Lv	H^F yp	F HqhH9sjHHHyH tcD  1HEdH+%(   Q  H0[A\A]A^]@ H   HHAL9tH   LQE9HyH uEtA   A     HAHTHH@ H9HH<HHH9H  HuHJHH4HT!ff.     HHHHAH: uHDMD]DELUHMDMD]DELUHM% HEO$L9A	HQH91AH;Q   HD\AHAHPHHQHHL } pfD  A^MUHAHTH*ff.     ff.     H1HH4HHH9tVHufHqHL   HMKt D]HgD]HMHHtAHHQLi#HAH{ Hǲ	 101[%H^{ H	 01[HM1D]1HqH9UHH dH%(   HE1Ht^DGHEu4Wu-H   Ht?H;rXs5HcHkxHH: u#D  H   HtHBH9t	HuHJHEdH+%(   uÐHHMHUpHMHUAUHAWAVAUATSH   dH%(   HEH   HXH  PXIp  IE11 ff.     IH uA  @       E~B tMHHH`IQHDAQ   IWH   HHع   MW@HpIWMOHHL`HIGPHhIH4HF8HpHFLUHxIG H+FHEIG(H+F HEIG0H+F(HEHF0HEHFHE~@ $      D  H{ H 101GYIG    LAII`IxIHXD;pXI$   HXHX誏IǄ$       HEdH+%(   u@HĈ   [A\A]A^A_]D  IG`IG    AGl    HlH     `f.     UH fInIfHnHfHnflHSflHdL%(   L]IH:  G   G   H   H  1H;wX  HcHkxHH?    1M9  I   AJH           MCIwU\f.     HH)HHHL9HH%HH9tL9s'IDHI\HHL9sHHGH9sIHEdH+%(      H]fM9H1HHƀIvH   IrMBH?D  1M9r1IvAB       IvABHƀIhAJ:f.     UIHAUATSHHdL$%(   LeMH  D_EuwDGEunH   H~  1H;wXn  HcHkxHLMX  1M9m  H  HOE1I HuN   ~f     M9   A   Iŀ1H   H   H   HOHtL   HH)HIL9rI9uEuHH9s    HtbM1LCMH)HHHHL9HH%HL9tL9s9IDHILHH9s"HOHIH9sHuMj   MbIHEdH+%(      H[A\A]] E1I f     1M9rAIŀHwf.     HvHOA   IŀH I H^ffff.     UHSH8dL%(   LMIH2  WusGulL   M  1HA;pX  HcHkxII8    I    MP`IHuC@ HEdH+%(      H]    L   I    MtMP`IHt9IyLEGLMLU؉IAPlA@h)9GH@H    H@HHItLELULMA@hI9]A@lI|IrH@HHEdH+%(   uH]鯅    I        UHHAWAVAUATSH(dL$%(   LeIH  ϋHMƅu{PutL   Ml  1HA;pX[  HcHkxII8 G  I$    IP`HHuK HEdH+%(   j  H([A\A]A^A_]fD  L   I$    MtIP`HHtA@lIL$AH@LlA@hLHEH@LTM9AE!M9   E  L9r7HFHL9u#HFL9  L;p`  L96W  H1oH˃H9L~L{HHvAL9sEuAphHuH92reHL9s\EtWE  HtL;rr	L93  L9
z  HrHt	L9h  HrL9sHH9rÐff.     I$    EW  HFHL9    HL9r1HuH92rHL9sEt5  @ ff.     ff.     ff.     oHHHLBLFL9Z9rQHh     1    ff.     ff.     ff.     ff.     ff.     oI˃HHALv9MsAL9sEuAphHuD  L9oH΃HHLBLF9r1H;]HL9}   EtxfHrHt	L9HL9Q9rH     I$     HEHuE11@ 1H;]HL9s	E1n	 ff.     UHAUI   ATSHdL$%(   LeIR>HtMHgHHt-LkLcHEdH+%(   u*HH[A\A]]     H     1    UHH dH%(   HU1Ht0HH?HE衤HUdH+%(   u#H}鸄     HEdH+%(   ujf.     UIHAWIAVAUMATISH   LurXHPLXdH%(   HE1HtC_`  D_ES  H   HtI;CXsHHkxHH; :  fE1   LLLHHH  LHDp\LPPA)  @\   H{ "  @ ff.     I$HK  IL$H   HXHPHCHLC8HHH8H`	HH  HCH;CA~L$H;HH%	  fHnHpHA   flHsLlHK HLHK(HL HK0HT8HL(fDL@DB HD0    N I   HH{H   Ds\HCPA;  I9tAGA9GX  H{ HC ID$HHC(ID$PHC0IT$HS@E$   A[  I$H  IL$H  E$   IL9   HXLDHHPHCHDILC8Hp8HCHH8HH  HCH;CA~L$H;DH	  fInHHHA	flHKALlHK HLHK(HL HK0HT8HL(D@ DTADB HD0    Au6HXH@Ht&HPH;GuHXH@H9G tC\   1HUdH+%(   f  H   [A\A]A^A_]f     A  IL$IH  I$HHHtLCA'  I  MPLKLIIH;  xB :  IHHIL;  xB   LHIIH>@       E~B tUHIPH`AP  MD$MPM9  1   MT$KHpMD$HL`HID$PHhI$H4HF8HpHFH]HxID$ H+FHEID$(H+F HEID$0H+F(HEHF0HEHFLmHE~@ $      D  C\   @ A   c  A     AHXHPHPH9WHHzH9x HCLIL$LC8HDIHp8HCHH8IH	  HCHSM|$H;H9$  HPHE1HSH    L|LlHS HTHS(HT HS0Lt8HT(fDD@DB HD0    HCH3HDH@BD  HPHP     APHEdH+%(   ^  H   LHL[A\A]A^A_]@ HCHLHHIˀyA HCHMdH+%(   
  HE1MH  fHPH@IM   LIl  MPKLM;A|B HsHE1HMHLP     I$M\$HHHPLHfff.     HXfInLs8LPHCHH H@ID$HXX)0L9H  M9  LHHLLL L(RHCL(L LH  HHPHTHLb8HWI9T$N  H@LMLLLPIH  HCH;CH;LP  fo0HPMLHHSDgV LlHHHS HTHS(HT HS0Ld8HT(LfDT@DB HD0    H@IH#  HCH;CH;DU \  ~HHPHXHSLlHS HTHS(HT HS0Lt8HT(fDT@DB HD0    HCHPHSHEdH+%(   /  HXE1MH   HL[A\A]A^A_] DCXHLL@DHH3H{`3H{H1HH    H)HCp    xHDHL@DCXAt$XFfD  HLLHLHLSP~fD  L   H(K4H@HLHf֍0HH  LHHH(HCLCH@~0qfD  HCHcHHu
L;jPHDLC81Ht8HCH1H8bIH  I$A~L$E$   HSH;H;S  HBA   HCHHI<fHnLhfl HS HPHS(HP HS0Lx8HP(fDP@@B H@0    D  HHHHH.    L   H0f֍@K4HMHH0  HH0HCLc~@DH HLE1MLSLHLLHCfD  LLHf     II8H;A7  M;q  IHCH  HHTHLb8A|$  tL9Hn  LsH@8HSHLXHXL:LhMk  I{-   H5U~ L0L@HHL(LPyHHL@L0L(_  L9P  LSL   HXf֍PK4HHH  HSHLcHX~PLH@IH9PH@MLLHIHG  HCH;C}  L;HPfo0HHSI LhHS HPHS(HP HS0Lp8A   HP(fDp@@B H@0     IL$MKDLC8LLIt8HH   HCH;HDHHP8H8  H@MLLLIHtoHCH;C  L#HPHXHHSILhA   H     HxHS HPHS(HP HS0Lp8HP(fDh@@B H@0    H   L(H4HPHHHtHPHL(HCHS
L   K4HHHtHDlO LcHCpHHC    E11MHLhHC    E11MHXHLLHLPBH{ LPLHwfHXLHLLL L(HCHPL(L HHWL!HHHkHHLa8D  LSKDH@HI9HXI}H9x tILCgL   K4HCHH&HHCLcH@MLLHOIHLcL9c   HCHX1HPHkHHHSH0HxL   H;IkHHHHCLcWL   H;IkHHtHHCLcI   H;IkH]HCHLcSAyB 1fD  UHHdH%(   HE1Ht`Wt)H   HtMH@HUdH+%(   u>     GuH   Ht1҅H;pXsHcHkxHH8 u1f.     f.      UHAWAVAUATSH(H}dH%(   HE1   HcAIIL$H ff.     ff.     HI9LGH9HBHI9uL)HE   HHHwv1ېff.     I1H={ D)IL)HcHHuH HHc1H}M9uHEdH+%(   uBH([A\A]A^A_]D  H$I$I$HH)HH
HH]f@ 1g    UHHdH%(   HE1HEdH+%(   u1-f.      UHHdH%(   HE1HEdH+%(   uɸf.     U1H	 HHdH%(   HEH{ 01.9HEdH+%(   uɸ UHHdH%(   HE1HEdH+%(   u_@ ff.     UHHdH%(   HE1HEdH+%(   u@ ff.     UHHdH%(   HE1HEdH+%(   u@ ff.     UHHdH%(   HE1HEdH+%(   u@ ff.     UHHdH%(   HE1HEdH+%(   u_@ ff.     UHHdH%(   HE1HEdH+%(   uf.     f.     f.     UHAVAUI   ATSHӉH5u H   dH%(   HE1FaIExH  fH*HCH)  fH*^LIY
 wHt    HH   }HH5t 1   `Ht H5t 1   `I] L9tLD  H1ɺ   HjKHet    HH1}H17HL9uHEdH+%(   u^H   [A\A]A^]f.     HfHH	HCH*XHHfHH	H*XW    UHAVAUI   ATSHӉH5is H   dH%(   HE1_IExH)  fH*HCH9  fH*^LIY/
 juHs    HH   {H   1H9 H5r _Hs    1H H5r ^I] L9tU    H1ɺ   HIH Hr    IH1F{Hj5HL9uHEdH+%(   uWH   [A\A]A^] HfHH	HCH*XHHfHH	H*X    UHAWAVI   AUIH5q ATISLH(  dH%(   HE1]IFxH  fH*ID$H  fH*^LLYe
 s   LHH.q    zIExH  fH*HCH  fH*^LIY
 0sHp    HH   yL   1HH5p \Hp    1Hp H5p \M>M9tyIEI]H_LH1ɺ   jGH1ɺ   HIQGL   LIH9p 1xL3M?HM9t	H;uHEdH+%(      H(  [A\A]A^A_]@ HfHH	ID$H*XH-HfHH	H*X HfHH	H*Xjf.     HfHH	H*X,fff.     UHAVAUATSHLcgL7dL,%(   LmIE~"ILM    HH  L9uLgHEdH+%(   uHL[A\A]A^]g_@ ff.     UHAWAVAUATSH8H}_   dL,%(   LmA]7 H  Lc    ILK+H  ~?HEIMcHHEIľ   L+HHF  DkH I9uHEMHuIHAOL6L9   M  1LEM  M   I  D?HHtvff.     HcCLLO;C   IHJx   MP1   MM[xI9IBBI9uH;O8sHcHM0>.HHuL..IHbLH 6eLsHCM6L9uHEdH+%(   uNH8L[A\A]A^A_]1@ HM CH]LmHH I9uLeE1OLweD  UHHdH%(   HMHcO~OHHH     ff.     H@ H9t'HH9puHEdH+%(   uHf.     1    UHAWAVAUATSH(H}WdH%(   HE1~}IE1AG~o HELE1HHIf.     IE9g~'LI>HIH31FtHIFIHCHEAU@9~AGIHEdH+%(   uH([A\A]A^A_]UHAVE1AUIH=k ATE1SHdH%(   H]H.AM*HfD  H8ALIDIAMD9~ IU LHHHpHuID9H=g	 E1E1-AM~IU LHHHx t_ID9H=W	 E1E1|-S~HLHHHx tQID9HEdH+%(   u]H[A\A]A^]@ H8ALIDAMD9i H8AHIDJSD9y    UHH HFdL%(   LMIHHHHu!R    ff.     HHHHt3H;uHEdH+%(   uSH. (   L18r     H9{ L  H1H>	 LM01Y+LMH     UHHdH%(   HE1vHEdH+%(   u 1    HEdH+%(   u{ffD  UHHdH%(   HE1f>   v9f tbf   f    HEdH+%(      g f   fv@HEdH+%(      t    HEdH+%(          fu"HEdH+%(   |   H*fD  H{ 1H5h 01)HEdH+%(   uBɸfD  fuHEdH+%(   u HR*fHEdH+%(   ufD  UHHdH%(   HE1f>   vYf    ftwH f tH{ 1Hvg 01-)1HUdH+%(   uUf.     fwHag fwftD  H< ft또H7g     H BfUHHdH%(   HE1f>   vAf ~   Hg ftH f u:fHUdH+%(   u}    fwRH/ fwHf ftH{ 1Hef 01(1     Hof     Hff ft빐H_f t_@ ff.     UHAUI1ATISHdH%(   H]HjC    LLHKHHEdH+%(   uH[A\A]] UHHdH%(   HE1ftvMHe ftUwHe f tEf t>f>t8H˄{ 1H?e 01&1fft:GfwHxe HUdH+%(   u$f     Hne     H+e "fU1HSHdH%(   H]Hh@HUdH+%(   uHH]HUXUHHdH%(   HE1HEdH+%(   uff.     UHHdH%(   HE1ftow-f   Gfw7Hd HUdH+%(   umff tYH~d w@f>tf tH\{ 1Hc 01%1 Hhd     fu    H%d fU1HSHdH%(   H]HgHUdH+%(   uHH]HWUHAWAVISHH(dL<%(   L}Iu HUdH+%(   u(H([A^A_]fD  LLH߈E?|E@ UHHdH%(   HE1f>   v9f tbf   f    HEdH+%(      3- f   fv@HEdH+%(          HEdH+%(      7'    fuHEdH+%(   up%D  Hy{ 1Ha 01#HEdH+%(   u:1ÐfuHEdH+%(   u AD  HEdH+%(   ukfD  UHHdH%(   HE1f>   v9f tbf   f    HEdH+%(      w f   fv@HEdH+%(      ^    HEdH+%(      'f    fuHEdH+%(   up5tD  H9{ 1H` 01d"HEdH+%(   u:1ÐfuHEdH+%(   u hD  HEdH+%(   u{)fD  UHHdH%(   HE1f>   v9f tbf   f    HEdH+%(      s f   fv@HEdH+%(      w    HEdH+%(          fuHEdH+%(   up%}D  H~{ 1Hm_ 01$!HEdH+%(   u:1ÐfuHEdH+%(   u D  HEdH+%(   u+zVfD  UHHdH%(   HEHfwFfw ft@HEdH+%(   uL1    HMdH+%(   u2HH=D  f>uHMdH+%(   uHH'#fUHAVIATSH   H(dL$%(   LeIHHRuHEdH+%(   uxH([A\A^]fAD$       ELHHCHU| MHI$IT$uH^ LHCMI$H| ID$yfUHSHdH%(   H]H   9HUdH+%(   uHH]H*QD  UHHdH%(   HEH H  HEdH+%(   u1aUHHdH%(   HE1HEdH+%(   u	Hn{ (     UHHdH%(   HE1HEdH+%(   u	H{      UHHdH%(   HE1HEdH+%(   u	Hv      UHSHdH%(   H]HHh   H%^  BtNt)uU
tmD  HEdH+%(   ubH] =  t6=  uHg   fD  He       Hh       Hf       Hd   f.     UHSHdH%(   H]H  7HHOtHUdH+%(   u.H]D  HEdH+%(   uHH]H5] NX     UHHdH%(   HE1HEdH+%(   u ff.     UHH~ { dH%(   HEH\ fHnfl  HEdH+%(   u1UHHdH%(   HE1HEdH+%(   u	H. {      UHHdH%(   HE1HEdH+%(   u	Hz H     UHHdH%(   HE1HEdH+%(   u	HFt      UHAWAVL5Z AUL-H { ATSH8H}HudL$%(   LeE1"    H}QIT$Mt MtxIH}H1E1j H}A   HMLrAXZEtH5 H}AKNH}BQHEdH+%(   uZHeD[A\A]A^A_]ÐH=	| HLA)MMc~z J    HJb fHnHEfl  @ UHH HU| dL%(   LEIHHtUH.| ff.     HHHHt3H;uHEdH+%(   uOH (   L1`     Hw{ Hѿ   LEHZ 01LEHX +ff.     UHHdH%(   HE1HEdH+%(   uH5| iK@ UHAWIAVSHH(H5| dL4%(   LuI-KuHEdH+%(   u6H([A^A_] H< LH߈EAF    =MI]fff.     UHH H}dH%(   HE1HtHUdH+%(   H}uHHEdH+%(   uɸUHSHdH%(   H]HHt;HHuHUdH+%(   u$H]D  f  ԸfU   HAWI   AVIAUATSH   H dH%(   HE1ƅ HH7 {H   e   H fHnHcHfHnflGH   Ią~LHHI1A   LH 5 t4LM1HUdH+%(   ukH   [A\A]A^A_]f     H5W H=W t*H=3 Hcz H=W Ij IDALgM+ff.     UHHdH%(   HE1HEdH+%(   u	Hδ|      UHHdH%(   HE1HEdH+%(   u	Hz      UHHdH%(   HE1HEdH+%(   u	Hn h     UHAVIATSH   H(dL$%(   LeIHHGuHEdH+%(   uNH([A\A^]fAD$       ELHH9MH?I$H| ID$ff.     UHSHdH%(   H]H   /HUdH+%(   uHH]HFeD  UHHdH%(   HEHa H  HEdH+%(   u1!UHHdH%(   HE1HEdH+%(   u	Hz      UHHdH%(   HE1HEdH+%(   u	HNz      UHHdH%(   HE1HEdH+%(   u	Hl h     UHSHdH%(   H]HH 7HHM| HCHEdH+%(   uH]@ ff.     UHSHdH%(   H]HH 7HHM"| HCHEdH+%(   uH]@ ff.     UHSHdH%(   H]HH] '7HH"| HCHEdH+%(   uH]O@ ff.     UHSHdH%(   H]HH+g 6HH8H      w1H         H0Htl̪H   HD1H      H   tJH0H   HDD  H"| HHCHEdH+%(   uuH]D  ЀHЀ@ H0̹H   HDf     H0Ѐβ@ H0Ѐ@ H0Hn	f     UHSHdH%(   H]HHH5t[ D(Ht6~wz Ha fHn1fl  HUdH+%(   uH]øfff.     UHHdH%(   HE1HEdH+%(   u	Hnz H     UHHdH%(   HE1HEdH+%(   u	Hz      UHHdH%(   HE1HEdH+%(   u	Hz      UHHFdL%(   LEL| H LEHEdH+%(   uHH׾(   1Hd VbfUHHFdL%(   LELtd Hfd LEHEdH+%(   uHH׾(   1H5d 7VfUH HH~dL%(   LEL{ LDHEdH+%(   uHH׾(   1Hc U UHHdH%(   HE1HEdH+%(   upkff.     UHAWIH5c AVSHH(dL4%(   LuI@uHEdH+%(   uDH([A^A_] H3 LH߈E2H6e LHI2MAF@ ff.     UHAWIH5b AVSHH(dL4%(   LuI@uHEdH+%(   uDH([A^A_] Hb LH߈E2Hb LHI1MAF/@ ff.     UHAWAVIATISHdL<%(   L}IRt&   HEdH+%(   ulH[A\A^A_] H5b L7?tH LLQ1HuHa LL91H_ LLI$1AGif     UHHdH%(   HE1HEdH+%(   u0+ff.     UHAWAVIATISHdL<%(   L}I t&   HEdH+%(   ulH[A\A^A_] H5a L7>tH LLQ0HuH` LL90H_ LLI$0AGif     UHATISHdH%(   H]HH5 H"HtB~Jz H` fHnflA$  1HUdH+%(   ucH[A\]    H5 HI"Ht$~z H>` fHnflA$  먐H5` H"HuȸU$   HAWAVIHAUIfHnATSHH  HdH%(   HE1ƅ HH   e   ǅ    HH* fHnH_ flfHnflu-1HUdH+%(      HH  [A\A]A^A_]fD  {   Hc IH   ~LHH<1A   LHV( u3H=7 Ht4HcH=( IiHtIDAE Lb@@(LP@+fD  UHHdH%(   HE1HEdH+%(   u	Hz      UHHdH%(   HE1HEdH+%(   u	H~z      UHHdH%(   HE1HEdH+%(   u	Hz X     UHAWAVAUATSH(dH<%(   H}HFHEH   HHUH5  vIHtfL-,|     LHxIHHteLHxIW:IEL+HUI]H5 1HCHIHuH}>1HUdH+%(   u8H([A\A]A^A_]He{ 1Hc 01H}}>AUHHdH%(   HEH@+| H9 HUdH+%(   u@ UHHHi{ dH%(   HEH냵FaHHH4HHu
H HtH9x(uHUdH+%(   uff.     H냵FaUHHHAVSH4H dL4%(   LuAHi{ HHHHu4@ HHt(H9J(uHEdH+%(      H H[A^]    HuHMHtNHMH}HEHH(HUHB0Ht$DrPHBhHHHtHPHHZH<Hc{ H9 1011YfD  UHAWAAVIAUIATSH)| H8UH  dH%(   HE1HEH9   Mt0E1E~(O| MuAH}H5 ITu
AD$v#1HUdH+%(   u}H8[A\A]A^A_] I`  HUL*Ht@L;I9t8H-HEfD  M?I9t H}IwHt       ID9eOrhf.     f.     f.     f.     UHHdL%(   LEIH+t%-tx tk1HUdH+%(      @ HPHHHQv    HHQwa   	HHHD  HfHPHHHQv f      u+HHQwa   A	 HH 5AUHAUATISHdL,%(   LmIHH5.0 HHI$8#u$HPI$P߀Gu0HI$AE     1HUdH+%(   ufH[A\A]]@ W1Hu     I<$HKHu"HEI9$t HwI$AU D  @ \ff.     UHAWAVAUIATIH5U/ SHHL7dL<%(   L}ILIL3A0	wbM   WHu1     H;I^I$AE }   HEH9tdH1HUdH+%(   udH[A\A]A^A_]ÐH5. LqLM$L#LMe MHtIH: t H렐f     G    UHH   H$ H0dH%(   HMHHHH   H   HTHLb~ HtwLA8HQHy u?HHѾ   PHE] 1PZYxAHHUdH+%(   uGfD  P   1AQLI@HH\ CP^_y1f     H ImLff.     UHAWAVI1AUIHATSHX  dL<%(   L}I8I(  HLÅuH} u5HHEdH+%(   u>HX  [A\A]A^A_]fD  HMI0  1LHL)LP臺    UHHdH%(   HE1y t>Gt:19 t>	tHUdH+%(   uUD  HEdH+%(   u? Nf/v%HEdH+%(   uH0  HH1H@D  UHATISHdH%(   H]HF3t4A|$  tJIT$Hh| H HH	HDH)I9D$sID$HEdH+%(   uH1[A\]@ AD$ HI\$Kff.     UHAVAUATSHdH%(   HE1H9      IHIIHH9uu    HI9tDHI9t<I9u	HI9t(H`I9tHSH9u4   +I9uIU HI9tI9tHI9tI9t*HI9uHEdH+%(   uhH[A\A]A^]fD  LHtI9tHI9tLHuLH"-A$      NA$    ff.     UHAWAVIAUIATISHH(DEdH%(   HE1H    H    ͼH   MIǅ  E1 I$H   H; t-1HUdH+%(   \  He[A\A]A^A_]f     IOH)HuL\MIHuI<$ uL%vZ{ A4$MMH=W	 11A4$HW	 11sfD  Iw-L(uAD9uuIOI$IG H)HsI<$ /L%Y{ A4$} uuqLHV	 11q  I$Hn  H; u
IGH)HIw-L(tJLbLIHuI<$ L%xY{ A4$LHW 11     L%IY{ L11HkU	 E1A4$oLE    HHuf    C*Ag   t<EAAwHELC1A4$MAVH(W 1A   XZHKHHt6Ls-LL#'tEuE1A4$LHV 11A4$1LHT	 1A4$11HT	 Iw-L&IOI$IG H)HI$Ht[H; u
IGH)HIw-L|&uAG*<LJIHuI<$  L%W{ A4$Iw-L1&uAG*<uIOI$IG H)Hfff.     UHAWAVDAUAATIDSHH(HMdH%(   HE1-tOM<$HL0HulA|$!    Ha[{ EB(
  A|$"     ff.     A|$$ uXHEdH+%(      He1[A\A]A^A_]@ LLHHHE2uHE<	ug HV{ AD$$ H1HT 01@ A|$" t`AD$AL$AD$9VfD  H9V{ H1AL$H{T E0S1LESAD$$XZfD  AL$贲@ UHAWAVAUIATSHH(dL$%(   LeAԀ     HGHuHH+GHG{" t1HHUdH+%(   d  H([A\A]A^A_]fD  A+tAL;LMLRF   L2LLHI0uC<.	   1fD  AHM[+tL3LMLEHMt.LLLHIE0uC</	HMufD  {! uZ{" tCC;CC 1HK {! uJ{" tCC;CPfC#   fHX{ EB u{" u1HX{ EB u{" u1ܰff.     UfHAWIAVIAUATISHHdH%(   H]ȉH    HuH    HH}H=q EEEEM襶xI} ud}    HE1IHEIHEdH+%(     HH[A\A]A^A_]D  EHNS{ HP	 101|MH0S{ L11HP	 3[HHuE    H= 3HLO	 1L1(3HO	 11KL-R{ HSQ 11Au Au +Lu=HO	 11Au HO	 11MHJO	 11HP 11U   HHdH%(   HEH   H H ʚ;HDHUdH+%(   uȮ     UIIIHH0dL%(   LEAH?    MZIIBIAIB     IBAAAB(AA AB,AA&AB0Iy tAy$ uI    1HUdH+%(      ÐIA   1LUI0  IqI8  AQMILUIHuH.Q{ HO    LU01ULU1I|fʑ| !HU{ Hu      H}H=~O HDEL]rDEL]|    LMLU^ ff.     UHH dH%(   HUHH?HtHrHU7HUH    HEdH+%(   u ff.     UHHdL%(   LEE1tpHΉHGH[| 1HHOHtHAHIE@HGHEdH+%(   u:HO{ HN    01@ HG    HEdH+%(   uBfUHAVIAUATISHHH~dL,%(   LmAKA  C$t(DkuBI|$ DU1fC&I|$(UC HEdH+%(   u.H[A\A]A^]fD  DfC&I|$(C 萫UHATSHdL$%(   LeIAt$fff   Hc(   HtltFHHHD  ff.     ff.     fHnHB     H(flBH9u1I$HEdH+%(   uH[A\]f1ҪfUHHdH%(   HE1HEdH+%(   uɾ     薪fD  UIAHH0dL%(   LMI;wsyH7AJAABu"]f.     ff.     o t=ȍHHHHHL;JrD LH1HUdH+%(   u}fD  H vR    fD  A9sHI:LMDEULU謢HHt'LUULMDEIAR3       뺸t~ ff.     UHSHdH%(   H]HHC    HEdH+%(   uH],ff.     UHHDOdH%(   HE1E   EQDWH?A      1 f.     oq D9sMЉDAHHHHE9   DHHL^L9YroC Dq D9rIJHpD +f.     ff.     ff.     o t ЍPHHHHH;qrHDHwHEdH+%(   uD  o HwDUHHdH%(   HE1Ht HEdH+%(   u$HGf.     HEdH+%(   u1舧     UHHdH%(   HE1HtHEdH+%(   u6HGHJ{ 1HH	 01HEdH+%(   uɸfD  UHHdH%(   HE1Ht HEdH+%(   u"HGf.     HEdH+%(   u躦f.     UHHdH%(   HE1Ht HG HtHUdH+%(   uD  HEdH+%(   u1X     UHHdH%(   HE1@t'Ht"HG(HtHUdH+%(   u    HEdH+%(   u1UHHdH%(   HE1Ht HG0HtLUdL+%(   uD  HEdH+%(   u1蘥     UHHdH%(   HE1Ht HwXHEdH+%(   u H    HEdH+%(   u18     UHHdH%(   HE1Ht HEdH+%(   u$HG@f.     HEdH+%(   u1ؤ     UHAWAVAUATSH   H$ H   H   Lw`HhHHEL`IdL<%(   L}L}Hx?HChL   LpE  Lx1M9  HzG{ H   HAE	    0LL)P1HSp^HpHx_H  H{x1HHH1HHH9rHCxH)I9  E  LHXHpH9xHXIr	L9  L)IL9y  L[xMI)IM)MAD$Pt1LHI)I)LIG	  H)HHLEH1HH0   LLfMH   LǅG   H   LVHHh`ZY  HpH   Eu-HSh$| H(  ID$HHt   LЅx   HUdH+%(      He[A\A]A^A_]@ H!H!Hgf.        HS`LLLxLpuaLpD  L)MM6E11@ I&     H{p EH{x1HHHH).fD  0詡f     UHHdH%(   HE1Ht0:euFMHHt6HG8Ht-HMdH+%(   u> 1HUdH+%(   u'D  HqD{ HrB	 101 UHAVATSHdH%(   HEHGXH   HIAH9u   fHI9\$XtvHnt1   udMd$XI|$ukI|$ DH   qƸt*HEdH+%(   uYHH[A\A^]@ HUdH+%(   u/H[A\A^]HEdH+%(   uHDH[A\A^]&     UHAWAVAUIATSHH(H}dL<%(   L}IHx  H  1HuLaIHEL8 H   M  L#L9_  M9$   t.  ff.     E$   M$$I9tM9$   uLM$$L9u@ L3L9  E E1fff.     L   LMEeHt%@A   MttLLHEM6L9uEM A   H}   L#I9u>xfD  A     EtJE=  L   *AENM$$L9t<E$   M9$   uLAE4  L   WM$$L9uA}N      1HUdH+%(     H([A\A]A^A_]fM$$L9M9$   M$$I9M9$   udf     HM   DqTMLD    H@{ A   D1Hg?	 01P@ L6L9 9    Hq@{ HZ?	 101HV@{ H?	 101fH9@{ 0EtH>	 11bH>	 11PmH@{ LH*>	 101/LH?{ H> 101.H?{ H>	 101if     UHAWAVAUE1ATSH(H}dH%(   H]HH9   ff.     H   H߄ALErH   L`M  H5%| H  L=|  IwIH   L/uA ulE   AG   MtH}HLEHH%tqHH9]D1HUdH+%(      H([A\A]A^A_]EuHt>{ LHB>	 1016D     H{HiH9>{ H>	 101g{D  H>{ LH = 101<H={ LH=	 101藚    UHHdH%(   HE1    HEdH+%(   u1W    UHAUATSHdL,%(   LmIH?I9t"H@ HGHCH@L9HHuHEdH+%(   uH[A\A]]fD  UHHH0dL%(   LEIH;?   HQHBH=   w8HHHLD
vHt
 HB1HUdH+%(      @   LEHuHMHUH   HMHUH@    HAHPHHHQHt\HBLEHumD  H}  LEHuHMHuHLEtHQH@    HAHHPH7軘ff.     U1HAWAVAUAATSHHHudH%(   HE1HHE    H9t$     ff.     HPHUH H;EuHu   D^Ht0S2 HUdH+%(      HH[A\A]A^A_]D  HEL L9tgff.     I\$E1I|$ u?fD  IHM;|$s*o   HuD)EHt1 uM$$L;eu1_X肗fUHAWAVAUIHuATASHӺ   H8dL4%(   LuAH  HEE   HHHHI9f  L@  0D  HHuHMHHHHItIL IGHEHPHUH     HuDH  L9@  D  LH  IGH=   v  GH  fInfInHH  flH@     ILH  M  IG:fHHHI9|  L@  ! HfoEHHADIGHEHPHUH!     HuDH&  L;@     LH  IGH=   v  lH   fInfInHH  flH@     ILH  M   IGG      H   HH  fInH@    HH  fHnfl HzfD    HtYHH  fInH@    HH  fHnfl Hf.     1HUdH+%(   uH8[A\A]A^A_]ø褔@ UHHdH%(   HU1Ht HH9HDHUdH+%(   uD  HH9HDO@ ff.     UHSHHv dH%(   HE1HtCHH(  ,Ht/@ ;Cs'HHHHUdH+%(   uH]    1ϓ@ ff.     UHHdH%(   HE1UH8  @uHt>z u8H@  z  u+H0  Ht0Hx t)HWHwLEHHUdH+%(   u	ø7    UHAVSH LW(dH%(   HE1҃MtHEdH+%(   uiH L[A^] LO0LwH}AHA| 1   LU؋ L!II)HLLUHtL]LIC8Ms@MS(聒UHH dH%(   HE1H( t=HH8Ht1Hr@HUHUHB8    HB@    HB(    HBp    HEdH+%(   uff.     UHSHdH%(   H]H莘{H uHEdH+%(   u(H] CH H{(HCp    HC    蜑ff.     UHH dH%(   HE1H}H}HEdH+%(   uN ff.     UHAWAVIAUIATSH8H8  A dL$%(   LeMHRHHtCft=HHHHHr(1HEdH+%(     H8[A\A]A^A_]fx   HcIH  A      I@  x    EMD9   Mu HIƀx u@APPAP PIUfHnHJIMIP`HPL@  fHnflA LfAEM.M$%D  H@0I+  I  I@(EMD9jCE  DA9st9rA9AC9  fff  ʾ(   LEH׉MHUDMHUMHLEDMId  HLIf     fHnH@     H(fl@H9uEthM] L1E1ҐI3H8H9t"LJH@LOI9HM] EMHBI3xAH(H(zxzx@zH@ HBE9rAMMu Q          (       LEDMMLEHIt|MDM     Mpx# uvDxMxMLLELEHt8LHDLEHE
HMLEI9uNIH(A@H    I@(    LsfD  HxLELEAuHLE
LEI@(    뵻볻词@ ff.     UIIʹ   HHĀoBdH%(   HE1H}HHBHMLEHEB$LUEB(R )EfEHUdH+%(   u%D  UHAWAVATSL$  H   H$ L9uH E1HILIdL4%(   LuIHLH߹   uH:Gt&HUdH+%(   uFH   [A\A^A_]    JL9uf/vLE1HLfD  T@ UHAWAVAUATSH(dH%(   HEH8  Htrx ulL@  H@  IHHEI9tOMt$E1I|$ t4@ ff.     INIHLuIIM;|$rM$$L;eu1HUdH+%(   uH([A\A]A^A_]苋ff.     UHAUIHAT   IH`SH   dH%(   HE1HHuH(  Hr LEHpǅxHt\I(  0HtRH(P E1L@$L牍|H`fEHUdH+%(   u!HĈ   [A\A]]D  ׸譊fff.     UHAUATSHOdL$%(   LeIteI$E1K\ HHH8H9t?ff.     HHGfHnflHBHI$HH8H9uAL$IA9rLkAD$    HEdH+%(   uH[A\A]] UfnfnfnfAnfbú@   fbHAVflAUATSHHHDm(De0dH%(   HE1HG    HGd    H)xHH   H{0DKHEHuC   CHC HE HC(Et5C   x   DkpDctfCHEdH+%(   uH[A\A]A^]ÐH{0'8f.     UHHdH%(   HE1jj u uuH0HEdH+%(   u虈f     UHAWAVIHJ,	 AUATSH   H(H+{ Hu01dL,%(   LmII(  HHxIJHtb F   IAGHfAD$LLLqÅuH}11LAՉLHEdH+%(   uH([A\A]A^A_]û跇    UIHSH(Hi,{ dH%(   H]HӀ8 udI8  Htx t"HCHUdH+%(      H]D  I0  Htn;GuiIH  HLPHHyfD  H*{ HHKHuH*	    H8C(PC$PC PLK1LC蓅LUH RH\ņD  UHHa dH%(   HE1L GfW	GGG@t9G1Ҹ   HG0H۞	 W8HG(HG@    HEdH+%(   u fW    3 UHAWAVAUATSH8dL,%(   LmI  HH  HE1E1L51$ t,PHOYw@IcL> AEGHτuEtEuAE8   IE0 1#fH({ HH)	 101HUdH+%(     H8[A\A]A^A_]D  <y(  AEG<,t< A  H    HH< t<,tA   0	Hu
   &HuIE0 t,uHVf
HH t,tH~  iLU$ IcL><L`  AEAE,@   G<,t<   H    HH< t<,tЃ0	_
   Hu|P  H}AE,2f<G   AEAE(   G<,t<   H    HH< t<,tЃ0	
   Hua|P  H}AE(fAEGH    AEGH    AE
GHo    AEGHW    AEGH?    AEGH'    AEGH    AEGH    AEGH    HHu
   HMS{H}IE@H9}f     AEAEGHf.     AElGHo    AEGHW    AE	GH?    AEGH'    AEIU`Iu\H}HMNH}DD  AEIUhIudH}HMvAEdtHU1H5 E    H=# E @  DAEp@ AEAEGHzf.     AEGH_    AE1@ AEfD  AEfD  AEAuLQ1{HHHE3AE8   1KHi  Hi  IE0~sH~AE8   FA   A   AE8   A   FA   AE8    A   FA   c> ff.     UHHdH%(   HE1HEdH+%(   u
H    UHo" HAWAVLw0AUATSHHDGLg(dL,%(   LmIAIcHz HH%" HHDH#"    L1-~AǋCt	M   H"    L1~E$CuaLs(HK   LAVCH#	 P1s DKDC}AIcHUdH+%(      He[A\A]A^A_]    tKptDCtH! L1   r}Auf.     LM   LHSZ/D H	HHHi ʚ;HH%! I)1"}E$d~@ UHHdH%(   HEFwH(  h
  HEdH+%(   u~f.     UHSHH  dH%(   HE1tHk  H=  4  t*HEdH+%(   u0H]H  H=  1HEdH+%(   uH]}fD  UHHdH%(   HEH8  Htx tHEdH+%(   u1fH { HH0>
'}    UHHdH%(   HUHW ff.     H   H   H   H1H9rHEdH+%(   uH|f.     UHHdH%(   HEHH u.HG$| H(  1HUdH+%(   u    T|@ UE1HHdH%(   HE1j [HUdH+%(   u|D  UHHdH%(   HE1AQA   HUdH+%(   u{fUHAWIAVAUATASHdH<%(   H}ȿ0   輰H   A   D   IILǻHtPDIE H(\(HMuHM}HEe(HIUHEdH+%(   u)HL[A\A]A^A_]LJf.     E1{fD  UHHdH%(   HE1HEdH+%(   u
H錼z    UHHdH%(   HE1HEdH+%(   u	Hz     UHAUATSH(dH%(   HE1H   HGIE1H   @ I$J4Ht{HHVHHtDfo	 )U     HSfo	 LiHHSHHHtHffoؓ	 H)]foMHL-ID$II9kID$     LHEdH+%(   u,H(L[A\A]]HEdH+%(   uH([A\A]]Zyf.     UHAWAVAUAATISH(dL4%(   LuIHWHtHG HHG H9r[EnEiGaI$    A+L$(AJHIHtLrL0IFHEdH+%(      H(1[A\A]A^A_]ÐHGE1H   I$J4Ht{HHVHHtDfo|	 )U     HSfod	 LHHSHHHtHffo8	 H)]foMHLID$II9kID$     w     UHHdH%(   HE1HteiGa    +O(HH4D  H;Vt HHuHEdH+%(   u* HVHHtHPfop	 1bwfUHHdH%(   HE1Ht>iGaH    +O(HHufH Ht9puHUdH+%(   u1vf     UfHnflHHdH%(   HE1G    HEdH+%(   uvff.     UHAVAUATSHdH%(   H]HH9tBL#IfHCfHnH{PflID$L Am誫HLoM9M$$uHEdH+%(   uH[A\A]A^]vD  UHAWAVAUIATISHdH%(   HE1>   fff.     X   HHtfHnfl LHCPIH  H5 HkIA0	  LH5 IH5 ILsLHZ  LHE8 t  HLsHEH5 L`	x   fCHS Hs8H H}襷Aƅ   H{  tHs0H}薶Aƅ   LuH5 L蘩IA>/{  LH5 |IA>@tsLH5 dfInIID$L+sPI\$MfHnflHAD$A}  {E1HEdH+%(     HD[A\A]A^A_] I~H53 MtA0	+  ff.     ALkPL>HC(    fHCH    CLHLaf     H5% LuCw@ H5 LuC W@ H5S LY   IfCLs& IHS(Hs@H; H}LuAƅH{( tHs4H}豴AƅCLu.f     LH5 衧H5 ILsHLHIA> A IALkPtr@ UHAWAVAUATSH   HHdL$%(   LeL'L9       M$X  LLP	E    H  HUHH5X 1HhHHd n]M    IǄ$X      LuLLLLAŅ  M9  H]L9	  H{ HXff.     H{ HC  LkHM&  L^zIH  H~  I )LIM  Hs H(  >*u
~   LxDC0HhLLL`ոL`F  HxHC8{    H{@    Hs(H!  f     DC4HhLLz  LJLAHXLP11H	 3L蹵3H	 11觵31H	 1蕵L=HEdH+%(     HeD[A\A]A^A_]     Hs(LxH<L褸H|H  HL  HL9$H f.     HH{ HXHPHX   I$X  HJ 01躴M$$L9HE1H{(HOLkHMH{ x %  LxK4HhLAŅ  HMLxHS8JH9u  H)HC@HHK(H   HXH	 0/   HXLHG	 101-    LxHEHS8LH9  H)HC@eH	{ x O  ?*u
 H  LxK0HhLL` AŅ   Hx{ H{(L`HC8t1H{@ u*HHEHC@HHK     Hf.     LXL	 HXHKHH	 011˲fD  1Lv  HC8    I  LHC@H˰HOfALD  L H{ HXqD  HhfHֲH= HE    )E)ErAŅ   } toEC8 HEHC@HX1H	 01ұEJ@ HXLK HK(0MtH11RH:	 蕱XZI1HR	 1{HX1H~	 01]LtHX1H	 017LHHXHKHH	 101LeLH{ 1AH	 0HX1հLmCk UHHdH%(   HEH0  HtLEdL+%(   uH fD  HEdH+%(   u1j     UHHdH%(   HEH0  Ht3H@Ht*H8  Htz uHUdH+%(   ufD  HEdH+%(   urjfUHHdH%(   HEH0  HtHUdH+%(   uH@ D  HEdH+%(   u1j     UHHdH%(   HEH0  HtHUdH+%(   uH@(D  HEdH+%(   uif.     UHHdH%(   HEH0  HtHUdH+%(   uH@0D  HEdH+%(   uZif.     UHHdH%(   HEH0  HtH@8HtHUdH+%(   uHEdH+%(   u1h     UHAWAVAUIATSH(H{ ZdL$%(   LeIԀ8 u!  H HcH>    HI{ پ   H H81)g    LLEfEuDI(  HH9t5f.     HLřM(  tH9      HL9uHEdH+%(   1  EH([A\A]A^A_]LLELLeEmD  LL荗EUD  LLUE=D  LLE%D  LLED  M'M9?E1f     HL<uL9tMLMDLM$$M9uMt?I0  pH0  I0     Hǃ0      A   ǃ      M(  fEUHHdH%(   HE1Hz HHUdH+%(   uffUHHdH%(   HE"w#Hn   Hr(u    HEdH+%(   u@     fff.     UfHH dH%(   HEH=  II  z  >  v    	  @	   9  	  t  y  1A    H9H   AP   I@  <   BHcH9   t< uyBHcH9snti< ucBHcH9sXtS< uMBHcȃtBH9s=< u7BHcȃt,H9s'< u!BHcH9su<       ELLǉEEHUdH+%(      f        ʃ  L IcL>D  ȃ<yH     BHGHB	   fD  ȃ<9HQ        HBGB   w 	  HH  DWLH  H	A
  H  DWLH  H	A	  H  DWLH  H	A	  H  DWLHHH	A	  Ha  DWLHH!H	A	  H8  DWLHH(H	A	  H  DWLHH/H	A	  H   DWLHH6H	A	  H   G	  f     fD  H      A     HtrGtn<  <af  <#T	    <	  <"[	  <uHv,A    GHI@      [     APWA.  <$H	vHGI@
          A@H HcH>HxGH   A@GfA@   A    Af     A@H} HcH>HGH   A@GfA@   A    A@+HD HcH>HGH   A@GfA@   A    ;A@H HcH>H`GH   A@GfA@   A 
   Y    pHA    GA@GA@   HGH   I@   H      uH      HHGA    I@	HvGH   I@   lH      VH8GH   I@   /HHGA 
   I@HGH   I@   HHGA    I@AHGH   I@   HGH   I@   H_GH   I@   H8GH   I@   H      HHGA    I@oHH=H	¸
   AH9IPA    D!e<  <^<&H<
 HcH>HuH      I GH      A@GA@H9H
%A    HGI@   H	A    HG0H      A    )HH/   f     HtHyHA    API@HA          H^G  <A    G<HI@      jHA 	   Gύ       b<!;H(
 HcH>H      A    H	
~tA       HA    G   I@GW%   	H   A@HA    G      A@GHI@H      A          <C  <S  <3H      A    nA         7<   <MH      A    ,               HGH      I@A    GA@G<`  <:  H      I@      R   H	   >H      A    LH      A    /HA    GH      fA@HG A GA@G_H
vA "   G?A@GI@HG9HE    HAA    GEGfEHEI@&H      I@    UH      I@@   7WfD  UHAVIAUATSHH Lo?dL$%(   LeI[I"  H5c
 HcH> HLY AUff.     HLL1   7ZYHUdH+%(     He[A\A]A^]D  HEdH+%(     HeLLL[H% A\1A]A^]Jf.     {]HEdH+%(   K  L HeLL   [HA\1A]A^]醣fD  HEdH+%(     L @ HEdH+%(     L @ HL AUCP1!PHLL1   H @ DIL APAU@ HCIL PAUw    HL AU^fD  LL HPLHPLHPAUSf     LHLB H PAPAU(fD  AUCLU P    CL$ PAUfD  1LL LLH   DKHLI<H)E7  E1Lf.     Hg 1HuH}HuH}ȅeDKHAMHH)E9   MyH 1HuH}ӆH}Huf     AUCL PfD  AUCL PfD  sH HӀ AUL HEPf.     LL HPDPLHPAUD  HL AU^CLt PAUL@    1HuLsH HzB +EȅH2"SfUHAVAUIATISHĀdH%(   H]H1Ʌ҉HH`k7  EI9*  C    C d    pu0x<  <ovPvHI
 HcH>@ UH    SH<wKHSsj     f.     1HUdH+%(   c  H[A\A]A^]fD  Ao$C@ H`<E    I$HHKILHHLH)I)ԃr1҉уI4H49rk A$KXALfLH     MHj	 fnHHfnMfbfCD  <3  Hi	 UHHЉSf     Hag	 UHHЉS    Hyg	 UHHЉS    Hqi	 UHHЉS`    HAi	 uHfnH>Hi	 }HfnH$H%i	 UHHЉSHh	 }HfnHd    UHЀm   H    SU UHfD  uyH4   wm      ugU   vUH}h	 sHCf.     XfD  A$KALL; 5t_H    s     H`脣    Hg	 SHHg	 sHHg	 sHuctuHg	 sHsHg	 sHaN UHH0dH%(   HMHM~x*EԃHUdH+%(   uf.     dN@ UHAWAVIAULATASDHH   OHPdL<%(   L}M)g   EL- D9kMtALkCinsnAEn:  } tJE1A      fG&HcIc   LLQ 1IHEA)D9HEdH+%(   u HĈ   L[A\A]A^A_]fL- bMfUHHdH%(   HE1H|z HHUdH+%(   u"MfUHSHH8GdH4%(   HuHփvxP1wXOH5 ?HuH! ɉMHOHUMHUHHuILN 1QHR   ؙZYHUdH+%(   u>H]Ð?HuEHuHUdH+%(   uHH]H1He ~DL@ UHHdH%(   HE1w
H
 HUdH+%(   uKf.      UHHdH%(   HE10HEdH+%(   u1K     UHAWAVAUIATSHdL4%(   LuIH?Ht^IHtVI^IFI! II^H9rIF    1AFI>H)LL9IGHHBIFHIFI)uHEdH+%(   uHL[A\A]A^A_]Jff.     UHSHHdH%(   HEHsz 8 "  H=B0|  t 1HUdH+%(     H]D  =/|     HDz HH0| H   =.|  tf=.| HUH)EHEH\H=.| ).| HE    HEfoEH HUH5P H=R.| HK.| $foEH[.| D$_H HtOHa/| @ H5c H=J.| HH;/| H9HKz   IH=-| ~1H/| fUHHdH%(   HEH.| HUdH+%(   uJIf.     UHHdH%(   HEHz @=-| 5{-|  HEdH+%(   uHf.     UHHdH<%(   H}H=P.| Ht趥H_z   HEdH+%(   uHfD  UHH=-| HHdH%(   HU   HEdH+%(   uɺ   H5> H=,| kYFHfD  UHHdH%(   HE1H=],|     H=-|       HZ,| H= f=?,|  H@,| H5),| H=,| uP   f   H,|    H= f+|  H+|     HEdH+%(      fH+| HH)uO@ ff.     HHt6?
uHpH   /fH+| H5+| H=j+| UD  1   fH5]+| Hf+| H=?+| Hu%D  HH?
uHH Fff.     UHAVIAUIATASH  dH%(   H]Ht(HEdH+%(      H  [A\A]A^]D  H=+| L   Hn DE   McIfD  H=+| 1HHZ    DI9uA+@ Hy+|       H=Ϲ AdAuH5R+|     訅HL   ԊH=-+|    1HHQ CDfD  E1~E ff.     UHAWAVAUIATSH8LcdL4%(   LuIOt+HEdH+%(   F  H8[A\A]A^A_]f     A   f.     H5y*|     τAuH=b*| 1LH    |CEtW   I9IFII]AD$Mtf.     H=*| 1HHY    /CL9uIw+EH)|       H=? A?cAuH5)|     L    Hu'?H=)| ~HMH    1BH      H= bCfff.     UHAWAVISH8dL<%(   L}It#HEdH+%(      H8[A^A_]D     ff.     H5(|     ?uL   1   H=(| Ha A     H(|       H= buH5(|     ݂L    Hu=H=e(| ~!HMH    1zA"D  H      H= aBfff.     UIHSH  HHHPHXL`Lht#)p)M)U)])e)m)u)}dH%(   H8Hz 8 tPL'| MtcHELҾ   LH(H H@ǅ    ǅ$0   H0YH8dH+%(   D  H] =!&|     HLz L L
'| M  =%|  if=%| HL) HHWLH=%| )%| Hǅ    HۂH fo LH5F H=:%| H3%| $foL@%| D$VH IHtbHC&| L    H5iZ H="%| LLIL&| MHz   h@H=$| u1H%| ՐUfHATSHH0Hz dL$%(   LeAHE    ǇH	      )E)EЀ8 uhHs(H}u5HUH  HUH  H   HuHx  }u:Eu5HUdH+%(      H0[A\]f     H= 1HEHǃP      ǃ	      HCxHz Hǃ`      ƃ$   Hp  ƃ/   8 u xHz 8 ubH= 1虵H=c 1艵?fUHSH  HHHPHXL`Lht#)p)M)U)])e)m)u)}dH%(   H81HEIL      H    H@H0ǅ   ǅ0   H(VhHz    H0H H81<Hz 8 uH8dH+%(   u#H]fD  H0H= 1c=ff.     UHATSHdH%(   H]H(	  P	  f     HcH	  H  H  H@  HH)H  H  u;Hp
  H   Hx
  H  Hǃp
      H  Hǃx
      	  H	  H(	  	  Hz    fnȀ9 fpfփH	  u/(	  B1HUdH+%(      H[A\]@ H  H@  H(	  t(	  1 H8uH  H  >HR	 9 ǃ
      ƃ$   HH	  ubfH  H@     H(	  	  tHz 8 tH= 1};fD  UHAWAVAUATSH(Hxz dL,%(   LmI8   M  MteL=M M     LLL貮H     MI9rLHLH)*[tfHuM@  Iǅ      Mp
  M!  Mx
  M  L= Iǅp
      M  Iǅx
      b    Ip
  M@  Iǅ      H  Mx
  I  Iǅp
      M  Iǅx
      A   A)McM9I4LHHMKZHMfoU	 M)I
  Mx
  A   LI)@  Ip
  I  Iǅ     A
  H= 1袰^1LuM  M  L= PHUdH+%(   u_H([A\A]A^A_]1L}uI  M  L)AH	  HEdH+%(   uH(L[A\A]A^A_]9fUHH H  H0	  dH%(   HMHH  Ƈ%  HH  #   tH	  Ɓ
  H   x	   uIT	     H   fH*Yh	  Hy7HfHH	H*X%Hx{fH*Yp	  HxfH*XN	 f/   H,H*z H`   H9sk   Hǁ0
      HEdH+%(       HփfHH	H*XpfHփfHH	H*XfH`  Hǁ0
      tHEdH+%(   u\HH= 1H5 Rf\H,H?,D  1H= HM&HMH;z H`   7f.     UHHdH%(   HE     H0	  D  ,	  %  A!р#      uƇ
    AD)AщHh  EH  H)֋  D    AH)H|z H  HǇ      Ƈ$  Ƈ&  8 t/HEdH+%(     DD1H=     HEdH+%(   S   (      4H`  L	  Ƈ
  I9L)   fH*H	  Y	  H   fH*XNL	 f/|   H,H9	  H	  fD  1DD  HIH)H1IHH)@ q~	  `  	  VD  \H,H?vD  IȃfII	I*X8fIȃfII	I*X5fff.     UHHOLG(dH4%(   HuH7	w,  	  H
 HcH>f.     
      H;ut0   HGI 1HUdH+%(   l  f     HGAP9t   A@`	  fH*^A@8f     Ax2 uYH       IP(H       H!HOHH9HBȃ$  EHI E  H-  fff.        8fD  Ax0 %  LOAPn  Ax1 c  A@1       +  D!	APD9    D)I@IHEHI@  +  D  Et&1D  IIH1IMIIJI;H(/$IH(\@ Ax2 D  E=HW  IH #     H)APIH       t!1ҋ  HHH)H1HHH)A  IHI@    fEP0@ )AP  f     A   )D9f     HH@ fHnflA@ ]D  T	     APh	  A@8 H)MD  H+`    fH*H   fH*^AH8f/vf(^f/H	 )  Ɔx	  Hz p	  AP t1iHwAH8   H= 螧If     8Hw   H=  sfD  HH+`  xfH*HxVfH*^TfD  HfHH	H*X
fHʃfHH	H*XHfHH	H*XHʃfHH	H*XlHz 8 YHw   H=i 蔦?
0f.     UHAVAUATISHH dL,%(   LmIHE    "   uƇ"  	    E1@  LLK(HuMHP  LS~Uo	  o0
  foflff0
  	  t\Hz ǃ\
      ǃ	     8   EHEdH+%(     H [A\A]A^]fD  M   MFfH~I9  AD$P  A$C  2    ǃ\
      A$   AD$   AoD$   
  W   K H0
  H	  H	  H`  	   tcH!A   H9H9sfL	  xL9P  $Xf     L	  L+	  MBf.     HH!H9sH	  ƃ	  H	  H)I@ HP  H5 1MH=g MYf     u	AD$tRL  HP  Mcl$Mv  Hc	  B   `  I	  MlAD$n     \
  HP  PHK@\
  AT$AT$HcHHP  HSHtW6  ;X
    H;@
  u  d
  u,`
  H@
  fnfpfփ`
  ff.        fD  HP  C0      HCH    HS@IcD$HHP  D  	  tMu8H	  fH~H`  H#	  H9%  H	   ff.     K0    Hǃ	       H 	  H   Hǃ 	      L01IH     l@ HA	 H@
  H`
  fD  	  H  tG	  HHDH  AD$fD  Hz 8 ugǃ	     HttHH  H 	   tTM?H  MHtI  fD  H	  H	  H5 H= 1HH 	  H1I   MHu_lHuȋMH*U1HSHuHHdH%(   H]H\      HX  3  2  Չȃ2  8tK0 @  fK63  Eă    HCHP  H  	    HcuHcUHHs(HHUHHUe  K0   fHnƃ#   flƃ	   ǃ	     HP  C@1HUdH+%(     H]D  HCHt׃	  uC0tHs(H{HЄtHX  K0   ǃ\
      2  12  ƃ#   ƃ	   ǃ	     xfD  ,	  HP  	  tJǃ	     HS@uHCH    1;f     HH  HCHHP  1    HS@1ƃ#   ƃ	   ǃ	     tHH  HP  K0   1HSHHP  Hz 8 u;ǃ	         Hz 8 u.ǃ	      HH5~ H= 1hH= 1X'UHHPdL%(   LUI0AB0Iǂ       A 
     fAnL
  1Ҁ fAnP
  fA 
  A
  fbAB0I
  fAւ  A   A   I  Aǂ
         A
  t.A3  AJ0 @  ʉAƂ
   fAB6ăA3  A	  @t8AB0A
  AƂ	   AA
  AA   ADAB0A	  t%AJ0I
  A   AƂ	   I   A	  tAJ0I
  AƂ	   I   A	  tAJ0 I 
  AƂ	   I   A	  E	  A	   t{AB0A   AƂ	   @AB0@   AƂ	   AB0EtAƂ	   IP  IBH    IB@0     HEdH+%(     ɉ@ @   AB0f     A
  AAƂ
    AR0A#     fAnL
     fAnP
  AB0A
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  fbfAւ  fD  E4AƂ	   'f.     E  AƂ	   A#     A)     AB0  AB0IP  AƂ#  IB@    IBHfD  HE    A!   A#   A)   I;H  A"   uAƂ"  A	  L  fI0
  I	  I	  I`  A	   ,  H!H9r&H9:  I	  ff.     HLUMJ(1HuIP  H}A   ARLUEIP     Hz 8 H56 H=8 1 fAnL
  A
  Aǂ
      fAnP
  A   I
  fbI  fAւ  D  -Az0D    Aǂ	       )I	  I+	  HH!H9I	  AƂ	  I	  H)~EA	  Ao	  Ao0
  flffA0
  A	  tCu&I	  fH~I`  I#	  H9s,I	  HcEAJ0HIP  `Iǂ	      I	  I	  !fD  UHAUATSH8dH%(   H]HLH  ff.     LHuHF    8  t6~   ƃ	   HUdH+%(   D  H8[A\A]]f     ƃ	   u΋E  Hz tJuǃ	      g    H= 1蒗ڋEt8Hz ƃ	   uf   ǃ	     M@ HP  HcEHI9t-ƃ	   HOz 8 tH5 H=m 1 	  Hǃ	     @A@t-Et(1HP  H5m H= 1迖R+ HP  i@ ff.     U   H HAWAVAUIATSHHHuLLdH%(   H]HHHtDIH)E    I)u0UtPt#HII)tHMHULLf1HUdH+%(      HH[A\A]A^A_]@ H       IUHH!H]H9rKH       HHH)H9HBHz 8 uUHM   H;sIEHAzf.     H       HH       H)HH9HBHez 8 tHH= 1/     UHAWAVAUATSH     H0	  dL4%(   LuI  ~A&     )9ލ   CA  I  I  I  /  HHI`  H9   L-z A}    A%      AƆ
  A#   tvI	  H9sjHH)  fH*AY	  I	  H$  fH*X3	 f/  H,I9	  sI	       Iǆ0
      A  AP	    A}     HEdH+%(     HĨ   [A\A]A^A_]I`  L-z Hf.     A  1E  HIH0H1IHH4           AƆ&   )!	9  )A  #f     HEdH+%(     HĨ   H5 H= 1[A\A]A^A_]鷒    Ih  fHMI  )EM  HEA$  HxI@  EA&  )EAo  EA	  ]I  LIcH	  Iǆ      HAƆx	   HUELPpǅt   Hh)EH)3IHPH0HXH8DfpXt"H0%u@XtpHHhIH)tH8HLHLuI`  D  H=Q 1RI`  fD  A  )iHȃfHH	H*Xf\H,H?D  HfHH	H*XUD  UHH0Hp  dH%(   HMHƇ$   H   H       HH!H0	  H9  HHH)H       H9HBfHnL{z Hǁp      Hǁ0
      fl`  P	  umH  Hǁ      Ɓx	   A8 tTHEdH+%(   [  H5) H=4 1f     H`  Hu4Lz P	  tA8 uHEdH+%(     f     H       Lz H!H0	  Hh  H9s%Iы  A8I)I9   @  Hր,   tQH;x  sHH;  s?H  u1HH=ݾ LEH  1HuHMHMHuLEHH`  Hǁ0
      H       H)H       HH9HBSf.     Hx  I       IHt'I9r"@   ,   tHB     @u[Lh  Lʀ,   ]L@ HH= 1HMH5q LE(HMLEH`  @ HH=J 1HMH5 LELMHMLELMp HH= 1HMH5d LE踍HMLEH`  @ ff.     UHAVL5[
 AUATSHdH%(   H]Hƃ(  (	  P	      HcH	  H  H  H@  HH)H  H  u;Hp
  H   Hx
  H  Hǃp
      H  Hǃx
      	  H	  H(	  	  ĶHݺz    fn؀9 fpfփH	  u'(	  @"*IcL> H  H@  H(	  謐(	   HpuEH  H  Ff     H+	 9 ǃ
      ƃ$   HH	  u,ƃ(   HUdH+%(   `  H[A\A]A^]H@  H     H(	  	  tHz 8 tH= 1荋 Hz ƃ$   8 ]  pHz 8 0  X  ǃ
      Hǃ0
      ǃ	     ƃ#   ǃ
      HP  f1  HC@1f
  4  HǃP      3  Hǃ	     H0	  HX  ʈf1  QH0	  H(
  ;T	  4`	  fT	  Hǃ      *H`  f(^H  ^h	  	  #   %   ~	  fHnfl	  H(	  ,	  ƃ#  HH  V  H54
 HcH>ျ$   tH(	  	  EK0<0	  
  (,	  H0	  |	  3  4  S6S7HL(	  Hi(	  10H= 1H= 1H0	  HH  ƃ'  Hh
  H      H!H0	  H0	  H      H       H	HHEH    H!H0	  f1H0	  1     UHAVAUATSH   dH%(   H]H
  tǃ
         (	  L5
 P	  fHcH	  H  H  H@  HH)H  H  u;Hp
  H   Hx
  H  Hǃp
      H  Hǃx
      	  H	  H(	  	  脱Hz   fnfpfփH	  u-(	  >"  IcL>f     H  H@  H(	  d(	   H(utH  H  >H0	  fHnƃ'  flH  K0   HCH%   u~	  `  	  X  Јf1  1HUdH+%(     H[A\A]A^]H!&	 ƃ$   ǃ
      HH	  ufD  H@  H     H(	  a	  tH z 8 tH= 1 Hz 8   ǃ	     ǃH	      :HP  ,	  HC@1  HH    H
 HcH>Hz ƃ#  8   ,	  HC@    1HH  m  H`
 HcH>H&(	  H0	  H(
  ;T	  `	  fT	  Hǃ      *H`  f(^H  ^h	  	  #   %   ~	  fHnfl	  d$   tHK(	  	  @K07HP  ,	  HC@1  HH  Y  Ha
 HcH>,	  H0	  |	  4  H0	  HX  Hz 8   X  ǃ
      Hǃ0
      ǃ	     ƃ#   ǃ
      HP  f1  HC@1f
  4  HǃP      3  Hǃ	     H]z 8    ǃ	      H0	  fHnƃ'  flH  HCHHX  K0   2  12  ƃ#   ƃ	   NH0	  fHnƃ'  flH  3  HCHHX  Ո2  ȃ2  8K0 @  1fK63  H=ֱ 1XHP  H=i 1>H=  1+[H=% 1;H      H!H0	   H0	  H      H       H	HHEH    H!H0	  f1H0	  H      H!H0	  vH0	  H      H       H	HHELH    H!H0	  3f1H0	  $H      H!H0	  ]H0	  H      H       H	HHE3H    H!H0	  f1H0	  1118
     UHAVL5
 AUATSHdH%(   H]Hƃ(  (	  P	      HcH	  H  H  H@  HH)H  H  u;Hp
  H   Hx
  H  Hǃp
      H  Hǃx
      	  H	  H(	  	  Hz    fnfpfփH	  u-(	  >"(IcL>f     H  H@  H(	  ă(	   Hu@H  H  >H	 ƃ$   ǃ
      HH	     ƃ(   HUdH+%(     H[A\A]A^]ƃ	   fD  Hz 8    ƃ#   ƃ	   ǃ
      Hʬz ƃ$   8 uvHP     	  jfD  H@  H     H(	  詂	  2Hdz 8 "H=0 1-~H= 1~wH= 1~2H0	  HX  ʈf1  cHz 8 0  X  ǃ
      Hǃ0
      ǃ	     ƃ#   ǃ
      HP  f1  HC@1f
  4  HǃP      3  Hǃ	     5Hbz 8   ǃ	      HM(	  H
(	  ,	  H0	  |	  3  4  S6S7Q0	  
  =$   0H(	  ,	  ƃ#  '   .  f  HP  H0	  fHnƃ'  flHh
  H  HHJz 9 1H5S H=U |(	  H(	  pH0	  H(
  ;T	  S`	  fT	  Hǃ      *f(^^h	  ~`  f֓  	  #   %   ~	  fl	  16HP  HH     H=
 HcH>H      H!H0	  HP  H0	  H      H       H	HHEH    H!H0	  gf1H0	  X1Qf     H= 1zH= 1zAD  UHAWAVAUATSH   dH%(   H]H+         f.     h  }n  E  )  <	  H@	  HP  P   <	  	  HcEHN  HC0q  ƃ
   HP    H	H@	  +   uW1HuH	PE+  1HUdH+%(   O  HĈ   [A\A]A^A_]Ë<	  H@	  f@   ƃ+   ǅd    )H艍`HhH1z 8   	  fnH	  HpfnP	  H@  \H`L  HEHcH	  fbL  fEHHUI)   IjH   HrI   Hu|H~9NЉHH~LEILH	)HNtNxEUHHEII)t4H\HxLL~xEtǃ"b`  HP  C0   HCH    HS@HhH   S    ƃ+   @@ ~P        H  H  H@	  H  <	  fHnHP  flÍWC@<	     H	  H@	       H(	  
  ,	    HH    H
 HcH>@ Hz 8   ǃ	      H@ H`  H  H0
  H8
  H	  HC`    EHHs@HH@	  HHP  HCHf.     HC0   H@	  Hs@HCH    HP  ~0	  @ ff.     HX  3  ƃ'  ~P  2  Չflȃfl2  K@H  8JK0 @  fK63  4H      H!H0	  fHn|~0	  H      H       fH~H	HHEfHnGH    H!H0	  fHn)f1H0	  fHnfH=[ 1uH=y 1t&Hz 8    ǃ	     ǃH	      THz 8    ǃ	     HŢz 8 tfH~H5 H=ޣ 1tHz 8 tfH~H5 H= 1^tHP  H56 H= 1@tUfH~H5 H=o 1tZfff.     UHAWAVAUL-
 ATSH   dL<%(   L}Iƅ (	  I@  I(	  M	  MA   AP	  A(	     I@  IcH	  I  I  HHH)I@  I  I  u;Ip
  H  Ix
  I  Iǆp
      I  Iǆx
      A	  LHA	  Hz @  fnfpfAֆH	  6I  I@  HwA(	  I	      A(	  A)      "  IcD L>Ao(	  AƆ
  AH
  A#   &  I@  @ Lh   I  I  D  A
   tAtAƆ
   A(	  AǉA)   [A*   t
A(   tuǃ<Hp
 HcH>@ Hq	 AƆ$   Aǆ
      IH	     HUdH+%(     H   [A\A]A^A_]Ã   I@  AƆ'  LIǆh
      I   IǆH      gMuIh
  AF0   HtAF0  IP  IG@IGH    1Xf.     I  I@     HuA	  Hz 8 H= 1pLA(	  AX  A,	  AƆ#   
  IH  M*  H5
 HcH>AX  A,	  
  IH  M  H5
 HcH>A,	  IH  MV  Hޡ
 HcH>Hɝz M8   AǇ	           LxA(	  I@  I@  fIǆh
      Hǅ@    I   )0A!   
  I  AƆ'  IǆH      Iǆh
      Ht7 ff.     HI  I 	   p	  tI  HuAǆ	      L$g  Ih
  AF0   IFH    IF@1Ao(	  LAH
  !A(	  {  Htz 8 I@  H5 H= 1/nzA,	  ME  IH    HA
 HcH>Ic
  I@  ?  HA,	  HfA
  I0	  A
  A
  I
  A,	  CAo(	  LAǆ	     A8	  A(	  I@  LKA(	  I@  A,	  I0	  LA|	  A4  轸A(	  GAƆ
  ƅ3I0	  A#   G  A(   9  LHa'A(	  H4  Hz 8 M  A0	  A
  A$   tL<A	  A"   AƆ"   I`   IP  1AF0   IvHIF@1f.     A,	  Md  IH  q  H3
 HcH>Lu;A(	    Hșz 8 I@  H5 H=ۚ 1kA,	  8  Hz I@   H= H5 1;kƅ A(	  I@  wI0	  I(
  AT	  9t~A`	  fAT	  Iǆ      *f(^^Ah	  A~`  fA֎  A	  A#   tA%   uA~	  flA	  A9X	  *AF0    1 E1AƆ	   I@  Aǆ
      fE#  I0	  AƆ	  I@  I
  rI0	  A	     I 
  I@  AƆ	  BIP  AF0   IFH    IF@I0	  I   1:A	  G  H	 fI0	  E   )EHEH	 )E)EA	  E   HEE   )E  ЋDA 	  F    HA   H;z 8 H= 1iA(	  I@  GA 	  A,	         LcMH4CtHЖz :   	C   LI0	  HHDII@  IP  AF0   IFH    IF@I0	  I   1I0	  LI
  A(	    H7z 8 ^I@  H5@ H=J 1g=IP  AF0@   IFH    IF@1ILs9A(	    Hƕz 8 I@  H5 H=ٖ 1gI0	  I@  IX  H{z M8   AX  1AǇ
      IǇ0
      AǇ	     AƇ#   IP  AǇ
      fA1  IG@A4  IǇP      A3  fA
  IǇ	     =AƆ#  AƆ	   A%   uA~	  A`  A	  AX  ЈfA1  A,	  y  H~z I@  8 H= H5 19fA(	  I@  |IP  AF0   IFH    IF@1L,A(	  I@  ?I0	  IH  AƇ'  AǇ	     HEdH+%(   uIH   L[A\A]A^A_]I0	  IH  AƇ'  AǇ	     HEdH+%(   t I 	  HH`I@  fA1  IH    H
 HcH>A	  I  LPfAnH	  I  fAnP	  ,H0HxIcH	  fbfօpHHhH)   HH,HH HXHHLIff.     H HLHW~VXpb  "w<Lxi  J   H  N  S    S  HL@ fo0IH  MA(	  A,	  `	  A,	  H@
 HcH>Aǆ 	  Hz 8 7H= 1ycA(	  I@  fAƆ   A   A       H= 1"cAƆ	  !AƆ	  AƆ	  A,	  A  AƆ 
  Hz 8 sA	  H= 1bCI0	  fHnAƇ'  flAH  A	     AG0      LIG@IGH    
1H      H!I0	  I0	  H      H       H	HHEA3  fHnIG@A2  flAƇ'  AG0   IGH    AH  8AG0@  1fAO6A3  ,H    H!I0	  f1I0	  qI0	  fHnIGH1flAO0   AƇ'  IG@    A2  AH  H      H!I0	  I0	  H      H       H	HHEH    H!I0	  of1I0	  `f1I0	  1I0	  H      H!I0	  I0	  H      H       H	HHEH    H!I0	  1H      H!I0	  iI0	  H      H       H	HHE?H    H!I0	  &f1I0	  H      H!I0	  GI0	  H      H       H	HHEIH  AƆ'  A!     A#     A	   l   _  Aǆ	     LHEdH+%(   H   L[A\A]A^A_]D  H    H!I0	  T11I0	  H      H       H	HHE>H    H!I0	  %f1I0	  I0	  H      H!I0	  f1I0	  111I0	  IH  AƇ'  AǇ	  
   I9P  tLI  AǇ	     IǇH      IǇh
      AƇ'  Ht)HI  I 	     cI  HuAǇ	      L*C  AG0   Ih
  H      H!I0	  &I0	  H      H       H	HHEH    H!I0	  f1I0	   *EPEAx D\EoXA@A XptHHhHI)Wf	w   HLAxA@ H= 1z\A	   A!   A#   1LAO0LIH 3AǇ	     1I 	  H%HAHAA@pA@A@uAx A@   pIP  L& AƆ	  A
  I@  H5A H=s 1[Aǆ	  	   Lxƅ A(	  I@  6A	  H=ʐ 1LL ZL A(	  LCI@  A
  AǇ	     1IP  I   1AF0    IV@IFH       Lͻ1H/z 8 tH5 H=I 1YZA3  MŃ8tAN0 @  fAv6A3  IH  wH[
 HcH>1fHnAO0   flAƇ'  IG@    IGHAH  A)   P1I0	  뵺  H0H!I0	  I0	  H/s  H0H	넺H H!I0	  lf1I0	  ]ff.     UHATSHdH%(   HE1H?   IH 
    PHH  I$ HID$HCID$HCID$HCID$ HC ID$(HC(AD$0   AD$1!  AD$h)  A|$h*  AD$2,  AD$3-  A~D$8fl  AD$lfDX
  AD$d8  IT$@H	  ID$HH	  At$P	  AL$TH*\	  HH`	  HEH	     AL$X       AD$\  At$`  uNǃ      L%mz ǃ     A<$    HEdH+%(   Q  HH[A\]f     t1u  @ H  1ɐff.     HHuHHHH	  H	  %     1qf     1H=t VA<$ M  1H= qVA<$ .  1H= RVA<$   1H=0 3VA<$   1H=- V)   A<$ H=] 1Uf     H	O@ ff.     UHHdH%(   HE1H  HEdH+%(   u     UHSHdH%(   H]HH  Ht,    HH  H 	   tTZH  Huǃ	      H  H 	  HEdH+%(   u#HH]ZD  H 	  HtHRfUOHHdH%(   HEHH5ׅ 
wHcHz H4H<HEdH+%(   u1    UHAWAVAUATL%Y
 SH
 H   dL,%(   LmIf.     AE0   Aǅ       A	    A	  HcH>fD  LtR  AU0ց   $  $  c$  %     t1҃   AU8IP  AX  I0
  IE@H?I`  A~	  I8
  A2  I  AT	  fAM`fA֍	    I     LL
Aƅ'   fAH  A4  E1Aǅ
      fE
  A3  Iǅ	      A!     L5z A>       L8A(	  wA(	  IcL>I  fAƅ#   Aƅ	   Aƅ'   Iǅh
      AH  Ht3f.     HI  I 	   H  WI  HuAǅ	      LtA,   R
  Aƅ(  I`   uIǅ`     AE0    AT	     Aǅ	     AE8    A;X	    I`  I  I0
  I8
  I	  IE`A
     A   I	  Aƅ
     f)p)E)E)E)EA(     A(	  I(	  M	   ff.     AP	  f     IcH	  I  I  I@  HH)I  I  u;Ip
  H^  Ix
  I  Iǅp
      I  Iǅx
      A	  HLA	  JzL5c~z A/  fnfpfAօH	    A(	  ;"H5K
 HcH>IP  AE0   Aǅ	     IE@IEH    AE8    AT	  A9X	  +AM0AX	  ,  A   AM0I(
  I   A%   uA   Au0I8
  A1  A~	     HIh  HI  fAM4A1  IuhtA\	  tH1HA~	  HflIEpIE0AEPHUdH+%(   9   H   [A\A]A^A_]L0LLL|IH  I9P  tL[I  Aǅ	     IǅH      Iǅh
      Aƅ'  Ht/fD  HI  I 	   X  SI  HuAǅ	      LD  Ih
  AE0   IEH    IE@A	  1AU8AT	  A;X	       A(   Aƅ#  D  I@  I  HQA(	  f&LX  I  I  D  H Aƅ$   Aǅ
      IH	  ucAU0   AE8   4f.     I 	  HH     I 	  HHx     I  I@     HPA	  sA> iH=A{ 1>LVHRzz 18 Z  Aǅ	      AE8   y    Aǅ	     AE0    'Aǅ	       Aƅ#  A%   uA~	  A`  A	  A,	  6  A'         I0	  fHnAƅ'  flAH    A> =  IP  E1AU01AX  Aǅ
      IE@A4  Iǅ0
      Aǅ	     IǅP      Aƅ#   Aǅ
      fE
  Iǅ	     A3  1   AE8   KA>   Aǅ	      Au0   L蔚A,	  Aƅ	   Aƅ#     A'         I0	  fHnAƅ'  flAH    I0	  IX  ЈfA1  x1Aƅ	   Aǅ
      fA#  VI0	  I(
  A;T	  8A`	  fAT	  Iǅ      *f(^^Ah	  A~`  fA֍  A	  A#   A%   A~	  flA	  I@  I  Iǅh
      IǅH      I   Aƅ'  Ht0    HI  I 	     NI  HuAǅ	      LIh
  IP  AE0   IEH    IE@H	  A	  A0	  A
  A,	  I0	  A|	  A3  A4  AE6AE7A,	  Aƅ#  A	  A'   !	  IH     H{
 HcH>A$   QL蹲DL̙7L*A,	    A'     IH    Hr{
 HcH>Aƅ'  LAǅ	     iIh
  AE0   IEH    IE@IP   A)     Aǅ	     AT	     AE8    A;X	  NtA	  A,	  I  M0	  H   I}(H9Ƹ    HDAU HA#     AX  	  H  LA LH I`  L)H!H       HHH!H	IH9  H       H)H       HH9LBA>   M;  r	M;x  r2I  u'HH=u L(I  1XL(M0	  A-   K  I  LH;  @ I0	  A	  A	  I  Aƅ(   A#  fAnH	  Hǅ8   fAnP	  4IcH	  H8fbL@I  HhM@  fօ`H)
  IH(HL IHXLAfD     Hsn("  Hd`HHXHI)  H4HHLHn  H`tHhvH(L @L<A#  8t
A> C	  A(	  <Aƅ0   /A(   X	  } U  Hu} uI  H   I}(H9Ƹ    HDAU II`  H]  H       II!M0	  I9I  H       L)H       LH9LBI  HHF  L]HMELUDH HωD)HHHA  H 
  HHHH(A>   DUML+(E	  x  MD  IqIA Ht~H	  A(   ttA.  A/  q  tXI9M  MA 1H=t AQ(LLL ʌLL IA H   Ay)   I0	  H HL)H(H!I0	  A-     A>   E1w	  I0	  IX  1Aƅ0   fA#  I0	  I(
  A;T	  A`	  fAT	  Iǅ      *f(^^Ah	  A~`  fA֍  A	  A#   LA%   >A~	  flA	  $Aƅ(   E I  fHpfAnP	  )EI  I  HMI  )E)p)E)EfAnH	  HMA	  HhIcH	  fbƉ8I@  L@fօ`H)  HH(HHXL Ifff.     H8HHLHj~ZH`t8JLhw:H=s
 HcH>AA0fff.     dHHXHI)uH(L EUtuH=p 1UA(	  A(  I0	  H   H9zI  nAƅ#   Aƅ0   YL1A(	  EA$   7LA(	  #LA(	    
  IP  H=A)   6        A	  IE@    IUHA>   AE8    AT	  A;X	  AM0AX	  IP  IEH    Iu@oHAA1AH`_oHAA3AA `BH(L AA4EUOoHAA2AA`I 	  HHH=n 1=H(L L<E   A(	  I  M  L@fAnH	  IcH	  HMI  fAnP	  M  HMA	  fbI@  8HpHhfօ`I9t  HII)L(HXMHq
 MfD  H8HHLLf~JH`t(JHhw*HcH>F0D  dHHXII)uL(UEtk  A(  /oHF3F `oHF1H`L(UF4EoHF2F`]H==k 1;Au0   Aǅ	     AU0   AE8   IP  Hn      IP  H
   Ix  LLH)H       H9LBH=j 1;dH=k 1;Aƅ#    g  A> ]  1H=Kl :A#  1H5j H=j :A	  I  fHpfAnP	  )EM  I  HUI  )EHUA	  HhIcH	  8I@  )p)EH)EfAnH	  E   fbL@HXfօ`I)   LH(HL MH8HHLHc   H`tlHhtT	tOH(L LuoHF3F A#   jIX  EHxSnHtdHHXHI)MH(L LA(    Mo  Mt  IA LH H1HL;(   IqHHAy(@uDA"(  
  I0	  !AHH)H H!I0	  A-   d  A> 8  E.     A  13H1E  HHH1IIHH	A(   d  }   Aƅ.   M;  r	M;x  rQMtIQ HR  H=n 1E/IH    H4l
 HcH>H=%i 1L輦A#  Aƅ/  A(	  A0  IH  Y  Hk
 HcH>H1H5l
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 H=h LD6A> LH 1H5l
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 H=@h M6A> L OH 1H5k
 H= h L6A> LH1H5Xk
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 H=g L5A> LA  i  H HH5j
 1L H=l r5A> L tH(H5j
 H=g 1E5L LL;(l  M;  _  M;x  R  Aƅ.   qx+  MtIQ H
  H=k 1X?H=f GEI0	  fHnAƅ'  flAH  Aǅ	     I0	  H/H      Aƅ'  H	fHnflAH  AE0AE0tI0	  H/H      Aƅ'  H	fHnflAH  AE0fAH  _H      H!I0	  HI0	  H/
H      Aƅ'  H	fHnflAH  H    H!I0	  Hf1I0	  HH      H!I0	  HH    H!I0	  Hf1I0	  HH      H!I0	  HH    H!I0	  Hgf1I0	  HUM  Aƅ.  ,MtTIqIA HyH=6i L(}L(}L;(rM;  rM;x  UI  ;HH=d L I  1|L I0	  H=h 1H   2+Ay(`A0	  I  PA3	  PI0	  HH)H H!I0	  A-     A> III0	  H=Ih 1MA 1I0	  HH)H H!I0	  A-     A> III0	  H=g 1MA +1III0	  H=g 1MA 	1A0	  I  PA3	  P|M;  rM;x  ]HEI  uHH=2c I  1!{M`  HHH)H       H9LBW111IqH=g 1LL zL LAA)A  1H 1A  HHH1HHHH`M;  rM;x  IqHF  H1fD  	   (&wH_d
 HcH>   hHILL1H=)f L(e/L(DI0
  AX  H?i   
   A:Q(MA AQ(ωщA0   '  wH=>a 1dyA0	  I  PA3	  PA0	  I  PA3	  PM1҃T1P@ 1H=` L xI0	  H L HL)H(H!A-   I0	  taA> I0	  H=d 1H   .A.  E/  u<E_<1IA0	  I  PA3	  PD@ UHAWAVIAUIH\ ATILSHLO|% HxEDELMEdH%(   HMȹ   )H      HLIHJ\ )HHtlLLL)H)HL)HuH)I܀}    HL9siHHfD  HL)I)L9sJIt$Hx   IH[ U)HuHEdH+%(     HxL[A\A]A^A_] HLLLH)H  MtIt$H{   Hr[ (HtHH)HI)f     HvIHSIHf     H)HD   HH.L9huL9puHMHH)I)tvH]LmLuLLpIE    Hx#     U  tHIH)tLLHLdUHxHMHHMIIIH     L)H     LH  H9XuL9huLMIL)ILE    LmLuI)HULHx+     U  HIH)LLHL|T HEJT# KD'
8N  J8H[  H8JE  H8J/  H8J=  z@8xuO'zHH@8xIDIJLxAHEHMILpHELxHEHpLhfHE    HM     Utht#HIH)tLLHLxS@ H]I   H}X Hs%HtNHL)IH)H]HvfD  HEH;EtVHMH9s-H)H H9r} uPL}G    HH)H H9gD  H;xSHELxHpLh HEIDH)IJD!A8AO8H   HA8O   AO8H   AO8H   AO8HupIWIO@A8GHDIyMqHELeIHxHE+INLxELx<Lx3Lx*UIII
II     UHAWAVAUIATSHhHxdH%(   HE1HUz HE    Hu8   I}(HUH5AU   HUH   I  H   M     H,V HL#IHthMH)LEMI)ME    MtILELmM@ U   t'HII)tHMHULLPfD  1HUdH+%(     Hh[A\A]A^A_]@ I  Ix
  Iǅp
      I  Iǅx
      I9x  I  I@  Ip
  Iǅ      Hu   L.ot	cHU Ix  LEH       H!HuH9   H       H)HH       H9HBH;xHSz 8    H]IpI  IǆP      I@     M  HqT L)H{I  I@  Aǆ	      Iǆ`      AƆ$   LE!H{LEHHEH)I)D  H       HH)H       HH9HB&    H=\ 1LE$LE!D  H=I\ 1$7     U@HHdH%(   HE1HRz HUdH+%(   uU@HHdH%(   HE1蜮    EHUdH+%(   uvfD  UHHHSz dH%(   HE1HHHHt@@   tuHUdH+%(   u#D  HcHHHt 1@ ff.     ULcHHL*Pz dH%(   HMHHI4 %Ht   tEu	HUdH+%(   uD  IIHt݋Yf     UHHdH%(   HE1@wGwB@HQz HHHHt'@  uuHUdH+%(   u#@ 1@ HHHtƫfD  UHHdH%(   HE1@wHTz @HHt@HUdH+%(   ukf.     UIHALHHdH%(   HE1HG    HH)pH   IpX9IphOEHSA@PHcHAIP`A@QHEdH+%(   uժD  UHAVAUATSH wdH%(   HE1@t%1HUdH+%(   
  H [A\A]A^] HGhHW`HHHH9  8  HHH9  x  HHH9  xx  HHH9~  xet  HHH9g  xn]  HKhHHICH   H98  8@uE1A֪uωJ
vR  usPLcHChCHPHShHPH9S`   xA芪DJ
=  EEt3D:+tAt(D:ktAtD:ktAtD8ktA   F,#AL$iCQ{S DCQWHChHPH9S`rPD(DEHShHK`ƃ7  HBADkCHChtCPHCH9=  8HHH9xHHH9xkHHH9zxvpHHH9cxm>TAEtSA8tg  Dk{S HShHK`HrCH9LDp   LJL9,sSz@tiDC@{      C@{LKh1uHrDkH9BCHshC	tCPCCCAAAu눃uHBH9B8tsS@u@@uDCCHzH9dBCH{hC@tyCPHBH99BHzCH9%BCH{hC@uID:+uAD8kuSAuD:kkSc聦UHAVSH dH%(   HE1 t$1HEdH+%(     H [A^]@ HpƅuHShHBH9C`8  
HChCK{    C=  {  CL{S tL   tECL          H߈MsM܅uW{@   SLbCL`  HShHBH9C`   
HChCPSL{ tst{MGM܃?  {]  s@H߉u؈MRSM܋u؅uL{ H߈M/MfD  |fD  MXM܉ D  {u؈M詥SM܃u؃_  C5  ƃDCEA@ADE%CL   t {DEv{ xAu	CPD    @ t{    {   CL    CfD  sO@ {	 x"ۤCLfD  s@    M賤{ MA   s   C   DRCLsf.     %  ` \CL    f   AHxvsOCL   
    {MM܃t;{tAs@OHM(MPM܉*ss蜢ff.     UHSH(dH%(   HE1$ t1HUdH+%(   7  H] H8?u؋CLĀt#HKhHQH9S`r~	HShC%K   u{S t
CNtCPC$ {    su_C   SLI CL{ t0StCNu1CLH@ :fD  HfD  {M脢M܃tB{tHs@fD  H߉MMWMMTsHsfff.     UHH dH%(   HE1S u1HUdH+%(   u.@ H}O0uH}% tG <諠ff.     UHH dH%(   HE1, t1HUdH+%(   uv@ H}/uH}% t!QtG t<tfD  G,f.     HGhHPH9W`r HWhG-G(Ҹ{ UHH dH%(   HE14 t1HUdH+%(           H}9uH}% tiW <t]<ti@<QtuG(<u@t*HWhHBH9G`r|HGhG5W0@ ff.     G4X    HGhHPH9W`rB HWhG5G0f@utHGhHPH9W`r HWhG5G0 UHH dH%(   HE1< t1HUdH+%(   2       H}'uH}GL   u%ptXH
 HcH>    GQ<  <  <uHHGhHPH9W`r: HWhG=G8GDG<`    WPJ   ttT@ 9fD  HOhHQH9W`r	HWhG=O8   tHGhHPH9W`r HWhGEG@HWhHJH9O`rHOhG=W8fHWhHO`HrH9{DHwhHrG=DG8H9_RHwhGEW@w@ HWhHJH9O`6HOhG=W8N WPw  *  HWhHJH9O`HOhG=W8GDG<@ WP   LGhHw`IHH9E DG8LAHOhW=L9LGhG<W@  fWDfD  HWhHBH9G`VHGhG=W8@ HGhHW`HHH9+0HOhHHG=w8H9@HOhGEG@LGhHw`IHH9E >HWhHO`HrH9DHwhHrG=DG8H9RHwhGEW@HOhHQH9W`	HWhG=O8S UHH dH%(   HE1R tHUdH+%(   u&fD  H}uH}HWhH+WXWRD  UHSHdH%(   H]Ht^HHEu{ uHUdH+%(   u3H]Ð{$ t߀{, tـ{4 tӀ{< D1H6_f.     f.     f.     UHHNdH%(   HEH0  9   HUdH+%(   u ff.     UHAWAVAUATE1SHdL,%(   LmL0  AEH       H{hI蓪HCh    H{x肪HCx    H   nH{ Hǃ       H{@H{8H{0HwIE@JD     E;eHs IE@O4J\ HnIE;eHrHEdH+%(   uHI}@[A\A]A^A_]Y@ UHAVAUATSHL0  dH%(   H]HI}XHI  Hǃ0      nHt3HfD  IHLI  HLHuI   :I  ^I  I  I  zI  nHEdH+%(   uHL[A\A]A^]fD  U   HAWAAVAUIHPATSH   dH%(   HE1HIEx(  L  H   IA     A   uoA	   ue   IF@H}   M.E~IEpH(  HH9   A       H H9tx9Hu@8 u1nf     A   `   9BH@H<   IF8HlI~@(I~8I~0LE1  fD     A   H(  ~y    fHnH4  IFPflAFXfHn)P~y AF`IEpI  flLxH(  hHt;HH9t3A   f.     H H9  9HuHH#xt1@ MHH9t=A   ff.     H H9t 9HuHp   Hu1       @}HH9tA   9HtH H9u1    H@HEIp  fA  EHtF@=  H1    HtHH9tE   D9@  H H9ufA|  Al  fAnx  EA  fbÉufEI   fEHEA  E@t4HH9t,A    H H9t9Hu@tu	E   fA  ~H^/  H`A   uuA   ukI|$8Ht   H5= uMHPdIF HFHEdH+%(     HĈ   L[A\A]A^A_]    I0  Hu$HEHuE   HE   l    A8     tluE   HE<    H#pHfHnw       fD  A(  H<   iIF0HfA   1A   E   HHH1HHHHHE'1E   HE UHAWAVAUL  ATSH8HuH  dL<%(   L}IL94  H+  E E1E HMff.     DcHsHE	H   H}&uyLK8M9rpHC@II9scH6z 9 t:EH L& LEHLPHM1H=@ HuDcXZEE   DEEAEĈEHL9YD]HMEEu*} u$H[6z 8 tHuLH=@ 1!EHEdH+%(   =  HeD[A\A]A^A_]f     LE1E1A   E1(fD  ff.     ff.     HI9   CA	H{H uLK8L9rHK@J4	H9sH55z > tFL H% LDHH=? 1QHuH HUNCYA   HU^HDEEDI9tEIEEH)5z 8 HP @ H	5z D EE1HIf     UHSH8dH%(   HEHHH  H	   H  L  Hu        HBH   HH;rtnrHBHuHZ0   HuHUHMLEHt=HMHufHHU@HHpHuHH H@(HHE#HEHHEdH+%(   u)H]H@ HZ|    1Li/@ ff.     U1HAUATSHGPdH%(   H]HIHGpAHt9PteHH   L`pHCp    I0  趟H6z Hǃ       x$ uNLD#IHtcHSH   HtOLcp1HUdH+%(   uAH[A\A]]    H{xGHCx    DLTHCxfD  ,ff.     U1HH HO(H7dH%(   HUHf         ǂ      t      t
          t5A@   Au       A8At    @  fD  HEdH+%(       t4Hy    y    y    ǂ   #  VfD  Hy uyǂ          t	      f   o         y V       G    ǂ   !     HUHu HUHu艂   HJ(lfD  ǂ   c   lff.     UHAUIATSH(H^ dL$%(   LeI~tV   uLHChHtlPSPA|$u@CXA       HEdH+%(     H([A\A]] sXI}x%CTh  H{h诜HCh    STtI}xHChHqA    tf.     DcPErHDHxpH0  IHPH;CptPHCp    H{x*HCx    H   11LHǃ       OH   H   LkpHChH   H   LM$H{xM̉Ht;Gt;E諛HCx    UȋMLMȉUŰMHHCxHt4D   G         f    CPfo    ?;ff.     UHAWAVAUATSH   H$ H   `  Dd  (MHMI,DMdL%(   L]D]       E1   Hu@      DDL0DHH DHL   ASDAQHQH V   AUDD(,H-z H08 tA @  8       I|$pL1)Aƅ   HEdH+%(     HeD[A\A]A^A_]ÐE1@uHu@   DDL0DHH HLDASDAQHQH V   AUDD(,H0A @  uH,z 8 uJArD  H1+z DHW7 101\    kHtHL贇@ UIHH0dH%(   HEHH0  HumH~IE1HGHv!HEdH+%(   ulHz@LLfHuH   HMLMHUĩHMLULMHUI    HudH+4%(   uHz@E1HLVUHAVIH50 ATSHHdL$%(   LeIt9H50 HtFHEdH+%(   uLH1[A\A^]f.     LHA$        I$  LH-FfD  UHAVSHH50 HdL4%(   LuIRtHEdH+%(   u-H1[A^]@ 11HHPHwAͅfff.     UHAWIAVAUATSHH  \HG@L7Ln(dL$%(   LeLg(HxI@  HtAI  HNI  1H9s(HEdH+%(   $  HĈ  [A\A]A^A_]ÐHfHn¾   flHHp)`5HxA   fo` 	   fD@H3HCP    HtCHC(Hx   x   ~   H   ~   Hf֍CXo  )   (fAG9uIG HA$     I$  HH  HC(x   @  @     H    Eи   EHxfPAt>A$     I$  Ht"I   H@ ff.     A tA     A     A$   uA$     IGpHpH`HA$  HPIǸ   H`M$   H)I   IH
 E$   L@`ff.     x)   DtHtHcI	wHIHO HI9uH`HPH A#$   HH I	W   I$  t0ff.     H
H   HHuHuH@ A$   1  I$   HHHS(z   H;   @  @     Bи   BD  Hx Jx @fD  A      A$   LK8uA$     I    MAM$   M$  I$  At{LfD  ШuaHII@HGI@HOHIHI?H?D	II>AAD	II=AAD		I@IHuI   II9jHC8HHAtA$     A @ tDA$   Ht&I$  HH   fHHM  A   t*A$   t\  H!    HA   tA$      A   t5Lp1LLTL1LHxfCHuI~pHpHx| u&Hpx购xQf     H"z Hb/ 1x01xf     A$  A$   t$t I$   tH       HH!H	Hf.     A$  H HC(H@ A    BH   fD  I$  H@ A$   A      I    fD  >  I$     HH^
 HHH   hH   P@HDHH%   H	Ȅ   H)    HH?f@HD  @     A(  HS0sXH{hM   LkHC0H@/ HH3A   sXLH{hHH
 HHH   hH   P HDHH%   H	ȃ@%H(H} z H, 101}ff.     UHAWAVAUATSH(dL,%(   LmI~I   IHvMt$   M<$A    uA   t{It	M      H{p   HShIUHSpIU HSXIUME  3  AEA|$J tAD$II}   HIt$Mt$A|$I o  AD$I$HHA@H<xHH<  ID$HP(H*I$H@pH@  x#   p1HHC(HH  f.     HHKE LMA  IvI~(E   PbHXZHtA   unHCHC(HKpH)HCht
} tCIIEHCpIE HCXIE{I AE HC`HIE  HSIUHS(|    H{(H1HMH){HMtfHxMtL# IE    1HUdH+%(   u&He[A\A]A^A_] MtLI\$z@ ff.     UHHe* HAWAVIAUATISHh  HHz H5 H;dH%(   HE1ǅ    ּMY  HHǅ    HxHHHHp     HxHLMH0A   .   ADOEdH;1HH|# H5 5IcHM$    AM H;1IHƍ H5 M9uA&@ H;H 1AH5 ԻAuE~yLpH   L~H;LHl 1H5P 菻HHH)HEdH+%(   u/Hh  [A\A]A^A_] H;H" H5 18qxU
   HSHdH%(   H]HHEdH+%(   uH(  H0  H]xfff.     UHSH8dL%(   LEL0  A    t%1HUdH+%(   .  H]f.     H@  IIx#    Xx     1   LULMLELELMHLUH   Ix@LLELkHz 8 YH}1҉AHCHEH=5 HpHX(HulHuHH}}f1f     H}HxLEHuLMLE؉LUI@   vfff.     U   HAUIATSHH(dL$%(   LeI	   fBFPAFTAH    tKHF(Hx '  x      AD$   AD$   A$      A$   CXAD$X   fA$   o  A$   A    $  HC(HHI$HC(HpIt$HC(H   x    H      H;      BBA$   ID$0      A$   fBA      A      HEdH+%(   )  H([A\A]]     Hx 
x  fD  HH?H?~ef.     x    H3      H;      BB-fH   I   HUHUID$ A   HS8sXH{hHC8I$   A(  HS0sXH{hM   M$H˸HC0I$   f.     HH?H?ysD  UHATISH H   dH%(   H]HHt&HEdH+%(      H [A\]z@ LsHcY{ HtjHп
   HHH=  ~H=      zM   P   rI$   HHxHEdH+%(   uMH 1[A\]@ H5X{ H=HE9HcX{ HU؅ltX{ @   @   Xrfff.     UHAWIAVAUATISHXGHHULwHHA@dH%(   H]H_L,f.     fHLHE    )E)EHH  HP(H  M$A    uA   @t{It	M      HKpH  HChHSXHEHMHUM  @  EH)  M;t$tM;t$tL#HuH}IAׅ-MtM9t$tM9t$tLEEHUdH+%(     He[A\A]A^A_]f.     HHKL]LMA  E   E IvI~(PL]HXZH  A     HCHC(HKpH)HCht
} tCIHSXHEHMHU{I H{`E HWHUHff.     I;\$%I;\$HD  I$H@pH@  x#    p1HrHC(HH
I9   I;\$   I;\$tHxD  HK`E HQHUHDRfHCH@ H{(H1HMH)pHMfHxT1Mt	f.     
I9tI;\$tI9\$tHloff.     UHSH(dH%(   HE1         IH   I9OIX@BAAKH;pt7   A1HHff.     H(9   ;puHX Ht0{L t*C\   ~?uHCz 8    C`   HUdH+%(      H]D  wθ   fAnfn1fbfC\D  9sK)HJHHT(     H(H9t;puAD  {H tC\   \H=' 1hII   LLE`LE؋sH   HIxX膵 CHm UHAWIAVIAUATSHH   IHHPL H@xdL$%(   LeMHXH`HH0f}C        IMt	I9H  IL$(I$y   IL$hH;   C  H  ǅ   H HP HƅBACHE1H8HH0HhH  LO M  A  G  IH H(4 uHGH+H(A t`B tWH(HXLLH#LHHtH HPH  H9  IHhH LHyLHEg  ADL(DYD  CI   L98  HcSIH;PIC  HhH;P{  HcCIHXHHA   LHM|H[  DHHH}   Hz 8 VI6HIGCK{ x  HL B    HP +  HhH(HXHx H  1l       H      A   ID$pHXHtAD$PA9$      Hz 8    ff.     H0诽HEdH+%(     H   [A\A]A^A_]     E1HH01L e H  ǅ        Hiz x$    A   LQu}ID$pHXIL$xH  AIaA   H   :@ 1LLH菴  HhLH@ Hz 8 H= 1RD  Haz LH; 1LH= LX; +HXHagHhM.Lp M   M  LљIHL`(LLL+ Lh AF(CAF,CAF0CAF4CAF8oCAF<xuLL1SfD  ƅB H!H^z 8 H= 1'AtHH5z 8 |H= 1iC        H= 1Dǅ   I$   IZHXLKgHcL{ Iǅu-H5L{ H=:HcL{ u}L{ @   @   L
   HHH=  ~H=      zM   P   ؇I   IHL1fD  H1z  Hu#=  H0%`H	z  tI6H= 1HHHHMA   HcSHXLuH5
z DHHtn   E1DS2HHHP IP(P,SP0SP4SP8So@<H^
z C8 6I6H14Hperf,pH3EHtwrite  H3MH	mpH=s 1DHUH= 1?I6H= 1e@ ff.     UHAWAVAUATSHHhHF(dL$%(   LeIDpE6  H  M$$E1M$  Iİ  M9   E1E1fD  MM9   ABA	IzH uMJ8L9rIR@IH9sH	z 9 tXL H LpLEHD1RHHH H= LpDZYABMEDDEM9aE   E   H|z 8 t*H HH1H= D5DE   D  I<$H;      Ml$hM   H}sHMHL   H   HEHH H   Hڀx4 tAI<$H   HNH}AҶHEdH+%(   uRHeD[A\A]A^A_]ÐHPH+    HEdH+%(   u HeHH1[A\A]A^A_]E1bff.     UHAWAVAUATSHX  L'Lw@dL<%(   L}II$@  HtHI$  1HJI$  H9s-HEdH+%(      HX  [A\A]A^A_]fD     HOLLLHzI~  fl)A$   u1I|$pHLÅuWHÏafD  I$  1HHH1LfAFHvÅtfD  Hz 1H6 01ݦHQGa    UHAWAVAUATSHh  L'Lw@dL<%(   L}II$@  HtHI$  1HJI$  H9s-HEdH+%(   6  Hh  [A\A]A^A_]fD     H߄LLLH
Iǅ    ǅt    ~(  IG(ǅ   H@xfl)HxHtH8A$   u.I|$pHL ÅuTH& I$  1HHGH1LfAFHÅtfD  H	z 1H 015H詍_@ ff.     UHAWAVAUATSHh  L'Lw@dL<%(   L}II$@  HtHI$  1HJI$  H9s-HEdH+%(   F  Hh  [A\A]A^A_]fD     H/LLLHZH u
ǅ    ǅt    I~   IG(H@Xflǅ   )HxHtH8A$   u4I|$pHL ÅuZH^f     I$  1HH臇H1LfAFHÅtfD  HIz 1H 01uH]@ ff.     UHAWAVAUATSHh  L'Lw@dL<%(   L}II$@  HtHI$  1HJI$  H9s-HEdH+%(   F  Hh  [A\A]A^A_]fD     HoLLLHH u
ǅ    ǅt    Iǅ   ~  IG(H@`fl)HxHtH8A$   u4I|$pHL`ÅuZH螊f     I$  1HHǅH1LfAFHNÅtfD  Hy 1H 01赡H)\@ ff.     UHAWAVAUATSHh  L'Lw@dL<%(   L}II$@  HtHI$  1HJI$  H9s-HEdH+%(   F  Hh  [A\A]A^A_]fD     HLLLHH u
ǅ    ǅt    Iǅ   ~  IG(H@hfl)HxHtH8A$   u4I|$pHLÅuZHވf     I$  1HHH1LfAFHÅtfD  Hy 1HN
 01Hi_Z@ ff.     UHAWAVAUATSHh  L'Lw@dL<%(   L}II$@  HtHI$  1HJI$  H9s-HEdH+%(   F  Hh  [A\A]A^A_]fD     H}LLLHH u
ǅ    ǅ|    Iǅ   ~  IG(   fl)|H|H8A$   u,I|$pHLÅuRHI$  1HHGH1LfAFHÅtfD  H	y 1H 015H詆X@ ff.     UHAWAVAUATSHh  L7dL,%(   LmII@  Ht=I  E1HQH9s*HEdH+%(   t  Hh  D[A\A]A^A_]fIE(Me@   H   A  *|LLLHUH u
ǅ    IE A  ǅ|    ǅ   ~   IE(@pfl)	ЉtA  xHtH8A   u3I~pHL AǅuYH=     M  1HLh1LLfAD$HAǅtD  H)y 1DH 01THȄyV ff.     UHAWAVAUATSHh  L?Lw@dH%(   H]HI@  HtII  E1HJI  H9s/HEdH+%(   z  Hh  D[A\A]A^A_]       HOzLHLHzH u
ǅ    HHK(ǅt    ~X  tfl)Q	Јt   Hǅ    ǅ      HtH8A   t8IP  1HH~1HLfAFH6AąuIpHLAąu5H@ tHAHxR    H)y DH 101TTfff.     UHAWAVAUATSHX  L'L@dH%(   H]HI$@  HtHI$  E1HJI$  H9s,HEdH+%(     HX  D[A\A]A^A_]@    H_xLHLHHHS(A$l  ~     fl)   HH{M uwHt$H   H+   o   H   HB H   A$   uhI|$pHL4AŅ   Hm     H   H+   HHtoHB H+   EI$  1HHg|1HLfAGHAŅ[ufD  H!y 1DH 01LHORfD  UHAWAVAUATSHX  L/Lg@dL<%(   L}II@  HtII  E1HJI  H9s/HEdH+%(     HX  D[A\A]A^A_]       HOvLLLHzH    IO(I~H         flf	)  ~HH  HcHHH@ ff.     HB    HHJHHH
H9uH  H8A   uHI}pHLAƅunHD  ǅ    f     M@  1HL(zL1LfAD$HAƅ{듐Hy 1DHm  01H~$~P ff.     UHAWAVE1AUATSH(dH%(   H]ȋ^`   Hy II8   At$XI}xٺXtAAD$HIE@L<I_ AtiA   u^HChH}   PSPAu@CXA       AD$`HEdH+%(     H(D[A\A]A^A_]fsXI}xCTuCPH{h\`HCh    STtI}xHChH`A    s DkPEcHDHxpH0  bIHAH;CptPHCp    H{x_HCx    H   _11LHǃ       H   H   L{pHChH   H   LMH{xMHt^;GuCD   G         fvXH= 1     E_HCx    UMLMUGUMHHCxHufoMi    !Mff.     UHAVAUATSH`  dH%(   HE1M tIH   HH+   t6L/Lw@I@  HtSI  HqI  H9s<ff.     1HEdH+%(   (  H`  [A\A]A^]f        HHHqLHLHsHH~  HHH   flH+   )o   H   A   u*I}pHLGÅuQHz"I  1HHuHL1fAFH?Åt    Hyy H  101襑L ff.     UHAVAUATSH  L'dH%(   H]HA$  t#   t*I$@  Lk@HtFI$  HJI$  H9s-1HEdH+%(   .  HĀ  [A\A]A^]fD     Ho   AE 	   fAEHCPHH    tCHC(Hx w  x m  ~   H   ~   HfօCXo     8f$A$      HC(HPHHHHH  x !  H      H;      BB   @&Hǅ   fAEH~  fl)A$   tNH'y 8uBH`foe Hǅ    HXfof)`)p H{M tH   H+  HHt$H   H+   o   H   HwA$   t<I$  1HHrH1LfAEHLÅI|$pHLÅHmy H 101虎i@ x ujH      H;      BBdfD  H   I$   ܪHHx x yfD  HH?H?rf.     HH?H?qeHD  U(   HAVAUATSHHp  L'Lw@HdH%(   HE1HI$@  HtII$  HJI$  1H9s.HEdH+%(   a  Hp  [A\A]A^]f        A	   fAFHCPHH      CXo     8f$A$      HC(HPHHHHH  x   H      H;      BB   @&Hǅ   fAFA$     A$     H u
ǅ    HHS(ǅ    ~     fl)HBPǅ   HHHHA$   t<I$  1HHo1HLfAFH'/I|$pHLHHy H 1|01p|D  HC(Hx tex t_~   H   ~   Hfօx    H      H;      BBOfHx x f     H   I$   LHA$   HS8sXH{hHC8HX&     A$(  HS0sXH{hM$   LHvHC0HPfD  HH?H?rf.     HH?H?qgDD  UHAWAVAUATSHHHHudL$%(   LeL'M$   Mu,Ml$xIp  H>
  I$   A$      Hy HE )  HE          Lk(L;ƃ    A  IU H     IU0H   CMHy x$ tA} uA} tHzAE A1   t	S  A
   t   @  A   t]  HC(  9   tHAƅ  AE t'?	   V	  @/
  	      t Ax     A     AE A   t
  A   t     IUHsXH{hA    W  E   MEIMAQE   AQE   AQRD      kH A   t5AEA8EtIMHtIUH  HAE   {L t%HIEH;   A  H  C\    H{ ǕDpIE   A=  {L tI$   I9E5  I}@H   A$   L3D{P1DCTA    `  A    tA} k  1HMMSXAuWLQDPH Aƅ7HEdH+%(     HeD[A\A]A^A_] IE(H   A   2fHC(Hƃ   轲A$    t2IUI$   H9sHuIUH9sH  f.     {L t
{\p  IE8H9   sH   L   M   A$    \HuH   H;HH	;<fD  HS(H;   tH  H  0   C  H8  4  H   HH$AƅAE MH         I9G   H;     ƃ    Ds\A   MD  Ds`CL AHE8 a  sXI|$xDcCLHID$@H4ԲC`s     I   DE DE          D   D   }S\5  C\   f        Hƃ   H  L(L   L9  H   ƃ    HH  LhL   MA$   -A$    ID$pH(  HH9A$   ff.     H H99Hu@8 uA$    A$   ID$xIǄ$       Lh  MtLKusI} BIHtbH]HC*<u<H{-H56 u(HsIE A}4 u
HI+MHH9r
I;u  H[HHuH]Hy IǄ$       HE HH   I9E|   %   h{`^ ff.     HE8 ;  IE@H   G       C\6  5  HLAƅ  C HAƅ-AE @HAƅAE @ HAƅHXAƅA   H'Aƅ    KPSXH=+ 1sDCTEHAƅuAE @ H8AƅUAE @      E1HH}IH  LeIHDDDHAH   DDHHHHDAHHƃDDHHHHDAHHƃDDHHHHDHA Df     HcH@IH(  H  8  H0  Lx  K?L  HHI#  5  =  H 0       HH  HDDHS   DHHHHDSHDHHHHDSHDHHHHDH @ LIp  @ HHAƅAE  HAƅvAE D  I;      C\   HXAƅ%AE T@ IE    HHUHM(AƅHUIE    HIUHMAIMD  sXDH=Z 1l    HAƅAE @ Hy 1H0 01'~H;    IU@Iu8H=d 1H 0   A    A   fD  LAE Le   1@ A     H}ALLe0   tHH8  4  H-y DH 101X}ƃ    L9mY{L uH{ LsZ{Lm6H;H'C\   L   H]H;A$   H H HuHDHLeLIIH{-Lu(HCIM A}4 u
HI+uHH9r
I;E   HHHuLeHuLHy I$   HE8 upA$   AƄ$   AL$HI|$@1Jt? Ht'FLAL$H9I|$@I(Jt? Huك9eI(I$   1H= ڬHE A$    3AƄ$   AL$HuLeHuLI$   6ff.     UHAWAVAUATSH(O`dH%(   HE1   HIfD  HCXHHE؎C`tHCXH@HHEI9sLeLH-HuL   t_AFH S`   HCXHPL9sz HIHC@L<Hy Mw 8 mLDH= 1衫T@ HUH}D|yfHEdH+%(   u1H([A\A]A^A_]1@ HUH}DE|M4ff.     UHAWAVAUATSH   Hay dL%(   LME1ɀ8   P   A  H0  HzIIHGH        Hǅx    AE 	/  i    |  PX  L5y   E1A>    IJd  uh  umX  
  ARXAu H=  1LxDpDpDx(A>DxuHtH1L]DxfHEdH+%(     HeD[A\A]A^A_] {L F  Hǅx           I(     AE 	   tI           H    %  HCpIr LpH(  H;   Lp	  AE fD  H   HpULpHHx{L       'L   M  HxHLp!LpAf.     AE MbEuHE    sHLpE1At	  HELhAL`HpDIމI~@KH4Ln Mt(A;]Tu"M   LHpLEFHIE9rLhL`L?@ ARArLpH{xFLp(  L   HArXMJH  .H  LpI      tfff.     I      AE   AEt     L5:y D  HSpLH{@MuLpULpIHCpIr H(  GMLpHH  MG M;  H2  I@(  O<6K7I(  IR I0  HCxH  Hx8Hx     H5K LhLpH`HXsLpLhH`     y/
  1ML5+y C8  AE f.         L5y lA> B
  ArXAMLpAUH{xvSLpA'      HAJARXE1A      HPA   PArEBLp赤H AvAE LpH    	    EuD  EzX   @	  fA  ABEbhL5y A
  IJDDHLpܾLpA~.H{xhDDYRLpA@ ff.     E
AE fD  KHCL Hǅx    LpLhE1fff.     HS@KD L<M;?   Mg EMb  A|$H ~   A|$L tA|$\tn    ueL=y A? 4  A$    tI$   H       I|$ H@t\uA? 5  fff.     KHIA9@LpLh    Hx fHQ8HtI$   A?   IL$(AƄ$   A$    t,I$   HtI9$   sAƄ$    ff.     L8I$   H{XDtAAD$H.fD  DH=IH  IG AGtAD$XAGAǄ$  AD$T    t!    u    tAD$Jf        AD$L  H  H AǄ$       I$   H  AƄ$   HE    HSpH{@LLp1H7  Lx LpM/AGI IRL5y I   IAJLbxAOPEBEGTPAWXA>   IhLp;AWTIGh    Lpt'AwP0  LLpq@LpIGhHuLLpAE LpS LxSHL   0M@ HK@KHH@ HtHx HtLHSHIA9rMfD  1DH= 菠A? AL$PAT$XD1ED$TH=B eH  H@AƄ$    I$   5    HX   H5  PLpLhH`HX   H5 LpLh    H`       Hɸ   HP  DhHELpHfDhA> Lp[IJ'fD  LH HLpwLpL5Yy AEzXA> @  IJDDHLp/LpA}H{xDDLLpAZf.     H{@KLd M  HpLhII$   H4H贛HuLsHLhA9rHCpA   LpH0  ;    ƃ   ƃ   LpI  fA  M  AJARLLpA   KL5y LpAh     HCxMeL`E}H@H   HhAEfPHEHHpH7fA} L`   ALHM|I$HXPHPL`HEH   H;   H;X   Lx MtHI   Ht<I܀x4 uL`L+ D,HtHP Hcp4HHI9Up  @,uHH;Xu@ ff.     HPLHHpLhyLh# Hp`HHhHt	HE9I;]rfD  DH= 1GKH    IA9_fD  I|$ VHA[&fD  KHCL @ QH  H    Ef     fA  4    AEEeh     IzH   LpGLpAMH=w AUI1ArXMBQLpsD  ARArLpH{xh:Lp   H  L   HIArXM[-H  LpLI   N5AE LpfD  A> H=/ 1Lp詚LpD  AwH=M 1LpLpI   H>  DkeA> uI   HH= 19XDH= 1H`H`LȩLpHIGh@AGPIzH   ELpDDIH= 1IJ趙LpHcy H, 101hAfD  EbEr      Ex|sHtuVA9H{@ABAKHD;xt.  BE1Hk(HAH(D9  D;xuH@ HtxL tp\@`Vw@\   H{xDLp臻LpA9H{xDDDLpnFL5y LpASHƃ    UHpH{@E1MKHt Ht*FL HIgSHA9sH{@KHt HuIA9rMLpH@L!H{ u:H5
{ H=;H8蟆{ H8u{ @   @   HcHп
   HHH=  ~H=      zM   P   4BI   HH!LpH9 H'y 101\fLpL5ny A9QIk()JHk(HHT(H(H9)D;xuAx LpH( mff.     UHAVAUATSH dH%(   HEHy 8 utP     H0  {L        u5HEdH+%(     H HH[A\A]A^]    KHHE    E1uYfD  1HUdH+%(   |  H [A\A]A^]fD  Iǅ   HIHuLKHA9sHC@KH4Ln MuIA9rD  KHCL #E1fD  HC@KT HH;   Lb EM:  A|$H ~   A|$L tA|$\tn    ueHny 8   A$    tI$   H9  f     I|$ vrH@t4uH y 8       KHIA9@U HQ8HtHy I$   8   IL$(AƄ$   A$    t.I$   Ht!I9$   sAƄ$     ff.     LȏI$   H{XDen  AD$HQDHHUхIH|  HUHB BtAD$XBAǄ$  AD$T    t          AD$L  RH  H AǄ$       I$   HtyAƄ$   ! 1DH= 臓Hy 8 2AL$PAT$XD1ED$TH=4 WfDH= 1?KHJ    H  H@AƄ$    I$           AD$J
I|$ &?KDH=o 1HM輒HM{qf.     UHAWAVAUATSH   dH%(   HE1fW  I  HPIHk  Hǀ      H  HH(聄LH=Aǅt[H(蟇I  PI  PL菗HEdH+%(     H   D[A\A]A^A_]    IF@HH -AǅuL8  A}  \  AoE A   AoEA  AoE A   AoE0A0  AoE@A@  AoEPAP  AoE`A`  IEpIp  Ae  @  H0  I^pIFxAD$AFhID$A   ID$fA   ID$ A   ID$(I   I|$0 A   ID$8I`  ID$@I  ID$HA   H׾y I|$P A   I|$X A   8 tLL=Hy Ml$f.     IHtHyy IM    H81^IHHy IL9uEL$fA    M$   O,M9sI? H5<y A   > 
  M`  IvpM  A   @  A     H(  HH9c  AfD  H H9t
  @(B  A   9HuLH#H)  E1@ ID$`Ih  ID$hIp  ID$pAx  ID$xA|  I$   I  HZy 8 tKL-^Gy M|$`MM(D  IUPHt Hy I   H81LOGy IIM9uEL$fA I$   A  Hy 8 a  Ly I$   H 1   M$   I8EL$O,fA JHy M$   8 ,  L_y 1LHb    I8>MtqIL$HM$M9(	  HLHvHHI  j  {   |   H(LưAǅ;  MHy 8 I  Hy L H    HH:H LE1Nf.     H=\ Y&    AuI   MA} uA} uA  AƆ   fE  AEA  fE   AƆ   E  Aǆ      1A   E1fE   H(  HH9t(f.     @*tD   EB  H H9u1A   A   A     E  H8  HxP   H(  HH9  A   fff.     H H9  9HuHpI#h  tI   H"  HvHIH0HI  H A$    H0xH08    H1HE<$HE  AE   ff.     H	y H" 1017Z   fAƆ   E   EP  1A   H(  HH9W  A   E1H H949HuML#P,  A   f.     ɚ;ɚ;;I   HA  11H5 H$Aǅ   I  WII   $Iǆ       jH ?THǃ0      4       fD  EL$M$   O,fA M$   M@ 1A   E10E   AƆ   EAǆ      IvxI   PAǅ  ~By HfHnHflfHnHyAfHnHx~ZBy fHnHy flAF~EBy flAF ~<By flAF0L0  8 4A     }  A   *  A       ʚ;1A   HHH1HHA  HHL$u%I$Haw̫HHHA  L-y A}    L1HHS㥛 HHHA  H8  D`XLhPE  M  A      Icľ   HH QI  H 
  Hy E  8 P  LHǅ    E  DM   HLGM>E1MP	  Hy M~8   HHHH9   HLE1IL  HHL`HtLH63IILLrH9sff.     ILLrH9r@Hy H9=
 H 101U    AUHH褍I  HH0tsH0Hǀ8:tEHI  fAD  H	y H 1017UrfHH fff.     H1H0英IA$   M  M  Mup  fIGH   IM;otcrIGHuIGH0   :DHtmHfLhHL8Hp H@p(HHH ZH0;rH0Hǀ8,H    AD  IGHdE   E Hy Hx    H81 Hy H;
 H 101SE1HWy H 101SH9y H 101gSH HAeDHLA   tA  "  A   tA    A   U  A   tqL-Fy A} 	  IFpH(  HH9t%@(   H8   IVpH H(  H9uA(  H<   ,BI  H  A  A   C  fAn,  fpfAֆ   C  A     AƆ      A   L(  Me M9`	  A        M$$M9B	  A9D$uA$   tH01   HHǅ4   ID$(A      % H  HHA    u	$HHID$0LHPXAT$8%p  	ЉXjLHHA   Y  A   tI LHA   tI   Hx   LHA      Hǅ8   I0  A8  u(A   1A   HHH1HHHHLgy LH@1H+ H    A3|PHHH8Ly 	  HAƆx  LHfHnHfInHflA  A      Hǅ8    I0  A8  u(A   1A   HHH1HHHHLy LH@1Hn H    A3OHHH7L?y   HAƆ  LHfHnHfInHflA  IHǅ@   LHA     I   ǅ0   LHA     A   t  A
   tAD$  A    
  A	     MnpI(  L L9  H      ff.     M$$I9p  A|$; yI$    tA0     _
 fA0  IFxH  HX8H     H5 HGC     H5 H+'     H5 H    u   A|$  1A4  M8  I(  )H H91LHH= x~Hy 8 INIH= 1M~LLM*I     ILLiI9sff.     ILLiI9r_AiA~AA   Ad  Ap  @TL-y A} ^  A   H(  HH9t  ff.     @;\H H9uH3
 Hp Hy 1A01(LfAn,  fpfAֆ   IFpH(  HH9t(@)   H8     IVpH H(  H9uA   H@H<   Q;I  HIFpH(  HH95  A   H H9   9Hu@8 uA      f.     H H9SvA   A  uA  uA  A   HH@  x  x  A      H@  H9@    H Hj  A~M tAƆ   A    HNy H    01yJL(  Ml$M9u  fD  MmM9  LH5 HuM   M&Hy1
 H" % H  ]AT$1H  HELy II   H fo H 1A3LH8IHHH1LAy   HAƆ  LHfHnHfInIHflA  LHH=y AEq1AE fA        HCk4LH= 1yA  A}  ZH= 1yA  @Hjy Hc    01HDH5/
 H=t 1xyH,y H͸ 101ZHjA   ALy L1HJ H"    Hǅ8    A3
HHHHT0Ly   AƆ  ~HA  IU I9t$H   HtHH;0  HI9uHLEy L1H{ Hn    Hǅ8   A3VGHHH/Ly    AƆ  ~HA  IU I9t$H   HtHH;0  HI9uHLHL! A3H-
 11H FDLe ˉL 뼉Ls AƆ  LHH[    Hy LHT M  Hǅ8   01&FHHHp.  HI   IU I9t$H   HtHH;0E  HI9uHLHHϬ H Hǅ8      L@HVy L01EHHH-LuVM(  IU I9tH   Ht	L; 5  HI9uHL@A   tAD$uEL*L Hy H,
 H% 101DDSHy LHH~ H    LHǅ8   01DHHH,L  M   IU I9$  H   Ht	L;   HI9u  1I   L7 Hءy LH
    LHH' Hǅ8   0M1CHLH.,:  ~HAP  Me M9uM$$M9I$   HtHH90uI$(   tI$(  B3H= LI$(  Hy LH` H- LH   Hǅ8   0M1
CHLHX+L uh~HA@  Me M9t&I$   HtHH;0  M$$M9uHA
   L AH;y H)
 1H 01bBH(   tH(  H 2HH=8 HKHH(  .L" 8H(   tH(  H1HH= HeKHH(  AƆ0   HLD H(   tH(  HE1HH= HJHH(  HLHHC H! Hǅ8      L@Hƞy L01@HHH@)L  M  IU H   Ht	L; i  HI9uHLHH H Hǅ8      L@H0y L01`@HHH(L   M  IU H   Ht	L; /  HI9uHLHH# H Hǅ8      L@Hy L01?HHH(Lu3M  IU H   HtL; t9HI9uHL bLw PH(   tH(  H/HH=N HHHH(  H(   tH(  H.HH= HtHHH(  I$(   tI$(  .H=Υ =HI$(  H(   tH(  HS.HH=x HGHH(  yH(   tH(  H	.HH=6 HGHH(  UL
 H(   tH(  H-HH=ߤ HSGHH(  UHHNdH%(   HEH0  9   HUdH+%(   u ff.     UHAVAUATS1HdL$%(   LeL0  AD$Hu$@@ sID$@HJD     A;\$HsID$@L,J| HuHA;\$HrHEdH+%(   uHI|$@[A\A]A^]72fUHATSH   H$ HXH 	   NXdL$%(   LeIvHPj DNDF   XH 1HI|$ptÅuHEdH+%(   u,He[A\]@ Hٙy HP 101<~ ff.     UHAWAVAUATSH   H$ H  L'I$   dL<%(   L}IHHt I$P  E1HJI$P  H9     H@,IT$xM/Hp  L@HM  I94        HCA~GfHHHHǅp   ~@  C$ǅ	   CTflXoCDC<f֍hf   fA$    uZHI|$pH@HϕAŅ   H@#HEdH+%(      HĨ  D[A\A]A^A_]HH@1I$H  I$8  Hf衃AŅs@       HH8AH8Hp  fD  Hy DHO 10193BfUHAWAVIAUATS1HdH%(   HMȋOHu.   A    uA} uI}    ANHH9sxIV@HL$M;$$tMl$ AMuX   (IH   L0XHf
 AE$IEAD$Ml$ uAE$AE$AD$AE eD  1HUdH+%(   uNH[A\A]A^A_]1L覎IEHEHPXI~XD:uAE' ff.     UHATSH   H$ HXH9 dL%(   LMAj IP   HAPAк   TI|$pH 1HHuHEdH+%(   u*He[A\]@ Hy 112H" 7VfD  U   HAWAVAUATSHxHudH%(   HE1   wHHLgW Hxx   HECHMHHA@HHEM}  A}I   M}(HM      X        Mup4  M  M}h0   	  I   MLM  LxAILLhTD  Ht9AET  IU AE<        u_DA#ETtHL  HK>H)HvyHHCHtIU H  AET  AE<        tLCHAUTAu$j j jHxH@`HEHPEM<H}HH a    LLx1LUuH}L赋UHHC%  H@XHuHH}UUHEdH+%(     He؉[A\A]A^A_]    ;vHEH@C    8H} -Mt#    u    A}I fIE`s$H}HPH@ LhN    Ht-CT  H;C<        uYLH  IK>L)HI$ID$HtH;H  CT  C<        tMD$I$STs$j j jIE`HPDK<H}H r HzxAU HpH}tH   LUHuHHpLhA   LHELph   HpUIM0Hc)PH}  (A}0/IU AETHHrxHp  H  H9HsH9A}TAETc   fH}I} AET    AE<              @ HBpH@  x#   p1L`IE(IH~  H    A}I  I}H;}HOIu1II)H9LCI9  HG(LmIHhLLxIHpf.     HL9  MI<LI)LuO4'LmHpLxHhLMupL)IuhHI    4  HxS HpHxrHpHHE   L]HxLhHA   LLx#~UHxHK0HcMudH}{0H;CTI$HOxHp  H  H9rIL$H9d{TZCTc   N     H}H;CT    C<        K Ss$M$gH;    1H讆IHmH    uC        H    C    M}Mu(o LLxs    AUAM Au$LIU  fD  5Hx^HHpHu={HuIU HpH;p  :HJxHsHp  HFHHpHMzHMIU HpHp   LmLxMHpHhJ    HHxHMzHMH;HxH;p  ^HWxIL$Hp  HHHxHULzHUH;HxHp  MeD  UHAWAVAUATSH(O`dH%(   HE1HE       IID  AE AF`HE    t{IFXL;`rq IV@I~XIHHLh BHuLxKuHUDI~X0yff.     HEdH+%(   u1H([A\A]A^A_]1@ HUDI~XEE0Mkff.     UHAVAUATSH dH%(   HEH	y 8 uNP   @  H0  HzII1HGHvJ{L uYHuAE    tV1HUdH+%(     H [A\A]A^]@ H   D
Hƀ{L tCL HHu[Huȅt뭐AEt    tHEdH+%(      H LH[A\A]A^]&fD  SH_HC@HAuH HАHHt;r tH(H9u1/ HUuHuHHUyAE H y H	 101N,@ ff.     UHH dH%(   HEH`y 8 u;H0      u+P   tQL u4HEdH+%(   uCH1HUdH+%(   u%D  GL H}H}yӸD  UHAWAVAUATSH(dH%(   H]H0              H@  IIx#   D`x       1DQHH  H{@LELL6s  H:y 8 a  H}1DcXHJ  HEH=W LpLx(+Hy 1Hz LH5 H;'M   HE    @ ff.     IA   .   MMFLeMH;HM1H H53 r'fAM H;1IH H5 O'M9uLmIw"H;H]X 1IH5 $'IuH;I   AGH L ILDMGH| 1H5 &HUMHUI)H}1HUdH+%(   ujH([A\A]A^A_]1Mf     HxWAI@       H	 H5 1[&xfD  } UHAWAVAUATS1H(L0  dL,%(   LmII~XGM0  ID$@HEAD$Hu&BfD  S_IT$@HJD     A;\$HsIT$@L<J| HuHA;\$HrH}S#Iǅ0      HEdH+%(   uH(L[A\A]A^A_]^ ff.     UHAWAVAUATSH   dH%(   HE1f7Z  HX  I~IHM  H@@HH Ow,t5L]^HEdH+%(   $  ,Hĸ   [A\A]A^A_]fI$0  Mep~y IExCAEhHCA   HCfA   HC A   HC(I   HH{0 fHnA   HH{8 flfHnH_Aƅ    AE fHn~=y H.y A   flAE ~%y flAE0M$0  8 tXL5y HL=y fff.     HI   1I>IHHy L9uHy 8 I$8  8 >  o A   o@A   o@ A   o@0A   o@@A   o@PA  o@`A  H@pI(  A    tA4  "  A       I$(  HH9z  A   HH9d  9Ju   t1   H0HHǅ4   HB(J8%K p  H  HHHB0HPX%	ȉX>IA    uHH L9q!  A}M IAƅ   <f     A4    Hy LHLH fo    0I1LH8$LH0LAƅ   HHfInAƅ0  fHnflA8  yHHIH      Hy H"    01$    pI   I$8  @A   ,H IǄ$0      Hvy H
 H  101#D,ǅ,ǅ,f.         UHHNdH%(   HEH0  9   HUdH+%(   u ff.     UHAWAVAUATE1SHdL,%(   LmL0  AEHuWqf.     H{PI3HCP    H{82uH{ H{hHHYIE@JD     E;eHsIE@O4J\ HuIE;eHrHEdH+%(   uHI}@[A\A]A^A_]3 ff.     UHAUIATSHH^ H   dL$%(   LeIs4uH{PuDAD$C0HtGGC,A|$t!HEdH+%(   uQH[A\A]]    GC4׉C0HCP    S0tI   GbHCPHHt@ UHAWAVAUATSH8OHdH%(   HE1GL A  HEL-v I1HEff.     H9  IV@HL$M9$$tI|$  ufp   )EIHF     IG H  Hn  M7A_]Mo,AG4HEL}A~{ t/A      9GH@H<   IGhH   H}!IG8H   AD$M|$ tAG4A( u!A(   t
fD  yFI8juANHH9f     1HUdH+%(   u`H8[A\A]A^A_]IG8uI~XHP@IWH"uAG(ANHfD  I Ih~LFV
f.     UHHdH%(   HE1G ufPw5GPHM
 HcH> H  H#H      H	HHEdH+%(   *  fD  H  H#H@    H	Hf     H  H#H@    H	H랐H  H#H@    H	H{fD  H  H#H@     H	HSfD  H H#H@   :   H	H+fD  H  H#H@    H	HfD  H  H#H      H	HfD  H H#H      H	HfD  H  !H#H@    H	HfD  H !H#H@     H	HcfD  H  H#H@    H	H;fD  H  H#H@     H	HfD  H  !H#H@    H	HfD  H !H#H@     H	HaUHHWPdH%(   HE1f	wH 
 HcH>    z Z  fHEdH+%(   p   G   H !H#H@     H	H    G    H  H#H@     H	H    G    H H#H       H	H\@ G ~   H  H#H@    H	H,@ G uRH  H#H@    H	H G u*H  H#H@    H	H     H  H#H      H	HfD  Hxy 1H͍ 01z    }     UHAWI   AVAUATISHx  HxHW8Lw dL,%(   LmL/HHp_MD$8HpA(   m  ~xI@(I;  HID$,HI   HAD$4IpAHHHǃ   E	ȈEA	   fAF   fAFHB0BPLLH)B HAD$`ID$hHHA}j t8M0  1HLkL1LfAFHbAąuI   HLtAąunHHEdH+%(   utHx  D[A\A]A^A_]fD  Ix@I   HhLp5HhLpH[Hvy DH 101qJf.     UHH HAWAVIAUATISHX  HHvy H5 H;dH%(   HE1M%  HHǅ    HHHHHLMA   .   ADOE[H;1HHs| H5 ,IcHM$ ff.     AM H;1IH H5 M9uA&@ H;HE 1AH5 AuE~YHH   t]HHH)HEdH+%(   uRHX  [A\A]A^A_]ÐH;H{ H5 1HfD  H;HHK H5 #\ff.     UHSH8dL%(   LEL0  A)   t%1HUdH+%(   .  H]f.     H@  IIx#    Xx     1   LULMLE=LELMHLUH   Ix@LLEL!kHWuy 8 YH}1҉CHCHEH=u HpHX(HuHuH H}f1f     H}HxLEHuDLMLE؉LUI@  j fff.     UHAVAUIATSHdL$%(   LeI)     HCIEHS(IU H   HTAD$I$It$Mt$HHA@H<jHHt[ID$Hx( uI$H   H@  x# u'p1H2BHC(Hu-fD  HxC MtLKTIE    1HUdH+%(   u&H[A\A]A^]D  MtLTI\$    UHHdH%(   HE1G ufPw5GPHa	 HcH> H  H#H      H	HHEdH+%(     fD  H !H#H@     H	Hf     H  H#H@     H	H랐H H#H       H	H{fD  H  H#H@    H	HSfD  H  H#H@    H	H+fD  H  H#H@    H	HfD  H !H#H@     H	Hf     UHAWAVAUATE1SHH(H}dL,%(   LmL0  I}X1L0  IG@HEAGHuPj H{PIHCP    H{8dH{ H{hHHIO@JD     E;gHsIO@O4J\ HuIE;gHrH}HEHǀ0      I  M  ~(LMdff.     HHdI9uL'HHEdH+%(   uH(L[A\A]A^A_]Hfff.     UHAWAVAUATISHh  L8Lw Hx   dL,%(   LmL/HMD$8HxA(   _  I@(I;  HID$,HI   HAD$4IpAPHHǃ   E	ЈEA	   fAF   fAFIG0HHHAG HAD$`ID$hHHA}j t8M0  1HLL1LfAFHNYAąuI   HLjAąuzH.HEdH+%(   |   Hh  D[A\A]A^A_]fD  Ix@I   HpLx+HpLxHi     Hly DH 101$ef.     UHAWI   AVAUATISHx  HxHW8Lw dL,%(   LmL/HHpoMD$8HpA(   U  ~xI@(I;  HID$,HI   HAD$4IpAHHHǃ   E	ȈEA	   fAF   fAFHBHBPLLH)B HA}j t8M0  1HLL1LfAFHWAąuI   HLhAąuuHHEdH+%(   u{Hx  D[A\A]A^A_]D  Ix@I   HhLp)HhLpHs     Hjy DH 101jjf.     UHAWAVAUATISHXHudL<%(   L}L?MI   u"I   Hp  H  I  M,$Mt$8A(  ff.     uvINXHtlAt$4I   t(HUdH+%(     HX[A\A]A^A_]fD  AD$LHIE@H4AƇ  Mt$8M,$ID$XHID$XI;     ID$X    AD$`    AF5  AD$`   AF  E      A  E  A  	    E A  A	    E   E E E	 E E E E E	 E E AD$`IF@t7]EMUDMDE]]uAD$`D]IFDU}]]   tA|$`MAE؋UDAFtAt$`AFDDQ  AT$`AFHE    1۩         u%    ҃E	ЈEI  "  I  Hj  IcL$4=  I  1HuJ  f.     HH93  HH9JuHBLx 1%  Iff.     :  H;rA9rAEt9uHHx HuI~TEI$%   IF}w6H     U    o  ʀU@ ff.     U ut UĨ0t" H  H#E   H	HEH]A8   tIF  *  A9   tIF2  P  A:   tIF Y  w  A}{   A;   uA>     AL$`I$It$8IT$hAɋ   A9E  H~8 AAEE	ȹ   HzH    9GHH@H   HD
    HH)1HEt{EtMHF(HBHF0HB     HBF  B"  ȐB"F  J   1ɿ   1EtHN8H@HLHH
HBA;   tAF  A<   tAFR  A=   t$AF tI  HLA>     Mt$8LQ  Mt$8   IF@IT$HH9sID$HHA(  uH]H;2  M,$C IEI$% E<   <  IFH H#UH       H	HUIp  LA(  M,$    "z X  I   .Hf   1H7,fA   tHHf.     EL<1IvHH    @ I        HH!H	H H#UH	HE<  UIF L      u	AL$`AF@ E        A   E  A   	     E  A  A	    E     E  E  E	  E E E E E	 E E  r H  HtTIct$4  L  Mu$9 ff.     ff.     HL9tHH9quA2   UUfD  H#E   H	HE I  HLI@  HLnIFIH  HLCIP  HLi)IFIX  HLBI`  HL#IFIh  HLoEE1Ix  HL UIFH          U       mHHaA2WUU5H H#EH@     H	HE<HB        H       HH	H H#uH	HU  fD    B"R  ȠB"FJ HF@tJ$HF   tJ F      9BJ  	ȹ   B    H$_y Ht    01O   H%   H=     H%   H=               H@H H#EH     H	HE<uHH҃H H!   
      HKHp  H H#EH     H	HE<HD   'H H#EH     H	HE<H   H҃$H H"H H#uH	HU @B"	 ujB"B"Hk]y Hr 101z    H18`B""      B"u B"ǹ    UHAWAVAUATSH(O`dH%(   HE1  HGXHIHE0D  HuL      AD$( S`   HCXL9h    H}HIHC@L<Mg IC`tHCXH@HHEI9sLm   uLHEHuLuHUH}DE MHEdH+%(   u@H([A\A]A^A_] HUH}Dh xǋS`2    1w    UHAVSH0dH%(   HEH]y 8 u2P     H0  HzIHGH   (   u&1HUdH+%(     H0[A^]     yL v  A8uʋyHHZHE    E@t1A  fff.     Hq@HH4HF Ht>D;@0u8HX@HHUDEHMHEH}HuHMDEHUyHH9r:HuH   HUHMHMLEHHUHyL    (   #HHULEHM5HM؀   LEHUA A@ EPE@DJXA  HEdH+%(   3  H   DDDH0[A^]@ 1HHULEHuHMf:HMLEHUȀ(   OHuH LA@HI4HF HtCHX@HHUHMHECH}HuHMHUȋyHH9rfD  H9rHXy Hn 101"HXy Hh 1DMDEȋ01DUDMDEDUHMYf     UHAVAUATSHdH%(   HEHYy 8 uMP      L0  A|$L    A$(   uIHL*uA$      1HUdH+%(      H[A\A]A^]D  AT$HHE    1ۅu. IE@LHHuLAT$H9sIL$@HH4Ln MuH9ru@ H=ym `    L8F<ff.     UHAWAVAUATSH   H HdH%(   HE1Gf  IH_LpH   Lo(HG   LgIcHLDHH H  E~  McJ    I)MdI1LLHAULcIDH(LHI(fLLHM+IIGL9("  LHuI    LL(LIM9uH .H    IH3  Mx@L(LGL(Hǅ     A  HI   H0  I   H @A   H HR  H@ A   H HHDI  I  I  Et<f  H1"@ HRHtH9uHH9<  HHHu1A  H   H(  HH9t(f.     ff.     B(H!H9uHA(  Hh  fA   Hp  A  Hx  I  ff   v:H  I  H  I     A      A!  ~xx HqfHnH%flfHnHA fHnH~Ex flA@ ~<x flA@0L0  H5Uy 8 L  I    H HH(HPЅ	  Lfx L,    H L(MILL-Sy Lf    I$I   1I} II聮L9uLH L(J\(t~L1L%x L DkAt<(L51Sy E1fD  JK   1I>IE9r(EJ;rLL HSy 8 tE1#  fD  HH8  Hv  8 m  o A@ho@A@xo@ A   o@0A   o@@A   A   o@PA   o@`A   H@pI     H=Ch 1L(AwL(LL(HL(Hǀ0      L`*~'H HcHL4ƐHHdL9uH #*HEdH+%(     H   D[A\A]A^A_]   HV  Lx@H(LBL(A9L)]Ixh1L(L(Aǀ       Iǀ      HL(  II9  A   HI9  9BuL01   LHǅ4   HB(A(     %	 H  I0  J8HHHHB0p  L(HPX%	ȉXI   H@L(HAx~   Ax   A      Ax{ t$A     HH   Hx   Axm ~  A      A    u  Axk   Aƀ>  HHLL(Hǅ8   L(AiI  M&M9u'  f.     ff.     M$$M9  I$   HtH;uI$(   tI$(  L(L(H= L(hL(I$(     @ ǅ    A      Ltx   %H H:  Lx@L?D  H HHǅ     H H   H0  IH   G   HGHǆ         1Hǆ     Hǆ         A.Hǅ     AHwMy Hd    L(01L(HLL(;L(AAxM Aƀ)  %	 H  H@AI   NH=c 1L(L(-Aƀ8  HHLGL(AI@  M&M9t%fD  I$   Ht	H;&  M$$M9uHHSLLH(LAH(IH  M&M9tI$   Ht	H;X  M$$M9uH3Aƀ;  HHLL(oL(AIp  M&M9tI$   Ht	H;"  M$$M9uHAƀ<  HHLL(L(AIx  M&M9tI$   Ht	H;  M$$M9uH  HLx@H(L<L(AML#H #DHǅ     uAƀ9  HHLL(3L(AIP  M&M9t!fI$   Ht	H;c  M$$M9uHHSLLH(LA~H(IX  M&M9tI$   Ht	H;  M$$M9uH.uAƀ:  HHLL(RL(A I`  M&M9tI$   Ht	H;  M$$M9uHHSLLH(LAH(Ih  M&M9tI$   Ht	H;7  M$$M9uH]HHy HS_ 101(AAƀ=  HHLL(\L(A
I  M&M9tI$   Ht	H;  M$$M9uH!HlHy H_    L(01L(I$(   tI$(  L(EL(H=S L(L(I$(  I$(   tI$(  L(L(H=S L(L(I$(  YI$(   tI$(  L(L(H=PS L(QL(I$(  dI$(   tI$(  L(^L(H="S L(L(I$(  I$(   tI$(  L(L(H=R L(L(I$(  I$(   tI$(  L(L(H= L(jL(I$(  I$(   tI$(  L(wL(H= L(L(I$(  I$(   tI$(  L(*L(H=R L(L(I$(  I$(   tI$(  L(L(H=Q L(L(I$(  H  WIHAf.     UHAUIATISHH   LPLXt&)`)p)U)])e)m)u)}dH%(   H(uqHEI4$I} IHLH0H   H ǅ    ǅ0   ixI4$HcIM H9r5D1 uH(dH+%(   u#H   [A\A]]     HIM I)$ ff.     UHHdH%(   HE1Hx HHUdH+%(   u負fUfHHdH%(   HEH Hl  х     qe  πB	  C  ʃd  H              I   A   HAA   HAEML9  I/  A    A	HHDHEdH+%(   E  ɉ        HcH9s < uH  H9r@ HN  W     -      WLGA   	Ѻ   f            HDBL9            OHH f    D     HcH9rs    B!)fff.        fD         AHADXHDBL9<\fD  LfD  HO1    O!    O 	   D  I	     A	    A	         P@         P    +UD  UHAWAVAUATISHhHuDoHUH_?dH%(   HE10HuHME    HEHuHMA<$	wSA$H0	 HcH>f.     LEHUHu1H}Hk E@ ff.     t8HHUHuIAD$E    H@ H}PLE1YEZYHUdH+%(     He[A\A]A^A_]fLEHUHuIH}HN 1Ew    Mt$   HuLmHM.HUHuLIE1HxHN HuE    AD$HuHx<  <"    HyN L{  fD  AHHuIكH}HUPLEH+N 1C^E_f     AD$Ml$HuHME    <f  <  rL%   H	  H=   	  1AHEHUHEHuH1HL HxHpA?
  A
  AH[K LHK HxLDHpH}1H [E AD$MD$HuHME    <n    <  HUHu1H}HL EnfD  HEMl$HuHUHMHuHHE HE1E    HxHpA  Ay  AG  A  A  A   A@  AŀM  A     A     A     A   y  A   D  A     A     A     A   p  A    ;  A  @   A      A      A   ukE <LHuH}I H?M!H"K RLH=RHZx LHU1[AZEA[    HxHpHJ 1H}(p HxHpHI 1H} ? HxHpHI 1H}
 HxHpHlI 1H} HxHpH>I 1H} HxHpHI 1H}`k HxHpHH 1H}86 HxHpHH 1H} HxHpHfH 1H} HxHpH9H 1H} HxHpHH 1H}b HxHpHG 1H}p- HxHpHG 1H}H HxHpHgG 1H}  HxHpH6G 1H} HxHpHG 1H}\ HxHpHF 1H}* HxHpHF 1H} HxHpHgF 1H}X HxHpH3F 1H}0 HxHpHF 1H}b HxHpHE 1H}0 HG L1fLHUHuMH8I?H}HcG PLH>PH I!1|AXEAYHiG L1_f.     HEHUHEHuH1HM HxHp!A  A  A  AHwF It"HqF ItI(HbF @ HxHp1H}E    AHF! HϢ HEHEHUHEHuH1HxHpjL%   H   L%   H wH	 HcH>HfE H0XHqE A%GL
H  L%   H@BHxH}1HJE HpAH2E     HD HD HD HD HD @ A  A  AHfD ~fD  HxHpHD 1H}(  HxHpHD 1H}  HxHpHWD 1H}LuL}HEHC LLHHE1LxLpLA    1HH}LLAHVC sA2  AHDC HEH:C HHEHUHu12LLH}HHHUHuA   	1AHB A:H}HUHu1HB E;HxHpHB 1H}BHxHpHB 1H}HxHpHTB 1H}aHxHpHKB 1H}<HxHpH
B 1H}LpL}HXB 1HxLLLA    1HHxLLAHA AuAHB 譏HxHpHtA 1H}}f.     UHSHdH%(   HE1H? t>H   qHtHHHSHPHUdH+%(   uH]f     1    UHHdH%(   HE1HEdH+%(   uێff.     UHAVAUL-	 ATSHHH0dH%(   HE1HG    HGH    H)JhHHCXHspYHEHuHChHspH   ~yH{hHSx$HShHsp   HHH)ƋCxHShHsp   HuL5L1y f   1H:3 )EA6)EjHsH}hHUdH+%(   t  H0[A\A]A^]     A6H2    1Hsp:{|H   H	g  IcD L>fD  HHHShHspvfS`-HS$@  @  @  CHׁ   KHp  H     t
  Ct	    K   @K    HSXS @      y  H H!Ѓ  qz HH:   1H	HOG qz Hr/y 01HspHS@   :HK/y H ? 101yH H!Hy#I       HH=L	HHHFH=ʼ	 HcH>C  DtCtCH   H   H> C3C     EHс   CH   vvHtH07  CH H       H       H!H	HHHDHCHHC0HC(HC8HCPHtkHupCy " D   ECPCE    EC*CCHс   H   Hу
Htc%   Hс   H@     ECHׁ   HtFH׃
HtH u@C  D      ECit   Ct   CF  @ C9L̀C)UHHdH%(   HE1HEdH+%(   u1fff.     UHHdH%(   HE1HEdH+%(   u1͈fff.     UHHdH%(   HE1HEdH+%(   u菈@ ff.     UHHNdH%(   HEH0  9HXHUdH+%(   uAUHHdH%(   HEH0  HǇ0      HUdH+%(   u	H-     UHAWAVAUATSH(H@  dL$%(   LeIx# B  DxLnMcLgHH   I$@  x  tMLHDOA9uZHC,y 8 ufH1HUdH+%(     H([A\A]A^A_]f1   DHuff.     HH3! D  H= E1Y1L=*y H5c I? H	 AD$1H
B AE!McLqM:E1D  DDHt6HI)IfD  HxHu{HuA    I?HS0 H5Î ;ff.     UHATSHdH%(   HE1f   H`   IH   I$0  L`H~Jx HPPSP@HSPXHfHnHflfHnH& fHn~x fl@ ~x fl@0I$0  H?*y 8 u1HUdH+%(   u?H[A\]H)y HK   H3 H81߃D  빸D  UHAVI.   AUATSHdL,%(   LmI貥L%(y 1H7 H5E I<$HcIMtI<$HA) 1H5 HTL9uۻ
   f.     I<$1HZ H5 'uHEdH+%(   u(I<$HL1[Hx H5 A\A]A^]&fD  UHAWIAVAUATSH(udH%(   HE1  HcD4.   M,訤L%'y 1H6 H5; I<$I\qAM I<$1IH6( H5 OL9uٻ
   D  I<$1HZ H5 'uDHI<$EL APH H6 PDH> H5 Hx %  LcPH|6 PD
PHq6 PD	PH_? PDPHP6 PDPHA6 PDP1pDmHpAHDLHA~L9u   HUdH+%(      He[A\A]A^A_]fH5 v?sH5 L-sH}5 LsHv5 L	sHo5 LsHD L    gfD  UHHdH%(   HE1HEdH+%(   u证@ ff.     UHHdH%(   HE1HEdH+%(   u1mfff.     UHHdH%(   HE1~uH~  HUdH+%(   u ff.     UHAUATSH   H$ H  (   LNdH%(   HE1IHPIՋVEUfnfpH	  HLPHNFHǅ   DfօXAÃA@   @tH~ uf~6  E   A         f   fH5Z#y @   ǅ	   6ARASRRH; QH-	 P1eIE H0HPHHxhv HPA跭   Eu]HUdH+%(      He[A\A]]    A         6 Et;A         fD  H"y H*; 1011 A      EuA         UHATIH5n2 SH   dH%(   H]Ht#1HUdH+%(   u~HĠ   [A\]fD  LH   Ht]HPHth%   = @  t(H!y 1LH: 01H   観   s7~Hp!y LH>: 101f     UHATSH   H$ H   fo~ dL%(   LMA)Efor HEI   )EfHP)EEAPAк   Pj I|$hH 1HP4ÅuHEdH+%(   u,He[A\]@ H y H : 101>} ff.     UHAWE1AVAUATSH(H0  dL,%(   LmIHxXHE4I0  HC@HECHtt ff.     H{@KL4    LLg Mt7I|$ Ht蕁ID$     I|$(Ht}ID$(    H{@LH IбD;{HrH}ѼHEIǅ0      H   覱HEdH+%(   uH}H([A\A]A^A_]P|ff.     UHAWAVAUATSHH  H@  L0  dL4%(   LuIx#    DhA$    uRH@  x  uq   1DHH  HI|$@LLÅuHA y 8 uL1HEdH+%(   (  He؉[A\A]A^A_]fD  1@ Hx?A^    H1DHtHHx(LpHH= LAL=y L1H7 H5C I?A  E$   M  Hf?     D  ff  ffE_  DHLMIHN$(HJ0L;  Hf) HHHHH$H%)0H!Aу	HAH#		HH 	ш#f; 3  HSHL[H(LSHʉIHуIHI?EɃ)AS @AREDAAP@ARPWAQR1H6 APA   TVH5i QDLA虻J+uK.B+HPHH f	Ef c  EI?DMH6 H5 L)DH 13L    HH)H9,I   HE    H% IHJD0o oH )@o@)`oH0)PfDfH~)pffFH@)MAHЉA@HHAH)MA	HxfA	Љ@fEfHDEHH@uf}HHMHU)Ef  +  DE@MH\5Dƃ@HA̃TAEAAAEHAAQAINATAFSRHk5 P1WLVH5P 菹H@fD  HfE1Hy HH3 10S1HXZfD  H$}    Hy LH3 101̻f.     Hyy H24 101觻D  HYy INHf4 101胻fAw?fA
   fA2wUfA0   @   A    ffDZAlfwjp       ff0Afw@AJ       fDfAU   A    fDfDD*uf.     UHAWAVAUATSHhdH%(   HEHy 8   P   	  L0  HLR	  u
F  M  AL   L}LxL}HxIGXHEAw`  IGXH9X   IW@H}IHHLp oAO`HڅtIGXH@HH9HGHMnMq  HUDeI}(   IH@hH@  x#   p1LIE(H  IuIEpIuhIN Hs     H覒H  Hy HN3 113IuhIUff.     HMM`   EFVHŤ	 RH+3 1AuPиI~H LOhLɁ  uHWpf: B  IF    IU fInLIEflHBHAE mHEAHUuH}诺D  E1HEdH+%(   y  HeD[A\A]A^A_]DB\EH(  'HtHx  uA    tDCXE;GHsI@DHHLh MIM(E1H  C\H      p!HRH`y Hi1 1A   01舷. IuhIUH1y l@       ffE  ffE   _  L  H  IHL)I%  Hk}I	Mk}H	I'  L9e  M  ]ELuHLmIIMHcHUL'tBUEHIǸ  L  H)H9r7M9  HUKt= LuLuLmI~    I   H IL9~  It    l  H  H  HHH)I%  Hk}I	Mk}H	I4  L9e'LuIFHHpIFH)Hht@ HO031HQ0 1I   讵I~HGh    IFfInLflH@p    IF    IU IEHBHAE Y  uH}L衷/f     A     I6AFHUHHF@1H<
IFIHHUHx(DeHUH  HpHxpHphIN H  Hy HLuLm   II~ Hx'I   f=  f=
  f=2  f=0^  @       fEfu    AOHAGL 
MoX1MLm'H}LDaAOHH9Y  IW@HL$M;$$tAI|$  u0   rIH6  L8X@A    tXI   HEH}H  AH!    1LU   IB H  H}LULUAD$MT$ $AB IN HHp   荌HzHy H5- 113\D  f-f   Ap   A    fD]fDe    LuLm   I~ f.     Ms     A0D  H}H5Ɯ LULUIB     f-fwNAJ       fD}fEHEdH+%(   Y  JsXLMЋRHe[A\A]A^A_]pIF    IU fInLIEflHBHAE QAU   A    fDEfDUwH    1 LUHNy HMH{+ 1LU01tAƇ    LU   AHy H* 1A01/I   H}HtVH&    1W AE~H}H5E IE(I}( tJH}IM(HyDkDH    1ALeA+HSy HMH * 1A   01wD  UHAWAVAUATSH(dH%(   HE1fq  I   IџHH`  I8  H   8    x ux t`Hy H* 1A01H   赟H}HEdH+%(      H(D[A\A]A^A_]     x ux ux ux ux ux xx nx dx Zx Px Fx <x 2f@      H{@Aą)I0  LkhLHCpAFC|   CxHUH5 E    Hx81訬~x     fDEf   HfHnH9flfHnHfHnHy ~x flC ~x flC0I0  8 }LH{@nuJ{M cƃ   W@ HH=H{@Aą     H{@EԨDeIǅ0      AA5hf.     f.     UHHdH%(   HE1HEdH+%(   u1gfff.     UHAUATSHdL$%(   LeL0  AD$Ht 1ID$@HHH| A;\$HrHEdH+%(   uHI|$@[A\A]]ߧjgf.     UHH   H$ H  fdH%(   HE1IHHW HIHIH	  HHpHpDHǅ   ƅHLH	     LL(ǅ   H)0[uHEdH+%(   u H	y H&    01sf UHAVAUATSHH H@  L0  dL4%(   LuIx#   DhH
y 8   H@  x       1DNHH  I|$@LELH=AąE  H}1DH+  HEH=ȃ HHHX(HMHMHL-B	y H5m HI} H1HIIH% !KvH   L4\D  K3H   CDKH0A0Hy DCAHHVy AHPH5% 1xXZL9tX.   跅I} 1DH H5Lm 苧H{ xHKHH5o 1   H0A0L9uH}@kE1HEdH+%(   uCHeD[A\A]A^]fD  1pHxgA!    cD A6dfD  UHAWAVAUATSHL0  dL,%(   LmII~X;M0  AD$Ht)1f     ID$@HHH| )A;\$HrI|$@(Iǅ0      HEdH+%(   uHL[A\A]A^A_]c UHAWAVAUATSH8dH%(   HEH'y 8 >  P     HJH$  L0  AL G  A`  IHM     IGXLuL9p   IW@MEHHHX IGXHHEAO`tIGXL@IM9MGML3   C\H9C8   H{H<  HG(Hs8HHC(HPHHC@HH]  HV0HS8HPHS@HOHS0HtWHH+KH  fH*HKPH`  fH*^Y[y f/Sx   H,H9sHK0HL9  I   IvpDCloHC@H"HCHsHHA@H<HHtUHCH@HωC\Hy(   LHaHHRHHC@CXH;A`HC8    CX    HHy H"    01讦C  Aw` ff.     1HUdH+%(     H8[A\A]A^A_]@ \0w I       H,L1f     IȃfII	I*XfIȃfII	I*XUfHH@pH@  x# uTpH1HMkHMHA(H{H{Hs8H}HC@u    HxHMHMH0.H.H0H0Hs8HC@AwHAGL s  HUE1I$ff.     ff.     IA9  IW@KL,M9m tI}  uڿp   萔HH  L8DpIE AEDutCl{  tAwHH;CHsHHG@H<IHtHCH@C\I}(   LLIeHHRHHC@CXI;E`   HC8    1CX    HF(Hx uH8H0H{HH@HS8HCPHF(HHC(HV`HC    SXHC@    HPHtRHHH+CH   fH*HCPH   fH*^t Yu f/   H,HS0uIXC HS87HH@pH@  x# uXp1LIE(HHsHfHH	H*XHHUHJHx1҉HfHH	H*X\H,H?*HJ,H y H 101赢&]fD  UHAWAVAUATSH   dH%(   HE1f  I   IHH  H@@HH(Aąt8HHEdH+%(   i  H   D[A\A]A^A_]     I0  Lsp~-x HCxAEL=.y ChIE   HfHnH^flfHnH~x HC0flC I0  A? .  M(  M} M9uQ  M?M9D  I(     H5 |uH01   HH HLHǅ8	   IG(AW:HHZ	ЈZH      H0tH LHH+uKHH   M} M9tI   Ht	H;   M?M9uH(LLH(A]Iǆ0      %D  Hx IM   H/	 H81gYA?      Hx H
    01l    I(   tI(  H=Y vI(  7AA/Zf.     D  UHAWAVAUATSHXdH%(   HU1f   HOHwOHx : u{Hx H 101BHUdH+%(   ?  HX[A\A]A^A_] Hx HR 1133   1HO 1뤐H_HMLL%Ex H}ML5x H]Hx @ IM I   1H;IIWM9u݋UHMHEMLH(  MA   I00000000E    KL   DyM94  H@@@@@@@@I9  HPPPPPPPPI9  E   q   H}E9L]ON,D}LDx ME1Aff.     KLK1   H;VLIL
x E9}ՋED}qL]LHcA9~TM$H  MHEMAuL]ME H;D   HU1AIzVE9uًML]A+EEu9uHcL    MKLDyM9E~ʍq   HUE9L]ON$E1AHx KLH;L]Jؾ   1UL]ICA9}wEAKABtL]HcA9YHUMEuL]L<MGH;D   H 1AIUE9u֋uL]B&+EfD  IQEq
   HUE9L]ON$D}E1MLx A    KLK1   H;ULILx E9}ՋED}QL]LHcA9pM$H< UHEMAԉML]ME H;D   HU1AITE9uًML]A+EE   A   MHEf.     H00000000H;LI9tH@@@@@@@@I9  H|
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TH00000000I9HENt( L-}x Me8tW    IIU   1H;IISM9u݃EE9E"E	HcEM$L,    4@ L-yx Me IIU   1H;IIgSM9u݃EE9EEHcEM$L,    H;LHt    1 SfTfD  UHAWAVAUIATSH(dH%(   HE1H   KHEHH   L5 @ ,   H3IHt  L=x L@ IwIHt+HSuIcWIU IU Mt\I\$    Hx HH 101H}EEHUdH+%(   u(H([A\A]A^A_]HwIE    H   DSfff.     UHHdH%(   HM1Ʌu)HHwH> u/HUdH+%(   u@H@ 1HUdH+%(   u"Hx H 101<RUHHdH%(   HE1MtA     HEdH+%(   u	H{ lRff.     UHHdH%(   HE1HEdH+%(   u1-Rf.      UHAWAVAUATSH8H}MdH%(   HE1   H? 3  H>   }    PIH   HܠHEH  IŐff.     ,   LIHt  A} ?uA}    1E1Ms.1Ҿ>   D軋HtHLˏHLHDAA@uHH  HEH	Ma  MnpIH;HEL 1HEdH+%(   9  H8[A\A]A^A_]H#x       E1H= L0LoAt61Ҿ>   1IHt I   L1H(% HUG  O   MtaHLuRM@t'Is1Ҿ>   薊IHuŃE1@uL
   H}8MH L1HF    N대} H LH H== HE11룻OD  UHHdH%(   HE1HEdH+%(   uH1JeOD  UHHdH%(   HE1HEdH+%(   uH   "OfUHAWAVAUATSHdL,%(   LmIH[  HH5 IOHH   @ ff.     ۝HH  =   HE1Ht  L`Iu H   MIwIH   HuMtn
   1LHIGHn1H5: pNHHdLL1HUdH+%(      H[A\A]A^A_]     IG    @ Hx 1HH	 01DHLHx H 101Hx HƸ 101rMfUHSHdH%(   H]HH=< 'HtB1HǺ
   H=< fHt
   1HfCf; tfu1HھT     <t  P HEdH+%(   uH]D  f; tf{ tL@ UHHSHXdH%(   H]H1yV111HUo)EoCe)EoC fE)EoC,ETHEdH+%(   uH]5Lf.     f.     f.     f.     f.      UHHH?H6dH%(   HE1HH9t)HUdH+%(   u!fHEdH+%(   uHHK ff.     UHAVSHHdL4%(   LuIH5 tHEdH+%(   u8H1[A^]@ HEdH+%(   uHLHH=0z [A^]\KfUfHAWAVAULmATIH=^SH8dH%(   H]H1)EHE    LH=m: H$HMHCH9s3H4RH{HHH9HBH3HqCH  HCHM11HtOfD  ff.     ff.     ff.     HKHsHyH{H}HH΍BHH;ErH}oH{Hs   HCx HE    >H薽H{ u_L50x 1LHl    I>oHH{ Y  L1蚎HEdH+%(     H8H[A\A]A^A_]D  E1E1f.     HC1A   LA      J4HɻHSHJEwMHHsI9rH{H!   gHKHsHL H  DA      @ ff.     AVIH9   HH9:tA5R.z       H    LHX臍IL   L-x Hv 1I} #G.z fI}    H *   Z^_ F1k-z d1uxfL=qx 1LLEH    I?FH{ =}3I?A   H: H@    1pFE1fff.     HCI?   HU J1IH:FE9rHx <      H=  HPfI>H H 1   E   A   i1H    H EERHCI?   H H1HE,Ff.     UHHdH%(   HE1Ht<      t$G$HG(HUdH+%(   uf.     ! uր" u1kFff.     UHHdH%(   HE1  tHG@HHUdH+%(   ufD  1F    UHAVSH   H$ H /   dH%(   H]HHt*HHUdH+%(      He[A^]fD     H胗toځIHtH   L   SL    LH1蟒H   L&ZYbLZ@ Iٹ      1L    HLBDff.     UHH dH%(   HE1>Wv8H~PHt/HFP    H}fH}HEdH+%(   uD  HEdH+%(   uDfUHH0dH%(   HE1H       HI     H8H? u<   f   A HA8H   HUdH+%(      f.        fuHqPHHtXH8HtHLEHMHuoHMLEHHy8tHuHH6HMLEHy8bfD  1rHHyHLEHuHMhKxHuHMLEHH8HyHy8KCff.     UHH dH%(   HE1E        IH   HwPH> t^H~1Ht1HO Ht(Hv LEHMH}HUH蹖LEHEA HEdH+%(   uAH     HW8HHLEHu{JHuLEy@ ff.     1gB    UHAWAVAUATSHh|dH%(   HE1    LwPHIII> U  IFHt<L; r7L;`s1LkHIp  H   HK8I9L)I98:  fH}QHC8I>HMLA   WHMHt:LKHLy4 taHq|AJ< E)H9Hy LLBLfAH}HEdH+%(      HhD[A\A]A^A_]fD  HQH+    LHC8HKHM;p  L(Hp  HHψ{HpHp{Hp  @ HW8HHLHABD  INLKHLy4 uHQH+Hq|AJ< E)H9Hy LLBLeAI@f     UHH0dH%(   HE1    HOhID	EtHEdH+%(     H@ HwPH> "  HVX   HFH  H=x H@ 	    Hk  Hy(g  H:  @@y1xy4HA8Hg  HB-HAHBHAHz Hy HF H9   AD+JDIB*A0HF fA@ HAAHI@8IPHLHp  H   I9H A2H>HtHMHuc>HMHuHAHF*A@ H   H HW8HHHMDMLEHuFHuLEDMHMff.     1mf     H~H++BAfD  HHMHuLMHUHUHMHuLMHp  @ fHA    1A    Af.     HA(    1A1 N=     UHAWAVAUATSH   dH%(   HE1   HH  LgPIIM<$Ml  L0LMIE8LLL   d8H8ǅpX   H@H  Hx HF z	   Hk  HUg  H:  UPUHPHEHj  oAHA-HxfH~EfH~H9  )tA*MmHEfHUIp  E EH   I9ƋX   HpEH9HHGsz    WvS@   LHCP1HUdH+%(   b  HĨ   [A\A]A^A_] H   H L蘏fD  HpH{HHHLHLHH)H)HdfD  1H+)fLHIp  @ ǅt    f1Hǅx    E@ HE    11E B pLfL     HW8HHLBxM<$Ms@ ff.     fD  pDDq:fD  UHH@dH%(   HE1  k  HG`I    W  HOpDE   LOXI9   IQX   IAH  H5x H@ ~	   Hk  Hq(g  H:  @@q1pq4HA8H  HB-HAHBHAHr Hq IA H9   AD+RDQB*A0IA fA@ HAAHI@8IPHHpHp  H   H9A2HEdH+%(   E  HD  IP8IxHHMDULMLEHu7Ax#HuLELMDUH>HMH    1@ H   H IqH)++BAfD  HHMHuHUHUHMHuHp  (@ HwPH>H8IP8LHMDULELM4xHMDULELM    fHA    1A    Af.     HA(    1A1 '(8     UHAVI   AUA   ATSHdL$%(   LeI8xH1  LHHH  Dk$   HLc(cMHCH   H5+ H'H{H5J HCxH{H5C H   H{H5 H   H{H5( H   βH   Ht9Hkx H5kx HxHHH  H  H)   H)HHEdH+%(   u@HH[A\A]A^]Hx H1Hl 01>|HlH޲16D  UHH dH%(   HE1Ht0HGxHwHHt G!HHHUHUB! D  1HUdH+%(   u86     UHSHdH%(   HE1HtOH   HHtG"HHC" H{SH>kHEdH+%(   u$HH]fHEdH+%(   uH]5fD  UHAUATL SHH  HEdL$%(   LeDeHw0HGXH@HGhHHW8HO@LGHLOPLo`HGpH2   oZǅ    HHrǅ@    ǅ    HoR oJ0HBPoB@8oJ`HXBXHoBp`   (dH   hHE   xE   fEB\EH   HEH   HEH   H   H0HuHpH    HEHEH   1HtHHHE1HUA(uUHψEJC H{HHELEt+   C  HUdH+%(   uGHĸ  [A\A]]@    HyH80H8    HE    U~3 ff.     UHAWAVSH   H$ H0L> dH%(   HE1VI   HIIϺ      X   HHZYH   H5 HHzHtmH5 HfHt-HHtHہIHHtǁIH\P   HUdH+%(   u,He[A^A_]D  H5< HH{1W2    UHAWAVAUATSH(dL,%(   LmIz<HP  I ff.     L(IH   I#HE    HE    AtHvItH=$ uHUHMLIw-KtHMIWHF    H5 HHD1 Hx  [H}蚭H}葭LyIHQfff.     HEdH+%(   u~H(L[A\A]A^A_]e HEHE#fD  HH H5 1   kH5 H}Hu^HEdH+%(   uH([A\A]A^A_]0 ff.     UHATSH   H$ HdH<%(   H}H= vH=}N lHt>IHL} 1         Hl}HHH1QUHH dH%(   HE1HtdHcHH   t<IHPHtHIuHpx u_1uHLLLU߻LULHUdH+%(   uv    1@ HLL1LU褻LUL Hix HD uLL1LUvLUELIL1LUYLU/ ff.     UHH   H$ H   dH%(   HE1   HtBLHIHH    1HXHXH`uHUdH+%(   u.     UHHdH%(   HE1(Ht#HcHH   HUdH+%(   u
@ 1/.@ ff.     UHHdH<%(   H}1 H    u$HHuHEdH+%(   uH-UHSHdH%(   H]1fH   `$HHuHEdH+%(   uH]|-ff.     UHHdH%(   HEH  Ht3H   Ht'@1҅tH9GHEdH+%(   uɉ@ 1-@ ff.     UHAWAVIAUATIHSH(HudH%(   HE1HE    HXHvnHEH   HLHH訤HHUE1H5 HH   fD  E1LDHxHtHHtHx A   AIIuHUH5* 1莃HHuH}=Et)1HUdH+%(   u<H([A\A]A^A_]H}Hx HMH 101Bq+@ ff.     UHAWAVAUATSHdH%(   H]1f.     H    u6H"HHu1HUdH+%(   uqH[A\A]A^A_]fD  IHtHE1E1DH負IHx tHPHLA
E AE A	AAuEu*@ ff.     UHAWAVAUL- ATS1H   L5x dL$%(   LeILL=( L@8 IMEMtdHx 0oH E1ɹ   I>AWH P   1(XZuHEdH+%(      He[A\A]A^A_] H E11I    H@   LL8L8MAMt5Hx 
~A      VfD  E1ɹ   C)L+ E11-D  UHAWAVIAUATSHH(  HHHdH%(   HE11Hǅ    HXjD$@AIcHHjH>  I    HIE1 I    uvL~IHuH t3跗HHI  L%HHHH15  f     HE1DL۝HHx A<    ;    HLDLHt~HSHLtgHcHH5" LH4HLlIw0HI   HOl5HL)HII1HH    DLH=Hx 1H12H lHYHUdH+%(   uiH(  [A\A]A^A_]H!HH    mH
x H 1H: 011l&yfff.     UHFHAWAVAUATSH8dH%(   H]HHE H  H   HHȃHEHȃyHEI<  E1E1L-_x %D  KT 1<HIIIt>It8AtHuHMtHuI or J<3D L)@ ;    H} u0H} uNDHUdH+%(      H8[A\A]A^A_]@ HuJ<3H 1L)藱HIH} tHuJ<3H 1L)rHI HE    A   HE    D  HuML)H H1-LcO48:Hu$D  UHAWAVAUATSH(dL$%(   LeIE    E  H   HFIH   HE   HH!ÍJf?   R     ۅtztuE1E1L=]x 10@ HuKK<,1L)RHIŋEIt2It,tHMtLI!~A or AD 멐   L ~AN/A    HUdH+%(   m  H([A\A]A^A_]Ðhi  EtfEÀ5H%   HLELE1H(8   HcH6\x HH   L1oHIHuHMK<41HD L)MDRD  Emissۀq     HuHMK<,1HWD L)D II|$HRemote  A   I$HH(8<H+H1[x H HL1詮LEHIM)K<4@ H L1}HI	>" ff.     UHAWAVAUATISH8HUdH%(   HEHF HEHS     ÈEHx  E1E1L=+Zx (f     K1HIIHt?It9tHuLMt{HuIA or K<4AD L)@ HEHtd   HtRt(LM   Hu1H [HIHt&M   HuLE1H 10HIA<$ t,DHUdH+%(      H8[A\A]A^A_]    L)uHuH< L1߬HI        fD  zHuIA or K<4AD L)0f        E1Ht+HuE1    LITzHuK<4A or AD L) UHHdH%(   HE1Ht0   u%tAHEdH+%(   uPH8 1 HEdH+%(   u/H 1«fHEdH+%(   uHl 1颫mfff.     UHHH0dH%(   HE1 HtI   AAt9u51ɨuOH 1HM=EHUdH+%(   uaf     HEdH+%(   uGH[ 1f1H, HuH}DE}H}HuvHcH)H{D  UHAVIH	 AUIATISHdH%(   HE1艪LHcHH)LMtA   -  H 1WLH 1HcH)L;LLHcL:LH 1HcH)LLLHcH)L֣LHa 1HcH)LکLLHcH)L3LH5 1HcH)L訩LLHcH)LmLH	 1HcH)LvLLHcH)I<;HUdH+%(      H[A\A]A^]D  u<u udtHH. 1D  H 1D  Hb 1D  H 1ҨvD  H# 1躨^UHAVSHD      D      dH%(   H]H^XDD   Eكf%?A   AAA )  A8AAE҃vGAtGpAvGt   G H,  [  f=vG,tG0tG<tG@   A~  OLQWLWTDJDOTA  GXG`@tAd  GHGXG`     E       A   AT  A   ~G\Gd~91 ffG\    E1E1D  >  GH=     f=vG   tGH~H 
  H~   1HUdH+%(     H[A^]@ 7E.(@ GlAZ  W(W(`  GdtG4f.     ҃c=@A  GLGTA    G$G ~/ ~GPffGPyD  GhAt6_(SW(uEuJID  Gl(    _$SW$uEu&    GlW$E    GDA@GHf     W$ GH    Ef.     @bOLWTQG8	G|GxGrfUHHdH%(   HEFGFGFGFGFGFGFGF G F$G$F(G(F,G,F0G0F4G4F8G8F<G<F@G@FDGDFHGHFLGLFPGPFTGTFXGXF\G\F`G`FdGdFhGhFlGlFpGpFtGtFxGxF|G|HEdH+%(   u UHHdH%(   HE1HH	 HcH>f     H   @t   @t1@@    HUdH+%(   4   H   tո   t1
t1       t   t1t   u1vfD  H!@wCHG	 @HcH>fD  H!
@wHH	 @HcH>    fD     fD     fD     fD     fD     fD  1@ UHHdH%(   HE1HyG	 HcH>f       Hp tHTa Hj HD    HUdH+%(          H. tHa H HD      HF	 HcH>@   HF	 HcH>@ h  HF	 HcH>@ H D@ H@ 4@ H $@ H+ @ H @ H @ H4 @ H	 @ H @ H @ H @ H @ H @ H t@ H d@ H{ T@ Hh D@ Hy_ H HD&fD  Hd @ HM OH8_  UHHdH%(   HE1Ht+        J   9t
BvHEdH+%(   uHff.     UHH dH%(   HE1Ht,   HD  r9r   9tuHEdH+%(   u; uHHMHMHy@HEdH+%(   u
H}j5D  UHHdH<%(   H}   -GHt
ǀ      HUdH+%(   u     UHSH(dH%(   H]HHt2HHHE(HEHs@Hx@(H   HEH   HUdH+%(   uH]mf.      UIк   HSHHdL%(   LMIH<;HcȍCH9LHUdH+%(   uH]fD  UHSHH   HXL`Lht#)p)M)U)])e)m)u)}dH%(   H81HEIHH(L    HH@ǅ    ǅ$0   H0d:HcȍCH9LH8dH+%(   uH]+ff.     UHATISHH   HXL`Lht#)p)M)U)])e)m)u)}dH%(   H81HEH LH(HH@ǅ    ǅ$0   H0{iA9~%AT$    )HHH<KIc DHcAT$L9MH8dH+%(   uH   [A\] UHATSH dH%(   H]H6@tYI@ sH@tCLHt
   HuLHEqHMHH9MuHcCHqff.     HHUdH+%(   u	H [A\]|ff.     UHHD% dH%(   HE1    f/v^K   f/wHEdH+%(   u!^f/v^G    M   ff.     UHHdH%(   HEHHxOfH*H莆$ f/s H,HUdH+%(   u7f.     \H,H?HfHH	H*X`UHAB   HHdH%(   HE1EBKMGE H  v9H
   H v!HѸ   HHvH   HDDHEdH+%(   uH  1f.     fUHAWAVI/   AUIATSHH8dL<%(   L}I輔H    %   HI蠔H    HuHHuHEwfHH9]  Hu
   I|$wHU:   fU^a" f/  Pf*Yf/v  %~" f/d  f*Yf/N  f/D  M  fI*}LL)   fH*YMU5"XEUf/! MsdH,YIf("XEf/! sXH,I9t	H9sHIF1HUdH+%(      H8[A\A]A^A_]D  \@! H,H?@ \(! H,H?@ HfHH	H*X"f.     LLfHH	H*XUf.     Ga
U
   HAUATSH8dL$%(   LeIHuAHuH.t   1.t3Hi ʚ;H1I$HUdH+%(     H8[A\A]]D  HHHuHucH	   HuH}κ	   P\E HHEcH}H	tV	   )HroH00000000H0HtHHHH)r1I00000000ƃL19rf
   HuBHU:  ut 0tǹ00  fL 0000D0000fD  UHATSH dL%(   LEE1Ht> u'HEdH+%(   Q  H D[A\]     HHWIH+  ,   H蜐HH   f  A<$ uwz    LmHCHHt	H9   E1L%^x He    1DEA4$MHKA4$1HQ    hMDE(    HLHEIHU؅n( fA<$ aHLNL軃HAXD  HzHsLANA UHAWAVAUATISHHXuHMLEdH%(   HUHc1H/   L"HA  -   LH   %   LIH  L`LcKT,I9  HcVHIH  LLH~/1  LHHMHUfC.CD. LEAxHEdH+%(     HXD[A\A]A^A_] L8UIH\  H4`HcLI9;  IHUM1Lmh   A>    L%x M1H+    A4$0KA4$MGH!    1KAMuIL;u;  9]*  ,   L蕍IHyA>   LgTIH[  -   H^IHt  I%   LBHA    HELHHE胧LE_LH9E  %   LH    HuLDLE^IL9e  LE^ E谀Eff/  f/   M^ f/h  f/ Z  HEH]  fH*mHEH+E!  fH*YMUXEUf/3 M   L,Yf(XEf/	    H,H9EM'M   1I9L5Цx H!A6H)H IG1HA6MGH    1HAMD  LmG      \x L,I?Ff     \X H,H?Kf     HfHH	H*XfHHf҃H	H*XUD  LQHEH  HIE1\HM4M9  LMIw   HMHLHU   L5x LD1H    HA6GA6LCD   1MuAH }GM9   D9e~1,   LIHmHMHUHLuH}}Aaf     L-٤x LD1H    Au FAu LCDH    1AFH}}@ H}o}D  L%qx M1H    LmA4$FA4$MGH    Dc1pFL} LmL}    LLm|E1 A]D  UHAUATSH(dL,%(   LmIHtbH}Ȼ   ZH}L$f,   膈HtHxL9rHcA] HEdH+%(   u#H(   [A\A]]k@            UHHdH%(   HE1HtH;7r+HWH9H!HUdH+%(   u        @ UHHHdH%(   HMH	Ht1HUdH+%(   ugf.     t>~3HcHH7ff.     H;rHwHtH9sHH9u   HEdH+%(   u	HUUHAWIAVAUATI%   SHXHUHMLEdH%(   H]D߆HuLI萞H&  IM     AL1Ʉ      ff.     <,Hu  LMXMH  MDqE  MMLmHELeIĉ]1۾,   L(Hx_aI*f.     Hax  <  I<,@  AE uLL蜐\  ID9  M    I$(  H
  HuH
     ML
  uLLx/   thtdHcLHL     ff.     ff.     ff.     I$(  H
  HI$(  H
  HPHH9uҋEH}HEHEL(1HUdH+%(   ^  HX[A\A]A^A_]     AE  IfLmL]LxHx H 101ALxLe]LmL]L߉u\xEx   AHcLLmL]HLe]LL]ގL]MgQIEHIT@ ff.     HxH98;HH9uL߉MwMYHLMHEuuL]:Hx H 101@D@ UHHdH%(   HE1HEdH+%(   u	E1     UHHdH%(   HE1HEdH+%(   uUHSZ/D HIHH	HHHHi ʚ;H)HS㥛 HHL1HIH/ 鱆|ff.     UHHdH%(   HE1HEdH+%(   u@HSZ/D HIHH	HHHi ʚ;HHrw H)1IL6UHAWAVAUATIHPSH   dL,%(   LmI1,   H`HPZLHtuH`HJ     H}:HtTYHMLLDXH' L1I-舅HEdH+%(   u HĈ   [A\A]A^A_]D  $f.     f.     f.     fD  UHAVAUATSHdL$%(   LeI  ALM <?tdHLLp@t'<\uAF  IFHLp@u HEdH+%(     HL[A\A]A^]fH9 H}D1   HcЅy0Hu H}  rу!  HH)HH  ,  1H    ff.     oHH9uЃA9   A)IDQAvNN   ILcȍHFE9}jHcDHAHD9~VMcɍHFEH9~CHcDHAHD9~/McɍHFEH9~HcɃAH9~
HA@H\39sF@ Ho1D  HH9uH\3LGIE11fff.     UHa    HHHx dH%(   HMHH81+   豄UHHdH%(   HE1HtBHGG      HG@ HGG(   HGG8    HF(HtHVHH;8tHEdH+%(   u1D  WV4HHRHV@H   H H HFF0f     UHHdH%(   HEHHUdH+%(   u ff.     UHHdH%(   HEHG(Ht&HWHHt@,HUdH+%(   uD  1/@ ff.     UHHdH%(   HEHG(Ht&HWHHt@0HUdH+%(   uD  1@ ff.     UHHdH%(   HEHGHUdH+%(   ufff.     UHHdH%(   HEHGHUdH+%(   uMfff.     UHHdH%(   HEG8HUdH+%(   u ff.     UHHdH%(   HEH   HUdH+%(   uf.     UHHdH%(   HE1H>HEdH+%(   uff.     UHHdH%(   HEHF(Ht!HVHHtx,HEdH+%(   uH=_ ,ff.     UHHdH%(   HEHF(Ht!HVHHtx0HEdH+%(   uH=^ !ff.     UHHdH%(   HE1H~HEdH+%(   uff.     UHHdH%(   HE1H~HEdH+%(   uKff.     UHHdH%(   HEG|HUdH+%(   u ff.     UHHdH%(   HE1~|HEdH+%(   uff.     UHHdH%(   HEH   HUdH+%(   uf.     UHHdH%(   HE1H   HEdH+%(   uH     UHHdH%(   HE1HEdH+%(   u2ff.     UHAWAVI@   AUATAHSHdL,%(   LmIH   D`A|$LHHcHCH   C    诊LHD8I^WL3C4   IE(Ht
IUH;tHC,   1MtLZdCC$E<$HEdH+%(   uHH[A\A]A^A_]H=<\ WfUHATSHdH%(   H]1H   I1   
I$H   HxH     fHǀ       HH)   HHI$H@(    H@@    H@H    H@T    H@`    @@1HUdH+%(   u5H[A\]    S       fD  ;     ff.     UHAVAUATISHH@H   dL,%(   LmE1nH   H@   }HH   HxH     Hǀ       HH)   LHLH3knHfH@(    H@@    H@H    H@T    H@`    @@1HUdH+%(   u8HĠ   [A\A]A^] +       fD      fD  UHHdH%(   HE1HEdH+%(   uff.     UHH dH%(   HUHH(HtwHB HHH9JsHEdH+%(      @ HHHUH4    HMpHUHB(HteHr HMfDD D0HJ D  Hֿ   HU7|HUHB(Htfo H     BaH=&Y UHAWAVAUIATSHHF(dH%(   H]HH   HSL$M   蕆HLD8IDSM,$AD$4   HC(Ht
HSL9$t	ID$,   1MtL<`%AD$$E>HC(HSHH@C4HH@HC@H   HHHS C0HEdH+%(   uRH[A\A]A^A_]HHSHC( @  H{L$HpI$HC(HݒHSL$x     UIHH0H~(dH%(   HUHH4  HB HJHpH9   H    HL9   Ht<HB@J0HJHB(HHJ@HHHJHB(HȋJ4HHz(HBHLHB(HJHH@B4HH@HB@H   H	H	HJ BP   B0HEdH+%(      fHHHUH4    LEHMnHUHB(H   Hr fHMLEDD D0Hz(HJ HuTM8    Hֿ   LEHU;yHULEHHB(t*H     fo Hz(BHtHJH=V @ UHSH8dH%(   HE1H   H|>    |>    H}Hֿ@   HHMHUxLEHMHtqfInfHnHflL@fnHuH@     @(   H@4     fpf@HEHEHUdH+%(   uH]f1H=XV ff.     UHAVAUATISHcHDkMcHLdL4%(   LuIwHX  Hǅ   Kڃ  L)HH    1HAoHH9u؃9   )rvI4H4t{HcAP9~dHcAP9~RHcAP9~@HcAP9~.HcAP9~Hc҃A9~
HA1LLfy[Hta@    HUdH+%(   uFH[A\A]A^]Ð1 ff.     AHH9u11H=T hH=F W    UHSH(dH%(   H]HH}
AH}HUdH+%(   uHH]- UHH0dH%(   HE1H   HH~(HHY  HF LFLHJ4    M9   H7H<7 t[HB@r0@0HrHB(HHr@HpHrHB(Hr4pHrHz(H    HtHH8 tHFHBHHHB(HJHH@B4HH@HB@H   H	H	HJ BP   B0HEdH+%(      L@HUJ4    HMLE#iHUHB(H   Hr LEfHMDD D0HBLB H4    Hz(HH9f.        HMHuNtHUHMHHB(tfo H     1BH=:Q %D  UHHdH%(   HE1HEdH+%(   u`ff.     UHH dH%(   HU1HtpHV(HHtHNHH;:t'P u.HUdH+%(   uRH     H    P tHxHEHuHEHu    HEdH+%(   uf.     UHH dH%(   HUHW(H   HOHH<HtuHHEwHEHP(HHH    HPHtHHPHH(Ht;HH
Ht/IH4H
HIHH@H   HHHP@P   P0HEdH+%(   u@ ff.     UHSHdH%(   H]HH(Hu:   D  HHvHSHC(HH    TH{(H   HCHHuHkHC(    H{`HWHC`    HfHC(    HHC@    HCH    HCT    CCHEdH+%(   uH]1Ð1'    UHHdH%(   HE1HEdH+%(   uɸ   f.     UHAWAVAUATSHXdL<%(   L}IH   vHuyAOLAGH   uAGL   I   I   IG(H  IWHHH  RAW4HHRIW@I   H H IGAG0LHj	 MR&L-	 LT	 HELI	 L	 L5{	 L	 ID$@MHEHAG0H}IAwLHcCff.     A$A<	fA<@ tAwhMgpHcAS9t?fff.     ff.     AFf]~HcA<:HCHcfA;SuIDU ICHf }HELeMA@uID$pHEIcD$hA@HuH}HI$   H)AT$8AT$0H It$@N  H5	 HcH>L&IWIG( @  IHLdHIWIG(HH4HCx H IGIG(HHx H IGI HuHI+$   EAD$0ID$(IT$H4HA8u9AIT$AD$4HHIT$ID$(H@8   IT$ID$(H4HHyIcT$4ID$@L<H}I$   L}I9{
  L}ITH9]
  Dy4H)Ep  H*	  L}H}H}L}LAt$LID$@uH9E	  HEHEHE   AHcufA<p tHEAt$hID$psHAC;UuJ  fD  ff.     ff.     HcH	 HcsHE<CD9p  HP	 p]@Ѹ|   ff.     HUdH+%(   F	  HX[A\A]A^A_]MHELD`+[LHH,DH]DHHOH  AD$0HuID$pHEIcD$hHE1k/   a*   W+   M-   C>   9<   /&   %^   ,   )   (   %   IL$Ict$8   I$   wL	 L	 L2	 Lk	 rHUMHr    
      u  k  a	  WLYLHtHuH(f.a     LxYH5	 H0  L\YLI!Iu1L     H~  A$  ADE HEHuEH9uHcEHE      DxE  Hg  HUH)HHR  .  D1HoHuHH9uA   D)HMHHHMHv)EHEHMH<H<EtoHEHH}BA9~RGFBA9~CGFBA9~4GFBA9~%GFBA9~GFA9~GFIT$ID$(H4Hy8T  qD)   ID$@LD}IfI|$H)IǍ6FIAD$HcHUP]HUHID$t9HzHr(McLHB@L$At$+}#AL$ uID$    H=RF D  D}LIԉ    9OЋA$  IcD}ME1HEHEIU	ULL	 LE	 L	 L	   
%  IIw(AH4H}Hv>HH}D9uMD}  AD$4    H@    AT$4E    u*E  IT$ID$(E   H@8   AT$4IL$(It$AH4H;A  AD$4HHuHR ID$(IT$HIcD$4HRD IT$ID$(HHHzI$     H}P  HcEAT$LMHHEID$@H9   H}AHE    AIcfA<p tHEEghIGpsHACD9u`tfff.     ff.     ff.     ff.     ff.     HcH6	 HcsHE$CD9tH	 p]@ADE HEAHEH9E/DHELeHE        HyHMLHcEJZHML	 L	 LQ		 L	 HAIT$ID$(HHz .  EBAD$4IL$IT$(DH4UapHE     HcEHEIcHEQfD  I|$gLO	 LH	 L	 L	   HE8       I|$5IT$ID$(   IL$H}HHUHx]L	 L	 AD$4LN	 L	 aIL$ID$(HȉPAD$P    LzWL	 L	 L	 L<	    AD$LI$   HIT$@(DeMD}I|$f  UL)	 L"	 L	 L	 AT$4ID}Hu1H}HE    	D1HuHH9uqH=A HcHEGHu  ~ H H}RH=A HcEH}HHA|$LHEID$@}H9   LeIA  AAHcMfA<H tHuNhL~pKHA4C;uu?Sfff.     ff.     HcH	 AHcKHA<C9tH
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  A   1  h  ?PtOhfD  H	 J4 4  ǅh    ǅh    Hmx H&l Hp*    L@01LHLPLPLHL@CD]@ H	 fopLPIAǅP   LHAD  h    HchH	 <   <  MA   Hp.M9tGHB	  <wI?IIM9t"IE <uI?IIwEM9uL;XtLaEHEdH+%(   +  H  D[A\A]A^A_]f     H0HpLL@LHbLLh@LH@ H	 D,p    Hi	 B4 PP  A   H	 0<    <   MIf.     A1tHpL@LHPLh}LhPLHL@HpCA   dǅh  HpCMIHchE1䁽h  w"D  < u	  H HAOA_~ f(fTf.	  d f.	  f/Z sff.z
  AG耽< tfTf.  H,fH,HH1H*< AOAW1]f(IOAGA_~ f(fTf.w   f.e  f/ sff.zb	  AG耽< tfTf.  ^1qAGfW I[AG耽< *  ( f(fTD f.  AOf(fT( f.  \1AO耽< '   f(fT f.b  AGf(fT f.F  X1AO AGf(fT% f(fT f.  f.   f/S sff.z  LIL@LHc[ 1LHL@LAO耽<    f(fT f.rrAGf(fT f.rZf/   f1AG耽<    f(fT f.rAOf(fT f.sI7ILL@LHA_) f(fT%E f.rAWf(fT- f.r f/7  1f/9f    f.E8 1AO AGf(fT% f(fT f.C  f.f/w sff.z  IOf(hL<1L@I7LHH(LHL@LHAO耽<    f(fT f.}AGf(fT f.aY1AOf(fT f.  f.   f/ sff.z  IOAGLILLHH@{I?sHH@LLLIG<LH(LHLH@4UH@H=H1LLLLIw   L@<LH;< %AG1A_GbIG<LH(LHLH@Cǅh    HchLA   Hcx    H  H2b A   01Hch< ?AGfA.GLL@LH    III?LH1L@LN< AG< AGf.zAOf. 1f.zAGf.f.zAGf.f.zAGf.f.   - f/ff.f/f.   fE1*Vf.   4 f/U  ff.G  A  f1f.	AOf.7f/% sff.zLI?L@LHf/% Tff.F@LI?L@LHLHf1L@Lf< AGH(I?LLH0LH@HH(LLLHH@H"f/ff.[f    f.Ef/I7I`IHaLIL@LHAGILILLHH@pIH `x Hw    LL@01LH< LHL@LI 1LHL@LLIL@LHHb_x Hv I0I   A   01Hch}f.     @ U1HHdH%(   HE1Ht5D  ff.     ff.     HHHH)HHuHEdH+%(   uHmfff.     UHHdH%(   HE1OHUdH+%(   u%D  U1H5H=+HSHdH%(   H]1`3H=HCHUdH+%(   uH]˺ff.     UHAUATSHdH%(   HE1HtsHG IE1HtCff.     IUJHt! HH{H[HuIE II9rHEdH+%(   u,HL[A\A]]3HEdH+%(   uH[A\A]]	f     U1ҹ   HH0dH%(   HE1LMLEHE    HE    >6H}E5H}5EHUdH+%(   u蓹 UHAWAVAUATSH8dL4%(   LuIHE    HE    H   IHM   	3LH2HE    H9LIBMBIF LuH   HMHQHML<Mu}D  MMtgIWI7LMLE   HH5H}A4H}4EtH72H}.21HUdH+%(   u<H8[A\A]A^A_]HEH@ HEH9E]H}1H LN ff.     UHHdH%(   HE1HEdH+%(   u	H?     UHAVAUI    ATISH0EdL4%(   LuAHE    HE    xH   EDpLLMI} LEй   H@    H 3AąuUHEHtX @CH}3H}x3HEdH+%(   u+H0D[A\A]A^]f     HH3A	f     UHHdH%(   HE1HEdH+%(   uɺ   5ƶfD  UHAVI    AUATSH dL,%(   LmIHE    HE    H   Me HLH   LcIULMLEC      HHSI>H2AąuZHcYx IM Hq    ME01H}-2H}$2HEdH+%(   u/H D[A\A]A^]D  H1H1A豵UHHdH%(   HE1Ht(Ht#H?4HUdH+%(   u@ \ff.     UHAWIAVE1AUIATSHdH%(   HEHHP HtiHHJHuQf.     H[Ht7H3HUL8 t1HUdH+%(   u*H[A\A]A^A_]@ IHP II9r   褴@ UHH H?dH%(   HE1HMHUHE    HE    3H}0H}0HEdH+%(   u=fff.     U   HSHdH4%(   Hu   WHtJ1H5H=H[,H= w"HHEdH+%(   uHH]    H/1诳@ ff.     UHAUATSHdL,%(   LmIH?HG Ht>E1HWJHt% HH{H[HuI} HG II9rHEdH+%(   uH[A\A]]+fUHAUATSHdH%(   HE1H   IH;I} HG HtIE1ff.     HWJHt% HH{H[HuI} HG II9r,HEdH+%(   u,HL[A\A]].HEdH+%(   uH[A\A]]@UHHAVI   ATSHHHZUx dL$%(   LeIHm 01zHuH{Lt)HUdH+%(   u^H[A\A^]f.     HuLSHM1HLIHuLrHuLEH}=rfUHAVAUIATISH dL4%(   LuI,  MM   AA   tRu'HOTx ALH1l    0   oHEdH+%(     H [A\A]A^]D  HTx AL   MAHQw 0    L5Sx MAL1Hv    LMA6A6L   Hk 1LMLAA   IQL<A6LMȅuLAL   Hv    HGSx L   Hk 01oLH=k    1Oȯ     UHHAVI   AUIATSHHRx dL$%(   LeIHj 01HuI|$*JÅuEHuLXQHMк   1LIBHuLHuL8CH}MtLLE۸OHEdH+%(   uH[A\A]A^]fUHHdH%(   HE1HEdH+%(   u諮ff.     UfHH*GdH%(   HE1HEdH+%(   uffD  UHATSHHH dL$%(   LeItAI$AT$1LE:&   HEH   fL%:Qx H*) L%)Qx H11Hfi A4$R A4$Hٿ   H\i    E(EHEdH+%(   uYH [A\] L%Px H11Hh A4$ HfL%Px HH	H*Xq6fD  UHAVATASHH?dH%(   H]H1H+   E1Eu'HEdH+%(      HfIn[A\A^]@ 賤IH   @   H4HtuHHH   @   H4@   H /DHL /&uL5 H(L-WfD  L5 E@ HLuL5      L5Q L5@ fD  UHAVSH dL4%(   LuI;HtRHLHdft,HE'EHEdH+%(   u%H [A^]f fD   aUHHdH%(   HE1FHt><v:AAA   tiHDF<tBH1H vH   HEdH+%(   uQD  H  vH   D  H9s#H   믐FHǈ    H   虪f     UHHP~w dH%(   HEH*f fHnH4f flfHnH2f )EfHnH0f ~Tw fHn1fl)E~Ew fl)E~=w fl)EwHcHDHUdH+%(   ufUHH   ~w dH%(   HEH\ fHnH\ flfHnH )pfHn~w H58 fHnH{e flfHnH~e )EfHnH. ~w fHnH} flfHn1)E~ww fl)E~ow fl)E~gw fl)E~_w fl)E~Ww fl)EwHcHpHUdH+%(   u蹨f     UHHdH%(   HEH@v*ҁ   t>HEdH+%(   uO@@!	HEdH+%(   u1H|      HUdH+%(   ux@ff.     UHAWAVAUATSH(oFoVoN(on8o^HovXfdH%(   HE1ofho~xfffffffofsffI~Mu)HEdH+%(   o	  H([A\A]A^A_]    IHI      H=oc 9L      H=Yc  L      H==c I   H  I   H  I   H8  I   H  M1Aff.     HHtnIDHtf  fH*Y Mv  fI*^HE/E   LHHb    HuI   H  I   H  I   H  I   H3  I   H  I   HO  I   H   I   H7Z  fH*Y	 M!  fI*^   E\EHUdH+%(   e  H(HL   [Ha A\   A]A^A_]f.     HfHH	H*XYw MLfHL	H*XxP  fH*Y< M  fI*^   EE   LHH`    Nj  fH*Yں M/  fI*^   E-E   LHH`    OM  fH*Yx M  fI*^   EE   LHH'`    芢  fH*Y M  fI*^   EiE   LHH_    (kJ  fH*Y M  fI*^   EE   LHHc_    ơ  fH*YR Md  fI*^   EE   LHH_    dG  fH*Y M  fI*^H^    LH^    I   H{  fH*Y M  fI*^H^    LHR^    赠)O  fH*YA M  fI*^H^    LH ^    c   fH*Y M   fI*^1EEE   LHH]       fH*Y MxqfI*^HY]    LHS]    趟LLfHH	H*X[HfHH	H*X#LLfHH	H*XwHfHH	H*XCLLfHH	H*XHfHH	H*XLLfHH	H*XHfHH	H*XLLfHH	H*XHfHH	H*XLLfHH	H*XHfHH	H*XLAfHL	H*XHfHH	H*XLLfHH	H*XHfHH	H*XLLfHH	H*X>HfHH	H*XLLfHH	H*XHfHH	H*XLLfHH	H*XHfHH	H*XLLLfHH	H*XHfHH	H*X
f.     UHAWE1AVAUATSH(oWoGUoO(oo8Huo_HowXfoghoxfffo   o   dH%(   HE1ffffofsfo   fH~o   ffffofsffH~H{  IH      1H    t0Hu   H L%ߓ HcLFY L1)AE1D  I   LDK|   IIuI      I      I    ^  I      I      I    9  I      I      I    t?uIcHT H}H L~X D)H HEHc17(AI    t@DuH}IcHx LDX H E)HH HEIc1'AHEdH+%(   s  H(D[A\A]A^A_]D  HL%f 1HcuLW H L   I'AI    iDHc   H})HW 5@ EDMcLeD)EHcuLH& H IHEHӑ 1'A1DmMcLeHW H LE)IH HEIc1&AI    Dm   McLeGH  HI LE)IHw HEIc1v&AI    Dm   McLeH H LE)IH  HEIc1&AI    YDm   McLeHR H LE)IH HEIc1%AI    Dm   McLeBH HD LE)IHr HEIc1q%AI    Dm   McLeH H LE)IH HEIc1%AI    ~Dm   McLeHM H LE)IH
 HEIc1$AI    5Dm   McLe=H H? LE)IHm
 HEIc1l$A/@ ff.     UHH0~Dw dH%(   HEHdT fHnHlT flfHn1)E~Mw fl)EwHcHDHUdH+%(   u誗f.     UfHAWAVAUATSHH(H   L  dL<%(   L}IHG    VxHES  E    LpE1 ff.     I~A6AI9EE9gxLcuK<vH"IH.  Awx  H}E1E11 ff.     LW11MuD   fD  H@LIt AHLHHHp L@(H LWIcHHL9s_HwIIJ4LIt IsEtLD@IMI9H uLM9X(uIp LWHHL9r ff.     AwxAHA9;H4@LHHEH2  E   L}L59x E1    IO(A6H\ 1MO MG   .HH   IO(fD  ff.     ff.     HPHtoHH;HrHPHuHPfILHAGAL:I0E9fHEHC1HUdH+%(   u\H([A\A]A^A_]fD  HPfH111H؍HEHu=xzy  t)1HEfD  輔LuEH;x 3      H=e[ H}#zy    뫐UHHdH%(   HE1HEdH+%(   u
HG    UHHdH%(   HEH@ HtH;ps%H@HuHUdH+%(   ufD  H;p r
H@@ @(֓f.     f.     fUHAVAUATSH dL,%(   LmLo   IH   A       Aƅ   1LI   H5?    H5O    MfL9Hw H5O ME HsHHtsLu{A   Iǅ       Hu	ueHiE ʚ;HEI   1HUdH+%(   umH [A\A]A^]@ Aƅ    fD  Aƅ    LH=Y 1H5x HY 101D  A   WO@ ff.     UHN HHdH%(   HEHw $ff.     ff.     HPHHt#9xuHEdH+%(   uHf.     HlN fUHAWAVAUATSHXHuHFdH%(   H]HHE    H9  HE    II1HMH     H   ff.     HH]  HHRuHJHMH   HEL8IGHEIHEHEf.     LLLAՅHE~L8IHt)L}I     L0IHt}LuI@ M7HMHEHQHMHPHLuHHEHLsH]H    H   HMHHHMHMH/IfD  M>HEH]HHEH@ ff.     HEHXHH HuHMHHYHEdH+%(     HX[A\A]A^A_]IFHEH   @ ff.     L}ff.     HLLAՅ~!IHHt-IHLLHAՅM7IHt,MI@ L3LuH]IFHtHEfD  ILuL}ff.     LuHLLAՅ~IHL{HIHѐM7IM~MHHEHNHMҎfUHATSH   dL$%(   LeIH\Rt6H`   H HZK 1IH1x 01H\L)t6H`   袻H HK 1IHh1x 01H\t6H`   \Hu HJ 1IH"1x 01YHEdH+%(   uHĠ   [A\]蹍f     UHATSH   dL$%(   LeIH\2t6H`   ˺H H:J 1IH0x 01   H\g0t6H`   耺H HI 1IHF0x 01}H\Lt6H`   7HP HI 1IH/x 014H\(t6H`   H
 H`I 1IH/x 01HEdH+%(   uHĠ   [A\]N ff.     UHATSH   dL$%(   LeIH\t6H`   [Ht HH 1IH!/x 01X   H\gt6H`   H) HH 1IH.x 01H\LNt6H`   ǸH H6H 1IH.x 01H\	t6H`   聸H HG 1IHG.x 01~HEdH+%(   uHĠ   [A\]ފ ff.     UHH   dH%(   HE1t6Hp   H HeG 1IH-x 01HEdH+%(   u]fff.     UHH   dH%(   HE1	t6Hp   vHo HF 1IH<-x 01sHEdH+%(   u݉fff.     UHH   dH%(   HE1t6Hp   H HeF 1IH,x 01HEdH+%(   u]fff.     UHH   dH%(   HE1}   t=t6Hp   lHE HE 1IH2,x 01i1HEdH+%(   uɉψ@ ff.     UHATSH   dL$%(   LeIH\t6H`   ۵H HJE 1IH+x 01H\Lt6H`   蒵H[ HE 1IHX+x 01H\t6H`   LH HD 1IH+x 01IHEdH+%(   uHĠ   [A\]詇f     UHATSH   dL$%(   LeIH\bt6H`   軴H H*D 1IH*x 01   H\t6H`   pH9 HC 1IH6*x 01mH\Lnt6H`   'H HC 1IH)x 01$H\t6H`   H HPC 1IH)x 01HEdH+%(   uHĠ   [A\]> ff.     UHH   dH%(   HE1Mt6Hp   VH HB 1IH)x 01SHEdH+%(   u轅fff.     UHH   dH%(   HE1Mt6Hp   ֲH HEB 1IH(x 01HEdH+%(   u=fff.     UHH   dH%(   HE1=t6Hp   VH HA 1IH(x 01SHEdH+%(   u轄fff.     UHH   dH%(   HE1mt6Hp   ֱH_ HEA 1IH'x 01HEdH+%(   u=f.     f.     f     UHAVAUATSH dH%(   HE1H   1    ff.     A   II9r   HHH<   MrIHt/ML`1ۉ@ ff.     LHI( #L9uHEdH+%(   u#H L[A\A]A^]@ 0   1A   D@ UHAUATS1HdL,%(   LmIMef     LHI( AM    HH9rHEdH+%(   uHL[A\A]]ɂf     UHHdH%(   HE1Hz!vHEdH+%(   u"1 HEdH+%(   uHHmh     UHAVAUATSH   H$ H   dH%(   HE1   AD9      :AH>    HH1H5 HIHtwH     L   HHtK;PPidu{:uL腆1HHH5^t uIf     LH1fD  HUdH+%(   uH   [A\A]A^]ø   %D  Uf1HSHH  dH%(   HE1H| 8H0	gy X@ǅX   Hh
H(  11HHH0HEH'x HH(aH= wHH~	HHEdH+%(   uH]1:f.     UHSH(dH%(   H]H   tNH'x H x H9u3ff.     1HUdH+%(      H]D  H H9tH9XuH(  H5< HtHEH}к   1     HHE!LEHA u:Hx Hx H9ukff.     H H9TH9HuKHr"x H(  HF 1011$fff.     UH58  HAVAUATSHdL$%(   LeIH=dy .H=dy {LHtEH=zdy H5  H={dy 1HUdH+%(     H[A\A]A^]@ X   膳HHF  I$(  HIgIH  R   HH    p:   LEH$    LHH{1ML   H:    LHx LcHx Hx H5  H=}cy HHCHH={cy I$  HH9fI9t!   tHjI$  HH9uD  M$(  Hy x 1LHD 01LLHDH5M  H=by aH=by W /   LKH|ff.     UHAVATSH(by dH%(   HEH       HEȅu&HEdH+%(     H([A\A^]fD  H5  IH=#by 貨H=+by FLn=Lby LHcHz9   H5 LS   by    EȺ     H}j   H=ay 6uRuHx LHC 101,H5   H=jay H=ray Mx     1@ Hx LHGC 101D  Eu2H=cay 螼uHsx LHqC 101@ =ay    HuÅ~H5s H}.;H x HQC 101Nz@ UHHdH%(   HE1HEdH+%(   uH=n`y 	z@ UH5H=9`y HAVSHH dL4%(   LuI諦H=$`y va`y tELHH   HHH  Ht!  sxe9taA8uJf.     H5)H=_y =H=_y 1HUdH+%(   udH [A^]    HUGHU؄t   Hz HBH   tH5H=@_y ϥH=H_y cWy    UHAWAVAUATSH   dH%(   HEH x 8   =_y IJ  Å  H54H=^y IEH=^y uLx M9	  H=^y ]  H=^y 	Lx B  Hx L9  1     H уL9u|	HcH#IH  Hq5 Hp~aw K^y fHnHr fHnD/^y fHnH>5 flʾ    flfHn1L`AH#5 ~w )PflABL`Hs foPIB0I$  AJ Hx8   L`   Lx $  Hx L9t=HcH=?r If.     H:HpHHrH L9uHcH    I    H=L]y LE]y K]y fH=/]y `dHx Lx `L9tff.     @PH L9u,     D  H5H=~\y H=\y asLiH5H=W\y H   xP    ӢH=L\y g    1v@ Hx H> 101迻LHIH@fInI|$HBflHA$iL1H=[y LRH=[y HEdH+%(   &  HĈ   [A\A]A^A_]    H=[y 11HuH=[y    H=' l,fD  H2 Hu2   LPfHnI$  fHnflHx)`SH   	   fo`LPL#x AB8uf     =[y    
=
[y eHx H= 101<xP   Etd ff.     UHAUATSH(dH%(   HM1	!  H  IHtHCHx   HX(Hx  HDI  H@Hx   L`(Hx      LDH5NH=Yy bH=Yy pLHH   H;x   ff.B z   Hx  2  !     Lj@ff.     H=UYy H5ݟH=VYy qH  L+M,$HCHID$HCHID$1HEdH+%(     H([A\A]]D  Hx 8 tXy   HWx     uW A   f(fTf.vXfU\f(fV f/s6L,@ @ A  D  Lj8    \L,I?D  ID$ID$M,$  A  Lf.     E1     H= HE@H59H=Wy EJH=Wy M̅H5H=Wy  H=Wy tnHU 1dH B(fD  LjH    Hx Hj: 101߶Wy    JKqff.     UH5tHSHdH%(   H]HH=Vy pH=Vy mHHt:HHPfHnHflHxHQH
 1HHx H9 t=H5H={Vy 
HEdH+%(      H]H=lVy fD  Vy tH= H5H=(Vy zVy     譜H=&Vy AH=Vy 1CH5lH=Uy 耜H=Uy l=Vy 虚=Vy 莚= Vy 胚=Uy x=Vy mH=Uy !Uy     of.      UHAWAVAUIATSHdL4%(   LuIcAą   Lx)HH$  LUuL   `  H   S   DhWAA}HְIM   1fD  A}     HHD'u3LHDD;tDH, L1   em LE1HHEdH+%(   uPHD[A\A]A^A_]@ ,IQ@ A   D   LH+ lI9nAAf.     f.     f.     f.     UHHHdH%(   HEHH9r1H9HEdH+%(   uɉm    UHHdH%(   HEHG HH9rHW HEdH+%(   u1nm ff.     UHAWAVAUATSH   H$ HXE(LeLmHE0IHM HHIHHE8LLHdH%(   HUI$tHGINj   8  HHGb  LH       H5) L    H     !     AFШ  H   H   HHǾ   Lc AUL   I1XHLsHXYH  I<$H˴HHz HIM,$H襢1HUdH+%(     He[A\A]A^A_]ÐH8    f       H  IFHt#HHtHJHtH)HBff.     IIF IGIFAG4 IGH tnAW(     JAO(9t
BvLLL腋LLL謡 ff.     I<$至HI$fD  I+FHHHAf      tH  IFIG HH      HHǾ   La AUL   I1RHLq^_HHHHP   HH誝IH  f  f  L	Af  H   I   `  fA`  e  Ae  f   	Af  HѯHHe  Af        HIFHHtHqHtH)HAHIF HBIFHBd  HHHAd  H   HHNLH  Aƅi  I<$nHfHI;Ff.     HHPIIFHifD  B4C    HHQHHPHLH۰HϞ"gL踰fD  UHAUIATSHHdL$%(   LeI1t-[   LHt;HC(HL9rLc(L9c0   1HUdH+%(      H[A\A]]HCHL9rLcHCL9rHuLcH5 L^   H5ߧ LG   H5s L0x   H¸H_L"HCXHsPHJfHnHKXfHnflBH0Lc0'    L#     LcrffUHAWAAVIAUAATSH(Hcy Hu8dH%(   H]LH   1LDIkL9t6L9HEdH+%(      H([A\A]A^A_]D  Lu1DLL9uHu"I HLDHxL9uL)t)Hy LDH9HG舢IHfu1bne[@ UHAVIAUATLeSH z 7dH%(   H]HLH{tgLm{ A6LH{t>HEI9r1L9HEdH+%(   u/H [A\A]A^]D  KHED  ;LmdUHAWE1AVIAUA   ATISHH(HMv>LEdH%(   HE1r1HoHu?P     LLA$Av>HHtH}Hct?ILHIHuE1HEdH+%(   u$H(L[A\A]A^A_]@ HEHtL(cfff.     UHAVAUATSHH   dL4%(   LuIm  HuH!H%  HE1HuH  HP[HH   1HH  H HzHH9r:      ff.     ff.     ff.     HH9   0XNSHLxu׃uҁxGNU uɸ   H9HF   F  tA   IH)   V  te ` HE1HuH HP[HH HE1HuH HP2HHfD  HUdH+%(      HĐ   [A\A]A^]HIvLHIHTH)H)IT&1ANN9r
H    HD2    HrHH)уf1҉׃H>    9rKATATHx H H 101賦    D
    a@ UHAVI1ATE1SH   dH%(   HE1xn1Ҿ   <HHtOHuHHH@MHHHt'H@E1HPL舃HHHAիHEdH+%(   uHĨ   D[A\A^]I`f     UfE1H
 HAWAVH0AUIATLSHx  H^dL4%(   LuI)0)@H)P)`oFHǅp    )oF()oF8)oFHL)蓂H   HHL˲Ht&HHH9PsH;P ?  @ ff.     f+     f=   f=  f>;  HhHH  H=x I      H*( 01a1HUdH+%(     Hx  [A\A]A^A_]f     f  Hǅ   f(  Hǅ0   faff.     H      HHL. _HH  HIE0HHf>  f  ƅLHHHE1LH HH׀HH+  t		I;   ,  I;     M   E   M1|HHH  1L{HH  DHkH  1H{IH  Hx   H1H(@0AĀ tHH;P  Lf@
  f>6
  HE1HHHE  HhLHhHHPHLL   @ f>u  ML H      1   KL3   LLL   ]H  HHMID;0	  H8DDHtB4HH@ 0  HtHHXH1HHHwoHIHEIـ; L D  HP     Hǅ   Hǅ    D  Hǅ   pHhHFHHHKH`      HHEHDHHHL؏     H8ďHw M   H H#    01躟UD  Hǅ    Hǅ   D  fE1LHHpH L|H  H   f>  H   HHLHLE1HLLr@ ML H1         }HHIع      LZHHLLL;   HLH{HLMA 9 HcAuHcA;A|%/PHcAT H
HOLJ<!H$f.       HHrHHHHHHHH;:sHHHLLLTf   E1HLHH zHf+  a  fm  Hǅ   f(  Hǅ0   fs   HHPƅ HFHF LJ    f>S&rHH
HD1HLLM%kH߹   L HIź      LE1ME6LEvLG    HHE1LHk yHH M   E0  H1\f= thf=tbf>0  HHFHHHHHH!  Hǅ   Hǅ   hHǅ   Hǅ    M@ ~X%qHhH`HHHEH 7LxILpE1U pu<HHHH	t&HHH9rH9HBHH9  IL;sHpDL|HuLxLp1HjsHE1LHHa HwHHHHH11H sHH bIHHHH|n1LrHHnb1HrHH 0H'H H      HIHHEH  LE1MMHI1H H/HHw  HDAHLHHH4; rN  HHHHHffD  Hǅ   PHǅ    Hǅ   5H8HE   LL謒H8HHELHt"1H8HD0HD9rEL0H   LL趈D0L:H7Hǅ   R; OLMMLDHHH   D HHLxLpH)HxHH蔤H	HH;PP*
t
@+LH-HLL5D0LPH81LPUHAVAUATSH   H$ H@fdH%(   HE1)Hd  HIH     Iu>A$AĸADDHEdH+%(   a  H@  D[A\A]A^]D  1HHo%  t;L   HHǅ    Z   HRz1H1VAŅ   1Ҿ   rHHtMLHHA~AFϚDyHM@ Hw IH H     A01蜔AAH@w IHx    01bANfUHAWAVAUATSH   H$ H   H$ H8H1IdH%(   HE1#Åy/       HcIԹ    HwqI9     H;H  DPAԃuAtTAQD    ~H3w HMH    A    2PH 1IXZ    SD     H襊HuoGNU       HI9LGLrI9H   L)J!s^   t HD`E1fAwHEdH+%(   u|HeD[A\A]A^A_]f    LH    HD
    HJHH)Ѓr1҉փH1    9roA1ɉ1
tVL UHAWIAVI1AUIATSH   dH%(   HE11  1Ҿ   AnHH   H|tGAHyDvHEdH+%(      HĘ   D[A\A]A^A_]f     HuHtH   E1H@HuHH	 nHt1H?jHoH0LLE1%_Hw MHo HX	    A01Ԑ6    Hw H: H 101訐 AKUHHdH%(   HE1   H    tHUdH+%(   uD  HX JUHHdH%(   HE1H    HUdH+%(   uJ@ UHSHdH%(   H]HH{赕HEdH+%(   u{H]t4J@ UHHPdH%(   HE1E fHUdH+%(   uIUHAWAVIAUIATSHH  HdH<%(   H}HMA  LLʗAƅ  Ad  1Ҿ   DkIH5  H`Hs  HL܅H  eLF  I:  
tHw x   L]{HLHǃ       H   L   I  H E1k   LHǃ       IEHH  L   H H   pkHShLC`L烻  HC`    H IEHH   8k{lIEHCX   Af    H  H'HH	  fo`LcDsCfopCC(foEC8foECHHEdH+%(     He[A\A]A^A_]     H11 Aƅ A\  R  fHuL  HcH@HuHH>HLK#HQw LH H|    01nA\    D  fob HL)Efob )EEXXX NH  HH LLH iH@    1HqH8  HpH8HS UHHO  H}B  H}CHlHAJE   1Ҿ   IhIH  Hw LH H    01#LMD pD9@ fo`H@$fopD$foED$ foED$0H@([ A\  oD  LxDoǅAH9w H    H$ 01]H A\  I    Hw LHs H    01Aǅ\  ^fD  Hw LH3 H\    01ΉAǅ\  fD  Aǅ\       6L   HӃ IH9w H" 01iAǅ\  f     Aǅ\  օL   Hs IHw H 01	Aǅ\  nNHw HH Aǅ\  H     01HHjw LH H    01臈Aǅ\  B Hw H    H  01C A\   ff.     UHHdH%(   HE1HEdH+%(   uoB@ ff.     UHAWAVAUATSH  HH@HHDldL,%(   LmEf  L  ƅ HǅX    Hǅ8    HH*L`XVfE  o   L   ) o   )o   ) o   )0HE1H@H HxHpddHt.foPoXHfoff   HH@XHPHt1H HP1L_HH~  (LQOHg  1Hn_HHM  HpVHxOH0  1H7_H(H  LNH  1H	_HpH  H 1fHǅ    )H8HHX 
  HXHHH HtH8 tHx 
  HHatH@HH+   HAHH  Hf     HX (  HXH	H  HyHHH   H߈f    DlƅE7      o  L   ) o  )o(  ) o8  )0WH9ys  fD  Hf   o  DlƅEp
  H@*f	  f=&	  HL`pVLL1HsH	  HǅH    1fff.     HLHHk	  HuHjHV	  EШuHULpVuIH+	     H5A H腼	     H5+ Li  HHHt#HUHHDHH!HHDH;E  oEfofsffօH#H߈f  Z  lƅ HǅH    7HHH1HHDE  ǅ    f(f= E1	Z t,DfEtfAt<  fAHHDfD9y  t<:  tDfEtǅx    HH   ;$  HE1HyX tAH;A`  fATHAHx@JH  H HhhHp  DxEt0D L:H5 HxLۗHxH  H f(\  Hf    E/  HH   .  HHH`HLhLu~H ttHxL`1H }u2HEHUHH	t"LMM9rH9HBLI9:  fD  HH;sHULHuHxL-w L1IHy H    Au HAu 1L   Hy LH H_HAXH+HLlHLMHHHIHE؉I;;LHLHH  HH!1I}0HAf  @ f +;$"sH=rh PHfxof.     HHH`A   Dh+AxHPHL,Hf  LH<HLDE1H@LH) HuL$eHEI9rHEI9  ILH/IHuH`DhAfDA   1sH= @HCk<.^fD  HHHHf  vfD  HHHHQ7QQH PHPLXL8HH@H0ZLLǅHEdH+%(     He[A\A]A^A_]fD  HH       HHx1EHyH HYcH(D  H`DhEOfH5 LHxHHw HHxHu Hl    0u1L{HEZHYH+E"fD  ǅx   f     H~+  ǅ        HHHXHH]ƅ H8HQHH}HH1LDE\1HXL HI4$H8g   HH@ID$HXHHBH+BHADlƅHǅH    E7HǅH    ƅƅ7H1H{0ieH{0HX \H8&YKE11HHA9PH}]ƅƅ7 HǅH    4UHAWAVIAUIATISHH(BdL<%(   L}Eǈd  I  g  	Јg  f{(j  EtH       H0询H       E1ELHLL
A   H    t.A   ELHLLDU   DUA{t@HEdH+%(   u|H(D[A\A]A^A_]    A$f  uME1     I    tA   ELLLLDUXDUtAf.     Au2UHAWIAVI1AUATA   SHhdL,%(   LmMTHG  HMtHdAE HuH)||usH} tvE1E   Jf.     }u0Et*HuHEH9HGHtHUH}LAօ   IL;msHUDHAHuǅ|H|HEdH+%(      |Hh[A\A]A^A_]f}u,Et&HuHEH9HGHtHUH}LAօu-IL;msHUDH赥Huǅ|o|dǅ|]0fU   HATSH`dH%(   HU18SHt{HH8at+E1H|HEdH+%(   uVH`D[A\]D  H߉EA   btHuHmHtf}>A   DDe    E1>0 ff.     UHAWAVAUATSL$ H   H$ L9uH  fLa H: H(LHILH   dH%(   HEH ))о))HPLfHnHh1fl) fInfl)莻   H1H: LS` LH0g   HL*  HPLn    LH9 -   H1H9 Ln L   HL荭   H0H(1L_ H\9    HʺHB,ǅ$H H9ht<HxH HhLhfD  HW(HPH耪LIE HW LhH9uHI9t4HxH HXD  HWHPH@HHCHWHXL9uHEdH+%(     $HA  [A\A]A^A_]ÐHPH7    HHLH HH   1躹1H1   1Ҿ   OH(H  H_$  H(H0iH{  H(H0   H7 LPH8H1LH5m HG/  HHH2     H1LH ȸH5el H   HʾHH軄   L-px HHоAu H~IIL!L!HHȾHEHH   HؾHtHH	HDHȾLHMtLRM9ICI!HLH   HtHtM    ff.     H(v VH0H(1LLk H 6    H获H)HH	HHȾ@f     HH	HT2HHtHkMt	H]H8Hxt$<E1LHx *  L L`@ IL;x  H8LDLXH  H   H#H      LXH9uHHH9HFIHtHLLH@KM9   I9   HȾHLL)LHHHXL)H9H8   HC^H  H@LHHx fInfHnHhLJ6flL)@HHHHH HXHP(H:LM9   I9   HHLL)LHHHXL)H9H8   HC1^H7  H@LHHx fInfHnHhLJ1flHXL)@HHHHp HP(H:HH9`LHIL`LML\    H@HXHXHhL)HPHHx HHHHp HP(H:ID$L`H9`t[AE PHI#$L9rL9sHHL8   HXH)HL9HB\HaL`%D  LLD  L L`H LHBMd  LhI9   Hff.     HrHJH|L9r	I9  HJ HQI9u1Hx0 t HH@ H9ht:H Hx0 uHPHHHH@ H9htHH f     H HBH9hu+?f.     HH+HQHPH@ H9htH HH0HuH@ H9hu拝$H   1   tp1Ҿ   HHxH  Hǉ9HxH  H@HHǅ    fo0Hǅ    H`f1fǅ    )$  @   @   8   HHff賐  HxH|~H           HxT      HHxHxTAU LhHDJH	HXH I9   HHHLHE1LXIH`fD  AU AL`ID$A~L$DH= HxHfHnID$HHǅ    flHHH`H蚂  ID$ I9tLHLXHx   H~   H9|yH H9h$  L`LxLh @ ff.     IG LxI9   I0 uIOI7MGp H9tL`HxnpNH+!H(n MLhH
D  H9tH0HxHH9r	H;2|HP0Hp HFI9uH HBH9h~4   4       Qǅ$L`HPL1LS Hz-    H(1H0LS HR-    îL11'AƅH011`   A] HdHIdHMteHt`HLXH4tt`HHXHIcH9u)LHLAuAU LD^IHyLXHL`RLDJLHLX֝LΝ`#LDLHxlpLH(l KLXlpKH&!fD  U1HAVAUATSH   Hx dH%(   H]HH?D 10  1Ҿ   7CH8H[  HS49  H8H@.]H  fo]< Lk H-XXXXXX D4LC IEDuDED  1Ҿ   BHEH  HD3H}H  HPfo@HE    HE    HEpHE   E)E4  @   @   8   HuHMfUfE܊   H}   xHttHCH}1fInHc8 CHHHox HHHǅ     H t}H}t   I9suH}tj}ILH8Sj0xIHEdH+%(      H   [A\A]A^] 4   4       @ HsLCLዽ0UH}Åhi}Ip    H8i0H_i}HL)(     UHHdH%(   HE1HEdH+%(   u
H     U1HAWAVAUATSH  HdH<%(   H}H1H  1Ҿ   ?ǅH HH  H@ZH  L HLā  E1HLH H@@H    LA  1H;HH(HH HHpH     LLHH H4ЄIH4  4uHH Hstapsdt H9u<  8      H(IHHH    H@HT2 HHPKH      LpHHPH&2 HHHǅX    Hǅ`    HxHǅ    Hǅ    [HHI  IM8HfHnHflHAE8H9  H 1t7HH H@H@H#  HPH1HH<H)HßH  HHiIEHQ  HHzHiIE H!  HH1HHHH)MHtHHH)H~8P:t/t+HxriIEHu!ǅm  f.     IE    H L  H0fo IE01AE AEH HEHH{VH  HH E1HH{ H<HHt#HHtA} p  AE A+E$AE HH E1H6 [<Ht6HHt*HA}   AU(   )AE(@ HHHFIu8HNIE@HJ[H)w 1H12Hp T^@ ǅLH d7CHEdH+%(   
  H  [A\A]A^A_]@ HHIE FAE(   `f     HH; uǅwD  IU0HH)HIE0IE I+E(IE H<w HW    H 01`]I}7MǅL%MI}Mǅǅǅǅǅf.     UHAVAUATSHdH%(   HUHH9   HHZHIE1Lr
fD  LrHK@fHnH{AflHJHC8OLHGLH{>LHLIF8IV8L9uHEdH+%(   uHD[A\A]A^]    E1fD  UHHdH%(   HEHH9t7HH1f     HA8HHH9uHEdH+%(   uɉD  1/@ ff.     UHHdH%(   HE1HEdH+%(   uɿ   黶fD  UHAWAVAUATSH   H$ HhHxIdH%(   HE1Ht*HH*  H5+  Héc  L)   H=E A   LH SPAE  L_*   HxLE1DHbIM  M      1L    H,b  B   1HtAŅ   LE/HEdH+%(   a  HeD[A\A]A^A_]f     HE1E1Dj HxHLώAXZE*Hw Hٿ   H 01YHyw Hٿ   H 01Y^@ HxHLE1Kb)   LHHA,    H	w DLH    01*YD  )   HH,r11H,nIXHw Hٿ   H< A01XED  UHAWAVAUATSH   H$ H8dL<%(   L}I?<  H5  ǉ$IH;  1E1 L(c   L  H蜞H   
   HҚHt  #   M  I$   HkÃuHw H 101Wff.     ff.     LHEdH+%(   c  H8  [A\A]A^A_]Ð   GHHHtfHn11fl RLH   I$    ty%uAD$H`I$   H   ID$HHHBÅ   IGIOMgfHnfHnflA$L aHFLMk    3f.     ID$HI$   蘠H,I$   FL߻1;tff.     UHAUATSH   H$ HdL$%(   LeAI[QMH    HH1[=y'HUdH+%(      H  [A\A]]fD  HIw EH! H   01iU1EtHkw 8 t&1H1fyݩ       H1=fD  UHAWAVAUATSHzx H(D-x dL<%(   L}AHE    HE    Et;DHDlHEdH+%(   U  H(D[A\A]A^A_]f     1H=? TAƅxH5 IH   LHuH}
   ;H   {    { ~   {( t`{8 tB{H t{X uHsPH}	{CX@ Hs@H}zCH{X u     Hs0H}zC8fD  Hs H}zC(fD  HsH}zCm H3H}zCL@ L^x H}Dk8UHATASADH   dH%(   H]t>H= bSAEx>HEdH+%(     HĠ   D[A\]     H= $SAEyAuFEE  L& Hy Hhw Hy 1D\01RD\y    A%  HJ L%Q D\裉D\u3D\$  D\MMI1Hٯw H12Hs RD\f.     A   DH`   D\Ak   9D\HD\-MIE1H^w H12H0 QD\u    L	 Hp+ D  H L% D  DH`   D\Au   9D\H]fD  Hɮw H 101PD\ffD  UHAVAUATSH   dH%(   HE1H   IH   HH=X AAADPDH=b PAE ;A1Dx'HUdH+%(     HĠ   [A\A]A^]@ u	D9  uuAC  ufL% L- [ur1=  uKMM1Hw H12H@ Oe@ WfD  AuL% L- ߺ   HPo7HHKL%<w LH1HHi 1A4$^OD   HP(7IJA4$M1HHU 1&O    EtFL| Hϥ Hw H 101N~D  L% L- L^ H( Hvw H 101N6	     UHAVAUATSH   H$ HdH%(   HE1   11OIH   |Å   H5W  IHuS       L  H\HHt7HbHHÀ;
u HLMx9LXtL%HEdH+%(   uIH  L[A\A]A^] HIw    12H rMLL袗E1a2@ ff.     U   HAWAVHAAUATSH  dH%(   HE1H貛H   I11I_IHF  E   @ H{H0uxOLH1H#    H@44   HZ   L襖L蝖E1HEdH+%(      H  L[A\A]A^A_]fHLHAAtExHJHHt`H{HWtyqfD  LH@IHAAt	E>HsJHHLϕ0D  UHHdH%(   HE1HEdH+%(   u1f     UHATSH   dL$%(   LeAHuHH̨w 0H   HH,    1JHw 8 t/E1H脁HEdH+%(      HĐ   D[A\]fHX_DHHjHI?_HI9}#H`   8AM2H&w 1AH 1H1NJmH    1A0JWfD  UHAWAVAUATSH(dH%(   HE1H   I   IHEH   HXAHtg    L{:   L_HtHpL>iuL{LL+itHsL|AătCE1H8HHHuH}藓HEdH+%(   uCH(D[A\A]A^A_]fD  Hw Hj 101IAAUHAWAVAUATSH   4dH%(   H]H^H}  HBL-zw H8xH8:   OAu H"   /   1E1H@H rHH@]4H@H!   HGHHtUHKH    1H@/Aƅ`ߺ   H@/Au HX 1H1GHEdH+%(      HĨ   D[A\A]A^A_]@ S   H@D8DEy/Au 1AHH 1GE-@ HK   H AUG_   ?E1_ ff.     UHAUATSHHw dH%(   HEH   Hc@9B   HH<@IH6IE HHtrH   HXHtWE1 HEHHt Iu IKdH{HHoyAD$HUdH+%(   uH[A\A]]1۸ f.     UHAULoATSHdH%(   H]H_L9t`L#HD  IHSfHnflIT$L"H   1H{H   5HL|I$LM9uHEdH+%(   uH[A\A]]& fD  UHSHdH%(   HE1Ht?H@;!HEdH+%(   u7HH]|D  [*f     HEdH+%(   uH]fD  UHAWI   AVSHdL4%(   LuI4H   HH@LLfHnHflCax-HxQHEdH+%(   ubHH[A^A_]@ HIw    12H rDH*1fD  Hw    12H BDff.     UHAWAVAUATIHSHdL,%(   LmISHW  I\$III92  A}D    M} @HtL胒t_@ ff.     H   Lat=HI9   MtIuH{ H9tHtHt0uH{L9u LzHEdH+%(      HH[A\A]A^A_] IuHtH{ H9tHuQ ff.     ff.     HL9tHH{HtIu H9tHt蜑tHL9ufD  胑[HL9u 1If     1A@ UHAWAVAUATLgSH(dH%(   H]H_L9   HIIAHE&    Ht} uLt0HL9tQH{ L9tHtEuLƐuH{L9uHEdH+%(   uH(H[A\A]A^A_]     1G    UHAWAVAUATSH(H}MdH%(   HE1H  IH  HH    g^IHtEHH@fInflHBHI   AE wI}I   1Lw   0HEIH  fHn11fl I   LmI    "  LPI   LmI      I}L%'   LuM0  AE1    H{ t7H!kIH5  I   HsAăj  LvAH`D9mHUM   E1HBLrHfHnHٺ fHnflAL0Hw 01?% Hw H    A01?HEdH+%(     H(D[A\A]A^A_]LmMt8I   ̉I}CI   W/Lv@ ff.     Hw H    A01>?sf     Hw Hҹ    01?I   HI~I   .Lu fD  Hw 1H 13>3Hn 1   >H}.fff.     UHAWAVAUATSH   HHdL,%(   LmLPfInLfl)PAąx  HPI96  L L`Lu@ ML$1@   LL    @   E  I$HLH H  H`    HHQ  A|$   EL$ I$L1LHH5} A|$ U  AT$(Ht  HH5^ 1  I|$HR  H<H(H  D<E  H@L1ǅ    HL         
   1LbHH	  HY2w IvL4HH>   LH    L
sLsH@rD<A9N  H(HcH5O DcL,    L4LRHtE9|sHL1DH    3xH@sEHǅH    IH  @   H_~IHLL5 @ H(LHHN    ND(1贊yH(L AL HI   eIIFfInflHBHI   AFI~H*LqL%HEdH+%(     H   D[A\A]A^A_]D  LL L L KqH ?qH@3qH(GHeAI   ,f     ML1HH5u LH  LpLp IT$0fD  ML$ bfD  LLH(L1L=LHRdH  H HH   mH߉(5p(  IT$8LbH9 PL AdHL L c   (H`HH   fHn11fl yH   H`H H       L 1LHγ    AGM$I   HMO  I<$7BLIG+BHIG HCHSL{fHnfHnflAL8H`.(H`H H\    L A1fD  MLL L nLncfL L rHw H 1L 017Htw D   H 017HPw MH6    L L 01j7LnHHnL L AHw H\    L L 017}    U11HAWAVAUATSH   dL%(   LMI?L]A  L1A9'A  LMaIQI9  H0HL5 HL@ HHL=c A|$ H7/ LEAHw 0El  M$   L   1He 5I$   L Hǅ   HJ   H HL Hǅ(   |VHA9~tI$   LxMu   LH4IH   IH J   H HLHǅ    VA9|H`E   >&  Hw    H; 014AHEdH+%(     H   D[A\A]A^A_]    DH    1D4Df.     H9w 1ɿ   H 01b4M$$L;E1jf     Dd%&Hw    H` 01
4DEtf     Hw    H% 013A?@ ff.     UHAWAVAULoATSH   dH%(   H]H_L9  H@L3IIH8XHLK       PH81   L
 :H8XLZRu1MM9   ILIHCHuH   LRtHw H   fIn1flHD M01) 2HHCfo HBHH   |H{LH   `"H(iM9]HEdH+%(   uHe1[A\A]A^A_]f.     UHAWAVAUATSH   dL<%(   L}IL%̏w    H HH1A4$1Hh   H0HJ  HXH   H@H8fH{1%IH   L`L;`   H{_HK   H5 IH1e[LhMuM9t[@ IFH   HMN       PH81   Lp 8H8XLZPudM6M9uLH/HH-H0{1HUdH+%(   ubHe[A\A]A^A_]ÐI   LAPtI   q1M6M95A4$   Ha 1e0f     UHHdH%(   HE1w    tHUdH+%(   u&D  1@ HEdH+%(   u1lff.     UHHdH%(   HE1HEdH+%(   uɿ   &fD  UHHdH%(   HE1HEdH+%(   uɿ   [fD  UHHdH%(   HE1HEdH+%(   uɿ   fD  UHHdH%(   HE1HEdH+%(   uɿ   ffD  UHHdH%(   HE1HEdH+%(   uɿ   &fD  U@   HATSH0dL$%(   LeIH}AO  It$HtdHHu	CHuH}H  IT$ H  AT$   A|$ t   H5Y H}   I$HtZHHUBHUȃ~'H/   HTHHU{pHUHHHHEH5 H}1ufI|$ t61H}IH}'XHEdH+%(   uwH0L[A\]@ AT$tH5 H}tff.     E1 H5 H}1E1 H5Ǭ H}1v|ff.     U1HAUE1ATSH   dH%(   HE1   1Ҿ   ǉ	IHtsHuH#H   E1HPHuLHɨ 	Hth1HHtYH8HtQ}      HDH5LI2=HEdH+%(   u*HĘ   L[A\A]]D  LE11o@ ff.     UHAVAUATSHHHG L6dL$%(   LeIb  H   LIՃHHcdu,C|. t,HUdH+%(   uIH[A\A]A^]     1@ S( JK(9t
BvI\$       UHAVATIHSH   dL4%(   LuIH@3L11H@AWE   D1Ҿ   HHteHuH8!H8H~   E1HPHuH8HU H8HtQH`H+h1I)0DQHEdH+%(   u)Hĸ   [A\A^]f~D  @ UHAWAVAUATISH   dL4%(   LuAH  /   HslHt^L LL|2H2IHu
A   LZVHEdH+%(     H   L[A\A]A^A_]f   IH@   L    0HDx H@H`  QH  HX HL eLLH   1H[1IALHCL%w H11H A4$(#D  L%iw H11H A4$(H5 H{  A4$H 11g(A4$H 11E1P( HQx Hh  Lk I:  M:  |  Htw Aǅ\      HP0H|  1HL_"z  A\  8  H@   HHG  IH  H*   LH<H1LH>yLGE~   E1fD  YL!E@  H L/H/H ISf     A4$H} 11&    L%w H    1A4$&A4$HH 11&HfD  H@   LH7@ HLFI   L LL$/H.IHAL%w H11H A4$& H5x L9@ L-w HH 1   Au %LH .H(.H IyRMAu     E)H@w 0f     H(unknownH@)   fHL%w H    1HA4$-%      H@Ht*EA4$HH# 11$hH(unknownfǅH) H@뺐ff.     UHH Hx dL%(   LMILh  MtIAP(    JAH(9t
BvI90sjI9prdLHuLMHuLMHeJx H^Jx H9tf     H;prH;prTH H9u1HUdH+%(   uYf     Hw 1LLEH 01#H}7   Hw LH׭ 101#-fff.     UHAWIAVAUAATISH(MdH%(   HEHx Hh  H0xlHxHt_H]L0MtSI6LquDIFIVH{ tEHDI$1HUdH+%(   uhH([A\A]A^A_]f.     Hx HULH`  aHt)HUH@z4 uHH+BEuH+B} tH+늸ff.     UH HAWIAVAUATSH  <H dL,%(   LmL-K LEHP HEE1If.     L   H|hH   HDw H8Mt\L1HH ,
   HdHt   HUdH+%(      HĨ  [A\A]A^A_]@ <LL1Hw LHH H81
   HdHuM%D  LmouH@   8	H~w 1H12Hϝ !1}fff.     UHAUATISHH?dH%(   H]HH5/ AH(    II<${D tX(HCHV  I}I<$(HH=  1Ҁ{D    HEdH+%(   (  H[A\A]]ÐHNw u	_   GtHWff.     1u0	v<_   BHuK 0Hw 1u@_ubPt7H ff.     1u0	v_u/PHu1#@ HC    I<$    HPH{GH }w I$1H 01JUHAUATISH8LdL,%(   LmIMT  MZM   I	ZH   H9ZHt-LHMLMLELELMHM   y HQLMLE`  HH5d L1HU LELM      Ay IQLE   H5( L1LEȅ   x_IPAx    HH5 L1Hߚ wx{x-IT$A|$ tQHH5 L1H GHHEdH+%(      H8[A\A]]fIT$A|$ uH5w L1 fD  @ H5V L1cf.     HH5, L1H LE@ H5 L1LMLED  UHAVIAUIATSH HLgdH%(   HE1H  H5 L=Å   Iv>@F  M   M$Mh  IH  H9Hg     LHMLECLEHMxEy HQLE  H5) L1LEȅ  fD   ff.     HEdH+%(     H [A\A]A^]fD  HHuA0HuLHZt@ )   LAObÅuEuIVH   HEdH+%(   }  H LH5 1[A\A]A^]    IFHM$$Mk@     Laq@    IT$A|$ tvHH5 L1H {Iv>@IFHHHHL1H5 A>f     1f     H5 L1D     IPAx t0HH5T L1HE 2>fD  H5. L1HH5 L1H LE   fUHSHH   HXL`Lht#)p)M)U)])e)m)u)}dH%(   H81HEIL H(H   HH@ǅ    ǅ$0   H09} H8dH+%(   uH]     @ U1HAWAVIAUATISH(DE>.H<dL<%(   L}E"H  IEtQHHt7H=zw 7P  I9tz_t_9 t=HAHu (     H5 HHtI9t  @ H LLLI H @   LD1Aǅh  LLH      } u,l  @ LLeH      t  ALH.M L@   1qAǅyHuw A@   MDH 011LMNHEdH+%(   =  H(D[A\A]A^A_]     HHLNA$H=Tyw u_uIAD$tIT$ D  ff.     BHs7u0	v<_tHtw LHw 1A014Htw A@   MDHF 0    Hatw LHϡ 1A01L.MH2tw H+ 1A01ZLMAfff.     UHAWAVAUATSH   H$ H8dH%(   HE1oH  HH    1HyAŅI  H5 HKlHH  E1H;x    @ (   .IH*  fHnIOIWIflH5w H HCL{IGIL81$K  H	   WH=C Ht/HxHH)HH<
u IG IH   Hrw IOAH MG   01H   HZHHHEdH+%(      H8  D[A\A]A^A_]D  L5q:x AHd:x L9t@ ff.     HHCfHnH{ flHBHHJIL9ug     AAXXshD(AC     UHATSHdL$%(   LeAH=x Huw 1@Å   H=x  uEt*1HEdH+%(      H[A\]f.     Huw HH0HtHpw Hv    01H=-x oHx HuL%pw    HI A4$F	"@ L%pw H    1A4$A4$H) 111@ UHHdH<%(   H}H=x Hpx     HEdH+%(   uH=dx f.     UHSH8dH%(   HE1tpHHHt@HH Ht7HHMHE'HkH}H@H}J*HUfD  HEdH+%(      H]H@ fHn)EHt"/   H}4THtOH}H뱐Hyx Hh  HtJ(     qr(9tAvs H9x HUH5>H`  b1HUI@ UHAWAVAUATSH(H}dH%(   HE1H~ A  HH> 4  ILAHE_IHM  HsHUHH   HsHx-   HETHMA   LAE   A*<
   MtdHmw HKH    LE01 HuH}L%~HC IF CAFCAF Aǅuf     AL2HEdH+%(   uxH(D[A\A]A^A_]ÐA|$4 u	M$M+D$M+D$LD  A     H9mw HKH^ 1LE01_LEAyfD  UfHAWAVI1AUATSHLHX  1dH%(   HE1) ))H  HHIAąi  Iu Et$AH  LBEx  EK  Lk HS(HK HLOAL9k tLEE  9Hlw HKDKHS H8Hj  ID+KH 1   WH{ H5H dIH  A   {)  f.     
   HPH^  L   H"THuLY%  Hfkw H 101ALHEdH+%(     HeD[A\A]A^A_]L=kw H    1A7DCSfoDL)=HDEHE1LHH))))  Iu E1AH  H   |H)   H!    AD9{A   HC0LhM   McM;er<     ID1+sLxID$I;ErE|$D   +sLiDTLA
IHuA   C=u/AGC& D1+sLAăCAA9~ #`H@   8PH)iw 1H12H THiw H
 1016foC{tDCHHHHLAHEH 1   Hrhw H 101
Ls>LKHLCM   H   PL` R      L1   A7XLZ1HU 16
AL=gw ^H   8IHK H 1IHgw 01	E$$AUVHL~ P^IQLZ PM@ UHHdH%(   HE1HEdH+%(   u@ ff.     UHAWIAVATISىH0dL4%(   LuImx4HMLHHMLLH}E5 EHUdH+%(   uH0[A\A^A_]d@ UHAWAVAUIATASH   EdH%(   H]HA  IuhI}H1҉xAH`Hz  3EDxK  IcMHkpID HH     M|$HE    LHhH  L5ew H   1H A6H`HULAm  E  L=fw    1E1HhH DxI?HcxLXIHHpDT LeI?H 1   MIL$MD$I|$/I|$8HtkLwMx  ǅx     ff.     I~	   IHHp&F  LIHuI|$8$QxuI      H= 1I@L9p0DTH}LXDxB=HhIp2=L9HDx.Y@ foEAfoEAGfoEAG A@A6  HhHŔ 11H!H<AH`Dx9DxDxDxHEdH+%(   ]  HĘ   D[A\A]A^A_]fD  INI?Ha 1   ξLfIHtxbfI|$8OAoD$HEH`LHHx)EAoG)EAoG )EfAD$AGAG MD$hIL$HEL$EAH`HULHxpH}H}DpfNfD  Hr 11DxHh=;DxnAcUHSHdH%(   H]HH*H"H{ H{(HEdH+%(   uH{0H]S莾 ff.     UfHSHdH%(   H]HHG0    GG 1LHHC0HUdH+%(   uH] ff.     UHAWAVAUATSH(dL$%(   LeIH  HH H5 HID$迶HEH  H9  HPHU  LmWHu1L     IN)AD$A7  HUI9  +   ED$L5`w H?    1A6AD$A9D$  HMA9   H5~ HHEH  HPHU  H}?*       ;   ID$H  H8HEdH+%(   M  H(D[A\A]A^A_]f.     LjHuLmL1҈E4(AD$AA  L;m  AL$}+DDED$f     	I$H@AL E1     H)_w HH 101TAf     H	ID$fD  I<$ H^w H 101fA6H 11  H5z HYHt4H	I$ A6H 11 T     H5bw u_uQCt7HS@ ff.     uȃ0	v<_uBHuHID$H]w HH 101 H]w Hx~ H 101H]w H^~ Hώ 101{JA@ ff.     UHAWAVAUATSHhHudH4%(   HuHu1HEH  M     HH]Hx  ;%     H5} Hh8u4:   HAHt"=   HAHd  ff.     H5} HqIHEDpDE  MtMA<$@
  I|$袵HEH`	  H-H]H}HCHL5HCHHE  A$ HuH}Å  HEH+}    HHx1M	  1HEH8   EL}AG@HH<HIGPH  HMQ@,  L=[w E1f.     KA7   HHEHxH| H]Nl1L=   L^@HEHt;L)LHgHHA  A7H   1Hx| rHELh@   L@HEHtI9tHxH5= Kw  :   L?HEHt:  HEHxHUHBH  A7H   1H| H5 | L8H^w HEAM H_шM  H  L)LHfH]IHCH8  A7HH7 1   HeLu    HIH  LEA <[  <.  Ax>  EMhAFH51{ LiHEHt`L)L3LH迯IFHHHH  A} [A7Hz    D@LE1HH} If     LuHLHU-HUHBHHHH+  A} [A7Hz    D@LE1QHEH8    HEHxH=6]w H@PHT
u_u
HMy$ uHMID9q@1    A7HƎ 11H}蟰HEdH+%(   J  He؉[A\A]A^A_] HE@D;%HH]f.     H9Xw Hg 101_D  MtA<$=_  H5y HI?H  H5x H衭H  D Lh  ;   EHE    Lu\  IF    A;t{H5x LRH  D8HX  A:  .  A%  A+  Hu1L輬IF0HE8 <  H  EIA;uLHHEHH(H   HEL=Vw DH A7E  H@0H  H}W$  LGHw  E1E1HGHEH  EuPHMHA80uKxxuEHu1HTUHMHA8HE8 t&HlVw H 101HMHAM  Lu Mh1QD  Mh1HuLELIFH@HU:]  I9LE  HBHEz uOHE    LuMo LHMHAH  A7H   1HT M        HEHv      HEA7@ 1Rf     A@   I~ J  A} *S  LIFH   fD  E1A:}Hu1LSAF HE8 HTw H 101@ HTw A~  Hu 1H3 01H5s LqEI  AF$$    HHHND@ EAHx( 6Hx0 +HHBu 1   EhA7LH 11*HA7H 110A} ; HE    HEE?  H@    HEHH(H|L=Sw DH EE)  L@HpM  HU  H@0HfHUR$HA?QHRH{    P1^H I|$HMHAHLHMHHH5s H!:HH)ؾ.   HHE4HAA$ HIH}LeÅH]uXI ۅ_D  H@    IF    H@0HWHz D11fHRw LH 101DuHQw H 101&DHQw H 101&A7HA 1HQw HH 101HH@0H8HH4 D11 HQQw    Hr 01wH 11]{A7H 11EcHy D11-KH 116 UHAUATSH(dH%(   HEHcG@   LgPHIM,I<$HTw H_Љt"HEdH+%(   uZH([A\A]]fD  H5q H}@At,H}H5q ,AtI(M9uD  1@    Ĭ@ UHHdH%(   HE1H tHEdH+%(   u2ɸ        G uH( uHEdH+%(   uX     UHHq HAWAVAUATI   SHHHL=_Ow dH%(   HE1A7HuL,H  Iă}  H8HEHH  LuH5 L+1LH51 HELH5p 1ILEHMM@@  H  A LHUEyH}HCHEhHIH  HMHx  DMA7   1Ho EAr:   C@M|$L$3IHt&HLL).HC H  8/M}CPLH5ݒ L$80  xxy  11HLHC8{P t#(   L2HtHx11HC0Ex{HHcHsHCXIH   CH   E1 I~ tuID9kH  Ot=   L92LHt  K|LpL{XLHHEHMLIL{XIHMIGL{XM4I> uA!@ I$A7Hr 11AH}%LʤHEdH+%(   s  HHD[A\A]A^A_]D  A7H 11AHE    D  x }I|$H   H5n A>=kHC8    I|$%IT$H      fD  ff.     IHITHuHmI    f     HHCH1LH5} Ht
   1HHC(D  HC(     E1   |fD  AA7   1AHl yz@ ff.     U@   HAVAUATSH0H_dL4%(   LuIH} C  M.INMtgHteLH5	 H}1mL-     ff.     1H}uHEdH+%(      H0H[A\A]A^]fILULH}L- Ht7f     { H H5Ν IEH}1ϵHtHt/HK9[uHHM HuH}H     IVHt1H5rf H}u1H}rHf.     1T@ U@   HAVAUATSH dL$%(   LeIH}  I$Ht-IT$H@ H5j H}HHD1ٴ   I|$跼HH   HHH}H   H1!AD$@5   @ HH5 H}1kx-LH!A9\$@~lIT$PHH<RIHuLr!1H}WHEdH+%(   u@H H[A\A]A^]     H8!fD  1@ 1H}H U    HAUATSH8dH%(   H]HH}  {@HKH}H5i L1rt  {P    Lc M   HK8Hu)H{H   H5Yi HM8HM   1H5?i H}L   H{0   CHE1~5LHuHH{X\AD$9CHIuЅxW1H}HI@ LCA80unAxxugHS LC8H~ H   H5h H}1mj1H}HEdH+%(      H8H[A\A]]f     HS Hw LK(H~ H5Sh H}HHDHD1 1@ 9tHS01H5h H}ѱ1҅OXD  Huw H2輢ff.     UHAVAUATSHdL,%(   LmII}I}HI}I}I}(AE@~zE1KH<    I}PH<    I}PHH<    I}PHqIEPH\Ht  IHI|$PLHuIE9u@AE@    I}P(I}hIEh    HEdH+%(   uH[A\A]A^]薡fD  UHAWAVAUATSH(H}H>dL4%(   LuIHtzHH  HEH8I~HtYHH  HEHxI~HHt7HH  HMHyHAFEAEI~HtHH  HEHxI~HtHH  HEHxI~(HtHH  H]H{(AF C AF$C$IF0HC0IcF@H<HHCPIH   AF@HuE1F@      I^PKT HHH;HtHU?HUHH   II<$H{HtHH   I|$H{HtHHtnI|$H[IHuFo    H{HtHHt=II$HSHPI$SPHM$$Ht+    I$IHuH}蜺D  IE9n@~HEL`P1HUdH+%(   uH([A\A]A^A_]H]H{gH{^H{(U UHAUATSHdL$%(   LeI*I|$ I|$I|$I|$ AD$H~tE1fD  I|$XLHHI|$XH|I|$XH|ID$XH\Ht@ ff.     HHeHuIE9l$HI|$X{AD$H    HEdH+%(   uH[A\A]] UHAWAVAUATSHHLc.HdL4%(   LuIE   HGw AT ;P~_AHcL$RIIff.     HH`I9uLHEdH+%(      HHD[A\A]A^A_]fHcOdm HH}L<RIHUIHuK<'MHEHUHItWHuLHK|% LHH}LMLEMM)E1AQHI    H躜A	@ ff.     UHAWAVAUATSHHHHuHwhHHUdH%(   HE1HE    E    ZHA  LpL`IM9$  HEHE     ff.     M6M9   I~HtIF HtHsHtHqtI~H3atHuLAǅ~HUH}HuAEtLGHcU~0HEL$RIHIfff.     HH`ԳI9uH}HUdH+%(   uLHHD[A\A]A^A_]D  LD}E~H} tHE8/uCEHE1fD  Uf1HAWAVIAUIHH}ATSH8HCw dL<%(   L}EI   )EHUH u/  HULe1H5_ LtH}texHMEt8HLx
HEdH+%(   W  H8[A\A]A^A_]@ Hi=w H; 101D  I~HEHH   HHLHH}YMtLH5_ L1襨Å6AF@3)   L%    3LefD     H5^ LE1YÅt6fD  HH5 L1$H}IUE9n@pIVPKD H<HEHuf     UA   HAWAVAUATSHpHH  $H(dH%(   HE1HH   H8HD,H  L`IM  H~x L0H@ ff.     I|$H#AŅytL0H8YHqL'H=~x ]HH{~x     FHEdH+%(     H  D[A\A]A^A_]fD  L(HpLuvLpHxH^    H@xH@Lu9H8蕲H譯LIHL0D  H?w Hpf)PH`#HxHIHMP  HG  LHǅ@    LH$ urM1  L59w Hp    1A6LHǅ@    LHHwH@H   LH      HHt11H HH1  LHLLL559w    LHl Ho MA6LD1NLHF H=A|x MIEHHtHH)HL  AHH{x H  1L1ǰH{x HH  HL%]  A6HCo    1LHǅ@    LH$ nHH   M   HQ}x LH@LLHH`  mL@H  HHA4 uII+OI)Hx-L {HH  L#   fD  1HH   uLHMIH@A6   H^n 1oHH  HHH Ht3HcH<HH HumL0AV H1H@íL@L    HH=yx H    E1E1   HLE1ff.     HLHH<H   H LHH J<0      AL$9II(uLHE  L8HA   HHL LA膭H螪E    HPAŅ2  HHPHnH 1HPALDHH J<6 ff.     HL0AH8Ьf L54w Hk    1A6LHǅ@    LHlHwx E1H&1& HHP    1H@'AŅH@1HHL03AL貐H=;wx 
1H5-wx {     UHSH(dH%(   H]HNH_:w x    1xf1HuH}1xQ}   }x4H1?}   U蚺}U܅~U舺U܉U=UHEdH+%(   u[H] HEdH+%(   uAHH]@ Hھ   }	wf    }|{ff.     UHHdH%(   HE1HEdH+%(   u?@ ff.     UHAWAVAUATI1SHxdH%(   H]ȉ1HpH  I  HcHkpLH`HEHhff.     AD$`E1   KvHI\$XH{   M<$M;  A|$D /  Ml$A   M?  LD|D|H?  LK@LhA   HpLw   L7LHI)HCM  H    HHHm  H*H	AD$`ID9 IpL9`1fff.     Hp|>|HUdH+%(   0  Hx[A\A]A^A_]fD  L;A   MtJMl$MtA|$D LkML-V  A|$E lB    M|$MtA?0u8Axu1{LL{D@ HhHpH5 L聖A   HuOH/w A@   L1Hg 01H/w H'Z    010UHAWAVI1AUATSH   8dH4%(   Hu1wH@H    ǅ<    MHǅX    I_HtH5 HL  AE h  AG`E1A   1ɅN  KvHI_XH{   MM  AD   MgA   M  LLHDP^DPLHH?  K@A   LH}H@H  H}LHHPHCHP   H    L#HO_ HX tHXLr  HK^ LH5e    1HHXL`    L'Q  LCA80)  Axx  HS H^ LC8Hd H5/O LHHDHD1  LA
   襪H@HEdH+%(     HĨ   D[A\A]A^A_]ÐLA   M  MgMtAD 6LcM)L% LAE A   1AV9ID<Ip<98~	ENA.D  HS H] LK(Hc H5N LHHDHD1ƗCHE1V   ff.     LLHH{XAU9SHIuԉA1L牍PfLH{HۋPt$HH5C    1HbPAG` A9     H5\    1}     MWMtA:0uIAzxuBLS{LLPLPD&@ H@Hu  LH5 LPbLPA   Hu A   1H*w 1HH b 01AE Hm*w Hb 1A011HI*w A@   L1Ha 01nAE1Aˆff.     UHAWAVAUATSH   dH%(   HE1  HcIHkpHHfff.     Ha0w A_EHǅhHǅp    Eo`@{Hǅx    D@GIGXHAƅp  HpH  DhEI  Hc@HE1H@HHHH0HEH8HPH    JpM7HHM5  AD *  MgA   M=  LDFDFH?  K@DGLHHH8tAƅ	  H8-LHIHCM  H    L IhLBhH	LAE   ƅGH`H;0  DkPH(LBh   H{ AE     L3A   M  MgMtAD LcML%T AuAE   AE1LpHhK<B<xbIEA   HuExIpL;<ff.     HEdH+%(   L  H   D[A\A]A^A_]     hAą}   JpH  Fh     MwMtA>0uQA~xuJ{LLs.DfH8HH     Bh H5 L行A   HusAEH,w x uE1f     IwhIHsHHt @HLH#  H%w H^ 101HʭHa%w A@   L1H\ 01A H(HIH{0    L(A}P    AEH~{MtvLH1&H5F L!   HA9]H   IEXIܾ@   INt L	HtH$w LH ] 1LH01Ln:H1<H(HI$w 1HJ01LHm\ pLHH(H\ 1LHH@XJL H#w 012gE1H#w H[    01	DBǄhwH#w H[    01DA֪<ff.     UHAUATSHdH%(   HE1~iLcIMkpI@ ff.     AE`~#1fD  H<[HHI}X+A9]`I}XAE`    LIpM9uHEdH+%(   uH[A\A]]@ UHAWIAVAUATISىH(dL4%(   LuIAŅxjLLHEH  HrAŅtk   MH HyD IE1HH1"w 01hH}迵*HEdH+%(      H(D[A\A]A^A_]D  HELx L耥{IH tE1IG@LJH-HuIM;gHrf     HIM;gHraf     Lh1HZ HHe!w Hً01HA$MH HWC AIE1HH%!w 01\}fUHATISHH~dH%(   H]HID$HtUH{HtID$Ht=H;Ht+I$Ht'1HUdH+%(   uH[A\] I$    ٸ:}f.     UHAWAVAUATSH   dH%(   HE1Q  HcIHkpHHfff.     AyE M  IAXH0Iy   IAH  80  xx  LL8PL8  `   藱L8IIAXH_  II8I|$   H HH8AA$AD$@AAEAD$P1L8  A|$P u%It$8I|$L8远L8  IL$81I|$HA    L8L8  IyHHt!L8L8HID$ s  I|$ t%IyL8L8HID$F  I9Ht L8rL8HI$  Icy@L8A|$HHEL8HID$X   AL$H~=1HM
D  I|$XIEPHH4HHHHtA9\$HM   AI`IpL;HIw L%Bw L9tAfff.     HHCfHnH{ flHBHͯHI$L9uE1f     HEdH+%(     H   D[A\A]A^A_]     IyXL8pL8IAX    AyD    IQHHV  H0LL83L8AyD   AɅ\AQAyD e  AyE X  H= L8L8IAH  IAHfD  IqhIyHL8<L8HI  LHL8L8HHM  H   H"w Hc@;B2
  IIHHd HU    L8HHDHw 014LLL8AyD    A?    H!w H9 L8輧L8Hw HU    01L8`D  IAHq(fD  AyD afff.     LL8豼L8Ay$   IqhIyHL(AL(HH8M  Hw HT    L(01H0H(H8L(    Hw H=    L (01譼L (AyE MaHIYX  M8  11L牍L(HǅH    L(HH <  H8HH   L(.L(  LL(HHLELHE1L ]H}HaHCH[  M+gL)k(LcH <HCH6  AH`A9  LHLc(H M)L;IHG  HsHx-HH(	H(qH; FH3F   L8HǅP    ǅH    ͂L8H  HXH  LHH(ML8fD  HxHH	  H{HPLHI^Aƅ~H8H0HPAL EtH(L D8qHcH8L ~0MaXH@MAHL@ LI`ԌI9uMDH0L8(谩L8AyD >D(IyHL8BHHd  H{IH"
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  M  Hw LH;    L 01L(H(H8LL o  HpIA0L`AA dL(AA$$H0H(H8L牅 |L(IylL(Iy(\foP L(A$fo`AD$fopAD$ hH8 L( L()    Haw x OLDHDL(tH (LDH]
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  FIIW IPA   HvI   HI   LAHIA$MMKHǅ    tFLgA   HjHEdH+%(   +  He[A\A]A^A_]fHHIEH  IG0H11HHHxHv IMH. AELME(   13!   跃HH7  IfE1L) Hǅ$   DA@E  LE1L    ƅ Mo3LH 1   蕓HHHH5ID(-n(31H    D)O,  D(HIHD9a@~vHQPKH5T L<MoLGH5- L;AoHIcAHAoGDIW HT z@ LIE	  IcHEuH-IEXHP  A}H  HLE1HLMI+_tSLH`  II(E9wH`LM   H=v HIWXI   ID$tI<$HK  HHHI   H8   I   3   H/ HH1褑I   IU HHHp2H!  H3   H/ H1UM   Iu MI   HHA)  .  x    I   HBH  DJ I   LHrHLHOHA  LI   LHzI   HHH   H5 H-H   HH5u HthHxu tSsuH tAuuHx t/H蛙HHGHM      B H`  HsHZ	W     H0   PL 1RD   HYH^=LH@   M   Iv3H/ 1H1	]      A    LM3H- IH   1DHH1I躎DD    LH  :   HH+HHt _I   HD  I   H1HHpHA    LM3H, IH   1HH1ǅ@ LMID ǅHǅ    fD  LLL3MH - I11|ǅHHHHHHH  H訛HHx蕛3   LxHH4 1H   HH5    HH5 z   Hu     ǅu   HW?@  HH0      PD   1L HXZ&Hft	=  HxH~H  xuTHH@H  fD  HH Hu   HxT{HxHH  @xHH5 tHH5 ȻYHMљ3H+ 1H1<ARǅK1Hθ   ǅs   lsuH t߃xuHx u   Ytǅx   +ǅLMIH3A@   1HH+ 1w@      Hv Hq( 101>ǅuLMIA<HHPF3HI 11MA3H* 11M։HMEHI63M1HH) 1螉]MEDCHM3H) 1H1S( ff.     UHAUIATISHHvdH%(   H]HHR܀HtH{nc.t!1HUdH+%(   uhH[A\A]]D  H3H{<tHSIu L舀HtH{ tH{#^HtH{HNuC       Bff.     UHATISHdH%(   H]HH~ t]Ht$H{HuH3HtL荩uI1fD  HuLuCU9~)9C~ډCHCAo$ AoD$@1C !Ao$HC AoD$@   C HUdH+%(   u	H[A\]BfUHAWAVAUATSH8dH%(   HE1HE    H  HIULsP   Ao$CPAoD$C`HU@   LB<Hs HMA   H   H}$L   HEH   H   D  LHSH}A{Hǃ       HEdH+%(   w  H8D[A\A]A^A_] Hs LH{0HLHs LH{0?H  LE1۔Hv 1H12H ?zf.     Hǃ       @H   80H   Ht|Hs HUQtHs H   HUQuH}HUH   ǳHxv HK 1H& 01袅H}IAfD  H    vH.v HG& 1A01VH
v HS& 1018?UHAVAUATSHHL.dL4%(   LuIMe I<$ twZHt!I<$HKuIt$HEu)1HUdH+%(   >  H[A\A]A^]    HPRtHZIt$HIESrIMED$1L1v H    A1]AL$AL$HLv    H AMED$ED$A1DH1EEAEHAD$AEAD$莏u*LH5  HvAF   f.     IEHLHDH5K   HIE x H@01ۋ@tAEX      A^Hx `s=f     UHAVIAUIATASH HqdH%(   H]HkIugD9caD9c|[HMHULH{觴~D9eu=HuLu-HH{  tCH{0DGyu ff.     1HUdH+%(   u'H [A\A]A^]fLHHC Hu= UHAVIATSHHLc   dH%(   H]HE~PH   IcHK HHf     H@H9t'H;H(u1HUdH+%(   L  HH[A\A^]ÐD9     AT$HIH{P   L   H$HS MH   L@+uIL$H{v H    MD$01衁11ID$8H   ƃ   HMHLH5   HM)\Hv 8 u-I|$8GID$8    	f.     ƃ    HMH{0HH5W   [I|$8GHv DH 101K;ff.     UfHAWAVAUATSHHHHv L   dL$%(   LeID   )EHEZt]4tXA$    t=It$ H   t'HUdH+%(     HH[A\A]A^A_]D     f     ID$PIt$ E1MI$   HHHEt	rHE@   UE$   HHEx?H&v x thE  EH5W H}   H> HEkt6H}H&v    H; 01Q1f.     HuH7upHv x t	E   Hv HM   H  01~IcH}1HHM4`cI~8HTH}k^fD  Hyv HM   Hy  01~fD  H}   H5Q  kLu	   LH}LHHM   H  AHv 013~EV+8UHH~HHSH(HdH%(   H]HHEH5{&H;x7HG0@u1HUdH+%(   u,H]D  CX       H E|mE8fUHcHAWAVIAUIATISHXHyxdH%(   H]H\HtHs(LuCt)1HUdH+%(      HX[A\A]A^A_]D  Hv D   MHg 01|HfDc)EH{0HML)EHaILk HE    ~@C(fn)EfAnLefbLefERu} uHs HMHhLR} tHL1҅O H	v H 1017|6     UHAWAVATSHpdH%(   HE19qt)1HUdH+%(   z  Hp[A\A^A_]    xHq(IIHAuDxHMHULH{0DE%x@HJv DE   Hl HM01m{HuL!uE9E   HfL{ LE)ELHMH{0)EHHE    ~@C(CLELxEE)E&QLxuI} tHLJ1҅OfD  Hs HMH{0LxHPLx} uHUv H 101zH2v H# 101`zHHx    fL{ LEHM)ELHH{0)EHE    ~@C(CLELpEEHx)E#PLpuv} HxtGHLLxHp5LxuUDEHMHkv H 101yHs HyH{0LxOLx} u3HuLLx"guHxDED+EDEHHxoD  UHHdH%(   HE  H1҃CHUdH+%(   u]3fff.     UHAWAVAUATISHHPH   dL<%(   L}I1HǅH    HǅP    HǅX    ǅ@    ǅD    oHHPI<$HEH`HܨH  HXHLeH`HD袩LHH``H  LKIH  HPLDtxǅD    HPH)I_ LPIGHT  HXHt2IH.     HUdH+%(     Hĸ   [A\A]A^A_]@ H@LHH0egLLmLL HXHHH(H9Pum  H(LaLuH9H-  XHtMH0LH8du3foEH8)EfoEH )ELHLTHuLKHHXHtH!DuHP Dt
+@AGHX1HD  L舄IHǅD    ċ@DuPH     +@L AGf.     ˛LD]RHXAG    H<v HH 101gu/I/eD  U   HAWAVAUIHhATISH   dH%(   HE1H`HHFH   HxH]fHnI} fHn)0fHnHH`1flH0H5fHǅP    Hǅ(    H )@荼DPEM  DEEf  H HHE1E1H H`HxH   @ HrHhI<$ t	HI  I|$    H1HH0H5Hǅ8    H0tmD8MD!L]  HI} LE1j HE1H t^_  H I} HHLkHtzI4$HHǅh    I|$ 1ID$HHH5HpDH`Aƅ  HG0Hu?ME1,    ML@ M  E   A   HsHtH"|ID$(H   H-v IL$    Hd 01SrExDuHEdH+%(      HeD[A\A]A^A_]D  H HHHDMEE1WfH aUAHv IL$    H 01qlfD  EuWHbv IL$    H 01q5IL$    H2v Hs A01\q+HxHfUHAWAVAUATSH   H$ H(L5hv Mn@dL$%(   LeIHIHe  M   L脅HIyI|lI$HH!  I@ @   I I~@ %  0H $2  I(  H{/   HH-  I<$   1IMH{5 HzI<$   |u1HUdH+%(      H(  [A\A]A^A_]ÐHI   HH9LLH?Lt;/tMM   H|u;H;yI$Hf^@ MtfD  LH_ 4f.     LH!_HL	_)f.     UfHAWAVAUATSH8  HHFxdL,%(   LmI) ))@r  I}0oIIEHp Ht)   Hs )   HHۃI}(HLH1VÅG  IE HH5q6 Hǅ    H@(HHIExHIHR  HA   1H@ IHL
   HH~DH|
uD HHƉtHLfD  Lt	HL,tkH~HLH5uHEdH+%(   ueH8  [A\A]A^A_]Hv HJ 101lD  Hv H   H& 01lHq:'UH@   8HTHH 1IHEv 01|l UHAWAVAUATSHH(L&dL,%(   LmIM4$9u(1HUdH+%(   N  H([A\A]A^A_]@ IvHttHxAIHl  I~HtHHE2LMuHLMGHHE7zHpv LEH    1H1kLMHML$(GID$pAV tVIt$H9YAF LAD$I|$0H51茘AEI~H5 /HtAEy\   HvuTHv x uLH5}
  H]AEuAE    I~H5 4/HtAE    fID$ HHHEIL$ Ht@I~( teLHAE?    H9v H 101gj*HxHv    Hu 1H1;jJI$zE t:I|$0HU]IL$ u#HtHUHz tz  uz$ uHz( t"IN0LHIL$ NAEP$Hz0 uHz8 uI<$ɍIL$ tHiv HR 101iHUIt$0HFAIL$ @ ff.     UHAWAVI1AUATSHxL.dL$%(   LeIrID$xHG  I}H  H5 {-HMHpH  HEE1ǅ|    HheD  HgID$(I} tHtCI}    HU1H5GHHE    LeSbE||   L}HI>E1E1j HpLHhhZYumHuI\$0I>HL`HtIuHLID$(    I} uI} UI}( tbLH||g I|$x膷ID$x    HEdH+%(      |He[A\A]A^A_]D  AE LH5HAD$Ք|f.     HEHpifI>ID$0HU)EI\$P1H5)EHE    AoEHEfH]HE    Le)E*}HpH|ǅ|Y!f     UHAVAUIATSH   H?dL$%(   LeI^H   HuHH]H   EfnME1HuHPH HfnfbfAք$   CHt	Tt<I} 3LLI$   HUdH+%(   u0HĐ   [A\A]A^]ÐHXI$   fD  \ ff.     U   HAWAVIHAUIATSHH  L%v dH%(   HE1HLHHH IFHEIcD$    H<@HETHHd  Au@HEE       HLHp uHx   AExQ}    Hp DDuE   HEdH+%(     H  D[A\A]A^A_] Hp< E~/E1E1@ ff.     H}ALI`L7D9eH>T@ H#EfHAT]UU  AM@+  #  HELHpXHc1L<@IM,7IH1IH`9   L	MIy tMI9   M  HLMILHHfI`M9S  I} HH uIL$H1   H 虲x#Mu HlIIFIE H| uHHpAh@ +A LH1IUPHH HHHv 0I1bHpQA
fD  MIHH@ I`M9t;I} LH uIL$H1   H 蝱*I`M9uŋHMH! HMHHHH9P@Hp1AHpd:f.     U   HATISHH(H   dH%(   HE1HHHHH HCHEHv Hcx}HPI$H   HEHHE    H} uH} twËU؅xMHEdH+%(   ujH   [A\]@ HcHH}HPHcEHHEHx8U؍BE؅uLPfD  뇺 UHATISH HdH%(   H]HHz( t$HEdH+%(      H H[A\]!HuHU蓊HU؅   HMHtKHK Hýv    HJ0HM HK 01_HLKHUdH+%(   u]H [A\]L;nHtv    H12H _LnHFv 1H12H q_f.     UHAVSHHdL4%(   LuI9t$   HUdH+%(   u&H[A^]    I6He    tuD  UHAVSHHdL4%(   LuI99.t$   HUdH+%(   u4H[A^]    HmHtLHH    UHAVSHHdL4%(   LuI8.t$1HUdH+%(   u=H[A^]f.     I6HutIFo oC@   qUHAVSHHdL4%(   LuIHE    18.t1HUdH+%(   u?H[A^]fHuHIuHMI9uIFo oC@       UHAUATISHdH%(   H]H7LAH3艦u-1A9HUdH+%(   u]H[A\A]]    CH{pHcHRHHt2HcCAo$HAoD$D   CHS(1@ UHAUATSH(dH%(   HE1Ht{IHUHuۂugH} t`E1 II9s&H}11Lo}LHHa"HEuL9t$HEdH+%(   uH(H[A\A]]    1w    U   HSH(dH%(   HUHUHt	H}
RHUdH+%(   uH] Un   HSH(dH%(   HUHU4Ht	H}QHUdH+%(   uH]UHSHdH%(   H]Hi1HtHHܩHEdH+%(   uH]{ff.     UHAVATSHH(dL$%(   LeI75t:4t5It$H   HUdH+%(   uuH([A\A^] I4$H܊tHU?   HHt
1fD  HU   HgHuHU   HQHk1|ff.     UHATSHHdL$%(   LeIihHtLHـu5H-Ht(HUdH+%(   u1HLH[A\]馀fD  HUdH+%(   u	H[A\] UY   HSH8dH%(   HUHUxHt%HuH}F4EHUdH+%(   uH]øfUHATSHUH dH%(   H]HI   1Ht.HH}貏HtHEdH+%(   uH H[A\]f17    UHAUAATSHHdL$%(   LeI@ H2&wIsHLFHHuHEdH+%(   uHH[A\A]]D  UHAUATSHH   dL$%(   LeIt24t/t*   HUdH+%(     He[A\A]]    HU   HHtHHELM1PHpH}HhLx<ZYH~HUHt;HEHH f<w<jH Ht<v<QH HuHuHH2(   bSHH   HU@  Hvo<wH}   C H}2HUfHnpC<tkwWH<owȃP<OFȉK<twT1<t<owP1<@ JI$KI$Hxf <t<uJf     <uJ뽀z GF12    UHATSHHdL$%(   LeI@ H`0uHLHHuHEdH+%(   uHH[A\]8     UHAWAVSHH   dL<%(   L}I/4t'   HUdH+%(     He[A^A_]@ LU   HLLX]
HtHHELM1PHXHpHhLx8:ZYH~HE8uHMHt:H @ w	SH Htvt7fD  HuHdGH(   PHHt7H}0HCHEH@HCH% HCIIH1ff.     UHAWAVAUATSH   H8H@dH%(   HE1v.4t1   HUdH+%(   |  He[A\A]A^A_]f.     H8HU   HtHPE1LpHH ff.     HLLhATHHL`H}HX8IXZMSHh>uHpHt2HN D  <w<uH Ht<v<uH HuH@H@H+FH0tq[HUH8L(HH EL(H*H Hx'L(H0H;xr
 1H@C1q     UHAWAVAUATSH   H8dL,%(   LmI,4  H8HU   #H  HXE1LpH@HPHH@ HLH}ATHHLhL`H@6IXZMt  IE H;`sH;XZ  HhA} t	8s  AU3  rP9x  p9mHpHHtJHH     w	BH Htv'H HuH.  1IcUH+PH(L  HEH8L HH0_CL H tH0*L A  H0HxL L qH(H;x]AE1  f   >AUH;P0HpHHtMHH "f.     w	H HtvH HuH3  1IcUH+PH(ff.     AE    1V  H9PHpHt<H  w	rH HtvWH HuIcMH:HEH8L(HH H0AL(H H  H0HL ()(L H  H0HxHL ((L H  H;x  AU1f.        HUdH+%(   '  He[A\A]A^A_]f     HpHHtMHH "f.     w	H HtvH HuH  1IcUH+PH(HEH8L HH0@L Hte t#H0L 'L   H0HxL }L xH(H;xHhofHpHt>H D  w	H HtvH HuIcU(HIHEH8L HH0H?L H   H0L &L HteH0HxHL mL HxXH;xsO(AE1x $x H0HZ>L HHuHhAU(x H0H>(L HHHhH0H=L H5H0H=L H\ff.     U>   HSH8dH%(   HUHU8#HtCHuH}%u2HUHBHH	HUdH+%(   uH]D  1    UHATSH0dH%(   HE1HtdIHBu1HUdH+%(   uKH0[A\]@ HUоU   LHt1HULEHLDHy뭸=fff.     UHSHHdH%(   H]HHE    #.t!1HUdH+%(   uXH]f.     HUо<   HHUkHUHu    HUH   uHuHs UHSH8dH%(   H]H^#.t!1҃tHEdH+%(   u9H] HuH܄   tHUоU   HHD  UHAVATSHH   dL$%(   LeISt6Hp1   HlHtHuHHHt	I$H9t*   HUdH+%(      HĘ   [A\A^]@ HHXa"t$It$HAT$AD$    u    HXHd5Hm;duHXHU:     HtmHhH}{"uYhHUX   H߉dHt0HhH}E"uh9dC     UHATSHUH0dL$%(   LeI8   HtnLH}!u1HUdH+%(   u}H0[A\]@ HUHuH}x+LEMt"HEIu#uH@I$fD  H"v ʿ   H 01JFt ff.     UHAVATSHHXdL$%(   LeIw t*   HUdH+%(      HX[A\A^]    HuH<xxHU1I9tHUHHHUj8HtH}Hux$HEL9sHEI9z    HEHE    L9rXf.     HUk   HHUHtH}Hu) t1HUVf.     HUHUX   HAVAUHUATSH`dL,%(   LmI_HtzHuH}uiLeEx`HU:   L/HtJj 11E1j H}E1Hu蟎ZYHt(1HuH}juH}Ic11e 1HUdH+%(   uHe[A\A]A^]fff.     U:   HAVAUHUATSH`dL,%(   LmIHtzHuH}uiLeEx`HU:   LOHtJj 11E1j H}E1Hu迍ZYHt(1HuH}iuH}Ic11d 1HUdH+%(   uHe[A\A]A^]fff.     UHAVATSHH8dL$%(   LeIHE    trH} u#   HUdH+%(      H8[A\A^]HXHtHuHHE0uIL$HUЋuH}AT$AD$t1D  HPHIhEMt=~9HuHlu)IL$HULuAT$AD$uff.        A<$ &-fD  UHAWAVIAUIHATSH8dL$%(   LeIStg    t[LLuLLLAՉÅt0tHMLLLHtfoEA$foEAD$L
     1HUdH+%(   uH8[A\A]A^A_]ff.     UfHAWAVAUATISHhL~LndH%(   H]H)E)EELmL}HtHtLI.tHHMHULH5ECHUdH+%(   uFHh[A\A]A^A_]D  HxLkuHxtLLAՉEtf     U1HATSHH dL$%(   LeE1HuH5AHUHU9HLHEHUdH+%(   u	H [A\]}fff.     U1HATSHH dL$%(   LeE1HuH5QHUHUd9HLHEHUdH+%(   u	H [A\]fff.     UHAWAVIAUATSHHxH`HhdH%(   HUHUeHtHuH}i  HUHuH   H]H   E1HuN    I]I9s>HIH}L)HI)L#HtgHuHAuWL;urMI9rLm LHAu1L;u   LH}Md$LC#Hu ff.     Hh   H`H9   HUdH+%(     Hx[A\A]A^A_]@ L9uH}H`HhH}H+f     LHAmHLgVL;uLH uH}Hc"IHu&fD  HhLQd	11LM@H`HHHht 	       UHAWAVAUIHUATSHHHudL4%(   LuIKcHtVH HHUHMH5nHHtLHAAǅtHEdH+%(   uHHD[A\A]A^A_]A UHH HuH5	dH%(   HMHHUHUdH+%(   uf.     UHAUATHMSHHHuH5dH%(   H]HHUHt[H@ ff.     oHMHUH5moGC|HHuHEdH+%(   uHHH[A\A]]1 ff.     UHATSHMH0dH%(   H]HHH5cHt1HH}-Ht HEdH+%(   uH0H[A\]D  1@ ff.     U1HSHxdH%(   HEHHuHuHU1HEHEqHt0HMHUH5H}dEHUdH+%(   uH]ø UHAWAVIAUATSH   HHdH%(   HE1ǅ4      11H`L]pH4LI'LHH  M  H@HPLL-v Au 2  HP1   H  9HP   1M9   ff.     H@HAIH  H0H6`n  HHL<W  H/L   /    H/Lb   /    HHL@tlHHH`LWH  H`qHtHH]  H8H`R&498g  HH;P@ ff.     HfL)EHEH)EHEHHtH<L%  HMHULH5EHUdH+%(     H   [A\A]A^A_]     Au H    17HH;P   H@HYIHtH0HR^uHHL:uH/Lu/ uH/Lau/ v11L:HHH0HEf     Au    1HH
 6H;P8cM9Zf.     Hf1L)EHUH51HEH)EHE0EtHǅ    McHXL`/HHXHߋ<EH`}H;11L8HHH0HHH;P.YH`[;0H    1|5LCH#v    H12H K5THv H#    01%5 ff.     UHH dH%(   HE1HuH5HUHUHUdH+%(   uG    UHHdH%(   HE1HEdH+%(   uHHH5   C ff.     UHAVSHH`dL4%(   LuIt4   @ ff.     HUdH+%(   ukH`[A^]     LHedt	1D  HpBHuHMHHHM"HtH}HULcHv11UHATSH0dL$%(   LeIHu(Ht$LH}'HUdH+%(   uH0[A\]ø UHSH(dH%(   H]HH}H}؃   tx  EAUHh  O    H~ HH HDHEdH+%(   D  HH]H5 1     HxyydHUdH+%(     H] HPy   uHEdH+%(      HH]H5 1f.        H5ɴ HEdH+%(      HH]@ HEdH+%(   uwHH]   H5 X     HtGH        H5 f.     H) @ H  D  UHATISHdH%(   H]H)xx5L?HUdH+%(   ujHH1HH5 [A\]fHɎv Hz    010   H5 H`yHUdH+%(   u	H[A\]?@ ff.     UHAWIAVIAUATSH   HHpHdL$%(   LeIZÅt*HEdH+%(     He؉[A\A]A^A_]fD  L>H H  Lm   LL,H  HxL(A   AH0LE1HhH8H`LeH@HXHH0    HH H1H5_ AŅ   E1HLATHHL0L8H@H(~IXZMtdH`H   HpLhH)I)H`LhEaLH5ڱ H1eAŅhDfIDEo   H5 L=TfD  LHuH0ILYÅ'L=H8H  HHu'   HELuML0HHL@A޻   HELHLHMH@Hx .)IHtrHEHULEH)I)HULEt(HH8L1H5 =Aƅx!1fLH5 L1AƅyDH}Id2Du   H5e Lӻ̻D  UfHSH8dH%(   H]HELHuH5UHUHE    EDEHtUԉHUdH+%(   uH]\ff.     UfHSHH8dH%(   HMH)EHUHuH5Y)EPHtUԉHUdH+%(   uH]ff.     UHH0dH%(   HUHHMH5	HEdH+%(   u ff.     UHH0dH%(   HUHHMH59HEdH+%(   uN ff.     UHATISH0HudH%(   H]HHE    HE    xHuHtYHUH0uIH}HuHU[Yƅu2HUH}Ht/HO <w<uH Ht<v<tN@ <tsw_P<owЃP<OFA$<t]wc1<t<owQP1<D  HEdH+%(   uEH0[A\]@  <t<uWA$<uW <uWD  UHATSLeH0dH%(   H]Ht[4tVLHC<t/LHt`1HUdH+%(   uYH0[A\]fD  LtŸ   D  L   HhHt}u   fD  LH1UHAWAVIAUATSHHuHhHUdH%(   HE1HE    HE    t%HEdH+%(   x  Hh[A\A]A^A_] HUHuH0uH]HtM6LmE1Le IL9tLLLH1,uL;uuHELuLHEHELHxHuHHOIML;x   HEHp!} upE9EuhM9ucIL9xtVLL5LHH+HpH OHuHHEH9ErHuHN+HEH;EsHMHIuLHuH +HEUD  UfHSHMHXdH%(   H]HHuHUH5<ESHEHEHUdH+%(   uH]@ ff.     UHAWAAVAUATSHHXdL,%(   LmI   oHEMcHE)EoC)ELLH5H}HHtzHuHHtiH}@t8foELAE foEAEHUdH+%(   umHX[A\A]A^A_] HuHftD+}Mch1@ HuH    xL;}soLAE oCAEUHAWAVASHHHdL<%(   L}It u/HMHHHMHtH}LDofD  1HUdH+%(   uHH[A^A_]/f.     D  UHHdH%(   HE1t)>wttG>wBHw  HcH>    wCHJ+v HHUdH+%(     ÐHv H 101%D  1@    \  w*^tu   uw؉H_)v Hf        t(  uwHv Hcf     HEdH+%(     ɉ%D  gHv H_LHSv Hw1HX$v HAH}v HH)v HAH v HHv H}H1*v Hb     H"v H? UHSH(dH%(   H]H   >w&M  >D  HE HcH>             1ҁ    @ HYv H<HtHHUqHU؅   HH u ff.     HUdH+%(     H]fHEdH+%(     HH]1҃^t9   uqH&v H<HtHHUqHU؅tDHH uHv H<HtHHUpHU؅tHHuMD  FHv H 101!  1fD  Hv H<HtHHUtpHU؅tHH`uD  1fD  H!v H<HtHHU4pHU؅`HHxuHEdH+%(   }  HH]Yh1    H)v H<HtHHUoHU؅ HHBu91    Hi&v H<HtHHUoHU؅HHu1    Hyv H<HtHHUToHU؅HHu1    Hv H<HtHHUoHU؅@HHBuyf     HEdH+%(   uXHH]2,f1 ff.     Hv H<HtHHUnHU؅HH u	D@ UHSHdH%(   H]˃>  wF%waH HcH>   d  .     tv   u.xEB   t<ff.     9,%f.     H|v H 101HUdH+%(   4  H]    {x׺a   u@ x   u@ {$x    j     {]xG   JuD  c	   &QKC   1  _J   D  &       #   D@ UHHdH%(   HE1 FHUdH+%(   u@ UHHdH%(   HE1FHUdH+%(   u@ UHHdH%(   HE1    u-18wH#v HHUdH+%(   u     HwH%v HW    UHAUL-#v ATS1H    dL$%(   LeIuV ff.     I| HtL>kt*HH9uHUdH+%(   u>H[A\A]]Ð@ L-$v I| HtLjtHHIuf     UHHdH%(   HE1#w0HcH H~tHUdH+%(   u@ 4@ UHHdH%(   HE1FHUdH+%(   u@ UHHdH%(   HE1%   tFHUdH+%(   uf.     UHHdH%(   HMEz tBz t$t    :DzHEdH+%(   u@ ff.     UHHdH%(   HE1t&w,HcH" tHUdH+%(   uf.     @ UHHdH%(   HE1FHUdH+%(   ut@ UHHdH%(   HE1t"w,HcH" tHUdH+%(   uf.     @ UHAUATSHdH%(   HE1?%u`H+v LgL  f     H;Lht1HL9uHUdH+%(   u H[A\A]]f     Cظ@ ff.     UHAUATSHdH%(   HE1?%u`H#v LgL0  f     H;Legt1HL9uHUdH+%(   u H[A\A]]f     Cظ@ ff.     UHHdH%(   HE1t/w,HcH" tHUdH+%(   uf.     t@ UHHdH%(   HE1t?w,HcH tHUdH+%(   uf.     @ UHAUATSH(dL$%(   LeI(   	HEHH   1L1mtAŅ   H=qv &qHCH   H"HF H{DHFHCHt{HsHgHHtgH{HUHs 3H{11H]Ht#Htv L   H 01H]HEdH+%(   uJH(H[A\A]]H{Ht)[HC     fCfD  H}7D]fD  UHAWAVAUATSH   H$ HXfdL<%(   L}I)ƅ Hǅ    MH   HLI\   Hkuv L;f.     A   LHLxLH   H3uLHwv LL   H8  LHUdH+%(   u[HX  [A\A]A^A_]f     HLB@ L    LHIH[ff.     UHH dH%(   HU1Ht8HHHtHEYHEHUdH+%(   u!H/K    HEdH+%(   ufUHAWAVAUATSHH   H`HwHdL,%(   LmA/HhH[  H{Aą=     E1HEEHXL-    Q    |HhH   HXHH   H@H`AHE9t+H{DH|3SLH(btAE9u1HUdH+%(      HĈ   [A\A]A^A_]@ |HhHtYHXH:HHtBH@H`HH+BHAE9tH{DH|RLHau됸]S'    UHAWIAVAUATISH(dL4%(   LuIH   ML1LHHa&L-
pv LH AE   1Au *DEEyQHAu MLH    1HUdH+%(   uMH([A\A]A^A_]f     DHIAu 1H    1뫸f.     f.     fUIHAVSHHPdL4%(   LuEƁ t
9O@tEt}HLH  H   oHUHuH)EoC)E   DH;EHUdH+%(      HP[A^]@ H?MHuLUt
}bHLDHtHtt   fD  HHHtH7HUHHHUHUHuH5   :f.        &UHAWAVAUATISH   dL,%(   LmIHǅ8    Et0   HUdH+%(     H   [A\A]A^A_]fD  8   6HH  L`    LL"LLDVLHuH}  foEL})EfoE)EH(L  L@8   LLH  H0LH1\LHC PHtaL8LMt<L0LH{(H H   1]   HC(HHC(HtzH(ILC4AE 0C0HCHCHCIEI]L+HCHMLHH5 L3 Hǅ(    HD1Lk   L`HtH0Ltx1L   LH0/HH8LH8HHH(z@ HuH}L} f.     H0Hzff.     UfHAVSHH HGdL4%(   LuAHt0H   fH*Y H   fH*^EEHHjv H8Hov x    x t2HEdH+%(      H DH 1[A^]	fD  HEdH+%(      H H    [A^]t	@ HHfHH	H*XY H1HfHH	H*XD  HEdH+%(   uH HH 1[A^]3 UHAWIAVAUIATISHH(MdL4%(   LuL5mv E    A~EHu    M?M   M9$     M9      A~) tA  tIc   IEXH<ЋS4%  Hcs0Hc1HH1HHHHfD  PHpHH9uEM?Moff.     HC(S0   LsLř K4H5 HIDP1s DEy4XZL;sthH= EL{M9tSEEMLLLM?M9uL;st+D}EHR H5 D}   AT1	4HEdH+%(   u,HeH= [A\A]A^A_]
11EIf     UHSHdH%(   H]HH?tHC0@HC0@HC0@(   HEdH+%(   uH]fD  UHAUATISHxdH%(   H]HAŃA	HH߉	D8t;v	HEdH+%(     Hx[A\A]]     ;u3HuL/xkHuHx[HEH9Eta@ HuL爕6HnHHuH]LeHufff.     1Af     LHAAHA8tm    SS UHAWAVAUIHuATISHHGHdL4%(   LuILx    8   HH   MtL
IH   Lk LmLLcLk(VIxHC0IGxHtmHs @ ff.     HHHHPH;p HBH
HufHHHCHHEdH+%(   uH[A\A]A^A_]fD  H1<HEdH+%(   uHH[A\A]A^A_]G=    UHGHAWAVAUATSH   dL$%(   LeLgHpI91  M4$LHCfo IFL0LkHCHhI9  M} LHHPLIEfo% HCHMeIEH`Ae I9G  M4$L@H8LID$fo-; HCHMl$ID$HXA,$I9  M} L0MIEfo5 ID$L MuIEAu I9M  L M>HL(IIFfo INIGL8MfAI9I  I$HMLIHSfo HCHEIT$L"HSH9  H
H]LeLuILmIIVfo=; IFHEIUL*I^A>H9   LmL#HSfo HKIT$L"LkI9tpIu IEfo LHHxHFH0A] HI} I}(L:HHIH6H9xuH{ H{(HL:I$L;et9I=I~ I~(LMd:IM9   I^LmI~ sI~(jLM/:IU L;mtID  H]LeLuLmH{ /H{(&HL9I$L;e\IL(L HI} I}(LM9I$L;XtIWL0I|$ I|$(LIh9HH;`tHL@H8I} mI}(dLI)9HH;htHXHPLHH{ .H{(%HL8IL;ptIHEdH+%(   uH   [A\A]A^A_]耼UHAWAVAUATSHHLjdH%(   H]ȉHJL9T  IDAE095  AE49)  IE(E1Ht>EHǐ ILH& HuHEH߲ 1(HHu1AHH)IMuIML9  AF09  AF49  MF(E1Mt:HU LHuH Ht HE1GHu1AHH)IMNINL93  AA09{  AA49o  MA(E1MtBH LLMHD H HuHE1FGHuLM1AHH)IMQIIL9  AB09  AB49  MB(E1MtBHo LLUH H HuHE1FHuLU1AHH)IMZIJL9?  AC09  AC49  MC(E1MtJH LDMHV H L]HE1HuTFHuDM1AL]HH)IIKM[L9  AC09F  AC49:  MC(E    MtRHu LDUH H DMHE1L]HuEHuDU1DML]EHH)IIKM[L9.  AC09  AC49  MC(E    MtRH LDUHH H	 DMHE1L]HuBEHuDU1DML]EHH)IIKM[L9   AC09`  AC49T  MC(M_  Hb LDUH H DMHE1L]HuDHuDUE1DML]EHH)ILLDUDM}DUDME}}DUEEEEHEdH+%(      HHD[A\A]A^A_]@ Mm L9E1fD  M6L9fM	L9mfML9fML9;u    ML9Z    ML9>    ML9     E    DKff.     UHAVATSH8H[v L%aZv dH%(   H]HHE     uA<$   w'H( HcH>A4$H 11LHuH    H}HuH61H}HI A4$LE1ILH 1L2HEdH+%(      H8[A\A^]@ A4$H 11fA4$H 11f.     A4$H$ 11|f.     A4$H 11\m    A4$H# 11<貵fUHHdH%(   HE1HUdH+%(   uyf     UHAWAVAUATSH8Lw(dL<%(   L}IHW(L9  IAF09  AF49}  MF(M  H LL1Hګ %A11AHI)IMNIvL9  AA09A  AA495  MA(E1Mt?HT LLH Ht LMHE1@LM11AHI)IIqMIL9  AA09  AA49  MA(E1Mt?H LLH? H  LMHE1A@LM11AHI)IIqMIL9  AA09  AA49u  MA(E1MtGHl LLH H DUHE1LM?DULM1AH1I)IIqMIL9   AA09  AA49	  MA(E    MtMH LLHK H D]HE1DULME?D]DU1ɉELMHI)IALLLD]DUa}D]DUAEEEHEdH+%(      H8D[A\A]A^A_] M6L9_E1    M	L9f.     M	L9fM	L9gfM	L9n       E1   @!UH   HHdH%(   HEHH9u>fD  H H9t0P09tx< t9}P89~HUdH+%(   u    1诱@ ff.     UHATSH dH%(   H]HuLo   CoAs0DC4C8   fC<C HEdH+%(      H [A\]     uHHuADEHMHMDMԅDEЋEy
HE    1oHCoAC8DK0DC4Dc=C t	C< lAC<_记 ff.     UHAWAVAAUIATASH(HMdL<%(   L}Ei HtDHMAEDHH,HEdH+%(   upH(H[A\A]A^A_]f.     @   HHtHMAHEDx,I   I   fHnfHnHXflI   ǯ    UHATSHdH%(   HEHHt<If     LhLHHH{H+I$HuHEdH+%(   u	H[A\]C UHAWIAVAUIATSHXHGH}dL4%(   LuIH@HXH-IHMHAw(HtcHP-IU HUH@z4 t=)AH}oI}  HUdH+%(   u2HX[A\A]A^A_]f     HH+B    IE     qUHAWIAVIAUATSH   HHL(L0dH%(   HE1HFHǅX    H@H@ LhxM   HXxHtL;{ s|H[HuHHMHUL5Ht(DEE1ɹ HuH0L  L(HXLLLG  1Q    L;{(rH[jf     IF8Hs0H0H8HtH(ED+S D   HUdH+%(   `  He[A\A]A^A_]@ HF8HHhH8H`H@HEHHHpH f.     L`HE1E1Lj H8HH@ZY
  HhHHHHǅp    LHtH HH.%LpMuMm M   Hǅx    ǅT    A}uIuHUHWHtIuHTHxLHFtTuIuI~HMHxrMm Muf     LpMLMm 'Muf.     IFH@H@ l    IFHHxtHXHHMHjHE$E1ɹ HuH0LH(HXHcH}HcUH(HXLI~H0H)Hp趪fD  UHAWAVAUATSH  HGHO0dL,%(   LmIHǅ0    H@Hǅ$ǅ(    H@ HAG@GHA D	y   A s  H@Ly @   1   @   H4 L%~ yL%  HMv H 0HuNv DE  11(HLv IEIUD 1HANv H@D	H+PE  H-R1IPLH` 1_AXIEIuHHx^M}8HHHHI?>H  HLD0@L HMv D E  pLHHLv 1IH12Hx 6A   HHH0O#H0@   D  McLEHI|$LxE1LHAz$D9uAL$+( 5  D9A R  LDH@ƅ IH DLEMIH0 MDDH HL@$HX  HLv H0 L  LILH5HnJv I1H12ATRDH A\XDDLD@HH HHJv AHKv 1 A    A  Hv AtHu AHu HEH[ 11H&Kv DEuHIv 86  H   LHHؠH  H`1HHXHHPHHHHHpHHLLHHHeAXAYHH   HH;XsH;PrlHHv Hu 101H`HHv 2g    o  O    HHH[u 11f   HAI XE拽LLD d  A|$   E;<$  AT$A9  A{    APC  ƅB H@fD@    LI LHeHGv Iؿ   2ATH QDH1A[[( D@A t   g  DHt -  11l   fo @H)foAH)ƅ0D  A  H
s AtHr AHr HEHI    1 H-RLIPHE    1Y^f   1w    LHHAFv IHr    1H1fA 0IM IULL HL#  HHH0LA@ LHE1=D  H I?HLHtHH1  LHI?E1E1j HH LA^ZtH=Ev 0HFv  "  HH 11SH\Jv 1ۃ@  HH@ (Hc    11D  O     HHL@1Hq 1   H=)@ AHH@Lp @      @   HP1IA\A^Hp @ H|p _@    1T       1<    1PHf 1   H@=x L@1H 1   H=OfL@1pHgp 1   H<$    L@ HH1HQp 1   H<f.     HH1HXp 1\   H<f.     H0H @   HDH/HH DHH <o  <O  D@EE@D$HxBv DHo AMD0HCv DE  11D H1Bv D H3 IM 0HCv EEH  11?   HE1[;HAv HJp 0HLCv   11 |   H%Cv HAv  3A  A  AWK    Hm AuHm H? 11HFv H01ۃ@$0    L   L:H0    HHLH  1HLI臽  HLHHXpH   Df|NH[HtmD;{LuHs8L1x/uLeHEdH+%(   !  HeH[A\A]A^A_]H[f.        1tn    `   HHtLp8HCLHC(fHnHDv flC(x'    HL`pLppMtLDkL*ff.     IL$ID$HDHHt%IE;l$LuIt$8H{80LE1fL#LHCH   1RA  H{k H=   11hHqDv H01ۃ@,H HSLH5%H@ƅ LH H HHHHHDLLDEHHH0 LIt$ H H߉@"H  H?v H0DHE  kLI`LHH=v E12AVHB QLH1XZHDLLD@ kH=v AH?v 2 A  2  A  Hi AtH}i AHi HEH    1H>v DEuH.=v 8   H   LqH   HHp1PHLXHPHHL`B_AXH~jH<v H~i 101H`H<v 1<    <o  <O  <  HJ1H[i 1@ H   5H ALDDHf.     [LIPLHH;v E   2AVH/ QLH1Y^D@IL$   Hh 11   fo @)foAD$H)ƅA  H|g AtHKg AHPg HEH 11UA LxEL H`I} DfHnH0flHpHǅ8    )`D   I} D   ƅ A   l   H5h HJHh   11bHk?v H01ۃ@ HPf Ho8   11%H.?v H01ۃ@(RLLEHH|1J  H MuMDfHnHPHpfHnflMHLDxflH)0HD)HH@HHPHHHHǅ    ff.     LH1foHH)pHq  H8v DxHe 0H9v 87  11H9v  uHZ8v 8~iHH薶H?8v 1H12He jHҴ.    H	8v 3   He 11,IGHHLHxIIGHHLHxH   L9tLfD  IGILHG H@H@I)H)Hz7v 0H8v  tC11IH   Ibf   1t       1\Hd 11JHH6v H^d 1H13H`H;pt.HxH@HWH9;  H;W4  HBxHpHGHpH;t'H`HxHpHpH`HHJHH8H8HHHHt-ff.     ff.     Hx   HPH HuIGH    fo0HH@HHx:v Dh1HI?) /tMHl ƅIƅyƅƅ	ƅ9ƅƅƅ)ƅYH0L`L;p3  HHHML@L)HICM{LHb L   H5v I   0H|6v    111LH IGpHHH9  LLMI     HI   HCIIGLHxkM   II  ǅ    AG@XAD x  HH  LLL IL    M6M  M;nuIG8IvLH8HtAv   ;X  ;4  HtIc^H[HH   J  A~    j  fo H[AVHH) foډDHl| ƄJƄH)0ENEFH3v 0H4v    11A   Ld,    IFpHLpH9 LMML;p~ǅ    HHML@H H;P=  L7HLLP HWHSHPL9HHuHd     M@ A^A~    +HHt
x=^  HE1L   HN3v H1v D4 2E9N   HH{_ A؅     1   L*M6MfLL M;gm  IH@PHtHHLLHL9pGIM^@ A^A~  L蹭    A~ @ HAH^ O  11&f     A~  &H[fo HH(H H`AV) foƄJDH9^ ƄH)0ENEFH30v HXH0H1v    11I   Ll)H[HHKHhHhKHRHH J~H`H;(iHXH; THLHhH;3Hkh0fo H</v Hk0H) 0foDKH0v )0H] 8 X    11'OfIG8HLHXLH8,LUǅXFfD  HxLl_       1    LL5HU'    H H&   1cL-   1K   1:A   HHLL_ L@IG0@y	LB Lc,LMΈ KTm HHHLLl5H=.v H5f-v AzAxD6E  HM1QRH~v PD1aH Ax   HHJ~  JH HcH>H,v HZ 0H>.v  s  11I?H.v  tIW0BIW0BIW0B(   d
  ǅ   HX Hc,v H 101H H;PL    H HH K|m HHQH+v HHZ 0H[-v 8
  11H KDm IW0HXHHfo )fo0D)BAGH6H,v  xAWHH;X   ǅ   HW H8+v He    01cH+v LH-Y 0Hx,v  	  11-KDm HXHHfo )fo0IG0)@AGHfH,v  AWHH;X  ǅ   HV IG0HX LchHP*v 0H+v  ]	  11tIG0x tOLcpD9uLc0HDKt,KvHH tMk0B5JuB5@IIWLLHLL H&+v  # AWHL    HHHKDm HHHH覿HO)v HH 0H*v DE  11cHH軥3  *  IG0DHE;  ;4)  IGH@H@ f  tIG0x{	  @  H*v HU ǅ    DE@    A;G@  ;4  AD {IGIwHx HV HH+(v 0H)v DE&  11MIG8HH HH8\#  9  HAwH+ |H'	    `  H'v HU 0H)v DE  11IH@PHtHHLHƅ  ,HH/'v HT 1H13Z)H<[LHH޿rHLH<辿A~  &HM   QRHo PD1H vHR AuHR H$    1   14   1`   1yH`LpDL9t'L'    HGID$L M9LM$$uH8Ht    HHHuA  ƅ <P  <  HJLB11HR -HQ \HQ H   Hg%v    L   12H8n H&v D E\  ǅ   HIQ HSR    1JqD$zLBHHQ 11"}MH?V DIE0D`Ey
AH@} DLux   R@@   @   LQ    LP1Y^Hv$v AEH2H%v : A  ARHMEPHm 11A[[H`LpL9H8H:Hc)v A   @0<IE8AEDH(H$HDH8?Dǅ$A,   1DHH~ 11HJ1HP 1HJ1HSP 1H$v HO     H*#v HN 101XAwHHHLH=   Hc$v   o@)o@ @0A)GH)=ǅ   HO dLBHj 11'HHij    1UH#v H%  HI"v HN    01tL觺H#v 8 ǅ   HzN    15v   1$ǅ   HM ǅH#v D Etǅ   HM ǅ   HM 3HHGHBHO   1&   1}   1l:H HPH9   L7Hǅ    LI   1%   1HHHH{HIk0IW0HDBAGH7  foL ) fo)HXL1	H`LpL9tWL'E1WMEHPHi    1AAXAY@      L1LkL @   VH8E1H;4IWHcHLL,LUH v  Hmv 2HM tG11,AGHH v 8 x {I?薟uIG0f   1MHv HRM 0Hl v 8    11"IG0IWLL,HLHcHH( v  %,AWHL{P=PHv 	t91L HLN   1}Vo@ P0)o@ A)WH)MfD  UHAWAVAUATSH(H}dH%(   HEHH    ff.     H]HTHIHI\$(M|$(L9tFL3HSfoH HIVL2&H{ 药H{(脯HLIM9M6uAD$P1ۅ~fD  ID$XH<HNA9\$PI|$X=I|$8AD$P    *LHEH H2HEdH+%(   uH([A\A]A^A_]y@ ff.     UHAWAVAUATSHHHuLEdH%(   HE1HthILcHX |   E2  E9wL(  HEHMIHc   IGXfHnHHcfHno
flJ2XfHH1HUdH+%(      HH[A\A]A^A_] H  DoL   Hc@HǉEHEIGXH   U   IcE1HHHUIL9mtvH}N$yI$IGXJ< uEt;IcAMHH)L$f     IGXH<HoI9uIXa    EAGPw@ ff.     UHAWAVAUIATSHXH   D   dL<%(   L}IHH Hov x tM9     I(     Hk  H5Jd A   HP81H*v x tM9     Hv x      L5 x   AH=d `HLH"e PL 1Lg H5H    LKXHv M(  ZxEE1AAMu       HH   I9     L9   u{HOv x) t
  tHc   ID$XH<AT$L  Ict$HHc1HH1HHHHfPHpHH9ukAHHoID$@AL$LHJ H5D AT$HIٿ   HHDE1P1At$8?AZIt$(A[I;t$(  H=H HuI\$(HuH9  HuDuDmIHSv Mx1ۃEMu   D  M6M   M9     M9      Hv x) tE  EtID$XIc   H<IcE4  IcM01HH1HHHHf     JHrHH9uʃM6MfIE(H=KI AM4A   AU0IH5C HHDǿ   P1Au _IuAXI;u3  H=PG Hu论MuHuI9  LmHu]LMff.     Hv IހxE1EHu   f.     M6M   L9     I9      Hv x) tA  tIc   ID$XH<IcW4&  IcO01HH1HHHHf.     HHpHH9uA赫M6Mef     IG(H=G AO4A   AW0IH5 B HHDǿ   P1Aw XIWYI;WtxH=E HUIMwHUI9t3DmMIfL   HL荬Mm M9uLDmMwL9t#DmHDG    1H5A AU H=i ոM?L9}HLmIHu]MuL9t&DuHF H5YA 1   DAVH=h Mm L9mHuI;t$(t$UU   1HF H5A bH=}h 6
   蜒HEdH+%(   &  Heظ>   [A\A]A^A_]11A   L5e rL5d ffD  11A11让LE1A      I9  L9   Hv x) t
  t!H(  D   1H5B AcHHuA   LHG0H0H9;D   H@0H0I9u"A   \pf.     @ UHAUATISH(dH%(   H]HWHH;Hs(iLI}M   H   LHEH}ȉHSLbHJI9   I|$H9{t\Hv H;:tHEHEID$HSHC{  u8HLvC 1HUdH+%(   uxH([A\A]]D  C  fHHU褾HULHu HAv H MHtH,v H9yHsHShy+off.     UHH dH%(   HEHH   HtHEHEHǀ       HEdH+%(   unf.     UHAWAVATSH dH%(   H]H   Ht$HEdH+%(      H H[A\A^A_]ÐH   I1HI1AƅxH=v HHtADLLHEH}Ht!11H}褕H}I$   HlD胘Zmf     UHAWMAVIAUIATISHxHEHxDtHhdH<%(   H}HkE    H   LHHH   HuHHtyHuHL
Hte1HUE1E11HHMt 1HtHH`1H`IHxHtEMt	t u0   1HUdH+%(      Hx[A\A]A^A_]@ HuHUHHxL>ufLmHxHHhL}EHHEH HEH`HMLHHHE} TH}cF)lf     UHAWAVAUATSH   H$ H8dL$%(   LeIHHzIHHپ   yL{M  I_ H  H      H5= WM7L  I<$L IHt=j L1E1j E11LHLL9^L_   H$v L   H   LLH8  [zL   H1ɺ   HeH   I<$E1MH   HIH   L    j 11E1j E1LL'HLHI<$ZYL9HUdH+%(   unHe[A\A]A^A_]fD  M+w    1@ I<$E1MH   HLIHSifUHAWAVE1AUATSHHH}dH%(   H]H^H{蚴Dc<Dk81ID蔜HE    HE ff.     ff.     AA@t,IGLsD   DDl9LAA@uԍC   HcE臩HEH   HE1HE&     ff.     ff.     @tXIGHs   DDllAƅxH}LHE    uHEHUIc΃Hʃ@u@ UH}Lat?L}H}1ULLHEdH+%(   u$HH[A\A]A^A_]HuH}116hfD  UHAWAVAUATSHhdH%(   H]HYLkI      {<IIyHSHxH      I   HxI   HII9rIT$H9   H}wH{HML   H   HuH~ Ht3HSA   MLH}HH      CHi
v H}к3LxMLHrT    1~ ff.     1HUdH+%(      Hh[A\A]A^A_]@ EI   L   A)IcLH	v H>T M01UD  H	v L   H8 3=fD  H	v 4Of@ ff.     UHHdH%(   HE1H: tHEdH+%(   u 1@ H2HEdH+%(   u0eff.     UHATSHHdL$%(   LeLeH   HtHLu"HEdH+%(   u!H[A\]D  H蘴I$mefff.     U1HAVAUIATSHpdH%(   H]HHuu[{> t%   HUdH+%(     Hp[A\A]A^]ÿH/v 1H12H3 Z     HuH}HxtHxHH}H}PHUHuLp]Lm} 
  Lcs4H}AFC4tHLH}7  LHLlXH}HIFHHHMH   Q(f     rq(9t
BvHUHEfHnMIfHnflBDHH   Mx4 uLHL+HHJ-M   H5 HwQ HDHv 01H}21k0T@ ILm HUfHnE1fHnflDH}1cE1mf     UHSHdH%(   HE1Ht/H1%mH;HEdH+%(   u#HH]HEdH+%(   uH]bfD  UHAWIAVEAUIATISH   HXDTdH%(   HEHHHhHtLǅt    HHСf`I   H  Hx   IcHH.HJw H  `fHXt@0HXfH<THX(Hh L`LhLx Dp0P8H>JHH  L8H4Jw `HCL8qI   Hx<   ZHv    H12Hj3 軦HIw P4~/E1f.     LIHH|@HIw D9`4HC    H1HUdH+%(     HĈ   [A\A]A^A_]    HEHUIw LxHHhH`pHhH`LbHhA#EAT$1ILHֻu ѢAt$HHw LHFuHHw usH4"L%Qv f     At$(D)AEHcHHH|0X tCHzHp(AHHP HlHw H4A9}ptW D;p0uID  AA9|ff.        覔H=u HIHHHhHi    J@'_    UHHdH%(   HE1Hz!vHEdH+%(   u"1 HEdH+%(   uHH͎^     UHAUATISHdH%(   H]HH"   sHtjtcL- <"(  <H  PZ  IcT L>fD  L      H=0 '}    CHuHEdH+%(      HL"   [A\A]]ڝf.     L      H=,0 |D  L      H=	0 |D  L      H= v |bfL      H=/ g|BfL      H=/ G|"f<\uIL      H=|/  | Ht/    L1[<~ L֜\ff.     UHAWIAVMAUAATISH   LHt))P)`)p)])e)m)u)}dH4%(   HL,   1ML
   @L	   0A9uLLL      H=Q {HELLH   H H ǅ (   ǅ0   HsHdH+%(   uH   [A\A]A^A_][f.     UHATISHH   L`Lht#)p)M)U)])e)m)u)}dH4%(   H8H޿,   *H޿
   H޿	   HELHH(   H@H ǅ     ǅ$0   H0rH8dH+%(   uH   [A\]Zf     UHATISHH   Lht#)p)M)U)])e)m)u)}dH4%(   H8H޿
   AH޿	   4H޿	   'LH|Hٺ      H=M yHE   HH(H H@H H0ǅ (   ǅ$0   qH8dH+%(   uH   [A\]Y     UHAUIATISH   LXt&)`)p)U)])e)m)u)}dH4%(   H(L
      '    L	   uLLcL      H=4 wHE   LHHH0H?+ H ǅ(   ǅ0   pH(dH+%(   uH   [A\A]]Xfff.     UHAUIATISH   LXt&)`)p)U)])e)m)u)}dH4%(   H(L
          L	   uLLCL      H= vHE   LHHH0H#* H ǅ(   ǅ0   oH(dH+%(   uH   [A\A]]}Wfff.     UHAVIAUIATLcSH   LPLXt&)`)p)U)])e)m)u)}dH4%(   H(L
   Et!1f     L	   H迖I9uHEL   LHHH0ǅ    ǅ0   H nH(dH+%(   uH   [A\A]A^]oV@ ff.     UH HAVAUI1ATIԺ   SHH`  dH%(   HE1H11MLr( HC    HmM   ID$H   fx(    Ml$MtMm H޿,   蠕ID$H޿
   A   Lp-脕@ H޿	   sAuH5	 H   HH=    UtLHMtM   Mt	A}  uBfHEdH+%(      HHH-| 1[   A\1A]A^]f     H޿,   A   ͔H޿
   H޿	   賔AuHH5- Hٺ      H=ύ sLHUTUHAWAVL@AUIATSH   H8H`  HH  dL<%(   L}M^LL I[dH8LL	\  H8A|  Ip  HP賑  I  Ah   5  Aƅh   11H    HE1   HH8L% H LH1H@   HL HB    DH1~H@   HL׽ HoB    DH1QA     H@DOE{  {RH޿,   A   IՒH޿
   Ȓ     H޿	   賒AuH5 HHٺ      H=ϋ qLH1   HL%& H+,    H8H   HA  ƅ(A   1H8 0  LtI    (Le0EtiLHb0LLH@蠸LLHIEHL蓥H8AWIH   H;   LtI w/H޿,   芑     H޿,   sfD  E1I;  I!  I   Hu LH    D001辖H8D0H   AWIH;1H    1HH8H       HuH   HaH(H   IH8    H}A   H8IH}H   IH޿,   LuH@H0HH޿
   ;ff.     H޿	   #AuH0HIjHٺ      H=; oLHFI? LH( HHv 11   hH |1HUdH+%(      H   [A\A]A^A_]D  H8DHXHߺ      1L H H@W    ƅ(,@ ƅ(@ ƅ(@ I  W H8H LH0H;u H]! 101iH 荢	N ff.     UI2   fHAWAVHAUATSHH  H8~{u Du ~u u ~5u 5u ~-~u -u    ~%*u dH%(   HE1%u )))) )~u u hHH) xrƅLPǅx   XHfofo HHu fofo ƅHXHu fofoHxH u HHHhH{   {   ;H8  1A  hAăU  H5| DH H  HP11HwIH=   H rH  H{Ht'HHLL*ÅO  H {   H 11H    H    1H    4LqII@  x#   XL E11L H    LH0  HHHH HHIHi    HH芌L,   L
   L	   L	   H5! LG   HL   iHL#MOL0B L1H       MO   1LB H    LMO   1LA H    LL,   M.AL
   4L	   'L	   H5 LkL   H߾   iLLKL,   MnډL
   ͉L	   L	   賉H5 LL   H߾   hLLL,   MnsL
   fL	   YL	   LH5t? LL   H߾   8hLL}Mn0MtcL,   L
   L	   L	   H5D L1   HL   gLLL,   Mn8蠈L
   蓈L	   膈L	   yH5I LL   H߾   egLLEN(1   L[ H    LdEN,1   L5 H    L>A     L,   Mn߇L
   ҇L	   ŇL	   踇H5U L	L   H߾   fLLE11   LL1 Hd    AFd~_ff.     M  L
      5D  L	   #uI   H J4IcE9ndLH 11   H 11Hn    yH    1He    LH 11Hn    6H 11Hm 1H 
   \Hu 1L8HPH>5    H;EH L 讜fH;L,_ H*   H;5    YYDH(H  H tHC{1LbH JHEdH+%(     H  [A\A]A^A_]fD  L,   s'Hu H 4    H~ 01L1      E  LL~ Hk ]L1   M  L}<    H 4   L1M  LT<    Hj H;HD4    1CHxҸ   Hu    H=a Hc   Hu    H= H\cHu 28tPH 11ĉmHsu H$2 101衉HXu HA2 101膉He2 11tHCu       H=^ HbDZnC UHHdH%(   HE1HEdH+%(   u1Cfff.     UHAWAVAUATSH   H$ HHH    dH%(   HE1LII   LH5r L+HE	  HHA      H=2 aHٺ=      H=2 aHٺI      H=2 aHٺJ      H= 3 aHٺI      H=W3 aHٺE      H=3 iaHٺQ      H=3 PaHٺ'      H=3 7aHٺ
      H= aHٺ      H= aHٺ1      H=3 `Hٺ3      H=3 `Hٺ"      H=4 `Hٺ      H=r `Hٺ      H=o `Hٺ      H=j o`Hٺ      H=l V`   Hٺ   H=e =`L:1LHG  9  H3 LHǅ    HH    HH   HA   L$H 1MD$IL$Hh?Hٺ      H= _Hٺ	      H= v_Hٺ      H= ]_Hٺ      H= D_Hٺ      H= +_Hٺ      H= _Hٺ      H= ^Hٺ      H= ^M|$(ǅ    M   IH\AM?MtTEnHٺ      H= ^Ai=3333wHٺ      H= p^DE@ Hٺ      H=Q G^DAEiA3333wHٺ      H= ^Hٺ      H= ]Hٺ      H= ]Hٺ_      H=M1 ]Hٺ	      H= ]Mt$(M   E1L@ INH H1   >=IF8b  H    H1=M6AMtPEtHٺ      H=< 2]Aiū=UUUUwHٺ      H= ]nfD  H    H1<M|$(Ml  LE1E1   f.     EiAƙA2333E  Hٺ
      H= \   HEHHq AHHHL@1 <IO   1HV HI<M?M   E~   EfAi=2333vGIG8@KtwEiAƙA2333  Hٺ      H= B Hٺ      H=u [D  Hٺ      H= [dfIHEA>M?M:Hٺ      H={ W[HHٺO      >[Hٺ      H=Z/ %[Hٺ      H=5 [   H1HK/ :Hٺ&      H=Z/ ZHٺE      H=i/ ZHٺ<      H=/ ZHٺB      H=/ ZHٺ	      H= yZ   H1H/ #:Hٺ      H= JZHH9OLHٺO      H=/ ZHٺ/      H=/ YHHٺO      Y   H1H/ 9   H1Hv0 q9H?H
u LH    H81I91HUdH+%(      HH  [A\A]A^A_]fHٺ      A   H= AY@ Hٺ      A   H= Y(@ tH    H18H    H18yH, H9Hu L   H H81]8 UHHHdH<%(   H}HHUdH+%(   uHHfa9UH=P HHdH4%(   HuH5 ؔ     UHAUATI   SHdL,%(   LmI6HtuI|$Hk1HHPI<$j   HHPAu HEdH+%(   u@HH[A\A]] I|$j   HHnPH5 H=> t8@ UHAWAVAUATSH8MdH%(   HM1A  E~IHwIHtMu(HEdH+%(     H8[A\A]A^A_]fD  MLE  A   1HLUMH  EHDADL}DMIȍ{A   DHHMHDύ{IADHHMHDύ{IADHHMHDσH E1E1 DUL<ƋuquIcMHH L1D)HcYK?HHH#EAAԅ   H 0       HH  HDDHS   DHHHHDSHDHHHHDSHDHHHHDHHE Hp    H A0       c@    1Z?6@ ff.     UHHdH%(   HE15H5E, H= 衑UHAWAVIAUATSHHHUdH%(   HEH   HE    HEH   H}HEk;EC      EH}1E1EH}A蠢D9      I  HXL;cK  HEH;C =  HCHHIHD(HËuH}[@   EMHEH*  LXH=w    Hz
 H1H=w 	f _Hx:   HuH= w H5w sIHk  H[  I2H}1HdLHc}H}   HJLH}Lm-   LH-LH;Lm   LHLH{Lm   LHKH{Lm   LHKH}   t  HuL蔴HH    x   H}x   H}At$I H}A褠D9H}HEi;EHEdH+%(   ~   HH[A\A]A^A_]fHyu H2w    H 01xv     1f     *TfD  */H5< H=x| s2fD  H5h H=U| PUHAWAVAUATSH  HxdL%(   LUL   M4      Hh    Lp  HH  LpLhMbI:   LXE1H`Lp  fD  LHAL;A r
HHI)H-H 1   L Lh0H5ä HHHhߪHhx  AD$H| uHJ- tH H     L1莽L/H5	 HIHqAE xAE d  H=Q6 AD$uH=, /H5 HIH,AE xAE /  H=e AD$uH=, l/H5Ҥ HIHAE xAE   H`H`x  HIIHXL;8  H@HH  HpI$HHx   ,+HH   y-    LHAL;A r
HHLI)H-1H    LL[.H5 HHHhҨHhx   HpIT$HHx   t*HHt
y- FHk9 HW L1   a\@ LH>9    1H# L4<    H&i H&Q H&4 L& L& Lp& H`HEdH+%(   usHĈ  H[A\A]A^A_]D  HHt&LpLhMb1HHuH5 H=v H5{$ H=tv 诉
.f.     UHAVAUI   ATASHdL4%(   LuIH   IcHY}1HHELD,   HHtEI   HEHHtT xt@xt#HEdH+%(   u5H1[A\A]A^]D  H%fD  $-f.     UHAUI   ATSHdL$%(   LeIH   I$   Hi|1HHDLHL+   HH|DI   HMHHtT xt@xt#HEdH+%(   u5H1[A\A]]    H$fD  $",fUHAWIAVIAUATI   SHdL,%(   LmIH   LHt{1HHCI~(^{   HHCI   B{   HHrCI$   HBHHtQ xt=xt HEdH+%(   u2H1[A\A]A^A_]H#fD  "+f.     UHAUI   ATSHdL$%(   LeIH   I$  Hiz1HHBIc|$Rz   HHBI|$(HB HHD*)   HHZBI   H+HHtR xt>xt!HEdH+%(   u3H1[A\A]]D  H!fD  !*fUHAWAVIAUI   ATISHdL<%(   L}IH   I$   HOy1HHAI  6y   HHfALy   HHNAIc|$y   HH4AIc|$x   HHAI   HHHtZ xtFxt)HEdH+%(   u;H1[A\A]A^A_]f     H fD   _(f.     UHAWIAVE1AUATSHHdL$%(   LeIHtLpID$E1HtHEu RH)L(   聚HH   I|$w1HH@Lw   HH?Lw   HH?I|$w   HH?I  H蕨HHtT xt@xt#HEdH+%(   u5H1[A\A]A^A_] HXfD  KDj'f.     UHAVAUI   ATISHdL4%(   LuI]H   I|$(Hv1HH>L7H%   HH>I   ~v   HH>I|$dv   HH>A|$ Iv   HHy>I   HJHHtY xtExt(HEdH+%(   u:H1[A\A]A^]f.     HfD  &f.     UHAWAVIH:  AUATIHuSHHdL<%(   L}I׺)   谀   H   I$   HMu1HH=I  4u   HHd=I$   $   HHG=I$   #   HH*=H}#   HH=I   HHHtQ xt=xt HEdH+%(   u2HH1[A\A]A^A_]HfD  _$f.     UHAWAVAUI   ATISHHiu dL<%(   L}IDp蟖H"  HLL)H8s1HH(<I   s   HH<I|$s   HH;I|$ s   HH;A|$*@@s   HH;I|$-k"   HH;I   HlHHt[ xtGxt*HEdH+%(   u<H1[A\A]A^A_]f.     H(fD  :#f.     UHAUATSHdL$%(   LeI@   5HEH   H=)w H5l aHH   H   LmL1LH:H}о   c   HuHMHH    xtdH}ЋxtKHEdH+%(   u^H[A\A]]f     Hyu Hk    H 01g 뮐H5_ H=k }!H5 H=k y}f     UHAWAVAUIATSHHH}	   L}HuLuHULELMdL$%(   LeDe 豓H\  H}Hq1HH?9HEH  p   HH9I}p   HH9Ic}Xp   HH8H}p   HH8H}p   HH8Lsp   HH8L[p   HH8IcCp   HHs8HEHH(  @HHtW xtCxt&HEdH+%(   u8HH1[A\A]A^A_]fD  H fD   fUHH H=5w dH4%(   HuH5 ^Ht4HHEt$H}1脠HH    xt{H=
w H=w HtxtFH=w HtxtYHEdH+%(   u31D  f     f     {!ff.     UH HAVAUATISH?H=!w dL4%(   LuIH5 HD]H   HI~      ӐHH   I|$]1HH`6I|$F   HHF6I|$,   HH,6Ic~Xm   HH6Ic~m   HH5Ic~m   HH5LH趞HHtr xtYxt$HEdH+%(   uDH[A\A]A^]     HEdH+%(   u HH[A\A]A^]]D  S|GfUHAWAVAUATISHHxHFLuHMLELmLxdL<%(   L}L} HL  HH H`Hk  HhH`LHHpHpHhx  HuH:  )   HpwHpFHuLHHpHpxh  HCH8<HuLHHE艕HUxD  HCHxHxLHHEQHUx  HCHxNLLHHEHUx   H{HtiH-fLLIHAxA   HSH{ HBH;z sPH)XLLHH觔x   HEdH+%(      Hx[A\A]A^A_]@ HSH    HHpHpGD  H H H H L! HEdH+%(   uHxH[A\A]A^A_]kfD  UHATSH dL$%(   LeItp   HU蒌HHF  H=Ow 1HH2L   HH2H}   HH1H5 Q    &HH   H=w ~1HH1Li   HH1H5 H=w XIHt0Hyt$LHGHH    xtNxt!HEdH+%(   uUH [A\]f     HEdH+%(   u4H H[A\]f     H5f H=bb t UHAVIAUE1ATSHHFdL$%(   LeIHtLh(   HH  I|$P:h1HHm0I$H   h   HHM0Lh   HH50ID$Hxg   HH0I|$g   HH/I|$ g   HH/I|$(g   HH/I|$@g   HH/I|$Heg   HH/ID$H HxDg	   HHt/Ic|$`*g
   HHZ/I|$Xg   HH@/I|$0f   HH&/I|$8f   HH/I  HݗHHtT xt@xt#HEdH+%(   u5H1[A\A]A^]D  HfD  WfUH HAWIAVIAUATL% SH   dL,%(   LmILE蚈H  LH+H=Ov I1HH.L   HH.Le   HH-L   HH-H=#w LTIHt0Hvt$LH脖HH    xtSxtHEdH+%(   uQH[A\A]A^A_]HEdH+%(   u3HH[A\A]A^A_]+ #H5 H=^ p9@ UHAVAUATSHdH%(   HE1HtMHL-\  {w:CIcD L>@ HKH5%w    H HHu@ HEdH+%(     H[A\A]A^]H{gH{^HHu@ H{GH5 w 1ҿ   L5 w Lcf     IL$IT$L   M$$MuHH$_    H{HS   H5G w jL5; w Lc @ ff.     IL$IT$L   M$$MuHH    H=v ̏H{bHHv H H{ ?H{(6HHZD  H{HH;vfD  H{H{H{ HH	D@ ff.     UHAWAVAUATSH(H=v DndL$%(   LeIL~(H5 QH  HIrv  AD$  ID$0HE   裄HH  A|$-1HH0*A|$   HH*Ic|$a   HH)Ic|$a   HH)Ic|$a   HH)I|$ 讱   HH)L薱   HH)H}M   HH})Lb   HHb)Ic|$pa	   HHH)Ic|$t`
   HH.)LHHH    xtrxt=HEdH+%(   u]H([A\A]A^A_]    ID$(E1HEj    HEdH+%(   u H(H[A\A]A^A_] GrfUHAWAVAUATISHH(=v  dL4%(   LuIt<HEdH+%(   @  H(LHH[H=Dv A\A]A^A_]F\fD  DoH=\v H5m6 OIH  HDp  EE;uCECE   HH  I|$药1HH'Ic|$XF_   HHv'Ic|$,_   HH\'Ic|$_   HHB'Hc}^   HH)'Hc}^   HH'Ic~^   HH&DAfeO   HH&1fA `@DO   HH&Ic$   g^	   HH&Ic$   J^
   HHz&LHOHHts xtZxt%HEdH+%(   uEH([A\A]A^A_]    HEdH+%(   u H(H[A\A]A^A_] f.     UHAUI   ATSHdL$%(   LeIH  I|$ H\]1HH%ID$H   >]   HHn%ID$H H8nH  ]   HHB%ID$H H   \   HH%I|$(\   HH%I|$0\   HH$I|$8\   HH$I|$@\   HH$ID$H8i\   HH$ID$HxK\	   HH{$ID$HcxX-\
   HH]$I|$H\   HHC$I|$P[   HH)$I|$X[   HH$ID$Hx[   HH#ID$Hx0[   HH#ID$Hx8[   HH#ID$Hx@g[   HH#ID$Hx`I[   HHy#ID$     #[   HHS#ID$   @Z   HH+#I|$`Z   HH#ID$HxHZ   HH"ID$HxPZ   HH"ID$Hc   Z   HH"ID$Hx fZ   HH"ID$Hx(HZ   HHx"ID$   W   HHW"I  H(HH;   x  xt.ID$x   t6HEdH+%(     H1[A\A]]HID$x   uI    t   |HH   I|$ pY1HH!ID$HxUY   HH!ID$p\H   q-   HHa!I   H2HHtI xt5#H fD   	fUHAWAVAUIATI1SHhdL4%(   LuI2H)  IHu x   I$      I>jLHHu LE1E1Hދ PZY  H  HCHC    HC HCH9  Lc M  	IHz  I<$T:H5f LIHOAxA  I|$   軕IH,  ID$Hx:H5f LHHxHxx  ID$Hx 9H5 LHHx蹀Hxx	  ID$x*@@VH5 LHHxrHxx  I|$w(H-H5A LHHx/Hxx  LH5 LAxA  Mt$M  I|$ H   ?:=  8H5 LIHAxA  ID$Ht`H@ H= Ht!H/u y	    H   H   H5 LIHKA$xA$   HC LLH@PHCHC *6AE xZAE mLHCH9eHEdH+%(     HeL[A\A]A^A_] Hk  W@ HH9C f     L8W 0     L- H}HxPA~4 I$Hx
  HEAV(rAv(9t
BvIt$HELuHVHH)HxH;F    jXHx6H5 LIH}AxAuLRI|$ H    H0 H ! HT L i Hk IH)HxGfD  IFI+@ H)u Hj 101WIfLSH5 H=L P_H5q H=L =_     UHAWAVAUATSH   H$ H(Hu H HLcIE|$IcdL,%(   LmIHH8HDH	  L1HA   wHE~(@ ff.     K|1TJIE9}H5u H=U !=HDHH5b H*	  H11H蕉AŅ  H=0 !Hv H   wH*Hv H   wH= \!HteH_*HHtUH(u 11HH8=IHt3HHH5 {   AE xAE   H=v Htx  H=v HtxuWHبu H   H= H81 A       H=v LH5 jzAE xAE uLIH=<v H5 ?IHt3H(at'L1蚁HHK   x  1'   H=v HH=v  AŅ  H=v H5y r?HtHg     =v  tH=Tv aq  E~#INdf.     I>IM9uHG|HEdH+%(   |  H(  D[A\A]A^A_]    H9u H   H~ H81t9E~INdfI>ItM9u{f.     H=v H5 Hv     b>HtHf  l  H=v H5a Hv     &>HtiHYf  tTHuv H  H Hjv Hu5H5 H=G Zf.     A
fD  Hu H=v    H5 v fP=H  HH^|  HH`Hiv H*v H=v H5 ?=H4  HHw^  HHH"v Hv H=Dv H5d <H  HH(^  HHHv Hv H=v H5 <Hv  HH]_  HH#Hv HUv H=v H5 R<H  HH]   HHHMv Hv H=Wv H5 <H  HH;]  HHHv Hv H=v H5? ;HY  HH\B  HHHv Hv H=v H5 e;H  HH\  HHGHxv H9v H=jv H5 ;H  HHN\  HHH1v Hv H=v H5~ :H<  HH[%  HHHv Hv H=v H5? x:H   HH[   HHjHv Hdv H=}v H5 ):H   HHa[tnHH?H`v H)v H=2v H5 9Ht6HH[HtHv _ L1Hv     Hv     FHv     Hv     Hgv     )HOv     H7v     kHv     Hv     Hv     NHv     Hv     XH5v H=:1H.v HqH5 H=A RUf{AH5j H=A (UNf     UHAWAVAUIATSH  HHHL dH%(   HE1ǅ    ߆HH  ʆIH  HBtHHH5 IHrA$xA$
  H   HxHH5SQ IHqA$xA$	  I} *H5<* LIHqA$xA$	  I}(]*H5 LIHXqA$xA$C	  A}GH5 LIH%qA$xA$ 	  A}wGH5 LIHpA$xA$  A}XDGH5b LIHpA$xA$z  I} )H5 LIHpA$xA$7  I}^)H5 LIHYpA$xA$  I}0+)H5 LIH&pA$xA$  I}h(H5 LIHoA$xA$n  I}(H5 LIHoA$xA$+  HH@0H  t  W     荓IHD  HI  IWHLH51 L5oAxA"  I}8	(H5h LIHoA$xA$  A   肕H5e LIHnA$xA$  I}@'H5mi LIHnA$xA$  蠔IH?  I}`['H5] LHHRnHxz  IE`H`Ld   HHI$   `LsHpH5 LIHmA$xA$&  HLH5^ mAxA  Au\I   MHH5 IHmA$xA$  HH8HHH5 S IH?mA$xA$  HH L PH L PHTi H PLH HL<H H LH5@ Hlxv  M   M  HA        L H H
  莐L HH  M`I8 K  HE1LL  H   H  H54 HHH lH x:  HIT$LA   NCH(H= Ht+H@ Ht"H[u z	   H   H  H5 HHH rkH x  LEHHS"x  HIIL;8
  HH  I<$#H5d HIHjAxA  I|$#H5d HIHjAxAf  A|$1H5 HIHjAxA@  A|$@1H5a HIHJjAxA  A|$@U1H5c HIHjAxA}  A|$@1H5d HIHiAxAS  A|$"H5T HIHiAxA+  L L| HI$LA   @H(H=G H*H@ HHu z	 Hk   I  4IH	  A  HM  LMHLMHI1HLo@ HLMNIT$HHA9  MML?fD  L L LB L L Ly L6 L L Lm Lx* Lh Hk  $@ HH H89 H(Q Lv L L Lk L L L HLHHH5) HfHxu  HLH0ۺHH5 IHfA$xA$m  A     A   <H5 LIH\fA$xA$7  H t   c-H5 LIHfA$xA$A  HH Lo LPH Ln PH Hr PHHp "H A     I}HHtI}P [  HA>   H8HtH1+DHHxpM   DxM  IcL-IH  HEMHDHppjLrHH5 HHdHx  M   MtTHEMDLHp`LHH5 IHdAE xAE   LegHEdH+%(   0  HHe[A\A]A^A_]@ M   M  Ic,IHSH5 H=3 qFHtƅ`bHat cHt rHt oHt sH t yH@t iHt AHt BHt EHt xHt gHt hH t DH@t tHt mH    HH5V LIH cA$xA$  HA   @   HPH8H5 LIHbA$A$L2D  8H5 LIHnbA$xA$  A   8H5 LIH8bA$A$LfI  H5 LHHaaVHrID  I   H5{ LHHaH*D  蛅HH  L M`    H~ L H y    L L L L Lx Lh> HXy LH L8 L( L  nH@LL_f.     +H5 LIH&`A$xA$   I}PH5 LIH_A$LA$?Lr2D  L` HPM   M.1贃HHH5 H=. AD  E1L JH5 H=. AH5q H=
/ AH5 H=. AH5 H=. zAf.     UHAWAVAUATSH   H$ H   H$ HxDwXL   LHH:IH`HHxdH%(   H]1   HHHHLQ
H  ILH5\ Hc]MMMEHHP H   1   H=v 赆IcU   HHHH#l  H=v H5v #HHY  HDI  1ۿ@   VHHn  HSZ/D L1H	HHHi ʚ;Hp1I)Hiu LhH8H=;v IH1HHL   HxHHHH =wLcIcHy  d3H55 HIH\AxA  Hp03H5 HIH\AxA  Hh2H5 HIHw\AxAo  L2H5V HIHG\AxA2  HH5 HIH\AxA  LH5d HL[AxA  Mu(A   M   L   D  AN,AF(}  M,tLF  L~If8IHts IvLHQ[AE xAE \  M6MtbIV8wIcv(HAV,L THAF8u	H  h1IHuHDLAM6MuDH  DEwIHH5 E1)IjMtZLH5 E1)HHt+H!HAǋxu A$xA$m  E9  Hx  HL!a  HHaHHU   xR  HxuYf     HEdH+%(   i  Hx   [A\A]A^A_] H=v H5 5HHtHq@tmHH}H5h H=) ;f     I I4Hu H H8\IV8VAN,AN(G@ Lx L8IXEoEwDHHRD  I}8/f.     .H   HHp.H   HHh.H   HLA   .H   HHiH   HH   H}Mu(MHH5 A   &IoMdǅ   A	   LH`HxHHHLHDhHH;LLLLCLsLfǅ   A   A      H5 H=& 8)   HH=Fv L       LH1j*H5#v H=& 8H5m H=& 8@ ff.     UMHAWIAVAUIATISHHH݂u dL4%(   LuMIHHH8L8{O  =v  t>HEdH+%(     HMMHL[LA\H=^v A]A^A_]~fH=v H5v Hprocess_Hv Hs_event Hv IH   HG<   @   %NHEH  LHLLLHILVH}1HH}      HuLU\HH    xt|H}xt[HEdH+%(   ufH[A\A]A^A_]D  HEdH+%(   uCHLLHL[A\A]A^A_]Jf.     f     zH5 H=## ~6詤H5/ H=# f6fD  UHAWAVAUATSL$ H   H$ L9uH8     dH%(   HE1HHA1HH}   H0ǉi   H`E1A1      IH      p   Hĳ HH`Aƅ   HLȾHH1Hǅ @  Hؾd|q   AH%H`LGd fD  AHEdH+%(      H8A  D[A\A]A^A_] } @  H+DHcH'H;.]D  Lcq{@  @  HD+Hc҉HH;	f.     U1HSH(dH%(   HE1z11fUx+Hu   MۉE;}HHMtHEdH+%(   uH]    Ef9±  UHAWAVAUATSL$ H   H$ L9uH         H H0,HdH%(   HE1HH0dÅ+  L1HHǅ0    Hǅ8    LHHǅP    H<H0AHPH   A   E   H8HuH 4'uH       L HLH0^LH8gh  H &   ET@     ,LH)IL9~   LHHǅP    EG1Au;H0oHEdH+%(   K  H@  [A\A]A^A_]     AO   H HcH>fHyu H    01DH3  Hxu HЯ    01Hxu H    01H H, H# Hi~ H, 뗍@weHT HcH>H H`xu Aؿ   H 01H Hn H H} H ff.     UHAUATISHdL,%(   LmAH5Ԯ pHt6HHD}HAbHEdH+%(   u5HD[A\A]]Hwu L   Ho A01)f     U1HSH8dH%(   HE1v1ɺZ   E7zXfM1fUE    x+Hu   MˉE}HIHMtHEdH+%(   u6H]     E9Et   @ Ef9Eu1eD  UfHHdH%(   HE1wHEdH+%(   u1# UHSHdH%(   H]HHHt>HC    H;Ht@H    HEdH+%(   uH]1fff.     UfInHAWIAVAUIATMSHH   HEHXLpHEdH%(   HE1HMEH? P  L1Hǅh    HuHMH9d  HMH`LP, LHuUIM,H)LhHEH9E   1LUI?HuHE    H)Mt IHpH`LuH9HFHEI?HuHxcHx|lHxLPH 1LIHtu 01HXLLPIHEdH+%(      HĈ   L[A\A]A^A_]     Lh    [IHt-AwH7HIu7HUHEE1Hsu H 101-IaLH
 1HHsu 01vfD  UfHnHAWAVIAUIATSHXHUdL$%(   LeMEfInHuHMEH    H1HuHuH9r+   D  HEHMIT HULH)HUH9MsWI~HuHUHHtHHM1Hru 2PH 1HMLEHEZYHUdH+%(      He[A\A]A^A_]fD  9IFHt*HfHH/u0HUHEHEHaru H 1011HcH<ru 1H12H g1Xf.     UfHAVAAUATSH0dH%(   H]HHE" HE     )E1HUHu}   k#Hu]h8u	}0tHqu H    01HUdH+%(   u?H0[A\A]A^]D  A~"1}" u΋ED     EUHH0H}؉ЉʈUԈEdH%(   HE1HUHEHѺ        HHEHEHUdH+%(   tU   H5 HAVAUATSH0dH%(   H]HK   L-tu CAD    HU'xIHcIHtoA        f     <$t|ADA9~/HHc3<_u|3_uݸ.   ADA9    HcL D  E1HEdH+%(      H0L[A\A]A^]f.     DL3LCD DoHt3DCD DZ@LEHMUHunHuA>_UHMDLE	fHN UIHAWIAVAUATISHHMdL,%(   LmEH  M9j  EE    1L5 E    D@ D9t4A$B<3wIcL>fHcÃAfD  IM9uHcL LHUdH+%(     HH[A\A]A^A_]f     HcI<A       E?  AM  HcÃALA6  EmD  HcLAa  VMD  At
A  AD$Hru    A  A   @ At
A  uHcHc 1LLM)DEHcdVDELMD  Av  HcE    A)    AN  HcA   A(x     AAEA[ AtA   G    u  EA   &fD  M  uAI<1HcH%u LM)HHe DEHcrUDELMËEtfHHL DEHELMLeA܋]DmAf.     IcHU1D)LHcUAAsDDELeLMDmEE    [ "Mf.     1Nf     uHcH 1LLMA   )DEHcTDELMu1H LMDE)HciTDELMËEHH? DEHELMLeA܋]DmAfff.     IcHU1D)LHcTAAsDDELeE    LMDmOuHcH 1LLM)DEHcSLMDEuHg 1LMDE)HcSA$LMDEHcL:f.     UHAWAVAUATSHdH%(   HE1H   A)   Ic_IH   L!Lt@LHH   IA  tAH1DE1LL)Ht\HEdH+%(   uYHH[A\A]A^A_] 1A   DHLrHtH H @HT@ HhB1/f.     f.     f.     f.         UaHHdH%(   HE1@wH @HcH> 1fD  HUdH+%(   Q   Hm     HT     H     Hյ     HF%     H
     H |@ Hҁ l@ H \@ H L@ H <@ Hn ,@ Hv @ H[ @ Hv @ HF @ H @ H, @ H @ HV @ HҞ W    UHHHOdL%(   LUIHwH9   LAH<_   I!B!1DXA	   DXAvDXAwEHHOI9r7Hk>IIr+H9t&HAH<_uHOHtHI1   HUdH+%(   u@f.     HO1     WHf     HOI9r0Hk>HG    UHHHOdH%(   HEHGH9tLIE1A u   0	v   HUdH+%(     D  HpHwH   M0H9tHA;_   HwE8  HzIsI;f.     8_   HH9uH# 1IA1HI	MYIQ_f     HHGH9@A A   0	)C H9A00<	w[IHHwI9HHHHH9uHH)H9H4M f     H9tA<0_uHFHGf.     HHt>L)LL^H)H H MIA1IQIA    UJH  ff.     UHH dH%(   HMHH(Ht<   H9Q0sHUdH+%(   u& HUHM8HMHUHQ(H)Q01f.     UIHAWAVAUATSHx  HdL,%(   LmMMHujI9s-   HUdH+%(   	  Hx  [A\A]A^A_] HHHLLL8LLM1    H   s  HN  HFHN	  ofHfoHfdfof`fhfofofqfifafo)fofq)fafi))H  oGfofdfof`fhfofofqfifafo)fofq) fafi) )0HP  oG fofdfof`fhfofofqfifafo)Pfofq)@fafi)`)pH  oG0fofdfof`fhfofofqfifafo)fofq)fafi))H~  oG@fofdfof`fhfofofqfifafo)fofq)fafi))H  oWPfdfof`fofofhfofofqfafifofq) fofafi)) )0H  oG`ffofdfof`fhfofofqfifafo)Pfofq)@fafi)`)pH;  oGpfdfof`fhfofofqfifafo)Mfofq)]fafi)U)ELLIE1HHAH   Hǅ   Hǅ  LLLIA$      E1M)Z    aHcH  HH  L  HIIL9  $   HL)HH  I$Mɸ   LA   IELLC   I9IFL9LCMM  ;G<gG<	4  HcWIHpunycodeAE{IE I@I9LHI}	LLHL[3LLHLCD	-IZ
I)L9HI| HLH3HLAD }LSf.     LHALH)HVH   ~ffdfof`f`fofofpNfqfafafof֜fpNf֌fofqfafaf֔fpNfք@oHHHPL9PTHPL97THPL9THPL9THPL9THPL9TfD  LLLHLLIHpunycodeAE{	   IE MfILr1LVE1IHArHH zH-   = ZI   MH    H)Hp   LH    L`LHLxLhIMLxL`A   L1LpLhH1IIIIT H  v?HD  ff.     ff.     HHI$HHHW>  wHHJ&1LHǅ   HHIUHLLJ4LE10f.     =  vI=  vb=    HH9<LL)HKL wIfD  ǃ?IȀA@9fD  I@9ǃ?Ȁ?Aπ@y}@ ÉAÃ?IA?	A?~ @D			؉71袶fUHSHdL%(   LELG(Mt6HG0HNHLMHVH>HEHFHuHEHC(H)C01HUdH+%(   uH]/@ ff.     UHAWAVAUATSHHdH%(   HEȸ   @  IIIHj  L!M  "LjIE    Ht  1IAH    AB<	vB<  BARJЀ	  IKDHSHAH    AJA<	vA<M  AAJq@	]  IKDHSHAH    AJA<	vA<  AAJq@	  IKDHSHAH    ARB<	vB<  BARJЀ	  IEI   IAE  <W  <8  Mq@?>  ?%  	H'  HZH}   EHuHL]LUE\DMLUL]H}      1L[    L]LU L]LUHMt?I9   It I)HMh    tUAU   IHEMtMtBAE "IHL)I1ff.     HUdH+%(     HH[A\A]A^A_]ø   <  <.         f     JwDS    q@wύDfD  q@wDfD  JwDE    E1E1H19f     Dȸ   HH}   L]H)H4LUHDMDME\LUL]Av  <  A
t+!E   t   A		E   /n   H<vr<   Mq@?w{}w@?wnuDFA?w`<  <uwO?  %   	ȉ  D0   J  Mq@?wu~@?   HGE\1E0   sHUIU H|I|I}LHH)H)1ANN9re\   A\A"   AA^DM   r   E   <   <MQ?H&4IIII<t~<u	?%   A%  DD0   H9    DHڸ   IIEAE DADbE"w}%oHgTfAT'聯UHHHwdL%(   LMIHWH9   LA:   HBHGH9   ADH<_   I!B!1DXA	   DXA   DXAwSHHWI9rEHk>IIr9H9t4HAH<_uHWHtHAHIHuf        f     1I	1HUdH+%(   uA     HW   D  WHhfD  HWI9r0Hk>H`4@ UHH@dH%(   HMHtBHA(HtHy0     ?HA(Hi01HUdH+%(     f.     IHQH   IHyHuHMHULELMPHM  HUHEHH9   Q r  M  Hy( LQ~ALELM`Aq HLΉULUHA    HM)EAHMLUfoEЋULQQ     Af   fD        H= Hq(Ht)H9Q0rAЃsX   t?@>HQ(H)Q0fD        H=5 D     H=" f.     LLNILLDLDL)D2H)AArA1ANOD9rqfD        H=̆ +DDB|B|@UHAWAVSH(dL%(   LEItI@(Ht{Ix0       kfIxIpHH9t+IHHPIP<_tlHЀ	va<wHH9uI@(HtIx0vfoM  I@(Ih0A    1HUdH+%(      H([A^A_]f     H9H)HMLEHrH1HEHILEȅt-+j     ?I@(Ih0f     IP(HjI@0HMLHLEHExLEHEI@(I)@02vfD  UHSHHdH%(   HEHG(H   H0    'HW(HBHG(HG0HHG0H   DG8I9  I)I   H   B_f    1H}H    HG(Ho0H})E)EKLMIQ(HtTH}HULMHI9A0rjHU     tE@  Iq(I)q0f     1HUdH+%(     H]D  Hukff.        f     HtAaDBHG(Ho0    Hvfo B   HG(Ho0yf     B_HG(Ho0]D  HEHzHHHLHLH)HMH)у1AЃNN9rELLLfL> ff.     UHAVSH`dL%(   LMIt?IA(HtIy0     ?IA(Ii01HUdH+%(     H`[A^]IAII;AtsII<GuiHHuIyHuIALMLLMIA(l  HuIH[  HLUtJIy0wkff.        jfD  Iy( t!ULLMALMUA)Q8@@ HEdH+%(     H`L[A^]A     for<IA(E1AY8Ii0HSIA(AQ8Iy0 p 'IQ(EA8HBIA(IA0HIA0M  II   H1AaDBIA(Ii0HIA(M9  IH  Iy0,   f0IA(AI8Ii0HQIA(AQ8Iy0 S Ht Iy0fo  IA(Ii0A       HB_H]f1IA(       HIi0H LML]LU)E)EZGLML]LUIQ(HHHLML]HULML]LUHUHI9A0     tE  IQ(H
I)I0IA(@ Hfo BIA(Ii0HA   IA(eD  LIVL)بuIAA8I9oIAA8AA8I9uWHEHHtHtHrHHH)H)ʃE1AJ J9r)IVHIy0>   fIA(Ii0EȋttIQ(tftIQ(UHAWAVATSHĀdL%(   LUI?  IRIBH9   EZ IzAHrIrAKDAJ      Ae0  A@~jAI$waH HcH>HH9tED  LIMJFDA_t	  AHЀ	v
AaAwLH9ufff.     IB(HtIz0vpfo  IB(Ij0A   1HUdH+%(   d  H[A\A^A_]fIB(HtIz0 t  ?IB(Ij0뽐IB(Ht8Iz0w   f     fox  fo} @	IB(Ij0A   o AI3A   IA uqAR   IB(Ht2Iz0 w _AIB(Ij0    AB DXEZ IrIB@ ff.     HH9@ IzHJIJ_  z@	varHH9ueD  AR  E	  IB(H  Iz0  &IB(E1HPIB0IR(HIB0Hmut L׾   IB(Ij0Lx	LxYE	  AIB(E  H  Iz0 ' {IB(A   IZ0HHSIB(IR0H *LIB(Ij0LxLxx@ IB(E  H  Iz0  {IB(A   IZ0HHSIB(IR0H} (AIB(Ij0!  1 IBI;B  IJ<E  HIBIB(H  HIR0H )IB(IZ0HHSIB(IR0EH }IB(Ij0f     H9|nHrIR(IrHwIz0 -IR(A2HBIB(IB0HIB0/HmB?AIB(Ij0EV  IB(HtIz0 : {IB(Ij0A          LLxL  LxEEIBI;BbIRHHIJ<T  <Ui<S:IB(Ht(Iz0f  {@ IB(Ij0A:    IBIRH9tIJ<Et	  E1MzH9tMIR<suCHHuLLxIBLpvLxw	  H}Lpe	  HuLLpLxKLpLxMB(n  Mt!Iz0foI A IB(Ij0A      H5E LLxLx0@ EH5-  LLxH-  HE1QLxAIR(E  Hm	  Iz0 !{IB(A   HPIB0IR(HIB0H[IB(AIj0HIB(u8IrIB1fH9   IB<0E   HIrIB(HTIz0  ]|HH9D  LIMJFDA_x  AHЀ	vAaALH9uIB( Ht(IB(HtIz0A,   fD8IB(Ij0   LHpLxLxE"E#HpIrIBH@ Ht(IB(HtIz0A,   fDIB(Ij0   LHpLxgLxHpE
HE@ H
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  IR0E1u E1H)H  H1ff.     HH9  <0tHH)H-H9  H0H1>     ff.     ff.     ff.     0HHHH9  Hx@	vۍx@WHHH)H	  H1HH9	  <0tHH)H}H9g	  H0H1Nfff.     ff.     ff.     ff.     ff.     0HHHH9y  Hx@	vۍx@WHHH)HHG  H1fff.     HH9&  <0tHH)H  H9  H<0HLE1;D  ff.     ff.     ff.     0HIHH9  IDXA	vDXA6  WHIfIB(HtKIz0  {IR(Ij0HBIB(B&IB(HPIB0IR(HIB0ARv  L׾   LxLx8IB(HIR0.H9A-   = |E\
  
    \   \  E   IB(HtIz0  'IB(Ij0HuLLxHx   H5 d@ Hd  IB(HHIz05 trueAIB(Ij0E1fH}    1H    LxDhHp)E)E-8LxIR(HyHpL`HpHxhL`HI9B0HxHpDh  $  tE@G  IR(MB0H2IJ(I)MB0HAz< ALhLpHxHxLpHLhHL`LxHhHpHH9xHpHhHxDL`HxAIR(I)R0&IB(H)Iz0n0x  fIB(HxIB0Iz(HIB0H9EHxLpDhLpHxDhMB0HIJ(IJ(I)MB0HIB9H9   |e   HLLxIRbh@ IB(HIz0fo  IB(Ij0H%Iz0 j ,IB(IZ0HHSIB(IR0)EIB(H  Iz0 ) &IB(Ij0L׾   LxLxIB(HIz0 fals@eAIB(Ij0_A   A   DHEHHLHLHJHHH)H)1AN N9rLLxLx7IB(HtIz0 # (IB(Ij0A: u1IBI;Bt#IJ<EuHIB   H5 9Ht&IB(HtIz0,   f8IB(Ij0   LHpLx;LxHpA2HgMt}IB0HMLMLpHUHuLxH}HE7LxHMLpIB0HIR(IR(H)HIB0tH f: IB(Ij0L׾   LpLxvLxLpAIIBIRH9tIJ<EM%IJ(HIz0t,   fIR(A
HBIB(IB0HIB0uIBIRH7B?IB(Ij0eMuE1>LLxLxE1A   DftIt   	   H}   1Lj    LxlLxHcE\0      LLx]n   r   zELLIR('t/F^\@u   KLfLIR('   $ UHH dH%(   HUHuhHBH;Bt^Hr4@LuJHHzHuHUHBMHUtvHr(MH   Hz0w        @Kt"HEdH+%(      H
  fD  HHBHEdH+%(   u_1HfD  HEdH+%(   u?HuH$@ fox HB(Hj0   HEdH+%(   uɉ]fff.     UHAWAVATSHĀD?dL%(   LUIE   AB AB =  wCIBIrH9   MJHxIzEAHwvL IcL>fIB(Ht,Iz0   fo  fo @	IB(Ij0A   1HUdH+%(   	  H[A\A^A_]fIB(HtIz0v0foH  IB(Ij0A   fIB(HtIz0 u   f      ?IB(Ij0zfD  HUIzs   DpLxhLxDpIR(}  HyIz0vfo IB(Ij0X L׉pLx8OLxIB(p w  H  Iz0#A::  fD IB(Iz0HHWIB(IR0H <A:IB(Ij0@  1 ff.     IBI;B2  IJ<E$  HIB      IzHUs   LpHx0HxLp*HuLxHE    HE    :LxMB(  MIz0#fo; A IB(Ij0     H57  LLxHf  HE1LxA\Aj RfD  IR(H  Iz0 <IB(Ij0LDpLx  lpMLxtLIB(HtIz0H  as IB(Ij01LLxLx    IB(H8Iz0  >AIB(Ij0 H9HHIJALA<vat11LpLxxLxp E"E&  IzHUs   pLxMrLxpHuLLpxHE    HE    xLp  LeLu0  LL	"   H5c LLxHxHu>IB(    Ht&IB(HtIz0w,   f0IB(Ij0LHpLxFLxHpA
HY@ IB(    1LHhDpLxHhLxDpHIR(*=     HS  IR0fD  MIB0HMLMLxHUHuH}HEoLxHUHIB(I)R0IB(HAz< vLEMi   H5Z LLpLx	LpfE11H9    H})E   Lu(H}.HxHuHHx   H5
 @ LLx  LxdAy@ IB(HIz08A::  fDIR(EHBIB(IB0HIB0EHB?IB(Ij0L׺   H5` LxLx   H5` L׈pLxCLxpW  S=  MHu   LLxYLxILL	tD   H5N` LLx&HxHuLx   H5 LLxLEf    1H    H})E)E&LxIR(Ht8H}HpLxI9B0|HpHuIB(I)B0   H5 LLxJo<g   H5>_ L׺   H5"_ Lxfff.     UHAVSH@DdH%(   H]HE   HSHKH9t|LJHCHMLK<LMIHU@}ĽDEHUHLMHM   D[ ESDS A     A@<%  H5 HcH>HC(HtH{0v0foH  HC(Hk0   1HC(HtH{0 u(   HUdH+%(   &  H@[A^]     ?1HC(Hk0    HC(Ht(H{0vfo؞  foݞ @	HC(Hk0   1D  HK(H^HHEHMHH9C0VHuH}HEHU1HS(H)S07fMtHS1HC DXD[ 1     HC(Ht,H{0  &DHC(Hk0E
  LKHKL9t>HCB<Lu3IHuH{DELKrDEЅ  HuHz  ARt2HC(Ht)H{0^ mut HC(Hk0 ff.     HH*f.     HC(HtH{0  [HC(Hk0HDE}A  HC(HH{0  ]HC(Hk0fD  HC(HcH{0  *HS(HC0HJHHK(HC0AP  HiBmut HC(Hk0H5  HD'6HC(Ht"H{0 " (;HC(Hk0  1f     HCH;C  HK<E  HHCHC(H  HHS0H )HC(Hk0HC(HtH{0 dyn HC(Hk0H5{  Hsj HCH;CHS<LHHuH{HC  HMH   H5)Z HHMHuH    MT  HuH{HMHUDUD]蒺  HEH;E  D]ASA  *  H{( DUu~EЉS CHHC    D]DU)E^foEDULs    D]DS C#!HC(HS0S@ Ht&HC(HtH{0,   f0HC(Hk0HHUHUЋHARoHC(=HAt   BconsfDIHC(Hk0;      H=QX HK(Ht;H9S0Wփ    tDD@  HS(H)S01"HC(HtH{0	A;   fD HC(Hk0   H(HH{0  ,HC(Hs0HHVHC(HS0   H=pW +      H=ZW    H5IW HkG]      H=9W H7LAIH1HtHtL)4
H)σ1AɃNO9rHDE   H5+ HպDEЃO{DD|7|1||7f|1mff.     UHAWAVAUATSHHdH%(   H]H  HCHsHH9  H{ADAUg  HHKH9  A   <K  HAHCH95  |C*  HHC(HKE9  HD  HS0A   HV ff.     H   Hextern "H0HC(Hk0LpLs(]fD  LHLHS(HC0LL)HS(HC0H  Htb-HC(Hk0LpLs(IIOM)  HL_   HM%HMHI  II)M&  L9c0lA   HEdH+%(     HHD[A\A]A^A_]ÐAK  Ls(Mt-HC0HvAfn  AF(fEHC(Hk0u4HCE1fff.     H;C   HS<E   HHCHC(H   H{0 L )HS(HBHC(HC0HHC0uHCH9Ct
HK<ut}HC0H	B -> HC(Hk0HEdH+%(     HHH[A\A]A^A_] Ls(Mff.     uHCH;CtHS<uuHE1HCfD  Mt&HC(HtH{0k,   f8HC(Hk0H]H3IHCD  E1
HC(HH{0 unsa@afe HC(Hk0LpLs((D  E1     HuH{賴HC(Iƅ   LmM   H}    HMET  H  HBHS0fMHC0H]A"   fEHC(LpHC0Ls(HHC0yfML9k0!LLHOLs(HC0ML)Ls(HC0    Ht H{0fo  HC(Hk0   HtH{0wAHH{0 unsaA   H @afe HC(LpHC0Ls(HHC0H`Hextern "IHC(Hk0LpLs( HtTH{0- unsa@afe HC(LpHC0Ls(HHC0Hu=f.     H*NfH>ufff.     UHHdH%(   HE1HEdH+%(   u1nuf     UHHdH%(   HE1HEdH+%(   uɾ   +vufD  UHAUATSHH8dL$%(   LeIuwHGH;GtmHOBu[HHGA$ 7   HG(HtH0           HEdH+%(     H8[A\A]] It#1Hyt1A$1f.     H1HHCNtHC(HtH{0 t <HC(Hk0E1u' HCH;C   HS<E   HHC   D  LoM  HuHUӯUH  HEIL9E  Dk AM  D  LC~CH{( CK LHHC    LE)EKLEfoEDk     LCCf     Mt&HC(HtH{0w,   fHC(Hk0HTI ?HG(Ho03fD        H=M Hs(Ht-H9K0Aȃs`   t?@>HK(H)K0f.        H=jM 뫹      H=WM 똹      H=[M LLNILLDLDL)D1H)AArA1ANOD9riDDB|B|T8r     UHAWAVAUATE1SHHHDdH%(   HE1Eu* ff.     HCH;Ct6HS<Eu,HHC1HUdH+%(   @  HH[A\A]A^A_]Mt*HC(Ht!H{0'   +  @ f8HC(Hk0HuH     HCH;C   HS<p   HHCHC(}   Hg  H{0     <HC(Hk0E  HuH{购LC(8  Mt`HC0HMLMHUHuH}HEuNHMHS(HC0HH)HS(HC0HtHv) =  B f
HC(Hk0H[f   fD  } uI\s    HC(HtH{0 t >HC(Hk0ǐHH{0v,   f0HC(Hk0HC(HH{0 l ?HC(Hk0p     E    Mt!H{00fo A HC(Hk0   zof.     UHHdH%(   HE1HEdH+%(   u1N9of     UHHdH%(   HE1HEdH+%(   uɾ   nfD  UHAVAUATISHĀdH%(   H]HH5I .LIHHM   AEt'IU    p@	v@<w`BHuMM)L9  fLc C0LC(Lc0Cf.     HEdH+%(     H[A\A]A^]H   IA<$_   A|$Z   A|$N   ML$MXMt$LKf     HH9   8 yL9PE,$A_.  A<$Rv  I  A<$_!A|$_A|$R	IL$Mh    E,$A   AZuA|$Nfff.     L9wfE,$AZI  A|$N=  ML$MX    AEU  LLE1IB<	E1	M90HKT HHHVIHB<	vI9LL)IEufHL[LH   L)LKH)LsC C0Lc LC(Hs0HC8H>.t    HC8    fD  HfD  ff.     ff.     !<]wHH9uI   H5F LH`LhLLhH`VML$MXA|$RIL$MhA<M  HIT @ 8 HH9uHpf1H}Lxfop)EMfLh)E)EMH`HEUoUoMHELh)p)MKHuH`HH;EsfA<   HfLL)CH)   HKLkC C0!I;LD  E1HA<$Rt'IAD$A<IL$MhAD$IL$A<wIE11H}L`)E)E)EHhHEUMdEHuL`9HhHuLE1   LLoi@ ff.     UHHdH%(   HE1HUdH+%(   u(i     UHAWIAVIAUIATSH   HxldH%(   HEȋ   tE   H_(H9`     HUdH+%(   t
  HĘ   [A\A]A^A_]fD  HGfHWH)EH}HEl)EHu   )E)ELuHUEtH}yHEL  ZHI)HxI_8I9PI)ICIw0LxHLA 1&HGHHHw	  H_LGHHǅP    IL9  E1;@ ff.     ff.     ff.     0KHHL$PL9tPЀ	vLH)L9  J#H@l tHPHH;Hu	M  HP i  I  ;_  {$  CIHL`LXMMI<.  <$  LCIU$   LLpuHHtaLpLPILLH)M)H)Iv  I,  v.C<uu&IQ1ff.     |0  HH9rLMML`LXM  L9SHH@LL)MLHpL`HPHPH9HHp  L`L9H@E1 M8  H::  IHfAUIrMuMHLH@bfHw HLI)^I| Hx D  HM:  A   1f     1<$tfD  <.tHL9<$uL9MU  I9HLHpHpHII)I)<.It{.  Mt_MA.IIHI  <.H  G<.C  H  .  LICHSI<.  HE1@f     C<S  <B,  <R  <L  C<T  <P(     fD  IML`LXLH@HP;  HH)H4H9+HtM1,D  ff.     ff.     0HHHI9t0HDHA	vDHAWHHHI9uиH9Љր-   = B          9     L1M  At1ƃDL5E6D9rH  GL<.M  IIf.     {C,   MM_AIIH  G<.T  LI+@ Uĸ   MW  I9II)@f.     Mo  I::  IIIfAFIZI  ABHI)<.IL`LXLH@HPHE1H9H  L9sHPw{P@   @ A   IHnIITf.     C<FN  <P)   f{Pz*   {@ ?   ʀ@uĈU HG<.1E1l??ʀ΀UƈEĸ   @uX<h2  HP   I0<   AAA??AA?E	5 D	D		Eĸ   <GY{Ty>   zLA   HÌ.&   KE1IHIVM-    IHH9uGHmAE  HxLHxI)HHxItH@HSfƃ߃A@v0<	vHP M"Hx    HE1HML`LXLM/E1hMIA\ IE1HL`LILLX/^LML`E1LXLHǅP      HHMpUHSH   dH%(   HE1H	Jv HuKH Hƅ*   HH HH菬HIv H HHIv HUdH+%(   tN]H]UHH H}HuHUH} tXHEHX HH胍tHEH     1HEHVHHHEHHEH Hu    H} tHE   HE   UHATSH  HHHHDLp|dH%(   HE1HHǅ    Hǅ    HǅHH|   LHHHH^HHHHHIIHHLwHHt
    q  HHHj u
    A  HH    H[HHHHHt
         HiHHpHHpH Hu
      ǅ      HHUHHHHpHHHHHHHHH HHtHH     $HHHpHHHHH HHHHHHPH   HPHH HtHH@H   ǅ    [HpHHHHHHHHpHHHHHHHH9sHpH輎    ;XHH   Hp tHpH     LHHHHJHHHHHIIHHLZHHt    .HHHHHHH#ÐHH虻HUdH+%(   tCXHĀ  [A\]UHH@  HHHHdH%(   HE1H0 HHH$u
       HH    HkHH t~HH;tnHH+HH t	HHH HIH       HHmHHN#H t	HHH*HUdH+%(   tVUHATSH   HHHdH%(   HE1HHǅ     Hǅ    HǅHH LHHHH±H H HHHIIHHLKXH H<t
       H HlH   H~t"H HKH   H=|H    H H$H HHHHHHUHÐH H蹸HHUdH+%(   tbUH   [A\]UHATSH   HHH@H8dH%(   HE1<HXHǅ`    Hǅh    HǅhH8H`LXH@HpHH%H}H`HhHpHxIIHHLHEHt    DHEHHX HEHHHH8HHHH HÐHEH'HHUdH+%(   tTH   [A\]@ UHAWAVAUATSH   H$ H  HEHIHIHDDHdH%(   HUD[iH  H   ILHhdHt Hǅ     8  H/   IH     H5G. H  AE0	  H I}
   HǾIH    H]AŅD9t	D9m  H H5- R  Ht D0E  1  H0HHL8L0H@HHD9~  I$(  H H@(H`HH     Hct D(E~$Hlt H   HE- H81PHHHH1HH5_ HHpLpM  (   eHHr  LoHp   H߾(   hAăE  D{DsKSLKLk =DTiJ9  =JiTD  ƅxAAIIH5`t D6yI  A  I  H8y q  Hp     DH(H(~6HIIH  Hp1HL   i  HL   E1LLLE ϗHH`DHHH@ HpH  HXHP        H  D#Cx tHSAD#CHHSÃ  A  HXH9hG  HpHHs   ~  HXA    EU  x h  CȉCCȉCHCHHCHC HHC HC(HHC(HC0HHC0HC8HHC8D3A
  ]  E  H8HHDcHH  HH  FHHHg  CHt$H  CH@X     LDhIHm  HxHfn1fn        fbL) f֍s8ATLHUHHHHAY^  H`LhxHHHHH H   0		A   McA
   AfAWGd,HIG    fEgHC(EIGHS0MG0HBAw(HAO,LEA@HELAGD   L)IG8   IWIHH`IWtI$H`
  L   L&qHLƅLH@LHID$LH HC(LH{CAƅu;AWH0L vH  L@1HLLHsH]zHpH-fff.     DHrt  ~'H}t EHH'    H81JHaHM  Hǀ      H\HHHHHxFHXHEdH+%(     HeD[A\A]A^A_]    Ht H   H& H81J    HFHtHL  H   H\H4  H   H5 A   AH   H5& !H   H5% E1bA    Ht H   H% H81,I    H(  HH9u@ xluH H9s@;uHyt HbE 101觏HOHpC~HpNA8@ H    HpDHH}HpNHǅp    lD  Au^CDhLKIH  Hs(LHHCHHHCHHC HsLE1@ H8HHDcHH  HH  BHH	  CPHt`B	  CTHC(   L{0HHHHC HCH@@HH  fHĈIHp  H@H      HHHL# AWI1ATLmHHxHHpHHhHH`HHXHt AZA[D E~ Ht L   H# H81^FHHHH  1A  #AHIǋ L费A  xHHS8D狍PpALcHPL)h`PLXHlH D牅qDEr  fnPfnTfbf֕H tH &  H tH   DHHHHAMcI:  H`HhxIHIH  A  A	HHE0	AE,LA   HAE 
   Fd"HHfEEfEeEIUHIE    IM0Eu(Au@HcAED   LEH+HIE8   IH`M}IUtI$H`  H   HiHHƅH@HLHID$H HH;Aƅ   AUH0LhnH  f  HHJIE(AoE0H0fHH@HǅX    H08dHtg  H`HtrL7    HH=HHlHXHhf     Hit DH> 101蔉T    DcI|$躅H  Hs IT$HHHCHf     HLc   I9LBL]HHHXH  Lhg    Avx iHCHHCHCHHCHC HHC # DPL@ Dx@ x CȉCCȉCHCHHCHC HHC HC(HHC(HC0HHC0 x HCHHCHCHHHsHyHC 1 HHHHHPPʉPPʉPH9rD@ H   11E1H1 fH{H8Hǅ     ) )y twHh  f Hp  Hx  Hff   v5o  )      !  H蛣HI|$tfD  HHHH貏H?H螳H tH F  H t,H t"HvvfHǅ    )L(AD  fH{H8Hǅ     ) )y twHh  f Hp  Hx  Hff   v5o  )      !  HSHI|$fD  H   11H     x fD  H1t H9 101_E1+    H訬u HE   P1QDRHz9 H @ HtHǅ    @ HHPof     HHf     HHTJf     HHtff     HDtHǅ    @ H$tfHǅ    )11[Ht DH~ 1H9 01LH1H AHt 01ƃH Hlt DHJ8 101藃HKt LHQ8 1H01rAbAnHt HY8 101>=D     UHAWAVIAUATMcS   H   EHH(LmHE L H8dL<%(   L}L}(  1Ҿ   _HHV  HHU  I     H >    fPH߃HHH@   fP>	l   HU HfHnH@   flH@fInH@0   fl@ 8QHHL  H0`YH0H  HR H@    H@    L0L`HHMH`  foHX HiR H@8    HHH @fo/X HHU    )Pfo!X HEHP)`HfLHH0)pxH0LLxM$  H;PHHO  HcXH  H5Q L+8L(LxHMH@    H@    HpLHY  I$   H@   HHH@8    IHT LxHOHH  HWH  H8KT5 H@    H@    HHHH-Q HHH)LH  HS MH@   LxHH@8    HOIH+  HCWHj  H5P H<bu H@    LH@    HH@r   HpKH<  H-S H@    HH@8    HL%au Hau    NIH  HVH  HtR Hmau H@    LH@    HH@0   HPKH  HR IH@    H@8   L0HH LP(   H0      HHXv0   H5`u LDvH(8   DhIMcLAyIH  H(IVHxHyMIH%  HUH|  H5-O H@    LH@    L LhHpJH1  HQ H@    H@8    L0HH L   H9LHHeuLLLWuHLIH{  HTIH  H0H5a$v H%Q L@$v    :$v GNU H'$v H $v IH>N IF    IF    IF$   IF%IHD  HP foS H@ $   H@8    HH @H      HH=A@ H= 1fAE1HqL9HEdH+%(      H   D[A\A]A^A_]ÐH= 1fH= 1rfH= 1bfH= Tf}    H=x 1:fAf       HE18HFH= 1f    H=R ef.     H=& efH= Ae H= 1el5H= 1ef.     @ UfHAWE1AVIAUIATISH   H dH%(   H]ȉHE    Hǅp    HE    )`)E)E~ @ M),$I|$A~MdD9u1A   A   @ KD- MIDIL	.HHEHt2HPH}LmL9sHm]u Hj]u THEHHELmHPH}A   L9r8@ MKD- IDHI-HHEHt!HPH}LmL9sHEHHELmHPH}A   L9r9D  MKD- IDHI9-HHEHt$HPH}LmL9s    HEHHEHUL`Hcû   LhHIGHpL9  @ ff.     MK$HDHI,HH`Ht@HPHpLhL9sH HH HTH`HH`LhHP   HpL9rK@ ff.     MK$HDHI,HH`Ht>HPHpLhL9sH[u H[u TH`HH`LhHP   HpL9r=MK$HDHI+HH`Ht-HPHpLhL9s H`HH`LhHP   HpL9r>fMK$HDHI*+HH`Ht-HPHpLhL9s H`HH`D)A   PHpBT8H`   LhfEHCHpL9rL@ ff.     MKD- IDHI*H`HHt-HpHCLhL9s H`HXH`LhHCHpA   L9r=MKD- IDHI*H`HHt-HpHCLhL9s	H`HXH`LhHCHpA   L9r=MKD- IDHI)H`HHt-HpHCLhL9sH`HXH`LhHCHpA   L9r=MKD- IDHI9)H`HHt1HpHCLhL9sH   H`HXH`H   HpLKHǅ@    A   Hǅ8    HLhHXHEǅ4   Hǅ    Hǅ(    HLLPf.     H( 
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  EFHXLD+4   wMML+8I'  4A9
  A)McL9PrFfD  HHIDHH'H`HH/  HpHBHhH9sH`LXHPH` EDLE1AIv	  @@t΀A   AHhHBHpH9rIfff.     HHIDHH&H`HHt-HpHBHhH9sD4H`HPH`EULXLhAFIH984HpHXHBHP9  H+8HXIL9PrFf.     MK$IDHI*&H`HHt;HpHBLhL9sH`HPH` ff.     DEHhHpȀIDEHBH9rD     HHIDHH%H`HHt-HpHBHhH9sD$H`HPH`MuILhH8HpHXHBHPHXL9PrKff.     MK$IDHI$H`HH,  HpHBLhL9sH`HPH`HpHLhHPHXHHH@H H@踅H9H MtLLPHHXA   M9rHff.     MK$IDHI$H`HHt-HpHCLhL9s H`HXH`LhHCHpA   L9r>MKD- IDHI#H`HHt-HpHCLhL9sH`HXH`LhHCHpA   L9r=MKD- IDHI9#H`HHt-HpHCLhL9sH`HXH`LhHpL9rGA   @ MKD- IDHI"H`HH8  HpLhL9sD)C   B?HELeH}HPL9rB@ ff.     MK$HDHIZ"HHEHt!HPH}LeL9sHEHHELeHPH}   L9r:    MK$HDHI!HHEHt!HPH}LeL9sHEHHELeHPH}   L9r:    MK$HDHI!HHEHt!HPH}LeL9sHEHHELeHPH}   L9r:    MK$HDHI:!HHEHt!HPH}LeL9sHEHHELeHPH}   L9r:    MK$HDHI HHEHt!HPH}LeL9sHEHHELeHPH}   L9r:    MK$HDHIz HHEHt!HPH}LeL9s HEHHELeHPH}   L9r:    MK$HDHI HHEHt!HPH}LeL9s HEHHELeHPH}   L9r:    MK$HDHIHHtHEHELeHPL9s HEH H;IH  HtCH/  HpH< LH@    H@    HH`HXHP7H  H? L H@8    fHHL:IH_  HBH  HUH@    LH@    HHUHXHPY7Hd  H? H@8    fLHHN:IH  HzBH5  HUH@    LH@    HHUHXHP6H  H> H@8    fLH   HH  1HpoZH}fZH}]ZHEdH+%(   h  H   [A\A]A^A_]fD  HHIH;88d    IFHHBHXL9PrD     MK$IDHIJH`HHt-HpHBLhL9s H`HPH`HHHX;~HXL`DEHhHpȀIDEHBH9rD     HHIDHHH`HHt-HpHBHhH9sD<H`HPH`MuHhHBHpH9rJ ff.     HHIDHH*H`HHt-HpHBHhH9sH`HPH`HHHX}HXHhL`HpIH9rEf     HHIDHHH`HHt:HpIHhH9sHHHL肚H`LH`HhHBHpH9rFf.     HHIDHHH`HHt-HpHBHhH9s H`HPH`HhHBHpH9rC    HHIDHHH`HHt-HpHBHhH9s H`HPH`HhHBHpH9rC    HHIDHH:H`HHt-HpHBHhH9s H`HPH`HhHBHHpH9rK@ ff.     HHIDHHH`HHt-HpHBHhH9sH`HPH`L    DEHhHpȀIDEHBH9rD     HHIDHH*H`HHt-HpHBHhH9sD<H`HPH`MuHpHHLhHXHJH(   HPMi   M|2I   A   H9Pr_DXLP    HHIDHHZH`HHttHpHBHhH9sDXLPD<H`D4HPL8H`CHpLhLKHXLSDXLPD4L8HpLhHXHBHPH= 1HNsHp}D  H= 1NLXH=f 1MH=B 1Mf.     fUHH H}dH%(   HE1HtHHGHt?H8 t9   H=
v ܸHEu0H
v HxH@H|
v     HEdH+%(   u5 HHt H 101cHE
v H@H     {ff.     UHHdH%(   HE1H=
v  uHEdH+%(   uþ   H=	v ٞ$@ UHAVIAUATISHHht dL,%(   LmIH3(uTHCH8 t Ht LH7 101>bHCL01LkHUdH+%(   uIH[A\A]A^]D  Ht LH3辰tHt LH3訰wT@ UHATSHHt dL$%(   LeIH3bu&HCH HUdH+%(   uEH[A\]    HYt LH3&tHt LH3Htf.     @ UHAWIAVAUATSH8HyHuHUD`dL,%(   LmILPH   I7HLHf{AU1H3AEfCI    H  E11HUHSHUD  AFII;G   IWHKH4HHCH  HUHBH}LHH)H)΁   HHHMH}P<tH߉EіEHUdH+%(   uH8[A\A]A^A_]1иpUHAWAVIAUI	   ATLSH(  dL<%(   L}IeHtHxH5 I]Åt/1HEdH+%(   -  H(  [A\A]A^A_]fD  M)LIt$xIH   B  H1HH5] ]t*1HH5V L\tL赕kIHu C      MfH1HL{LH{H      SHV H   fC1\1fCfCAT$HAD$fCHI~INL:LUIHHSHHHHsdL%(   LMIѺ   H)H;BHSHHCH9HGHCHEdH+%(   uH]_@ ff.     UHAWIAVAAUATSH8H   dL,%(   LmIH   HuHEFhEHbpf_progH_   fGHLmE1HLdIcD  HH)I|	1HL4,    dAL9uA]	LmHuDMtz   HELt+CL0agIHt-   HcLZ H)I<   1Hc~dHEdH+%(   u6H8[A\A]A^A_]@ Eu}uLN@~@ uŐL0 fUHAWAVAUATISHHt dH%(   H]H8    KftNfu(HEdH+%(      H1[A\A]A^A_]@ Ht H    01[fM$  MtCLAVHtL0AFxt1ېI   I$`  H4AHtcHP fnfAnHfbHƂe  L   fւ   LA;^xr-D  Ht HH0Nf     HA;^xr     UHATSHdH%(   HE1Ht]IH t1ېIT$H<肑CHI;D$rI|$kI<$bHEdH+%(   u+HL[A\]C HEdH+%(   u	H[A\] UHATSHdH%(   H]H_Ht+HNHVIHH6u1H9ID$    HEdH+%(   uSH[A\]     HCHHt 0HtH, 11Yf     HA 11Y9f     UHAWAVAUATSH  O4dH%(   HE1  HG8Hǅ    HH`HH8ڏAǅ2  H1   Hǅ h   HH DHH N  `  h  p  U  HxH5
 oH  }HH  uH>HH@f  %  u  LqE1LH@L$ff.     A6He>Hߋ0b   H5u HGA IM9uE  lGHHH  H@Dǅ@    HH]  D<H   D   5GIH|   EJ    HHGIFH  E   HLLE1 IHCM9tR   N$0FI$HCJ<0 uHHH;B4E1  IHOd II  L^FIHH  1B   HLHT   MLfDfLM>IDIG    IǇ       H)  HH@  H@HID LHLHD  LAu L-<L0H``   H5: HI	  I  H;  L41HG @   IK7  K7  KǄ7      KǄ7H      HH)@  HIL$K7  Bfo2, Ee1H K7P  HH5H H     L(Hǅ@   HǅH    HPssHI7sLLLHLlI  IL;LLHA   E1MMͅt0f.     IFDHLJ<IE;   rMHLˈHߊLHEdH+%(   uKH  L[A\A]A^A_]H訊     HxD8LIf     UHAWAVAUATSH(dH%(   HE1?C  OftYfu+1HEdH+%(   2  H([A\A]A^A_]D  Ht Hj	    01<Sf.     IfAŉǅ    7HH=    H      (   E#OIH  HH{LLID${   Eu1E1L/D7fIH   HuHWUIHz UHUNHHt6fnEHUHx LfnMfbf@HLG~   1ofD  Hɯt Ha    E1H 01Q>D  Ht DEHna H    01QH1_LE1TH1E+DE   Ha H2t Hs 01A]Q     H߻ڇ~D  UHH dH%(   HEHH  HUHuH5HEH0  H@HEHEdH+%(   uC UHAWE1AVAUATSH   HHH`dH%(   HE1E    y^ t+HEdH+%(     HĨ   D[A\A]A^A_] zHMIH  yLH  HMIHE1HPHEH0H8f.     HPtnAǅ  }c\  HHHH  HE/\  H@E4IH  H=   8   b  H      Xx;     ;X|            A     9G  胬HHEA   xH[  H0H}ATUHpHz XHhKIHtGfnxfnXHx HpHhfbf@)H@LD  IEHp    LHhID$ME1HxfI$   C   HJ4I$   B1HHsHxDSHpIH      H   HUfC AV1fCIfCH=	fD{LHH`H})L9hUAH8MI܀x^    L3H}
EM  \v2}^fD  IEHp  HE         Ht DEH] Ho    01	MID$HE    Hx AE"^ f1A$AVHxID$    AL$HA$   AD$IEID$fA\$(   HHH  L(H@HH@    *  H]H`LLHi(HpAIHH`LHHLE1A{fD  Ht    MH[ H 01K\0AH"t H`LmHH0LuHx8HG HMHHDHHHH  HE8   L H H8x^ 8L1 ßME1 I   AL(    Ht HZ    H	 01JHt HZ H 101J6LMAȿ   IHNt HGZ Hx 01wJLH}~\k/LMHE1Lh @E1L 1MHMĀHͧt    HY Hz 01I\.LM   IHt HY Hf 01IL]\.L@	ALMH"H}}@ UI   HHH   dH%(   HE1HpHǅh	   HH HLH`E@H`EE@E   lHUdH+%(   uUD  UHAWAVAUATSH8  dL,%(   LmIEEhE9   uE9Elt%HEdH+%(     He[A\A]A^A_] HMexI]pIA      Hǅ    A  AMH L1   DMDE   LE1LEf     HDIHHHHLKDAD$H<  L   APH1 XZE9uH|D  DDH	pHx D9:DHfD  H1LHHA$HLAM   LLPHJ 1 Y^V_f.     D  U   HAWAAVIAUATSHHH(  HdH%(   HE1ǅ   HHH	t1HEdH+%(     H(  L[A\A]A^A_]f     HDHH;A  DA ;  DL%]V 1E1LMfHc   HHI9H  LcHIyI97  HcxII!ޅ5  A9  M  DExIBH=HHAՃH	tDDH   AIH  LXHX1   LM   HU HLG@ EDAE   LcExIK4AHHHƃH	      HHtLcBLcJExIFMEyODED  HH!D  MtDExIBfD  IBEC<     IBfHLL9LA  ENA T  D[    IcT$AA؅   Ic$AAMcɅxHMM9  DIIMǃI	      HHtIcT$؅xHEA9zHt AHS 2H 11/CLyI HDEE9:Ht H1S H 0fD  A   En_Ht A   HR H_    01BDD  HCt A   HR H    L01ZBDLc    Ht H    01$BI     Hɟt H    01ALxHt 1MHR H 01ALox5I8f     UHHdH%(   HEHGtH   H)W(tH   H)W0tH   H)WHtH   H)   tH   H)    tH   H)   @tH   H)   tH   H)   tH   H)   HEdH+%(   uS UHHdH%(   HEHGtH   HW(tH   HW0tH   HWHtH   H   tH   H    tH   H   @tH   H   tH   H   tH   H   HEdH+%(   u UHAVAUATSH   H$ H dL,%(   LmIH=Ŷ Hǅ    7H   HMIIH   HH5 H{QHHu(   fD  HH5 1SQHHtc   H1MHx 1HKu   LuHEdH+%(   u$H   [A\A]A^]fD  1@ 1g    UHAUATSH   H$ HdH%(   HMHHtRI1 HIL Ht:H1L     H  )Hmt
D  HUdH+%(   uH  [A\A]]f     UHAVATSH(dH%(   HE1H t3IA.1HE    H/.HH褌u0HU1I$HUdH+%(   w  H([A\A^]     H=O 5HtNH}H1   L  H  Iˌ  H}Ѐ?/>  ayL1-H5  H   H5z] H   H5  Hԋ   H5&  H轋   H5 H見   H5x H菋   ;s   {h   {    Ht HAt HHUHUȃ   HH}о   HLs  1H  謋tH}r1Ҹe    Ht     1H9    Hɟt k@ Ht [Ht OH)t CH5  H荊teH5  Hzt^H5  Hgt\H5  HTuUHt H  HH= 1HHUt Ht Hؙt HH= 1D  UHHdH%(   HE1@+H5O  H豉HUdH+%(   uVf.     f.     fU1ɉHSH(dH%(   H]HHHHu܉}܉U   MHGHuH{   GHuH{   wGC HEdH+%(   uH]f     UHAUATSHH}H8dL$%(   LeIHuutH1ɸ   HHAAAAAAA   Av%   AAAHHMLHR1H  2$   HLc"|ZYHi   tBD# 1HUdH+%(   u+He[A\A]]@ AA%   EAA@ ff.     UHATSH0dH<%(   H}迀   *5HHtaHuH}u̅unAAHHMо   HR1HI N$   HLc>{ZYHtBD# HEdH+%(   }   HeH[A\]f1ɸ   HHAAAAAAAt Ai%   AYfD  AA%   EAA4lff.     UHAWAVIAUATS1HXdL,%(   LmI@ Hx-   OzHuLE1
fAHx-   .zHuA   E1t   LH}v    E1H}HM   LFaH}ALEuYDeD+eMc   E   -   LL)L9&D  Ht LH 1016   HUdH+%(   uUHX[A\A]A^A_]f     HYt LH= 1016fA   D  LKkf.     @ UH5t  H=j+ HAVAUATSH dH%(   HE1HE    HE    蟌H  IH]
   H5'+ HotlLHuH}
   迅HHt H 11ۋ015H}VlLHEdH+%(      H H[A\A]A^] H{H5  XLH{HHUH5 1*3]	 YE f/sH,HiI \H,H?{Ht H 11ۋ014=ff.     UHHdH%(   HE11H H	HEdH+%(   uHUHH@dH%(   HE1=u  t<4 |u f/   H,HUdH+%(           H}HuIu H} H}H5 JH   }v#1ɸ   HH@@uuFHxSfH* u f/W\H,H?IfD  ɉ1HHHHyHfHH	H*XfD  1f.     fUHAVAUATSH  dH%(   HE1=|u  t.pu HUdH+%(      HĀ  [A\A]A^]D  AŅ   `AE1HxHǅh    D     HpF   H=Z HHHpFI)Lhkt<M`  HD   1AIH~(HpD`HD  u     D0}u D  UHAWAVATSH dH%(   HE1=Gu  t);u HUdH+%(      H [A\A^A_] HUHuE1HE    H= IxH}AiH}I%hLHuH= 1HE    xxH}iH}HgHXLAXH߉Du 6jL.jsu )}fff.     UHAWAVAUATSHhdH%(   H]HH0@B  1Ff   Aă   \Aƅ  LmH;1H5i LY.  DA1AƋEAHu otkLcN4M>M  H{01 FH{0W~+I>1E1FH{0ADEH{0WD9H{0iI>[HC0HEdH+%(     Hh[A\A]A^A_]ÐHEdH+%(     Hft H   H 0Hh1[A\A]A^A_]/1iEfuoE  AH    HEH  HEAO  ARA   L}LmH;1H5 L,*  EHL9  AHou f.     HEdH+%(     Ht H 10Hh1[A\A]A^A_].fD  fo t   Hu fU)Efo| )EB<!    0HuLHE    EHEHHxexH}eH}Id1LL-`u DHlu CD    B!LgG| mfA   L}Ht HH 101-    Hqt HH 101-    Hu F<H{0UbIHH{01E1KCA(fD  IIcEADfDdPH{0!CAH{0TD9#HԊt Hx   H 01,CD     Ht EHY 101,D@ UH5ג HATSH L'dH%(   H]HLO{uHdt CCHC(H5u L){uCCDt4H;H5  {   HEdH+%(     H [A\]Ð{ t*H5  HL  H4t H    =u     D%u EtL#   H= Ld/     LH= d^HEdH+%(     1H H[A\]fD  H9t HH   uH50 H3`HH@81x Ht      Ht H    Hɉt H   D  1XHt<HH= HEH}؅AD%u cau     u  u PD  HEdH+%(   u
   f.     UHHdH%(   HE1=1u  t'u HUdH+%(   uG@    vxHtH5_M HJuu u fD  u Zf.     UHHdH%(   HE1tHUdH+%(   ufD  H   uHH @ ff.     UHHdH%(   HE1tHUdH+%(   u%fD  HWH   uHH fD  UHATSHdL$%(   LeI,u 1HUdH+%(   ukH[A\]fD  LDtI$  HH9uf.     HH9tI$   H9   uI9tHuI$      UHAUIHzATSHdL$%(   LeIpH   H@   I$   HTH   I$   Sƃ   H=EK H   I$  H  u1LH(  A$    A$    A$    A$    A$    ,HHVIEI]L+HCH1HUdH+%(   uH[A\A]]ø    UHAVATISHH(dL4%(   LuIH u2Wt-Ht tH5w" Lu   fD  H5 Lut%1HUdH+%(      H([A\A^]D  H%u HcH{C9|3    #      CMHH   HcMHCHi  LLL4Hc   Hi  HCHHHcHi  HCH@    Hc;Hi  H{H?4Ls*    HcHi  `JUHAWAVAUATSH   H$ H8f   E1dL4%(   LuIHI))6gH5  HC]t/HEdH+%(      H8  D[A\A]A^A_]    HHHAąuZHHtN~Y1E1f9~CHI  HLLLHBtAHI[E@ HA  *[&UHAUIATSH(H^dL$%(   LeIu'1HUdH+%(      H([A\A]]    LxHHHHM8IT$1HHRHHT(HUL   It$   HUHMHt1~D@fCHH{(fSIU HSIEH)к   HCIEHC ID$@C<IL$IT$HI<$}@ ff.     UHSH8dH%(   H]H`  H}zHuH(  HUHEHt5HHUH5|7CH}؉YHEdH+%(   u+H]H~t    H 01"f.      UHAVATSHHdL$%(   LeI~uSA$     t9      A+$   HUdH+%(      H[A\A^]D  t[fH   H=u=L=uXI$   H9   pHkzLA`z<tEtrD  A;3fD     KfD  LpfD  UHAVAUATSHdL4%(   LuIX}   II9txE1E1HL9t8AH<uXMuHyLEHL9ufff.     Mt+HEdH+%(   u:HAt$LH[A\A]A^]`HEdH+%(   uH1[A\A]A^]f.      UHHdH%(   HE1HEdH+%(   uɾ   ffD  UHSHdH%(   H]H>|uHUdH+%(   u&H]D  HhH1Htԃz`UHSHdH%(   H]HuHUdH+%(   u3H]D  H8xuHEdH+%(   uHH]H; UIL  HHHGdH4%(   HuHփ	wH}t LH  MLDH t@H  HD HtHHEdH+%(   u?H  L1ef     HEdH+%(   uLH] L1le7    UHAVSHHH  dL4%(   LuIH5ź dH     H5 0ucHSH   HzP    H      +      HHBPHIF@HEdH+%(      H[A^]D  HEdH+%(      H  HW HH{t 0H11[A^]f.     HEdH+%(   uqHZ{t HH 0@ HEdH+%(   uIH2{t H(  H 0HEdH+%(   u!H
{t H 10H1[A^]0ff.     UHSH(dH%(   HE1u tHEdH+%(      H]ÐH}H4tH}7HtH=-" HEH= HErHMHUHtr9qt=HtJ9HuC
tH3zt Hd 101aKu    XfCL@ ff.     UHAWIAVAATSHH0dL$%(   LeI3t3fC9   1HUdH+%(     H0[A\A^A_]D  Ht f)EHEAuwtHn7   H9   tH  H5W{t Z6LE   H  LLE~HMLLHU 1aH}EEEEfHH0H 8i$xbxs{8v9HEdH+%(     H0LL1[Hj A\A^A_]vafD  C:uD  HHsH  HH9uff.     HH9H9tHHUsH  HUtHCH9BuH5zt 5LM   H  LLMBLEHLEOLELLHH> 1`H}EDE^f.     f.     f.     UHAUATS1H  dH%(   HE1AHtKIHù   MP   1L    H!1H%ZYtHEdH+%(   uHe[A\A]]f     U@HAWAVAUATS1HH  dL$%(   LeI􉅜HH          1ALH LZ_HHL   H1HHH5ڴ IHA
OA         DDIH   D(I<$DpXAGAD$pAGAt$HcH`H   IcWL<I$CL91HUdH+%(      HH  [A\A]A^A_]@  uHPut H׳ 101~&@ H1ut A1H_ 01VHut H 1016LM[@ ff.     UHAWAVAUIATSHdH%(   H]H~2Htt H 101LR+IHg  C        Hu _IH;  sE1   @ ID9   H     LH JD@1APEAPurLLj	ZYAċCEt~E1fD  HJ<ID9kHHLLLHEdH+%(      HeD[A\A]A^A_]D  IU I9tX ff.     ff.     ff.     ff.        ɍAIHHHH  HI9uC    E1NA[     UHAWAVAUATSH   HhdL4%(   LuLwP;DEN        IH  E1LDÅuoAE9uL%u AFHh    HhH5 Icu}   Hixt HEdH+%(   f  HĈ   [A\A]A^A_]EL$E1E~ I$J<IE9l$L LJfD  1@ Hwt            IH  HhtHPHH  HxH58q %IHQ  HsLmǅ\HhHtH`        H5 L|E111LLZ=  HhH`H5 L  Hpt 1LH1 01 L(Hu DstHZ  HcPN  H0HHfHH93  L MtA;$uE:D$uIcD$H    AFPAVAD$IcvI>HH  ǅ\    IcT$L$IHxH5o 1-$IHAF  L%u M`  AT$  E1D  I$J<IE9l$LLH\   L5u HPgH;fHiot 1LH 01L,'5    IcV~@IH4@ ff.     HH9tHHt;
uD:BHH9uHnt H 101f.     L&M5AFE1~#fff.     IJ<I E9fL LjG\HYnt H 101LU LG\AF]AFt5L%:u Mtǅ\AL$LLFHmt H 101L%u M   ǅ\A|$ LLpFHtmt H% 101LJFL%u M+ǅ\A|$ lLGLFbAFXA|$ ~#ǅ\E1LP#LLE1HP;yA|$ xff.     UHAVAUATSHHdH%(   HE1H9t[IIL  I9tAI~0Ht5Mt0AD$HE$H ED$AL$   P1XZLHI9uHEdH+%(   uHe[A\A]A^]f.     UHAUATSHHdH%(   HE1H9t3I H  HL9tLL  I9uHI9uHEdH+%(   uH[A\A]]6fD  UHHdH%(   HEH  H  HtBIDHHVXD Ht@R   L1AQAPRLIHLH iH HEdH+%(   u)ÐHH L1R   HNiXZD  UHHdH%(   HMHO0 u]G8t&HEdH+%(   umɺ       H=M  HEdH+%(   uGɺ      H=i f.     HEdH+%(   uɺ      H=3 D  UHH   dH%(   HMHљЃ)H\%t HLH  PH  H@H;PsHx  tLLJD(LHMu.fHEdH+%(     H1HA1H @ LPMtH  Ht;y  u5HvH;VmH~  mHLHt(HLLHLP1H H)x>fH*MxpfI*MxBfI*^^Y	 B@ HfHH	H*XD  LAfHL	H*X@ LAfHL	H*Xz4@ UHAWIAVIAUATMSHH(HUH7HMdL,%(   LmMoHMLHL-gHs0LaM>M9trf     I  H  HtBI9  t9LLHMHUHLfH{0HM1H)     LLHAM?M9uHEdH+%(   uHs0H(
   [A\A]A^A_]'    UHATSHH`H dL$%(   LeIuH}@   A$    M   HGenuineIH9Et%1HUdH+%(     H`[A\]    HneIntel,H9EuH=,o ԿH= HEĿHUHHH9tHtxH   DIDB11ff.     HH D9@	D9	H9u   @   FL;fD  A$*    Ht3q1 ff.     9pH 	H9u ff.     H H9H H9u    r1ff.     9pH 	H9uLS @ufD  Het Hz 101A$]f.     f.     f     UHHdH%(   HE1HEdH+%(   u`-ff.     UIHH dH%(   HMHHtLHHu1HMLEcHULEHM: u)H   ALI   1HUdH+%(   u1׸@UHHHGpdH%(   HUHH8H9t@HR`R@ ff.     H?H9t 9WuHEdH+%(   u"fD  HEdH+%(   uɸfff.     UHHHGpdH%(   HUHH8H9t@HR`R@ ff.     H?H9t 9WuHEdH+%(   u"~@fD  HEdH+%(   uɸ-fff.     UHATSH   dL$%(   LeI~*1D  I$   H[HH<7A9$   I$    HEdH+%(   uHL[A\];蜿ff.     UHSHHdH%(   H]HH9tkHS`R
fH H9tX9PuHX  HtGrHH@HH   HҺ   HDH   HUdH+%(   uH]f        @ UHAWAVIH5 SHHdL<%(   L}IRt!HEdH+%(   u&H1[A^A_]D  LHAGx@ ff.     UHAWMAVLAAUMATSHHH  HHp dH%(   HE1+tHǅ    1LLDH  H+   HHHHHoHHHt1I!HILI?wR   1HHtBHEdH+%(   3  HH  [A\A]A^A_] r   sƅ   1E1   L    Di@{  HG  H  H   IcHD1   H)LIAMA@+  HAǸ   tAAA     H   tUAMA@   H   Ic   D1H)HQ LHAMA?   HAAtkIc   HA_ 1H)L_HA'    Ic   1H)Ho L.HDi?tGHAu+D1f     D    1AH^t HM1H L*g 01 Hp  E1E1HLTO@ ff.     UH  HATISHMHH5 HdH%(   HE1	tTE       H1^t I$IH    01U HEdH+%(      HH[A\]fD  EtH5 L:H   HH9}   AL$ ff.     HH9t`9JuHr1ɺ@   fff.     ff.     HyHHHHHHHHu߃   HcD     f     UHAWLcAVI   AUATIHs SLH`HMH\t H! 01dL,%(   LmMA0M	EY^A~z   A   D9;  I   I   O<J<Hug &  IT$1H H9o  L]Hc)HIITD  HH9C  H8 tG   @ LM  LWML$L;JI9S  EM9rsL)HI9rhLuLLMHMK4LELUHESLEHMLMu4HULH+ELHMI<HLM!HMLMLEEI9  HuI)HLLA0} g  HLɌ IM IL$HMM HF[t H   Hο 0Q1HZ eX1ZHUdH+%(     He[A\A]A^A_]    IT$AFzI      vQIvpI~`HUPHUH   HtH	HHH      HCH9sI   HH9r 1A   I   D9Ҹ   DA9|D  A9}Hc   UMVHH  HcEI   H@H.MI   HA   ^f     ML$IE M   1It$IMM HL L9IL$HMM o@ I9M9 UHEHLLMHMJ4LELEHMLME LuLLLMHML.LMHMJ<8K4HH)L)I46-    I!4     ID$HHMHEHt=I   J<    JI   HEH+EJDI   I   LHXt AH 1H 01hD@ UHAWAVAUATSH  dH%(   H]Hǅ    荺HQ    HA1 ALH§  DAH 1H{"tFǅ   1LDHH H J"  ǅ    D  u1LDHH@  H "   ǅ   {  1LDHH<  H !   HAWt HLH    01b1   H0HH űHH "tV1H D(HEdH+%(     H  H[A\A]A^A_]Ë/D  E1E1   HH H0Hǅ8    vH8l     1LDHH  H  Mc   H 1L)J->    1LDHH H F    ǅ    KfD     1tJEʉt=   Eʉt+   t             Ic   HU 1H)H=>Aq    uN¹EʉtH   Eʉt6      $@ ¹(f1u     Ic   H 1H)H==A       $@ tfD  D  t   t	u끨tqjf.     ð UfHAWAVAUATSH(  HLw`dH%(   HE1) Hǅ     )H9     L0I   HLLHL=H5L L   Hǅ    L31   LHLH5œ L_   Hǅ    L1   LHL迭H5 L    Hǅ    LH5f L&   LH1HLjH5Ӓ L{  Hǅ    L`1ɸ   H5 HHL鉽LHo  1
tHǅ0    1LHΡ  LH5ڒ ߫t
ǅ    HH(  HH9  IO`Ifff.     H H9  9HuLX  M  LHHIċJ0  H  H8H  H |d  )  H=L 1}H1H(  HzHHØ   C ǃp   AvHHSHHxHSHsHHKHsHHsIcWhHSAWyHCHHSHCHHCЋHC؋HCHHCH0HCLcMt.M  LIXHH  HLLHcH1HUdH+%(     H(  [A\A]A^A_]D  E1E1   LLLHǅ8    YH8HQf     E1E1   LLLHǅ8    <H8HE1E1   LLLHǅ8     =H8H5E1E1   LLLHǅ8     H8HH   H(  f.     E1E1/D  1|f     HHL$S    I1BRO@ ff.     UHAWAVIAUATSHH   HFLg`HdL,%(   LmIHI^pAELAFyL;E1L9u    @ ff.     M?L9   AD$A9GuM  Ag9H0H= IG    P     u
0AƇ  AG:AƇ  	AG:AEKIH9  xA9|$C  MIM?L9eA}L    E   E$  HH9t/1     ff.     P;H H9u6  A}K   A}N   M  "A    1L0H  H L MND   L HU DLHS D     QA}K Y  A}N HCLt H 101q     H!Lt H2 101OAHEdH+%(   2  H   D[A\A]A^A_]MN Lʋ Ha Hŋ L
D   MNDLH[ L H D  RA}L <  A}N   AMlA}K tP  HWu 0      1AMlA}hu   1AEh@ ff.     8  A}L u'A}N u HVu  HHH9BAFx1H0   H HH HHLHH5C   HE1E1LH    Hǅ8      HL8
A}K   M#f   H<uZA}R tA}Q tL"AĄ  I} G  Hxx t	     HAEQEAhAF8 u$?3tVtAE`fff.     HLeH)<  A}K   1I} tAv8@HIHk  HHoEt	AƄ$  H;     L    MA}L D  HHt H 101fH}Tu ʋ HA}L 9  H=  vHPH   A      HDA}K MH@h)  E1-fD  1H5 L.*HLI   AMlIHSu D LHa         @ 1AAElII   H<  HL&LGt HH EH9  1E1@    HtIIH9LCH9HBHH9uH(Su AUl9  H~ uA}hu   1AEhAA1H	HI   HH   H   HH     A      H HHH9HCACHHAH9CHHH9H?HBQH9CH    HCH]     IHAUlW  A}N         H9rHpHUH/Ft H1Hc 01ZH8I}   AF8H=̮ 1A2LEt H  11A3MND IMN    Lo.)}     h  WHF   H	1HIH   HH C  H       H  IIH9ICCH H9yCHHH9HHCǍyH9CHHH9H?HCǍyH9CH<    HCH?   HLAMlLDt AI9  H8  0  HHT ƿ   1L L MI   I   H9LH=N 1?DbALI9  ILH` Dֿ   1LH HLH   L9iH LH= 1L       @   E111DHڪ    H     AMlA}K SHOu 0  @ 1AMl.HII   LkL   +   L+   1AAElA}h   1AAEhA}h<   1AEh*AUlE111DH    H  E1I}  YA}  NI} C@ HA      H0@HBt H 101@/   ?   E11|H5J H     H^IH= g  ƀ  H@h   I}     A}  I} f.     H-Mu HE11H 11t HHͨ D11Y   HLH@t HV 101#HH\ 11	A   HIHtH;HǾ   ƀ  g)   LZ)   LM)   LPHAEQ @h   LA@t  A1L"I H8    A3H LMILD A3H    1/L?t ܐUHH dH%(   HE1=u  tHu HFHEdH+%(   uHuȊu HuHu . ff.     UHAVSH0dL4%(   LuIH=G EH     H5n H= H      HH   HHH=HUfHnbAt )E HHU~Vs fHnHJfoEflfHnHHZ`
fHnH~"s fHnBT   HflB@J~s flJ ~s flJ0HUdH+%(   u+H0[A^]    4 A1A1UHHdH%(   HE1HEdH+%(   uɸ0   芚f.     UHHdH%(   HE1HEdH+%(   uKff.     UIHH dH%(   HMHHtLHHu1HMLE<HULEHM: u)H   ALI@x1HUdH+%(   u 1׸UHAWAVMAUI   ATIHC SHcH0HMH<t H 01dL<%(   L}MA0M	AA   Y^9   I   H[H<ǀ u`It$1HH H9(  H]Lc)LJHT ff.     HH9   H8 tGIL{m IID$IMH;t HH H8    3P1X1ZHUdH+%(   
  He[A\A]A^A_] Ҹ   D9|         9}Hc   UMHH   HcUI   HRH#MI   HA   f.     IT$III!Ht-MILz L9ID$IM    1HIH:t AH" Hz 01s UHHHGhdH%(   HUHH8H9t@HR`R@ ff.     H?H9t 9WuHEdH+%(   u"fD  HEdH+%(   uɸfff.     UHHHGhdH%(   HUHH8H9t@HR`R@ ff.     H?H9t 9WuHEdH+%(   u"fD  HEdH+%(   uɸ]fff.     UHATSH   dL$%(   LeI~*1D  I$   H[HH<gA9$   I$   PHEdH+%(   uHL[A\]̕ff.     UfHATSH@dL$%(   LeLg`HE    )E)EH0   H(  H0   H  HH8H   HuHU荸HUt%t'HUdH+%(      H@[A\]@ EąuiH=ry 1HUg}E1HuHUB   ED$HzLBHB Hr(HJ0CpHB81f.     1111fD  }Huȹ   뫐V葔UHAWIAVAUATSHH(Lo`LfdL4%(   LuIcEA~N d  I_hAFLAGpHE1H9udff.     H H9tQHA9MuM  `9H@    ƀ  AFKHH9  Au9rU  IHH H9uAFKA~L   ;  L)  A~L e  H=Bu I   ANlDLH    } R    @ 1AAFlII   Hƅ&  WHF   H	1HIH   HH   /   ?   I  HHI9HCCH H9yCHHH9HHCǍyH9CHHH9H?HCǍyH9CH<    HCH?   HLANlH5t  I9  H    HHv ƿ   1AvKANl@     MthHL5L'  AvK@tCH59  Hu2LcH߉ELVAd$9EID$    f1HUdH+%(   =  H([A\A]A^A_]@ H4t H 101I     H=]@u uKD}       1AANlA~hu   1AAFhuMH=@u HA~L tm      H9r	HPHtaH4t H 101<P   } dA~ha   1AFhO            M[v  @ 1AANl>HII   LH       %   L8θ   1AAFlA~h   1AAFhH3t HK 101H\Hҙ 111EH2t H 101'HHL 11H2t H6 101QUHAVSHdL4%(   LuIH=p uH      H5a H=Ns H      H   HHX`~s HLfHnHp@P   flfHnH9 fHnHZ~s fHnfl@~s fl@ ~s fl@0fHn)4t @@HUdH+%(   u1H[A^]D  S( A1     A1UH1H5] HHdH%(   HUHUbt.H}eH=\ H14HUdH+%(   u	 1觍    UH1      H5È  HATSLEH0dL%(   LME1B'   H}1E    E    H   H@(HXH   HK Ht~Hp HHM.H}HUHuHHt{HUHLcEuHH=pq H1:HIHEdH+%(   u@H0L[A\]@ 11E1    E1 11E1    LcE1kff.     UH1      H5q HH0dL%(   LMLMLE&   H}1qHHtyH@8HthH8  Ht\   8 t"H=s  1LHUdH+%(   uA H}HUkHUHHR8H8  1fD  말1臋    UH1      H5  HHdL%(   LME1LE%%tAH}1HHt.YHUdH+%(   u-ɉH=  1yf     HEdH+%(   u1     UH1      H5  HHdL%(   LME1LE$tAH}1HHt.HUdH+%(   u-ɉH=   1f     HEdH+%(   u1H     UH1      H5c  HHdL%(   LME1LE#tAH}1VHHt.HUdH+%(   u-ɉH=`  19f     HEdH+%(   u1訉     UH1      H5Ä  HH dL%(   LME1LEE#   H}1HH   HxH? tC   fu`H@(H H8Ht4HMHMHQ(HyH2HqHMHy   fuH6.t HUdH+%(   u+D  HEdH+%(   uHǨ   锬@ 1览    UH1      H5Ã  HATSLEHdL%(   LME1B"   H}1E    HtsH@(HxHtnH_ 1HtHp BHUHHUHH=l H1lHI!HEdH+%(   u HL[A\]fD  E1 11轇fff.     UH=Dt HSHdH4%(   Hu  %H,t H5-^ HHHEdH+%(   u	HH]OUHH}HuHEHE]UHH}HuHE HE 8]UHH0H}HuHUH} u
           txHE    ]HUHEHHMHEHHHtZHUHEHHMHEHHHt   .HEHEH;Er    HUHMHEHHUHHH}    tHEHHEHAUHHH}HuHEHUHH} tHEHL    HUHBUHH}HuHEHHEH H9sHEHE]ÐUHHH}HEH@HʺHEH H躺HEH论ÐUHSHH}u]HEHGH9r%H H5 HA HѺg   HMHEUHH[H]ÐUHHH}HEHUHH H}HEHEHEHBUHHH}HEHÐUHHH}HEHR~ÐUHHH}HE    HE@   HE@ HE@	HE@
HE@ HE@ HE@ HE@ HEHHHEH0HHEHHHHEHhHHEH   HHEH   HHEH       H   ÐUHHH}HEH   H2HEH   H HEHhH蠸HEHHH萸HEH0H~HEHHpÐUHH0H}dH%(   HE1HE    HEE HUHEHHEHH#uHEHUdH+%(   t豂ÐUHHH}HEH袃UHH H}HEHEHEHUHSH8H}dH%(   HE1H]HEHEHEHNHHEHHHyHEH=HEHEؐHEȾ    H蒕HEdH+%(   t݁H]ÐUHHH}HEH:HEHÐUHHH}HEH螂UHH H}HEH@HEHEHH;EHEÐUHH H}HEH HEHEH Ht)HEHHHEHEHEH HH菻HEH     ÐUHHH}HEHtUHHH}HuHEHH9Er%H H5 H HѺ(  H{HEH[HUHiҸ   HÐUHHH}HEHPHEH H)HHHHEHHEHHHEHÐUHH0H}HEH\HUHRHMH	HMHUHEHUHEHH>HEH!UHH H}HEHEHEHEHEHUHSHH}HuHEH,HHEHH9u;HEHHHEH]HHEHHH踋u       H]UHHH}HEHÐUHHH}HEHHE  tHEHHHEHH
UHH}HE  ]ÐUHHH}HEHHEHHHEHHUHHH}HEHHE   tHEH軤HcHEHH]	UHH}HE   ]ÐUHHH}HEH>HEHRUHHH}HEHHEH(HHEHHUHHH}HEHؔHt"H H H   H֥HEHUHHH}HEH0H(HEHÐUHHH}HEH<HE@XtHEH^H&HEHsHÐUHH}HE@X]UHHH}HEHğHEHHHEHH6UHH}HuHEHE 8]ÐUHH}HEH ]ÐUHHH}HEHHUHH}HuHUHEHEHEHUHUHEHEHEHEHEHEHUH]UHH H}HudH%(   HE1HUHEHHDE HEH4|HUHHEHHHEdH+%(   tzÐUHHH}HEHtHEHPHEHHlÐUHH}HE]UHSHH}HEH{HHEHڑH9tHEH@H       H]UHH}HuHEHUHP]ÐUHH}]ÐUHH@H}dH%(   HE1HHEHEHIHEHEHEHEHEHHEHUHEHHxH HHUdH+%(   tyÐUHHH}HEHUHHH}HEH
UHHH}HuHEHtHHHHҐÐUHH}HE@]UHATSH0H}HuHEL`HEHyHHEH訌HEH]LeHUHMHEHHH0[A\]UHHH}HEH辨UHH}HE]UHH}HEH ]ÐUHH}HEH ]ÐUHSHH}HEHHHEH2|Hi   HH]UHH}]ÐUHH@H}HuHUH} t0HEHEHEHEHEHEHUHMHEHHUHH}HE]UHH}HEH     HEH@    HEH@    ]UHH}]ÐUHHH}HE  u%H8 H5 H HѺ  HRrHEUHSHH}HEHHHEH蠐HHUHEHH]UHHH}HE  u%H H5" H HѺ  HqHEÐUHH}HuHE]UHH}]ÐUHHH}HE   u%H H5 H HѺ  HDqHEUHHH}HE   u%H H5^ HW HѺ  HpHEÐUHH}HuHE]UHHH}HEHvUHH}]ÐUHHH}HE@Xu%H# H5 H HѺ  HepHEÐUHHH}HE@Xu%HX H5 Hz HѺ  HpHEUHH}HuHE]UHH}HEHEHEHEHE]ÐUHHH}HEHH{UHHH}HEH蜄UHHH}HEH>UHH H}HuHEHEHEH2HE HEH;EuݐÐUHHH}HEH蒵tHEH菍HUHHH}HuHm   HEH
HEH;Eu␐UHH}HE]UHH}HEHEHEHEHE]UHHH}HEH{ÐUHH H}HuHUHUHEHHUHHH}HEH迂ÐUHH H}HuHUHEHHHEHHJUHHH}HEHÐUHSHH}HEHHEHԮH9H]UHHH}HEHUHHH}HEHqUHH}HEH]UHH}HE]UHH}HE]fUHcH HHHdH%(   HE1? HEHfH u1? HEHF f     H u1? HEHFf     H u1? HEHFf     H u1? HEHFf     HH u?0FY0FXH1Ҁ HEHV8fHx u1Ҁ8 HEHV@f     Hx u1Ҁ8 HEHVHf     Hx u1Ҁ8 HEHVPf     Hx u1Ҁ8 HDHF(HEdH+%(   up UHcHU HHHdH%(   HU1Ҁ8 HEHVHx u1Ҁ8 HEHVf     Hx u1Ҁ8 HEHVf     Hx u1Ҁ8 HEHV f     Hx u1Ҁ8 HEHV8f     Hx u1Ҁ8 HEHV@f     Hx u1Ҁ8 HEHV(f     Hx u1Ҁ8 HEHV0f     Hx u1Ҁ8 HEHVHf     Hx u1Ҁ8 HEHVPf     Hx uff  x0fdF`f`fn ffofqfafFXHEdH+%(   unf     UHAWAVAUAATSH(dH%(   HE1=f]u  tf9=U]u HF]u    DxIH   =]u     L5s E1LH{LH0 x   IHHuH=\u HE\HEL%\u \u H\u fD-\u H\u \u HUdH+%(   ueH([A\A]A^A_]    H=i\u H	RHJ\u LHEHE     KHLT1vm@ UHAWAVAUATSH   HHHXdH%(   HE1H   WI   HǅP    IfD  LPIM&HH t#Ict$H HHH-   1   H`1HH IcD$HHEAD$tEfD  I$H`<H` tLLH`Xu,HA;\$rHPAFH9P81fD  HUdH+%(   u@HĘ   [A\A]A^A_]    HPAFHPH9sIIM&kff.     UHAWAVAUATSH   HXHHH8H0L(dH%(   HE1H  G  H8   H] E1L`H@kf.     H8ԩ      H0    H(HXL0=   HXI@I9/  HXLHHHcsH@HH tHHtHcsH@HDc   LHP1HAxHuE1C,HPLHcË<H`HDkE9}@fD  Dcf.     1HUdH+%(     Hĸ   [A\A]A^A_]H0 tH(HXL0=uHXH@H9r, ff.     H 1L`H@HXIL@IHHL0IcvLHttIcvLAV1   LM.HЃgHuLAHA| PH` AFEu3i@ ff.     UHAWAVAUATSH(dH%(   HE1HtGItuHE    IE1L5      LLHI$HcsLtCHEAD$II9rHEdH+%(   u HEH([A\A]A^A_] HE    Yhf     UHAWAVAUATSH   HXdH%(   HE1H   I׋WI   HhHǅP    HH@ ff.     HH1   LPHIM&H IcD$HH`AD$tE1I$H`<Hx tLLH`Xu,HA;\$rAVHPH9Pf1@ HUdH+%(   uHĘ   [A\A]A^A_]gf.     UHAWAVAUATSH   HXH0L(dH%(   HE1H  GHm  H  H H8E1HPrf.     H8   6  LHH@H0 *  H(HH`0=
  CII9   MIL#Ict$HPHX tHX<tIct$HPM$Ed$Hh1   HAxH`E1H@LHMC,H`HcA<HhHDkE9}H@LHCII92f.     f     Dcf.     1HUdH+%(      Hĸ   [A\A]A^A_]H E1HPMLPHXIL+IcuLHttZIcuLAU   1Mu HhHx5H`L`LAHcA<Hh t"AWEuًCII9i@ H0HH(HL=t(d     UHAVAUATSHdH%(   HE1H   L/L%˺ HLL   I$x L   I$ L   H{0IHt}@tvE1AFII9scLHHIVHcrL虙tIFHUdH+%(   uFH[A\A]A^]D  VHH@Huf.     1@ L5s vb    UHHdH%(   HE1HEdH+%(   u	HNs b     UHHdH%(   HE1HP HHEHUdH+%(   ujbf.     UHHdH%(   HE1HEdH+%(   u	Hs (b     UHAUATIH=  SHs HdL,%(   LmI@ H{0H0Ht LuH{LskuH{HEdH+%(   uHH[A\A]]af     UHAUATIH=  SHs HdL,%(   LmI@ H{0H0Ht LuH{LjuH{ HEdH+%(   uHH[A\A]]	af     UHAUIATSHys HdL$%(   LeI H0H{ t1LLHtHUdH+%(   uH[A\A]]`fUHAUIATSHs HdL$%(   LeI H0H{ tLLHtHUdH+%(   uH[A\A]]$`@ UHH=PE HSHdH%(   H]15Hs HEHUdH+%(   uH]_ ff.     UHHdH%(   HE1HEdH+%(   uHH1H=s |_ff.     UHHdH%(   HE1HEdH+%(   uHHH=ps ._ ff.     U   HAWA   AVAUE1ATSHڵ HdL$%(   LeI?[ +    E~E9BCL= Hck HHc<AHLAAAt0yEnE9~1HUdH+%(   u(H[A\A]A^A_]D  McHk JcDHO^f.     D  UHHdH%(   HE1HEdH+%(   uHGH@  ^ UHHdH%(   HE=wHEdH+%(   uH]UHHdH%(   HEHcG HUdH+%(   u]fff.     UHAVAUATSHdH%(   HEHF     IHIIH  1LHP   H  H袝IFIT     LHP     HnIFI      LSHP      H:IF I      LHP      HIF(I      LHP   t|H֜IF0I      LHP   tLH覜IF8It\   D  H舜IDHI9t:HLoHP   uHKt H5k H8̇D  1HUdH+%(   u%H[A\A]A^]Ht H5C H8茇u[D  UHAUATSHdL,%(   LmI   IHt$1I|ѪHLHHeHuHEdH+%(   uHL[A\A]]Z    U1Ht HSHHLEHdH4%(   HuHH6C HE    |ct(H}HHCHUdH+%(   uH]øtZ@ UHHHdH%(   HE1lHUdH+%(   uH4Z@ UHSHdH%(   H]HHHEdH+%(   uHCHH]H@  YU1Ht HSHHLMLEHdH4%(   HuHH%B EEbbt.u}SHHCHUdH+%(   uH]@ TY@ UHHHdH%(   HE1\HUdH+%(   uHY@ UHSHdH%(   H]HHzHEdH+%(   uHCHH]H@  XUHHdH%(   HE1HEdH+%(   uHGH8)WX@ UHth    HH D]  `  dH%(   HE1Dd  1H}AAx-H}VH}HEGHEHUdH+%(   uf苮W@ UHh@    HH dH%(   HE1H}x,H}SVH}HEHEHUdH+%(   u
ÐW@ U1Hg    HH Lh  dH%(   HMH`  H}x.H}UH}HEXHEHUdH+%(   u 蛭W@ UH     1HH(dH%(   HM`  RHCg x  p  Lh  Dd  H}xH x0H}7UH}HEHEHUdH+%(   uD  dV@ UHHdH%(   HE1HEdH+%(   ud  `  1H=f [{VfD  UH5  H* HHX  Hp  dL%(   LELx  Hh  HDHEdH+%(   uH=f 1zUfD  UH|m  H52c  HHX  `  dH%(   HMd  p  HDDl  Dh  1H=f zHUdH+%(   u*Uf.     UHHdH%(   HE1HEdH+%(   u"d  `  Hh  1H=Yf zT@ ff.     UHHdH%(   HE1HEdH+%(   uHGH= = H01y{Tff.     U   IHH	f HATSHHPLXLPH   dH%(   HE1HǅH    ǅ    ǅ    ǅ     ǅ    ǅ    HLHDHǅh  ǅ    Ht ǅ    ǅ    ǅ    ǅ    ǅ     ǅ$   ǅ(    ǅ,    ǅ0    ǅ4    ǅ8    ǅ<    ǅ@   ǅD    PHEPHEPHEPHEPH@PH<PH8PH4PH0PH,PH(PH$PH PHPHPHPHPHPHPHPH PHPHPHpPHhPHHPH`P1/[H     HHHtH`   H`H{HPǅT    	Ѝ    	Ѝ    	Ћ	Ћ 	Ћ@	Ћ	Ћ   	Ћ 	   	Ћ$
   	Ћ(   	Ћ,   	Ћ0    	Ћ4 @  	Ћ8  	Ћ<   	Ћ@   	Ћ   	Ћx  	ЋDxx1HUdH+%(   uHe[A\]@ P@ UHAVAUATIH=(t SH dL,%(   LmIE    E    H  HHM1LHUH58 c  I$   u0AŅ'  I$   uA4  I$  HK  I$  H@I|$IcIcH;P  H;H   LLHLLOL
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(HDHM_HMoCoAC HA HC0I$H)CID$H)CID$H)C oA$oAAD$HA ID$ HEdH+%(      H H[A\A]A^]     His UH5` H81ED  1@ HAs UH5` 1H81f     I$   EI$   A蠻DǉEI$  Ht6}D~I$  HtI$  DEZD  E1軤HN ff.     UHSH(dH%(   H]HH=,t 藂HHtH   HEHUHBHEdH+%(   u	H]HMf.     UHSH(dH%(   H]HH=t 'HHtH   HE߾HUHBHEdH+%(   u	H]H:Mf.     UHSH(dH%(   H]HH=Lt 跁HHtH{0HErHUHBHEdH+%(   u	H]HLfff.     UH4t 1HSHHLMLEH(dH4%(   HuHHUE    RHURH5 HE    HE    E    (UZY}   HMH{HtHIHuHtHvUCH	HʈCHJx/HXs wHUdH+%(   uH]@ Hs H8Q1K     UHATSHdH%(   H]H_HHI-DHUdH+%(   uHLH1[H=4 A\]p]Kfff.     UHSHdH%(   H]HHzHEdH+%(   uHCHH]H@  KU1HSHMHUH(dH%(   H]HHH53 HE    HE    :t6HEH{HPHEHpX1HUdH+%(   uH]fD  tJ@ UHHHdH%(   HE1,AHs =wHEdH+%(   uHJ ff.     UHHHdH%(   HE1,AH5s =wHEdH+%(   uHI ff.     UH    HH  dH%(   HE1HHH8 HzHs ƅ3ff)Hb ǅ`HTHEE   HE.Hgs =wHEdH+%(   uHHU1HSHUHdH%(   H]HHH54 >tZHuH{=w	HuC H   Us H=  1HUdH+%(   uH]     1WH    U1Ht HSHHLEHdH4%(   HuHH0 EPtHuH{x)H=  1YHUdH+%(   uH]@ Hs H8A1G     UHHHdH%(   HE1|Hs =wHEdH+%(   uH^G ff.     UHSHdH%(   H]HHzHEdH+%(   uHCHH]H@  GUHSHdH%(   H]HHtHEdH+%(   uHCHH]H@  FUHH dH4%(   Hu10  HHt1HE<=HUHBHEdH+%(   uH[Fff.     UHAVATSHH8HdL$%(   LeIt2HEdH+%(     H8LH[A\A^]:f.     jIH= wHtLSHtHHEreHUH   HLHU&HUHx  HcHAHq8L   Q,H8A(@   @   I< u@HMHMHa8HHUdH+%(      H8[A\A^]D  HMUH}DH}ȋUHMtC     H<fD  HHMI4 iHMHHA8ujtf1P@ HHML<HM I4 HMLEHMLEȉHq8   y,y(f!DU1Hbt HAVATIHLMSLEH(dH4%(   HuHH, E   L  IcT$@Mԅ  Hi   I$  Hf     H   H9`  C9uHO(  HHH  BvBz  Ff=H?  Hs HuH<wHB  HuHX  HEIVHuI|$gHMHI   HAHHMHMLLHQ[HMȅt?xuHωEw:EHs H5T H:1H    HEdH+%(      H(H[A\A^]ËyGf     Hs =wf     Hs H5* H81膌1뒃uH9Hws H  H5T H81QlHTHMs H5* H81,AD  UHAVAUATSHdL,%(   LmI1IAMP~wE1fD  IE9eP~bIE`E1E1HN  H5<  B<j j \eHXZHt]HLgquAxuHI8E9ePHEdH+%(   uJHeL[A\A]A^]D  xt HEdH+%(   uHe[A\A]A^]EH}8@fD  UHAWAVAUATSHdH%(   H]H1H   L
  IMtlM~(Mn(M9uJD  M?M9t=I>HHtgHLdpuXx҃uH7M?M9uLKIHu HEdH+%(   u>HL[A\A]A^A_]    A$x	A$tE1fLE1u7? ff.     UHATSHdL$%(   LeI1HtmI|$H1HHA  ,Aąu%HEdH+%(   uPHH[A\]f.     xt#.DډH8s H8x1@ H6>UHHdH%(   HE1HEdH+%(   u1H=Lt g>fUHAWAVAUATSHH=t HdL4%(   LuE1 sIH  L`HxH@    HLHǀ      LH)   HLHS(Hs KL;L9u    LLEKM?L9   H=ҿt A   rHtLpHxH@    HLIwHǀ      H)1  HLA   eLLA9M9   tLLid@ M	M9  L謁IHN  HEdH+%(     HL[A\A]A^A_]MuM9u&   D  I  L9   M6M9   L脇HL9tHH9  1H H9  H9uIu1I9u       H6I9  9uL腱I  L9}HH9l  1H H9Y  H9uIE1I9u  H I9q  9uI  M6M9.H
  I
  1LM
  MHH9tAIK1fH H9t,H9uIE1I9u7  H I9(  9uICMK(MS(M9D     Iy8HH LI   D  LL91H H9   H9uIE1I9u    ff.     H I9   9uHMq8I<6HHLHHM  HLLԯJ1Lů;1I  fI<6HH@H'    1l1:fff.     U`  HSHHLLHH  dH%(   HE1Hǅ    Hǅ    Hǅ    HHHH5" 膿   HHtHRHHtHvHRGHHj  HA   HHHDHE11j jj ?H u=HHHlHHUdH+%(   u0H]feډHls H8z1#9 U`  HAVAUHHATLSH@  dH%(   HE1Hǅ    Hǅ    HHHH5! 2   LMtMmLMtMd$HQLLHEH1E1j HHA   HpZYu:HHIkHEdH+%(   u7HeL[A\A]A^]HHݰHs H8^yE17@ UH1Ht HH dH4%(   HuHLMLEHE    H|  HE    T@t0H}Hu3HcHUdH+%(   uf.     1G7    UHATSHdH%(   HE1m1IcHtvLHH5q  HɰAąu2HH=X  nAąuHEdH+%(   uGHH[A\]Ðxt#DډHs H8x1@ HX.6UHHdH%(   HEHcG H9~VHGHH9u @ ff.     H HH9tHuHUdH+%(   uAHpH=  1}D  Hs H5 H8bHEdH+%(   u15f.     UHHHdH%(   HE1x(Hs wHUdH+%(   uÐHs H8v1h5     U1Hrt HSHHLMLEHdH4%(   HuHH E   E    =tNuH{bx.HGs wHUdH+%(   uH] Hs H8Av14    UHSH(dH%(   HUHWHtMHH=þt .iHHtH{HEHx%+HUHCHEdH+%(   u'H]HD  Hs HUH8mHU"4fUHATISHHdH%(   H]H%jHH9~6I|$bZHUdH+%(   uKHH=V  1[A\]+ HYs H5 H8_HEdH+%(   uH1[A\]3 UHATISHHdH%(   H]HuHH9~>I|$貎HUdH+%(   uSHH=  1[A\]f.     Hs H5 H8
_HEdH+%(   uH1[A\]2ff.     Uf   H5 HAVAUATSH Hfs dL,%(   LmIH})EHEdI]II9uBtfD  軭H  H5Q  H}H1H<AHL9tB,   H}FHH   utHIILH}H
dHL9u   H5 H}cH}0H}HHEdH+%(   uH H[A\A]A^]1@ UHHdH%(   HE1HEdH+%(   uHGH@  s1 UHHdH%(   HE1HEdH+%(   uHGH@  31 UHAVIHATSH(dH%(   H]H/IH/MHH ujMtEA$xA$t$@ HEdH+%(      H([A\A^]LHMt(HMHt1ۋxÃuHT(fHLLHMާHMȅA$u"xŃA$uLHM(HM xA$uLHM'HM0ff.     UHAUIATSH(dL$%(   LeI觽H  IT$HHtH5j  HZ  IT$HtH5  Hq9  IT$HtH5 HP  IT$ HtH5 H/   IT$(HtH5  H   IT$0HtH5> H   IT$8HtH5  H   IT$HHtH5
 HtwIT$PHtH5 HtZA|$X u:HL^uCxtNHUdH+%(   uaH([A\A]]@ H HH6ufxt#@ H߉E&E     H%!.U1HAWAVHMHUAULEATSHhdL$%(   LeIHH5% E    E    HE    H  M$
  Ml$M  LeMf(M~(M9  I|$Hu_  ID$8H HN  HMHYI9u5<  fD  ff.     ff.     HL9  ID$8H H9  uH   uxH   uE}xMH]MEM$D]HUHHE  Md$8Mo@McI$IHm  LxIHUL}D]      I  HcUHXH;S  L;s   H;HCHIHD(HHFH;P
L;p  HpHLIHT2(uLULE<LEI H+w  fH*I@H+C  fH*I@H+C  fH*f.Ѻ   Etff.EtY^UH}L蔪v  M,$IM+  L;HzIH  HMH  Ht H  H  H9tI;    LYEI  HI   8aI   މǉE[I  H8  }t[I  H  HXI  HcUH;S4ff.     1Cf     HfHH	I@H*XH+CyHfHH	I@H*XH+CiHfHH	H*XT@ M$$M9~L[nIHYDEMH5a< Hjs HUH81Ltff.     1HUdH+%(     Hh[A\A]A^A_]@ H  HH9fH;  t!ff.     H H9EH;  uL9  uE   I/ L}LxMtXI}  tQH] II}  t=LHʁtH}$H3s H8sjfD  IWHuH}AtHE    H}貂E8; ;(f.     UHAWAVAUATISH(HUdH%(   HE1 H  H= H&HEH  1IH  M|$Mu:@ HL)  M~;   L+IHuLH  HuLHC,  IT$HtH5 H:  I$HtH5Q  Hb  IT$HtH5 HA   IT$ HtH5 H    IT$(HtH5 H   IT$0HtH5 H   IT$8HtH5~ HtyIT$@HtH5r Ht\H}H WuLxkudH߉EtETHMx'  AE xAE u	LAx   @ ff.     HUdH+%(      H([A\A]A^A_]f     LIH LLAVAAtCMLHŧIHLLUAAuLs볐HE "HMHKfD  H8H+Q%UH=$t HAWAVATSH dH4%(   Huؾ  uIH  Hs HH=>t H't Ht Hat Ht Hst Ht HEt Ht H7t 躊R  H=t 覊>  H=t 蒊*  H=t ~  H=t j  H=t V  H=Gt B  H=st .  H=?t Hpt   H=t Ht   H=)t HZt ݉u  H=t H?t Z  H=St 讉F  H=߭t Ht 蓉+  H=$t HUt x     薬Hst wt =w	gt H`t H5 L]t =w	t Ht H5f L\?t =w	/t H(t H5 L\t =w	t Ht H5 L\t =w	t Ht H5 La\t =w	t Ht H5 L5\t =w	t Ht H5| L	\Ct =w	3t H,t H5 L[Wt =w	Gt H@t H5 L[˵t =w	t Ht H5 L[߱t =w	ϱt Hȱt H5i LY[t =w	t Ht H5 L-[t =w	wt Hpt H5 L[t =w	t Ht H5 LZL-IIHt`L5s H5kB  D  IvIFIHt;Ic~HuSpHHt&HuHL̙xƃuHW@DHtHs H5
 H8uLD  HEdH+%(   uH L[A\A^A_]< f.     fH t 1.6  HH                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               %d [  ,   %s%d  ]       /sys /proc /sys/kernel/debug /debug /sys/kernel/tracing /sys/kernel/debug/tracing /tracing /trace               /sys/fs/bpf sysfs procfs debugfs tracefs hugetlbfs bpf r /proc/mounts %*s %4096s %99s %*s %*d %*d
 fs/fs.c !fs->path fs->path PERF_%s_ENVIRONMENT %d %s/%s %s/sys/%s    fs__init_once   %s/%s  tracing/ %s%s %s/events/%s events * sdt_ Error:	File %s/events/%s not found.
Hint:	SDT event cannot be directly recorded on.
	Please first use 'perf probe %s:%s' before recording it.
  Error:	File %s/events/%s not found.
Hint:	Perhaps this kernel misses some CONFIG_ setting to enable this feature?.
     Error:	Unable to find debugfs/tracefs
Hint:	Was your kernel compiled with debugfs/tracefs support?
Hint:	Is the debugfs/tracefs filesystem mounted?
Hint:	Try 'sudo mount -t debugfs nodev /sys/kernel/debug' %s        Error:	No permissions to read %s/events/%s
Hint:	Try 'sudo mount -o remount,mode=755 %s'
 r /proc/mounts cgroup  ,      devices/system/cpu/online       devices/system/cpu/cpu%d/cpufreq/cpuinfo_max_freq       INTERNAL ERROR: strerror_r(%d, [buf], %zd)=%d   mmap_per_cpu    mmap_per_thread overwrite_rb_find_range cpu_map refcnt unbalanced
 devices/system/cpu/online thread map refcnt unbalanced
 libperf: move evt_head: %lx
  Fatal:  PWD Too long path: %.*s PREFIX %s%s/%s /usr/local/bin:/usr/bin:/bin LINES COLUMNS Out of memory, realloc failed perf- %s%s/ help.c cmds->names[ci] == NULL available %s in '%s'
 FRSX LESS /usr/bin/less /usr/bin/pager PAGER cat -c -%c --%s [=<n>] [<n>]  <n> [=<%s>] [<%s>]  <%s> [=...] [...]  ... %*s%s
 %*s(not built-in because %s)
   Error: %s
 
 Usage: %s
     or: %s
  Error: switch `%c' %s  Error: option `no-%s' %s  Error: option `%s' %s is being ignored because %s  is not available because %s takes no value isn't available is not usable cannot be used with %s requires a value  Warning: switch `%c' %s  Warning: option `no-%s' %s  Warning: option `%s' %s expects a numerical value vasprintf failed no- %s%s %s [<options>] { help-all list-opts list-cmds --%s  %sunknown option `%s' %sunknown switch `%c' exec %s: cd to %s failed (%s) /dev/null /proc/%u/status State:  Error: waitpid failed (%s) BUG: signal out of range: %d color.ui libperf-gtk.so Error:
 Warning:
 Should not reach here
 %.*s %s %.*s  %*.1f  %*.2f%% Self Overhead latency guest sys guest usr Children Samples Period Weight1 Weight2 Weight3 Mem Op Snoop D-TLB |           Not enough memory!                 %s
 |
 Bad callchain mode
  /  %s%-.*s %*sno entry >= %.2f%%
 %.10s end
 UNKNOWN %20s events: %10d  (%4.1f%%)
 %20s events: %10d
 colors. Press any key... Warning! 
'%s' key not associated%s!
 default medium green normal selected black yellow blue magenta white End Home Del Backspace Untab F1 Right PgUp PgDown Left Ctrl+%c F%d Unknown (%d) No source file location. Source file location: %s [Type] assertion failed at %s:%d
 %s  %s [Percent: %s] %s Couldn't annotate %s:
%s String not found! On Press ESC to exit  [source: %s] ENTER: OK, ESC: Cancel String:  Search Invalid jump offset: %lx ui/browsers/annotate.c , use 'h'/F1 to see actions local hits global hits local period global period  %10s %10s  %*s};  %10lu  %10d  %10.2f  %#10x %#10x  %s%s  %#10x %#10x  %*s%s	%s%s %*s %10s %10s %10s  %s Field %*s%c %s
  lost: %lu/%lu  drop: %lu/%lu  [z]  -c %s   -S %s   --time %s,%s # Samples: %lu  of event '%s' %lu%c%s%s : %ld%c%schunks LOST! <...> no entry >= %.2f%% the Kernel Run scripts for all samples%s %.*lx Annotate %s ui/browsers/hists.c out of into Collapse Expand Collecting samples... perf.hist.%d Couldn't write to %s: %s %s written! Verbosity level set to %d
 Symbol to show Percent Limit Invalid percent: %.2f Do you really want to exit? Annotate type %s Zoom %s %s(%d) thread Zoom %s %s thread Browse map details Zoom %s Processor Socket %d with assembler with source Exit Available samples ? - help Branch counter abbr list , use '?' to see actions %*lx %*lx %c  restart with -v to use Search by name/addr %s not found! scripts. Running %s
 Cannot run %s
 [c[H[J  --inline -i  perf script -s  Show individual samples %s script %s -F +metric %s %s -F +disasm -F +srcline,+srccode %s/scripts Failed to open directory '%s' perl top. %s/scripts/%s/%s bin/%s-record -e  	 perf script command %s script %s %s%s %s %s%s 2>&1 | less Press 'q' to exit Header information samples.context --tid  --cpu  %s: CPU %d tid %d --show-lost-events  [m TUI initialization failed.
 ^(kB) Fatal Error perf -------- backtrace -------- Warning: Error: Help Enter: Yes, ESC: No %s [%s/%s] arm64 ^blr?$ bez bnez bnezad bhsz bhz blsz blz jmpi bsr rts jsri jsr csky jirl bltu bgeu loongarch bgezal bltzal bgtzal blezal beqzal bnezal bgtzl bltzl bgezl blezl jialc beql bnel jal jr mips __fentry__ call [%x] %s
 call [%x] return -> reg%d this_cpu_off add [%x] offset %#lx to reg%d add [%x] percpu %#lx -> reg%d sub [%x] offset %#lx to reg%d imul idiv shl shr sar neg dec %s [%x] invalidate reg%d
 xor xor [%x] clear reg%d
 mov [%x] imm=%#x -> reg%d
 mov [%x] reg%d -> reg%d mov [%x] -%#x(stack) -> reg%d mov [%x] %#x(reg%d) -> reg%d __per_cpu_offset mov [%x] percpu base reg%d
 mov [%x] reg%d -> -%#x(stack) mov [%x] reg%d -> %#x(reg%d)  reg%d offset %#x -> test sub x86 %*[^,],%u,%u,%u AuthenticAMD bwlq adc andps bt btr cmovae cmovbe cmove cmpxch cmpxchg divsd divss ja jae jb jbe jc jcxz je jecxz jg jge jl jle jna jnae jnb jnbe jnc jne jng jnge jnl jnle jno jnp jns jnz jo jp jpe jpo jrcxz js jz lea mov movapd movaps movdqu movsb movsl movss movsw movupd movups movzb movzl movzw mulss nop paddq pcmpeqb por rcl sbb sete tzcnt ucomiss vaddsd vandpd vmovdqa vmovq vmovsd vmulsd vorpd vsubsd vucomisd xadd xbegin xorpd xorps %-*s %s brinc bper bnl bnl+ bnl- bnla bnla+ bnla- powerpc mulli subfic addic addic. addi addis SUB_CARRY_XO_FORM MUL_HDW_XO_FORM1 ADD_CARRY_XO_FORM MUL_HW_XO_FORM1 SUB_XO_FORM MUL_HDW_XO_FORM MUL_HW_XO_FORM SUB_EXT_XO_FORM ADD_EXT_XO_FORM SUB_ZERO_EXT_XO_FORM ADD_ZERO_EXT_XO_FORM SUB_EXT_XO_FORM2 MUL_DW_XO_FORM ADD_EXT_XO_FORM2 MUL_W_XO_FORM ADD_XO_FORM DIV_DW_XO_FORM1 DIV_W_XO_FORM1 DIV_DW_XO_FORM DIV_W_XO_FORM OP_31_XOP_LXSIWZX OP_31_XOP_LWARX OP_31_XOP_LDX OP_31_XOP_LWZX OP_31_XOP_LDUX OP_31_XOP_LWZUX OP_31_XOP_LXSIWAX OP_31_XOP_LDARX OP_31_XOP_LBZX OP_31_XOP_LVX OP_31_XOP_LBZUX OP_31_XOP_STXSIWX OP_31_XOP_STDX OP_31_XOP_STWX OP_31_XOP_STDUX OP_31_XOP_STWUX OP_31_XOP_STBX OP_31_XOP_STVX OP_31_XOP_STBUX OP_31_XOP_LHZX OP_31_XOP_LHZUX OP_31_XOP_LXVDSX OP_31_XOP_LWAX OP_31_XOP_LHAX OP_31_XOP_LWAUX OP_31_XOP_LHAUX OP_31_XOP_STHX OP_31_XOP_STHUX OP_31_XOP_LXSSPX OP_31_XOP_LDBRX OP_31_XOP_LSWX OP_31_XOP_LWBRX OP_31_XOP_LFSUX OP_31_XOP_LXSDX OP_31_XOP_LSWI OP_31_XOP_LFDX OP_31_XOP_LFDUX OP_31_XOP_STXSSPX OP_31_XOP_STDBRX OP_31_XOP_STXWX OP_31_XOP_STWBRX OP_31_XOP_STFSX OP_31_XOP_STFSUX OP_31_XOP_STXSDX OP_31_XOP_STSWI OP_31_XOP_STFDX OP_31_XOP_STFDUX OP_31_XOP_LXVW4X OP_31_XOP_LHBRX OP_31_XOP_LXVD2X OP_31_XOP_LFIWAX OP_31_XOP_LFIWZX OP_31_XOP_STXVW4X OP_31_XOP_STHBRX OP_31_XOP_STXVD2X OP_31_XOP_STFIWX riscv bras brasl basr lrl lgrl llgfrl strl stgrl s390 jmpl retl sparc ??:0 .debug_line -a -f 	%c%s %016lx
,
 local global ↓ ↑ ← → 
Sorted summary for file %s
  Nothing higher than %1.1f%%
  %7.2f annotate. annotate.offset_level annotate.disassemblers llvm capstone Invalid disassembler '%.*s'
 annotate.hide_src_code annotate.jump_arrows annotate.show_linenr annotate.show_nr_jumps annotate.show_nr_samples annotate.show_total_period annotate.use_offset annotate.disassembler_style annotate.objdump annotate.addr2line annotate.demangle annotate.demangle_kernel %s: addr=%#lx
 account_cycles failed %d
 %s: unsupported arch %d
 %#lx %s %.*s %s
  '-' No event occurs
 # Branch counter abbr list:
  %s = %s
 =- %gs: ,)  push [35m [31m [34m  %7lu  %11lu   %*lx: 	#  +%.2f%%  -%.2f%% (p:%.2f%%) 		# data-type: %s  +%#x  // %s  %*s:
  %*s: %-*d %s
 Percent util/annotate.h %-*.*s----
 %*lx: %lu
 h->nr_samples %*s: %lu
 %11lu  %7lu  %7.2f  %*.2f  IPC %*s  %*lu  %lu(%lu/%lu) Cycle(min/max) Branch Counter %-*s   %lx:  %*lx:  %s, [percent: %s]
%s() %s
 %s.annotation %s() %s
Event: %s

 (stack canary) (stack operation) [%s -> %s] [%7lx -> %7lx] %.1fM %.1fK %1d [unknown] Sampled Cycles% Sampled Cycles Avg Cycles% Avg Cycles [Program Block Range] %s/sys/kernel/notes %s/%s/%s/kallsyms [kernel.kallsyms] %s/%s/%s %s/.build-id/%.2s/%s %s/.build-id/ Error in lsdir(%s): %d
 [vdso] %s%s%s%s%s vdso /usr/lib/debug/.build-id/ %.2s/%s.debug Can't read link: %s
 Found %d SDTs in %s
 true yes false core. core.proc-map-timeout core.addr2line-timeout hist. ui.show-headers call-graph. buildid. buildid.dir Invalid buildid directory!
 stat. stat.big-num stat.no-csv-summary stat.bpf-counter-events addr2line. /etc/perfconfig %s: strdup failed
 ﻿ PERF_CONFIG_NOSYSTEM PERF_CONFIG_NOGLOBAL HOME %s/.perfconfig Missing value for '%s' PERF_BUILDID_DIR %s.XXXXXXx no branch trace begin / %s %s / trace end unconditional jump software interrupt return from interrupt return from system call asynchronous branch hardware interrupt transaction abort trace begin vm entry vm exit (%r %-*s %.*s%lx %-*s %s,%s %-*s *%lx (%rip) ^/[^:]+:([0-9]+) %-*s  Invalid BPF file: %s. --prefix-strip= --prefix  -S --no-show-raw-insn -l -M  /bin/sh to be implemented Executing: %s
 Failure starting to run %s
 Error running %s
 No output from %s
  nop   nopl   nopw  %#lx <%s>: Disassembled with %s
 EXPERIMENTAL_KEY_INSTRUCTIONS ENOENT ESRCH EINTR ENXIO E2BIG ENOEXEC EBADF ECHILD EAGAIN ENOMEM EACCES EFAULT ENOTBLK EBUSY EEXIST EXDEV ENODEV ENOTDIR EISDIR EINVAL ENFILE EMFILE ENOTTY ETXTBSY EFBIG ENOSPC ESPIPE EROFS EMLINK EPIPE EDOM ERANGE EDEADLK ENAMETOOLONG ENOLCK ENOSYS ENOTEMPTY ELOOP ENOMSG EIDRM ECHRNG EL2NSYNC EL3HLT EL3RST ELNRNG EUNATCH ENOCSI EL2HLT EBADE EBADR EXFULL ENOANO EBADRQC EBADSLT EBFONT ENOSTR ENODATA ETIME ENOSR ENONET ENOPKG EREMOTE ENOLINK EADV ESRMNT ECOMM EPROTO EMULTIHOP EDOTDOT EBADMSG EOVERFLOW ENOTUNIQ EBADFD EREMCHG ELIBACC ELIBBAD ELIBSCN ELIBMAX ELIBEXEC EILSEQ ERESTART ESTRPIPE EUSERS ENOTSOCK EDESTADDRREQ EMSGSIZE EPROTOTYPE ENOPROTOOPT EPROTONOSUPPORT ESOCKTNOSUPPORT EOPNOTSUPP EPFNOSUPPORT EAFNOSUPPORT EADDRINUSE EADDRNOTAVAIL ENETDOWN ENETUNREACH ENETRESET ECONNABORTED ECONNRESET ENOBUFS EISCONN ENOTCONN ESHUTDOWN ETOOMANYREFS ETIMEDOUT ECONNREFUSED EHOSTDOWN EHOSTUNREACH EALREADY EINPROGRESS ESTALE EUCLEAN ENOTNAM ENAVAIL EISNAM EREMOTEIO EDQUOT ENOMEDIUM EMEDIUMTYPE ECANCELED ENOKEY EKEYEXPIRED EKEYREVOKED EKEYREJECTED EOWNERDEAD ENOTRECOVERABLE ERFKILL EHWPOISON (unknown) EDEADLOCK EINIT EREMDEV ECANCELLED EPROCLIM ERREMOTE branches branch_counter_nr branch_counter_width duplicated bpf prog info %u
 duplicated btf %u
 pmu mappings not available
 %u:%s x86_64 aarch64 mips64 parisc64 riscv64 s390x sparc64 parisc sun4u sa110 alpha GenuineIntel Old New             %s bytes:  %02x INVALID  exec %s: %s:%d/%d
 
		  %u/%s: %lu/%#lx%s  cgroup: %llu %s
  nr:  (%d:%d):(%d:%d)
  pid: %u tid: %u
  hw_id: %#llx
 OUT         IN          OUT preempt next  %s  %s pid/tid: %5d/%-5d
  type %u, flags %u, id %u
  prog %s
   entry %d: %20s = %s
  %llx   old len %u new len %u
 
cpu%u  %lu  
domain%u   lost %llu
 [hypervisor] <not found>  ... thread: %s:%d
  ...... dso: %s
 TOTAL NAMESPACES KSYMBOL BPF_EVENT CGROUP TEXT_POKE AUX_OUTPUT_HW_ID CALLCHAIN_DEFERRED EVENT_TYPE TRACING_DATA BUILD_ID FINISHED_ROUND ID_INDEX AUXTRACE_INFO AUXTRACE AUXTRACE_ERROR THREAD_MAP CPU_MAP STAT_CONFIG STAT STAT_ROUND EVENT_UPDATE TIME_CONV FEATURE COMPRESSED FINISHED_INIT COMPRESSED2 BPF_METADATA SCHEDSTAT_CPU SCHEDSTAT_DOMAIN dummy:u sched kernel/perf_event_mlock_kb mmap size %zuB
 %s && common_pid != %d failed to create 'ready' pipe failed to create 'go' pipe failed to fork perf-exec unable to read pipe unable to write to pipe 
Hint:	 Shouldn't get there
 Weak group for %s/%d failed
 fifo: Failed to open '%s': %m
 ack
 \0 \n disabled Message from ctl_fd: "%s%s"
 enable disable is snapshot
 Events disabled
 Events enabled
 failed: wrong command
 Event %s %s
 -v -g -F ctlfd: unsupported %d
  , %u - %u %n timerfd_create failed: %m
 timerfd_settime failed: %m
 Pu %s/cycles/%s mem-loads-aux   %-32s %s
 PERF_TEST_ATTR %s/event-%d-%llu-%d w+ [event-%d-%llu-%d]
 group_fd=%d
 cpu=%d
 pid=%d
 flags=%lu
 size=%u
 config=%llu
 sample_period=%llu
 read_format=%llu
 disabled=%d
 inherit=%d
 pinned=%d
 exclusive=%d
 exclude_user=%d
 exclude_kernel=%d
 exclude_hv=%d
 exclude_idle=%d
 mmap=%d
 comm=%d
 freq=%d
 inherit_stat=%d
 enable_on_exec=%d
 task=%d
 watermark=%d
 precise_ip=%d
 mmap_data=%d
 sample_id_all=%d
 exclude_host=%d
 exclude_guest=%d
 exclude_callchain_kernel=%d
 exclude_callchain_user=%d
 mmap2=%d
 comm_exec=%d
 context_switch=%d
 write_backward=%d
 namespaces=%d
 use_clockid=%d
 wakeup_events=%u
 bp_type=%u
 config1=%llu
 config2=%llu
 branch_sample_type=%llu
 sample_regs_user=%llu
 sample_stack_user=%u
 %s/fd anon_inode:[perf_event] %s/cmdline Possible processes:
 %s/%s/comm oprofiled ppp ftrace:function %s:%s unknown-hardware %s-%s-%s unknown-ext-hardware-cache-op invalid-cache unknown-software raw 0x%lx unknown tracepoint mem:0x%lx: unknown attr type: %d anon group %s {  Unknown format value: %d
 (%s) && (%s) offcpu-time msec %.60s
 perf_event_attr:
 cpu-clock task-clock %s%su %s%sH fs/selinux/enforce wrong clockid (%d). switching off bpf_event
 switching off ksymbol
 switching off write_backward
 switching off clockid
 switching off cloexec flag
 switching off mmap2
 switching off sample_id_all
 switching off group read
 Opening: %s
 broken group leader for %s
 test attr FAILED user stack dump failure
 %s/%.*s/%s %s/%.*s,%s %s/%s/ refs Reference prefetch prefetches speculative-read speculative-load L1-dcache l1-d l1d L1-data L1-icache l1-i l1i L1-instruction LLC L2 dTLB d-tlb Data-TLB iTLB i-tlb Instruction-TLB bpu btb bpc page-faults context-switches cpu-migrations minor-faults major-faults alignment-faults emulation-faults dummy instructions cache-references cache-misses branch-misses bus-cycles stalled-cycles-frontend stalled-cycles-backend ref-cycles sample_freq sample_period %s{  %s=%lu  (not a tracepoint)  (no trace field)  trace_fields: %s  <- %c%16lx (cookie) 
  %s 
    (inlined) PERF_TYPE_HARDWARE PERF_TYPE_RAW PERF_TYPE_BREAKPOINT PERF_TYPE_HW_CACHE PERF_TYPE_TRACEPOINT PERF_TYPE_SOFTWARE PERF_COUNT_HW_CPU_CYCLES PERF_COUNT_HW_REF_CPU_CYCLES PERF_COUNT_HW_BUS_CYCLES PERF_COUNT_HW_BRANCH_MISSES PERF_COUNT_HW_CACHE_MISSES PERF_COUNT_HW_INSTRUCTIONS PERF_COUNT_SW_CPU_CLOCK PERF_COUNT_SW_CGROUP_SWITCHES PERF_COUNT_SW_BPF_OUTPUT PERF_COUNT_SW_DUMMY PERF_COUNT_SW_PAGE_FAULTS_MAJ PERF_COUNT_SW_PAGE_FAULTS_MIN PERF_COUNT_SW_CPU_MIGRATIONS PERF_COUNT_SW_PAGE_FAULTS PERF_COUNT_SW_TASK_CLOCK PERF_COUNT_HW_CACHE_L1D PERF_COUNT_HW_CACHE_L1I PERF_COUNT_HW_CACHE_LL PERF_COUNT_HW_CACHE_DTLB PERF_COUNT_HW_CACHE_ITLB PERF_COUNT_HW_CACHE_BPU PERF_COUNT_HW_CACHE_NODE PERF_COUNT_HW_CACHE_OP_READ PERF_COUNT_HW_CACHE_OP_WRITE %lu (%s) %#lx (%s/config=%#lx/) %#lx (%s) %#lx (%s/%s/) %#lx (%s | %s | %s) %#lx (%s/%s | %s | %s/) BRANCH_STACK REGS_USER STACK_USER IDENTIFIER REGS_INTR DATA_SRC WEIGHT PHYS_ADDR DATA_PAGE_SIZE CODE_PAGE_SIZE WEIGHT_STRUCT read_format pinned exclusive exclude_user exclude_kernel exclude_hv exclude_idle mmap inherit_stat enable_on_exec precise_ip mmap_data sample_id_all exclude_host exclude_guest exclude_callchain_kernel exclude_callchain_user mmap2 comm_exec use_clockid context_switch write_backward namespaces ksymbol bpf_event aux_output cgroup text_poke build_id inherit_thread remove_on_exec sigtrap defer_callchain defer_output bp_type { bp_addr, config1 } { bp_len, config2 } KERNEL ANY ANY_CALL ANY_RETURN IND_CALL ABORT_TX IN_TX NO_TX CALL_STACK IND_JUMP NO_FLAGS NO_CYCLES TYPE_SAVE HW_INDEX PRIV_SAVE COUNTERS branch_sample_type sample_regs_user sample_stack_user sample_regs_intr aux_watermark sample_max_stack aux_sample_size sig_data aux_start_paused aux_pause aux_resume x86_64-pc-linux i686-pc-linux %s-linux-gnu intel   # %#lx %p: %s mask[%zd]: %s
 config1 config2 config3 config4 %s'%s'
 event syntax error:  %*s\___ %s
 
%s
 unknown term %s=%#lx No PMU found for '%s'
 <no help> can't access trace events failed to add tracepoint *? nr_addr_filters uid == %d valid terms: %s,%s valid terms: %s expected numeric value expected string value invalid branch sample type expected 0 or 1 too big not a valid PMU or CPU number zero or negative Invalid term_type needs a core PMU %s// Attempt to add: %s
 %s -> %s/%s/
 %s -> fake/%s/
 Bad event or PMU <sysfs term> branch_type call-graph stack-size no-inherit max-stack no-overwrite driver-config percore aux-output aux-action aux-sample-size metric-id ratio-to-prev legacy-hardware-config legacy-cache-config hardware-cache Failed to get buildids: %d
 %s:%s@%s %s@%s(%.12s) SDT event rNNN Raw event descriptor mem:<addr>[/len][:access] Hardware breakpoint %s/%s/id ^(x[1-2]?[0-9]|3[0-1])$ ^\[sp(, )?([0-9]+)?\]$ Regex compilation error.
 %%%.*s +0(%%sp) +%.*s(%%sp) vg %r1 %r2 %r3 %r4 %r5 %r6 %r7 %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 %r16 %r17 %r18 %r19 %r20 %r21 %r22 %r23 %r24 %r25 %r26 %r27 %r28 %r29 %r30 %r31 $1 $2 $3 $4 $5 $6 $7 $8 $9 $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $20 $21 $22 $23 $24 $25 $28 $29 $30 $31 ^(%r)?([1-2]?[0-9]|3[0-1])$ %%gpr%.*s %c%.*s(%%gpr%.*s) nip orig_r3 ccr softe sier mmcra mmcr0 mmcr1 mmcr2 mmcr3 sier2 sier3 pmc1 pmc2 pmc3 pmc4 pmc5 pmc6 sdar siar tp R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8 FP9 FP10 FP11 FP12 FP13 FP14 FP15 MASK %eax +0 %.*s%.*s%.*s%.*s%.*s CX DI DS XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 XMM9 XMM10 XMM11 XMM12 XMM13 XMM14 XMM15 %ax %rax %al %ah %ebx %bx %rbx %bl %bh %ecx %cx %rcx %cl %ch %edx %dx %rdx %dl %dh %esi %si %rsi %sil %edi %di %rdi %dil %ebp %bp %rbp %bpl %rsp %sp %esp %spl %r8b %r8w %r8d %r9b %r9w %r9d %r10b %r10w %r10d %r11b %r11w %r11d %r12b %r12w %r12d %r13b %r13w %r13d %r14b %r14w %r14d %r15b %r15w %r15d /bad-path/ devices/system/cpu/smt/active == || != && %s %s %d %s%c%c \"' file:// %lu%s  ],   (target_pid: %s  (target_tid: %s  (uid: %s  (all , CPU%s: %s) , %d CPU%s) /usr/lib/debug /usr/lib/ .debug%s gz [guest.kernel.kallsyms [vdso32] [vdsox32] [vsyscall] [%.*s] dso open failed: %m
 failed to get fd limit
 dso cache fstat failed: %m
 NOT  dso: %s ( %sloaded,  /tmp/perf-%d.map Invalid ELF file Can not read build id Mismatching build id Decompression failure %.0s%s %s/.debug/%s /usr/lib/debug%s/%s [JIT] tid %d %-40s %s
 /boot/vmlinux compat_SyS %s sym:%s end:%#lx
 %s: %s %#lx-%#lx
 acpi_idle_do_entry arch_cpu_idle cpu_startup_entry idle_cpu intel_idle intel_idle_ibrs default_idle native_safe_halt enter_idle exit_idle mwait_idle mwait_idle_with_hints poll_idle ppc64_runlatch_off pseries_dedicated_idle_sleep psw_idle psw_idle_exit __entry_SYSCALL_64_trampoline [guest.kernel].%d [kernel].%d @@ [%s] _stext Using %s for kernel data
 Using %s for symbols
 /proc/kcore [kernel.kcore]  (deleted) problems parsing %s list
 Invalid file: %s
 /boot/vmlinux-%s /lib/modules/%s/build/vmlinux  %lx-%lx %c %s
 +0x%lx [%#lx] [32m never always auto dumb TopdownL No_group duration_time found event %s
 ,metric-id= /metric-id= ,-=@ }:W Parsing metric events '%s'
 Default Matched metric-id %s to %s
 metric expr %s for %s
 __threshold__ %s/level %s/coherency_line_size %s/number_of_sets %s/ways_of_associativity %s/type %s/size %s/shared_cpu_list # e_machine : %u
 #   e_flags : %u
 # schedstat version	: %u
 # Maximum sched domains	: %u
 # cpu		: %u
 # nr_domains	: %u
 # Domain		: %u
 # Domain name      : %s
 # Domain cpu map   : %s
 # Domain cpu list  : %s
 # hybrid cpu system:
 # %s cpu list : %s
 Zstd Unknown # clockid frequency: %lu MHz
 # CPU cache info:
 #   L%d %-15s %8s [%s]
 # contains stat data
 # sibling sockets : %s
 # sibling dies    : %s
 # sibling threads : %s
 , %s = %s # total memory : %llu kB
 # cpuid : %s
 # cpudesc : %s
 # nrcpus online : %u
 # nrcpus avail : %u
 # arch : %s
 # perf version : %s
 # os release : %s
 # hostname : %s
 # btf info empty # btf info of id %u
 # bpf_prog_info empty #  %3lu [%s]: %s
 unknown feature %d
 # time of first sample : %s
 # time of last sample : %s
 # group: %s{%s }
 # pmu mappings:  %s%s = %u # node%u cpu list :  # cmdline :  %s\' broken or missing trace data
 # %s pmu capabilities:  # reference time disabled
 %F %T %s.%06d # clockid: %s (%u)
 legacy perf.data format
 %s/devices/system/node/ node%u memory%u ibs_op util/header.c group desc not available
 {anon_group} invalid group desc
 # event : name = %s,  , id = { /proc/meminfo MemTotal: %*s %lu failed to write feature %s
 failed to write perf header
 /proc/cpuinfo model name PERF_CPUID Using CPUID %s
 /proc/schedstat version %d
 cpu%u %*s domain domain%u %s %s %*s domain%u %s %*s # captured on    : %s # header version : %u
 # data offset    : %lu
 # data size      : %lu
 # feat offset    : %lu
 # missing features:  magic/endian check failed
 endian/magic failed
 incompatible file format
 # %s 
... id:    %llu
 ... scale: %f
 ... unit:  %s
 ... name:  %s
 ...  failed to get cpus
 ... unknown type
 %s: reading input file HOSTNAME OSRELEASE VERSION ARCH NRCPUS CPUDESC TOTAL_MEM CMDLINE EVENT_DESC CPU_TOPOLOGY NUMA_TOPOLOGY PMU_MAPPINGS GROUP_DESC SAMPLE_TIME MEM_TOPOLOGY CLOCKID DIR_FORMAT BPF_PROG_INFO BPF_BTF CPU_PMU_CAPS CLOCK_DATA HYBRID_TOPOLOGY CPU_DOMAIN_INFO E_MACHINE flat fractal folded Chain comparison error
 defer dwarf record-mode dump-size print-type Invalid callchain mode: %s
 order caller callee Invalid callchain order: %s
 sort-key threshold print-limit none percent %s %s%s  (calltrace) %s%s:%.1f%% %s%s:%ld iter avg_cycles %s: not enough memory
 # %*s  %*s  %*s  %*s  %*s
 Count Raw   %*d  %*d  %*s  %*x  %*lu # %*s  %*s   %*d  %*d   %04x:  debug_file not set %F %H:%M:%S [%s.%06lu]  [%13lu.%06lu]      #%zd %p in %s      #%zd %p  verbose ordered-events stderr data-convert perf-event-open kmaps type-profile %s: cannot open %s dir
 build %s/proc/modules %s/proc/version Linux version  %s/lib/modules/%s Thread init failed thread %d
 [guest.kernel.kallsyms.%d] [guest.kernel.kallsyms] [guest/%d] %s/%d Can't access file %s
 swapper : id:%llu: lost:%llu
 bpf_trampoline_ bpf_dispatcher_ _edata _etext [kernel] [guest.kernel] %s/%s/proc/kallsyms Threads: %zu
 _entry_trampoline __entry_trampoline_start [kernel.vmlinux] __sched_text_start __sched_text_end __lock_text_start __lock_text_end __traceiter_contention_begin trace_contention_begin _text /data/app-lib/ /system/lib/ //anon /dev/zero /anon_hugepage [stack /SYSV [heap] APP_ABI APK_PATH %s/libs/%s/%s NDK_ROOT APP_PLATFORM bpf_prog_ %s with build id %s not found Failed to open %s , continuing without symbols
  %lx-%lx %lx %s
 Map: Map missing from maps overlapping maps:
 %s: %p not on the pstack!
 %s: top=%d, overflow!
 failed to mmap file
 
%#lx@%s [%#x]: event: %d
 -1 -1  %#lx [%#x]: PERF_RECORD_%s .... %-5s 0x%016lx
  (PERF_CONTEXT_HV)  (PERF_CONTEXT_KERNEL)  (PERF_CONTEXT_USER)  (PERF_CONTEXT_GUEST)  (PERF_CONTEXT_GUEST_KERNEL)  (PERF_CONTEXT_GUEST_USER)  (PERF_CONTEXT_USER_DEFERRED) ... LBR call chain: nr:%lu
 ..... %2d: %016lx
 ... FP chain: nr:%lu
 ..... %2d: %016lx%s
 ...... (deferred) non matching sample_type
 non matching sample_id_all
 non matching read_format
 Cannot read kernel map
 ... branch stack %s: nr:%lu
 ... branch callstack ..... %2lu: %016lx
 ... weight: %lu ,0x%hx  . data_src: 0x%lx
  .. phys_addr: 0x%lx
  .. data page size: %s
  .. code page size: %s
 ... transaction: %lx
 ... sample_read: ...... time enabled %016lx
 ...... time running %016lx
 .... group nr %lu
 ..... id %016lx, value %016lx , lost %lu : %d %d %s %llu
 ... time enabled : %llu
 ... time running : %llu
 ... id           : %llu
 ... lost         : %llu
 (IP, 0x%x): %d/%d: %#lx
 Can't parse sample, err = %d
 Processing events... failed to read event header
 bad event header size
 failed to read event data
 
Aggregated stats:%s
 Kernel and module maps:
 # ========
 # ========
#
 Too big: nr %zu max_nr %zu
 Too big2: nr %zu max_nr %zu
  nr: %zu
  ... id: %llu   idx: %llu   cpu: %lld   tid: %lld   machine_pid: %lld   vcpu: %llu
 Invalid cpu_list
 32-bit 64-bit : unhandled!
 Couldn't decompress data
 decomp (B): %zd to %zd
 event= event=%x <unknown> NNPA_ALL CRYPTO_ALL cpum_cf  L2Miss 1  L2Miss 0 uOps  OpBrnMisp 1  OpBrnMisp 0  OpBrnTaken 1  OpBrnTaken 0  OpReturn 1  OpReturn 0 CacheHitSt 1=O-State  CacheHitSt 0=M-state   L1TlbPgSz 4KB  L1TlbPgSz 1GB  L1TlbPgSz 2MB  IcMiss 0  IcMiss 1  L1TlbPgSz RESERVED  L1TlbPgSz 16KB IbsFetchLinAd:	%016llx
 IbsFetchPhysAd:	%016llx
  L3MissOnly %d  LdLatThrsh %2d LdLatEn %d IbsOpRip:	%016llx
  L2Miss %d  OpDcMissOpenMemReqs %2d  OpMemWidth %2d bytes  DcPageSize %4s  DcL2TlbHit2M %d  DcL2TlbHit1G %d IbsDCLinAd:	%016llx
 IbsDCPhysAd:	%016llx
 IbsBrTarget:	%016llx
 %u:%9s ibs_fetch zen4_ibs_extensions ldlat dtlb_pgsize %*[^,],%u,%u problem parsing cpuid
   4K   2M   1G   ??  DataSrc 1=(reserved)  DataSrc 2=Local node cache  DataSrc 3=DRAM  DataSrc 4=Remote node cache  DataSrc 5=(reserved)  DataSrc 6=(reserved)  DataSrc 7=Other  DataSrc 4=(reserved)  DataSrc 6=Long-latency DIMM  DataSrc 8=Extension Memory  DataSrc 9=(reserved)  DataSrc 10=(reserved)  DataSrc 11=(reserved) io_setup io_destroy io_submit io_cancel io_getevents lsetxattr fsetxattr lgetxattr fgetxattr llistxattr flistxattr lremovexattr fremovexattr getcwd lookup_dcookie eventfd2 epoll_create1 epoll_ctl epoll_pwait dup dup3 fcntl inotify_init1 inotify_add_watch inotify_rm_watch ioctl ioprio_set ioprio_get flock mknodat mkdirat unlinkat symlinkat umount2 pivot_root nfsservctl fstatfs ftruncate fallocate faccessat fchdir chroot fchmod fchmodat fchownat fchown openat close vhangup pipe2 quotactl getdents64 pread64 pwrite64 preadv pwritev sendfile pselect6 ppoll signalfd4 vmsplice tee readlinkat newfstatat fsync fdatasync sync_file_range timerfd_create timerfd_settime timerfd_gettime utimensat acct capget capset personality exit_group waitid set_tid_address unshare futex set_robust_list get_robust_list getitimer setitimer kexec_load delete_module timer_create timer_gettime timer_getoverrun timer_settime timer_delete clock_settime clock_gettime clock_getres clock_nanosleep syslog ptrace sched_setparam sched_setscheduler sched_getscheduler sched_getparam sched_setaffinity sched_getaffinity sched_yield sched_get_priority_max sched_get_priority_min sched_rr_get_interval restart_syscall tkill tgkill sigaltstack rt_sigsuspend rt_sigaction rt_sigprocmask rt_sigpending rt_sigtimedwait rt_sigqueueinfo rt_sigreturn setpriority getpriority reboot setregid setgid setreuid setuid setresuid getresuid setresgid getresgid setfsuid setfsgid setpgid getpgid getsid setsid getgroups setgroups sethostname setdomainname getrusage getcpu gettimeofday settimeofday adjtimex getpid getppid getuid geteuid getgid getegid gettid sysinfo mq_open mq_unlink mq_timedsend mq_timedreceive mq_notify mq_getsetattr msgget msgctl msgrcv msgsnd semget semctl semtimedop semop shmget shmctl shmat shmdt socketpair listen accept connect getsockname getpeername sendto recvfrom setsockopt getsockopt shutdown sendmsg recvmsg readahead brk munmap mremap add_key request_key keyctl clone execve fadvise64 swapon swapoff msync mlock munlock mlockall munlockall mincore remap_file_pages mbind get_mempolicy set_mempolicy migrate_pages move_pages rt_tgsigqueueinfo perf_event_open accept4 recvmmsg wait4 prlimit64 fanotify_init fanotify_mark name_to_handle_at open_by_handle_at clock_adjtime syncfs setns sendmmsg process_vm_readv process_vm_writev kcmp finit_module sched_setattr sched_getattr renameat2 seccomp getrandom memfd_create bpf execveat userfaultfd membarrier mlock2 copy_file_range preadv2 pwritev2 pkey_mprotect pkey_alloc pkey_free statx io_pgetevents rseq kexec_file_load pidfd_send_signal io_uring_setup io_uring_enter io_uring_register open_tree move_mount fsopen fsconfig fsmount fspick pidfd_open clone3 close_range openat2 pidfd_getfd faccessat2 process_madvise epoll_pwait2 mount_setattr quotactl_fd landlock_create_ruleset landlock_add_rule landlock_restrict_self process_mrelease futex_waitv set_mempolicy_home_node cachestat fchmodat2 map_shadow_stack futex_wake futex_wait futex_requeue statmount listmount lsm_get_self_attr lsm_set_self_attr lsm_list_modules mseal setxattrat getxattrat listxattrat removexattrat open_tree_attr file_getattr file_setattr listns rseq_slice_yield dup2 vfork getdents rename mkdir rmdir creat symlink readlink lchown getpgrp utime mknod uselib ustat sysfs modify_ldt _sysctl arch_prctl setrlimit iopl ioperm create_module get_kernel_syms query_module getpmsg putpmsg afs_syscall tuxcall security set_thread_area get_thread_area epoll_create epoll_ctl_old epoll_wait_old epoll_wait utimes vserver inotify_init futimesat renameat signalfd eventfd uretprobe uprobe memfd_secret waitpid break oldstat umount stime oldfstat stty gtty nice ftime prof mpx ulimit oldolduname sgetmask ssetmask oldlstat readdir profil socketcall vm86old ipc bdflush _llseek _newselect vm86 ugetrlimit ftruncate64 lstat64 fstat64 lchown32 getuid32 getgid32 geteuid32 getegid32 setreuid32 setregid32 getgroups32 setgroups32 fchown32 setresuid32 getresuid32 setresgid32 getresgid32 setuid32 setgid32 setfsuid32 setfsgid32 fcntl64 sendfile64 fstatfs64 fadvise64_64 fstatat64 clock_gettime64 clock_settime64 clock_adjtime64 clock_getres_time64 clock_nanosleep_time64 timer_gettime64 timer_settime64 timerfd_gettime64 timerfd_settime64 utimensat_time64 pselect6_time64 ppoll_time64 io_pgetevents_time64 recvmmsg_time64 mq_timedsend_time64 mq_timedreceive_time64 semtimedop_time64 rt_sigtimedwait_time64 futex_time64 sched_rr_get_interval_time64 queue_event nr_events %u
 empty queue max_timestamp
 last_flush
 out of order event
 NONE FINAL HALF  TOP   TIME  Tgid: NStgid: nsinfo refcnt unbalanced
 /proc/%d/ns/mnt /proc/%d/status /proc/self/ns/mnt util/namespaces.c /proc/self/status net uts %d/task/%d/comm Thread %d %s
 /proc/%d/exe %d thread%s:  %s/%d/comm Bad base %d number "%s" Duplicate modifier '%c' (%s) hypervisor non_idle Maximum precise value is 3 precise_max sample_read weak dont_regroup input in flex scanner failed bad buffer in yy_scan_bytes() Unrecognized input Bad event name syntax error memory exhausted uncore_ default_core kprobe *?[ %s/bus/event_source/devices/ %s/events/%s.%s %s/events/%s.unit %s/events/%s.scale long_desc topic identifier %s (%s)
 no value assigned for term Invalid sysfs entry %s=%s
 value too big for format events/%s Failed to read alias %s
 .per-pkg .snapshot Cannot open %s
 Cannot set up %s
 %s/events Kernel PMU event =? %.*s/%s/ ,%s=%s %G%s legacy-hardware-config= legacy-cache-config= Failed to parse terms Error evaluating legacy terms caps cpumask caps/max_precise alias config=0..0xffffffffffffffff config1=0..0xffffffffffffffff config2=0..0xffffffffffffffff config3=0..0xffffffffffffffff config4=0..0xffffffffffffffff legacy-hardware-config=0..9, name=string period=number freq=number branch_type=(u|k|hv|any|...) call-graph=(fp|dwarf|lbr) stack-size=number max-stack=number nr=number aux-sample-size=number cpu=number ratio-to-prev=string Unexpected event %s/%s/
 %s=0..0x%llx %s=0..%llu hwmon_ drm_ tool drm- hwmon cpu_ %.*s/ ,.../modifier fake %s/fdinfo KiB MiB Unexpected bytes unit '%s'
 KHz MHz Unexpected hz unit '%s'
 drm-driver: drm-active- drm-cycles- Busy cycles drm-engine-capacity- Engine capacity drm-engine- Utilization in ns drm-maxfreq- Maximum frequency drm-purgeable- drm-resident- drm-shared- Size of shared memory buffers drm-total-cycles- Total busy cycles drm-total- drm-client-id: drm-pdev: drm DRM event %s/config=0x%x/ unexpected drm event term 1bytes 1capacity 1cycles 1hz 1ns _alarm Not a hwmon file '%s'
 %s_%s  :,/
	 hwmon_pmu: %s has no events
 hwmon_%s Hwmon event %s in unit %s named %s. %s%d_%s%s %s%s%s=%g%s %s/config=0x%lx/ unexpected hwmon event term %s/class/hwmon/ %s/class/hwmon/%s %s%d_input CPU core reference voltage Current Cumulative energy use Fan Humidity Voltage Chassis intrusion detection Power use Temperature 0.001V 0.001A 0.001J 1rpm 0.001% 0.001W 1Hz 0.001'C accuracy auto_channels_temp average average_highest average_interval average_interval_max average_interval_min average_lowest average_max average_min beep cap cap_hyst cap_max cap_min emergency emergency_hist label lcrit lcrit_hyst max_hyst min_hyst pulses rated_max rated_min reset_history target vid curr energy fan humidity intrusion power pwm %s/firmware/acpi/tables/NFIT slots user_time system_time has_pmem num_cores num_cpus num_cpus_online num_dies num_packages smt_on system_tsc_freq core_wide target_cpu /proc/%d/stat /proc/stat common Tracepoint event tracepoint/config=0x%x/ %s/%s/format filter header_event header_page Cannot open %s for output
     ]]>
   </style>
</defs>
 <g>
 </g>
 %.1f us %.1f ms <desc>Blocked on:
%s</desc>
 blocked sample_hi sample waiting WAITING <desc>Waiting on:
%s</desc>
 CPU %i c%i %9lli  %6lli Mhz  %6.2f Ghz <desc>%s</desc>
 disk Disk Network Sync Poll Running Deeper Idle Deepest Idle process2 Sleeping Waiting for cpu Blocked on IO </svg>
 topology: no memory
 Can't read '%s' writing file size failed
 can't read directory '%s' can't write count
 Can't make temp file 0.6 can't read '%s' can't write header_page
 can't write header_event
 ftrace can't get tracing/events printk_formats saved_cmdlines Python Perl tr strt  tr end   vmentry jcc iret sysret hw int tx abrt vmexit (%s%s%s) not_taken python common_lock_depth common_flags common_preempt_count %d %16s HI_SOFTIRQ NET_TX_SOFTIRQ NET_RX_SOFTIRQ BLOCK_SOFTIRQ IRQ_POLL_SOFTIRQ TASKLET_SOFTIRQ SCHED_SOFTIRQ HRTIMER_SOFTIRQ RCU_SOFTIRQ HRTIMER_NORESTART HRTIMER_RESTART repiping input file no data repiping input file string no trace data in the file tracing trace_event__init failed did not read header page did not read header event memory allocation failure
 error reading ftrace file.
 error parsing ftrace file.
 error parsing event file.
 error reading saved cmdlines
 %7d:%-*.*s [other] %*.*d %lu/0x%lx %-*llu %-*u [%c]  %-#*llx %-5.2f [%5.1f%%] %-5s %2s %s: cache-line %d no field %s +%#x (%s) Invalid regex: %s
%s %*.*s n/a [e] %s [p] %s [.] %s %-*hd :%lx Memory allocation failed
 [%c] %-#.*llx [%c] %s+0x%llx %-#*llx %c  Finish Cyc Global Finish_cyc Dispatch Cyc Global Dispatch_cyc Local Retire Latency local_p_stage_cyc local_ins_lat Local INSTR Latency Local Pipeline Stage Cycle callchain_branch_predicted callchain_branch_abort callchain_branch_cycles unsupported field option %s
 trace_fields Cannot find event: %s
 %s is not a tracepoint event
 # %s: %s
 sym_from sym_to dso_from dso_to addr_from addr_to Invalid --sort key: `+' overhead overhead_children latency_children {},  dcacheline Invalid --sort key: `%s' Unknown --sort key: `%s' parent Invalid --fields key: `+' Invalid --fields key: `%s' Unknown --fields key: `%s' 
			  overhead_sys overhead_us overhead_guest_sys overhead_guest_us weight1 weight2 weight3 memory snoop dtlb symbol_daddr dso_daddr symbol_iaddr phys_daddr data_page_size symbol_from symbol_to mispredict in_tx srcline_from srcline_to ipc_lbr srcfile local_weight symbol_size dso_size cgroup_id ipc_null code_page_size local_retire_lat simd typeoff typecln parallelism Data Type Cacheline Data Type Offset Data Type DSO size Symbol size Transaction                 Branch in transaction Transaction abort Code Page Size Data Page Size Data Physical Address Blocked Data Cacheline Memory access TLB access Locked Data Object Code Symbol Data Symbol Local Weight Branch Mispredicted Basic Block Cycles Target Address Source Address Target Symbol Source Symbol Target Shared Object Source Shared Object Trace output Time Socket Cgroup cgroup id (dev/inode) Parallelism Parent symbol Source File Abort Predicted IPC   [IPC Coverage] To Source:Line From Source:Line Symbol Offset Simd       Tgid:Command     Pid:Command comm,dso,symbol %s stats:
 LOST_SAMPLES (BPF) call-graph=no , UID: %s , Thread: %s(%d) , Thread: %s , DSO: %s , Processor Socket: %d  %d Hz, relative absolute Invalid percentage: %s
 hist.percentage stat failed: %s
 kcore_dir__[1-9]* kernel/perf_event_max_stack kernel/nmi_watchdog %.*s%s%.*s
 data.* kernel/perf_event_paranoid tips.txt Tip: %s /proc/self/exe DEBUGINFOD_URLS system DEBUGINFOD_URLS=%s
 /proc/%d/root %s/devices/system/cpu/present Invalid cpumap entry %u
 Invalid cpumap entry %d
 physical_package_id die_id cluster_id core_id cpu_map not initialized
 %s: calloc failed
 %s/devices/system/node cpu%u %s%d-%d cpumask list: %s
 failed to get system cpumap
 Error creating CPU topology %s/devices/system/node/online %*s %*d %31s %lu MemFree: perf_event no access to cgroup %s
 memory allocation failed
 {}[]()|*+?^$ no cgroup matched: %s
 PID/TID switch overriding CPU BPF switch overriding CPU BPF switch overriding PID/TID BPF switch overriding THREAD /proc/self/maps cannot open maps
 %p-%p r-xp %*x %*x:%*x %*u %n perf-read-vdso32 perf-read-vdsox32 %s: %lu %lu %lu
 Invalid CPU %d for event %s.
 INTERVAL 
... time %llu, type %s
 ... aggr_mode %d
 ... scale     %d
 ... interval  %u
 %s (%s) %s  %s_%d %s  %s %8.1f %8.2f nearly bad less good %s"metric-threshold" : "%s" %s"%s" : "%s" time%s %s"core" : "S%d-D%d-C%d" %s"cpu" : "%d" %s"thread" : "%s-%d" S%d-D%d-C%d%s%d%s S%d-D%d-L%d-ID%d%s%d%s S%d-D%d-CLS%d%s%d%s S%d-D%d%s%d%s N%d%s%d%s S%d-D%d-C%d%s CPU%d%s %s-%d%s S%d-D%d-C%d S%d-D%d-L%d-ID%d S%d-D%d-CLS%d S%d-D%d N%d S%d-D%d-C%d  CPU%-*d  %*s-%-*d  %-*s %*d  
{ %s%lu%s%.2f   (%.2f%%) %s"cgroup" : "%s" %s"metricgroup" : "%s"} <not counted> <not supported> %.2f%s %.0f%s %'*.2f  %'*.0f  %*.0f  %s"counter-value" : "%f" %s"counter-value" : "%s" %s"unit" : "%s" %s"event" : "%s" %s"variance" : %.2f %s%.2f%%   ( +-%6.2f%% ) [33m  #  "interval" : %lu.%09lu %lu.%09lu%s %6lu.%09lu  [H[2J #%*s %-*s ctrs #%*s %-*s #%*s %*s-%-*s #%*s counts  %*s %*s events
 'BPF program(s) %s 'system wide 'CPU(s) %s process id '%s thread id '%s  (%d runs) :

 "metric-value" : "none"  %17.9f seconds time elapsed  %17.9f seconds user
  %17.9f seconds sys
  %17.9f 
%*s# Final result:
  %17.9f (%+.9f)  die cluster comm-pid cpu, socket,ctrs, die,ctrs, cluster,ctrs, cache,ctrs, core,ctrs, comm-pid, node, software/cpu-clock/u %s/%s/u %s:%u addr2line.style libdw libbfd Unknown addr2line style: %s
 %s[%lx] cannot open source file %s
 cannot mmap source file %s
 /proc/%u/ns/%s /proc/%d/task/%d/status couldn't open %s
 Name: PPid: VmPeak: Threads: process synth event failed
 failed to open directory: %s
 %s/proc/%d/task/%d/maps %s/proc/%d/task %s/proc Synthesizing id index
 Bad id sample size %d
 Couldn't synthesize attrs.
 Couldn't synthesize config.
 Error writing feature
 %s/schedstat version 15
 version 16
 version 17
 Unsupported %s version: %s %s.old failed to open %s: %m perf.data   (try 'perf record' first) failed to open %s : %m
 util/data.c %s/data.%d data. %s/data Failed to rename %s to %s
 Failed to lseek to %zu: %m
 %s/kcore_dir %s/kcore_dir/kallsyms %s/kcore_dir__%d/kallsyms 
... Time Shift      %llu
 ... Time Multiplier %llu
 ... Time Zero       %llu
 ... Time Cycles     %llu
 ... Time Mask       %#llx
 ... Cap Time Zero   %d
 ... Cap Time Short  %d
 Error flushing thread stack!
 __x86_indirect_thunk_ ▁ ▂ ▃ ▄ ▅ ▆ ▇ █ 
hot chain %d:
 cycles: %ld, hits: %.2f%% %35s	%35s
 %35s	%35s 
hot chain pair %d:
 --------------------------- [ Matched hot streams ] Unsupported kvm-stat host %d
 vcpu_id scause icptcode exit_reason kvm:kvm_entry kvm:kvm_enter kvm_hv:kvm_guest_enter kvm:kvm_s390_sie_enter kvm:kvm_exit kvm_hv:kvm_guest_exit kvm:kvm_s390_sie_exit esr_ec VM-EXIT WFx CP15_32 CP15_64 CP14_MR CP14_LS FP_ASIMD CP10_ID PAC CP14_64 SVC64 HVC64 SMC64 SYS64 IMP_DEF IABT_LOW IABT_CUR PC_ALIGN DABT_LOW DABT_CUR SP_ALIGN FP_EXC32 FP_EXC64 SERROR BREAKPT_LOW BREAKPT_CUR SOFTSTP_LOW SOFTSTP_CUR WATCHPT_LOW WATCHPT_CUR BKPT32 VECTOR32 BRK64 TRAP HYP_GONE inst_word kvm:kvm_reenter loongarch64 kvm:kvm_exit_gspr Interrupt Mem Read Mem Store Inst Fetch Mem Modify FPU LSX LASX Privilege Error Hypercall CPUCFG IOCSR Others Unknown hcall code: %lld
 trace_cycles trace_imc trace_imc/trace_cycles/ hcall HCALL-EVENT kvm_hv:kvm_hcall_enter kvm_hv:kvm_hcall_exit H_REMOVE H_ENTER H_READ H_CLEAR_MOD H_CLEAR_REF H_PROTECT H_GET_TCE H_PUT_TCE H_SET_SPRG0 H_SET_DABR H_PAGE_INIT H_SET_ASR H_ASR_ON H_ASR_OFF H_LOGICAL_CI_LOAD H_LOGICAL_CI_STORE H_LOGICAL_CACHE_LOAD H_LOGICAL_CACHE_STORE H_LOGICAL_ICBI H_LOGICAL_DCBF H_GET_TERM_CHAR H_PUT_TERM_CHAR H_REAL_TO_LOGICAL H_HYPERVISOR_DATA H_EOI H_CPPR H_IPI H_IPOLL H_XIRR H_MIGRATE_DMA H_PERFMON H_REGISTER_VPA H_CEDE H_CONFER H_PROD H_GET_PPP H_SET_PPP H_PURR H_PIC H_REG_CRQ H_FREE_CRQ H_VIO_SIGNAL H_SEND_CRQ H_COPY_RDMA H_REGISTER_LOGICAL_LAN H_FREE_LOGICAL_LAN H_ADD_LOGICAL_LAN_BUFFER H_SEND_LOGICAL_LAN H_BULK_REMOVE H_MULTICAST_CTRL H_SET_XDABR H_STUFF_TCE H_PUT_TCE_INDIRECT H_CHANGE_LOGICAL_LAN_MAC H_VTERM_PARTNER_INFO H_REGISTER_VTERM H_FREE_VTERM H_RESET_EVENTS H_ALLOC_RESOURCE H_FREE_RESOURCE H_MODIFY_QP H_QUERY_QP H_REREGISTER_PMR H_REGISTER_SMR H_QUERY_MR H_QUERY_MW H_QUERY_HCA H_QUERY_PORT H_MODIFY_PORT H_DEFINE_AQP1 H_GET_TRACE_BUFFER H_DEFINE_AQP0 H_RESIZE_MR H_ATTACH_MCQP H_DETACH_MCQP H_CREATE_RPT H_REMOVE_RPT H_REGISTER_RPAGES H_DISABLE_AND_GET H_ERROR_DATA H_GET_HCA_INFO H_GET_PERF_COUNT H_MANAGE_TRACE H_FREE_LOGICAL_LAN_BUFFER H_POLL_PENDING H_QUERY_INT_STATE H_ILLAN_ATTRIBUTES H_MODIFY_HEA_QP H_QUERY_HEA_QP H_QUERY_HEA H_QUERY_HEA_PORT H_MODIFY_HEA_PORT H_REG_BCMC H_DEREG_BCMC H_REGISTER_HEA_RPAGES H_DISABLE_AND_GET_HEA H_GET_HEA_INFO H_ALLOC_HEA_RESOURCE H_ADD_CONN H_DEL_CONN H_JOIN H_VASI_STATE H_ENABLE_CRQ H_GET_EM_PARMS H_SET_MPP H_GET_MPP H_HOME_NODE_ASSOCIATIVITY H_BEST_ENERGY H_XIRR_X H_RANDOM H_COP H_GET_MPP_X H_SET_MODE H_RTAS RETURN_TO_HOST SYSTEM_RESET MACHINE_CHECK DATA_SEGMENT INST_SEGMENT EXTERNAL EXTERNAL_HV PROGRAM FP_UNAVAIL HV_DECREMENTER H_DATA_STORAGE H_INST_STORAGE H_EMUL_ASSIST ALTIVEC VSX IRQ_S_SOFT IRQ_VS_SOFT IRQ_M_SOFT IRQ_S_TIMER IRQ_VS_TIMER IRQ_M_TIMER IRQ_S_EXT IRQ_VS_EXT IRQ_M_EXT IRQ_S_GEXT IRQ_PMU_OVF EXC_INST_MISALIGNED EXC_INST_ACCESS EXC_INST_ILLEGAL EXC_BREAKPOINT EXC_LOAD_MISALIGNED EXC_LOAD_ACCESS EXC_STORE_MISALIGNED EXC_STORE_ACCESS EXC_SYSCALL EXC_HYPERVISOR_SYSCALL EXC_SUPERVISOR_SYSCALL EXC_INST_PAGE_FAULT EXC_LOAD_PAGE_FAULT EXC_STORE_PAGE_FAULT EXC_INST_GUEST_PAGE_FAULT EXC_LOAD_GUEST_PAGE_FAULT EXC_VIRTUAL_INST_FAULT EXC_STORE_GUEST_PAGE_FAULT order_code IBM Wait state kvm:kvm_s390_handle_sigp kvm:kvm_s390_handle_diag kvm:kvm_s390_intercept_prog Prog Operation Prog Privileged Operation Prog Execute Prog Protection Prog Addressing Prog Specification Prog Data Prog Fixedpoint overflow Prog Fixedpoint divide Prog Decimal overflow Prog Decimal divide Prog HFP exponent overflow Prog HFP exponent underflow Prog HFP significance Prog HFP divide Prog Segment translation Prog Page translation Prog Special operation Prog Operand Prog Trace table Prog Spaceswitch event Prog HFP square root Prog AFX translation Prog ASX translation Prog LX translation Prog EX translation Prog Primary authority Prog Secondary authority Prog LFXtranslation exception Prog LSXtranslation exception Prog ALET specification Prog ALEN translation Prog ALE sequence Prog ASTE validity Prog ASTE sequence Prog Extended authority Prog LSTE sequence Prog ASTE instance Prog Stack full Prog Stack empty Prog Stack specification Prog Stack type Prog Stack operation Prog Region first translation Prog Region third translation Prog Monitor event Prog PER event Prog Crypto operation DIAG (0x10) release pages DIAG (0x44) time slice end DIAG (0x308) ipl functions DIAG (0x501) KVM breakpoint SIGP sense SIGP external call SIGP emergency signal SIGP start SIGP stop SIGP restart SIGP stop and store status SIGP initial cpu reset SIGP cpu reset SIGP set prefix SIGP store status at address SIGP set architecture SIGP sense running SIGP set multithreading 0x01 PR 0x01 PTFF 0x01 SCKPF 0xAA RINEXT 0xAA RION 0xAA TRIC 0xAA RIOFF 0xAA RIEMIT 0xB2 STIDP 0xB2 SCK 0xB2 STCK 0xB2 SCKC 0xB2 STCKC 0xB2 SPT 0xB2 STPT 0xB2 PTLB 0xB2 SPX 0xB2 STPX 0xB2 STAP 0xB2 SIE 0xB2 SETR 0xB2 STETR 0xB2 PC 0xB2 SERVC 0xB2 IPTE 0xB2 PT 0xB2 ISKE 0xB2 RRBE 0xB2 SSKE 0xB2 TB 0xB2 PGIN 0xB2 PGOUT 0xB2 CSCH 0xB2 HSCH 0xB2 MSCH 0xB2 SSCH 0xB2 STSCH 0xB2 TSCH 0xB2 TPI 0xB2 SAL 0xB2 RSCH 0xB2 STCRW 0xB2 STCPS 0xB2 RCHP 0xB2 SCHM 0xB2 BAKR 0xB2 PALB 0xB2 TAR 0xB2 CSP 0xB2 MVPG 0xB2 STHYI 0xB2 BSG 0xB2 BSA 0xB2 CHSC 0xB2 SIGA 0xB2 XSCH 0xB2 STCKE 0xB2 STCKF 0xB2 STSI 0xB2 STFLE 0xB2 STFL 0xB2 LPSWE 0xB2 TEND 0xB2 TABORT 0xB9 KMAC 0xB9 PCKMO 0xB9 KMF 0xB9 KMO 0xB9 KMCTR 0xB9 KM 0xB9 KMC 0xB9 KIMD 0xB9 KLMD 0xB9 CSPG 0xB9 EPSW 0xB9 IDTE 0xB9 CRDTE 0xB9 EQBS 0xB9 PTF 0xB9 ESSA 0xB9 RRBM 0xB9 PFMF 0xE3 LRAG 0xE3 LRAY 0xE3 NTSTG 0xE5 LASP 0xE5 TPROT 0xE5 TBEGIN 0xE5 TBEGINC 0xEB STCTG 0xEB LCTLG 0xEB LRIC 0xEB STRIC 0xEB MRIC 0xEB SQBS 0xC8 ECTG SVC SSM LPSW DIAG SIGP STNSM STOSM LRA STCTL LCTL PLO Host interruption Instruction Program interruption External request External interruption I/O request Validity Stop request Operation exception Partial-execution I/O interruption I/O instruction Timing subset %#llx:%s POUT PIN %#lx:%s kvm:kvm_msr kvm:kvm_pio rw kvm:kvm_mmio gpa VMX Hygon SVM pfm-events ioport MSR Access IO Port Access MMIO Access read_cr0 read_cr2 read_cr3 read_cr4 read_cr8 write_cr0 write_cr2 write_cr3 write_cr4 write_cr8 read_dr0 read_dr1 read_dr2 read_dr3 read_dr4 read_dr5 read_dr6 read_dr7 write_dr0 write_dr1 write_dr2 write_dr3 write_dr4 write_dr5 write_dr6 write_dr7 DE excp DB excp BP excp OF excp BR excp UD excp NM excp DF excp TS excp NP excp SS excp GP excp PF excp MF excp AC excp MC excp XF excp nmi smi vintr cr0_sel_write read_idtr read_gdtr read_ldtr read_rt write_idtr write_gdtr write_ldtr write_rt rdtsc rdpmc pushf popf cpuid rsm swint hlt invlpg invlpga task_switch ferr_freeze vmrun hypercall vmload vmsave stgi clgi skinit rdtscp icebp wbinvd monitor mwait xsetbv write_efer_trap write_cr0_trap write_cr4_trap write_cr8_trap invpcid buslock idle-halt npf avic_incomplete_ipi avic_unaccelerated_access vmgexit vmgexit_mmio_read vmgexit_mmio_write vmgexit_nmi_complete vmgexit_ap_hlt_loop vmgexit_ap_jump_table vmgexit_page_state_change vmgexit_guest_request vmgexit_ext_guest_request vmgexit_ap_creation vmgexit_hypervisor_feature invalid_guest_state EXCEPTION_NMI EXTERNAL_INTERRUPT TRIPLE_FAULT INIT_SIGNAL SIPI_SIGNAL INTERRUPT_WINDOW NMI_WINDOW TASK_SWITCH INVLPG RDPMC RDTSC VMCALL VMCLEAR VMLAUNCH VMPTRLD VMPTRST VMREAD VMRESUME VMWRITE VMOFF VMON CR_ACCESS DR_ACCESS IO_INSTRUCTION MSR_READ MSR_WRITE INVALID_STATE MSR_LOAD_FAIL MWAIT_INSTRUCTION MONITOR_TRAP_FLAG MONITOR_INSTRUCTION PAUSE_INSTRUCTION MCE_DURING_VMENTRY TPR_BELOW_THRESHOLD APIC_ACCESS EOI_INDUCED GDTR_IDTR LDTR_TR EPT_VIOLATION EPT_MISCONFIG INVEPT RDTSCP PREEMPTION_TIMER INVVPID WBINVD XSETBV APIC_WRITE RDRAND INVPCID VMFUNC ENCLS RDSEED PML_FULL XSAVES XRSTORS UMWAIT TPAUSE BUS_LOCK NOTIFY TDCALL MSR_READ_IMM MSR_WRITE_IMM Memory allocation failure
 %s 0x%lx/0x%lx%s%s %s 0x%lx%s%s #%d	0x%lx	%c	%s
 		which is near		%s
 Symbol '%s' not found.
 Kernel symbol lookup:  Uninitialized auxtrace_mmap
 failed to mmap AUX area
 AUX area mmap length %zu
 No AUX area event to sample
 Bad aux-action '%s'
 itrace.debug-log-buffer-size unknown AUX  %s error type %u  time %lu.%09llu  time 0  machine_pid %d vcpu %d %u %s errors
 instruction trace tracestop  , Address filter: %s
  type: %u
 start-paused %s no ip %s 0x%llx %s CTC 0x%x FC 0x%x %s IF:%d %lld %s TXAbort:%u InTX:%u %s 0x%llx (NR=%d) %s 0x%llx IP:0 %s 0x%llx IP:1 %s IP:0 %s IP:1 %s SZ %s-byte Type 0x%llx %s ID 0x%02x Value 0x%llx %s Type 0x%02x Payload 0x%llx %s 0x%llx (%d) Bad Packet! PAD TNT TIP.PGD MODE.Exec MODE.TSX MTC TIP CYC PSB CBR TraceSTOP PIP PTWRITE EXSTOP PWRE PWRX BBP BIP EVD <bad> %02x  %s %s%d Call Jcc Jmp Loop IRet Int Syscall Sysret VMentry Erets Eretu .log Dumping debug log buffer
 End of debug log buffer dump
   %08lx:  Bad instruction!
 Getting more data
 No more data
 Reference timestamp 0x%lx
 ERROR: Bad packet
 Scanning for PSB
  Setting timestamp %s to 0x%lx
 %s at 0x%lx
 ERROR: Never-ending loop ERROR: Internal error
 Wraparound timestamp Suppressing bad timestamp Timestamp out of range ERROR: Unexpected packet
 ERROR: Buffer overflow
 ERROR: Missing TIP after FUP
 Omitting PGE ip 0x%lx
 Setting IP Emulated ptwrite detected
 Skipping zero TIP.PGE Skipping zero FUP ERROR: Missing FUP after BEP ERROR: Missing FUP after CFE ERROR: Too many EVD packets timestamp: mtc_shift %u
 timestamp: tsc_ctc_mult %u
 timestamp: tsc_slip %#x
 Unknown error! Scanning for full IP
 ERROR: PSB without PSBEND Surprising PGE change in OVF! ERROR: TSC without TMA %s: last_mtc_ctc %#lx
 %s: last_ctc %#x
 %s: ctc_delta %#lx
 %s: delta %#lx
 %s: ctc %#x
 %s: new_ctc_delta %#lx
 %s: last_ctc_timestamp %#lx
 %s: fc %#x
 %s: expected_tsc %#lx
 ERROR: Missing VMCS VMCS: %#lx  TSC Offset %#lx ERROR: Unknown VMCS Memory allocation failed Internal error Bad packet No more data Failed to get instruction Overflow packet Lost trace data Broken emulated ptwrite GenuineIntel,6,92, intel-pt.mispred-all intel-pt.max-loops intel-pt.cache-divisor   %08zx:   Bad packet!
 ERROR: no guest machine
 ERROR: no guest thread
 ERROR: no thread
 perf,ptwrite   switch: cpu %d tid %d
 perf_trace_sched_switch __perf_event_task_sched_out __switch_to switch_ip: %lx ptss_ip: %lx
 TSC %lx est. TSC %lx
 queue %u getting timestamp
 queue %u has no timestamp
 queue %u timestamp 0x%lx
 next_pid Bad AUX output hardware ID
 GenuineIntel,6,175, GenuineIntel,6,182, GenuineIntel,6,190, intel_pt   Max non-turbo ratio %lu
   Filter string len.  %lu
 %s: bad filter string length
 Filter string   %-20s%s
   Cap Event Trace     %d
 sched:sched_switch TSC frequency %lu
 Maximum non-turbo ratio %u
 %s: %u range(s)
 transactions cbr psb pwre exstop pwrx evt iflag   PMU Type            %ld
   Time Shift          %lu
   Time Multiplier     %lu
   Time Zero           %lu
   Cap Time Zero       %ld
   TSC bit             %#lx
   NoRETComp bit       %#lx
   Have sched_switch   %ld
   Snapshot mode       %ld
   Per-cpu maps        %ld
   MTC bit             %#lx
   MTC freq bits       %#lx
   TSC:CTC numerator   %lu
   TSC:CTC denominator %lu
   CYC bit             %#lx
  %lx -> %lx %s
  Bad record!
   PMU Type           %ld
   Time Shift         %lu
   Time Multiplier    %lu
   Time Zero          %lu
   Cap Time Zero      %ld
   Snapshot mode      %ld
 l1d-miss l1d-access llc-miss llc-access tlb-miss tlb-access remote-access     Magic            :0x%lx
     CPU #            :%ld
     Num of params    :%ld
     MIDR             :0x%lx
     PMU Type         :%ld
     Min Interval     :%ld
     Event Filter     :0x%lx
   Header version     :%ld
   Header size        :%ld
   PMU type v2        :%ld
   CPU number         :%ld
   PMU Type           :%ld
   Per CPU mmaps      :%ld
 COND-SELECT INSN-OTHER  EXCEPTION-GEN  RETIRED  L1D-ACCESS  L1D-REFILL  TLB-ACCESS  TLB-REFILL  NOT-TAKEN  MISPRED  LLC-ACCESS  LLC-REFILL  REMOTE-ACCESS  ALIGNMENT  TXN  SVE-PARTIAL-PRED  SVE-EMPTY-PRED  L2D-ACCESS  L2D-MISS  HITM  LFB  SNOOPED  STREAMING-SVE  SMCU SVE-OTHER  EVLEN %d  FP  PRED SME-OTHER  ETS %d  ASE  AT  EXCL  AR  SIMD-FP  GP-REG  UNSPEC-REG  NV-SYSREG  MTE-TAG  MEMCPY  MEMSET  SVE-SME-REG  SG  GCS  COMM  COND  IND  CR-BL  CR-RET  CR-NON-BL-RET %s %lld %s 0x%llx el%d ns=%d VA 0x%llx PA 0x%llx ns=%d ch=%d pat=%x %s 0x%lx el%d %s %d  TOT ISSUE XLAT TGT VA PBT CONTEXT OP-TYPE DATA-SOURCE Get packet error!
   %08x:  Prefix Header DW0 Header DW1 Header DW2 Header DW3 Format Length SO T8 T9 auxtrace.dumpdir %s/aux.ctr.%02x %s/aux.smp.%02x %*[^,],%u boot_tb: %lu, tb_freq: %lu
 VPA requires ordered events
 vpa_dtl vpa-dtl unused firmware_internal_event time_slice virtual_memory_page_fault H_CONFER_ADJUNCT hcall_adjunct HDEC_adjunct external_interrupt decrementer_interrupt system_reset conferred_cycles expropriated_adjunct priv_doorbell , version supported <= %x
 	Magic number		       %llx
 	CPU			       %lld
 	NR_TRC_PARAMS		       %llx
 	TRCCONFIGR		       %llx
 	TRCTRACEIDR		       %llx
 	TRCIDR0			       %llx
 	TRCIDR1			       %llx
 	TRCIDR2			       %llx
 	TRCIDR8			       %llx
 	TRCAUTHSTATUS		       %llx
 	TS_SOURCE		       %lld
 	ETMCR			       %llx
 	ETMTRACEIDR		       %llx
 	ETMCCER			       %llx
 	ETMIDR			       %llx
 	Header version		       %llx
 	Snapshot		       %llx
 any any_call any_ret ind_call abort_tx no_tx cond ind_jmp no_flags no_cycles save_type hw_index priv counter -I --user-regs= available registers:  Unknown option name '%s'
 help.autocorrect one of these 
Did you mean %s?
 this ./%s %s/dlfilters/%s :-1 dlopen failed for: '%s'
 filter_event filter_event_early perf_dlfilter_fns filter_description   %-36s %s
 %39s%s
 List of available dlfilters: %s/dlfilters : available
 %-*s%-*s%s  hit  miss Unknown level %d Fwd Peer Yes  N/A  Addr |OP  PFETCH |LVL  |SNP  |TLB  |LCK  |BLK  Load Ld+St Pfetch L1 L3 L4 L1-buf L2-buf MSC Uncach CXL PMEM L?-Hit HitM Miss L2-Hit L1-Hit None core, same node node, same socket socket, same board L2 MHB Memory-side Cache Uncached I/O Any cache LFB/MAB HIT Local RAM Remote RAM (1 hop) Remote RAM (2 hops) Remote Cache (1 hop) Remote Cache (2 hops) Walker Fault ldlat-loads %s/mem-loads,ldlat=%u/P mem-loads ldlat-stores %s/mem-stores/P mem-stores %lu%c start time %lu,  end time %lu
 start time %d: %lu,  end time %d: %lu
 Invalid time string
 %lu.%06lu %Y%m%d%H%M%S %s%02u Error creating IDs for '%s' division by zero
 adding ref metric %s: %s
 parsing metric: %s
 %s not found
 lookup(%s): val %f
 processing metric: %s ENTRY
 %s failed to count
 Failure to read '%s' Unrecognized literal '%s' literal: %s = %f
 FAULT_ALGN FAULT_DATA FAULT_INST ARCH_1 ARCH_2 ARCH_3 ARCH_4 ARCH_5 UNCOND SYSRET COND_CALL COND_RET ERET 
# 
# Branch Statistics: COND_FWD 
%8s: %5.1f%% COND_BWD CROSS_4K CROSS_2M SPEC_WRONG_PATH NON_SPEC_CORRECT_PATH monotonic CLOCK_ (not found) monotonic_raw realtime boottime tai mono real %s error: '%s'
 %s/%d/status tpebs_event_ %s/name=tpebs_event_%p/%s -o -W --synth=no --control=fd:%d,%d -C [%d] = %d,
 [%d] = ERROR,
 .text %s: cannot get elf header.
 .note.gnu.build-id .notes .note .plt.got .rela.dyn %s@plt offset_%#lx@plt .plt.sec .rela.plt .rel.plt  %s: cannot read %s ELF file.
 .gnu_debuglink .gnu_debugdata %s: fmemopen: %m
 %s: mkstemp: %m
 .symtab .dynsym .opd .init .exit adtx %s/kcore %s/modules .note.stapsdt gelf_xlatetom : %s
 %s : cannot get elf header.
 .stapsdt.base .probes Failed to get cache from %s
 %s/probes Failed to open cache(%d): %s
 Opening %s write=%d
 README kprobe_events CONFIG_KPROBE_EVENTS=y uprobe_events CONFIG_UPROBE_EVENTS=y {k,u}probe_events strlist__add failed (%d)
 Writing event: %s
 Failed to write event: %s
 -:%s Failed to delete event: %s
 Cache open error: %d
 Cache read error: %d
 Failed to add probe caches
 Added probe cache: %d
 Failed to get sdt note: %d
 sdt_%s %s:%s=%s p:%s/%s %s:0x%llx (0x%llx) [sp, Allocation error
  arg%d=%s%s Cache committed: %d
 Writing cache: %s%s
 Removed cached event: %s
 list cache with filter: %s
 %s (%s):
 *type: * x8/16/32/64,* *place (kretprobe): * *ref_ctr_offset* *u]<offset>* *Create/append/* *\imm-value,* :s64 :s32 :s16 :s8 :u8 :u16 :u32 :u64 %return .gnu.linkonce.this_module Failed to find module %s.
 .ko Rebuild with -g,  %s is out of .text, skip it.
 %7d   File read error: %s
 +u %s%ld( %+ld(  %s= %s%+ld __return .@ %s/kprobes/blacklist 0x%lx-0x%lx Blacklist: 0x%lx-0x%lx, %s
 Failed to init symbol map.
 Use vmlinux: %s
 machine__new_host() failed.
 Failed to init vmlinux path.
 file: %s, line: %d function: %s, line:%d Debuginfo analysis failed.
 <%s@%s:%d>
 <%s:%d>
 Failed to open %s: %s
 Searching variables at %s
 Available variables at %s
 	@<%s+%lu>
 		(No matched variables)
 start line end line Line range is %d to %d
 /. Failed to split arguments.
 sdt_ ;=@+% %%%s ;: ;:+@% util/probe-event.c %s_L%d parsing arg: %s into  name:%s  user_access  type:%s  -.[ %s(%d),  %s(%d)
 $params $vars Parsing probe_events: %s
 Group:%s Event:%s probe:%c
 (null) %s:%s= %c:%s/%s  0x0 %s:0x%lx (0x%lx) %s%s0x%lx %s%s%s+%lu   %-20s (on   in %s  with [$+-]* Failed to get a map for %s
 Failed to load symbols in %s
 Failed to make a group name.
 abs_%lx Found %d probe_trace_events.
 Probe point '%s' not found.
 Trying to use symbols.
 \%ld DW_OP %x is not supported.
 converting %s in %s
 Var real type: %s (%x)
 Array real type: %s (%x)
 Probe point found: %s+%lu
 Expanding %s into: ustring b%d@%d/%d %s type is %s.
 Out of memory error
 unsigned char %c%d Ignoring tail call from %s
 fname: %s, lineno:%d
 New line range: %d to %d
 [INV]	 [VAL]	 [EXT]	 Add new var: %s
 Error in strbuf
 Reversed line: %s:%d
 path: %s
 Matched function: %s [%lx]
 %s has no entry PC. Skipped
 .eh_frame \%lx found inline addr: 0x%jx
 Get %zd lines from this CU
 union  struct  enum  [] (function_type) void* (unknown_type) @<%s+[%lu-%lu ,%lu-%lu ]> %r0 $0 $26 $27 %29 $hi $lo %g0 %g1 %g2 %g3 %g4 %g5 %g6 %g7 %o0 %o1 %o2 %o3 %o4 %o5 %o7 %l0 %l1 %l2 %l3 %l4 %l5 %l6 %l7 %i0 %i1 %i2 %i3 %i4 %i5 %fp %i7 %f0 %f1 %f2 %f3 %f4 %f5 %f6 %f7 %f8 %f9 %f10 %f11 %f12 %f13 %f14 %f15 %f16 %f17 %f18 %f19 %f20 %f21 %f22 %f23 %f24 %f25 %f26 %f27 %f28 %f29 %f30 %f31 %f32 %f33 %f34 %f35 %f36 %f37 %f38 %f39 %f40 %f41 %f42 %f43 %f44 %f45 %f46 %f47 %f48 %f49 %f50 %f51 %f52 %f53 %f54 %f55 %f56 %f57 %f58 %f59 %f60 %f61 %f62 %f63 %c0 %c1 %c2 %c3 %c4 %c5 %c6 %c7 %c8 %c9 %c10 %c11 %c12 %c13 %c14 %c15 %a0 %a1 %a2 %a3 %a4 %a5 %a6 %a7 %a8 %a9 %a10 %a11 %a12 %a13 %a14 %a15 %pswm %pswa %"%zero" %"%ra" %"%sp" %"%gp" %"%tp" %"%t0" %"%t1" %"%t2" %"%s0" %"%s1" %"%a0" %"%a1" %"%a2" %"%a3" %"%a4" %"%a5" %"%a6" %"%a7" %"%s2" %"%s3" %"%s4" %"%s5" %"%s6" %"%s7" %"%s8" %"%s9" %"%s10" %"%s11" %"%t3" %"%t4" %"%t5" %"%t6" %gpr0 %gpr1 %gpr2 %gpr3 %gpr4 %gpr5 %gpr6 %gpr7 %gpr8 %gpr9 %gpr10 %gpr11 %gpr12 %gpr13 %gpr14 %gpr15 %gpr16 %gpr17 %gpr18 %gpr19 %gpr20 %gpr21 %gpr22 %gpr23 %gpr24 %gpr25 %gpr26 %gpr27 %gpr28 %gpr29 %gpr30 %gpr31 %msr %xer %link %ctr %dsisr %dar %x0 %x1 %x2 %x3 %x4 %x5 %x6 %x7 %x8 %x9 %x10 %x11 %x12 %x13 %x14 %x15 %x16 %x17 %x18 %x19 %x20 %x21 %x22 %x23 %x24 %x25 %x26 %x27 %x28 %x29 %lr %ip %pc $stack %regs9 %regs0 %regs1 %regs2 %regs3 %regs4 %regs5 %regs6 %regs7 %regs8 %epc %exregs0 %exregs1 %exregs2 %exregs3 %exregs4 %exregs5 %exregs6 %exregs7 %exregs8 %exregs9 %exregs10 %exregs11 %exregs12 %exregs13 %exregs14 %tls %hi %lo xmm0 xmm1 xmm2 xmm3 xmm4 xmm5 xmm6 xmm7 xmm8 xmm9 xmm10 xmm11 xmm12 xmm13 xmm14 xmm15 st0 st1 st2 st3 st4 st5 st6 st7 rflags eflags fs.base gs.base mxcsr fcw fsw rip eip Open Debuginfo file: %s
 Got a source %s
  %7d  %#10x %#10x  %*s%s	%s %*s}  percpu base
  constant
  percpu pointer  stack canary
 no/void pointer no type information offset bigger than size type size is unknown fbreg Good! invalid state reg%d, reg%d CU for %s (die:%#lx)
 frame base: cfa=%d fbreg=%d
  variable location:  base=reg%d, offset=%#lx
 address=%#lx
 use frame base, offset=%#lx
 base=reg%ld, offset=%#lx
 reg%ld
 addr=%#lx type_offset=%#x
 scope: [%d/%d]  (die:%lx)  [function] %s
 [inlined] %s
 [block]
 [unknown] tag=%x
 bb: [%lx - %lx]
 var [%lx] %#x(reg%d) var [%lx] -%#x(stack) var [%lx] reg%d offset %x var [%lx] copyback reg%d (ptr->%s) percpu ptr stack canary percpu var  : retry
 cfa this-cpu var global var final result:  no variable found
 (unknown type)  event[%d] = %s
 %*s %10s %10s  %s
 /tmp/jitted- unwind: no map for %lx
 '' unwind: failed with '%s'
 \" \\ \b \f \r \t \u%04x %li "0x%lx" Sample resolution failed!
 Error opening output file!
 Error creating perf session!
 Symbol init error!
 "linux-perf-json-version": 1 "headers": { header-version %FT%TZ captured-on data-offset data-size feat-offset os-release cpu-desc nrcpus-online nrcpus-avail clock-time real-time perf-version "samples": [ %s.py import os
 import sys

 from Core import *


 def trace_begin():
 	print("in trace_begin")

 def trace_end():
 	print("in trace_end")

 def %s__%s( event_name,  context,  common_cpu,
 	common_secs,  common_nsecs,  common_pid,  common_comm,
	 common_callchain,  
		 perf_sample_dict 		print(" " \
		" %%d %%u " %% \
		( flag_str(" %s__%s",  "%s", %s) symbol_str(" ))

 
			if 'sym' in node: 
			else: 		print()

 generated Python script: %s
 couldn't create Python tuple %5s:0x%lx  stat__%s can't find python handler %s
 error resizing Python tuple couldn't create Python list %s+0x%x trace_end unthrottle define_symbolic_field define_flag_field define_flag_value define_symbolic_value auxtrace_error binding sym_off sym_srcline perf_trace_context Can't open python script "%s" __main__ perf_script_context trace_begin failed to initialize export perf_db_export_mode perf_db_export_calls perf_db_export_callchains evsel_table machine_table comm_table comm_thread_table dso_table symbol_table branch_type_table sample_table call_path_table call_return_table context_switch_table synth_data ev_name phys_addr time_enabled time_running couldn't create mem-info datasrc datasrc_decode raw_buf mispred from_dsoname to_dsoname brstack brstacksym machine_pid vcpu cpumode addr_correlates_sym addr_dso_map_end addr_dso_map_start addr_dso_bid addr_dso addr_map_pgoff addr_symoff addr_symbol flags_disp insn_cnt cyc_cnt iregs uregs common_pid %s__%s trace_unhandled couldn't create Python dict __code__ common_cpu common_s common_ns common_comm common_callchain co_argcount 1.3.1  Compressed file is corrupt Unknown error, possibly a bug lzma: read error: %m
 lzma: write error: %m
 lzma: failed %s
 rb caml void byte double float long short boolean bool i8 i16 i32 i64 i128 isize u128 usize f64 \u{%x} {invalid syntax} {bug} {recursion limit reached} ::{ closure shim ::  +  .llvm. __ZN jit marker trying : %s
 /jit- .dump jit marker found: %s
 [anon: /memfd: injecting: %s
 %s/jitted-%d-%lu.so write ELF image %s
 cannot create jit ELF %s: %m
 injected: %s (%d)
 ELF initialization failed elf_begin failed cannot get ehdr cannot create section cannot get new data cannot get section header cannot allocate strsym elf_update 4 failed elf_update debug failed Overwrite existing hook: %s
 record_end record_start [bpf] bpf_trampoline_%lu bpf_dispatcher_%s .rodata bpf_metadata_  -- kernel too old? # bpf_prog_info %u:
 can't get prog info: %m
 CROSS_COMPILE riscv32 mips-unknown-linux-gnu- mipsel-linux-android- mips-linux-gnu- mips64-linux-gnu- mips64el-linux-gnuabi64- mips64-linux-gnuabi64- mipsel-linux-gnu- x86_64-pc-linux-gnu- x86_64-unknown-linux-gnu- i686-pc-linux-gnu- i586-pc-linux-gnu- i486-pc-linux-gnu- i386-pc-linux-gnu- i686-linux-android- i686-android-linux- x86_64-linux-gnu- i586-linux-gnu- sparc-unknown-linux-gnu- sparc64-unknown-linux-gnu- sparc64-linux-gnu- sh-unknown-linux-gnu- sh-linux-gnu- s390-ibm-linux- s390x-linux-gnu- riscv64-unknown-linux-gnu- riscv64-linux-android- riscv64-linux-gnu- riscv32-unknown-linux-gnu- riscv32-linux-android- riscv32-linux-gnu- powerpc-unknown-linux-gnu- powerpc-linux-gnu- powerpc64-unknown-linux-gnu- powerpc64-linux-gnu- powerpc64le-linux-gnu- aarch64-linux-android- aarch64-linux-gnu- arm-eabi- arm-linux-androideabi- arm-unknown-linux- arm-unknown-linux-gnu- arm-unknown-linux-gnueabi- arm-linux-gnu- arm-linux-gnueabihf- arm-none-eabi- arc-linux- arc-snps-linux-uclibc- arc-snps-linux-gnu- %s,%u,%u,%u$ %s-%u-%X-%X$  @   @ %lfGHz uncore_cha_ Unexpected: no CHAs found
 uncore_cha_%u uncore_imc_%u intel_bts GenuineIntel-6-A[DE] uncore_imc_ mem-ldst %s/ldlat=%u/ acr_mask Mode iostat is not supported
 %04x:%02hhx Failed to realloc memory
 %08x:%02hhx S%d-uncore_iio_%d<%04x:%02x>
 %6lu.%09lu%s%04x:%02x%s port,    port          %8.0f Inbound Read(MB) Inbound Write(MB) Outbound Read(MB) Outbound Write(MB) GenuineIntel, intel-pt.all-switch-events -%u caps/topa_multiple_entries psb_period %s psb_period %zu
 not  %s: failed, error %d
 caps/mtc caps/mtc_periods ,mtc,mtc_period=%d caps/psb_cyc caps/psb_periods ,psb_period=%d format/pt format/branch ,pt,branch %s default config: %s
 noretcomp mtc_period max_nonturbo_ratio caps/event_trace cyc_thresh caps/cycle_thresholds Intel PT snapshot size: %zu
 JITDUMP_USE_ARCH_TIMESTAMP Intel BTS: TSC not available
 Intel BTS snapshot size: %zu
 (sIs#) (sI) common_pc perf_sample_insn perf_set_itrace_options Set --itrace options. perf_sample_srcline perf_sample_srccode perf_config_get Get perf config entry pmu_events__test_soc_sys testarch testcpu GenuineIntel-6-BE GenuineIntel-6-C[56] GenuineIntel-6-(3D|47) GenuineIntel-6-56 GenuineIntel-6-4F GenuineIntel-6-DD GenuineIntel-6-9[6C] GenuineIntel-6-CF GenuineIntel-6-5[CF] GenuineIntel-6-7A GenuineIntel-6-B6 GenuineIntel-6-(3C|45|46) GenuineIntel-6-3F GenuineIntel-6-7[DE] GenuineIntel-6-6[AC] GenuineIntel-6-3A GenuineIntel-6-3E GenuineIntel-6-2D GenuineIntel-6-(57|85) GenuineIntel-6-BD GenuineIntel-6-(AA|AC|B5) GenuineIntel-6-1[AEF] GenuineIntel-6-2E GenuineIntel-6-CC GenuineIntel-6-A7 GenuineIntel-6-2A GenuineIntel-6-8F GenuineIntel-6-AF GenuineIntel-6-55-[01234] GenuineIntel-6-86 GenuineIntel-6-8[CD] GenuineIntel-6-2C GenuineIntel-6-25 GenuineIntel-6-2F AuthenticAMD-23-[[:xdigit:]]+ AuthenticAMD-25-[[:xdigit:]]+ AuthenticAMD-26-[[:xdigit:]]+ Value assigned must be a list |s |ii { type: sample } pmu(%s) |OOii evsel(%s/%s/) i|i Unknown CPU '%d' Unexpected header type %u s|sOO s|OO |ss Index out of range evlist([ ]) scale_unit encoding_desc event_type_desc deprecated sii MetricGroup MetricName MetricExpr MetricThreshold ScaleUnit Compat BriefDescription PublicDescription perf: Init failed! threads wakeup_events bp_addr bp_len cpustr Get tracepoint config. parse_events parse_metrics pmus Returns a sequence of pmus. COUNT_HW_CACHE_REFERENCES COUNT_HW_BRANCH_INSTRUCTIONS COUNT_HW_CACHE_OP_PREFETCH COUNT_HW_CACHE_RESULT_ACCESS COUNT_HW_CACHE_RESULT_MISS COUNT_SW_CONTEXT_SWITCHES COUNT_SW_ALIGNMENT_FAULTS COUNT_SW_EMULATION_FAULTS SAMPLE_IP SAMPLE_TID SAMPLE_ADDR SAMPLE_READ SAMPLE_CALLCHAIN SAMPLE_ID SAMPLE_CPU SAMPLE_PERIOD SAMPLE_STREAM_ID SAMPLE_RAW FORMAT_TOTAL_TIME_ENABLED FORMAT_TOTAL_TIME_RUNNING FORMAT_ID FORMAT_GROUP RECORD_MMAP RECORD_LOST RECORD_COMM RECORD_EXIT RECORD_THROTTLE RECORD_UNTHROTTLE RECORD_FORK RECORD_READ RECORD_SAMPLE RECORD_MMAP2 RECORD_AUX RECORD_ITRACE_START RECORD_LOST_SAMPLES RECORD_SWITCH RECORD_SWITCH_CPU_WIDE RECORD_MISC_SWITCH_OUT perf.evlist all_cpus compute_metric open the file descriptors. close the file descriptors. get_pollfd read_on_cpu reads an event. perf.evsel tracking tracking event. attribute type. attribute size. attribute config. attribute sample_period. attribute sample_type. attribute read_format. attribute wakeup_events. read counters perf.counts_values Name field Value of event ena Time for which enabled Time for which running Unique ID for an event lost Num of lost samples pmus.iterator perf.pmu perf.thread_map perf.cpu_map perf.context_switch_event sample_ip event ip sample_pid event pid sample_tid event tid sample_time event timestamp sample_addr event addr sample_id event id sample_stream_id event stream id event period sample_cpu event cpu event type next_prev_pid next/prev pid next_prev_tid next/prev tid perf.sample_event perf.read_event perf.lost_event number of lost events perf.throttle_event perf.comm_event process name perf.task_event event ppid event ptid perf.mmap_event event misc start of the map map length page offset filename backing store  Perf can support %d CPUs. Consider raising MAX_NR_CPUS
 libperf: Unexpected characters at end of cpu list ('%s'), using online CPUs.            libperf: Number of online CPUs (%d) differs from the number configured (%d) the CPU map will only cover the first %d CPUs.      libperf: idx %d: set output fd %d -> %d
        libperf: idx %d: mmapping fd %d
        libperf: %s: nr cpu values (may include -1) %d nr threads %d
   libperf: Miscounted nr_mmaps %d vs %d
  libperf: %s: nr cpu values %d nr threads %d
    failed to keep up with mmap data. (warn only once)
     libperf: %s: buf=%p, start=%lx
 libperf: Finished reading overwrite ring buffer: rewind
        libperf: Finished reading overwrite ring buffer: get start
     Cannot determine the current working directory   Error: too many args to run %s
        %s available from elsewhere on your $PATH
      cannot be used with switch `%c' expects an unsigned numerical value     should not happen, someone must be hit on the forehead  STOP_AT_NON_OPTION and KEEP_UNKNOWN don't go together    Error: did you mean `--%s` (with two dashes ?)
         Error: Ambiguous option: %s (could be --%s%s or --%s%s)
       SUBCMD_HAS_NOT_BEEN_INITIALIZED GTK browser requested but could not find %s
    Not enough memory to display remaining hits
    WARN: jump target inconsistency, press 'o', notes->offsets[%#x] = NULL
 Only available for source code lines.   ui/browsers/../../util/annotate.h       Annotation has no source code.  Press 'h' for help on key bindings      DWARF debuginfo not found.

Data-type in this DSO will not be displayed.
Please make sure to have debug information.    UP/DOWN/PGUP
PGDN/SPACE    Navigate
</>           Move to prev/next symbol
q/ESC/CTRL+C  Exit

ENTER         Go to target
H             Go to hottest instruction
TAB/shift+TAB Cycle thru hottest instructions
j             Toggle showing jump to target arrows
J             Toggle showing number of jump sources on targets
n             Search next string
o             Toggle disassembler output/simplified view
O             Bump offset level (jump targets -> +call -> all -> cycle thru)
s             Toggle source code view
t             Circulate percent, total period, samples view
c             Show min/max cycle
/             Search string
k             Toggle line numbers
l             Show full source file location
P             Print to [symbol_name].annotation file.
r             Run available scripts
p             Toggle percent type [local/global]
b             Toggle percent base [period/hits]
B             Branch counter abbr list (Optional)
?             Search string backwards
f             Toggle showing offsets to full address
T             Toggle data type display
  %d: nr_ent=%d, height=%d, idx=%d, top_idx=%d, nr_asm_entries=%d Huh? No selection. Report to linux-kernel@vger.kernel.org       Actions are only available for assembly lines.  Actions are only available for function call/return & jump/branch instructions. 
 The branch counter is not available.
 The called function was not found.      Not enough memory for annotating '%s' symbol!
  Annotate type: '%s' (%d samples)        UP/DOWN/PGUP
PGDN/SPACE    Navigate
</>           Move to prev/next symbol
e             Expand/Collapse current entry
E             Expand/Collapse all children of the current
q/ESC/CTRL+C  Exit

   Can't search all data files due to memory shortage.
    Too many perf data files in PWD!
Only the first 32 files will be listed.
       Data switch failed due to memory shortage!
     Won't switch the data files due to
no valid data file get selected!
    To zoom out press ESC or ENTER + "Zoom out of %s(%d) thread"    To zoom out press ESC or ENTER + "Zoom out of %s thread"        To zoom out press ESC or ENTER + "Zoom out of %s DSO"   Run scripts for samples of thread [%s]%s        Run scripts for samples of symbol [%s]%s        Events are being lost, check IO/CPU overload!

You may want to run 'perf' using a RT scheduler policy:

 perf top -r 80

Or reduce the sampling frequency.      %d: nr_ent=(%d,%d), etl: %d, rows=%d, idx=%d, fve: idx=%d, row_off=%d, nrows=%d Press '?' for help on key bindings      Press 'f' again to re-enable the events Press 'f' to disable the events or 'h' to see other hotkeys     Max event group index to sort is %d (index from 0 to %d)        Annotation is only available for symbolic views, include "sym*" in --sort to use it.    No samples for the "%s" symbol.

Probably appeared just in a callchain  Too many perf.hist.N files, nothing written!    Please enter the name of symbol you want to see.
To remove the filter later, press / + ENTER.   Please enter the value you want to hide entries under that percent.     , use 'h'/'?'/F1 to see actions Zoom %s %s DSO (use the 'k' hotkey to zoom directly into the kernel)    %s [%s] callchain (one level, same as '+' hotkey, use 'e'/'c' for the whole main level entry)   Show context for individual samples %s  Switch to another data file in PWD      ESC: exit, ENTER|->: Browse histograms  Press ESC to exit, %s / to search       Prefix with 0x to search by address     Show individual samples with assembler  Show individual samples with source     Show samples with custom perf script arguments  Enter perf script command line (without perf script prefix)     --show-switch-events --show-task-events         %s script %s%s --time %s %s%s %s%s --ns %s %s %s %s %s | less +/%s      ESC: exit, ENTER|->: Select option      maximum size of symbol name reached!    ^blx?(cc|cs|eq|ge|gt|hi|le|ls|lt|mi|ne|pl|vc|vs)?$      ^bx?(cc|cs|eq|ge|gt|hi|le|ls|lt|mi|ne|pl|vc|vs)?$       ^[ct]?br?\.?(cc|cs|eq|ge|gt|hi|hs|le|lo|ls|lt|mi|ne|pl|vc|vs)?n?z?$     lea [%x] address of -%#x(stack) -> reg%d        lea [%x] address of %#x(reg%d) -> reg%d lea [%x] address of %s%#x(reg%d) -> reg%d       mov [%x] stack canary -> reg%d
 mov [%x] this-cpu addr=%#lx -> reg%d    mov [%x] addr %#x(reg%d) -> reg%d       mov [%x] global addr=%lx -> reg%d       mov [%x] percpu %#x(reg%d,reg%d) -> reg%d       mov [%x] percpu %#x(reg%d) -> reg%d     mov [%x] pointer %#x(reg%d) -> reg%d    %*[^,],%u,%[^,],%[^,],%[^,],%s  %s %s: addr2line read address for sentinel: %s  %s %s: addr2line read line: %s  %s %s: addr2line filename:number : %s   addr2line missing ':' in filename split
        Failed to allocate memory for addr2line could not start addr2line (%s) for %s: start_command return code %d
    %s %s: addr2line_subprocess_init failed
        Detected LLVM addr2line style
  Detected binutils addr2line style
      %s %s: addr2line configuration failed
  Unknown/broken addr2line style
 %s %s: could not send request
  %s %s: could not read first record
     %s %s: could not read sentinel record
  %s %s: unexpected record instead of sentinel    ----------------------------------------------
 Failed to add disassembler %d
  Not enough memory for annotate.disassembler_style
      Not enough memory for annotate.objdump
 Not enough memory for annotate.addr2line
       %s variable unknown, ignoring...        %s(%d): ERANGE! sym->name=%s, start=%#lx, addr=%#lx, end=%#lx
  %s(%d): ENOMEM! sym->name=%s, start=%#lx, addr=%#lx, end=%#lx, func: %d
        %#lx %s: period++ [addr: %#lx, %#lx, evidx=%d] => nr_samples: %lu, period: %lu
 BB with bad start: addr %lx start %lx sym %lx saddr %lx
         '+' Event occurrences may be lost due to branch counter saturated
     --prefix-strip requires --prefix
        %-*.*s|	Source code & Disassembly of %s for %s (%lu samples, percent: %s)
     (Average IPC: %.2f, IPC Coverage: %.1f%%)       problem processing %d event, skipping it.
      Downloading debug info with build id %s
        build <%s> already linked to %s
        Failed to update/scan SDT cache for %s
 Truncating build_id size from %zd
      bad config value for '%s' in %s, ignoring...
   bad config value for '%s', ignoring...
 bad config file line %d in %s
  Not enough memory to process %s/.perfconfig, ignoring it.
      File %s not owned by current user or root, ignoring it.
        Error in the given config file: wrong config key-value pair %s=%s
      No vmlinux file%s
was found in the path.

Note that annotation using /proc/kcore requires CAP_SYS_RAWIO capability.

Please use:

  perf buildid-cache -vu vmlinux

or:

  --vmlinux vmlinux
   Please link with binutils's libopcode to enable BPF annotation  Problems with arch specific instruction name regular expressions.       Problems while parsing the CPUID in the arch specific initialization.   The %s BPF file has no BTF section, compile with -g or use pahole -J.   Couldn't determine the file %s type.    Internal error: Invalid %d error code
  Failure allocating memory for tab expansion
    %s %s%s --start-address=0x%016lx --stop-address=0x%016lx %s -d %s %s %s %c%s%c %s%s -C "$1"     Failure allocating memory for the command to run
       Failure creating FILE stream for %s
    %s: filename=%s, sym=%s, start=%#lx, end=%#lx
  annotating [%p] %30s : [%p] %30s
       Reading raw instruction from : %s using dso__data_read_offset
  unknown stat config term %llu
   %d/%d - nr_namespaces: %u
		[   %d/%d: [%#llx(%#llx) @ %#llx]: %c %s
   %d/%d: [%#llx(%#llx) @ %#llx <%s>]: %c%c%c%c %s
        %d/%d: [%#llx(%#llx) @ %#llx %02x:%02x %llu %llu]: %c%c%c%c %s
        failed to get threads from event
       failed to get cpumap from event
         offset: %#llx size: %#llx flags: %#llx [%s%s%s%s]
      addr %llx len %u type %u flags 0x%x name %s
   Unsupported /proc/schedstat version %d.
        rounding mmap pages size to %s (%lu pages)
     Invalid argument for --mmap_pages/-m
   Read format differs %#lx vs %#lx
       FATAL: evlist->threads need to be set at this point (%s:%d).
   Error:	%m.
Hint:	Check /proc/sys/kernel/perf_event_paranoid setting.    For your workloads it needs to be <= 1
Hint:	   For system wide tracing it needs to be set to -1.
      Hint:	Try: 'sudo sh -c "echo -1 > /proc/sys/kernel/perf_event_paranoid"'
Hint:	The current value is %d. kernel/perf_event_max_sample_rate       Error:	%m.
Hint:	Check /proc/sys/kernel/perf_event_max_sample_rate.
Hint:	The current value is %d and %lu is being requested.   Error:	%m.
Hint:	Check /proc/sys/kernel/perf_event_mlock_kb (%d kB) setting.
Hint:	Tried using %zd kB.
 Hint:	Try 'sudo sh -c "echo %d > /proc/sys/kernel/perf_event_mlock_kb"', or
    Hint:	Try using a smaller -m/--mmap-pages value.        Control descriptor is not initialized
  Failed to add ctl fd entry: %m
 failed to write to ctl_ack_fd %d: %m
   Failed to read from ctlfd %d: %m
       failed: can't find '%s' event
  cannot locate proper evsel for the side band event
     enabling sample_id_all for all side band events
        test attr - failed to open event file   test attr - failed to write event file  unknown-ext-hardware-cache-type unknown-ext-hardware-cache-result       Error getting tracepoint format '%s': %m
       Unknown/empty format name: %s
  decreasing precise_ip by one (%d)
      The cycles event is not supported, trying to fall back to %s    kernel.perf_event_paranoid=%d, trying to fall back to excluding kernel and hypervisor  samples  Trying to fall back to excluding guest samples  No fallback found for '%s' for error %d Access to performance monitoring and observability operations is limited.
      Enforced MAC policy settings (SELinux) can limit access to performance
monitoring and observability operations. Inspect system audit records for
more perf_event access control information and adjusting the policy.
  No permission to enable %s event.

     Consider adjusting /proc/sys/kernel/perf_event_paranoid setting to open
access to performance monitoring and observability operations for processes
without CAP_PERFMON, CAP_SYS_PTRACE or CAP_SYS_ADMIN Linux capability.
More information can be found at 'Perf events and tool security' document:
https://www.kernel.org/doc/html/latest/admin-guide/perf-security.html
perf_event_paranoid setting is %d:
  -1: Allow use of (almost) all events by all users
      Ignore mlock limit after perf_event_mlock_kb without CAP_IPC_LOCK
>= 0: Disallow raw and ftrace function tracepoint access
>= 1: Disallow CPU event access
>= 2: Disallow kernel profiling
To make the adjusted perf_event_paranoid setting permanent preserve it
in /etc/sysctl.conf (e.g. kernel.perf_event_paranoid = <setting>)    The %s event is not supported.  Too many events are opened.
Probably the maximum number of open file descriptors has been reached.
Hint: Try again after reducing the number of events.
Hint: Try increasing the limit with 'ulimit -n <limit>' /proc/sys/kernel/perf_event_max_stack   Not enough memory to setup event with callchain.
Hint: Try tweaking /proc/sys/kernel/perf_event_max_stack
Hint: Current value: %d       No such device - did you specify an out-of-range profile CPU?   %s: PMU Hardware or event type doesn't support branch stack sampling.   %s: PMU Hardware doesn't support 'aux_output' feature   %s: PMU Hardware doesn't support 'aux_action' feature   %s: PMU Hardware doesn't support sampling/overflow-interrupts. Try 'perf stat'  'precise' request may not be supported. Try removing 'p' modifier.      No hardware sampling interrupt available.
      Unsupported event (%s) in per-thread mode, enable system wide with '-a'.        The PMU counters are busy/taken by another profiler.
We found oprofile daemon running, please stop it and try again.    The PMU %s counters are busy and in use by another process.
    Asking for the code page size isn't supported by this kernel.   Asking for the data page size isn't supported by this kernel.   Reading from overwrite event is not supported by this kernel.   clockid feature not supported.  The 'aux_action' feature is not supported, update the kernel.   The 'aux_output' feature is not supported, update the kernel.   Invalid event (%s) in per-thread mode, enable system wide with '-a'.    Cannot collect data source with the load latency event alone. Please add an auxiliary event in front of the load latency event. The sys_perf_event_open() syscall failed for event (%s): %m
"dmesg | grep -i perf" may provide additional information.
 LBR callstack option is only available to get user callchain information. Falling back to framepointers.
       Cannot use LBR callstack with branch stack. Falling back to framepointers.
     WARNING: The use of --call-graph=dwarf may require all the user registers, specifying a subset with --user-regs may render DWARF unwinding unreliable, so the minimal registers set (IP, SP) is explicitly forced.
     Cannot use DWARF unwind for function trace event, falling back to framepointers.
       Disabling user space callchains for function trace event.
      per-event callgraph setting for %s failed. Apply callgraph global setting for it
       Invalid ratio-to-prev value %lf
        Invalid use of ratio-to-prev term without preceding element in group
   Event using ratio-to-prev term must have a core PMU
    Previous event does not exist.
 Compared events ("%s", "%s") must have same PMU
        Event period term or count (-c) must be set when using ratio-to-prev term.
     switching off exclude_guest for PMU %s
 switching off branch counters support
  switching off branch HW index support
  switching off branch sample type no (cycles/flags)
     switching off deferred callchain support
       Using PERF_SAMPLE_READ / :S modifier is not compatible with inherit, falling back to no-inherit.
       switching off PERF_FORMAT_LOST support
 switching off weight struct support
    Kernel has no PERF_SAMPLE_CODE_PAGE_SIZE support
       Kernel has no PERF_SAMPLE_DATA_PAGE_SIZE support
       Kernel has no cgroup sampling support
  Kernel has no attr.aux_output support
  sys_perf_event_open: pid %d  cpu %d  group_fd %d  flags %#lx    
sys_perf_event_open failed, error %d
  WARNING: Ignored open failure for pid %d
       failed to attach bpf fd %d: %m
 WARNING: A requested CPU in '%s' is not supported by PMU '%s' (CPUs %s) for event '%s'
 <not enough memory for the callchain cursor>%s  PERF_COUNT_HW_STALLED_CYCLES_BACKEND    PERF_COUNT_HW_STALLED_CYCLES_FRONTEND   PERF_COUNT_HW_BRANCH_INSTRUCTIONS       PERF_COUNT_HW_CACHE_REFERENCES  PERF_COUNT_SW_EMULATION_FAULTS  PERF_COUNT_SW_ALIGNMENT_FAULTS  PERF_COUNT_SW_CONTEXT_SWITCHES  PERF_COUNT_HW_CACHE_OP_PREFETCH PERF_COUNT_HW_CACHE_RESULT_ACCESS       PERF_COUNT_HW_CACHE_RESULT_MISS { sample_period, sample_freq }  { wakeup_events, wakeup_watermark }     ERROR: switch-%s event not found (%s)
  HINT:  use 'perf evlist' to see the available event names
      failed to mmap perf event ring buffer, error %d
        failed to alloc mmap affinity mask, error %d
   failed to init mmap compressor, error %d
       failed to mmap data buffer, error %d
   failed to allocate aiocb for data buffer, error %m
     failed to allocate cblocks for data buffer, error %m
   failed to allocate data buffer, error %m
       failed to allocate data buffer area, error %m   Failed to allocate node mask for mbind: error %m
       Failed to bind [%p-%p] AIO buffer to node %lu: error %m
        invalid or unsupported event:   WARNING: failed to set leader: empty list       WARNING: event parser found nothing
    WARNING: events were regrouped to match PMUs
   evlist after sorting/fixing: '%s'
      WARNING: failed to provide error string or struct
      Failed to allocate memory for event parsing error: %s (%s)
     Weak modifier is for use with groups    Maximum combined precise value is 3, adding precision to "%s"   Run 'perf list' for a list of valid events
     Not enough memory to create evlist
     --filter option should follow a -e tracepoint or HW tracer option
      not enough memory to hold filter string
        Error: BPF filter is requested but perf is not built with BPF.
	Please make sure to build with libbpf and BPF skeleton.
        Failed to add UID filtering that uses BPF filtering.
   --exclude-perf option should follow a -e tracepoint option
     '%s' is not usable in 'perf stat'       valid terms: call-graph,stack-size
     ..after resolving event: %s/%s/
        Unable to find PMU or event on a PMU of '%s'    Failed to allocate new strlist for SDT
 Unknown ELF machine %d, standard arguments parse will be skipped.
      Unknown ELF machine %d, interrupt sampling register mask will be empty.
        Unknown ELF machine %d, user sampling register mask will be empty.
     Failed to find register %d for ELF machine type %u
     Failed to find IP register for ELF machine type %u
     Failed to find SP register for ELF machine type %u
     Skipping unsupported SDT argument: %s
  ^(\-)?([0-9]+)\((%r)?([1-2]?[0-9]|3[0-1])\)$    ^([+\-]?)([0-9]*)(\(?)(%[a-z][a-z0-9]+)(\)?)$   Couldn't bump rlimit(MEMLOCK), failures may take place when creating BPF maps, etc
     this should not happen, your vsnprintf is broken        ............................................................................................................................................................................................................... ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------    PerfTop:%8.0f irqs/sec  kernel:%4.1f%%  exact: %4.1f%% lost: %lu/%lu drop: %lu/%lu [    PerfTop:%8.0f irqs/sec  kernel:%4.1f%% us:%4.1f%% guest kernel:%4.1f%% guest us:%4.1f%% exact: %4.1f%% [     Internal error: passing unmasked cpumode (%x) to is_kernel_module       Failed to check whether %s is a kernel module or not. Assume it is.     DSO data fd counter out of bounds.      DSO %s is still in rbtree when being deleted!
  unrecognized DSO data encoding %d
      %s/sys/module/%.*s/notes/.note.gnu.build-id     Internal tools/perf/ library error      acpi_processor_ffh_cstate_enter mwait_idle_with_hints.constprop.0       %s/proc/{kallsyms,modules} inconsistency while looking for "%s" module!
        Failed to open %s. Note /proc/kcore requires CAP_SYS_RAWIO capability to access.
       Using %s for kernel object code
        Looking at the vmlinux_path (%d entries long)
  No kallsyms or vmlinux with build-id %s was found
      Annotation needs to be init before symbol__init()
      '.' is the only non valid --field-separator argument
   failed to parse parallelism filter list
        Requested parallelism level %d is invalid.
     /proc/sys/kernel/kptr_restrict  /usr/lib/debug/boot/vmlinux-%s  /usr/lib/debug/lib/modules/%s/vmlinux   /usr/lib/debug/boot/vmlinux-%s.debug    Bad metric-id encoding in: '%s' Cannot find metric or group `%s'
       Try disabling the NMI watchdog to comply NO_NMI_WATCHDOG metric constraint:
    echo 0 > /proc/sys/kernel/nmi_watchdog
    perf stat ...
    echo 1 > /proc/sys/kernel/nmi_watchdog
    Events in '%s' fully contained within '%s'
     Cannot resolve IDs for %s: %s
  failed: recursion detected for %s
      Not grouping metric %s's events.
       Use hardware aware grouping instead of traditional metric grouping method
      copying metric event for cgroup '%s': %s (idx=%d)
      devices/system/cpu/cpu%d/cache/index%d/ # compressed : %s, level = %d, ratio = %d
      # directory data version : %lu
 # contains AUX area data (e.g. instruction trace)
      # contains samples with branch stack
   # CPU %d: Core ID %d, Die ID %d, Socket ID %d
  # Core ID, Die ID and Socket ID information is not available
   # CPU %d: Core ID %d, Socket ID %d
     # Core ID and Socket ID information is not available
   # memory nodes (nr %d, block size 0x%llx):
     Failed to lseek to %lu offset for feature %d, continuing...
    # %s info available, use -I to display
 unknown feature %d, continuing...
      # sample duration : %10.3f ms
  # pmu mappings: not available
  # pmu mappings: unable to read
 # node%u meminfo  : total = %lu kB, free = %lu kB
      Error: calling %s in pipe-mode.
        failed to write buildid table
  cannot find event format for %d
        # %s pmu capabilities: not available
   # reference time: %s = %ld.%06d (TOD) = %ld.%09ld (%s)
 Failed to process auxtrace index
       Failed to write auxtrace index
 Pipe ABI%d perf.data file detected
     ABI%d perf.data file detected, need_swap=%d
    build id event received for %s: %s [%zu]
       Failed to read buildids, continuing...
 %s: couldn't read %s, does this arch have topology information?
        Failed to write MEM_TOPOLOGY, size %zd nodes
   %s/devices/system/node/node%lu  failed: can't open memory sysfs data '%s'
      # AMD systems uses ibs_op// PMU for some precise events, e.g.: cycles:p, see the 'perf list' man page for further details.
     pmu capabilities not available
 %s pmu capabilities not available
      cpu pmu capabilities not available
     interpreting btf from systems with endianness is not yet supported
     interpreting bpf_prog_info from systems with endianness is not yet supported
   detected invalid bpf_prog_info
 Reserved bits are set unexpectedly. Please update perf tool.
   Unknown sample type (0x%llx) is detected. Please update perf tool.
     Unknown read format (0x%llx) is detected. Please update perf tool.
     Unknown branch sample type (0x%llx) is detected. Please update perf tool.
      # event desc: not available or unable to read
  devices/system/memory/block_size_bytes  failed to write feature section
        File contains data but offset unknown
  failed to write perf header attribute
  Invalid regular expression %s
  Failed to open /proc/schedstat
 failed to write perf pipe header
       Perf file header corrupt: header overlaps attrs
        Perf file header corrupt: header overlaps data
 Perf file header corrupt: Attributes and data overlap
  In-place update not supported when byte-swapping is required
   WARNING: The %s file's data size field is 0 which is unexpected.
Was the 'perf record' command properly terminated?
    ERROR: The %s file's attr size field is 0 which is unexpected.
Was the 'perf record' command properly terminated?
      cannot read %d bytes of header attr
    file uses a more recent and unsupported ABI (%zu bytes extra)
  invalid record type %d in pipe-mode
    failed to get event_update cpus
        %s: repiping tracing data padding       %s: tracing data size mismatch  not enough memory to create child for code path tree    Warning: empty node in callchain tree
  not enough memory for the code path tree        not enough memory for the code path branch statistics   callchain cursor creation failed        callchain: Incorrect stack dump size (max %ld): %s
     callchain: No more arguments needed for --call-graph lbr
       callchain: Unknown --call-graph option value: %s
       callchain: deferred callchain only works with FP
       Invalid callchain sort key: %s
 Invalid callchain threshold: %s
        Invalid callchain print limit: %s
      Can't register callchain params
        failed to allocate read_values threads arrays   failed to allocate read_values counters array   failed to enlarge read_values threads arrays    failed to enlarge read_values counters array    failed to enlarge read_values ->values array    INTERNAL ERROR: Failed to allocate counterwidth array
  
. ... raw event: size %d bytes
        invalid callchain context: %ld
 Problems setting modules path maps, continuing anyway...
       Discarding thread maps for %d:%d
       Failed to join map groups for %d:%d
    problem inserting idle task for machine pid %d
 problem processing PERF_RECORD_COMM, skipping event.
   
WARNING: kernel seems to support more namespaces than perf tool.
Try updating the perf tool..

        
WARNING: perf tool seems to support more namespaces than the kernel.
Try updating the kernel..

       problem processing PERF_RECORD_NAMESPACES, skipping event.
     : id:%lu: lost samples :%llu%s
 %s: unsupported cpumode - ignoring
     Failed to write kernel text poke at %#llx
      Failed to find kernel text poke address map for %#llx
  Added extra kernel map %s %lx-%lx
      Problems creating module maps, continuing anyway...
    Problems creating module maps for guest %d, continuing anyway...
       Problems creating extra kernel maps, continuing anyway...
      invalid directory (%s). Skipping.
      removing erroneous parent thread %d/%d
 problem processing PERF_RECORD_FORK, skipping event.
   Failed to allocate space for stitched LBRs. Disable LBR stitch
 corrupted branch chain. skipping...
    Not resolving symbols with an unwinder isn't currently supported
       problem processing PERF_RECORD_MMAP2, skipping event.
  problem processing PERF_RECORD_MMAP, skipping event.
   %.*s/platforms/%.*s/arch-%s/usr/lib/%s  %.*s was updated (is prelink enabled?). Restart the long running apps that use it!
     no symbols found in %s, maybe install a debug package?
 Internal error: map__kmap with a non-kernel map
        Internal error: map__kmaps with a non-kernel map
       Internal error: kernel dso with non kernel map
 overlapping maps in %s (disable tui for more info)
     
Reloading kvm_intel module with vmm_exclusive=0
will reduce the gaps to only guest's timeslices.       Processed %d events and lost %d chunks!

Check IO/CPU overload!

       Processed %lu samples and lost %3.2f%%!

       AUX data lost %lu times out of %u!

    module/kvm_intel/parameters/vmm_exclusive       AUX data had gaps in it %lu times out of %u!

Are you running a KVM guest in the background?%s

        AUX data detected collision  %lu times out of %u!

     Found %u unknown events!

Is this an older tool processing a perf.data file generated by a more recent tool?

If that is not the case, consider reporting to linux-kernel@vger.kernel.org.

    %u samples with id not present in the header
   Found invalid callchains!

%u out of %u events were discarded for this reason.

Consider reporting to linux-kernel@vger.kernel.org.

   %u unprocessable samples recorded.
Do you have a KVM guest running and not using 'perf kvm'?
   %u out of order events recorded.
       %d map information files for pre-existing threads were
not processed, if there are samples for addresses they
will not be resolved, you may find out which are these
threads by running with -v and redirecting the output
to a file.
The time limit to process proc map is too short?
Increase it by --proc-map-timeout
       cpu_map swap: unsupported long size
    ... %s regs: mask 0x%lx ABI %s
 failed to parse original sample
        incompatible file format (rerun with -v to learn more)
 WARNING: No sample_id_all support, falling back to unordered processing
        (IP, 0x%x): %d/%d: %#lx period: %lu addr: %#lx
 ..... %2lu: %016lx
..... %2lu: %016lx
  ..... %2lu: %016lx -> %016lx %hu cycles %s%s%s%s %x %s %s
      ... branch stack counters: nr:%lu (counter width: %u max counter nr:%u)
        ... ustack: size %lu, offset 0x%x
      Unsupported header type %u, please consider updating perf.
     Unexpected perf_event_attr size
        %s: head=%#lx event->header.size=%#x, mmap_size=%#zx: fuzzed or compressed perf.data?
  %#lx [%#x]: failed to process type: %d
 %#lx [%#x]: failed to process type: %d [%m]
    failed to allocate memory to read event
        unexpected end of event stream
 No trace sample to read. Did you call 'perf %s'?
        (excludes AUX area (e.g. instruction trace) decoded / synthesized events)      File does not contain CPU events. Remove -C option to proceed.
 Requested CPU %d too large. Consider raising MAX_NR_CPUS
       Couldn't allocate memory for decompression
     Failure to allocate sample user_regs    Failure to allocate sample intr_regs    Invalid counter set entry at %zd
       Invalid counter set data encountered
       [%#08zx] Trailer:%c%c%c%c%c Cfvn:%d Csvn:%d Speed:%d TOD:%#lx
      		1:%lx 2:%lx 3:%lx TOD-Base:%#lx Type:%x

         [%#08zx] Counterset:%d Counters:%d
 	Counter:%03zd %s Value:%#018lx
        Invalid %s raw data encountered
        	Counter:%03d %s Value:%#018lx
  L3MissOnly %d FetchOcMiss %d FetchL3Miss %d    ibs_fetch_ctl:	%016llx MaxCnt %7d Cnt %7d Lat %5d En %d Val %d Comp %d%s PhyAddrValid %d%s L1TlbMiss %d L2TlbMiss %d RandEn %d%s%s
     ic_ibs_ext_ctl:	%016llx IbsItlbRefillLat %3d
   Invalid raw IBS Fetch MSR data encountered
     ibs_op_ctl:	%016llx MaxCnt %9d%s En %d Val %d CntCtl %d=%s CurCnt %9d%s
        ibs_op_data:	%016llx CompToRetCtr %5d TagToRetCtr %5d%s%s%s BrnRet %d  RipInvalid %d BrnFuse %d Microcode %d
   ibs_op_data2:	%016llx %sRmtNode %d%s
    DcL1TlbMiss %d DcL2TlbMiss %d   DcL1TlbHit2M %d DcL1TlbHit1G %d        ibs_op_data3:	%016llx LdOp %d StOp %d%s%s%s DcMiss %d DcMisAcc %d DcWcMemAcc %d DcUcMemAcc %d DcLockedOp %d DcMissNoMabAlloc %d DcLinAddrValid %d DcPhyAddrValid %d%s%s SwPf %d%s%s DcMissLat %5d TlbRefillLat %5d
     Invalid raw IBS Op MSR data encountered
         DataSrc 1=Local L3 or other L1/L2 in CCX        DataSrc 2=Another CCX cache in the same NUMA node       DataSrc 5=Another CCX cache in a different NUMA node    DataSrc 7=MMIO/Config/PCI/APIC  DataSrc 12=Coherent Memory of a different processor type       next_flush - ordered_events__flush PRE  %s, nr_events %u
       Processing time ordered events...       next_flush - ordered_events__flush POST %s, nr_events %u
       last flush, last_flush_type %d
 alloc size %luB (+%zu), max %luB
       allocation limit reached %luB
  broken map groups on thread %d/%d parent %d/%d
 scandir for %d returned empty, skipping
        Couldn't resolve comm name for pid %d
  yyset_lineno called with no buffer      yyset_column called with no buffer      out of dynamic memory in yy_create_buffer()     out of dynamic memory in yyensure_buffer_stack()        flex scanner push-back overflow fatal flex scanner internal error--end of buffer missed fatal error - scanner input buffer overflow     out of dynamic memory in yy_get_next_buffer()   fatal flex scanner internal error--no action found      out of dynamic memory in yy_scan_buffer()       out of dynamic memory in yy_scan_bytes()        Unable to find event on a PMU of '%s'   WARNING: event '%s' not valid (bits %s of %s '%llx' not supported by kernel)!
  alias %s differs in field '%s' ('%s' != '%s')
  WARNING: '%s' format '%s' requires 'perf_event_attr::config%d'which is not supported by this version of perf!
  unknown term '%s' for pmu '%s'  Required parameter '%s' not specified
  value too big for format (%s), maximum is %llu  Failure to parse '%s' terms '%s': %d
   Failed to parse terms '%s': %d
 Cannot parse '%s' terms '%s': %d
       Attempt to set event's unit twice       Attempt to set event's scale twice      Attempt to set event snapshot twice     legacy-cache-config=0..0xffffff,        aux-action=(pause|resume|start-paused)  Failure to set up any core PMUs
        FATAL: not enough memory to print PMU events
   (see 'man perf-list' or 'man perf-record' on how to encode it)  Unable to encode DRM PMU type for %s
   Total memory active in one or more engines      Size of resident and purgeable memory buffers   Size of resident memory buffers Size of shared and private memory       Unhandled DRM PMU fdinfo line match '%s'
       unexpected drm event term (%s) %s       hwmon_pmu: not a hwmon file '%s'
       hwmon_pmu: not a hwmon item '%s' in file name '%s'
     hwmon_pmu: not a hwmon type '%s' in file name '%s'
     hwmon_pmu: empty label file %s %s
      hwmon_pmu: memory allocation failure
   hwmon_pmu: %s removing event '%s%d' that has no input file
     Unable to encode hwmon type from %s in valid PMU type
  unexpected hwmon event term (%s) %s     hwmon_pmu: not a directory: '%s/class/hwmon/%s'
        hwmon_pmu: failure to open '%s/class/hwmon/%s/name'
    Pulse width modulation fan control      <?xml version="1.0" standalone="no"?> 
 <!DOCTYPE svg SYSTEM "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
       <svg width="%i" height="%lu" version="1.1" xmlns="http://www.w3.org/2000/svg">
 <defs>
  <style type="text/css">
    <![CDATA[
       rect          { stroke-width: 1; }
             rect.process  { fill:rgb(180,180,180); fill-opacity:0.9; stroke-width:1;   stroke:rgb(  0,  0,  0); } 
         rect.process2 { fill:rgb(180,180,180); fill-opacity:0.9; stroke-width:0;   stroke:rgb(  0,  0,  0); } 
         rect.process3 { fill:rgb(180,180,180); fill-opacity:0.5; stroke-width:0;   stroke:rgb(  0,  0,  0); } 
         rect.sample   { fill:rgb(  0,  0,255); fill-opacity:0.8; stroke-width:0;   stroke:rgb(  0,  0,  0); } 
         rect.sample_hi{ fill:rgb(255,128,  0); fill-opacity:0.8; stroke-width:0;   stroke:rgb(  0,  0,  0); } 
         rect.error    { fill:rgb(255,  0,  0); fill-opacity:0.5; stroke-width:0;   stroke:rgb(  0,  0,  0); } 
         rect.net      { fill:rgb(  0,128,  0); fill-opacity:0.5; stroke-width:0;   stroke:rgb(  0,  0,  0); } 
         rect.disk     { fill:rgb(  0,  0,255); fill-opacity:0.5; stroke-width:0;   stroke:rgb(  0,  0,  0); } 
         rect.sync     { fill:rgb(128,128,  0); fill-opacity:0.5; stroke-width:0;   stroke:rgb(  0,  0,  0); } 
         rect.poll     { fill:rgb(  0,128,128); fill-opacity:0.2; stroke-width:0;   stroke:rgb(  0,  0,  0); } 
         rect.blocked  { fill:rgb(255,  0,  0); fill-opacity:0.5; stroke-width:0;   stroke:rgb(  0,  0,  0); } 
         rect.waiting  { fill:rgb(224,214,  0); fill-opacity:0.8; stroke-width:0;   stroke:rgb(  0,  0,  0); } 
         rect.WAITING  { fill:rgb(255,214, 48); fill-opacity:0.6; stroke-width:0;   stroke:rgb(  0,  0,  0); } 
         rect.cpu      { fill:rgb(192,192,192); fill-opacity:0.2; stroke-width:0.5; stroke:rgb(128,128,128); } 
         rect.pstate   { fill:rgb(128,128,128); fill-opacity:0.8; stroke-width:0; } 
            rect.c1       { fill:rgb(255,214,214); fill-opacity:0.5; stroke-width:0; } 
            rect.c2       { fill:rgb(255,172,172); fill-opacity:0.5; stroke-width:0; } 
            rect.c3       { fill:rgb(255,130,130); fill-opacity:0.5; stroke-width:0; } 
            rect.c4       { fill:rgb(255, 88, 88); fill-opacity:0.5; stroke-width:0; } 
            rect.c5       { fill:rgb(255, 44, 44); fill-opacity:0.5; stroke-width:0; } 
            rect.c6       { fill:rgb(255,  0,  0); fill-opacity:0.5; stroke-width:0; } 
            line.pstate   { stroke:rgb(255,255,  0); stroke-opacity:0.8; stroke-width:2; } 
  <title>fd=%d error=%d merges=%d</title>
        <rect x="%.8f" width="%.8f" y="%.1f" height="%.1f" class="%s"/>
        <title>#%d blocked %s</title>
  <title>#%d running %s</title>
  <desc>Switched because:
%s</desc>
      <text x="%.8f" y="%.8f" font-size="%.8fpt">%i</text>
   <g transform="translate(%.8f,%.8f)">
   <title>#%d waiting %s</title>
  <rect x="0" width="%.8f" y="0" height="%.1f" class="%s"/>
      <text transform="rotate(90)" font-size="%.8fpt"> %s</text>
     <rect x="%.8f" width="%.8f" y="%.1f" height="%.1f" class="cpu"/>
       <text x="%.8f" y="%.8f">%s</text>
      /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies      <text transform="translate(%.8f,%.8f)" font-size="1.25pt">%s</text>
    <title>%d %s running %s</title>
        <text transform="rotate(90)" font-size="%.8fpt">%s</text>
      <rect class="%s" x="%.8f" width="%.8f" y="%.1f" height="%.1f"/>
        <text x="%.8f" y="%.8f" font-size="%.8fpt">C%i</text>
  <line x1="%.8f" x2="%.8f" y1="%.1f" y2="%.1f" class="pstate"/>
 <text x="%.8f" y="%.8f" font-size="0.25pt">%s</text>
   <title>%s wakes up %s</title>
  <line x1="%.8f" y1="%.2f" x2="%.8f" y2="%.2f" style="stroke:rgb(32,255,32);stroke-width:0.009"/>
       <g transform="translate(%.8f,%.8f)"><text transform="rotate(90)" font-size="0.02pt">%s &gt;</text></g>
 <g transform="translate(%.8f,%.8f)"><text transform="rotate(90)" font-size="0.02pt">%s &lt;</text></g>
 <circle  cx="%.8f" cy="%.2f" r = "0.01"  style="fill:rgb(32,255,32)"/>
 <title>Wakeup from interrupt</title>
   <circle  cx="%.8f" cy="%.2f" r = "0.01"  style="fill:rgb(255,128,128)"/>
       <rect x="%i" width="%.8f" y="0" height="%.1f" class="%s"/>
     <text transform="translate(%.8f, %.8f)" font-size="%.8fpt">%s</text>
   <line x1="%.8f" y1="%.2f" x2="%.8f" y2="%lu" style="stroke:rgb(%i,%i,%i);stroke-width:%.3f"/>
  topology: can't parse siblings map
     No memory to alloc tracepoints list
    can't get tracing/events/header_page    can't record header_page file
  can't get tracing/events/header_event   can't record header_event file
 can't get tracing/events/ftrace can't get tracing/printk_formats        can't get tracing/saved_cmdline Python scripting not supported.  Install libpython and rebuild perf to enable it.
For example:
  # apt-get install python-dev (ubuntu)
  # yum install python-devel (Fedora)
  etc.
    Perl scripting not supported.  Install libperl and rebuild perf to enable it.
For example:
  # apt-get install libperl-dev (ubuntu)
  # yum install 'perl(ExtUtils::Embed)' (Fedora)
  etc.
    Error registering Python script extension: disabling it
        Error registering Perl script extension: disabling it
  printk format with empty entry  reading input file (size expected=%d received=%d)       not a trace file (missing 'tracing' tag)        '%s' event is ambiguous: it can be %s or %s
    Cannot find event field for %s.%s
      --fields weight shows the average value unlike in the --sort key.
      Not enough memory to set up --sort      Not enough memory to setup sort keys    Not enough memory to setup overhead keys        The "dcacheline" --sort key needs to know the cacheline size and it couldn't be determined on this system       Not enough memory to setup output fields        Samples: %lu%c of event%s '%s',%s%sEvent count (approx.): %lu   FATAL ERROR: Couldn't setup hists class
        kernel/perf_event_max_contexts_per_stack        devices/system/cpu/cpu%d/topology/%s    %s/devices/system/cpu/possible  sysfs path crossed PATH_MAX(%d) size
   Read out of bounds max cpus of %d
      Failed to read max cpus, using default of %d
   %s/devices/system/node/possible Failed to read max nodes, using default of %d
  cpu_map__new_data unknown type %d
      %s/devices/system/cpu/cpu%d/topology/die_cpus_list      %s/devices/system/cpu/cpu%d/topology/package_cpus_list  %s/devices/system/cpu/cpu%d/topology/core_siblings_list %s/devices/system/cpu/cpu%d/topology/core_cpus_list     %s/devices/system/cpu/cpu%d/topology/thread_siblings_list       %s/devices/system/node/node%d/meminfo   %s/devices/system/node/node%d/cpulist   must define events before cgroups
      PID/TID switch overriding SYSTEM        SYSTEM/CPU switch overriding PER-THREAD failed to read per-pkg counter
 Unmatched aggregation mode between aliases
     Failed to resolve counter for stat event.
      Failed to find perf count for CPU %d thread %d on event %s.
    
... id %llu, cpu %d, thread %d
        ... value %llu, enabled %llu, running %llu
     Unexpected CPU0 missing in aggregation for tool event.
 %s"metric-value" : "%f", "metric-unit" : "%s"   %s"core" : "S%d-D%d-C%d", "counters" : %d       %s"cache" : "S%d-D%d-L%d-ID%d", "counters" : %d %s"cluster" : "S%d-D%d-CLS%d", "counters" : %d  %s"die" : "S%d-D%d", "counters" : %d    %s"socket" : "S%d", "counters" : %d     %s"node" : "N%d", "counters" : %d       %s"event-runtime" : %lu, "pcnt-running" : %.2f   Performance counter stats for  Cannot allocate per-core aggr map for display
  %*s# Table of individual measurements:
  %17.9f +- %.9f seconds time elapsed    Some events weren't counted. Try disabling the NMI watchdog:
	echo 0 > /proc/sys/kernel/nmi_watchdog
	perf stat ...
	echo 1 > /proc/sys/kernel/nmi_watchdog
    cannot set frequency and period at the same time
       frequency and count are zero, aborting
 error: Maximum frequency rate (%'u Hz) exceeded.
       Please use -F freq option with a lower value or consider
       tweaking /proc/sys/kernel/perf_event_max_sample_rate.
  warning: Maximum frequency rate (%'u Hz) exceeded, throttling from %'u Hz to %'u Hz.
         The limit can be raised via /proc/sys/kernel/perf_event_max_sample_rate.
         The kernel will lower it when perf's interrupts take too long.
         Use --strict-freq to disable this throttling, refusing to record.
      Lowering default frequency rate from %u to %u.
Please consider tweaking /proc/sys/kernel/perf_event_max_sample_rate.
   couldn't read /proc/sys/kernel/perf_event_max_sample_rate
      info: Using a maximum frequency rate of %'d Hz
 not enough memory for the srcline node  not enough memory for the inline node   Failed to read build ID for %s
 Couldn't get COMM, tigd and ppid for pid %d
    Name: string not found for pid %d
      Tgid: string not found for pid %d
      PPid: string not found for pid %d
      Reading %s/proc/%d/task/%d/maps time out. You may want to increase the time limit by --proc-map-timeout
        cannot find cgroup mount point
 Not enough memory synthesizing mmap event for kernel modules
   Perf runs in non-root PID namespace but it tries to     gather process info from its parent PID namespace.
     Please mount the proc file system properly, e.g.        add the option '--mount-proc' for unshare command.
     Couldn't synthesize evsel unit.
        Couldn't synthesize evsel evsel.
       Couldn't synthesize evsel cpus.
        Couldn't synthesize evsel name.
        failed to create perf header attribute
 Couldn't synthesize thread map.
        No record header feature for header :%d
        Couldn't synthesize features.
  Couldn't record tracing data.
  Failed to open %s. Possibly CONFIG_SCHEDSTAT is disabled.
      Can't remove old data: Unknown file found (%s)
 Can't remove old data: %m (%s)
 Can't move data: %m (%s to %s)
 File %s not owned by current user or root (use -f to override)
 zero-sized data (%s), nothing to do!
   failed to get perf_event_mmap_page lock
        Synthesizing TSC conversion information
        perf_event_open(..., PERF_FLAG_FD_CLOEXEC) failed with unexpected error %d (%s)
        perf_event_open(..., 0) failed unexpectedly with error %d (%s)
 Out of memory: no thread stack
 Out of memory: discarding thread stack
 iostat mode is not supported on current platform
       
[ Hot streams in old perf data only ]  
[ Hot streams in new perf data only ]  unknown kvm exit code:%lld on %s
       kvm:kvm_s390_intercept_instruction      Prog Translation specification  Prog ASNtranslation specification       Prog PCtranslation specification        Prog Region second translation  DIAG (0x9c) time slice end directed     DIAG (0x204) logical-cpu utilization    DIAG (0x258) page-reference services    DIAG (0x288) watchdog functions DIAG (0x500) KVM virtio functions       SIGP conditional emergency signal       SIGP store additional status at address Instruction and program interruption    Multiple symbols with name '%s'
        Disambiguate symbol name by inserting #n after the name e.g. %s #2
     Or select a global symbol by inserting #0 or #g or #G
  N'th occurrence (N=%d) of symbol '%s' not found.
       Global symbol '%s' not found.
  Note that symbols must be functions.
   Failed to parse /proc/kallsyms
 Multiple kernel symbols with name '%s'
 AUX area tracing is not supported on this architecture
 auxtrace idx %d old %#lx head %#lx diff %#lx
   No AUX area tracing to snapshot
        Bad AUX area sampling option: '%s'
     Cannot add AUX area sampling to an AUX area event
      Cannot add AUX area sampling to a group leader
 AUX area sample size %u too big, max. %d
       Cannot add AUX area sampling because group leader is not an AUX area event
     AUX area sampling requires an AUX area event group leader plus other events to which to add samples
    AUX area sampling is not supported by kernel
   aux-action '%s' can only be used with AUX area event
   aux-action '%s' cannot be used for AUX area event itself
       Events with aux-action must have AUX area event group leader
   Synthesizing auxtrace information
       size: %#llx  offset: %#llx  ref: %#llx  idx: %u  tid: %d  cpu: %d
     Bad Instruction Tracing options '%s'
    cpu %d pid %d tid %d ip %#llx code %u: %s
     Error: number of address filters (%d) exceeds maximum (%d)
     Kernel addresses are restricted. Unable to resolve kernel symbols.
     Symbol '%s' (0x%lx) comes before '%s' (0x%lx)
  Symbol '%s' (0x%lx) comes before address 0x%lx)
        Cannot determine size of symbol '%s'
   Failed to load symbols from: %s
        File '%s' not found or has no symbols.
 Failed to determine filter for %s
Cannot determine file size.
  Failed to parse address filter: '%s'
   Filter format is: filter|start|stop|tracestop <start symbol or address> [/ <end symbol or size>] [@<file name>]
        Where multiple filters are separated by space or comma.
        %s 0x%llx Hints 0x%x Extensions 0x%x    %s 0x%llx HW:%u CState:%u Sub-CState:%u %s 0x%llx Last CState:%u Deepest CState:%u Wake Reason 0x%x     %s IP:%d Type 0x%02x Vector 0x%llx      Suppressing CYC timestamp 0x%lx less than current timestamp 0x%lx
      CTC timestamp 0x%lx last MTC %#x  CTC rem %#x
  Timestamp: calculated %g TSC ticks per cycle too big (c.f. CBR-based value %g), pos 0x%lx
      Timestamp: calculated %g TSC ticks per cycle c.f. CBR-based value %g, pos 0x%lx
        Timestamp: calculated %g TSC ticks per cycle c.f. unknown CBR-based value, pos 0x%lx
   ERROR: Failed to get instruction        ERROR: Conditional branch when expecting indirect branch        ERROR: Unexpected branch at FUP instruction     ERROR: Unexpected indirect branch       ERROR: Unexpected conditional branch    Buffer 1st timestamp 0x%lx ref timestamp 0x%lx
 Suppressing MTC timestamp 0x%lx less than current timestamp 0x%lx
      Suppressing backwards timestamp ERROR: RET when expecting conditional branch    ERROR: Bad RET compression (stack empty)        ERROR: Bad RET compression (TNT=N)      ERROR: Missing deferred TIP for indirect branch ERROR: Missing FUP after MODE.TSX       ERROR: Missing FUP after PTWRITE        ERROR: Missing FUP after EXSTOP WARNING: Unknown block type %u
 WARNING: Duplicate block type %u
       WARNING: Unknown block item %u type %d
 WARNING: Duplicate block item %u type %d
       timestamp: tsc_ctc_ratio_n %u
  timestamp: tsc_ctc_ratio_d %u
  Hop mode: decoding FUP and TIPs, but not TNT
   ERROR: First TSC is not in PSB+ Translated VM TSC %#lx -> %#lx    VMCS %#lx    TSC Offset %#lx
 ERROR: First TSC, unknown TSC Offset    ERROR: First TSC, no PIP, unknown TSC Offset    %s: intel_pt_ctc_to_tsc(decoder, new_ctc_delta) %#lx
   ERROR: Unknown TSC Offset for VMCS %#lx Fast forward towards timestamp 0x%lx
   Fast forward to next PSB timestamp 0x%lx
       Trace doesn't match instruction Never-ending loop (refer perf config intel-pt.max-loops)        TIP.PGD ip %#lx offset %#lx in %s hit filter: %s offset %#lx size %#lx
 TIP.PGD ip %#lx offset %#lx in %s is not in a filter region
    Intel Processor Trace: failed to deliver error event, error %d
 Intel PT missing data_src info
 Intel PT: failed to deliver event, error %d
    . ... Intel Processor Trace data: size %zu bytes
       ERROR: cpu %d expecting switch ip
      ERROR: guest sideband but no guest machine
     ERROR: thread has no dso for %#lx
      ERROR: thread has no map for %#lx
      ERROR: failed to read at offset %#lx    Emulated ptwrite signature found
       Emulated ptwrite signature not found
   queue %u decoding cpu %d pid %d tid %d
 PEBS-via-PT record with no applicable_counters
 PEBS-via-PT record with no matching event, hw_id %d
    queue %u processing 0x%lx to 0x%lx
     Intel Processor Trace requires ordered events
  queue %u cpu %d pid %d tid %d
  sched_switch: cpu %d tid %d time %lu tsc %#lx
  itrace_start: cpu %d pid %d tid %d time %lu tsc %#lx
   Expecting CPU-wide context switch event
        context_switch event has no tid
        Invalidated instruction cache for %s at %#lx
   event %u: cpu %d time %lu tsc %#lx      %s: filter string not null terminated
  Intel PT has no time information for VM Time Correlation
       Time ranges cannot be specified with VM Time Correlation
       MTC packets must have been enabled for VM Time Correlation
     Failed to parse VM Time Correlation options
    %s: missing sched_switch event
 %s: missing context_switch attribute flag
      range %d: perf time interval: %lu to %lu
       range %d: TSC time interval: %#lx to %#lx
      There are no selected events with Intel Processor Trace data
   Synthesizing '%s' event with id %lu sample type %#lx
   %s: failed to synthesize '%s' event type
       WARNING: Intel PT with pipe mode is not recommended.
         The output cannot relied upon.  In particular,
         timestamps and the order of events may be incorrect.
     Intel PT decoding without timestamps
   Intel BTS: failed to deliver error event, error %d
     Intel BTS: failed to deliver branch event, error %d
    Intel BTS requires ordered events
      . ... Intel BTS data: size %zu bytes
   There are no selected events with Intel BTS data
       Synthesizing 'branches' event with id %lu sample type %#lx
     %s: failed to synthesize 'branches' event type
 AmpereOne: Unknown data source (0x%x)
  ARM SPE: failed to deliver event, error %d
     . ... ARM SPE data: size %#zx bytes
    Old SPE metadata, re-record to improve decode accuracy
 No data or all data has been processed.
        SPE trace requires ordered events
      Arm SPE CONTEXT packets not found in the traces.
Matching of TIDs to SPE events could be inaccurate.
   Failed to parse Arm SPE metadata.
      You must only use i (instructions) --itrace period with Arm SPE. e.g --itrace=i1i
      Arm SPE has a hardware-based sampling period.

--itrace periods > 1i downsample by an interval of n SPE samples rather than n instructions.
    No selected events with SPE trace data
 Arm SPE supports only two bstack entries (PBT+TGT).
    ignoring unsupported address packet index: 0x%x
        . ... HISI PTT data: size %zu bytes
      %s %x %s %x %s %x %s %x %s %x %s %x %s %x %s %x
      %s pos:%#zx ip:%#lx P:%d CL:%d pid:%d.%d cpumode:%d cpu:%d
     s390 Auxiliary Trace: failed to deliver event
  Failed to find auxtrace log directory %s, continue with current directory...
   Missing auxtrace log directory %s, continue with current directory...
  s390 Auxiliary Trace: failed to deliver error event,error %d
   . ... s390 AUX data: size %zu bytes
    Invalid AUX trace data block size:%zu (type:%d bsdes:%hd dsdes:%hd)
    Invalid AUX trace basic entry [%#08zx]
     [%#08zx] Basic   Def:%04x Inst:%#04x %c%c%c%c AS:%d ASN:%#04x IA:%#018llx
		CL:%d HPP:%#018llx GPP:%#018llx
        Invalid AUX trace diagnostic entry [%#08zx]
        [%#08zx] Diag    Def:%04x %c
       Invalid AUX trace trailer entry [%#08zx]
           [%#08zx] Trailer %c%c%c bsdes:%d dsdes:%d Overflow:%lld Time:%#llx
		C:%d TOD:%#llx
        s390 Auxiliary Trace requires ordered events
   Failed to open counter set log file %s, continue...
    Failed to write counter set data
       Failed to open auxiliary log file %s,continue...
       Failed to write auxiliary data
 %s queue_nr:%d buffer:%ld offset:%#lx size:%#zx rest:%#zx
      [%#08lx] Invalid AUX trailer entry TOD clock base
      Unsupported --itrace options specified
 Failed to create sample for dtl entry
  . ... VPA DTL PMU data: size %zu bytes, entries is %zu
 dispatch_reason:%s, preempt_reason:%s, enqueue_to_dispatch_time:%d, ready_to_enqueue_time:%d, waiting_to_ready_time:%d
 All data in the queue has been processed.
      No selected events with VPA trace data
 migration_hibernation_page_fault        
CS ETM Trace: Unknown Header Version = %#lx    	Magic number Unknown	       %lx
       	Unknown parameter [%d]	       %lx
     
CS ETM Trace: OpenCSD is not linked in, please recompile with CORESIGHT=1
     	TRCDEVARCH                     %llx
   	TS_SOURCE                      %lld
   	PMU type/num cpus	       %llx
 unknown branch filter %s, check man page
       Error: Can't use --branch-any (-b) with --branch-filter (-j).
  Unknown register "%s", check man page or run "perf record %s?"
 ERROR: Failed to allocate command list for unknown command.
    WARNING: You called a perf program named '%s', which does not exist.
Continuing under the assumption that you meant '%s'
       in %0.1f seconds automatically...
      perf: '%s' is not a perf-command. See 'perf --help'.
   %s/bus/event_source/devices/%s/events/%s        failed: event '%s' not found, use '-e list' to get list of available events
    failed: event '%s' not supported
       Memory events are enabled on a subset of CPUs: %s
      HINT: no first/last sample time found in perf data.
Please use latest perf binary to execute 'perf record'
(if '--buildid-all' is enabled, please set '--timestamp-boundary').
 lookup(%s): ref metric name %s
 processing metric: %s EXIT: %f
 lookup(%s): ref val %f metric name %s
  No memory nodes, is CONFIG_MEMORY_HOTPLUG enabled?
     mem2node %03lu [0x%016lx-0x%016lx]
     WARNING: Failed to determine specified clock resolution.
       unknown clockid %s, check man page
     Bad evsel for tpebs find '%s'
  Tpebs event modifier broken '%s'
       perf record control write control message '%s' failed
  tpebs failed: perf record ack timeout for '%s'
 tpebs failed: did not received an ack for '%s'
 tpebs: perf record control ack failed
  tpebs: Failed to create control fifo    Could not create thread to process sample data.
        Using precomputed retirement latency data as no samples
        Missing PLT entry size for %s
  %s: problems reading %s PLT info.
      Failed to decompress (error %d) %s
     %s: truncating reading of build id in sysfs file %s: n_namesz=%u, n_descsz=%u.
 %s: .gnu_debugdata of ELF file %s has no data.
 %s: error reading .gnu_debugdata of %s: %s
     %s: using .gnu_debugdata of %s
 %s: build id mismatch for %s.
  %s: failed to find program header for symbol: %s st_value: %#lx
        %s: adjusting symbol: st_value: %#lx sh_addr: %#lx sh_offset: %#lx
     %s: adjusting symbol: st_value: %#lx p_vaddr: %#lx p_offset: %#lx
      Failed to get build-id from %s.
        Failed to add build-id cache: %s
       strlist__add failed with -ENOMEM
       run this command again with sudo.       try 'sudo mount -o remount,mode=755 /sys/kernel/tracing/'       No permission to %s tracefs.
Please %s
 Debugfs or tracefs is not mounted
Please try 'sudo mount -t tracefs nodev /sys/kernel/tracing/'
        %s/%s does not exist.
Please rebuild kernel with %s.
   Failed to open %s/%cprobe_events: %s
   CONFIG_KPROBE_EVENTS=y and CONFIG_UPROBE_EVENTS=y       Failed to open %s/kprobe_events: %s.
   Failed to open %s/uprobe_events: %s.
   Failed to synthesize probe trace event.
        Internal error: %s should have ':' but not.
    Failed to get a valid sdt type
 Failed to find debuginfo in debuginfod.
        Load debuginfo from debuginfod (%s)
    Module %s is not loaded, please specify its full path name.
    Failed to find the path for the kernel: %s
     Rebuild with CONFIG_DEBUG_INFO=y,       or install an appropriate debuginfo package.
   The %s file has no debug information.
  %s is blacklisted function, skip it.
   Semantic error :%s is bad for event name -it must follow C symbol-naming rule.
 snprintf() failed: %d; the event name '%s' is too long
  Hint: Set a shorter event with syntax "EVENT=PROBEDEF"
        EVENT: Event name (max length: %d bytes).
      Error: event "%s" already exists.
 Hint: Remove existing event by 'perf probe -d'
       or force duplicates by 'perf probe -f'
       or set 'force=yes' in BPF source.
       Add suffix failed: %d; the event name '%s' is too long
  Hint: Set a shorter event with syntax "EVENT=PROBEDEF"
        EVENT: Event name (max length: %d bytes).
      Internal error: "%s" is an invalid event name.
 Too many events are on the same function.
      Warning: The probe function (%s) is a GNU indirect function.
Consider identifying the final function used at run time and set the probe directly on that.
      Symbol %s address found : %lx
  Failed to find line range in debuginfo. Fallback to alternative
        function: %s, file:%s, line: %d Specified source line(%s) is not found.
        Failed to find source file path.
       Source file is shorter than expected.
  Failed to find the address of %s
       Semantic error :No file/function name in '%s'.
 Semantic error :'%s' is not a valid number.
    Semantic error :Start line must be smaller than end line.
      Semantic error :Tailing with invalid str '%s'.
 Semantic error :Only '@*' is not allowed.
      Semantic error :'%s' is not a valid function name.
     Semantic error :Too many probe arguments (%d).
 Semantic error :%s must be an SDT name.
        Semantic error :Invalid absolute address.
      Semantic error :There is non-digit char in line number.
        Semantic error :There is non-digit character in offset.
        Semantic error :SRC@SRC is not allowed.
        Semantic error :%%%s is not supported.
 This program has a bug at %s:%d.
       Semantic error :Lazy pattern can't be used with line number.
   Semantic error :Lazy pattern can't be used with offset.
        Semantic error :Offset can't be used with line number.
 Semantic error :File always requires line number or lazy pattern.
      Semantic error :Offset requires an entry function.
     Semantic error :Offset/Line/Lazy pattern can't be used with return probe.
      symbol:%s file:%s line:%d offset:%lu return:%d lazy:%s
 Semantic error :ftrace does not support user access
    Semantic error :Array index must be a number.
  Semantic error :Argument parse error: %s
       Semantic error :You can't specify local variable for kretprobe.
        Semantic error :Too few probe arguments.
       Semantic error :Failed to parse event name: %s
 try to find information at %lx in %s
   Failed to find corresponding probes from debuginfo.
    Failed to find probe point from both of dwarf and map.
 Probe group string='%s' is too long (>= %d bytes)
      WARN: Group name %s is ignored
 ERROR: Bootconfig doesn't support uprobes
      %sftrace.event.kprobes.%s.probe =       Failed to get current event list.
      A semaphore is associated with %s:%s and seems your kernel doesn't support it.
 %s accesses a variable by symbol name, but that is not supported for user application probe.
   Please upgrade your kernel to at least 3.14 to have access to feature %s
       Failed to add event to probe cache
     Failed to find symbols matched to "%s"
 No kprobe blacklist support, ignored
   Too many entries matched in the cache of %s
    Could not open debuginfo. Try to use symbols.
  Try to find probe point from debuginfo.
        Failed to get ELF symbols for %s
       Relocated base symbol is not found! Check /proc/sys/kernel/kptr_restrict
and /proc/sys/kernel/perf_event_paranoid. Or run as privileged perf user.

    Post processing failed or all events are skipped. (%d)
 An error occurred in debuginfo analysis (%d).
  Warning: No dwarf info found in the vmlinux - please rebuild kernel with CONFIG_DEBUG_INFO=y.
  Failed to load symbols from %s
 Please ensure the file is not stripped.
        Please ensure you can read the /proc/kallsyms symbol addresses.
If /proc/sys/kernel/kptr_restrict is '2', you can not read
kernel symbol addresses even if you are a superuser. Please change
it to '1'. If kptr_restrict is '1', the superuser can read the
symbol addresses.
In that case, please run this command again with sudo.
  Failed to find symbol %s in %s
 Too many functions matched in %s
       Found duplicated symbol %s @ %lx
       Too many symbols are listed. Skip it.
  Offset %ld is bigger than the size of %s
       Specified offset is out of %s
  Failed to find symbol at 0x%lx
 Failed to find "%s%%return",
 because %s is an inlined function and has no return point.
       Mapping for the register number %u missing on this architecture.
       Failed to get the type of %s.
  Semantic error: %s must be referred by '->'
    %s is not a data structure nor a union.
        Semantic error: %s is not a pointer nor array.
 Semantic error: %s must be referred by '.'
     Structure on a register is not supported yet.
  %s(type:%s) has no member %s.
  Failed to get the offset of %s.
        Too many( > %d) probe point found.
     Searching '%s' variable in context.
    Failed to find '%s' in this function.
  Converting variable %s into trace event.
       Failed to find the location of the '%s' variable at this address.
 Perhaps it has been optimized out.
 Use -V with the --range option to show '%s' location range.
     Sorry, we don't support this variable location yet.
    Failed to get a type information of %s.
        Failed to cast into string: %s(%s) is not a pointer nor array.
 Failed to get a type information.
      Failed to cast into string: %s is not (unsigned) char *.
       %s exceeds max-bitwidth. Cut down to %d bits.
  Failed to convert variable type: %s
    Caller must pass a scope DIE. Program error.
   Failed to find probe point in any functions.
   Failed to get call frame on 0x%jx
      Probe line found: line:%d addr:0x%llx
  Failed to find scope of probe point.
   This line is sharing the address with other lines.
     Please try to probe at %s:%d instead.
  Failed to find debug information for address %#lx
      No matched lines found in %s.
  A function DIE doesn't have decl_line. Maybe broken DWARF?
     Target program is compiled without optimization. Skipping prologue.
Probe on address 0x%lx to force probing at the function entry.

    Failed to get entry address of %s.
     %s has no valid entry address. skipped.
        Unable to get offset:Unexpected OP %x (%zd)
    Failed to get the declared file name of %s
     Failed to get CU from given DIE.
       Failed to get source lines on this CU.
 Failed to get line info. Possible error in debuginfo.
  Failed to get type, make it unknown.
   ELF MACHINE %x is not supported.
       Search %s from debuginfod -> %d
        Failed to find %s in debuginfod (%s)
    type='%s' size=%#lx (die:%#lx)
        -----------------------------------------------------------
    find data type for %s%#x(%s) at %s+%#lx
        cannot find CU for address %lx
 found by addr=%#lx type_offset=%#x
     unknown: code=%#x, number=%#lx
 found "%s" (die: %#lx) in scope=%d/%d (die: %#lx)       stack_offset=%#x type_offset=%#x
       cannot find a basic block from %lx to %lx
      prepend basic blocks: mismatched disasm line %lx -> %lx
        var [%lx] reg%d addr offset %x  chk [%x] reg%d offset=%s%#x ok=%d kind=%d       found by insn track: %s%#x(%s) type-offset=%#x
 Annotate type: '%s' in %s (%d samples):
        ============================================================================    unwind: access_mem 0x%lx not inside range 0x%lx-0x%lx
  unwind: access_mem addr 0x%lx, val %lx, offset %d
      unwind: %s:ip = 0x%lx (0x%lx)
  --all is currently unsupported for JSON output.
        --tod is currently unsupported for JSON output.
        Output file exists. Use --force to overwrite it.
       Failed to get mtime of source file, not writing captured-on     [ perf data convert: Converted '%s' into JSON data '%s' ]
      [ perf data convert: Converted and wrote %.3f MB (%lu samples) ]
       [ perf data convert: Skipped %lu samples ]
     # perf script event handlers, generated by perf script -g python
       # Licensed under the terms of the GNU GPL License version 2

   # The common_* event handler fields are the most useful fields common to
       # all events.  They don't necessarily correspond to the 'common_*' fields
      # in the format files.  Those fields not available as handler params can
       # be retrieved using Python functions of the form common_*(context).
   # See the perf-script-python Documentation for the list of available functions.

       from __future__ import print_function

 sys.path.append(os.environ['PERF_EXEC_PATH'] + \
       	'/scripts/python/Perf-Trace-Util/lib/Perf/Trace')
     
from perf_trace_context import *
      		print_header(event_name, common_cpu, common_secs, common_nsecs,
			common_pid, common_comm)

 		print('Sample: {'+get_dict_as_string(perf_sample_dict['sample'], ', ')+'}')

 		for node in common_callchain: 
				print("	[%%x] %%s%%s%%s%%s" %% (   
					node['ip'], node['sym']['name'],  
					"+0x{:x}".format(node['sym_off']) if 'sym_off' in node else "",   
					" ({})".format(node['dso'])  if 'dso' in node else "",    
					" " + node['sym_srcline'] if 'sym_srcline' in node else ""))      
				print("	[%%x]" %% (node['ip']))

  def trace_unhandled(event_name, context, event_fields_dict, perf_sample_dict):
 		print(get_dict_as_string(event_fields_dict))
 def print_header(event_name, cpu, secs, nsecs, pid, comm):
	print("%%-20s %%5u %%05u.%%09u %%8u %%-20s " %% \
	(event_name, cpu, secs, nsecs, pid, comm), end="")

     def get_dict_as_string(a_dict, delimiter=' '):
	return delimiter.join(['%%s=%%s'%%(k,str(v))for k,v in sorted(a_dict.items())])
        problem in Python trace event handler   couldn't create Python dictionary       Failed to resolve callchain. Skipping
  Error running python script %s
 Error starting python script %s
        failed to create calls processor        failed to create call path root Failed to setting regs in dict  ug! no event found for type %lu Unsupported decompressor flags  The input is not in the .xz format      Compressed file is truncated or otherwise corrupt       lzma: lzma_stream_decoder failed %s (%d)
       lzma: fopen failed on %s: '%m'
 Couldn't create compression stream.
    Failed to initialize compression stream: %s
    failed to compress %ld bytes: %s
       Couldn't create decompression stream.
  Failed to initialize decompression stream: %s
  failed to decompress (B): %zd -> %zd, dst_size %zd : %s
        capget syscall failed (%m) fall back on root check
     problem processing JIT mmap event, skipping it.
        version=%u
hdr.size=%u
ts=0x%llx
pid=%d
elf_mach=%d
use_arch_timestamp=%d
      wrong jitdump version %u, expected 1    jitdump file contains invalid or unsupported flags 0x%llx
      jitdump file uses arch timestamps but there is no timestamp conversion
 next_entry: unknown record type %d, skipping
   %s: thread %d not found or created
     error, jitted code must be sampled with perf record -k 1
       Fatal error (SEGFAULT) in perf hook '%s'
       unexpected bpf event type of %d
        Couldn't synthesize final BPF metadata for %s.
 Couldn't synthesize final BPF metadata.
        %s: failed to get BPF program info. aborting
   %s: duplicate add bpf info request for id %u
   %s: failed to get BTF of id %u %d
      %s: can't get next program: %m%s
       %s: failed to get fd for prog_id %u
    %s: the kernel is too old, aborting
    %s: mismatch in BPF sub program count and BTF function info count, aborting
    %s: failed to get BTF of id %u, aborting
       %s: failed to synthesize bpf images: %m
        # bpf_prog_info %u: %s addr 0x%llx size %u
     # 	sub_prog %u: %s addr 0x%llx size %u
 %s:%d: unexpected program type %u
      %s: mismatch in element count %u vs %u
 %s: mismatch in rec size %u vs %u
      %s: mismatch in array %p vs %llx
       binutils for %s not supported.
 Please install %s for %s.
You can add it to PATH, set CROSS_COMPILE or override the default using --%s.
        Invalid CPUID %s. Full CPUID is required, vendor-family-model-stepping
 Failed to read /proc/cpuinfo for TSC frequency
 Failed to find TSC frequency in /proc/cpuinfo
  devices/system/node/node0/cpulist       devices/system/cpu/cpu0/cache/index3/shared_cpu_list    Ignoring cpumask adjust for %s as unexpected first CPU
 Unexpected: unable to compute CHA number '%s'
  Unexpected: unable to compute IMC number '%s'
  Unexpected IMC %d for SNC%d mapping
    Failed to read valid CPU list from <sysfs>/%s
  Not enough memory synthesizing mmap event for extra kernel maps
        {%s/mem-loads-aux/,%s/mem-loads,ldlat=%u/}:P    '%s' does not have acr_mask format support
     '%s' does not have config2 format support
      '%s' has set config2 (acr_mask?) already, configuration not supported
  WARNING: Hw internally resets sampling period when L3 Miss Filtering is enabled
and tagged operation does not cause L3 Miss. This causes sampling period skew.
 AMD IBS doesn't support privilege filtering. Try again without the privilege modifiers (like 'k') at the end.   Topdown slots event can only be group leader in '%s'.   Perf metric event '%s' is duplicated in the same group (only one event is allowed) in '%s'.     %s/bus/event_source/devices/uncore_iio_%d       bus/event_source/devices/uncore_iio_%d/die%d    Invalid mapping data: iio_%d; die%d
    The -e and -M options are not supported.All chosen events/metrics will be dropped
      {uncore_iio_%x/event=0x83,umask=0x04,ch_mask=0xF,fc_mask=0x07/,	  uncore_iio_%x/event=0x83,umask=0x01,ch_mask=0xF,fc_mask=0x07/,	  uncore_iio_%x/event=0xc0,umask=0x04,ch_mask=0xF,fc_mask=0x07/,	  uncore_iio_%x/event=0xc0,umask=0x01,ch_mask=0xF,fc_mask=0x07/}      Unsupported uncore pmu configuration
   ^([a-f0-9A-F]{1,}):([a-f0-9A-F]{1,2})   Root port %04x:%02x were not found
     Requested root ports were not found
    Unrecognized root port format: %s
Please use the following format:
	 [domain]:[bus]
	 for example: 0000:3d
     #          time    port                 intel_pt and intel_bts may not be used together
        Invalid %s for %s. Valid values are: %s
        %s: mmap index %d old head %zu new head %zu
    %s: wrap-around %sdetected, adjusted old head %zu adjusted new head %zu
        Intel Processor Trace: TSC not available
       There may be only one intel_pt event
   module/kvm_intel/parameters/pt_mode     Snapshot mode (-S option) requires intel_pt PMU event (-e intel_pt)
    Snapshot mode (intel_pt PMU) and sample trace cannot be used together
  Cannot use clockid (-k option) with intel_pt
   intel_pt supports at most one event with aux-output
    pt=0 doesn't make sense, forcing pt=1
  Snapshot size %zu must not be greater than AUX area tracing mmap size %zu
      Failed to calculate default snapshot size and/or AUX area tracing mmap pages
   Intel PT snapshot size (%zu) may be too small for PSB period (%zu)
     Intel PT min. sample size: %zu max. sample size: %zu
   Sample size %zu must not be greater than AUX area tracing mmap size %zu
        Intel PT sample size (%zu) may be too small for PSB period (%zu)
       Invalid mmap size for Intel Processor Trace: must be at least %zuKiB and a power of 2
  %s: failed to create %s, error = %d
    Unable to select sched:sched_switch
    Intel Processor Trace decoding will not be possible except for kernel tracing!
 Intel BTS does not support AUX area sampling
   There may be only one intel_bts event
  Snapshot mode (-S option) requires intel_bts PMU event (-e intel_bts)
  intel_bts does not support per-cpu recording
   Invalid mmap size for Intel BTS: must be at least %zuKiB and a power of 2
      Get the common preempt count event field value. Get the common flags event field value. Get the common lock depth event field value.    Get the machine code instruction.       Get source file name and line number.   Get source file name, line number and line.     GenuineIntel-6-(97|9A|B7|BA|BF) GenuineIntel-6-(1C|26|27|35|36) GenuineIntel-6-55-[56789ABCDEF] GenuineIntel-6-(37|4A|4C|4D|5A) GenuineIntel-6-(4E|5E|8E|9E|A5|A6)      AuthenticAMD-23-([12][0-9A-F]|[0-9A-F]) AuthenticAMD-25-([245][[:xdigit:]]|[[:xdigit:]])        AuthenticAMD-26-([12467][[:xdigit:]]|[[:xdigit:]])      List members should be numbers  { type: context_switch, next_prev_pid: %u, next_prev_tid: %u, switch_out: %u }  { type: lost, id: %#llx, lost: %#llx }  { type: mmap, pid: %u, tid: %u, start: %#llx, length: %#llx, offset: %#llx, filename: %s }      { type: read, pid: %u, tid: %u }        { type: %sthrottle, time: %llu, id: %llu, stream_id: %llu }     { type: %s, pid: %u, ppid: %u, tid: %u, ptid: %u, time: %llu}   { type: comm, pid: %u, tid: %u, comm: %s }      |iKiKKiiiiiiiiiiiiiiiiiiiiiiKK  CPU %d is not part of evsel's CPUs      Thread %d is not part of evsel's threads        Unexpected event size: %zd < %u perf: can't parse sample, err=%d        Unknown metric '%s' for CPU '%d' and thread '%d'        Returns a list of metrics represented as string values in dictionaries. Parse a string of events and return an evlist.  Parse a string of metrics or metric groups and return an evlist.        COUNT_HW_STALLED_CYCLES_FRONTEND        COUNT_HW_STALLED_CYCLES_BACKEND CPU map union of all evsel CPU maps.    List of metric names within the evlist. compute metric for given name, cpu and thread   mmap the file descriptor table. poll the file descriptor table. get the poll file descriptor table.     adds an event selector to the list.     Apply default record options to the evlist.     Disable the evsels in the evlist.       Enable the evsels in the evlist.        open the event selector file descriptor table.  CPUs the event is to be used with.      threads the event is to be used with.   Iterator for the pmus string sequence.  Returns a sequence of events encoded as a dictionaries. Name of the PMU including suffixes.                 C      Y@      @      ?{Gz?                   00000000







      ?            0C      ??     j@    .A     @@      ư>                 ?33333333UUUUUUUU       MbP?    eA      >@      ?      )@      9@      $@      ?      @     K@      @      @     @?      ??      ?      ?     1@     `]@     0k@     s@     z@     v@     @     ܄@     @333333?       @      .@333333?         &.>                @                                             	                  
                                               P?             h      Z                              !      4      @      L            >                       is not availableis being ignoredSort by index only available with group events!  -F +brstackinsn                              with build id  	                                                                       /tmp/perf-kmod-X        PERFILE2h       PERFILE2               /proc/self/ns/mn                     ?        /tmp/perf-XXXXXX show reference e callgraph,                                                           Lost Auxiliary Trace Buffer                    /tmp/perf.gnu_debugdata.elf.XXXX/tmp/perf-kcore-{invalid syntax}{recursion limitn limit reached}              skgrn<:ORQhك[                              devices/system/node/node0/cpulisexclude_cmds    pFFPEpE0GF GPGGGEF                libbpf: %s size (%zu) is too small
     libbpf: %s has non-zero extra bytes
    libbpf: failed to dup FD %d to FD > 2: %d
 cgroup_inet_ingress cgroup_inet_egress cgroup_inet_sock_create cgroup_sock_ops sk_skb_stream_parser sk_skb_stream_verdict cgroup_device sk_msg_verdict cgroup_inet4_bind cgroup_inet6_bind cgroup_inet4_connect cgroup_inet6_connect cgroup_inet4_post_bind cgroup_inet6_post_bind cgroup_udp4_sendmsg cgroup_udp6_sendmsg lirc_mode2 flow_dissector cgroup_sysctl cgroup_udp4_recvmsg cgroup_udp6_recvmsg cgroup_getsockopt cgroup_setsockopt trace_raw_tp trace_fentry trace_fexit modify_return lsm_mac trace_iter cgroup_inet4_getpeername cgroup_inet6_getpeername cgroup_inet4_getsockname cgroup_inet6_getsockname xdp_devmap cgroup_inet_sock_release xdp_cpumap sk_lookup xdp sk_skb_verdict sk_reuseport_select    sk_reuseport_select_or_migrate perf_event trace_kprobe_multi lsm_cgroup struct_ops netfilter tcx_ingress tcx_egress trace_uprobe_multi cgroup_unix_connect cgroup_unix_sendmsg cgroup_unix_recvmsg cgroup_unix_getpeername cgroup_unix_getsockname netkit_primary netkit_peer trace_kprobe_session trace_uprobe_session trace_fsession unspec raw_tracepoint tracing cgroup iter netns kprobe_multi tcx uprobe_multi netkit sockmap hash array prog_array perf_event_array percpu_hash percpu_array stack_trace cgroup_array lru_hash lru_percpu_hash lpm_trie array_of_maps hash_of_maps devmap cpumap xskmap sockhash cgroup_storage reuseport_sockarray percpu_cgroup_storage queue stack sk_storage devmap_hash ringbuf inode_storage task_storage bloom_filter user_ringbuf cgrp_storage arena insn_array socket_filter kprobe sched_cls sched_act tracepoint cgroup_skb cgroup_sock lwt_in lwt_out lwt_xmit sock_ops sk_skb sk_msg cgroup_sock_addr lwt_seg6local sk_reuseport raw_tracepoint_writable cgroup_sockopt ext lsm syscall LIBBPF_LOG_LEVEL warn debug info    libbpf: unrecognized '%s' envvar value: '%s', should be one of 'warn', 'debug', or 'info'.
 %zu bytes %.1f KiB %.1f MiB libbpf: permission error while running as root; try raising 'ulimit -l'? current value: %s
 v1.7        libbpf: sec '%s': corrupted program '%s', offset %zu, size %zu
 libbpf: sec '%s': failed to allocate memory for prog '%s'
      libbpf: sec '%s': failed to get symbol name for offset %zu
     libbpf: sec '%s': program at offset %zu crosses section boundary
       libbpf: sec '%s': program '%s' is static and not supported
     libbpf: sec '%s': found program '%s' at insn offset %zu (%zu bytes), code size %zu insns (%zu bytes)
   libbpf: sec '%s': failed to alloc memory for new program '%s'
  libbpf: converted %zu BPF programs to native byte order
 %.*s bpf_struct_ops_ %s%s      libbpf: struct_ops init_kern: struct %s is not found in kernel BTF
     libbpf: struct_ops init_kern: struct %s data is not found in struct %s
 libbpf: struct_ops init_kern %s: type_id:%u kern_type_id:%u kern_vtype_id:%u
   libbpf: struct_ops init_kern %s: failed to resolve the size of member %s
       libbpf: struct_ops init_kern %s: Cannot find member %s in kernel BTF
   libbpf: struct_ops %s: member %s not found in kernel, skipping it as it's set to zero
  libbpf: struct_ops init_kern %s: bitfield %s is not supported
  libbpf: struct_ops init_kern %s: Unmatched member type %s %u != %u(kernel)
     libbpf: struct_ops init_kern %s: member %s is not a struct_ops program
 libbpf: struct_ops init_kern %s: kernel member %s is not a func ptr
    libbpf: struct_ops init_kern %s func ptr %s: invalid reuse of prog %s in sec %s with type %u: attach_btf_id %u != kern_type_id %u
      libbpf: struct_ops init_kern %s func ptr %s: invalid reuse of prog %s in sec %s with type %u: expected_attach_type %u != kern_member_idx %u
    libbpf: struct_ops init_kern %s: func ptr %s is set to prog %s from data(+%u) to kern_data(+%u)
        libbpf: struct_ops init_kern %s: Error in size of member %s: %zd != %zd(kernel)
        libbpf: struct_ops init_kern %s: copy %s %u bytes from data(+%u) to kern_data(+%u)
     libbpf: struct_ops init: DATASEC %s not found
  libbpf: struct_ops init: Cannot resolve var type_id %u in DATASEC %s
   libbpf: struct_ops init: anonymous type is not supported
       libbpf: struct_ops init: %s is not a struct
 .struct_ops.link   libbpf: struct_ops init: var %s is beyond the end of DATASEC %s
        libbpf: struct_ops init: struct %s(type_id=%u) %s found at offset %u
   libbpf: alloc memory failed for %s
     libbpf: elf: init internal error
       libbpf: elf: failed to open %s: %s
     libbpf: elf: failed to open %s as ELF file: %s
 libbpf: elf: '%s' is not a proper ELF object
   libbpf: elf: '%s' is not a 64-bit ELF object
   libbpf: elf: failed to get ELF header from %s: %s
      libbpf: elf: '%s' has unknown byte order
       libbpf: elf: failed to get section names section index for %s: %s
      libbpf: elf: failed to get section names strings from %s: %s
   libbpf: elf: %s is not a valid eBPF object file
        libbpf: invalid license section in %s
 libbpf: license of %s is %s
     libbpf: invalid kver section in %s
     libbpf: kernel version of %s is %x
     libbpf: failed to get sym name string for var %s
 libbpf-placeholder-fd %.*s%.*s        libbpf: map '%s' (global data): at sec_idx %d, offset %zu, flags %x.
   libbpf: failed to alloc map '%s' content buffer: %s
 libbpf: map %td is "%s"
   libbpf: extern (kcfg) '%s': value '%c' implies tristate or char type
   libbpf: extern (kcfg) '%s': value '%c' implies bool, tristate, or char type
    libbpf: extern (kcfg) '%s': value '%s' implies char array type
 libbpf: extern (kcfg) '%s': invalid string config '%s'
 libbpf: extern (kcfg) '%s': long string '%s' of (%zu bytes) truncated to %d bytes
      libbpf: failed to parse '%s': %s
       libbpf: failed to parse '%s' as integer completely
     libbpf: extern (kcfg) '%s': value '%llu' implies integer, char, or boolean type
        libbpf: extern (kcfg) '%s': value '%llu' isn't boolean compatible
      libbpf: extern (kcfg) '%s': value '%llu' doesn't fit in %d bytes
 CONFIG_       libbpf: failed to parse '%s': no separator
     libbpf: failed to parse '%s': no value
 libbpf: extern (kcfg) '%s': value '%s' isn't a valid integer
   libbpf: extern (kcfg) '%s': value '%s' implies integer type
    libbpf: extern (kcfg) '%s': set to %s
 /boot/config-%s re /proc/config.gz       libbpf: failed to open system Kconfig
  libbpf: error parsing system Kconfig line '%s': %s
 r   libbpf: failed to open in-memory Kconfig: %s
   libbpf: error parsing in-memory Kconfig line '%s': %s
 .kconfig void int ptr struct union enum fwd typedef volatile const restrict func func_proto var datasec float decl_tag type_tag enum64 unknown   libbpf: map '%s': attr '%s': expected PTR, got %s.
     libbpf: map '%s': attr '%s': type [%u] not found.
      libbpf: map '%s': attr '%s': expected ARRAY, got %s.
   libbpf: map '%s': attr '%s': expected ENUM or ENUM64, got %s.
  libbpf: map '%s': attr '%s': invalid __ulong
 %s/%s /sys/fs/bpf libbpf: map '%s': invalid field #%d.
 type max_entries map_flags numa_node key_size     libbpf: map '%s': conflicting key size %u != %u.
 key   libbpf: map '%s': key type [%d] not found.
     libbpf: map '%s': key spec is not PTR: %s.
     libbpf: map '%s': can't determine key size for type [%u]: %zd.
 libbpf: map '%s': conflicting key size %u != %zd.
 value_size   libbpf: map '%s': conflicting value size %u != %u.
 value       libbpf: map '%s': value type [%d] not found.
   libbpf: map '%s': value spec is not PTR: %s.
   libbpf: map '%s': can't determine value size for type [%u]: %zd.
       libbpf: map '%s': conflicting value size %u != %zd.
 values map-in-map inner prog-array value   libbpf: map '%s': multi-level inner maps not supported.
        libbpf: map '%s': '%s' member should be last.
  libbpf: map '%s': should be map-in-map or prog-array.
  libbpf: map '%s': conflicting value size %u != 4.
      libbpf: map '%s': %s type [%d] not found.
      libbpf: map '%s': %s spec is not a zero-sized array.
   libbpf: map '%s': %s def is of unexpected kind %s.
     libbpf: map '%s': prog-array value def is of unexpected kind %s.
       libbpf: map '%s': map-in-map inner def is of unexpected kind %s.
 %s.inner pinning      libbpf: map '%s': inner def can't be pinned.
   libbpf: map '%s': invalid pinning value %u.
 map_extra  libbpf: map '%s': unknown field '%s'.
  libbpf: map '%s': ignoring unknown field '%s'.
 libbpf: map '%s': map type isn't specified.
    libbpf: map '%s': found type = %u.
     libbpf: map '%s': found key [%u], sz = %u.
     libbpf: map '%s': found key_size = %u.
 libbpf: map '%s': found value [%u], sz = %u.
   libbpf: map '%s': found value_size = %u.
       libbpf: map '%s': found max_entries = %u.
      libbpf: map '%s': found map_flags = 0x%x.
      libbpf: map '%s': found map_extra = 0x%llx.
    libbpf: map '%s': found pinning = %u.
  libbpf: map '%s': found numa_node = %u.
        libbpf: map '%s': found inner map definition.
 static global extern libbpf: map #%d: empty name.
       libbpf: map '%s' BTF data is corrupted.
        libbpf: map '%s': unexpected var kind %s.
      libbpf: map '%s': unsupported map linkage %s.
  libbpf: map '%s': unexpected def kind %s.
      libbpf: map '%s': invalid def size.
    libbpf: map '%s': failed to alloc map name.
    libbpf: map '%s': at sec_idx %d, offset %zu.
   libbpf: map '%s': couldn't build pin path.
     libbpf: elf: sec '%s': declared ARENA map size (%zu) is too small to hold global __arena variables of size %zu
 .maps   libbpf: elf: failed to get %s map definitions for %s
   libbpf: DATASEC '%s' not found.
        libbpf: map '%s': only single ARENA map is supported (map '%s' is also ARENA)
 .addr_space.1    libbpf: elf: sec '%s': to use global __arena variables the ARENA map should be explicitly declared in SEC(".maps")
 enum64_placeholder .BTF     libbpf: Error loading ELF section %s: %s.
 .BTF.ext     libbpf: Ignore ELF section %s because its depending ELF section %s is not found.
       libbpf: Error loading ELF section %s: %s. Ignored and continue.
        libbpf: BTF is required, but is missing or corrupted.
  libbpf: No name found in string section for DATASEC kind.
 .ksyms       libbpf: sec '%s': failed to determine size from ELF: size %u, err %s
   libbpf: sec '%s': unexpected non-VAR type found
        libbpf: sec '%s': failed to find name of DATASEC's member #%d
  libbpf: sec '%s': failed to find ELF symbol for VAR '%s'
       libbpf: Error loading vmlinux BTF: %s
  libbpf: Kernel doesn't support BTF, skipping uploading it.
     libbpf: Error loading .BTF into kernel: %s. BTF is mandatory, can't proceed.
   libbpf: Error loading .BTF into kernel: %s. BTF is optional, ignoring.
 libbpf: elf: failed to get section name string at offset %zu from %s: %s
       libbpf: elf: failed to get section(%zu) from %s: %s
    libbpf: elf: failed to get section(%zu) header from %s: %s
     libbpf: elf: failed to get section(%zu) name from %s: %s
 <?>   libbpf: elf: failed to get section(%zu) %s data from %s: %s
 .debug_ .text .rel libbpf: elf: failed to get the number of sections for %s: %s
   libbpf: elf: multiple symbol tables in %s
      libbpf: elf: couldn't find symbol table in %s, stripped object file?
   libbpf: elf: section(%d) %s, size %ld, link %d, flags %lx, type=%d
 license version maps        libbpf: elf: legacy map definitions in 'maps' section are not supported by libbpf v1.0+
 .data .data. .rodata .rodata. .struct_ops ?.struct_ops ?.struct_ops.link .jumptables   libbpf: elf: skipping unrecognized data section(%d) %s
 .rel.struct_ops .rel.struct_ops.link .rel?.struct_ops .rel?.struct_ops.link .rel.maps   libbpf: elf: skipping relo section(%d) %s for section(%d) %s
 .bss .bss.        libbpf: elf: skipping section(%d) %s (size %zu)
        libbpf: elf: symbol strings section missing or invalid in %s
 libbpf_tristate dummy_ksym        libbpf: cannot create a dummy_ksym var
 libbpf: looking for externs among %d symbols...
        libbpf: failed to find BTF for extern '%s': %d
 libbpf: failed to find BTF for extern '%s' [%d] section: %d
    libbpf: extern function %s is unsupported under %s section
     libbpf: failed to resolve size of extern (kcfg) '%s': %d
       libbpf: failed to determine alignment of extern (kcfg) '%s': %d
        libbpf: extern (kcfg) '%s': type is unsupported
        libbpf: unrecognized extern section '%s'
       libbpf: collected %d externs total
     libbpf: extern (ksym) #%d: symbol %d, name %s
  libbpf: failed to find extern definition for BTF %s '%s'
       libbpf: extern (kcfg) #%d: symbol %d, off %u, name %s
  libbpf: failed to find extern definition for BTF var '%s'
      libbpf: prog '%s': invalid relo against '%s' for insns[%d].code 0x%x
   libbpf: prog '%s': extern relo failed to find extern for '%s' (%d)
     libbpf: prog '%s': found extern #%d '%s' (sym %d) for insn #%u
 libbpf: prog '%s': incorrect bpf_call opcode
   libbpf: prog '%s': bad call relo against '%s' in section '%s'
  libbpf: prog '%s': bad call relo against '%s' at offset %zu
    libbpf: prog '%s': invalid relo against '%s' in special section 0x%x; forgot to initialize global var?..
       libbpf: prog '%s': bad subprog addr relo against '%s' at offset %zu+%d
 libbpf: prog '%s': bad arena data relocation at insn %u, no arena maps defined
 libbpf: prog '%s': found arena map %d (%s, sec %d, off %zu) for insn %u
        libbpf: prog '%s': bad map relo against '%s' in section '%s'
   libbpf: prog '%s': found map %zd (%s, sec %d, off %zu) for insn #%u
    libbpf: prog '%s': map relo failed to find map for section '%s', off %zu
       libbpf: prog '%s': bad data relo against section '%s'
  libbpf: prog '%s': found data map %zd (%s, sec %d, off %zu) for insn %u
        libbpf: prog '%s': data relo failed to find map for section '%s'
       libbpf: sec '%s': collecting relocation for section(%zu) '%s'
  libbpf: sec '%s': failed to get relo #%d
       libbpf: sec '%s': symbol #%zu not found for relo #%d
   libbpf: sec '%s': corrupted symbol #%zu pointing to invalid section #%zu for relo #%d
  libbpf: sec '%s': invalid offset 0x%zx for relo #%d
 <? libbpf: sec '%s': relo #%d: insn #%u against '%s'
      libbpf: sec '%s': relo #%d: couldn't find program in section '%s' for insn #%u, probably overridden weak function, skipping...
 /proc/%d/fdinfo/%d      libbpf: failed to open %s: %s. No procfs support?
 map_type:	%u key_size:	%u value_size:	%u max_entries:	%u map_flags:	%i       libbpf: object '%s': token is prevented, skipping...
  , skipping optional step...      libbpf: object '%s': failed (%s) to open BPF FS mount at '%s'%s
        libbpf: object '%s': BPF FS at '%s' doesn't have BPF token delegation set up, skipping...
      libbpf: object '%s': failed (%d) to create BPF token from '%s'%s
       libbpf: Failed to bump RLIMIT_MEMLOCK (err = %s), you might need to do it explicitly!
 GPL      libbpf: Error in %s(): %s. Couldn't load trivial BPF program. Make sure your kernel supports BPF (CONFIG_BPF_SYSCALL=y) and/or that RLIMIT_MEMLOCK is set to big enough value.
 libbpf: failed to get map info for map FD %d: %s
       libbpf: found no pinned map to reuse at '%s'
   libbpf: couldn't retrieve pinned map '%s': %s
  libbpf: couldn't reuse pinned map at '%s': parameter mismatch
  libbpf: reused pinned map at '%s'
      libbpf: map '%s': failed to set initial contents: %s
   libbpf: map '%s': failed to freeze as read-only: %s
    libbpf: map '%s': failed to re-mmap() contents: %s
     libbpf: map '%s': failed to create inner map: %s
       libbpf: Error in bpf_create_map_xattr(%s): %s. Retrying without BTF.
   libbpf: map '%s': failed to initialize slot [%d] to map '%s' fd=%d: %s
 libbpf: map '%s': slot [%d] set to map '%s' fd=%d
      libbpf: map '%s': failed to initialize slot [%d] to prog '%s' fd=%d: %s
        libbpf: map '%s': slot [%d] set to prog '%s' fd=%d
     libbpf: map '%s': failed to determine number of system CPUs: %d
        libbpf: map '%s': setting size to %d
   libbpf: map '%s': skipped auto-creating...
     libbpf: map '%s': error reusing pinned map
     libbpf: map '%s': cannot find pinned map
       libbpf: map '%s': skipping creation (preset fd=%d)
     libbpf: map '%s': created successfully, fd=%d
  libbpf: map '%s': failed to mmap arena: %s
     libbpf: map '%s': failed to auto-pin at '%s': %s
       libbpf: map '%s': failed to create: %s
 libbpf: CO-RE relocating [%d] %s %s: found target candidate [%d] %s %s in [%s]
 libbpf: skipping module BTFs loading, missing privileges
       libbpf: failed to iterate BTF objects: %s
      libbpf: failed to get BTF object #%d FD: %s
    libbpf: failed to get BTF object #%d info: %s
 vmlinux  libbpf: failed to load module [%s]'s BTF object #%d: %s
        libbpf: prog '%s': relo #%d: target candidate search failed for [%d] %s %s: %ld
        libbpf: failed to parse target BTF: %s
 libbpf: sec '%s': found %d CO-RE relocations
   libbpf: sec '%s': skipping CO-RE relocation #%d for insn #%d belonging to eliminated weak subprogram
   libbpf: prog '%s': relo #%d: failed to record relocation: %s
   libbpf: prog '%s': relo #%d: failed to relocate: %s
    libbpf: prog '%s': relo #%d: failed to patch insn #%u: %s
      libbpf: prog '%s': relo #%d: poisoning insn #%d that loads map #%d '%s'
        libbpf: prog '%s': relo #%d: poisoning insn #%d that calls kfunc '%s'
  libbpf: map '.jumptables': jumptable start %u should be multiple of %u
 libbpf: map '.jumptables': jumptable size %d should be multiple of %u
  libbpf: map '.jumptables': ELF file is missing jump table data
 libbpf: map '.jumptables': jumptables_data size is %zd, trying to access %d
    libbpf: map '.jumptables': invalid instruction index %d
        libbpf: map '.jumptables': invalid jump table value 0x%llx at offset %u
        libbpf: prog '%s': relo #%d: bad insn
  libbpf: prog '%s': relo #%d: can't create jump table: sym_off %u
       libbpf: prog '%s': relo #%d: bad relo type %d
  libbpf: prog '%s': error relocating .BTF.ext function info: %s
 libbpf: prog '%s': missing .BTF.ext function info.
     libbpf: prog '%s': missing .BTF.ext function info for the main program, skipping all of .BTF.ext func info.
    libbpf: prog '%s': error relocating .BTF.ext line info: %s
     libbpf: prog '%s': missing .BTF.ext line info.
 libbpf: prog '%s': missing .BTF.ext line info for the main program, skipping all of .BTF.ext line info.
        libbpf: prog '%s': failed to realloc prog code
 libbpf: prog '%s': added %zu insns from sub-prog '%s'
  libbpf: prog '%s': failed to add subprog offsets: %s
   libbpf: prog '%s': unexpected relo for insn #%zu, type %d
      libbpf: prog '%s': missing subprog addr relo for insn #%zu
     libbpf: prog '%s': no .text section found yet sub-program call exists
  libbpf: prog '%s': insn #%zu relocated, imm %d points to subprog '%s' (now at %zu offset)
 exception_callback:  libbpf: prog '%s': exception_callback:<value> decl tag not applied to the main program
 libbpf: prog '%s': exception_callback:<value> decl tag contains empty value
    libbpf: prog '%s': exception callback %s must be a global non-hidden function
  libbpf: prog '%s': multiple subprogs with same name as exception callback '%s'
 libbpf: prog '%s': cannot find exception callback '%s'
 bpf_cgroup_dev_ctx __sk_buff bpf_sock bpf_sock_addr bpf_sockopt bpf_sysctl bpf_user_pt_regs_t bpf_nf_ctx bpf_perf_event_data bpf_raw_tracepoint_args bpf_sk_lookup sk_msg_md sk_reuseport_md bpf_sock_ops xdp_md <anon> pt_regs libbpf: prog '%s': subprog '%s' arg#%d is expected to be of `struct %s *` type
 arg:ctx libbpf: failed to perform CO-RE relocations: %s
        libbpf: prog '%s': failed to relocate calls: %s
        libbpf: prog '%s': failed to relocate data references: %s
      libbpf: prog '%s': failed to perform .BTF.ext fix ups: %s
      libbpf: .maps relo #%d: failed to get ELF relo
 libbpf: .maps relo #%d: symbol %zx not found
   libbpf: .maps relo #%d: for %zd value %zd rel->r_offset %zu name %d ('%s')
     libbpf: .maps relo #%d: cannot find map '%s' at rel->r_offset %zu
 map prog     libbpf: .maps relo #%d: '%s' isn't a BTF-defined map
   libbpf: .maps relo #%d: hash-of-maps '%s' should have key size %zu.
    libbpf: .maps relo #%d: '%s' isn't a valid map reference
       libbpf: .maps relo #%d: '%s' isn't a valid program reference
   libbpf: .maps relo #%d: '%s' isn't an entry-point program
      libbpf: .maps relo #%d: map '%s' slot [%d] points to %s '%s'
 libbpf: internal error at %d
     libbpf: prog '%s': no BTF-based attach target is specified, use bpf_program__set_attach_target()
       libbpf: prog '%s': missing BPF prog type, check ELF section name '%s'
  libbpf: prog '%s': SEC("struct_ops") program isn't referenced anywhere, did you forget to use it?
      libbpf: prog '%s': failed to prepare load attributes: %s
       libbpf: prog '%s': -- BEGIN PROG LOAD LOG --
%s-- END PROG LOAD LOG --
 libbpf: prog '%s': failed to bind map '%s': %s
 libbpf: prog '%s': BPF program load failed: %s
 %d: (%*d) call unknown#195896080
 ...   %d: <invalid CO-RE relocation>
failed to resolve CO-RE relocation %s%s
 %d: (%*d) call unknown#%d
      %d: <invalid BPF map reference>
BPF map '%s' is referenced but wasn't created
  %d: <invalid kfunc call>
kfunc '%s' is referenced but wasn't resolved
  invalid func unknown#195896080
 invalid func unknown#200100 invalid func unknown#2002   libbpf: prog '%s': skipped loading
     libbpf: prog '%s': failed to load: %s
  libbpf: prog '%s': unrecognized ELF section name '%s'
  libbpf: prog '%s': failed to initialize: %s
 (mem buf)  libbpf: failed to init libelf for %s
 bpf_object_open_opts      libbpf: loading object '%s' from buffer
        libbpf: loading object from %s
 LIBBPF_BPF_TOKEN_PATH %lx-%zx /proc/kallsyms    libbpf: failed to open /proc/kallsyms: %s
 %llx %c %499s%*[^
]
 libbpf: failed to read kallsyms entry: %d
 .llvm.       libbpf: extern (ksym) '%s': resolution is ambiguous: 0x%llx or 0x%llx
  libbpf: extern (ksym) '%s': set to 0x%llx
      libbpf: extern (var ksym) '%s': not found in kernel BTF
        libbpf: extern (var ksym) '%s': incompatible types, expected [%d] %s %s, but kernel has [%d] %s %s
     libbpf: extern (var ksym) '%s': resolved to [%d] %s %s
 libbpf: extern (func ksym) '%s': not found in kernel or module BTFs
    libbpf: extern (func ksym) '%s': func_proto [%d] incompatible with %s [%d]
     libbpf: extern (func ksym) '%s': module BTF fd index %d too big to fit in bpf_insn offset
      libbpf: extern (func ksym) '%s': resolved to %s [%d]
 LINUX_KERNEL_VERSION      libbpf: extern (kcfg) '%s': failed to get kernel version
 LINUX_HAS_BPF_COOKIE LINUX_HAS_SYSCALL_WRAPPER LINUX_ libbpf: extern (kcfg) '%s': unrecognized virtual extern
        libbpf: extern (kcfg) '%s': set to 0x%llx
      libbpf: extern '%s': unrecognized extern kind
  libbpf: extern '%s' (strong): not resolved
     libbpf: extern '%s' (weak): not resolved, defaulting to zero
   libbpf: object '%s': prepare loading can't be attempted twice
  libbpf: object '%s': load can't be attempted twice
     libbpf: object '%s': loading non-native endianness is unsupported
      libbpf: failed to load object '%s'
     libbpf: failed to mkdir %s: %s
 libbpf: failed to statfs %s: %s
        libbpf: specified path %s is not on BPF FS
     libbpf: prog '%s': can't pin program that wasn't loaded
        libbpf: prog '%s': failed to pin at '%s': %s
   libbpf: prog '%s': pinned at '%s'
      libbpf: prog '%s': can't unpin program that wasn't loaded
      libbpf: prog '%s': unpinned from '%s'
 libbpf: invalid map pointer
     libbpf: map '%s': can't pin BPF map without FD (was it created?)
       libbpf: map '%s' already has pin path '%s' different from '%s'
 libbpf: map '%s' already pinned at '%s'; not re-pinning
        libbpf: missing a path to pin map '%s' at
      libbpf: map '%s' already pinned
 libbpf: pinned map '%s'
       libbpf: failed to pin map: %s
  libbpf: no path to unpin map '%s' from
 libbpf: unpinned map '%s' from '%s'
    libbpf: object not yet loaded; load it first
 gen_loader_opts   libbpf: error: program handler doesn't match object
 socket sk_reuseport/migrate kprobe+ uprobe+ uprobe.s+ kretprobe+ uretprobe+ uretprobe.s+ kprobe.multi+ kretprobe.multi+ kprobe.session+ uprobe.multi+ uretprobe.multi+ uprobe.session+ uprobe.multi.s+ uretprobe.multi.s+ uprobe.session.s+ ksyscall+ kretsyscall+ usdt+ usdt.s+ tc/ingress tc/egress tcx/ingress tcx/egress tc classifier action netkit/primary netkit/peer tracepoint+ tp+ raw_tracepoint+ raw_tp+ raw_tracepoint.w+ raw_tp.w+ tp_btf+ fentry+ fmod_ret+ fexit+ fentry.s+ fmod_ret.s+ fexit.s+ fsession+ fsession.s+ freplace+ lsm+ lsm.s+ lsm_cgroup+ iter+ iter.s+ xdp.frags/devmap xdp/devmap xdp.frags/cpumap xdp/cpumap xdp.frags sockops sk_skb/stream_parser sk_skb/stream_verdict sk_skb/verdict cgroup_skb/ingress cgroup_skb/egress cgroup/skb cgroup/sock_create cgroup/sock_release cgroup/sock cgroup/post_bind4 cgroup/post_bind6 cgroup/bind4 cgroup/bind6 cgroup/connect4 cgroup/connect6 cgroup/connect_unix cgroup/sendmsg4 cgroup/sendmsg6 cgroup/sendmsg_unix cgroup/recvmsg4 cgroup/recvmsg6 cgroup/recvmsg_unix cgroup/getpeername4 cgroup/getpeername6 cgroup/getpeername_unix cgroup/getsockname4 cgroup/getsockname6 cgroup/getsockname_unix cgroup/sysctl cgroup/getsockopt cgroup/setsockopt cgroup/dev struct_ops+ struct_ops.s+ libbpf_prog_handler_opts    libbpf: failed to guess program type from ELF section '%s'
     libbpf: supported section(type) names are:%s
   libbpf: struct_ops reloc: failed to get %d reloc
       libbpf: struct_ops reloc: symbol %zx not found
 libbpf: struct_ops reloc: cannot find map at rel->r_offset %zu
 libbpf: struct_ops reloc %s: for %lld value %lld shdr_idx %u rel->r_offset %zu map->sec_offset %zu name %d ('%s')
      libbpf: struct_ops reloc %s: rel->r_offset %zu shdr_idx %u unsupported non-static function
     libbpf: struct_ops reloc %s: invalid target program offset %llu
        libbpf: struct_ops reloc %s: cannot find member at moff %u
     libbpf: struct_ops reloc %s: cannot relocate non func ptr %s
   libbpf: struct_ops reloc %s: cannot find prog at shdr_idx %u to relocate func ptr %s
   libbpf: struct_ops reloc %s: prog %s is not struct_ops BPF program
 btf_trace_ bpf_lsm_ bpf_iter_       libbpf: vmlinux BTF is not found
       libbpf: %s is not found in vmlinux BTF
 libbpf: failed bpf_prog_get_info_by_fd for FD %d: %s
   libbpf: The target program doesn't have BTF
    libbpf: Failed to get BTF %d of the program: %s
        libbpf: %s is not found in prog's BTF
  libbpf: prog '%s': attach program FD is not set
        libbpf: prog '%s': failed to find BPF program (FD %d) BTF ID for '%s': %s
      libbpf: prog '%s': failed to find kernel BTF type ID of '%s': %s
       libbpf: failed to guess attach type based on ELF section name '%s'
     libbpf: attachable section(type) names are:%s
  libbpf: map '%s': cannot be resized, map value type is not a datasec
   libbpf: map '%s': cannot be resized, map value datasec is empty
        libbpf: map '%s': cannot be resized, last var must be an array
 libbpf: map '%s': cannot be resized, element size (%d) doesn't align with new total size (%u)
  libbpf: map '%s': failed to resize memory-mapped region: %s
    libbpf: map '%s': failed to adjust resized BTF, clearing BTF key/value info: %s
        libbpf: error: unsupported map type
    libbpf: error: inner_map_fd already specified
  libbpf: exclusive programs must be set before map creation
     libbpf: excl_prog and map must be from the same bpf object
     libbpf: error in %s: map handler doesn't belong to object
      libbpf: map '%s': unexpected key size %zu provided, expected %u
        libbpf: map '%s': can't use BPF map without FD (was it created?)
       libbpf: map '%s': BPF_F_CPU and BPF_F_ALL_CPUS are mutually exclusive
  libbpf: map '%s': unexpected value size %zu provided for either BPF_F_CPU or BPF_F_ALL_CPUS, expected %u
       libbpf: map '%s': unexpected value size %zu provided for per-CPU map, expected %d * %zu = %zd
  libbpf: map '%s': unexpected value size %zu provided, expected %u
      libbpf: prog '%s': can't use BPF program without FD (was it loaded?)
   libbpf: failed to open link at %s: %d
  libbpf: link fd=%d: pinned at %s
       libbpf: link fd=%d: unpinned from %s
 bpf_perf_event_opts       libbpf: prog '%s': invalid perf event FD %d
    libbpf: prog '%s': can't attach BPF program without FD (was it loaded?)
        libbpf: prog '%s': failed to create BPF link for perf_event FD %d: %s
  libbpf: prog '%s': user context value is not supported
 libbpf: prog '%s': failed to attach to perf_event FD %d: %s
    libbpf: prog '%s': try add PERF_SAMPLE_CALLCHAIN to or remove exclude_callchain_[kernel|user] from pfd %d
      libbpf: prog '%s': failed to enable perf_event FD %d: %s
       libbpf: failed to open '%s': %s
        /sys/bus/event_source/devices/kprobe/type %d
   /sys/bus/event_source/devices/uprobe/type       /sys/bus/event_source/devices/kprobe/format/retprobe config:%d
 /sys/bus/event_source/devices/uprobe/format/retprobe uprobe     libbpf: failed to determine %s perf type: %s
   libbpf: failed to determine %s retprobe bit: %s
 /sys/kernel/debug/tracing /sys/kernel/tracing  /sys/kernel/debug/tracing/kprobe_events /sys/kernel/tracing/kprobe_events       /sys/kernel/debug/tracing/uprobe_events /sys/kernel/tracing/uprobe_events       /sys/kernel/debug/tracing/available_filter_functions    /sys/kernel/tracing/available_filter_functions  /sys/kernel/debug/tracing/available_filter_functions_addrs      /sys/kernel/tracing/available_filter_functions_addrs libbpf_%u_%d_%s_0x%zx kretprobes kprobes %c:%s/%s %s+0x%zx -:%s/%s %s/events/%s/%s/id      libbpf: failed to add legacy kprobe event for '%s+0x%zx': %s
   libbpf: failed to determine legacy kprobe event id for '%s+0x%zx': %s
  libbpf: legacy kprobe perf_event_open() failed: %s
 x64 __%s_sys_bpf bpf_kprobe_opts kretprobe  libbpf: prog '%s': failed to create %s '%s+0x%zx' perf event: %s
       libbpf: prog '%s': failed to attach to %s '%s+0x%zx': %s
 bpf_ksyscall_opts __%s_sys_%s __se_sys_%s     libbpf: failed to open %s: %s
 %499s%*[^
]
     libbpf: failed to parse available_filter_functions entry: %d
 %llx %499s%*[^
]
 libbpf: failed to parse available_filter_functions_addrs entry: %d
 bpf_kprobe_multi_opts       libbpf: prog '%s': failed to find a unique match for '%s' (%zu matches)
        libbpf: prog '%s': failed to attach: %s
 kretprobe/ %m[a-zA-Z0-9_.]+%li libbpf: kprobe name is invalid: %s
     libbpf: kretprobes do not support offset specification
 ksyscall kretsyscall kretsyscall/ kprobe.multi kretprobe.multi kretprobe.multi/ %m[a-zA-Z0-9_.*?]       libbpf: kprobe multi pattern is invalid: %s
 kprobe.session     libbpf: kprobe session pattern is invalid: %s
 %m[^/]/%m[^:]:%m[^
] uprobe.session uretprobe.multi      libbpf: prog '%s': invalid format of section definition '%s'
 uretprobes uprobes %c:%s/%s %s:0x%zx      libbpf: failed to add legacy uprobe event for %s:0x%zx: %s
     libbpf: failed to determine legacy uprobe event id for %s:0x%zx: %s
    libbpf: legacy uprobe perf_event_open() failed: %s
     libbpf: zip: failed to open %s: %ld
    libbpf: zip: could not find archive member %s in %s: %ld
       libbpf: zip: found entry for %s in %s at 0x%lx
 libbpf: zip: entry %s of %s is compressed and cannot be handled
        libbpf: elf: could not read elf file %s from %s: %s
    libbpf: elf: symbol address match for %s of %s in %s: 0x%x + 0x%lx = 0x%lx
 /lib/x86_64-linux-gnu .so .so. LD_LIBRARY_PATH /usr/lib64:/usr/lib PATH /usr/bin:/usr/sbin %.*s/%s  libbpf: resolved '%s' to '%s'
 bpf_uprobe_multi_opts    libbpf: prog '%s': failed to resolve full path for '%s': %s
    libbpf: prog '%s': failed to attach multi-uprobe: %s
 bpf_uprobe_opts !/ uretprobe      libbpf: prog '%s': failed to create %s '%s:0x%zx' perf event: %s
       libbpf: prog '%s': failed to attach to %s '%s:0x%zx': %s
       libbpf: prog '%s': section '%s' missing ':function[+offset]' specification
 +%li%n uretprobe.s  libbpf: prog '%s': uretprobes do not support offset specification
 usdt usdt/%m[^:]:%m[^:]:%m[^:]       libbpf: invalid section '%s', expected SEC("usdt/<path>:<provider>:<name>")
    libbpf: tracepoint %s/%s path is too long
      libbpf: failed to determine tracepoint '%s/%s' perf event ID: %s
       libbpf: tracepoint '%s/%s' perf_event_open() failed: %s
 bpf_tracepoint_opts    libbpf: prog '%s': failed to create tracepoint '%s/%s' perf event: %s
  libbpf: prog '%s': failed to attach to tracepoint '%s/%s': %s
 tp tp/ bpf_raw_tracepoint_opts   libbpf: prog '%s': can't attach before loaded
  libbpf: prog '%s': failed to attach to raw tracepoint '%s': %s
 libbpf: prog '%s': invalid section name '%s'
 bpf_trace_opts    libbpf: prog '%s': failed to attach to %s: %s
 bpf_cgroup_opts  libbpf: prog '%s': relative_fd and relative_id cannot be set at the same time
 bpf_tcx_opts     libbpf: prog '%s': target netdevice ifindex cannot be zero
 bpf_netkit_opts     libbpf: prog '%s': supply none or both of target_fd and attach_func_name
       libbpf: prog '%s': only BPF_PROG_TYPE_EXT can attach as freplace
 freplace bpf_iter_attach_opts libbpf: prog '%s': failed to attach to iterator: %s
 bpf_netfilter_opts libbpf: prog '%s': failed to attach to netfilter: %s
   libbpf: map '%s': can't attach non-struct_ops map
      libbpf: map '%s': can't attach BPF map without FD (was it created?)
    libbpf: failed to munmap cpu_buf #%d
   libbpf: failed to open perf buffer event on cpu #%d: %s
        libbpf: failed to mmap perf buffer on cpu #%d: %s
      libbpf: failed to enable perf buffer event on cpu #%d: %s
 perf_buffer_opts perf_buffer_raw_opts        /sys/devices/system/cpu/online  libbpf: page count should be power of two, but is %zu
  libbpf: failed to get map info for FD %d; API not supported? Ignoring...
       libbpf: map '%s' should be BPF_MAP_TYPE_PERF_EVENT_ARRAY
       libbpf: failed to create epoll instance: %s
    libbpf: failed to allocate events: out of memory
       libbpf: failed to allocate buffers: out of memory
      libbpf: failed to get online CPU mask: %s
      libbpf: failed to set cpu #%d, key %d -> perf FD %d: %s
        libbpf: failed to epoll_ctl cpu #%d perf FD %d: %s
     libbpf: unknown perf sample type %d
    libbpf: error while processing records: %s
     libbpf: perf_buffer: failed to process records in buffer #%d: %s
       libbpf: prog '%s': can't associate BPF program without FD (was it loaded?)
     libbpf: prog '%s': can't associate struct_ops program
  libbpf: map '%s': can't associate BPF map without FD (was it created?)
 libbpf: map '%s': can't associate non-struct_ops map
 %d%n-%d%n libbpf: Failed to get CPU range %s: %d
 libbpf: Invalid CPU range [%d,%d] in %s
 libbpf: Empty CPU range
       libbpf: Failed to open cpu mask file %s: %s
    libbpf: Failed to read cpu mask from %s: %s
    libbpf: CPU mask is too big in file %s
 libbpf: failed to find skeleton map '%s'
       libbpf: failed to find skeleton program '%s'
   libbpf: failed to initialize skeleton BPF object '%s': %s
      libbpf: failed to populate skeleton maps for '%s': %s
  libbpf: failed to populate skeleton progs for '%s': %s
 libbpf: subskeletons require BTF at runtime (object %s)
        libbpf: failed to populate subskeleton maps: %s
        libbpf: type for map '%1$s' is not a datasec: %2$s
     libbpf: failed to load BPF skeleton '%s': %s
   libbpf: prog '%s': failed to auto-attach: %s
   libbpf: map '%s': BPF skeleton version is old, skipping map auto-attachment...
 libbpf: map '%s': BPF map skeleton link is uninitialized
       libbpf: map '%s': failed to auto-attach: %s
            bpf_object__probe_loading       __bpf_map__iter raw_tp raw_tp.w raw_tracepoint.w        /sys/devices/system/cpu/possible              @      0Alibbpf: %s size (%zu) is too small
     libbpf: %s has non-zero extra bytes
    libbpf: failed to dup FD %d to FD > 2: %d
 GPL bpf_map_create_opts bpf_prog_load_opts bpf_map_batch_opts bpf_obj_pin_opts bpf_obj_get_opts bpf_prog_attach_opts bpf_prog_detach_opts bpf_link_create_opts bpf_link_update_opts bpf_prog_query_opts bpf_test_run_opts bpf_get_fd_by_id_opts bpf_raw_tp_opts bpf_btf_load_opts bpf_prog_bind_opts bpf_token_create_opts bpf_prog_stream_read_opts bpf_prog_assoc_struct_ops_opts  libbpf: Attribute of type %#x found multiple times in message, previous attribute is being ignored.
    libbpf: Failed to parse extended error attributes
      libbpf: Kernel error message: %s
       libbpf: %s size (%zu) is too small
     libbpf: %s has non-zero extra bytes
 libbpf: BTF header not found
      libbpf: Can't load BTF with non-native endianness due to unsupported header length %u
  libbpf: Invalid BTF magic: %x
  libbpf: BTF header len %u larger than data size %u
     libbpf: Invalid BTF total size: %u
     libbpf: Invalid BTF data sections layout: type data at %u + %u, strings data at %u + %u
        libbpf: BTF type section is not aligned to 4 bytes
     libbpf: Invalid BTF string section
     libbpf: Malformed BTF string section, did you forget to provide base BTF?
      libbpf: Unsupported BTF_KIND:%u
        libbpf: BTF type [%d] is malformed
     libbpf: BTF types data is malformed
    libbpf: btf: type [%u]: invalid %s (string offset %u)
  libbpf: btf: type [%u]: invalid referenced type ID %u
 type name field name enum name   libbpf: btf: type [%u]: referenced type [%u] is not FUNC_PROTO
 param name      libbpf: btf: type [%u]: unrecognized kind %u
   libbpf: unsupported BTF_KIND:%u
 void   libbpf: failed to get EHDR from %s
     libbpf: failed to get section names section index for %s
       libbpf: failed to get e_shstrndx from %s
       libbpf: failed to get section(%d) header from %s
       libbpf: failed to get section(%d) name from %s
 .BTF .BTF.ext .BTF.base libbpf: unexpected section type (%d) of section(%d, %s) from %s
        libbpf: failed to get section(%d, %s) data from %s
     libbpf: failed to init libelf for %s
   libbpf: failed to open %s: %s
  libbpf: failed to open %s as ELF file
  libbpf: failed to find '%s' ELF section in %s
  libbpf: failed to get ELF class (bitness) for %s
 rbe   libbpf: BTF loading error: %s
  libbpf: -- BEGIN BTF LOAD LOG ---
%s
-- END BTF LOAD LOG --
    libbpf: .BTF.ext %s section is not aligned to 4 bytes
  libbpf: %s section (off:%u len:%u) is beyond the end of the ELF section .BTF.ext
       libbpf: .BTF.ext %s record size not found
      libbpf: %s section in .BTF.ext has invalid record size %u
      libbpf: %s section in .BTF.ext has no records
  libbpf: %s section header is not found in .BTF.ext
     libbpf: %s section has incorrect num_records in .BTF.ext
 func_info line_info core_relo libbpf: BTF.ext header too short
       libbpf: Invalid BTF.ext magic:%x
       libbpf: Unsupported BTF.ext version:%u
 libbpf: Unsupported BTF.ext flags:%x
   libbpf: BTF.ext header not found
 libbpf: BTF.ext has no data
  libbpf: BTF.ext header missing func_info, line_info
 btf_dedup_opts     libbpf: btf_dedup_new failed: %ld
      libbpf: btf_dedup_prep failed: %s
      libbpf: btf_dedup_strings failed: %s
   libbpf: btf_dedup_prim_types failed: %s
        libbpf: btf_dedup_struct_types failed: %s
      libbpf: btf_dedup_resolve_fwds failed: %s
      libbpf: btf_dedup_ref_types failed: %s
 libbpf: btf_dedup_compact_types failed: %s
     libbpf: btf_dedup_remap_types failed: %s
       libbpf: unknown kind %d for type [%d]
  libbpf: Reached depth limit for identical type comparison for '%s'/'%s'
 STRUCT UNION   libbpf: %s '%s' size=%d vlen=%d id1[%u] id2[%u] shallow-equal but not identical for field#%d '%s'
      libbpf: %s '%s' size=%d vlen=%d cand_id[%u] canon_id[%u] shallow-equal but not equiv for field#%d '%s': %d
 /sys/kernel/btf/vmlinux /boot/vmlinux-%1$s  /lib/modules/%1$s/vmlinux-%1$s  /lib/modules/%1$s/build/vmlinux /usr/lib/modules/%1$s/kernel/vmlinux    /usr/lib/debug/boot/vmlinux-%1$s        /usr/lib/debug/boot/vmlinux-%1$s.debug  /usr/lib/debug/lib/modules/%1$s/vmlinux libbpf: kernel BTF is missing at '%s', was CONFIG_DEBUG_INFO_BTF enabled?
      libbpf: failed to read kernel BTF from '%s': %s
        libbpf: loaded kernel BTF from '%s'
    libbpf: loading kernel BTF '%s': %s
    libbpf: failed to find valid kernel BTF
 /sys/kernel/btf/%s     libbpf: unexpected reference to base type[%u] of kind [%u] when creating distilled base BTF.
   libbpf: unexpected kind when adding base type '%s'[%u] of kind [%u] to distilled base BTF.
 btf_permute_opts long long int int long unsigned long long unsigned unsigned long int unsigned int long long unsigned int long int unsigned int unsigned long int long unsigned     Something wrong in libelf BPF object format invalid     'version' section incorrect or lost Endian mismatch Internal error in libbpf Relocation failed  Kernel verifier blocks program loading Program too big Incorrect kernel version Kernel doesn't support this program type Wrong pid in netlink message Invalid netlink sequence  Incorrect netlink message parsing %s Unknown libbpf error %d -E2BIG -EACCES -EADDRINUSE -EADDRNOTAVAIL -EAGAIN -EALREADY -EBADF -EBADFD -EBUSY -ECANCELED -ECHILD -EDEADLK -EDOM -EEXIST -EFAULT -EFBIG -EILSEQ -EINPROGRESS -EINTR -EINVAL -EIO -EISDIR -ELOOP -EMFILE -EMLINK -EMSGSIZE -ENAMETOOLONG -ENFILE -ENODATA -ENODEV -ENOENT -ENOEXEC -ENOLINK -ENOMEM -ENOSPC -ENOTBLK -ENOTDIR -ENOTSUPP -ENOTTY -ENXIO -EOPNOTSUPP -EOVERFLOW -EPERM -EPIPE -EPROTO -EPROTONOSUPPORT -ERANGE -EROFS -ESPIPE -ESRCH -ETXTBSY -EUCLEAN -EXDEV %d           /BD7q۵[V9Y?^[1$}Ut]rހܛtiGƝ̡$o,-tJܩ\ڈvRQ>m1'YGQcg))
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e
jv.,r迢KfpK£Ql$օ5pjl7LwH'49JNOʜ[o.htocxxȄǌlPxqlibbpf: %s size (%zu) is too small
     libbpf: %s has non-zero extra bytes
    libbpf: Netlink error reporting not supported
  libbpf: Invalid message or trailing data in Netlink response: %d bytes left
 bpf_xdp_attach_opts bpf_xdp_query_opts netdev clsact bpf_tc_hook %s:[%u] bpf_tc_opts bpf   /proc/version_signature re %*s %*s %u.%u.%u
 Debian  Debian %u.%u.%u %u.%u.%u   attach_btf_id 1 is not a function       Cannot replace kernel functions GPL invalid func  unknown func  program of this type cannot use helper  libbpf: %s size (%zu) is too small
     libbpf: %s has non-zero extra bytes
    													          btf_dump_opts   libbpf: unsatisfiable type cycle, id:[%u]
 __builtin_va_list    libbpf: anonymous struct/union loop, id:[%u]
 ;

 long int short char 
%s%s: %d;    struct union %s%s%s %s%s%s { 
%s : %d ; 
 %s} }  __attribute__((packed)) __Poly8_t unsigned char __Poly16_t unsigned short __Poly64_t unsigned long long __Poly128_t unsigned __int128 typedef %s %s;

 enum %s 
%s%s___%zd = %d, 
%s%s___%zd = %u, 
%s%s = %d, 
%s%s = %u, 
%s%s___%zd = %lldLL, 
%s%s___%zd = %lluULL, 
%s%s = %lldLL, 
%s%s = %lluULL, enum%s%s  { 
%s}  __attribute__((mode(byte)))  __attribute__((mode(word))) union %s struct %s __gnuc_va_list      typedef __builtin_va_list __gnuc_va_list typedef  btf_dump_emit_type_decl_opts  libbpf: not enough memory for decl stack: %s
   libbpf: unexpected type in decl chain, kind:%u, id:[%u]
 volatile  const  restrict  %s%s void %s *  *  volatile  const  restrict  __attribute__((%s))    __attribute__((btf_type_tag("%s"))) [%u] ( )  ( void) ,  ... %s___%zu , <unsupported kind:%u>  libbpf: unexpected bitfield size %d
 0x%llx%s%s libbpf: unexpected size %d for id [%u]
 0x%llx%016llx%s%s %lld%s%s %llu%s%s %d%s%s %u%s%s '\0'%s%s '%c'%s%s     libbpf: unexpected sz %d for id [%u]
 %Lf%s%s %lf%s%s %f%s%s static  extern   %s =  " %c \x%02x libbpf: unexpected elem size %zd for array type [%u]
 [%s ]%s%s {%s }%s%s %p%s%s 0x%x%s%s       libbpf: unexpected size %d for enum, id:[%u]
 %d %lldLL %lluULL%s%s SEC("%s") %s%s      libbpf: unexpected size [%zu] for id [%u]
      libbpf: unexpected error skipping mods/typedefs for id [%u]
 .%s =      libbpf: unexpected kind [%u] for id [%u]
 btf_dump_type_data_opts       libbpf: %s size (%zu) is too small
     libbpf: %s has non-zero extra bytes
    libbpf: ringbuf: failed to get map info for fd=%d: %s
  libbpf: ringbuf: map fd=%d is not BPF_MAP_TYPE_RINGBUF
 libbpf: ringbuf: failed to mmap consumer page for map fd=%d: %s
        libbpf: ringbuf: failed to mmap data pages for map fd=%d: %s
   libbpf: ringbuf: failed to epoll add map fd=%d: %s
 ring_buffer_opts    libbpf: ringbuf: failed to create epoll instance: %s
   libbpf: user ringbuf: failed to get map info for fd=%d: %s
     libbpf: user ringbuf: map fd=%d is not BPF_MAP_TYPE_USER_RINGBUF
       libbpf: user ringbuf: failed to mmap consumer page for map fd=%d: %s
   libbpf: user ringbuf: failed to mmap data pages for map fd=%d: %s
      libbpf: user ringbuf: failed to epoll add map fd=%d: %s
 user_ring_buffer_opts  libbpf: user ringbuf: failed to create epoll instance: %s
      libbpf: %s size (%zu) is too small
     libbpf: %s has non-zero extra bytes
 bpf_linker_opts    libbpf: libelf initialization failed: %s
       libbpf: failed to create '%s': %d
 fd:%d        libbpf: failed to create ELF object: %s
        libbpf: failed to create ELF header: %s
  .strtab       libbpf: failed to create STRTAB section: %s
    libbpf: failed to create STRTAB data: %s
 .symtab       libbpf: failed to create SYMTAB section: %s
    libbpf: failed to create SYMTAB data: %s
 bpf_linker_file_opts  libbpf: failed to open file '%s': %s
 mem:%p+%zu        libbpf: failed to create memfd '%s': %s
        libbpf: failed to write '%s': %s
 .debug_ .text .rel .BTF .BTF.ext      libbpf: linker: adding object file '%s'...
     libbpf: failed to parse ELF file '%s': %s
      libbpf: failed to get ELF header for %s: %s
    libbpf: unknown byte order of ELF file %s
 big little   libbpf: linker: set %s-endian output byte order
        libbpf: byte order mismatch with ELF file %s
   libbpf: unsupported kind of ELF file %s: %s
    libbpf: failed to get SHSTRTAB section index for %s: %s
        libbpf: failed to get section #%zu header for %s: %s
   libbpf: failed to get section #%zu name for %s: %s
     libbpf: failed to get section #%zu (%s) data from %s: %s
       libbpf: multiple SYMTAB sections found, not supported
  libbpf: failed to parse .BTF from %s: %s
       libbpf: failed to parse .BTF.ext from '%s': %s
 libbpf: unrecognized section #%zu (%s) in %s
   libbpf: ELF is missing SYMTAB section in %s
    libbpf: ELF is missing section headers STRTAB section in %s
    libbpf: ELF section #%zu has empty name in %s
  libbpf: ELF section #%zu alignment %llu is non pow-of-2 alignment in %s
        libbpf: ELF section #%zu has inconsistent alignment addr=%llu != d=%llu in %s
  libbpf: ELF section #%zu has inconsistent section size sh=%llu != d=%llu in %s
 libbpf: ELF section #%zu has unexpected size alignment %llu in %s
      libbpf: ELF section #%zu (%s) has unrecognized type %zu in %s
  libbpf: ELF SYMTAB section #%zu points to missing STRTAB section #%zu in %s
    libbpf: ELF SYMTAB section #%zu points to invalid STRTAB section #%zu in %s
    libbpf: ELF sym #0 is invalid in %s
    libbpf: ELF sym #%d in section #%zu has unsupported symbol binding %d
  libbpf: ELF sym #%d in section #%zu has unsupported symbol visibility %d
       libbpf: ELF sym #%d is invalid extern symbol in %s
     libbpf: ELF sym #%d in section #%zu points to missing section #%zu in %s
       libbpf: ELF relo section #%zu points to invalid SYMTAB section #%zu in %s
      libbpf: ELF relo section #%zu points to missing section #%zu in %s
     libbpf: ELF relo section #%zu name has invalid name in %s
      libbpf: ELF relo section #%zu points to invalid section #%zu in %s
     libbpf: ELF relo #%d in section #%zu has unexpected type %zu in %s
     libbpf: ELF relo #%d in section #%zu points to invalid symbol #%zu in %s
       libbpf: ELF relo #%d in section #%zu points to missing symbol #%zu in %s
       libbpf: sec %s types mismatch
  libbpf: sec %s flags mismatch
  libbpf: sec %s entsize mismatch
        libbpf: failed to init section '%s'
    libbpf: ELF sections %s are incompatible
 license version       libbpf: non-identical contents of section '%s' are not supported
       libbpf: can't fetch symbol name for symbol #%d in '%s'
 libbpf: global '%s': incompatible forward declaration names '%s' and '%s'
 union struct libbpf: global '%s': incompatible %s forward declaration and concrete kind %s
  libbpf: global '%s': incompatible BTF kinds %s and %s
  libbpf: global '%s': incompatible %s names '%s' and '%s'
       libbpf: global '%s': incompatible %s '%s' size %u and %u
       libbpf: global '%s': incompatible func '%s' linkage
    libbpf: global '%s': incompatible var '%s' linkage
     libbpf: global '%s': incompatible number of %s fields %u and %u
        libbpf: global '%s': incompatible field #%d names '%s' and '%s'
        libbpf: global '%s': incompatible field #%d ('%s') offsets
     libbpf: global '%s': incompatible number of %s params %u and %u
        libbpf: global '%s': unsupported BTF kind %s
 type key_size key type value_size value type max_entries map_flags numa_node pinning inner map %s.inner   libbpf: global '%s': map %s mismatch
   libbpf: global '%s': invalid map definition type [%d]
  libbpf: global '%s': invalid map definition
    libbpf: global '%s': invalid dst map definition
        libbpf: BTF info is missing for global symbol '%s'
     libbpf: only extern variables and functions are supported, but got '%s' for '%s'
 .maps libbpf: failed to find BTF info for object '%s'
        libbpf: global/extern '%s' BTF is ambiguous: both types #%d and #%u match
      libbpf: failed to find BTF info for global/extern symbol '%s'
  libbpf: externs without BTF info are not supported
 .jumptables .extern libbpf: failed to find matching ELF sec '%s'
   libbpf: conflicting non-weak symbol #%d (%s) definition in '%s'
        libbpf: sections %s are not compatible
 libbpf: relocation against STT_SECTION in non-exec section is not supported!
   libbpf: failed to find symbol for variable '%s' in section '%s'
        libbpf: failed to append BTF type #%d from file '%s'
   libbpf: failed to find new ID mapping for original BTF type ID %u
      libbpf: global '%s': section mismatch %d vs %d
 libbpf: global '%s': failed to resolve size of underlying type: %d
     libbpf: can't find section '%s' referenced from .BTF.ext
       libbpf: incompatible .BTF.ext record sizes for section '%s'
    libbpf: failed to finalize ELF layout: %s
      libbpf: failed to write ELF contents: %s
       libbpf: failed to add consolidated BTF type for datasec '%s': %d
       libbpf: .BTF.ext generation failed: %s
 libbpf: BTF dedup failed: %s
   libbpf: failed to write out .BTF ELF section: %s
       libbpf: failed to write out .BTF.ext ELF section: %s
   libbpf: mismatch in func_info record size %zu != %u
    libbpf: mismatch in line_info record size %zu != %u
    libbpf: mismatch in core_relo_info record size %zu != %u
       libbpf: failed to parse final .BTF.ext data: %s
        libbpf: Total maps exceeds %d
 close(%%d) = %%d libbpf: nr_progs %d/%d nr_maps %d/%d mismatch
 libbpf: gen: finish %s
  libbpf: gen: load_btf: off %d size %d, attr: off %d size %d
 btf_load size %d   libbpf: gen: map_create: %s idx %d type %d value_type_id %d, attr: off %d size %d
      map_create %s idx %d type %d value_size %d value_btf_id %d %s%s libbpf: gen: find_attach_tgt %s %d
 find_by_name_kind(%s,%d) kallsyms_lookup_name(%s,%d)        libbpf: BTF fd off %d for kfunc %s exceeds INT16_MAX, cannot process relocation
         func (%s:count=%d): imm: %%d, off: %%d  func (%s:count=%d): btf_fd      var t=%d w=%d (%s:count=%d): imm[0]: %%d, imm[1]: %%d   var t=%d w=%d (%s:count=%d): insn.reg ld64 call        libbpf: gen: emit_relo (%d): %s at %d %s
       libbpf: gen: prog_load: prog_idx %d type %d insn off %d insns_cnt %zd license off %d
   libbpf: gen: prog_load: func_info: off %d cnt %d rec size %d
   libbpf: gen: prog_load: line_info: off %d cnt %d rec size %d
   libbpf: gen: prog_load: core_relos: off %d cnt %d rec size %zd
 libbpf: gen: prog_load: attr: off %d size %d
 prog_load %s insn_cnt %d  libbpf: gen: map_update_elem: idx %d, value: off %d size %d, attr: off %d size %d
      update_elem idx %d value_size %d        libbpf: gen: populate_outer_map: outer %d key %d inner %d, attr: off %d size %d
        populate_outer_map outer %d key %d inner %d     libbpf: gen: map_freeze: idx %d, attr: off %d size %d
 map_freeze       byte_off byte_sz field_exists signed lshift_u64 rshift_u64 local_type_id target_type_id type_exists type_matches type_size enumval_exists enumval_value unknown libbpf: unexpected kind %s relocated, local [%d], target [%d]
 0 %d%n   libbpf: prog '%s': relo for [%u] %s (at idx %d) captures type [%d] of unexpected kind %s
       libbpf: prog '%s': relo %d at insn #%d can't be applied to array access
        libbpf: prog '%s': relo %d at insn #%d can't be satisfied for bitfield
 libbpf: prog '%s': relo #%d: unrecognized CO-RE relocation %s (%d) at insn #%d
 libbpf: prog '%s': relo #%d: substituting insn #%d w/ invalid insn
     libbpf: prog '%s': relo #%d: unexpected insn #%d (ALU/ALU64) value: got %u, exp %llu -> %llu
   libbpf: prog '%s': relo #%d: patched insn #%d (ALU/ALU64) imm %llu -> %llu
     libbpf: prog '%s': relo #%d: unexpected insn #%d (LDX/ST/STX) value: got %u, exp %llu -> %llu
  libbpf: prog '%s': relo #%d: insn #%d (LDX/ST/STX) value too big: %llu
 libbpf: prog '%s': relo #%d: insn #%d (LDX/ST/STX) accesses field incorrectly. Make sure you are accessing pointers, unsigned integers, or fields of matching type and size.
   libbpf: prog '%s': relo #%d: patched insn #%d (LDX/ST/STX) off %llu -> %llu
    libbpf: prog '%s': relo #%d: insn #%d (LDX/ST/STX) unexpected mem size: got %d, exp %u
 libbpf: prog '%s': relo #%d: insn #%d (LDX/ST/STX) invalid new mem size: %u
    libbpf: prog '%s': relo #%d: patched insn #%d (LDX/ST/STX) mem_sz %u -> %u
     libbpf: prog '%s': relo #%d: insn #%d (LDIMM64) has unexpected form
    libbpf: prog '%s': relo #%d: unexpected insn #%d (LDIMM64) value: got %llu, exp %llu -> %llu
   libbpf: prog '%s': relo #%d: patched insn #%d (LDIMM64) imm64 %llu -> %llu
     libbpf: prog '%s': relo #%d: trying to relocate unrecognized insn #%d, code:0x%x, src:0x%x, dst:0x%x, off:0x%x, imm:0x%x
 <anon> <%s> [%u] %s %s ::%s = %d ::%s = %u ::%s = %lld ::%s = %llu .%s [%u]  (  : %s%d  @ offset %u.%u)  @ offset %u) <?>     libbpf: prog '%s': relo #%d: parsing [%d] %s %s + %s failed: %d
        libbpf: prog '%s': relo #%d: %s
        libbpf: prog '%s': relo #%d: <%s> (%d) relocation doesn't support anonymous types
      libbpf: prog '%s': relo #%d: error matching candidate #%d %s: %d
 non-matching matching libbpf: prog '%s': relo #%d: %s candidate #%d %s
       libbpf: prog '%s': relo #%d: field offset ambiguity: %u != %u
 failure success  libbpf: prog '%s': relo #%d: relocation decision ambiguity: %s %llu != %s %llu
 libbpf: prog '%s': relo #%d: no matching targets found
 __bpf_usdt_specs __bpf_usdt_ip_to_spec_id       libbpf: usdt: failed to find USDT support BPF maps, did you forget to include bpf/usdt.bpf.h?
  libbpf: usdt: unrecognized ELF kind %d for '%s'
        libbpf: usdt: attaching to 32-bit ELF binary '%s' is not supported
     libbpf: usdt: unsupported ELF class for '%s'
   libbpf: usdt: unsupported type of ELF binary '%s' (%d), only ET_EXEC and ET_DYN are supported
  libbpf: usdt: ELF endianness mismatch for '%s'
 libbpf: usdt: discovered PHDR #%d in '%s': vaddr 0x%lx memsz 0x%lx offset 0x%lx type 0x%lx flags 0x%lx
 libbpf: usdt: failed to find PT_LOAD program headers in '%s'
 /proc/%d/root%s   libbpf: usdt: failed to get absolute path of '%s' (err %s), using path as is...
 /proc/%d/maps re       libbpf: usdt: failed to open '%s' to get base addr of '%s': %s
 libbpf: usdt: discovered segment for lib '%s': addrs %zx-%zx mode %s offset %zx
 %zx-%zx %s %zx %*s %*d%[^
]
   libbpf: usdt: failed to find '%s' (resolved to '%s') within PID %d memory mappings
 .note.stapsdt       libbpf: usdt: no USDT notes section (%s) found in '%s'
 libbpf: usdt: invalid USDT notes section (%s) in '%s'
  libbpf: usdt: failed to process ELF program segments for '%s': %s
 .stapsdt.base        libbpf: usdt: failed to find ELF program segment for '%s:%s' in '%s' at IP 0x%lx
       libbpf: usdt: matched ELF binary '%s' segment [0x%lx, 0x%lx) for '%s:%s' at IP 0x%lx is not executable
 libbpf: usdt: attaching to shared libraries without specific PID is not supported on current kernel
    libbpf: usdt: failed to get memory segments in PID %d for shared library '%s': %s
      libbpf: usdt: failed to find shared lib memory segment for '%s:%s' in '%s' at relative IP 0x%lx
 exec lib       libbpf: usdt: probe for '%s:%s' in %s '%s': addr 0x%lx base 0x%lx (resolved abs_ip 0x%lx rel_ip 0x%lx) args '%s' in segment [0x%lx, 0x%lx) at offset 0x%lx
     libbpf: usdt: kernel doesn't support USDT semaphore refcounting for '%s:%s' in '%s'
    libbpf: usdt: failed to find ELF loadable segment with semaphore of '%s:%s' in '%s' at 0x%lx
   libbpf: usdt: matched ELF binary '%s' segment [0x%lx, 0x%lx] for semaphore of '%s:%s' at 0x%lx is executable
   libbpf: usdt: sema  for '%s:%s' in %s '%s': addr 0x%lx base 0x%lx (resolved 0x%lx) in segment [0x%lx, 0x%lx] at offset 0x%lx
   libbpf: usdt: failed to set USDT spec #%d for '%s:%s' in '%s': %s
      libbpf: usdt: IP collision detected for spec #%d for '%s:%s' in '%s'
   libbpf: usdt: failed to map IP 0x%lx to spec #%d for '%s:%s' in '%s': %s
       libbpf: usdt: failed to attach uprobe #%d for '%s:%s' in '%s': %s
      libbpf: usdt: failed to attach uprobe multi for '%s:%s' in '%s': %s
 stapsdt    libbpf: usdt: too many USDT arguments (> %d) for '%s:%s' with args spec '%s'
   libbpf: usdt: unsupported arg #%d (spec '%s') size: %d
 libbpf: usdt: unrecognized register '%s'
        %d @ %ld ( %%%15[^,] , %%%15[^,] , %d ) %n      %d @ ( %%%15[^,] , %%%15[^,] , %d ) %n  %d @ %ld ( %%%15[^,] , %%%15[^)] ) %n   %d @ ( %%%15[^,] , %%%15[^)] ) %n      libbpf: usdt: invalid SIB scale %d, expected 1, 2, 4, 8
  %d @ %ld ( %%%15[^)] ) %n  %d @ ( %%%15[^)] ) %n  %d @ %%%15s %n  %d @ $%ld %n        libbpf: usdt: unrecognized arg #%d spec '%s'
   /sys/bus/event_source/devices/uprobe/format/ref_ctr_offset rip eip rax eax ax al rbx ebx bx bl rcx ecx cx cl rdx edx dx dl rsi esi si sil rdi edi di dil rbp ebp bp bpl rsp esp sp spl r8 r8d r8w r8b r9 r9d r9w r9b r10 r10d r10w r10b r11 r11d r11w r11b r12 r12d r12w r12b r13 r13d r13w r13b r14 r14d r14w r14b r15 r15d r15w r15b  libbpf: elf: failed to init libelf for %s
      libbpf: elf: failed to open %s: %s
     libbpf: elf: could not read elf from %s: %s
    libbpf: elf: failed to get ehdr from %s: %s
    libbpf: elf: failed to find symbol table ELF sections in '%s'
  libbpf: elf: failed to get symbols for symtab section in '%s': %s
      libbpf: elf: failed to get verdef ELF section in '%s'
  libbpf: elf: ambiguous match for '%s', '%s' in '%s'
    libbpf: elf: symbol address match for '%s' in '%s': 0x%lx
      should not be 0 in a shared library     try using shared library path instead   libbpf: elf: '%s' is 0 in symtab for '%s': %s
  libbpf: elf: failed to find symbol '%s' in '%s'
        libbpf: elf: ambiguous match found '%s@%lu' in '%s' previous offset %lu
                GPL libbpf_nametest libbpf_global       libbpf: Error in %s(): %s. Couldn't create simple array map.
 libbpf_mmap libbpf_det_bind / det_arg_ctx arr global_reloc        libbpf: Error in %s(): Program loading unexpectedly succeeded.
 direct value offset of  invalid access to map value pointer     libbpf: Error in %s(): Program unexpectedly failed with message: %s.
 BPF program name global variables minimal BTF BTF functions BTF data section and variable BTF global function ARRAY map mmap()    BPF_PROG_LOAD expected_attach_type attribute    bpf_probe_read_kernel() helper BPF_PROG_BIND_MAP support module BTF support BTF_KIND_FLOAT support BPF perf link support BTF_KIND_DECL_TAG support BTF_KIND_TYPE_TAG support memcg-based memory accounting BPF cookie support BTF_KIND_ENUM64 support Kernel using syscall wrapper BPF multi-uprobe link support kernel-side __arg_ctx tag      BTF DATASEC names starting from '?' full range LDIMM64 support  libbpf: Detection of kernel %s support failed: %s
              probe_kern_global_data  int      int x a         int x a         x .data         x ?.data  float  tag  tag      probe_prog_bind_map  int         enum64  a b arg:ctx            probe_ldimm64_full_range_off    libbpf: base BTF id [%d] maps to invalid distilled base BTF id [%d]
    libbpf: distilled base BTF type '%s' [%u], size %u has multiple candidates of the same size (ids [%u, %u]) in base BTF
 libbpf: distilled base BTF type '%s' [%d] is not mapped to base BTF id
 libbpf: type [%d], kind [%d] is invalid for distilled base BTF; it is anonymous
        libbpf: type [%d] in distilled based BTF has unexpected kind [%d]
      libbpf: string '%s' [offset %u] is not mapped to base BTF
                              `````g```jxjHjjij kuvuuuuuvlulululululululululuu                            t t       j    Ll   ϑ             e    U +et0                                                                                                                                              t=NȈȈȈȈȈȈȈȈȈȈȈȈȈVȈȈ6ȈȈȈȈ?ȈȈȈȈȈȈȈȈwȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈ\ȈEȈ8+Ȉӏ؋ȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈȈ````````````ą`ą``ۋ`@````````````````````````3````݊Њ`x_ąNR``````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````````ąl5l'000000006000M0000000000000                            ' ''@&@&&@&@&@&@&@&@&@&@&@&@&@&@&@&@&@&@&@&@&@&@&@&@&@&@&@&@&p&@&&****%%)%%%%%%%%%%%%%%%%%%%%%%%%%%(%)1x2x2x2x2x21x2x2x2k3x2x2x2x2x2x2x2x2x2x2x2x2x2:x2x2x2x2x2x2x2x2x2x2x2x2x2x2x2x2x2x2x2R:2222222222x2x2x2x2x23x2x2x2x2x2x29x2x2x2x2x2v@x2x2x2w<x2x2;x2x2;x2x2x2x2x2x2x2x2x2x2;x2x2;x2Z2x23:x29x2k3x2x2x219g9P9x2x2x2x2x2:         q/ESC         Quit 
 B             Branch counter abbr list (Optional)
                        h/?/F1        Show this window
UP/DOWN/PGUP
PGDN/SPACE    Navigate
q/ESC/CTRL+C  Exit browser or go back to previous screen

For multiple event sessions:

TAB/UNTAB     Switch events

For symbolic views (--sort has sym):

ENTER         Zoom into DSO/Threads & Annotate current symbol
ESC           Zoom out
+             Expand/Collapse one callchain level
a             Annotate current symbol
C             Collapse all callchains
d             Zoom into current DSO
e             Expand/Collapse main entry callchains
E             Expand all callchains
F             Toggle percentage of filtered entries
H             Display column headers
k             Zoom into the kernel map
L             Change percent limit
m             Display context menu
S             Zoom into current Processor Socket
P             Print histograms to perf.hist.N
t             Zoom into current Thread
V             Verbose (DSO names in callchains, etc)
z             Toggle zeroing of samples
f             Enable/Disable events
/             Filter symbol by name   h/?/F1        Show this window
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PGDN/SPACE    Navigate
q/ESC/CTRL+C  Exit browser or go back to previous screen

For multiple event sessions:

TAB/UNTAB     Switch events

For symbolic views (--sort has sym):

ENTER         Zoom into DSO/Threads & Annotate current symbol
ESC           Zoom out
+             Expand/Collapse one callchain level
a             Annotate current symbol
C             Collapse all callchains
d             Zoom into current DSO
e             Expand/Collapse main entry callchains
E             Expand all callchains
F             Toggle percentage of filtered entries
H             Display column headers
k             Zoom into the kernel map
L             Change percent limit
m             Display context menu
S             Zoom into current Processor Socket
i             Show header information
P             Print histograms to perf.hist.N
r             Run available scripts
s             Switch to another data file in PWD
t             Zoom into current Thread
V             Verbose (DSO names in callchains, etc)
/             Filter symbol by name
0-9           Sort by event n in group             h/?/F1        Show this window
UP/DOWN/PGUP
PGDN/SPACE
LEFT/RIGHT    Navigate
q/ESC/CTRL+C  Exit browser                        read_addr2line_record           cmd_addr2line_configure cmd__addr2line          thread__get_arch                __symbol__inc_addr_samples  ԄĄ        add_config_item add_section     collect_config  (((((AAAAAABBBBBB                                0Pp`    symbol__disassemble                                                                             ++++++t+h+\+P+D+8+,+ +++***********x*l*`*T*H*<*0*$*** *)))+)))))))|)p)d)X)L)@)4)())+))(((((((((((t(h(\(P(D(8(,( ((('''''''''''x'l'`'T'H'<'0'$''' '&&&&&&&&&&|&p&d&X&L&@&4&(&&&&&%%%%%%%%)00///////////x/l/`/T/H/</0/$/// /..........|.p.d.X.L.@.4.(....-----------t-h-\-P-D-8-,- ---),,,,))))),,),,,,,x,l,`,T,H,<,0,$,,, ,+++++++)+++|+p+d+X+L+@+4+(++++***********w*n*e*\*S*J*A*8*/*&**H.|4p4d4X4L4@444(444433333333333t3h3\3P3D383,3 33322222222222x2l2`2H.H.H.T2H2<202$222H.H. 21111111111|1p1H.d1X1H.H.L1@141(111100000000000t0h0\0P0D0H.H.H.H.H.H.H.H.H.H.H.H.H.H.H.H.H.H.H.H.80,0 000///////////H.x/l/`/T/H/</0/$/// /....H.H.H.H.H.H..........v.m.T2p8d8X8L8@848(888877777777777t7h7\7P7D787,7 77766666666666x6l6`6T6H6T2T2<606$666 6T255555T2T25T25555|5p5d5T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2X5L5@545(555544444444444t4h4\4P4D484,4 44T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2T2433333333333x3l3`3T3H3<303$333 32T222T222T2222T22T22222y2:::::::::x:l:`:T:H:<:0:$::: :9999999999|9p9d9X9L9@949(9999:88888888888t8h8\8P8D888,8 88877777777777x7l7`7T7H7<707$777 76666666666|6p6d6X6L6@646(666655555555555t5h5\5P5D5;525)5 555544444d?X?L?@?4?(????>>>>>>>>>>>t>h>\>P>D>8>,> >>>=====d?======x=l=`=T=H=<=0=$=== =<<<<<<<<<<|<p<d<X<L<@<4<(<<<<;;;;;;;;;;;t;h;\;P;D;8;,; ;;;:::::::::::x:l:`:T:H:<:0:$::: :999999999999v9m9d9[9R9I99t44Tā܁DD<Tl$devlist__prepare_workload        @@p`
(	
,D0++,0+0+0+0+0+0+0+0+0+-+0+0+p-0+0+ +0+0+,0+X,0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+8,FFXF8FFEEEGC@GCxECCCCCCCXE                                                                     X8@  8¤Τڤ
ɣգ="+ѣ4cHdl$|,l999(HHxhxxxxxxxx8h00000000000000000000000000000000001000000000000000000000000000000000001h1h1h1h1 2h1h1h1h1h1h1h1h1h1h1h111@2h1h1h1h1h1h1h1h1h1h1h1h1h1h1h1h1h1 2832222(32222222222222322222222222222222340404040440404040404040404040404444040404040404040404040404040404040445858585855858585858585858585858555 685858585858585858585858585858585855H;8;8:(:::99999999x9h9X9H9::::x:h:X:H:::::;;(;999999999999989;;L<\<l<|<<<<<<,<<<;;;=??=?=???|?l?\?L?<?,???>>>>>>>>|>l>\>L><>,>>>====@`@xAhAXAHA8A(AAA@@@@@@@AAAAAAAA8B(BBBXBHBhBDDDDDDDxDhDXDHD8D(DDDCCCCCCCCxChCXCDDHC8C(C CHGKKxKhKXKHK8K(KKKJJJJJJJJxJhJXJHJ8J(JJJIHHHHHHHHxHhHXHHH8H(HHIxIhIXIHI8I(IIIIIIIIIKKLLLLLL|LlL\LLL<L,LLLK\MLM<M,MMMLLMM|MlMMMMNdN|PO|OlO\OLO<O,OOONNNNNNNPOOOOOOOLP<P,PPlP\PPXtXdXTXDX4X$XXXWWWWWWWWtWdWTWDW4W$WWUUUUUUUUVVVVtVtVdVdVTVTVDVDV4V4V$V$VVVVVVVVVVVVVWWVV܏܏܏܏܏܏܏܏܏܏܏܏܏܏܏܏܏܏܏܏܏܏܏܏܏܏܏܏܏܏܏܏܏܏܏܏܏܏܏܏܏See 'perf help COMMAND' for more information on a specific command.                             perf [--version] [--help] [OPTIONS] COMMAND [ARGS]              H p0  ((H            kgvVjlBDfuxbndGMKm  o                                                                            ED EDPDPDEEPDPDPDPDPDPDDDDD EDPD\C$C\C$CBBtCtCBBBBBB\A\A\A\A\C$C    symbol__new             symbols__fixup_end                                    	                           
                              perf_event__process_tracing_data        do_write_feat           write_tracing_data      write_build_id  write_auxtrace          build_mem_topology                                                                              7.0.12          get_tls_callchain_cursor    4lT            \\]]]\\ ^\\ ^@^X^p^\\ ]@]`]]\ ]        maps__set_modules_path_dir      machine__process_text_poke      pstack__push    pstack__remove  xH(  pP0@(`@dD$TT4ll$Dprefetch_event  24433      Y     Z [ 1 3 
r q s p  9  j        ] ^ 0  / 2 4 5 7 6  S 
      P , R . b  d   =     f                i       $      &h   	 %      >      " !    (                  e O * 	8  \ ; ) !" I  C E H u D F < ?  N A         %        } ~ { y x  z v w |     G    c `       g                  J   L + #  $ Q T  t M  k o m l n U W V   -  '  # a X : K _ @ B                            +       %  1 A } ~ P Z \  1    8  * FU     ! $ #    "; B<   ,-Q [ ] H K  9 I 9     J M     5O N  l k h s $ 4 y o '  n  >x v a b | 3 7  ` f     &    M       8@  > ^  V 	2          D?  S   E 	   
        G D F E     /#   0" *  % JKI   'G.67e   (H     Y   - +/   R <  T N       )   ;    :   =  B @ A  ( 3. ,     { z j t  & 4m  r w u q  p 6  i    C  0  !) 5   L  X 
 2 c g        d  L  _  ? W PO C   :   =                                     l! 3 |    ie -       = W
	x  jy   ) ? J I ? CH f  3 DRS ^ 2_  *7    ^     l  ,d v # ]   + 8 >   2  1  /  P  i p A   @ ` c    L M  om N      p  $#L%     6 e n "!u ] %    	 /k  5     k   wd& ' ( ) x Z  {  =} 8     [ U  "  T ;  m  V' P * K }~| 5  MzT[\, b 4   N{    Y U 1 X sQt & .a  (        O   `    _   bR   Yrq7 y     .  Q  J h Z9 a G      F  K B nO    D uC  0 AGI ~ w H gf h9E j  c   s W S 0$ :X t g ; BFE+  \   : <  4 z 
 -6V v>  @ o  q <r          iiud;Σ1|ǩ]YG:вf>uN 9q@N_N-  ԫcaaʭ#W޷/ǷkC                                                                                                                                                                                                                                                                                                                         4           '    +      *             ,  +  4 '      * ,                         $ $ $ $ $ $ $ B  B B                                                        - / 2 3  K O  W -   - K L q  O 3 W        2 / C   L q C C             ) N . 9 9 9 9 9 9 ) P . @ @ @ @ @ @ J R ^ U ) ) . M P . S N U  # # # # # # # F F F F F F F M Q S J R T [ ] \ S [ o p j t ^ Q \ j j o r v # & T u ] & & z v w p & r y & t u & w & z &   & 1 1 1 1 1 1 1 | y 1 1 {    1 1 1 1 1 1 : : : : : :  {  : : | {  } : : : : : : ; ;   }  ;   ; }  ;  ;   ;     ; = = = = = =    = =     = = = = = = G G G G G G   G G     G G G G G G I I     I   I   I  I     I    I X X     X   X   X  X    X  X   X Y Y Y Y Y Y    Y Y    Y Y Y Y Y Y                Y e e e e e e    e e     e e e e e e f f     f   f   f  f    f   f h h h h h h    h h    h h h h h h l l l l l l    l l     l l l l l l n n     n   n   n  n     n   }in ~ ~ ~ ~ ~ ~    ~ ~    ~ ~ ~ ~ ~ ~           W H                                 8         )            )7  &        &',* /9 ;0 7 _'*j >9:;       ,/>  E_j            :ET  +R^            ^K(  %T$F        FRGS `k u G KSkt `u~       t  ~                                    x  s g c a  ` _ Z V        H D <   7 6 0 (                	                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   		        	    	    	  	        	        	
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                                                                                                                                                        """"""      ""        """"""##        #    #    #  #        #        #------      --        ------......      ..        ......111111      11        11111122        2    2    2  2        2        2333333      33        333333555555      55        55555566        6    6    6  6        6        6<<<<<<      <<        <<<<<<======      ==        ======??????      ??        ??????@@        @    @    @  @        @        @AAAAAA      AA        AAAAAACCCCCC      CC        CCCCCCDD        D    D    D  D        D        DIIIIII      II        IIIIIIJJJJJJ      JJ        JJJJJJLLLLLL      LL        LLLLLLMM        M    M    M  M        M        MNNNNNN      NN        NNNNNNPPPPPP      PP        PPPPPPQQ        Q    Q    Q  Q        Q        QUUUUUU      UU        UUUUUUVVVVVV      VV        VVVVVVXXXXXX      XX        XXXXXXYY        Y    Y    Y  Y        Y        YZZZZZZ      ZZ        ZZZZZZ\\\\\\      \\        \\\\\\]]        ]    ]    ]  ]        ]        ]aaaaaa      aa        aaaaaabbbbbb      bb        bbbbbbcccccc      cc        ccccccdd        d    d    d  d        d        deeeeee      ee        eeeeeegggggg      gg        gggggghh        h    h    h  h        h        hllllll      ll        llllllmmmmmm      mm        mmmmmmnnnnnn      nn        nnnnnnoo        o    o    o  o        o        opppppp      pp        pppppprrrrrr      rr        rrrrrrss        s    s    s  s        s        svvvvvv      vv        vvvvvvwwwwww      ww        wwwwwwxxxxxx      xx        xxxxxx||||||      ||        ||||||                                                                                          
  
    
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  
    ! 
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
              """"""""""""""########--------------..............1111111111111122222222333333333333335555555555555566666666<<<<<<<<<<<<<<==============??????????????@@@@@@@@AAAAAAAAAAAAAACCCCCCCCCCCCCCDDDDDDDDIIIIIIIIIIIIIIJJJJJJJJJJJJJJLLLLLLLLLLLLLLMMMMMMMMNNNNNNNNNNNNNNPPPPPPPPPPPPPPQQQQQQQQUUUUUUUUUUUUUUVVVVVVVVVVVVVVXXXXXXXXXXXXXXYYYYYYYYZZZZZZZZZZZZZZ\\\\\\\\\\\\\\]]]]]]]]aaaaaaaaaaaaaabbbbbbbbbbbbbbccccccccccccccddddddddeeeeeeeeeeeeeegggggggggggggghhhhhhhhllllllllllllllmmmmmmmmmmmmmmnnnnnnnnnnnnnnoooooooopppppppppppppprrrrrrrrrrrrrrssssssssvvvvvvvvvvvvvvwwwwwwwwwwwwwwxxxxxxxxxxxxxxyyyyyyyyzzzzzzzzzzzzzz||||||||||||||}}}}}}}}            4 4 4 4 4 4 4 4 4 4 4 4 7 7 7 7 8 8 8 8 8 8 > > > > > > > > > > > > D D D D D D D H H H ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ a a a a a a a a a a a a c c c c c c c c c E E E E E E E                                    	                 & & 1 & & 1 Y Y 1 & 1 1 1 & 1 1 1 & 1 1 1 & 1 1 1 & 1 1 1 & 1 1 1 & 1 1 1 & 1 1 1 & 1 1 1 & 1 1 1 & 1 1 1 & 1 1 1 & 1 1 1 & 1 1 1 1 1             2 `    1 ?     D J   j  p   v   -3  = 7 J    P  ,    ep   ^                 C  	X  c)! *#/+>93UQmEM X        lFy  g!6  KVy  v  )41
)+Wl/  3,4Ei_kHXZ^w]'J  _jlt{|  9y(=R]  RPM;	  0;
^s  &\^L#.Q  fq<_8  		>a/	D	Y	d		  		~k				"
  7
B
lde
z

      
}pe;
  5(
q~

!'1<GQ\hpzPOKJI     ] 1 0 .      	





















             	
 !"#$%&'()*+,-./0123                  ? = < = 4 7 6 1 1 8 ; 3 4 4 9 : . > . , , . ( & " # $ $ = & & & & & & & & & & & & & &   >   4 1 4 3 4 0 + * ,   ) ( & & $ & ' & & & & & & & & & & & & &  & &       & &           5 2 3 4 0 - ) ( %   & & & & &  & & & & & & & & & &   & & & &     2 3 / 0 - ) % ' & & & & &  & & & & & 
 & & & & &   ! & &   2 3 0 - % & & & & & & & & & & & & & & & &   ! & & 2 3 0 - % & & & & & &  & & & & & & & &    ! & & 2 3 0 - % & & & & & &    	  & & & & & &    ! & & 2 3 0 - % & & & & & & & & & & & & &   ! & & 2 3 0 - % & & & & & & & &   & &    ! & & 2 3 0 - % &   & &  & &  &   ! &  2 3 0 - % & &  & & &   ! & 2 3 0 - % & & & &    ! & 2 3 0 - % & & & &   !  2 3 0 - % & & & &   ! 2 3 0 - % &  & &   ! 2 3 0 - % & & &   ! 2 3 0 - % & & &   ! 2 - % & & !  & ! & &      ،،،(،((((،(((((((((P@ЏpH `0  ( ،ȍܙܙܙܙܙ$D$ĜdD,ܙXȠȠ`ȠЯ( بܡЪXӫ>66>6vXؤGxHh                                          !!!!!""####$%&'((())*++,,---------..         	 !"#$%&'	*+,- 	!().
..(..+	+(
	,-,((((    			+		:	.		79$UV(D[
	
.'84 AB8R$$;"YC?$!Q	8"TGIJKL23O56KLMDP<EXZ@+W.\&'&(D(/S0:178=9HVU[F>#N 
,-%)*        .6 Y'!              %7  
77%774-05( * 7 "6  %   6   %$   '    	32+,1)/.!#&%% %   5>#4;E????<=@CAK7L#+N*1:OT#	P    	
p`0(    .IVIIzKKIHHII
I                                       
                                                   	 
                                                                                                                                             	
      	                                                `UpWWWW@W        	

         	  
      	                                     xȳ@            %                          %88@@@@@@@@@@@@@@@@@@@@@@@@@@xtrace   dso,symbol      dso,symbol                              local_weight,mem,sym,dso,symbol_daddr,dso_daddr,snoop,tlb,locked,blocked,local_ins_lat,local_p_stage_cyc                        comm,dso_from,symbol_from,symbol_to,cycles      ^sys_|^do_page_fault            init_cpunode_map                                70` X7X h  `  <{=1616161616&=|616|6K-1/////1-/                                                    //anon                                                                        P                    h`@8 h    hP0  hH|$4Ld                    U  ~W>>L $ b    }o Q {^D.	DDDD4T
Tl$
			        

























 





































@@





@@```






































      	      	   E   C           E   E    '@&@& '@&&'@&@&'ECEEEGGGGbGE,GGCEGzFEXFECEEEEEEEEEEEEEEHHGGGHGJ<MJJKJJmLJL1LJRKhHJJeKJLLhHJJJJJJJJJJJJJJ0ONNeNLN0OLO!NNMMOHNNNNNNLWR#OPPP{RRRRRPSS#O#OOTSPQQ#OPPPPPPPPPPPPPPdTUT<TTSdTRYYYlYNYYX,_\:a`hhaaanbb^c\_\w_\ctd`gzg\bfffgddd eehce\R``[[ \][[[[[[/^m^[[\o#m
mlloln`lJlk1mn%mqmlXm.mkqm3kLommum\mLog7onnnm7ohon`nmnons*ppoososEt-ttsssz:zNz-zzz<y<y~~~E}|@pzpzq 9,~˄FdpzpzՂ{{>b>{{>0w<ۊ{{{{{{{{0]A0r~A%Vɍ(((?((?(??(?HHH_HHЏ_H__HxvZx\,\$    intel_pt_calc_expected_tsc                                                                                                                                                                                                              P  P          P  P                                      P  P          P  P                                      0  0  0                                                                                                                                                                                                              P  P                                                                                                                           `                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 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                      `                                                                                                                      	          `                                                                                                                                            P                                              `                                            p   p   p   p   p   p   p   p                                                                                                               `  `  P                                                                     5X6556656intel_pt_synth_event            intel_pt_setup_time_ranges      intel_pt_process_auxtrace_info       B    B    B    B    B@    B     B  F   B    B &   B    B  :   B   z   B  :   B     B          B    B    B    B    B     B    B    B  F   B &   B     B   &   BP    B P :   B     B                 	   
                                                               intel_bts_synth_events          X0h@ <l$|,T`H                          @                                          A      A      A      pA      A      @A      A      A       A      PA      A      A       A      A      @A       N                  222t3T5344t45t3<T<T<T<<T<T<T<T<T<T<T<T<T<T<T<<T<T<T<<T<T<T<T<T<T<T<T<T<T<T<<@BBBqBaBXBAAADDD0D'D           s390_cpumsf_make_event          s390_cpumsf_run_decoder ȷ0HDtdDDDDDDT`P@ p0<\xh4TD$̹ܹ    {}si2	Zf                                                                      !    )  \ !  " "   ! # $ " $ ( % ) # % * $ & & # , % $ - . ( / 2 W 4 0 * 4 5 2 - 6 0 6 5 , / . 0 9 : < > ? : @ A ? > B D C E F 9 A @ C < F G H G H D E J K B L M K N L O Q R S J U X T X Y Z N V M O S T V [ Q R P U I = Y ; Z 8 7 3 1 + [ ^ ^ _ _ '     ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ]                      	 
                                    ! # " $ " & ( " ' ' " " " " " ' % * ! + " ) " , " " . ' ' - / % 0 # ' $ " 1 5 " 2 " " 3 " % " " % " " 4 " 2 " " 0 6 < " " 8 " " > = 7 : 9 % " " " " " @ " " C B " " " " " ? E D G A J " " K L H I " " F " " N " O " " " " M " " " Y " " Q " P R U V X " S T " W " " Z ; [ " " " ; " \       " " " ]  ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ]                 ]  ] ] ] ^ ] ] ] ] ] ] ] ] _ ] _ _ ] ] _ ] ] _ _ _ _ _ _ ] ^ _ _ ] _ _ _ _ _ _ _ _ _ _ _ _ _ _ ] _ _ _ _ _ _ _ _ _ ] _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _   ] ]                            )   ! $ " * #     / < = @ E B  : , ?  D G H J U  R  M Q T   \ ]  ^  _ ` b c f h g i j q r  w x z { }         L     .                           	
 !"#$%&'()*                                  
                      	                                                pppV !am  R|T                  !!!!!!!!!!!!!!!!!!!!!                       	
 !!  !!!!!!!!!!!!!!!!!                              
 !"	
 567;                                !"#$% !"*+,-./01234	&')
<=>?( 89: !";       !" !"    5 !"    6 !"    7 !"   @ !"   A !"   B !" !" !"                                                           
   	                                    
    ' (    % & .             C R a    9        p ~                             	
cond_broadcast  cond_signal     cond_wait       cond_destroy    __cond_init     mutex_trylock   mutex_unlock    mutex_lock      mutex_destroy   __mutex_init    populate_sdt_note               dso__load_sym_internal          read_gnu_debugdata      symsrc__init            filename__read_debuglink        sysfs__read_build_id            elf_read_build_id       read_build_id           dso__synthesize_plt_symbols 1 ``? X|\$$<                                                                                   	      
         	      
                                                                                                      	   
                                                                      B       m   l   e                                       	   
                                                                  @   A                                                       1   3   4   5   2   6   7      	   
                                                                                                                                                                                               	   )   *   +   (   ,   -                                                                                                                       |p3Q21p30//[ZZ[ZZ[[[[[[[[[[[[[[[[[[[[<ZT8xФT`````set_table_handlers              python_process_general_event    python_process_brstacksym       python_process_brstack          set_sample_datasrc_in_dict      get_sample_value_as_tuple       set_sample_read_in_dict         get_perf_sample_dict            get_field_numeric_entry         python_process_callchain        define_field    define_value    python_process_tracepoint       process_stat    stat__interval  python_process_stat_interval    handler_call_die        tuple_new   B
\\\\\d\\\\\\\\\\\$\\\\\\\\\\\\\\\\\\\\\tdTD44$4444tdT$$<4s7(0(&&&&&`'&&&&)&&&&&&&&&& )P24@13@13@1@1@1@1@1@1@1@12211P2:3                       '1˗\ȥsoO@/;jWePIiW
@ox?9B.?Uk@+eG?&{?-DT!	@m0_?kﴑ[?mBP?;f?;f?LXz?3Ey?w?T-@h?r1?]@;?[>I@>?n??5?׳?:??     @ `P0pH(hX8xD$dT4tL,l\<|B"bR2r
J*jZ:zF&fV6vN.n^>~A!aQ1q	I)iY9yE%eU5uM-m]=}C#cS3sK+k[;{G'gW7wO/o_?const llvm::DILineInfo& llvm::DIInliningInfo::getFrame(unsigned int) const      /usr/lib/llvm-21/include/llvm/DebugInfo/DIContext.h Index < Frames.size() <invalid> %s+0x%lx    const T& llvm::SmallVectorTemplateCommon<T, <template-parameter-1-2> >::operator[](size_type) const [with T = llvm::DILineInfo; <template-parameter-1-2> = void; const_reference = const llvm::DILineInfo&; size_type = long unsigned int]      /usr/lib/llvm-21/include/llvm/ADT/SmallVector.h idx < size() this->_M_is_engaged()      constexpr _Tp& std::optional<_Tp>::operator*() & [with _Tp = long unsigned int] /usr/include/c++/15/optional    llvm::Expected<T>::storage_type* llvm::Expected<T>::getStorage() [with T = llvm::DIInliningInfo; storage_type = llvm::DIInliningInfo]   /usr/lib/llvm-21/include/llvm/Support/Error.h   !HasError && "Cannot get value when an error exists!"   llvm::Expected<T>::error_type* llvm::Expected<T>::getErrorStorage() [with T = llvm::DIInliningInfo; error_type = std::unique_ptr<llvm::ErrorInfoBase>]  HasError && "Cannot get error when a value exists!"     llvm::Expected<T>::storage_type* llvm::Expected<T>::getStorage() [with T = llvm::DILineInfo; storage_type = llvm::DILineInfo]   llvm::Expected<T>::error_type* llvm::Expected<T>::getErrorStorage() [with T = llvm::DILineInfo; error_type = std::unique_ptr<llvm::ErrorInfoBase>]      llvm::Expected<T>::storage_type* llvm::Expected<T>::getStorage() [with T = llvm::DIGlobal; storage_type = llvm::DIGlobal]       llvm::Expected<T>::error_type* llvm::Expected<T>::getErrorStorage() [with T = llvm::DIGlobal; error_type = std::unique_ptr<llvm::ErrorInfoBase>]        jit_add_pid               perf_env__add_bpf_info          perf_event__synthesize_one_bpf_prog                             perf_event__synthesize_bpf_events                               get_bpf_prog_info_linear                     8   4   p   h   x   l                                        intel_pt_track_switches         intel_pt_find_snapshot          intel_bts_find_snapshot   =drm_                           default_core l1-dcache legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-dcache-load legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-dcache-load-refs legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-dcache-load-reference legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-dcache-load-ops legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-dcache-load-access legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-dcache-load-misses legacy cache Level 1 data cache read misses legacy-cache-config=0x10000  00     l1-dcache-load-miss legacy cache Level 1 data cache read misses legacy-cache-config=0x10000  10     l1-dcache-loads legacy cache Level 1 data cache read accesses legacy-cache-config=0  00     l1-dcache-loads-refs legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-dcache-loads-reference legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-dcache-loads-ops legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-dcache-loads-access legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-dcache-loads-misses legacy cache Level 1 data cache read misses legacy-cache-config=0x10000  10     l1-dcache-loads-miss legacy cache Level 1 data cache read misses legacy-cache-config=0x10000  10     l1-dcache-read legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-dcache-read-refs legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-dcache-read-reference legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-dcache-read-ops legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-dcache-read-access legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-dcache-read-misses legacy cache Level 1 data cache read misses legacy-cache-config=0x10000  10     l1-dcache-read-miss legacy cache Level 1 data cache read misses legacy-cache-config=0x10000  10     l1-dcache-store legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-dcache-store-refs legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-dcache-store-reference legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-dcache-store-ops legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-dcache-store-access legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-dcache-store-misses legacy cache Level 1 data cache write misses legacy-cache-config=0x10100  00     l1-dcache-store-miss legacy cache Level 1 data cache write misses legacy-cache-config=0x10100  10     l1-dcache-stores legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  00     l1-dcache-stores-refs legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-dcache-stores-reference legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-dcache-stores-ops legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-dcache-stores-access legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-dcache-stores-misses legacy cache Level 1 data cache write misses legacy-cache-config=0x10100  10     l1-dcache-stores-miss legacy cache Level 1 data cache write misses legacy-cache-config=0x10100  10     l1-dcache-write legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-dcache-write-refs legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-dcache-write-reference legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-dcache-write-ops legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-dcache-write-access legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-dcache-write-misses legacy cache Level 1 data cache write misses legacy-cache-config=0x10100  10     l1-dcache-write-miss legacy cache Level 1 data cache write misses legacy-cache-config=0x10100  10     l1-dcache-prefetch legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-dcache-prefetch-refs legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-dcache-prefetch-reference legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-dcache-prefetch-ops legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-dcache-prefetch-access legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-dcache-prefetch-misses legacy cache Level 1 data cache prefetch misses legacy-cache-config=0x10200  00     l1-dcache-prefetch-miss legacy cache Level 1 data cache prefetch misses legacy-cache-config=0x10200  10     l1-dcache-prefetches legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  00     l1-dcache-prefetches-refs legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-dcache-prefetches-reference legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-dcache-prefetches-ops legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-dcache-prefetches-access legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-dcache-prefetches-misses legacy cache Level 1 data cache prefetch misses legacy-cache-config=0x10200  10     l1-dcache-prefetches-miss legacy cache Level 1 data cache prefetch misses legacy-cache-config=0x10200  10     l1-dcache-speculative-read legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-dcache-speculative-read-refs legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-dcache-speculative-read-reference legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-dcache-speculative-read-ops legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-dcache-speculative-read-access legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-dcache-speculative-read-misses legacy cache Level 1 data cache prefetch misses legacy-cache-config=0x10200  10     l1-dcache-speculative-read-miss legacy cache Level 1 data cache prefetch misses legacy-cache-config=0x10200  10     l1-dcache-speculative-load legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-dcache-speculative-load-refs legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-dcache-speculative-load-reference legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-dcache-speculative-load-ops legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-dcache-speculative-load-access legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-dcache-speculative-load-misses legacy cache Level 1 data cache prefetch misses legacy-cache-config=0x10200  10     l1-dcache-speculative-load-miss legacy cache Level 1 data cache prefetch misses legacy-cache-config=0x10200  10     l1-dcache-refs legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-dcache-reference legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-dcache-ops legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-dcache-access legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-dcache-misses legacy cache Level 1 data cache read misses legacy-cache-config=0x10000  10     l1-dcache-miss legacy cache Level 1 data cache read misses legacy-cache-config=0x10000  10     l1-d legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-d-load legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-d-load-refs legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-d-load-reference legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-d-load-ops legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-d-load-access legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-d-load-misses legacy cache Level 1 data cache read misses legacy-cache-config=0x10000  10     l1-d-load-miss legacy cache Level 1 data cache read misses legacy-cache-config=0x10000  10     l1-d-loads legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-d-loads-refs legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-d-loads-reference legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-d-loads-ops legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-d-loads-access legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-d-loads-misses legacy cache Level 1 data cache read misses legacy-cache-config=0x10000  10     l1-d-loads-miss legacy cache Level 1 data cache read misses legacy-cache-config=0x10000  10     l1-d-read legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-d-read-refs legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-d-read-reference legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-d-read-ops legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-d-read-access legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-d-read-misses legacy cache Level 1 data cache read misses legacy-cache-config=0x10000  10     l1-d-read-miss legacy cache Level 1 data cache read misses legacy-cache-config=0x10000  10     l1-d-store legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-d-store-refs legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-d-store-reference legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-d-store-ops legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-d-store-access legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-d-store-misses legacy cache Level 1 data cache write misses legacy-cache-config=0x10100  10     l1-d-store-miss legacy cache Level 1 data cache write misses legacy-cache-config=0x10100  10     l1-d-stores legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-d-stores-refs legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-d-stores-reference legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-d-stores-ops legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-d-stores-access legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-d-stores-misses legacy cache Level 1 data cache write misses legacy-cache-config=0x10100  10     l1-d-stores-miss legacy cache Level 1 data cache write misses legacy-cache-config=0x10100  10     l1-d-write legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-d-write-refs legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-d-write-reference legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-d-write-ops legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-d-write-access legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-d-write-misses legacy cache Level 1 data cache write misses legacy-cache-config=0x10100  10     l1-d-write-miss legacy cache Level 1 data cache write misses legacy-cache-config=0x10100  10     l1-d-prefetch legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-d-prefetch-refs legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-d-prefetch-reference legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-d-prefetch-ops legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-d-prefetch-access legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-d-prefetch-misses legacy cache Level 1 data cache prefetch misses legacy-cache-config=0x10200  10     l1-d-prefetch-miss legacy cache Level 1 data cache prefetch misses legacy-cache-config=0x10200  10     l1-d-prefetches legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-d-prefetches-refs legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-d-prefetches-reference legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-d-prefetches-ops legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-d-prefetches-access legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-d-prefetches-misses legacy cache Level 1 data cache prefetch misses legacy-cache-config=0x10200  10     l1-d-prefetches-miss legacy cache Level 1 data cache prefetch misses legacy-cache-config=0x10200  10     l1-d-speculative-read legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-d-speculative-read-refs legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-d-speculative-read-reference legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-d-speculative-read-ops legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-d-speculative-read-access legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-d-speculative-read-misses legacy cache Level 1 data cache prefetch misses legacy-cache-config=0x10200  10     l1-d-speculative-read-miss legacy cache Level 1 data cache prefetch misses legacy-cache-config=0x10200  10     l1-d-speculative-load legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-d-speculative-load-refs legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-d-speculative-load-reference legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-d-speculative-load-ops legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-d-speculative-load-access legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-d-speculative-load-misses legacy cache Level 1 data cache prefetch misses legacy-cache-config=0x10200  10     l1-d-speculative-load-miss legacy cache Level 1 data cache prefetch misses legacy-cache-config=0x10200  10     l1-d-refs legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-d-reference legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-d-ops legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-d-access legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-d-misses legacy cache Level 1 data cache read misses legacy-cache-config=0x10000  10     l1-d-miss legacy cache Level 1 data cache read misses legacy-cache-config=0x10000  10     l1d legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1d-load legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1d-load-refs legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1d-load-reference legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1d-load-ops legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1d-load-access legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1d-load-misses legacy cache Level 1 data cache read misses legacy-cache-config=0x10000  10     l1d-load-miss legacy cache Level 1 data cache read misses legacy-cache-config=0x10000  10     l1d-loads legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1d-loads-refs legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1d-loads-reference legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1d-loads-ops legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1d-loads-access legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1d-loads-misses legacy cache Level 1 data cache read misses legacy-cache-config=0x10000  10     l1d-loads-miss legacy cache Level 1 data cache read misses legacy-cache-config=0x10000  10     l1d-read legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1d-read-refs legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1d-read-reference legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1d-read-ops legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1d-read-access legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1d-read-misses legacy cache Level 1 data cache read misses legacy-cache-config=0x10000  10     l1d-read-miss legacy cache Level 1 data cache read misses legacy-cache-config=0x10000  10     l1d-store legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1d-store-refs legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1d-store-reference legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1d-store-ops legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1d-store-access legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1d-store-misses legacy cache Level 1 data cache write misses legacy-cache-config=0x10100  10     l1d-store-miss legacy cache Level 1 data cache write misses legacy-cache-config=0x10100  10     l1d-stores legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1d-stores-refs legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1d-stores-reference legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1d-stores-ops legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1d-stores-access legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1d-stores-misses legacy cache Level 1 data cache write misses legacy-cache-config=0x10100  10     l1d-stores-miss legacy cache Level 1 data cache write misses legacy-cache-config=0x10100  10     l1d-write legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1d-write-refs legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1d-write-reference legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1d-write-ops legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1d-write-access legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1d-write-misses legacy cache Level 1 data cache write misses legacy-cache-config=0x10100  10     l1d-write-miss legacy cache Level 1 data cache write misses legacy-cache-config=0x10100  10     l1d-prefetch legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1d-prefetch-refs legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1d-prefetch-reference legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1d-prefetch-ops legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1d-prefetch-access legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1d-prefetch-misses legacy cache Level 1 data cache prefetch misses legacy-cache-config=0x10200  10     l1d-prefetch-miss legacy cache Level 1 data cache prefetch misses legacy-cache-config=0x10200  10     l1d-prefetches legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1d-prefetches-refs legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1d-prefetches-reference legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1d-prefetches-ops legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1d-prefetches-access legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1d-prefetches-misses legacy cache Level 1 data cache prefetch misses legacy-cache-config=0x10200  10     l1d-prefetches-miss legacy cache Level 1 data cache prefetch misses legacy-cache-config=0x10200  10     l1d-speculative-read legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1d-speculative-read-refs legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1d-speculative-read-reference legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1d-speculative-read-ops legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1d-speculative-read-access legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1d-speculative-read-misses legacy cache Level 1 data cache prefetch misses legacy-cache-config=0x10200  10     l1d-speculative-read-miss legacy cache Level 1 data cache prefetch misses legacy-cache-config=0x10200  10     l1d-speculative-load legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1d-speculative-load-refs legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1d-speculative-load-reference legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1d-speculative-load-ops legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1d-speculative-load-access legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1d-speculative-load-misses legacy cache Level 1 data cache prefetch misses legacy-cache-config=0x10200  10     l1d-speculative-load-miss legacy cache Level 1 data cache prefetch misses legacy-cache-config=0x10200  10     l1d-refs legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1d-reference legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1d-ops legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1d-access legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1d-misses legacy cache Level 1 data cache read misses legacy-cache-config=0x10000  10     l1d-miss legacy cache Level 1 data cache read misses legacy-cache-config=0x10000  10     l1-data legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-data-load legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-data-load-refs legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-data-load-reference legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-data-load-ops legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-data-load-access legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-data-load-misses legacy cache Level 1 data cache read misses legacy-cache-config=0x10000  10     l1-data-load-miss legacy cache Level 1 data cache read misses legacy-cache-config=0x10000  10     l1-data-loads legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-data-loads-refs legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-data-loads-reference legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-data-loads-ops legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-data-loads-access legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-data-loads-misses legacy cache Level 1 data cache read misses legacy-cache-config=0x10000  10     l1-data-loads-miss legacy cache Level 1 data cache read misses legacy-cache-config=0x10000  10     l1-data-read legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-data-read-refs legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-data-read-reference legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-data-read-ops legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-data-read-access legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-data-read-misses legacy cache Level 1 data cache read misses legacy-cache-config=0x10000  10     l1-data-read-miss legacy cache Level 1 data cache read misses legacy-cache-config=0x10000  10     l1-data-store legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-data-store-refs legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-data-store-reference legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-data-store-ops legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-data-store-access legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-data-store-misses legacy cache Level 1 data cache write misses legacy-cache-config=0x10100  10     l1-data-store-miss legacy cache Level 1 data cache write misses legacy-cache-config=0x10100  10     l1-data-stores legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-data-stores-refs legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-data-stores-reference legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-data-stores-ops legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-data-stores-access legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-data-stores-misses legacy cache Level 1 data cache write misses legacy-cache-config=0x10100  10     l1-data-stores-miss legacy cache Level 1 data cache write misses legacy-cache-config=0x10100  10     l1-data-write legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-data-write-refs legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-data-write-reference legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-data-write-ops legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-data-write-access legacy cache Level 1 data cache write accesses legacy-cache-config=0x100  10     l1-data-write-misses legacy cache Level 1 data cache write misses legacy-cache-config=0x10100  10     l1-data-write-miss legacy cache Level 1 data cache write misses legacy-cache-config=0x10100  10     l1-data-prefetch legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-data-prefetch-refs legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-data-prefetch-reference legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-data-prefetch-ops legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-data-prefetch-access legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-data-prefetch-misses legacy cache Level 1 data cache prefetch misses legacy-cache-config=0x10200  10     l1-data-prefetch-miss legacy cache Level 1 data cache prefetch misses legacy-cache-config=0x10200  10     l1-data-prefetches legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-data-prefetches-refs legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-data-prefetches-reference legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-data-prefetches-ops legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-data-prefetches-access legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-data-prefetches-misses legacy cache Level 1 data cache prefetch misses legacy-cache-config=0x10200  10     l1-data-prefetches-miss legacy cache Level 1 data cache prefetch misses legacy-cache-config=0x10200  10     l1-data-speculative-read legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-data-speculative-read-refs legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-data-speculative-read-reference legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-data-speculative-read-ops legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-data-speculative-read-access legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-data-speculative-read-misses legacy cache Level 1 data cache prefetch misses legacy-cache-config=0x10200  10     l1-data-speculative-read-miss legacy cache Level 1 data cache prefetch misses legacy-cache-config=0x10200  10     l1-data-speculative-load legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-data-speculative-load-refs legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-data-speculative-load-reference legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-data-speculative-load-ops legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-data-speculative-load-access legacy cache Level 1 data cache prefetch accesses legacy-cache-config=0x200  10     l1-data-speculative-load-misses legacy cache Level 1 data cache prefetch misses legacy-cache-config=0x10200  10     l1-data-speculative-load-miss legacy cache Level 1 data cache prefetch misses legacy-cache-config=0x10200  10     l1-data-refs legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-data-reference legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-data-ops legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-data-access legacy cache Level 1 data cache read accesses legacy-cache-config=0  10     l1-data-misses legacy cache Level 1 data cache read misses legacy-cache-config=0x10000  10     l1-data-miss legacy cache Level 1 data cache read misses legacy-cache-config=0x10000  10     l1-icache legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-icache-load legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-icache-load-refs legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-icache-load-reference legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-icache-load-ops legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-icache-load-access legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-icache-load-misses legacy cache Level 1 instruction cache read misses legacy-cache-config=0x10001  00     l1-icache-load-miss legacy cache Level 1 instruction cache read misses legacy-cache-config=0x10001  10     l1-icache-loads legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  00     l1-icache-loads-refs legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-icache-loads-reference legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-icache-loads-ops legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-icache-loads-access legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-icache-loads-misses legacy cache Level 1 instruction cache read misses legacy-cache-config=0x10001  10     l1-icache-loads-miss legacy cache Level 1 instruction cache read misses legacy-cache-config=0x10001  10     l1-icache-read legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-icache-read-refs legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-icache-read-reference legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-icache-read-ops legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-icache-read-access legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-icache-read-misses legacy cache Level 1 instruction cache read misses legacy-cache-config=0x10001  10     l1-icache-read-miss legacy cache Level 1 instruction cache read misses legacy-cache-config=0x10001  10     l1-icache-prefetch legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-icache-prefetch-refs legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-icache-prefetch-reference legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-icache-prefetch-ops legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-icache-prefetch-access legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-icache-prefetch-misses legacy cache Level 1 instruction cache prefetch misses legacy-cache-config=0x10201  00     l1-icache-prefetch-miss legacy cache Level 1 instruction cache prefetch misses legacy-cache-config=0x10201  10     l1-icache-prefetches legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  00     l1-icache-prefetches-refs legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-icache-prefetches-reference legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-icache-prefetches-ops legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-icache-prefetches-access legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-icache-prefetches-misses legacy cache Level 1 instruction cache prefetch misses legacy-cache-config=0x10201  10     l1-icache-prefetches-miss legacy cache Level 1 instruction cache prefetch misses legacy-cache-config=0x10201  10     l1-icache-speculative-read legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-icache-speculative-read-refs legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-icache-speculative-read-reference legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-icache-speculative-read-ops legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-icache-speculative-read-access legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-icache-speculative-read-misses legacy cache Level 1 instruction cache prefetch misses legacy-cache-config=0x10201  10     l1-icache-speculative-read-miss legacy cache Level 1 instruction cache prefetch misses legacy-cache-config=0x10201  10     l1-icache-speculative-load legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-icache-speculative-load-refs legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-icache-speculative-load-reference legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-icache-speculative-load-ops legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-icache-speculative-load-access legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-icache-speculative-load-misses legacy cache Level 1 instruction cache prefetch misses legacy-cache-config=0x10201  10     l1-icache-speculative-load-miss legacy cache Level 1 instruction cache prefetch misses legacy-cache-config=0x10201  10     l1-icache-refs legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-icache-reference legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-icache-ops legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-icache-access legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-icache-misses legacy cache Level 1 instruction cache read misses legacy-cache-config=0x10001  10     l1-icache-miss legacy cache Level 1 instruction cache read misses legacy-cache-config=0x10001  10     l1-i legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-i-load legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-i-load-refs legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-i-load-reference legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-i-load-ops legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-i-load-access legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-i-load-misses legacy cache Level 1 instruction cache read misses legacy-cache-config=0x10001  10     l1-i-load-miss legacy cache Level 1 instruction cache read misses legacy-cache-config=0x10001  10     l1-i-loads legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-i-loads-refs legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-i-loads-reference legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-i-loads-ops legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-i-loads-access legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-i-loads-misses legacy cache Level 1 instruction cache read misses legacy-cache-config=0x10001  10     l1-i-loads-miss legacy cache Level 1 instruction cache read misses legacy-cache-config=0x10001  10     l1-i-read legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-i-read-refs legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-i-read-reference legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-i-read-ops legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-i-read-access legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-i-read-misses legacy cache Level 1 instruction cache read misses legacy-cache-config=0x10001  10     l1-i-read-miss legacy cache Level 1 instruction cache read misses legacy-cache-config=0x10001  10     l1-i-prefetch legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-i-prefetch-refs legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-i-prefetch-reference legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-i-prefetch-ops legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-i-prefetch-access legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-i-prefetch-misses legacy cache Level 1 instruction cache prefetch misses legacy-cache-config=0x10201  10     l1-i-prefetch-miss legacy cache Level 1 instruction cache prefetch misses legacy-cache-config=0x10201  10     l1-i-prefetches legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-i-prefetches-refs legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-i-prefetches-reference legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-i-prefetches-ops legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-i-prefetches-access legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-i-prefetches-misses legacy cache Level 1 instruction cache prefetch misses legacy-cache-config=0x10201  10     l1-i-prefetches-miss legacy cache Level 1 instruction cache prefetch misses legacy-cache-config=0x10201  10     l1-i-speculative-read legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-i-speculative-read-refs legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-i-speculative-read-reference legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-i-speculative-read-ops legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-i-speculative-read-access legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-i-speculative-read-misses legacy cache Level 1 instruction cache prefetch misses legacy-cache-config=0x10201  10     l1-i-speculative-read-miss legacy cache Level 1 instruction cache prefetch misses legacy-cache-config=0x10201  10     l1-i-speculative-load legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-i-speculative-load-refs legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-i-speculative-load-reference legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-i-speculative-load-ops legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-i-speculative-load-access legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-i-speculative-load-misses legacy cache Level 1 instruction cache prefetch misses legacy-cache-config=0x10201  10     l1-i-speculative-load-miss legacy cache Level 1 instruction cache prefetch misses legacy-cache-config=0x10201  10     l1-i-refs legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-i-reference legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-i-ops legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-i-access legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-i-misses legacy cache Level 1 instruction cache read misses legacy-cache-config=0x10001  10     l1-i-miss legacy cache Level 1 instruction cache read misses legacy-cache-config=0x10001  10     l1i legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1i-load legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1i-load-refs legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1i-load-reference legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1i-load-ops legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1i-load-access legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1i-load-misses legacy cache Level 1 instruction cache read misses legacy-cache-config=0x10001  10     l1i-load-miss legacy cache Level 1 instruction cache read misses legacy-cache-config=0x10001  10     l1i-loads legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1i-loads-refs legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1i-loads-reference legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1i-loads-ops legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1i-loads-access legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1i-loads-misses legacy cache Level 1 instruction cache read misses legacy-cache-config=0x10001  10     l1i-loads-miss legacy cache Level 1 instruction cache read misses legacy-cache-config=0x10001  10     l1i-read legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1i-read-refs legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1i-read-reference legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1i-read-ops legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1i-read-access legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1i-read-misses legacy cache Level 1 instruction cache read misses legacy-cache-config=0x10001  10     l1i-read-miss legacy cache Level 1 instruction cache read misses legacy-cache-config=0x10001  10     l1i-prefetch legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1i-prefetch-refs legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1i-prefetch-reference legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1i-prefetch-ops legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1i-prefetch-access legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1i-prefetch-misses legacy cache Level 1 instruction cache prefetch misses legacy-cache-config=0x10201  10     l1i-prefetch-miss legacy cache Level 1 instruction cache prefetch misses legacy-cache-config=0x10201  10     l1i-prefetches legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1i-prefetches-refs legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1i-prefetches-reference legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1i-prefetches-ops legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1i-prefetches-access legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1i-prefetches-misses legacy cache Level 1 instruction cache prefetch misses legacy-cache-config=0x10201  10     l1i-prefetches-miss legacy cache Level 1 instruction cache prefetch misses legacy-cache-config=0x10201  10     l1i-speculative-read legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1i-speculative-read-refs legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1i-speculative-read-reference legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1i-speculative-read-ops legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1i-speculative-read-access legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1i-speculative-read-misses legacy cache Level 1 instruction cache prefetch misses legacy-cache-config=0x10201  10     l1i-speculative-read-miss legacy cache Level 1 instruction cache prefetch misses legacy-cache-config=0x10201  10     l1i-speculative-load legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1i-speculative-load-refs legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1i-speculative-load-reference legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1i-speculative-load-ops legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1i-speculative-load-access legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1i-speculative-load-misses legacy cache Level 1 instruction cache prefetch misses legacy-cache-config=0x10201  10     l1i-speculative-load-miss legacy cache Level 1 instruction cache prefetch misses legacy-cache-config=0x10201  10     l1i-refs legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1i-reference legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1i-ops legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1i-access legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1i-misses legacy cache Level 1 instruction cache read misses legacy-cache-config=0x10001  10     l1i-miss legacy cache Level 1 instruction cache read misses legacy-cache-config=0x10001  10     l1-instruction legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-instruction-load legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-instruction-load-refs legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-instruction-load-reference legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-instruction-load-ops legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-instruction-load-access legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-instruction-load-misses legacy cache Level 1 instruction cache read misses legacy-cache-config=0x10001  10     l1-instruction-load-miss legacy cache Level 1 instruction cache read misses legacy-cache-config=0x10001  10     l1-instruction-loads legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-instruction-loads-refs legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-instruction-loads-reference legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-instruction-loads-ops legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-instruction-loads-access legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-instruction-loads-misses legacy cache Level 1 instruction cache read misses legacy-cache-config=0x10001  10     l1-instruction-loads-miss legacy cache Level 1 instruction cache read misses legacy-cache-config=0x10001  10     l1-instruction-read legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-instruction-read-refs legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-instruction-read-reference legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-instruction-read-ops legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-instruction-read-access legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-instruction-read-misses legacy cache Level 1 instruction cache read misses legacy-cache-config=0x10001  10     l1-instruction-read-miss legacy cache Level 1 instruction cache read misses legacy-cache-config=0x10001  10     l1-instruction-prefetch legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-instruction-prefetch-refs legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-instruction-prefetch-reference legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-instruction-prefetch-ops legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-instruction-prefetch-access legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-instruction-prefetch-misses legacy cache Level 1 instruction cache prefetch misses legacy-cache-config=0x10201  10     l1-instruction-prefetch-miss legacy cache Level 1 instruction cache prefetch misses legacy-cache-config=0x10201  10     l1-instruction-prefetches legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-instruction-prefetches-refs legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-instruction-prefetches-reference legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-instruction-prefetches-ops legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-instruction-prefetches-access legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-instruction-prefetches-misses legacy cache Level 1 instruction cache prefetch misses legacy-cache-config=0x10201  10     l1-instruction-prefetches-miss legacy cache Level 1 instruction cache prefetch misses legacy-cache-config=0x10201  10     l1-instruction-speculative-read legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-instruction-speculative-read-refs legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-instruction-speculative-read-reference legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-instruction-speculative-read-ops legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-instruction-speculative-read-access legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-instruction-speculative-read-misses legacy cache Level 1 instruction cache prefetch misses legacy-cache-config=0x10201  10     l1-instruction-speculative-read-miss legacy cache Level 1 instruction cache prefetch misses legacy-cache-config=0x10201  10     l1-instruction-speculative-load legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-instruction-speculative-load-refs legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-instruction-speculative-load-reference legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-instruction-speculative-load-ops legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-instruction-speculative-load-access legacy cache Level 1 instruction cache prefetch accesses legacy-cache-config=0x201  10     l1-instruction-speculative-load-misses legacy cache Level 1 instruction cache prefetch misses legacy-cache-config=0x10201  10     l1-instruction-speculative-load-miss legacy cache Level 1 instruction cache prefetch misses legacy-cache-config=0x10201  10     l1-instruction-refs legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-instruction-reference legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-instruction-ops legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-instruction-access legacy cache Level 1 instruction cache read accesses legacy-cache-config=1  10     l1-instruction-misses legacy cache Level 1 instruction cache read misses legacy-cache-config=0x10001  10     l1-instruction-miss legacy cache Level 1 instruction cache read misses legacy-cache-config=0x10001  10     llc legacy cache Last level cache read accesses legacy-cache-config=2  10     llc-load legacy cache Last level cache read accesses legacy-cache-config=2  10     llc-load-refs legacy cache Last level cache read accesses legacy-cache-config=2  10     llc-load-reference legacy cache Last level cache read accesses legacy-cache-config=2  10     llc-load-ops legacy cache Last level cache read accesses legacy-cache-config=2  10     llc-load-access legacy cache Last level cache read accesses legacy-cache-config=2  10     llc-load-misses legacy cache Last level cache read misses legacy-cache-config=0x10002  00     llc-load-miss legacy cache Last level cache read misses legacy-cache-config=0x10002  10     llc-loads legacy cache Last level cache read accesses legacy-cache-config=2  00     llc-loads-refs legacy cache Last level cache read accesses legacy-cache-config=2  10     llc-loads-reference legacy cache Last level cache read accesses legacy-cache-config=2  10     llc-loads-ops legacy cache Last level cache read accesses legacy-cache-config=2  10     llc-loads-access legacy cache Last level cache read accesses legacy-cache-config=2  10     llc-loads-misses legacy cache Last level cache read misses legacy-cache-config=0x10002  10     llc-loads-miss legacy cache Last level cache read misses legacy-cache-config=0x10002  10     llc-read legacy cache Last level cache read accesses legacy-cache-config=2  10     llc-read-refs legacy cache Last level cache read accesses legacy-cache-config=2  10     llc-read-reference legacy cache Last level cache read accesses legacy-cache-config=2  10     llc-read-ops legacy cache Last level cache read accesses legacy-cache-config=2  10     llc-read-access legacy cache Last level cache read accesses legacy-cache-config=2  10     llc-read-misses legacy cache Last level cache read misses legacy-cache-config=0x10002  10     llc-read-miss legacy cache Last level cache read misses legacy-cache-config=0x10002  10     llc-store legacy cache Last level cache write accesses legacy-cache-config=0x102  10     llc-store-refs legacy cache Last level cache write accesses legacy-cache-config=0x102  10     llc-store-reference legacy cache Last level cache write accesses legacy-cache-config=0x102  10     llc-store-ops legacy cache Last level cache write accesses legacy-cache-config=0x102  10     llc-store-access legacy cache Last level cache write accesses legacy-cache-config=0x102  10     llc-store-misses legacy cache Last level cache write misses legacy-cache-config=0x10102  00     llc-store-miss legacy cache Last level cache write misses legacy-cache-config=0x10102  10     llc-stores legacy cache Last level cache write accesses legacy-cache-config=0x102  00     llc-stores-refs legacy cache Last level cache write accesses legacy-cache-config=0x102  10     llc-stores-reference legacy cache Last level cache write accesses legacy-cache-config=0x102  10     llc-stores-ops legacy cache Last level cache write accesses legacy-cache-config=0x102  10     llc-stores-access legacy cache Last level cache write accesses legacy-cache-config=0x102  10     llc-stores-misses legacy cache Last level cache write misses legacy-cache-config=0x10102  10     llc-stores-miss legacy cache Last level cache write misses legacy-cache-config=0x10102  10     llc-write legacy cache Last level cache write accesses legacy-cache-config=0x102  10     llc-write-refs legacy cache Last level cache write accesses legacy-cache-config=0x102  10     llc-write-reference legacy cache Last level cache write accesses legacy-cache-config=0x102  10     llc-write-ops legacy cache Last level cache write accesses legacy-cache-config=0x102  10     llc-write-access legacy cache Last level cache write accesses legacy-cache-config=0x102  10     llc-write-misses legacy cache Last level cache write misses legacy-cache-config=0x10102  10     llc-write-miss legacy cache Last level cache write misses legacy-cache-config=0x10102  10     llc-prefetch legacy cache Last level cache prefetch accesses legacy-cache-config=0x202  10     llc-prefetch-refs legacy cache Last level cache prefetch accesses legacy-cache-config=0x202  10     llc-prefetch-reference legacy cache Last level cache prefetch accesses legacy-cache-config=0x202  10     llc-prefetch-ops legacy cache Last level cache prefetch accesses legacy-cache-config=0x202  10     llc-prefetch-access legacy cache Last level cache prefetch accesses legacy-cache-config=0x202  10     llc-prefetch-misses legacy cache Last level cache prefetch misses legacy-cache-config=0x10202  00     llc-prefetch-miss legacy cache Last level cache prefetch misses legacy-cache-config=0x10202  10     llc-prefetches legacy cache Last level cache prefetch accesses legacy-cache-config=0x202  00     llc-prefetches-refs legacy cache Last level cache prefetch accesses legacy-cache-config=0x202  10     llc-prefetches-reference legacy cache Last level cache prefetch accesses legacy-cache-config=0x202  10     llc-prefetches-ops legacy cache Last level cache prefetch accesses legacy-cache-config=0x202  10     llc-prefetches-access legacy cache Last level cache prefetch accesses legacy-cache-config=0x202  10     llc-prefetches-misses legacy cache Last level cache prefetch misses legacy-cache-config=0x10202  10     llc-prefetches-miss legacy cache Last level cache prefetch misses legacy-cache-config=0x10202  10     llc-speculative-read legacy cache Last level cache prefetch accesses legacy-cache-config=0x202  10     llc-speculative-read-refs legacy cache Last level cache prefetch accesses legacy-cache-config=0x202  10     llc-speculative-read-reference legacy cache Last level cache prefetch accesses legacy-cache-config=0x202  10     llc-speculative-read-ops legacy cache Last level cache prefetch accesses legacy-cache-config=0x202  10     llc-speculative-read-access legacy cache Last level cache prefetch accesses legacy-cache-config=0x202  10     llc-speculative-read-misses legacy cache Last level cache prefetch misses legacy-cache-config=0x10202  10     llc-speculative-read-miss legacy cache Last level cache prefetch misses legacy-cache-config=0x10202  10     llc-speculative-load legacy cache Last level cache prefetch accesses legacy-cache-config=0x202  10     llc-speculative-load-refs legacy cache Last level cache prefetch accesses legacy-cache-config=0x202  10     llc-speculative-load-reference legacy cache Last level cache prefetch accesses legacy-cache-config=0x202  10     llc-speculative-load-ops legacy cache Last level cache prefetch accesses legacy-cache-config=0x202  10     llc-speculative-load-access legacy cache Last level cache prefetch accesses legacy-cache-config=0x202  10     llc-speculative-load-misses legacy cache Last level cache prefetch misses legacy-cache-config=0x10202  10     llc-speculative-load-miss legacy cache Last level cache prefetch misses legacy-cache-config=0x10202  10     llc-refs legacy cache Last level cache read accesses legacy-cache-config=2  10     llc-reference legacy cache Last level cache read accesses legacy-cache-config=2  10     llc-ops legacy cache Last level cache read accesses legacy-cache-config=2  10     llc-access legacy cache Last level cache read accesses legacy-cache-config=2  10     llc-misses legacy cache Last level cache read misses legacy-cache-config=0x10002  10     llc-miss legacy cache Last level cache read misses legacy-cache-config=0x10002  10     l2 legacy cache Level 2 (or higher) last level cache read accesses legacy-cache-config=2  10     l2-load legacy cache Level 2 (or higher) last level cache read accesses legacy-cache-config=2  10     l2-load-refs legacy cache Level 2 (or higher) last level cache read accesses legacy-cache-config=2  10     l2-load-reference legacy cache Level 2 (or higher) last level cache read accesses legacy-cache-config=2  10     l2-load-ops legacy cache Level 2 (or higher) last level cache read accesses legacy-cache-config=2  10     l2-load-access legacy cache Level 2 (or higher) last level cache read accesses legacy-cache-config=2  10     l2-load-misses legacy cache Level 2 (or higher) last level cache read misses legacy-cache-config=0x10002  10     l2-load-miss legacy cache Level 2 (or higher) last level cache read misses legacy-cache-config=0x10002  10     l2-loads legacy cache Level 2 (or higher) last level cache read accesses legacy-cache-config=2  10     l2-loads-refs legacy cache Level 2 (or higher) last level cache read accesses legacy-cache-config=2  10     l2-loads-reference legacy cache Level 2 (or higher) last level cache read accesses legacy-cache-config=2  10     l2-loads-ops legacy cache Level 2 (or higher) last level cache read accesses legacy-cache-config=2  10     l2-loads-access legacy cache Level 2 (or higher) last level cache read accesses legacy-cache-config=2  10     l2-loads-misses legacy cache Level 2 (or higher) last level cache read misses legacy-cache-config=0x10002  10     l2-loads-miss legacy cache Level 2 (or higher) last level cache read misses legacy-cache-config=0x10002  10     l2-read legacy cache Level 2 (or higher) last level cache read accesses legacy-cache-config=2  10     l2-read-refs legacy cache Level 2 (or higher) last level cache read accesses legacy-cache-config=2  10     l2-read-reference legacy cache Level 2 (or higher) last level cache read accesses legacy-cache-config=2  10     l2-read-ops legacy cache Level 2 (or higher) last level cache read accesses legacy-cache-config=2  10     l2-read-access legacy cache Level 2 (or higher) last level cache read accesses legacy-cache-config=2  10     l2-read-misses legacy cache Level 2 (or higher) last level cache read misses legacy-cache-config=0x10002  10     l2-read-miss legacy cache Level 2 (or higher) last level cache read misses legacy-cache-config=0x10002  10     l2-store legacy cache Level 2 (or higher) last level cache write accesses legacy-cache-config=0x102  10     l2-store-refs legacy cache Level 2 (or higher) last level cache write accesses legacy-cache-config=0x102  10     l2-store-reference legacy cache Level 2 (or higher) last level cache write accesses legacy-cache-config=0x102  10     l2-store-ops legacy cache Level 2 (or higher) last level cache write accesses legacy-cache-config=0x102  10     l2-store-access legacy cache Level 2 (or higher) last level cache write accesses legacy-cache-config=0x102  10     l2-store-misses legacy cache Level 2 (or higher) last level cache write misses legacy-cache-config=0x10102  10     l2-store-miss legacy cache Level 2 (or higher) last level cache write misses legacy-cache-config=0x10102  10     l2-stores legacy cache Level 2 (or higher) last level cache write accesses legacy-cache-config=0x102  10     l2-stores-refs legacy cache Level 2 (or higher) last level cache write accesses legacy-cache-config=0x102  10     l2-stores-reference legacy cache Level 2 (or higher) last level cache write accesses legacy-cache-config=0x102  10     l2-stores-ops legacy cache Level 2 (or higher) last level cache write accesses legacy-cache-config=0x102  10     l2-stores-access legacy cache Level 2 (or higher) last level cache write accesses legacy-cache-config=0x102  10     l2-stores-misses legacy cache Level 2 (or higher) last level cache write misses legacy-cache-config=0x10102  10     l2-stores-miss legacy cache Level 2 (or higher) last level cache write misses legacy-cache-config=0x10102  10     l2-write legacy cache Level 2 (or higher) last level cache write accesses legacy-cache-config=0x102  10     l2-write-refs legacy cache Level 2 (or higher) last level cache write accesses legacy-cache-config=0x102  10     l2-write-reference legacy cache Level 2 (or higher) last level cache write accesses legacy-cache-config=0x102  10     l2-write-ops legacy cache Level 2 (or higher) last level cache write accesses legacy-cache-config=0x102  10     l2-write-access legacy cache Level 2 (or higher) last level cache write accesses legacy-cache-config=0x102  10     l2-write-misses legacy cache Level 2 (or higher) last level cache write misses legacy-cache-config=0x10102  10     l2-write-miss legacy cache Level 2 (or higher) last level cache write misses legacy-cache-config=0x10102  10     l2-prefetch legacy cache Level 2 (or higher) last level cache prefetch accesses legacy-cache-config=0x202  10     l2-prefetch-refs legacy cache Level 2 (or higher) last level cache prefetch accesses legacy-cache-config=0x202  10     l2-prefetch-reference legacy cache Level 2 (or higher) last level cache prefetch accesses legacy-cache-config=0x202  10     l2-prefetch-ops legacy cache Level 2 (or higher) last level cache prefetch accesses legacy-cache-config=0x202  10     l2-prefetch-access legacy cache Level 2 (or higher) last level cache prefetch accesses legacy-cache-config=0x202  10     l2-prefetch-misses legacy cache Level 2 (or higher) last level cache prefetch misses legacy-cache-config=0x10202  10     l2-prefetch-miss legacy cache Level 2 (or higher) last level cache prefetch misses legacy-cache-config=0x10202  10     l2-prefetches legacy cache Level 2 (or higher) last level cache prefetch accesses legacy-cache-config=0x202  10     l2-prefetches-refs legacy cache Level 2 (or higher) last level cache prefetch accesses legacy-cache-config=0x202  10     l2-prefetches-reference legacy cache Level 2 (or higher) last level cache prefetch accesses legacy-cache-config=0x202  10     l2-prefetches-ops legacy cache Level 2 (or higher) last level cache prefetch accesses legacy-cache-config=0x202  10     l2-prefetches-access legacy cache Level 2 (or higher) last level cache prefetch accesses legacy-cache-config=0x202  10     l2-prefetches-misses legacy cache Level 2 (or higher) last level cache prefetch misses legacy-cache-config=0x10202  10     l2-prefetches-miss legacy cache Level 2 (or higher) last level cache prefetch misses legacy-cache-config=0x10202  10     l2-speculative-read legacy cache Level 2 (or higher) last level cache prefetch accesses legacy-cache-config=0x202  10     l2-speculative-read-refs legacy cache Level 2 (or higher) last level cache prefetch accesses legacy-cache-config=0x202  10     l2-speculative-read-reference legacy cache Level 2 (or higher) last level cache prefetch accesses legacy-cache-config=0x202  10     l2-speculative-read-ops legacy cache Level 2 (or higher) last level cache prefetch accesses legacy-cache-config=0x202  10     l2-speculative-read-access legacy cache Level 2 (or higher) last level cache prefetch accesses legacy-cache-config=0x202  10     l2-speculative-read-misses legacy cache Level 2 (or higher) last level cache prefetch misses legacy-cache-config=0x10202  10     l2-speculative-read-miss legacy cache Level 2 (or higher) last level cache prefetch misses legacy-cache-config=0x10202  10     l2-speculative-load legacy cache Level 2 (or higher) last level cache prefetch accesses legacy-cache-config=0x202  10     l2-speculative-load-refs legacy cache Level 2 (or higher) last level cache prefetch accesses legacy-cache-config=0x202  10     l2-speculative-load-reference legacy cache Level 2 (or higher) last level cache prefetch accesses legacy-cache-config=0x202  10     l2-speculative-load-ops legacy cache Level 2 (or higher) last level cache prefetch accesses legacy-cache-config=0x202  10     l2-speculative-load-access legacy cache Level 2 (or higher) last level cache prefetch accesses legacy-cache-config=0x202  10     l2-speculative-load-misses legacy cache Level 2 (or higher) last level cache prefetch misses legacy-cache-config=0x10202  10     l2-speculative-load-miss legacy cache Level 2 (or higher) last level cache prefetch misses legacy-cache-config=0x10202  10     l2-refs legacy cache Level 2 (or higher) last level cache read accesses legacy-cache-config=2  10     l2-reference legacy cache Level 2 (or higher) last level cache read accesses legacy-cache-config=2  10     l2-ops legacy cache Level 2 (or higher) last level cache read accesses legacy-cache-config=2  10     l2-access legacy cache Level 2 (or higher) last level cache read accesses legacy-cache-config=2  10     l2-misses legacy cache Level 2 (or higher) last level cache read misses legacy-cache-config=0x10002  10     l2-miss legacy cache Level 2 (or higher) last level cache read misses legacy-cache-config=0x10002  10     dtlb legacy cache Data TLB read accesses legacy-cache-config=3  10     dtlb-load legacy cache Data TLB read accesses legacy-cache-config=3  10     dtlb-load-refs legacy cache Data TLB read accesses legacy-cache-config=3  10     dtlb-load-reference legacy cache Data TLB read accesses legacy-cache-config=3  10     dtlb-load-ops legacy cache Data TLB read accesses legacy-cache-config=3  10     dtlb-load-access legacy cache Data TLB read accesses legacy-cache-config=3  10     dtlb-load-misses legacy cache Data TLB read misses legacy-cache-config=0x10003  00     dtlb-load-miss legacy cache Data TLB read misses legacy-cache-config=0x10003  10     dtlb-loads legacy cache Data TLB read accesses legacy-cache-config=3  00     dtlb-loads-refs legacy cache Data TLB read accesses legacy-cache-config=3  10     dtlb-loads-reference legacy cache Data TLB read accesses legacy-cache-config=3  10     dtlb-loads-ops legacy cache Data TLB read accesses legacy-cache-config=3  10     dtlb-loads-access legacy cache Data TLB read accesses legacy-cache-config=3  10     dtlb-loads-misses legacy cache Data TLB read misses legacy-cache-config=0x10003  10     dtlb-loads-miss legacy cache Data TLB read misses legacy-cache-config=0x10003  10     dtlb-read legacy cache Data TLB read accesses legacy-cache-config=3  10     dtlb-read-refs legacy cache Data TLB read accesses legacy-cache-config=3  10     dtlb-read-reference legacy cache Data TLB read accesses legacy-cache-config=3  10     dtlb-read-ops legacy cache Data TLB read accesses legacy-cache-config=3  10     dtlb-read-access legacy cache Data TLB read accesses legacy-cache-config=3  10     dtlb-read-misses legacy cache Data TLB read misses legacy-cache-config=0x10003  10     dtlb-read-miss legacy cache Data TLB read misses legacy-cache-config=0x10003  10     dtlb-store legacy cache Data TLB write accesses legacy-cache-config=0x103  10     dtlb-store-refs legacy cache Data TLB write accesses legacy-cache-config=0x103  10     dtlb-store-reference legacy cache Data TLB write accesses legacy-cache-config=0x103  10     dtlb-store-ops legacy cache Data TLB write accesses legacy-cache-config=0x103  10     dtlb-store-access legacy cache Data TLB write accesses legacy-cache-config=0x103  10     dtlb-store-misses legacy cache Data TLB write misses legacy-cache-config=0x10103  00     dtlb-store-miss legacy cache Data TLB write misses legacy-cache-config=0x10103  10     dtlb-stores legacy cache Data TLB write accesses legacy-cache-config=0x103  00     dtlb-stores-refs legacy cache Data TLB write accesses legacy-cache-config=0x103  10     dtlb-stores-reference legacy cache Data TLB write accesses legacy-cache-config=0x103  10     dtlb-stores-ops legacy cache Data TLB write accesses legacy-cache-config=0x103  10     dtlb-stores-access legacy cache Data TLB write accesses legacy-cache-config=0x103  10     dtlb-stores-misses legacy cache Data TLB write misses legacy-cache-config=0x10103  10     dtlb-stores-miss legacy cache Data TLB write misses legacy-cache-config=0x10103  10     dtlb-write legacy cache Data TLB write accesses legacy-cache-config=0x103  10     dtlb-write-refs legacy cache Data TLB write accesses legacy-cache-config=0x103  10     dtlb-write-reference legacy cache Data TLB write accesses legacy-cache-config=0x103  10     dtlb-write-ops legacy cache Data TLB write accesses legacy-cache-config=0x103  10     dtlb-write-access legacy cache Data TLB write accesses legacy-cache-config=0x103  10     dtlb-write-misses legacy cache Data TLB write misses legacy-cache-config=0x10103  10     dtlb-write-miss legacy cache Data TLB write misses legacy-cache-config=0x10103  10     dtlb-prefetch legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     dtlb-prefetch-refs legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     dtlb-prefetch-reference legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     dtlb-prefetch-ops legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     dtlb-prefetch-access legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     dtlb-prefetch-misses legacy cache Data TLB prefetch misses legacy-cache-config=0x10203  00     dtlb-prefetch-miss legacy cache Data TLB prefetch misses legacy-cache-config=0x10203  10     dtlb-prefetches legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  00     dtlb-prefetches-refs legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     dtlb-prefetches-reference legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     dtlb-prefetches-ops legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     dtlb-prefetches-access legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     dtlb-prefetches-misses legacy cache Data TLB prefetch misses legacy-cache-config=0x10203  10     dtlb-prefetches-miss legacy cache Data TLB prefetch misses legacy-cache-config=0x10203  10     dtlb-speculative-read legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     dtlb-speculative-read-refs legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     dtlb-speculative-read-reference legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     dtlb-speculative-read-ops legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     dtlb-speculative-read-access legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     dtlb-speculative-read-misses legacy cache Data TLB prefetch misses legacy-cache-config=0x10203  10     dtlb-speculative-read-miss legacy cache Data TLB prefetch misses legacy-cache-config=0x10203  10     dtlb-speculative-load legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     dtlb-speculative-load-refs legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     dtlb-speculative-load-reference legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     dtlb-speculative-load-ops legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     dtlb-speculative-load-access legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     dtlb-speculative-load-misses legacy cache Data TLB prefetch misses legacy-cache-config=0x10203  10     dtlb-speculative-load-miss legacy cache Data TLB prefetch misses legacy-cache-config=0x10203  10     dtlb-refs legacy cache Data TLB read accesses legacy-cache-config=3  10     dtlb-reference legacy cache Data TLB read accesses legacy-cache-config=3  10     dtlb-ops legacy cache Data TLB read accesses legacy-cache-config=3  10     dtlb-access legacy cache Data TLB read accesses legacy-cache-config=3  10     dtlb-misses legacy cache Data TLB read misses legacy-cache-config=0x10003  10     dtlb-miss legacy cache Data TLB read misses legacy-cache-config=0x10003  10     d-tlb legacy cache Data TLB read accesses legacy-cache-config=3  10     d-tlb-load legacy cache Data TLB read accesses legacy-cache-config=3  10     d-tlb-load-refs legacy cache Data TLB read accesses legacy-cache-config=3  10     d-tlb-load-reference legacy cache Data TLB read accesses legacy-cache-config=3  10     d-tlb-load-ops legacy cache Data TLB read accesses legacy-cache-config=3  10     d-tlb-load-access legacy cache Data TLB read accesses legacy-cache-config=3  10     d-tlb-load-misses legacy cache Data TLB read misses legacy-cache-config=0x10003  10     d-tlb-load-miss legacy cache Data TLB read misses legacy-cache-config=0x10003  10     d-tlb-loads legacy cache Data TLB read accesses legacy-cache-config=3  10     d-tlb-loads-refs legacy cache Data TLB read accesses legacy-cache-config=3  10     d-tlb-loads-reference legacy cache Data TLB read accesses legacy-cache-config=3  10     d-tlb-loads-ops legacy cache Data TLB read accesses legacy-cache-config=3  10     d-tlb-loads-access legacy cache Data TLB read accesses legacy-cache-config=3  10     d-tlb-loads-misses legacy cache Data TLB read misses legacy-cache-config=0x10003  10     d-tlb-loads-miss legacy cache Data TLB read misses legacy-cache-config=0x10003  10     d-tlb-read legacy cache Data TLB read accesses legacy-cache-config=3  10     d-tlb-read-refs legacy cache Data TLB read accesses legacy-cache-config=3  10     d-tlb-read-reference legacy cache Data TLB read accesses legacy-cache-config=3  10     d-tlb-read-ops legacy cache Data TLB read accesses legacy-cache-config=3  10     d-tlb-read-access legacy cache Data TLB read accesses legacy-cache-config=3  10     d-tlb-read-misses legacy cache Data TLB read misses legacy-cache-config=0x10003  10     d-tlb-read-miss legacy cache Data TLB read misses legacy-cache-config=0x10003  10     d-tlb-store legacy cache Data TLB write accesses legacy-cache-config=0x103  10     d-tlb-store-refs legacy cache Data TLB write accesses legacy-cache-config=0x103  10     d-tlb-store-reference legacy cache Data TLB write accesses legacy-cache-config=0x103  10     d-tlb-store-ops legacy cache Data TLB write accesses legacy-cache-config=0x103  10     d-tlb-store-access legacy cache Data TLB write accesses legacy-cache-config=0x103  10     d-tlb-store-misses legacy cache Data TLB write misses legacy-cache-config=0x10103  10     d-tlb-store-miss legacy cache Data TLB write misses legacy-cache-config=0x10103  10     d-tlb-stores legacy cache Data TLB write accesses legacy-cache-config=0x103  10     d-tlb-stores-refs legacy cache Data TLB write accesses legacy-cache-config=0x103  10     d-tlb-stores-reference legacy cache Data TLB write accesses legacy-cache-config=0x103  10     d-tlb-stores-ops legacy cache Data TLB write accesses legacy-cache-config=0x103  10     d-tlb-stores-access legacy cache Data TLB write accesses legacy-cache-config=0x103  10     d-tlb-stores-misses legacy cache Data TLB write misses legacy-cache-config=0x10103  10     d-tlb-stores-miss legacy cache Data TLB write misses legacy-cache-config=0x10103  10     d-tlb-write legacy cache Data TLB write accesses legacy-cache-config=0x103  10     d-tlb-write-refs legacy cache Data TLB write accesses legacy-cache-config=0x103  10     d-tlb-write-reference legacy cache Data TLB write accesses legacy-cache-config=0x103  10     d-tlb-write-ops legacy cache Data TLB write accesses legacy-cache-config=0x103  10     d-tlb-write-access legacy cache Data TLB write accesses legacy-cache-config=0x103  10     d-tlb-write-misses legacy cache Data TLB write misses legacy-cache-config=0x10103  10     d-tlb-write-miss legacy cache Data TLB write misses legacy-cache-config=0x10103  10     d-tlb-prefetch legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     d-tlb-prefetch-refs legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     d-tlb-prefetch-reference legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     d-tlb-prefetch-ops legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     d-tlb-prefetch-access legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     d-tlb-prefetch-misses legacy cache Data TLB prefetch misses legacy-cache-config=0x10203  10     d-tlb-prefetch-miss legacy cache Data TLB prefetch misses legacy-cache-config=0x10203  10     d-tlb-prefetches legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     d-tlb-prefetches-refs legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     d-tlb-prefetches-reference legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     d-tlb-prefetches-ops legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     d-tlb-prefetches-access legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     d-tlb-prefetches-misses legacy cache Data TLB prefetch misses legacy-cache-config=0x10203  10     d-tlb-prefetches-miss legacy cache Data TLB prefetch misses legacy-cache-config=0x10203  10     d-tlb-speculative-read legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     d-tlb-speculative-read-refs legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     d-tlb-speculative-read-reference legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     d-tlb-speculative-read-ops legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     d-tlb-speculative-read-access legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     d-tlb-speculative-read-misses legacy cache Data TLB prefetch misses legacy-cache-config=0x10203  10     d-tlb-speculative-read-miss legacy cache Data TLB prefetch misses legacy-cache-config=0x10203  10     d-tlb-speculative-load legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     d-tlb-speculative-load-refs legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     d-tlb-speculative-load-reference legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     d-tlb-speculative-load-ops legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     d-tlb-speculative-load-access legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     d-tlb-speculative-load-misses legacy cache Data TLB prefetch misses legacy-cache-config=0x10203  10     d-tlb-speculative-load-miss legacy cache Data TLB prefetch misses legacy-cache-config=0x10203  10     d-tlb-refs legacy cache Data TLB read accesses legacy-cache-config=3  10     d-tlb-reference legacy cache Data TLB read accesses legacy-cache-config=3  10     d-tlb-ops legacy cache Data TLB read accesses legacy-cache-config=3  10     d-tlb-access legacy cache Data TLB read accesses legacy-cache-config=3  10     d-tlb-misses legacy cache Data TLB read misses legacy-cache-config=0x10003  10     d-tlb-miss legacy cache Data TLB read misses legacy-cache-config=0x10003  10     data-tlb legacy cache Data TLB read accesses legacy-cache-config=3  10     data-tlb-load legacy cache Data TLB read accesses legacy-cache-config=3  10     data-tlb-load-refs legacy cache Data TLB read accesses legacy-cache-config=3  10     data-tlb-load-reference legacy cache Data TLB read accesses legacy-cache-config=3  10     data-tlb-load-ops legacy cache Data TLB read accesses legacy-cache-config=3  10     data-tlb-load-access legacy cache Data TLB read accesses legacy-cache-config=3  10     data-tlb-load-misses legacy cache Data TLB read misses legacy-cache-config=0x10003  10     data-tlb-load-miss legacy cache Data TLB read misses legacy-cache-config=0x10003  10     data-tlb-loads legacy cache Data TLB read accesses legacy-cache-config=3  10     data-tlb-loads-refs legacy cache Data TLB read accesses legacy-cache-config=3  10     data-tlb-loads-reference legacy cache Data TLB read accesses legacy-cache-config=3  10     data-tlb-loads-ops legacy cache Data TLB read accesses legacy-cache-config=3  10     data-tlb-loads-access legacy cache Data TLB read accesses legacy-cache-config=3  10     data-tlb-loads-misses legacy cache Data TLB read misses legacy-cache-config=0x10003  10     data-tlb-loads-miss legacy cache Data TLB read misses legacy-cache-config=0x10003  10     data-tlb-read legacy cache Data TLB read accesses legacy-cache-config=3  10     data-tlb-read-refs legacy cache Data TLB read accesses legacy-cache-config=3  10     data-tlb-read-reference legacy cache Data TLB read accesses legacy-cache-config=3  10     data-tlb-read-ops legacy cache Data TLB read accesses legacy-cache-config=3  10     data-tlb-read-access legacy cache Data TLB read accesses legacy-cache-config=3  10     data-tlb-read-misses legacy cache Data TLB read misses legacy-cache-config=0x10003  10     data-tlb-read-miss legacy cache Data TLB read misses legacy-cache-config=0x10003  10     data-tlb-store legacy cache Data TLB write accesses legacy-cache-config=0x103  10     data-tlb-store-refs legacy cache Data TLB write accesses legacy-cache-config=0x103  10     data-tlb-store-reference legacy cache Data TLB write accesses legacy-cache-config=0x103  10     data-tlb-store-ops legacy cache Data TLB write accesses legacy-cache-config=0x103  10     data-tlb-store-access legacy cache Data TLB write accesses legacy-cache-config=0x103  10     data-tlb-store-misses legacy cache Data TLB write misses legacy-cache-config=0x10103  10     data-tlb-store-miss legacy cache Data TLB write misses legacy-cache-config=0x10103  10     data-tlb-stores legacy cache Data TLB write accesses legacy-cache-config=0x103  10     data-tlb-stores-refs legacy cache Data TLB write accesses legacy-cache-config=0x103  10     data-tlb-stores-reference legacy cache Data TLB write accesses legacy-cache-config=0x103  10     data-tlb-stores-ops legacy cache Data TLB write accesses legacy-cache-config=0x103  10     data-tlb-stores-access legacy cache Data TLB write accesses legacy-cache-config=0x103  10     data-tlb-stores-misses legacy cache Data TLB write misses legacy-cache-config=0x10103  10     data-tlb-stores-miss legacy cache Data TLB write misses legacy-cache-config=0x10103  10     data-tlb-write legacy cache Data TLB write accesses legacy-cache-config=0x103  10     data-tlb-write-refs legacy cache Data TLB write accesses legacy-cache-config=0x103  10     data-tlb-write-reference legacy cache Data TLB write accesses legacy-cache-config=0x103  10     data-tlb-write-ops legacy cache Data TLB write accesses legacy-cache-config=0x103  10     data-tlb-write-access legacy cache Data TLB write accesses legacy-cache-config=0x103  10     data-tlb-write-misses legacy cache Data TLB write misses legacy-cache-config=0x10103  10     data-tlb-write-miss legacy cache Data TLB write misses legacy-cache-config=0x10103  10     data-tlb-prefetch legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     data-tlb-prefetch-refs legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     data-tlb-prefetch-reference legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     data-tlb-prefetch-ops legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     data-tlb-prefetch-access legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     data-tlb-prefetch-misses legacy cache Data TLB prefetch misses legacy-cache-config=0x10203  10     data-tlb-prefetch-miss legacy cache Data TLB prefetch misses legacy-cache-config=0x10203  10     data-tlb-prefetches legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     data-tlb-prefetches-refs legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     data-tlb-prefetches-reference legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     data-tlb-prefetches-ops legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     data-tlb-prefetches-access legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     data-tlb-prefetches-misses legacy cache Data TLB prefetch misses legacy-cache-config=0x10203  10     data-tlb-prefetches-miss legacy cache Data TLB prefetch misses legacy-cache-config=0x10203  10     data-tlb-speculative-read legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     data-tlb-speculative-read-refs legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     data-tlb-speculative-read-reference legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     data-tlb-speculative-read-ops legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     data-tlb-speculative-read-access legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     data-tlb-speculative-read-misses legacy cache Data TLB prefetch misses legacy-cache-config=0x10203  10     data-tlb-speculative-read-miss legacy cache Data TLB prefetch misses legacy-cache-config=0x10203  10     data-tlb-speculative-load legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     data-tlb-speculative-load-refs legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     data-tlb-speculative-load-reference legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     data-tlb-speculative-load-ops legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     data-tlb-speculative-load-access legacy cache Data TLB prefetch accesses legacy-cache-config=0x203  10     data-tlb-speculative-load-misses legacy cache Data TLB prefetch misses legacy-cache-config=0x10203  10     data-tlb-speculative-load-miss legacy cache Data TLB prefetch misses legacy-cache-config=0x10203  10     data-tlb-refs legacy cache Data TLB read accesses legacy-cache-config=3  10     data-tlb-reference legacy cache Data TLB read accesses legacy-cache-config=3  10     data-tlb-ops legacy cache Data TLB read accesses legacy-cache-config=3  10     data-tlb-access legacy cache Data TLB read accesses legacy-cache-config=3  10     data-tlb-misses legacy cache Data TLB read misses legacy-cache-config=0x10003  10     data-tlb-miss legacy cache Data TLB read misses legacy-cache-config=0x10003  10     itlb legacy cache Instruction TLB read accesses legacy-cache-config=4  10     itlb-load legacy cache Instruction TLB read accesses legacy-cache-config=4  10     itlb-load-refs legacy cache Instruction TLB read accesses legacy-cache-config=4  10     itlb-load-reference legacy cache Instruction TLB read accesses legacy-cache-config=4  10     itlb-load-ops legacy cache Instruction TLB read accesses legacy-cache-config=4  10     itlb-load-access legacy cache Instruction TLB read accesses legacy-cache-config=4  10     itlb-load-misses legacy cache Instruction TLB read misses legacy-cache-config=0x10004  00     itlb-load-miss legacy cache Instruction TLB read misses legacy-cache-config=0x10004  10     itlb-loads legacy cache Instruction TLB read accesses legacy-cache-config=4  00     itlb-loads-refs legacy cache Instruction TLB read accesses legacy-cache-config=4  10     itlb-loads-reference legacy cache Instruction TLB read accesses legacy-cache-config=4  10     itlb-loads-ops legacy cache Instruction TLB read accesses legacy-cache-config=4  10     itlb-loads-access legacy cache Instruction TLB read accesses legacy-cache-config=4  10     itlb-loads-misses legacy cache Instruction TLB read misses legacy-cache-config=0x10004  10     itlb-loads-miss legacy cache Instruction TLB read misses legacy-cache-config=0x10004  10     itlb-read legacy cache Instruction TLB read accesses legacy-cache-config=4  10     itlb-read-refs legacy cache Instruction TLB read accesses legacy-cache-config=4  10     itlb-read-reference legacy cache Instruction TLB read accesses legacy-cache-config=4  10     itlb-read-ops legacy cache Instruction TLB read accesses legacy-cache-config=4  10     itlb-read-access legacy cache Instruction TLB read accesses legacy-cache-config=4  10     itlb-read-misses legacy cache Instruction TLB read misses legacy-cache-config=0x10004  10     itlb-read-miss legacy cache Instruction TLB read misses legacy-cache-config=0x10004  10     itlb-refs legacy cache Instruction TLB read accesses legacy-cache-config=4  10     itlb-reference legacy cache Instruction TLB read accesses legacy-cache-config=4  10     itlb-ops legacy cache Instruction TLB read accesses legacy-cache-config=4  10     itlb-access legacy cache Instruction TLB read accesses legacy-cache-config=4  10     itlb-misses legacy cache Instruction TLB read misses legacy-cache-config=0x10004  10     itlb-miss legacy cache Instruction TLB read misses legacy-cache-config=0x10004  10     i-tlb legacy cache Instruction TLB read accesses legacy-cache-config=4  10     i-tlb-load legacy cache Instruction TLB read accesses legacy-cache-config=4  10     i-tlb-load-refs legacy cache Instruction TLB read accesses legacy-cache-config=4  10     i-tlb-load-reference legacy cache Instruction TLB read accesses legacy-cache-config=4  10     i-tlb-load-ops legacy cache Instruction TLB read accesses legacy-cache-config=4  10     i-tlb-load-access legacy cache Instruction TLB read accesses legacy-cache-config=4  10     i-tlb-load-misses legacy cache Instruction TLB read misses legacy-cache-config=0x10004  10     i-tlb-load-miss legacy cache Instruction TLB read misses legacy-cache-config=0x10004  10     i-tlb-loads legacy cache Instruction TLB read accesses legacy-cache-config=4  10     i-tlb-loads-refs legacy cache Instruction TLB read accesses legacy-cache-config=4  10     i-tlb-loads-reference legacy cache Instruction TLB read accesses legacy-cache-config=4  10     i-tlb-loads-ops legacy cache Instruction TLB read accesses legacy-cache-config=4  10     i-tlb-loads-access legacy cache Instruction TLB read accesses legacy-cache-config=4  10     i-tlb-loads-misses legacy cache Instruction TLB read misses legacy-cache-config=0x10004  10     i-tlb-loads-miss legacy cache Instruction TLB read misses legacy-cache-config=0x10004  10     i-tlb-read legacy cache Instruction TLB read accesses legacy-cache-config=4  10     i-tlb-read-refs legacy cache Instruction TLB read accesses legacy-cache-config=4  10     i-tlb-read-reference legacy cache Instruction TLB read accesses legacy-cache-config=4  10     i-tlb-read-ops legacy cache Instruction TLB read accesses legacy-cache-config=4  10     i-tlb-read-access legacy cache Instruction TLB read accesses legacy-cache-config=4  10     i-tlb-read-misses legacy cache Instruction TLB read misses legacy-cache-config=0x10004  10     i-tlb-read-miss legacy cache Instruction TLB read misses legacy-cache-config=0x10004  10     i-tlb-refs legacy cache Instruction TLB read accesses legacy-cache-config=4  10     i-tlb-reference legacy cache Instruction TLB read accesses legacy-cache-config=4  10     i-tlb-ops legacy cache Instruction TLB read accesses legacy-cache-config=4  10     i-tlb-access legacy cache Instruction TLB read accesses legacy-cache-config=4  10     i-tlb-misses legacy cache Instruction TLB read misses legacy-cache-config=0x10004  10     i-tlb-miss legacy cache Instruction TLB read misses legacy-cache-config=0x10004  10     instruction-tlb legacy cache Instruction TLB read accesses legacy-cache-config=4  10     instruction-tlb-load legacy cache Instruction TLB read accesses legacy-cache-config=4  10     instruction-tlb-load-refs legacy cache Instruction TLB read accesses legacy-cache-config=4  10     instruction-tlb-load-reference legacy cache Instruction TLB read accesses legacy-cache-config=4  10     instruction-tlb-load-ops legacy cache Instruction TLB read accesses legacy-cache-config=4  10     instruction-tlb-load-access legacy cache Instruction TLB read accesses legacy-cache-config=4  10     instruction-tlb-load-misses legacy cache Instruction TLB read misses legacy-cache-config=0x10004  10     instruction-tlb-load-miss legacy cache Instruction TLB read misses legacy-cache-config=0x10004  10     instruction-tlb-loads legacy cache Instruction TLB read accesses legacy-cache-config=4  10     instruction-tlb-loads-refs legacy cache Instruction TLB read accesses legacy-cache-config=4  10     instruction-tlb-loads-reference legacy cache Instruction TLB read accesses legacy-cache-config=4  10     instruction-tlb-loads-ops legacy cache Instruction TLB read accesses legacy-cache-config=4  10     instruction-tlb-loads-access legacy cache Instruction TLB read accesses legacy-cache-config=4  10     instruction-tlb-loads-misses legacy cache Instruction TLB read misses legacy-cache-config=0x10004  10     instruction-tlb-loads-miss legacy cache Instruction TLB read misses legacy-cache-config=0x10004  10     instruction-tlb-read legacy cache Instruction TLB read accesses legacy-cache-config=4  10     instruction-tlb-read-refs legacy cache Instruction TLB read accesses legacy-cache-config=4  10     instruction-tlb-read-reference legacy cache Instruction TLB read accesses legacy-cache-config=4  10     instruction-tlb-read-ops legacy cache Instruction TLB read accesses legacy-cache-config=4  10     instruction-tlb-read-access legacy cache Instruction TLB read accesses legacy-cache-config=4  10     instruction-tlb-read-misses legacy cache Instruction TLB read misses legacy-cache-config=0x10004  10     instruction-tlb-read-miss legacy cache Instruction TLB read misses legacy-cache-config=0x10004  10     instruction-tlb-refs legacy cache Instruction TLB read accesses legacy-cache-config=4  10     instruction-tlb-reference legacy cache Instruction TLB read accesses legacy-cache-config=4  10     instruction-tlb-ops legacy cache Instruction TLB read accesses legacy-cache-config=4  10     instruction-tlb-access legacy cache Instruction TLB read accesses legacy-cache-config=4  10     instruction-tlb-misses legacy cache Instruction TLB read misses legacy-cache-config=0x10004  10     instruction-tlb-miss legacy cache Instruction TLB read misses legacy-cache-config=0x10004  10     branch legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branch-load legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branch-load-refs legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branch-load-reference legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branch-load-ops legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branch-load-access legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branch-load-misses legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  00     branch-load-miss legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     branch-loads legacy cache Branch prediction unit read accesses legacy-cache-config=5  00     branch-loads-refs legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branch-loads-reference legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branch-loads-ops legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branch-loads-access legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branch-loads-misses legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     branch-loads-miss legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     branch-read legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branch-read-refs legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branch-read-reference legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branch-read-ops legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branch-read-access legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branch-read-misses legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     branch-read-miss legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     branch-refs legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branch-reference legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branch-ops legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branch-access legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branch-miss legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     branches-load legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branches-load-refs legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branches-load-reference legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branches-load-ops legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branches-load-access legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branches-load-misses legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     branches-load-miss legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     branches-loads legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branches-loads-refs legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branches-loads-reference legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branches-loads-ops legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branches-loads-access legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branches-loads-misses legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     branches-loads-miss legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     branches-read legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branches-read-refs legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branches-read-reference legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branches-read-ops legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branches-read-access legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branches-read-misses legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     branches-read-miss legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     branches-refs legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branches-reference legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branches-ops legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branches-access legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     branches-misses legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     branches-miss legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     bpu legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpu-load legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpu-load-refs legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpu-load-reference legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpu-load-ops legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpu-load-access legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpu-load-misses legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     bpu-load-miss legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     bpu-loads legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpu-loads-refs legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpu-loads-reference legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpu-loads-ops legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpu-loads-access legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpu-loads-misses legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     bpu-loads-miss legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     bpu-read legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpu-read-refs legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpu-read-reference legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpu-read-ops legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpu-read-access legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpu-read-misses legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     bpu-read-miss legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     bpu-refs legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpu-reference legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpu-ops legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpu-access legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpu-misses legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     bpu-miss legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     btb legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     btb-load legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     btb-load-refs legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     btb-load-reference legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     btb-load-ops legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     btb-load-access legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     btb-load-misses legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     btb-load-miss legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     btb-loads legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     btb-loads-refs legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     btb-loads-reference legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     btb-loads-ops legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     btb-loads-access legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     btb-loads-misses legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     btb-loads-miss legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     btb-read legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     btb-read-refs legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     btb-read-reference legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     btb-read-ops legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     btb-read-access legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     btb-read-misses legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     btb-read-miss legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     btb-refs legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     btb-reference legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     btb-ops legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     btb-access legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     btb-misses legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     btb-miss legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     bpc legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpc-load legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpc-load-refs legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpc-load-reference legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpc-load-ops legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpc-load-access legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpc-load-misses legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     bpc-load-miss legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     bpc-loads legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpc-loads-refs legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpc-loads-reference legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpc-loads-ops legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpc-loads-access legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpc-loads-misses legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     bpc-loads-miss legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     bpc-read legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpc-read-refs legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpc-read-reference legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpc-read-ops legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpc-read-access legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpc-read-misses legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     bpc-read-miss legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     bpc-refs legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpc-reference legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpc-ops legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpc-access legacy cache Branch prediction unit read accesses legacy-cache-config=5  10     bpc-misses legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     bpc-miss legacy cache Branch prediction unit read misses legacy-cache-config=0x10005  10     node legacy cache Local memory read accesses legacy-cache-config=6  10     node-load legacy cache Local memory read accesses legacy-cache-config=6  10     node-load-refs legacy cache Local memory read accesses legacy-cache-config=6  10     node-load-reference legacy cache Local memory read accesses legacy-cache-config=6  10     node-load-ops legacy cache Local memory read accesses legacy-cache-config=6  10     node-load-access legacy cache Local memory read accesses legacy-cache-config=6  10     node-load-misses legacy cache Local memory read misses legacy-cache-config=0x10006  00     node-load-miss legacy cache Local memory read misses legacy-cache-config=0x10006  10     node-loads legacy cache Local memory read accesses legacy-cache-config=6  00     node-loads-refs legacy cache Local memory read accesses legacy-cache-config=6  10     node-loads-reference legacy cache Local memory read accesses legacy-cache-config=6  10     node-loads-ops legacy cache Local memory read accesses legacy-cache-config=6  10     node-loads-access legacy cache Local memory read accesses legacy-cache-config=6  10     node-loads-misses legacy cache Local memory read misses legacy-cache-config=0x10006  10     node-loads-miss legacy cache Local memory read misses legacy-cache-config=0x10006  10     node-read legacy cache Local memory read accesses legacy-cache-config=6  10     node-read-refs legacy cache Local memory read accesses legacy-cache-config=6  10     node-read-reference legacy cache Local memory read accesses legacy-cache-config=6  10     node-read-ops legacy cache Local memory read accesses legacy-cache-config=6  10     node-read-access legacy cache Local memory read accesses legacy-cache-config=6  10     node-read-misses legacy cache Local memory read misses legacy-cache-config=0x10006  10     node-read-miss legacy cache Local memory read misses legacy-cache-config=0x10006  10     node-store legacy cache Local memory write accesses legacy-cache-config=0x106  10     node-store-refs legacy cache Local memory write accesses legacy-cache-config=0x106  10     node-store-reference legacy cache Local memory write accesses legacy-cache-config=0x106  10     node-store-ops legacy cache Local memory write accesses legacy-cache-config=0x106  10     node-store-access legacy cache Local memory write accesses legacy-cache-config=0x106  10     node-store-misses legacy cache Local memory write misses legacy-cache-config=0x10106  00     node-store-miss legacy cache Local memory write misses legacy-cache-config=0x10106  10     node-stores legacy cache Local memory write accesses legacy-cache-config=0x106  00     node-stores-refs legacy cache Local memory write accesses legacy-cache-config=0x106  10     node-stores-reference legacy cache Local memory write accesses legacy-cache-config=0x106  10     node-stores-ops legacy cache Local memory write accesses legacy-cache-config=0x106  10     node-stores-access legacy cache Local memory write accesses legacy-cache-config=0x106  10     node-stores-misses legacy cache Local memory write misses legacy-cache-config=0x10106  10     node-stores-miss legacy cache Local memory write misses legacy-cache-config=0x10106  10     node-write legacy cache Local memory write accesses legacy-cache-config=0x106  10     node-write-refs legacy cache Local memory write accesses legacy-cache-config=0x106  10     node-write-reference legacy cache Local memory write accesses legacy-cache-config=0x106  10     node-write-ops legacy cache Local memory write accesses legacy-cache-config=0x106  10     node-write-access legacy cache Local memory write accesses legacy-cache-config=0x106  10     node-write-misses legacy cache Local memory write misses legacy-cache-config=0x10106  10     node-write-miss legacy cache Local memory write misses legacy-cache-config=0x10106  10     node-prefetch legacy cache Local memory prefetch accesses legacy-cache-config=0x206  10     node-prefetch-refs legacy cache Local memory prefetch accesses legacy-cache-config=0x206  10     node-prefetch-reference legacy cache Local memory prefetch accesses legacy-cache-config=0x206  10     node-prefetch-ops legacy cache Local memory prefetch accesses legacy-cache-config=0x206  10     node-prefetch-access legacy cache Local memory prefetch accesses legacy-cache-config=0x206  10     node-prefetch-misses legacy cache Local memory prefetch misses legacy-cache-config=0x10206  00     node-prefetch-miss legacy cache Local memory prefetch misses legacy-cache-config=0x10206  10     node-prefetches legacy cache Local memory prefetch accesses legacy-cache-config=0x206  00     node-prefetches-refs legacy cache Local memory prefetch accesses legacy-cache-config=0x206  10     node-prefetches-reference legacy cache Local memory prefetch accesses legacy-cache-config=0x206  10     node-prefetches-ops legacy cache Local memory prefetch accesses legacy-cache-config=0x206  10     node-prefetches-access legacy cache Local memory prefetch accesses legacy-cache-config=0x206  10     node-prefetches-misses legacy cache Local memory prefetch misses legacy-cache-config=0x10206  10     node-prefetches-miss legacy cache Local memory prefetch misses legacy-cache-config=0x10206  10     node-speculative-read legacy cache Local memory prefetch accesses legacy-cache-config=0x206  10     node-speculative-read-refs legacy cache Local memory prefetch accesses legacy-cache-config=0x206  10     node-speculative-read-reference legacy cache Local memory prefetch accesses legacy-cache-config=0x206  10     node-speculative-read-ops legacy cache Local memory prefetch accesses legacy-cache-config=0x206  10     node-speculative-read-access legacy cache Local memory prefetch accesses legacy-cache-config=0x206  10     node-speculative-read-misses legacy cache Local memory prefetch misses legacy-cache-config=0x10206  10     node-speculative-read-miss legacy cache Local memory prefetch misses legacy-cache-config=0x10206  10     node-speculative-load legacy cache Local memory prefetch accesses legacy-cache-config=0x206  10     node-speculative-load-refs legacy cache Local memory prefetch accesses legacy-cache-config=0x206  10     node-speculative-load-reference legacy cache Local memory prefetch accesses legacy-cache-config=0x206  10     node-speculative-load-ops legacy cache Local memory prefetch accesses legacy-cache-config=0x206  10     node-speculative-load-access legacy cache Local memory prefetch accesses legacy-cache-config=0x206  10     node-speculative-load-misses legacy cache Local memory prefetch misses legacy-cache-config=0x10206  10     node-speculative-load-miss legacy cache Local memory prefetch misses legacy-cache-config=0x10206  10     node-refs legacy cache Local memory read accesses legacy-cache-config=6  10     node-reference legacy cache Local memory read accesses legacy-cache-config=6  10     node-ops legacy cache Local memory read accesses legacy-cache-config=6  10     node-access legacy cache Local memory read accesses legacy-cache-config=6  10     node-misses legacy cache Local memory read misses legacy-cache-config=0x10006  10     node-miss legacy cache Local memory read misses legacy-cache-config=0x10006  10     cpu-cycles legacy hardware Total cycles. Be wary of what happens during CPU frequency scaling [This event is an alias of cycles] legacy-hardware-config=0  00     cycles legacy hardware Total cycles. Be wary of what happens during CPU frequency scaling [This event is an alias of cpu-cycles] legacy-hardware-config=0  00     instructions legacy hardware Retired instructions. Be careful, these can be affected by various issues, most notably hardware interrupt counts legacy-hardware-config=1  00     cache-references legacy hardware Cache accesses. Usually this indicates Last Level Cache accesses but this may vary depending on your CPU.  This may include prefetches and coherency messages; again this depends on the design of your CPU legacy-hardware-config=2  00     cache-misses legacy hardware Cache misses. Usually this indicates Last Level Cache misses; this is intended to be used in conjunction with the PERF_COUNT_HW_CACHE_REFERENCES event to calculate cache miss rates legacy-hardware-config=3  00     branches legacy hardware Retired branch instructions [This event is an alias of branch-instructions] legacy-hardware-config=4  00     branch-instructions legacy hardware Retired branch instructions [This event is an alias of branches] legacy-hardware-config=4  00     branch-misses legacy hardware Mispredicted branch instructions legacy-hardware-config=5  00     bus-cycles legacy hardware Bus cycles, which can be different from total cycles legacy-hardware-config=6  00     stalled-cycles-frontend legacy hardware Stalled cycles during issue [This event is an alias of idle-cycles-frontend] legacy-hardware-config=7  00     idle-cycles-frontend legacy hardware Stalled cycles during issue [This event is an alias of stalled-cycles-fronted] legacy-hardware-config=7  00     stalled-cycles-backend legacy hardware Stalled cycles during retirement [This event is an alias of idle-cycles-backend] legacy-hardware-config=8  00     idle-cycles-backend legacy hardware Stalled cycles during retirement [This event is an alias of stalled-cycles-backend] legacy-hardware-config=8  00     ref-cycles legacy hardware Total cycles; not affected by CPU frequency scaling legacy-hardware-config=9  00     software cpu-clock software Per-CPU high-resolution timer based event config=0  001e-6msec     task-clock software Per-task high-resolution timer based event config=1  001e-6msec     faults software Number of page faults [This event is an alias of page-faults] config=2  00     page-faults software Number of page faults [This event is an alias of faults] config=2  00     context-switches software Number of context switches [This event is an alias of cs] config=3  00     cs software Number of context switches [This event is an alias of context-switches] config=3  00     cpu-migrations software Number of times a process has migrated to a new CPU [This event is an alias of migrations] config=4  00     migrations software Number of times a process has migrated to a new CPU [This event is an alias of cpu-migrations] config=4  00     minor-faults software Number of minor page faults. Minor faults don't require I/O to handle config=5  00     major-faults software Number of major page faults. Major faults require I/O to handle config=6  00     alignment-faults software Number of kernel handled memory alignment faults config=7  00     emulation-faults software Number of kernel handled unimplemented instruction faults handled through emulation config=8  00     dummy software A placeholder event that doesn't count anything config=9  00     bpf-output software An event used by BPF programs to write to the perf ring buffer config=0xa  00     cgroup-switches software Number of context switches to a task in a different cgroup config=0xb  00     tool duration_time tool Wall clock interval time in nanoseconds config=1  00     user_time tool User (non-kernel) time in nanoseconds config=2  00     system_time tool System/kernel time in nanoseconds config=3  00     has_pmem tool 1 if persistent memory installed otherwise 0 config=4  00     num_cores tool Number of cores. A core consists of 1 or more thread, with each thread being associated with a logical Linux CPU config=5  00     num_cpus tool Number of logical Linux CPUs. There may be multiple such CPUs on a core config=6  00     num_cpus_online tool Number of online logical Linux CPUs. There may be multiple such CPUs on a core config=7  00     num_dies tool Number of dies. Each die has 1 or more cores config=8  00     num_packages tool Number of packages. Each package has 1 or more die config=9  00     slots tool Number of functional units that in parallel can execute parts of an instruction config=0xa  00     smt_on tool 1 if simultaneous multithreading (aka hyperthreading) is enable otherwise 0 config=0xb  00     system_tsc_freq tool The amount a Time Stamp Counter (TSC) increases per second config=0xc  00     core_wide tool 1 if not SMT, if SMT are events being gathered on all SMT threads 1 otherwise 0 config=0xd  00     target_cpu tool 1 if CPUs being analyzed, 0 if threads/processes config=0xe  00     bp_l1_btb_correct branch L1 BTB Correction event=0x8a  00     bp_l2_btb_correct branch L2 BTB Correction event=0x8b  00     l3_cache_rd cache L3 cache access, read event=0x40  00    Attributable Level 3 cache access, read segment_reg_loads.any other Number of segment register loads event=6,period=200000,umask=0x80  00     dispatch_blocked.any other Memory cluster signals to block micro-op dispatch for any reason event=9,period=200000,umask=0x20  00     eist_trans other Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions event=0x3a,period=200000  00     hisi_sccl,ddrc uncore_hisi_ddrc.flux_wcmd uncore DDRC write commands event=2  00     uncore_cbox unc_cbo_xsnp_response.miss_eviction uncore A cross-core snoop resulted from L3 Eviction which misses in some processor core event=0x22,umask=0x81  00     event-hyphen uncore UNC_CBO_HYPHEN event=0xe0  00     event-two-hyph uncore UNC_CBO_TWO_HYPH event=0xc0  00     hisi_sccl,l3c uncore_hisi_l3c.rd_hit_cpipe uncore Total read hits event=7  00     uncore_imc_free_running uncore_imc_free_running.cache_miss uncore Total cache misses event=0x12  00     uncore_imc uncore_imc.cache_hits uncore Total cache hits event=0x34  00     uncore_sys_ddr_pmu sys_ddr_pmu.write_cycles uncore ddr write-cycles event event=0x2b v8 00     uncore_sys_ccn_pmu sys_ccn_pmu.read_cycles uncore ccn read-cycles event config=0x2c 0x01 00     uncore_sys_cmn_pmu sys_cmn_pmu.hnf_cache_miss uncore Counts total cache misses in first lookup result (high priority) eventid=1,type=5 (434|436|43c|43a).* 00     l1d.hwpf_miss cache L1D.HWPF_MISS event=0x51,period=1000003,umask=0x20  00     l1d.replacement cache Counts the number of cache lines replaced in L1 data cache event=0x51,period=100003,umask=1  00    Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace l1d_pend_miss.fb_full cache Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability event=0x48,period=1000003,umask=2  00    Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses l1d_pend_miss.fb_full_periods cache Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability event=0x48,cmask=1,edge=1,period=1000003,umask=2  00    Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses l1d_pend_miss.l2_stall cache This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLS event=0x48,period=1000003,umask=4  10     l1d_pend_miss.l2_stalls cache Number of cycles a demand request has waited due to L1D due to lack of L2 resources event=0x48,period=1000003,umask=4  00    Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses l1d_pend_miss.pending cache Number of L1D misses that are outstanding event=0x48,period=1000003,umask=1  00    Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type l1d_pend_miss.pending_cycles cache Cycles with L1D load Misses outstanding event=0x48,cmask=1,period=1000003,umask=1  00    Counts duration of L1D miss outstanding in cycles l2_lines_in.all cache L2 cache lines filling L2 event=0x25,period=100003,umask=0x1f  00    Counts the number of L2 cache lines filling the L2. Counting does not cover rejects l2_lines_out.non_silent cache Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fill event=0x26,period=200003,umask=2  00    Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3 l2_lines_out.silent cache Non-modified cache lines that are silently dropped by L2 cache event=0x26,period=200003,umask=1  00    Counts the number of lines that are silently dropped by L2 cache. These lines are typically in Shared or Exclusive state. A non-threaded event l2_lines_out.useless_hwpf cache Cache lines that have been L2 hardware prefetched but not used by demand accesses event=0x26,period=200003,umask=4  00    Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cache l2_request.all cache Counts the total number of L2 Cache accesses. Counts on a per core basis event=0x24,period=200003  00    Counts the total number of L2 Cache Accesses, includes hits, misses, rejects  front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only.  Counts on a per core basis l2_request.all cache All accesses to L2 cache [This event is alias to L2_RQSTS.REFERENCES] event=0x24,period=200003,umask=0xff  00    Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.REFERENCES] l2_request.hit cache Counts the number of L2 Cache accesses that resulted in a hit. Counts on a per core basis event=0x24,period=200003,umask=2  00    Counts the number of L2 Cache accesses that resulted in a hit from a front door request only (does not include rejects or recycles), Counts on a per core basis l2_request.miss cache Counts the number of L2 Cache accesses that resulted in a miss. Counts on a per core basis event=0x24,period=200003,umask=1  00    Counts the number of L2 Cache accesses that resulted in a miss from a front door request only (does not include rejects or recycles). Counts on a per core basis l2_request.miss cache Read requests with true-miss in L2 cache. [This event is alias to L2_RQSTS.MISS] event=0x24,period=200003,umask=0x3f  00    Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.MISS] l2_rqsts.all_code_rd cache L2 code requests event=0x24,period=200003,umask=0xe4  00    Counts the total number of L2 code requests l2_rqsts.all_demand_data_rd cache Demand Data Read access L2 cache event=0x24,period=200003,umask=0xe1  00    Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once l2_rqsts.all_demand_miss cache Demand requests that miss L2 cache event=0x24,period=200003,umask=0x27  00    Counts demand requests that miss L2 cache l2_rqsts.all_hwpf cache L2_RQSTS.ALL_HWPF event=0x24,period=200003,umask=0xf0  00     l2_rqsts.all_rfo cache RFO requests to L2 cache event=0x24,period=200003,umask=0xe2  00    Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches l2_rqsts.code_rd_hit cache L2 cache hits when fetching instructions, code reads event=0x24,period=200003,umask=0xc4  00    Counts L2 cache hits when fetching instructions, code reads l2_rqsts.code_rd_miss cache L2 cache misses when fetching instructions event=0x24,period=200003,umask=0x24  00    Counts L2 cache misses when fetching instructions l2_rqsts.demand_data_rd_hit cache Demand Data Read requests that hit L2 cache event=0x24,period=200003,umask=0xc1  00    Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache l2_rqsts.demand_data_rd_miss cache Demand Data Read miss L2 cache event=0x24,period=200003,umask=0x21  00    Counts demand Data Read requests with true-miss in the L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. An access is counted once l2_rqsts.hwpf_miss cache L2_RQSTS.HWPF_MISS event=0x24,period=200003,umask=0x30  00     l2_rqsts.miss cache Read requests with true-miss in L2 cache. [This event is alias to L2_REQUEST.MISS] event=0x24,period=200003,umask=0x3f  00    Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.MISS] l2_rqsts.references cache All accesses to L2 cache [This event is alias to L2_REQUEST.ALL] event=0x24,period=200003,umask=0xff  00    Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.ALL] l2_rqsts.rfo_hit cache RFO requests that hit L2 cache event=0x24,period=200003,umask=0xc2  00    Counts the RFO (Read-for-Ownership) requests that hit L2 cache l2_rqsts.rfo_miss cache RFO requests that miss L2 cache event=0x24,period=200003,umask=0x22  00    Counts the RFO (Read-for-Ownership) requests that miss L2 cache l2_rqsts.swpf_hit cache SW prefetch requests that hit L2 cache event=0x24,period=200003,umask=0xc8  00    Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full l2_rqsts.swpf_miss cache SW prefetch requests that miss L2 cache event=0x24,period=200003,umask=0x28  00    Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full l2_trans.l2_wb cache L2 writebacks that access L2 cache event=0x23,period=200003,umask=0x40  00    Counts L2 writebacks that access L2 cache longest_lat_cache.miss cache Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis event=0x2e,period=200003,umask=0x41  00    Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis longest_lat_cache.miss cache Core-originated cacheable requests that missed L3  (Except hardware prefetches to the L3) event=0x2e,period=100003,umask=0x41  00    Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2.  It does not include hardware prefetches to the L3, and may not count other types of requests to the L3 longest_lat_cache.reference cache Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis event=0x2e,period=200003,umask=0x4f  00    Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis longest_lat_cache.reference cache Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3) event=0x2e,period=100003,umask=0x4f  00    Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2.  It does not include hardware prefetches to the L3, and may not count other types of requests to the L3 mem_bound_stalls.ifetch cache Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM) event=0x34,period=200003,umask=0x38  00    Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM) mem_bound_stalls.ifetch_dram_hit cache Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM) event=0x34,period=200003,umask=0x20  00    Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (non-DRAM) mem_bound_stalls.ifetch_l2_hit cache Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache event=0x34,period=200003,umask=8  00    Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache mem_bound_stalls.ifetch_llc_hit cache Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other core with HITE/F/M event=0x34,period=200003,umask=0x10  00    Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the Last Level Cache (LLC) or other core with HITE/F/M mem_bound_stalls.load cache Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM) event=0x34,period=200003,umask=7  00     mem_bound_stalls.load_dram_hit cache Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM) event=0x34,period=200003,umask=4  00     mem_bound_stalls.load_l2_hit cache Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache event=0x34,period=200003,umask=1  00     mem_bound_stalls.load_llc_hit cache Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/M event=0x34,period=200003,umask=2  00    Counts the number of cycles the core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M mem_inst_retired.all_loads cache Retired load instructions  Supports address when precise event=0xd0,period=1000003,umask=0x81  00    Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW. Available PDIST counters: 0  Supports address when precise mem_inst_retired.all_stores cache Retired store instructions  Supports address when precise event=0xd0,period=1000003,umask=0x82  00    Counts all retired store instructions. Available PDIST counters: 0  Supports address when precise mem_inst_retired.any cache All retired memory instructions  Supports address when precise event=0xd0,period=1000003,umask=0x83  00    Counts all retired memory instructions - loads and stores. Available PDIST counters: 0  Supports address when precise mem_inst_retired.lock_loads cache Retired load instructions with locked access  Supports address when precise event=0xd0,period=100007,umask=0x21  00    Counts retired load instructions with locked access. Available PDIST counters: 0  Supports address when precise mem_inst_retired.split_loads cache Retired load instructions that split across a cacheline boundary  Supports address when precise event=0xd0,period=100003,umask=0x41  00    Counts retired load instructions that split across a cacheline boundary. Available PDIST counters: 0  Supports address when precise mem_inst_retired.split_stores cache Retired store instructions that split across a cacheline boundary  Supports address when precise event=0xd0,period=100003,umask=0x42  00    Counts retired store instructions that split across a cacheline boundary. Available PDIST counters: 0  Supports address when precise mem_inst_retired.stlb_miss_loads cache Retired load instructions that miss the STLB  Supports address when precise event=0xd0,period=100003,umask=0x11  00    Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB). Available PDIST counters: 0  Supports address when precise mem_inst_retired.stlb_miss_stores cache Retired store instructions that miss the STLB  Supports address when precise event=0xd0,period=100003,umask=0x12  00    Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB). Available PDIST counters: 0  Supports address when precise mem_load_completed.l1_miss_any cache Completed demand load uops that miss the L1 d-cache event=0x43,period=1000003,umask=0xfd  00    Number of completed demand load requests that missed the L1 data cache including shadow misses (FB hits, merge to an ongoing L1D miss) mem_load_l3_hit_retired.xsnp_fwd cache Retired load instructions whose data sources were HitM responses from shared L3  Supports address when precise event=0xd2,period=20011,umask=4  00    Counts retired load instructions whose data sources were HitM responses from shared L3. Available PDIST counters: 0  Supports address when precise mem_load_l3_hit_retired.xsnp_hit cache Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache  Supports address when precise event=0xd2,period=20011,umask=2  00    Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache. Available PDIST counters: 0  Supports address when precise mem_load_l3_hit_retired.xsnp_hitm cache Retired load instructions whose data sources were HitM responses from shared L3  Supports address when precise event=0xd2,period=20011,umask=4  00    Counts retired load instructions whose data sources were HitM responses from shared L3. Available PDIST counters: 0  Supports address when precise mem_load_l3_hit_retired.xsnp_miss cache Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache  Supports address when precise event=0xd2,period=20011,umask=1  00    Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache. Available PDIST counters: 0  Supports address when precise mem_load_l3_hit_retired.xsnp_none cache Retired load instructions whose data sources were hits in L3 without snoops required  Supports address when precise event=0xd2,period=100003,umask=8  00    Counts retired load instructions whose data sources were hits in L3 without snoops required. Available PDIST counters: 0  Supports address when precise mem_load_l3_hit_retired.xsnp_no_fwd cache Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache  Supports address when precise event=0xd2,period=20011,umask=2  00    Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache. Available PDIST counters: 0  Supports address when precise mem_load_l3_miss_retired.local_dram cache Retired load instructions which data sources missed L3 but serviced from local dram  Supports address when precise event=0xd3,period=100007,umask=1  00    Retired load instructions which data sources missed L3 but serviced from local DRAM. Available PDIST counters: 0  Supports address when precise mem_load_misc_retired.uc cache Retired instructions with at least 1 uncacheable load or lock  Supports address when precise event=0xd4,period=100007,umask=4  00    Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock). Available PDIST counters: 0  Supports address when precise mem_load_retired.fb_hit cache Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1  Supports address when precise event=0xd1,period=100007,umask=0x40  00    Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready. Available PDIST counters: 0  Supports address when precise mem_load_retired.l1_hit cache Retired load instructions with L1 cache hits as data sources  Supports address when precise event=0xd1,period=1000003,umask=1  00    Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source. Available PDIST counters: 0  Supports address when precise mem_load_retired.l1_miss cache Retired load instructions missed L1 cache as data sources  Supports address when precise event=0xd1,period=200003,umask=8  00    Counts retired load instructions with at least one uop that missed in the L1 cache. Available PDIST counters: 0  Supports address when precise mem_load_retired.l2_hit cache Retired load instructions with L2 cache hits as data sources  Supports address when precise event=0xd1,period=200003,umask=2  00    Counts retired load instructions with L2 cache hits as data sources. Available PDIST counters: 0  Supports address when precise mem_load_retired.l2_miss cache Retired load instructions missed L2 cache as data sources  Supports address when precise event=0xd1,period=100021,umask=0x10  00    Counts retired load instructions missed L2 cache as data sources. Available PDIST counters: 0  Supports address when precise mem_load_retired.l3_hit cache Retired load instructions with L3 cache hits as data sources  Supports address when precise event=0xd1,period=100021,umask=4  00    Counts retired load instructions with at least one uop that hit in the L3 cache. Available PDIST counters: 0  Supports address when precise mem_load_retired.l3_miss cache Retired load instructions missed L3 cache as data sources  Supports address when precise event=0xd1,period=50021,umask=0x20  00    Counts retired load instructions with at least one uop that missed in the L3 cache. Available PDIST counters: 0  Supports address when precise mem_load_uops_retired.dram_hit cache Counts the number of load uops retired that hit in DRAM  Supports address when precise event=0xd1,period=200003,umask=0x80  00     mem_load_uops_retired.hitm cache Counts the number of load uops retired that hit in the L3 cache, in which a snoop was required and modified data was forwarded from another core or module  Supports address when precise event=0xd1,period=200003,umask=0x20  00     mem_load_uops_retired.l1_hit cache Counts the number of load uops retired that hit in the L1 data cache  Supports address when precise event=0xd1,period=200003,umask=1  00     mem_load_uops_retired.l1_miss cache Counts the number of load uops retired that miss in the L1 data cache  Supports address when precise event=0xd1,period=200003,umask=8  00     mem_load_uops_retired.l2_hit cache Counts the number of load uops retired that hit in the L2 cache  Supports address when precise event=0xd1,period=200003,umask=2  00     mem_load_uops_retired.l2_miss cache Counts the number of load uops retired that miss in the L2 cache  Supports address when precise event=0xd1,period=200003,umask=0x10  00     mem_load_uops_retired.l3_hit cache Counts the number of load uops retired that hit in the L3 cache  Supports address when precise event=0xd1,period=200003,umask=4  00     mem_load_uops_retired_misc.hit_e_f cache Counts the number of load uops retired that hit in the L3 cache, in which a snoop was required, and non-modified data was forwarded  Supports address when precise event=0xd2,period=1000003,umask=0x40  00     mem_load_uops_retired_misc.l3_miss cache Counts the number of load uops retired that miss in the L3 cache  Supports address when precise event=0xd2,period=1000003,umask=0x20  00     mem_scheduler_block.all cache Counts the number of cycles that uops are blocked for any of the following reasons:  load buffer, store buffer or RSV full event=4,period=20003,umask=7  00     mem_scheduler_block.ld_buf cache Counts the number of cycles that uops are blocked due to a load buffer full condition event=4,period=20003,umask=2  00     mem_scheduler_block.rsv cache Counts the number of cycles that uops are blocked due to an RSV full condition event=4,period=20003,umask=4  00     mem_scheduler_block.st_buf cache Counts the number of cycles that uops are blocked due to a store buffer full condition event=4,period=20003,umask=1  00     mem_store_retired.l2_hit cache MEM_STORE_RETIRED.L2_HIT event=0x44,period=200003,umask=1  00     mem_uops_retired.all_loads cache Counts the number of load uops retired  Supports address when precise event=0xd0,period=200003,umask=0x81  00    Counts the total number of load uops retired  Supports address when precise mem_uops_retired.all_stores cache Counts the number of store uops retired  Supports address when precise event=0xd0,period=200003,umask=0x82  00    Counts the total number of store uops retired  Supports address when precise mem_uops_retired.load_latency_gt_128 cache Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled  Supports address when precise event=0xd0,period=1000003,umask=5,ldlat=0x80  00    Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly  Supports address when precise mem_uops_retired.load_latency_gt_16 cache Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled  Supports address when precise event=0xd0,period=1000003,umask=5,ldlat=0x10  00    Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly  Supports address when precise mem_uops_retired.load_latency_gt_256 cache Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled  Supports address when precise event=0xd0,period=1000003,umask=5,ldlat=0x100  00    Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly  Supports address when precise mem_uops_retired.load_latency_gt_32 cache Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled  Supports address when precise event=0xd0,period=1000003,umask=5,ldlat=0x20  00    Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly  Supports address when precise mem_uops_retired.load_latency_gt_4 cache Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled  Supports address when precise event=0xd0,period=1000003,umask=5,ldlat=0x4  00    Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly  Supports address when precise mem_uops_retired.load_latency_gt_512 cache Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled  Supports address when precise event=0xd0,period=1000003,umask=5,ldlat=0x200  00    Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly  Supports address when precise mem_uops_retired.load_latency_gt_64 cache Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled  Supports address when precise event=0xd0,period=1000003,umask=5,ldlat=0x40  00    Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly  Supports address when precise mem_uops_retired.load_latency_gt_8 cache Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled  Supports address when precise event=0xd0,period=1000003,umask=5,ldlat=0x8  00    Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly  Supports address when precise mem_uops_retired.lock_loads cache Counts the number of load uops retired that performed one or more locks  Supports address when precise event=0xd0,period=200003,umask=0x21  00     mem_uops_retired.split_loads cache Counts the number of retired split load uops  Supports address when precise event=0xd0,period=200003,umask=0x41  00     mem_uops_retired.stlb_miss cache Counts the total number of load and store uops retired that missed in the second level TLB  Supports address when precise event=0xd0,period=200003,umask=0x13  00     mem_uops_retired.stlb_miss_loads cache Counts the number of load ops retired that miss in the second Level TLB  Supports address when precise event=0xd0,period=200003,umask=0x11  00     mem_uops_retired.stlb_miss_stores cache Counts the number of store ops retired that miss in the second level TLB  Supports address when precise event=0xd0,period=200003,umask=0x12  00     mem_uops_retired.store_latency cache Counts the number of stores uops retired. Counts with or without PEBS enabled  Supports address when precise event=0xd0,period=1000003,umask=6  00    Counts the number of stores uops retired. Counts with or without PEBS enabled. If PEBS is enabled and a PEBS record is generated, will populate PEBS Latency and PEBS Data Source fields accordingly  Supports address when precise mem_uop_retired.any cache Retired memory uops for any access event=0xe5,period=1000003,umask=3  00    Number of retired micro-operations (uops) for load or store memory accesses ocr.corewb_m.any_response cache Counts modified writebacks from L1 cache and L2 cache that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10008  00    Counts modified writebacks from L1 cache and L2 cache that have any type of response. Available PDIST counters: 0 ocr.corewb_m.l3_hit cache Counts writebacks of modified cachelines that hit in the L3 or were snooped from another core's caches event=0x2a,period=100003,umask=1,offcore_rsp=0x1F803C0008  00    Counts writebacks of modified cachelines that hit in the L3 or were snooped from another core's caches. Available PDIST counters: 0 ocr.corewb_nonm.l3_hit cache Counts writebacks of non-modified cachelines that hit in the L3 or were snooped from another core's caches event=0x2a,period=100003,umask=1,offcore_rsp=0x1F803C1000  00    Counts writebacks of non-modified cachelines that hit in the L3 or were snooped from another core's caches. Available PDIST counters: 0 ocr.demand_code_rd.any_response cache Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10004  00    Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response. Available PDIST counters: 0 ocr.demand_code_rd.l3_hit cache Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x1F803C0004  00    Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache. Available PDIST counters: 0 ocr.demand_code_rd.l3_hit.snoop_hitm cache Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0004  00    Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. Available PDIST counters: 0 ocr.demand_code_rd.l3_hit.snoop_hit_no_fwd cache Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0004  00    Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. Available PDIST counters: 0 ocr.demand_code_rd.l3_hit.snoop_hit_with_fwd cache Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0004  00    Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. Available PDIST counters: 0 ocr.demand_data_rd.any_response cache Counts demand data reads that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10001  00    Counts demand data reads that have any type of response. Available PDIST counters: 0 ocr.demand_data_rd.any_response cache Counts demand data reads that have any type of response event=0x2a,period=100003,umask=1,offcore_rsp=0x10001  00    Counts demand data reads that have any type of response. Available PDIST counters: 0 ocr.demand_data_rd.l3_hit cache Counts demand data reads that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x1F803C0001  00    Counts demand data reads that were supplied by the L3 cache. Available PDIST counters: 0 ocr.demand_data_rd.l3_hit.snoop_hitm cache Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0001  00    Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. Available PDIST counters: 0 ocr.demand_data_rd.l3_hit.snoop_hitm cache Counts demand data reads that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified event=0x2a,period=100003,umask=1,offcore_rsp=0x10003C0001  00    Counts demand data reads that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified. Available PDIST counters: 0 ocr.demand_data_rd.l3_hit.snoop_hit_no_fwd cache Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0001  00    Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. Available PDIST counters: 0 ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd cache Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0001  00    Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. Available PDIST counters: 0 ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd cache Counts demand data reads that resulted in a snoop hit in another cores caches which forwarded the unmodified data to the requesting core event=0x2a,period=100003,umask=1,offcore_rsp=0x8003C0001  00    Counts demand data reads that resulted in a snoop hit in another cores caches which forwarded the unmodified data to the requesting core. Available PDIST counters: 0 ocr.demand_rfo.any_response cache Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10002  00    Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response. Available PDIST counters: 0 ocr.demand_rfo.any_response cache Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response event=0x2a,period=100003,umask=1,offcore_rsp=0x10002  00    Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response. Available PDIST counters: 0 ocr.demand_rfo.l3_hit cache Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x1F803C0002  00    Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache. Available PDIST counters: 0 ocr.demand_rfo.l3_hit.snoop_hitm cache Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0002  00    Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. Available PDIST counters: 0 ocr.demand_rfo.l3_hit.snoop_hitm cache Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified event=0x2a,period=100003,umask=1,offcore_rsp=0x10003C0002  00    Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified. Available PDIST counters: 0 ocr.demand_rfo.l3_hit.snoop_hit_no_fwd cache Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0002  00    Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. Available PDIST counters: 0 ocr.demand_rfo.l3_hit.snoop_hit_with_fwd cache Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0002  00    Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. Available PDIST counters: 0 ocr.reads_to_core.l3_hit cache Counts all data read, code read, RFO and ITOM requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches event=0x2a,period=100003,umask=1,offcore_rsp=0x1F803C4477  00    Counts all data read, code read, RFO and ITOM requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches. Available PDIST counters: 0 ocr.swpf_rd.any_response cache Counts L1 data cache software prefetches which include T0/T1/T2 and NTA (except PREFETCHW) that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x14000  00    Counts L1 data cache software prefetches which include T0/T1/T2 and NTA (except PREFETCHW) that have any type of response. Available PDIST counters: 0 ocr.swpf_rd.l3_hit cache Counts L1 data cache software prefetches which include T0/T1/T2 and NTA (except PREFETCHW) that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x1F803C4000  00    Counts L1 data cache software prefetches which include T0/T1/T2 and NTA (except PREFETCHW) that were supplied by the L3 cache. Available PDIST counters: 0 ocr.swpf_rd.l3_hit.snoop_hitm cache Counts L1 data cache software prefetches which include T0/T1/T2 and NTA (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C4000  00    Counts L1 data cache software prefetches which include T0/T1/T2 and NTA (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. Available PDIST counters: 0 ocr.swpf_rd.l3_hit.snoop_hit_no_fwd cache Counts L1 data cache software prefetches which include T0/T1/T2 and NTA (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C4000  00    Counts L1 data cache software prefetches which include T0/T1/T2 and NTA (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. Available PDIST counters: 0 ocr.swpf_rd.l3_hit.snoop_hit_with_fwd cache Counts L1 data cache software prefetches which include T0/T1/T2 and NTA (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C4000  00    Counts L1 data cache software prefetches which include T0/T1/T2 and NTA (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. Available PDIST counters: 0 offcore_requests.all_requests cache OFFCORE_REQUESTS.ALL_REQUESTS event=0x21,period=100003,umask=0x80  00     offcore_requests.data_rd cache Demand and prefetch data reads event=0x21,period=100003,umask=8  00    Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type offcore_requests.demand_code_rd cache Cacheable and noncacheable code read requests event=0x21,period=100003,umask=2  00    Counts both cacheable and non-cacheable code read requests offcore_requests.demand_data_rd cache Demand Data Read requests sent to uncore event=0x21,period=100003,umask=1  00    Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore offcore_requests.demand_rfo cache Demand RFO requests including regular RFOs, locks, ItoM event=0x21,period=100003,umask=4  00    Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM offcore_requests_outstanding.all_data_rd cache This event is deprecated. Refer to new event OFFCORE_REQUESTS_OUTSTANDING.DATA_RD  Spec update: ADL038 event=0x20,period=1000003,umask=8  10     offcore_requests_outstanding.cycles_with_data_rd cache OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD  Spec update: ADL038 event=0x20,cmask=1,period=1000003,umask=8  00     offcore_requests_outstanding.cycles_with_demand_code_rd cache Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore event=0x20,cmask=1,period=1000003,umask=2  00    Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.cycles_with_demand_data_rd cache Cycles where at least 1 outstanding demand data read request is pending event=0x20,cmask=1,period=2000003,umask=1  00     offcore_requests_outstanding.cycles_with_demand_rfo cache Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore event=0x20,cmask=1,period=1000003,umask=4  00    Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.data_rd cache OFFCORE_REQUESTS_OUTSTANDING.DATA_RD  Spec update: ADL038 event=0x20,period=1000003,umask=8  00     offcore_requests_outstanding.demand_code_rd cache Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle event=0x20,period=1000003,umask=2  00    Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.demand_data_rd cache For every cycle, increments by the number of outstanding demand data read requests pending event=0x20,period=1000003,umask=1  00    For every cycle, increments by the number of outstanding demand data read requests pending.   Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor sq_misc.bus_lock cache Counts bus locks, accounts for cache line split locks and UC locks event=0x2c,period=100003,umask=0x10  00    Counts the more expensive bus lock needed to enforce cache coherency for certain memory accesses that need to be done atomically.  Can be created by issuing an atomic instruction (via the LOCK prefix) which causes a cache line split or accesses uncacheable memory sw_prefetch_access.any cache Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed event=0x40,period=100003,umask=0xf  00     sw_prefetch_access.nta cache Number of PREFETCHNTA instructions executed event=0x40,period=100003,umask=1  00    Counts the number of PREFETCHNTA instructions executed sw_prefetch_access.prefetchw cache Number of PREFETCHW instructions executed event=0x40,period=100003,umask=8  00    Counts the number of PREFETCHW instructions executed sw_prefetch_access.t0 cache Number of PREFETCHT0 instructions executed event=0x40,period=100003,umask=2  00    Counts the number of PREFETCHT0 instructions executed sw_prefetch_access.t1_t2 cache Number of PREFETCHT1 or PREFETCHT2 instructions executed event=0x40,period=100003,umask=4  00    Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed topdown_fe_bound.icache cache Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses event=0x71,period=1000003,umask=0x20  00     arith.fpdiv_active floating point Counts the number of cycles the floating point divider is in the loop stage event=0xcd,period=1000003,umask=2  00     arith.fpdiv_active floating point ARITH.FPDIV_ACTIVE event=0xb0,cmask=1,period=1000003,umask=1  00     arith.fpdiv_uops floating point Counts the number of floating point divider uops executed per cycle event=0xcd,period=1000003,umask=8  00     assists.fp floating point Counts all microcode FP assists event=0xc1,period=100003,umask=2  00    Counts all microcode Floating Point assists assists.sse_avx_mix floating point ASSISTS.SSE_AVX_MIX event=0xc1,period=1000003,umask=0x10  00     fp_arith_dispatched.port_0 floating point FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0] event=0xb3,period=2000003,umask=1  00     fp_arith_dispatched.port_1 floating point FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1] event=0xb3,period=2000003,umask=2  00     fp_arith_dispatched.port_5 floating point FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2] event=0xb3,period=2000003,umask=4  00     fp_arith_dispatched.v0 floating point FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0] event=0xb3,period=2000003,umask=1  00     fp_arith_dispatched.v1 floating point FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1] event=0xb3,period=2000003,umask=2  00     fp_arith_dispatched.v2 floating point FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5] event=0xb3,period=2000003,umask=4  00     fp_arith_inst_retired.128b_packed_double floating point Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=4  00    Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.128b_packed_single floating point Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=8  00    Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.256b_packed_double floating point Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=0x10  00    Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.256b_packed_single floating point Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=0x20  00    Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.4_flops floating point Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below.  Each count represents 2 or/and 4 computation operations, 1 for each element.  Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=0x18  00    Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision  floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 or/and 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.scalar floating point Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below.  Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element event=0xc7,period=1000003,umask=3  00    Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.scalar_double floating point Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=1  00    Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.scalar_single floating point Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=2  00    Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.vector floating point Number of any Vector retired FP arithmetic instructions event=0xc7,period=1000003,umask=0xfc  00    Number of any Vector retired FP arithmetic instructions.  The DAZ and FTZ flags in the MXCSR register need to be set when using these events machine_clears.fp_assist floating point Counts the number of floating point operations retired that required microcode assist event=0xc3,period=20003,umask=4  00    Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops uops_retired.fpdiv floating point Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt) event=0xc2,period=2000003,umask=8  00     baclears.any frontend Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches event=0xe6,period=100003,umask=1  00    Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend.  Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches baclears.any frontend Clears due to Unknown Branches event=0x60,period=100003,umask=1  00    Number of times the front-end is resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch which occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore decode.lcp frontend Stalls caused by changing prefix length of the instruction event=0x87,period=500009,umask=1  00    Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk decode.ms_busy frontend Cycles the Microcode Sequencer is busy event=0x87,period=500009,umask=2  00     dsb2mite_switches.penalty_cycles frontend DSB-to-MITE switch true penalty cycles event=0x61,period=100003,umask=2  00    Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE frontend_retired.any_dsb_miss frontend Retired Instructions who experienced DSB miss event=0xc6,period=100007,umask=1,frontend=0x1  00    Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Available PDIST counters: 0 frontend_retired.dsb_miss frontend Retired Instructions who experienced a critical DSB miss event=0xc6,period=100007,umask=1,frontend=0x11  00    Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss. Available PDIST counters: 0 frontend_retired.itlb_miss frontend Retired Instructions who experienced iTLB true miss event=0xc6,period=100007,umask=1,frontend=0x14  00    Counts retired Instructions that experienced iTLB (Instruction TLB) true miss. Available PDIST counters: 0 frontend_retired.l1i_miss frontend Retired Instructions who experienced Instruction L1 Cache true miss event=0xc6,period=100007,umask=1,frontend=0x12  00    Counts retired Instructions who experienced Instruction L1 Cache true miss. Available PDIST counters: 0 frontend_retired.l2_miss frontend Retired Instructions who experienced Instruction L2 Cache true miss event=0xc6,period=100007,umask=1,frontend=0x13  00    Counts retired Instructions who experienced Instruction L2 Cache true miss. Available PDIST counters: 0 frontend_retired.latency_ge_1 frontend Retired instructions after front-end starvation of at least 1 cycle event=0xc6,period=100007,umask=1,frontend=0x600106  00    Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall. Available PDIST counters: 0 frontend_retired.latency_ge_128 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=1,frontend=0x608006  00    Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall. Available PDIST counters: 0 frontend_retired.latency_ge_16 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=1,frontend=0x601006  00    Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops. Available PDIST counters: 0 frontend_retired.latency_ge_2 frontend Retired instructions after front-end starvation of at least 2 cycles event=0xc6,period=100007,umask=1,frontend=0x600206  00    Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall. Available PDIST counters: 0 frontend_retired.latency_ge_256 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=1,frontend=0x610006  00    Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall. Available PDIST counters: 0 frontend_retired.latency_ge_2_bubbles_ge_1 frontend Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=1,frontend=0x100206  00    Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall. Available PDIST counters: 0 frontend_retired.latency_ge_32 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=1,frontend=0x602006  00    Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops. Available PDIST counters: 0 frontend_retired.latency_ge_4 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=1,frontend=0x600406  00    Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall. Available PDIST counters: 0 frontend_retired.latency_ge_512 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=1,frontend=0x620006  00    Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall. Available PDIST counters: 0 frontend_retired.latency_ge_64 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=1,frontend=0x604006  00    Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall. Available PDIST counters: 0 frontend_retired.latency_ge_8 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=1,frontend=0x600806  00    Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops. Available PDIST counters: 0 frontend_retired.ms_flows frontend FRONTEND_RETIRED.MS_FLOWS event=0xc6,period=100007,umask=1,frontend=0x8  00    FRONTEND_RETIRED.MS_FLOWS Available PDIST counters: 0 frontend_retired.stlb_miss frontend Retired Instructions who experienced STLB (2nd level TLB) true miss event=0xc6,period=100007,umask=1,frontend=0x15  00    Counts retired Instructions that experienced STLB (2nd level TLB) true miss. Available PDIST counters: 0 frontend_retired.unknown_branch frontend FRONTEND_RETIRED.UNKNOWN_BRANCH event=0xc6,period=100007,umask=1,frontend=0x17  00    FRONTEND_RETIRED.UNKNOWN_BRANCH Available PDIST counters: 0 icache.accesses frontend Counts the number of requests to the instruction cache for one or more bytes of a cache line event=0x80,period=200003,umask=3  00    Counts the total number of requests to the instruction cache.  The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line or byte chunk count as one.  Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line icache.misses frontend Counts the number of instruction cache misses event=0x80,period=200003,umask=2  00    Counts the number of missed requests to the instruction cache.  The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one.  Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line icache_data.stalls frontend Cycles where a code fetch is stalled due to L1 instruction cache miss event=0x80,period=500009,umask=4  00    Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The decode pipeline works at a 32 Byte granularity icache_data.stall_periods frontend ICACHE_DATA.STALL_PERIODS event=0x80,cmask=1,edge=1,period=500009,umask=4  00     icache_tag.stalls frontend Cycles where a code fetch is stalled due to L1 instruction cache tag miss event=0x83,period=200003,umask=4  00    Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss idq.dsb_cycles_any frontend Cycles Decode Stream Buffer (DSB) is delivering any Uop event=0x79,cmask=1,period=2000003,umask=8  00    Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path idq.dsb_cycles_ok frontend Cycles DSB is delivering optimal number of Uops event=0x79,cmask=6,period=2000003,umask=8  00    Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the DSB (Decode Stream Buffer) path. Count includes uops that may 'bypass' the IDQ idq.dsb_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path event=0x79,period=2000003,umask=8  00    Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path idq.mite_cycles_any frontend Cycles MITE is delivering any Uop event=0x79,cmask=1,period=2000003,umask=4  00    Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB) idq.mite_cycles_ok frontend Cycles MITE is delivering optimal number of Uops event=0x79,cmask=6,period=2000003,umask=4  00    Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB) idq.mite_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,period=2000003,umask=4  00    Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) idq.ms_cycles_any frontend Cycles when uops are being delivered to IDQ while MS is busy event=0x79,cmask=1,period=2000003,umask=0x20  00    Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE idq.ms_switches frontend Number of switches from DSB or MITE to the MS event=0x79,cmask=1,edge=1,period=100003,umask=0x20  00    Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer idq.ms_uops frontend Uops delivered to IDQ while MS is busy event=0x79,period=1000003,umask=0x20  00    Counts the total number of uops delivered by the Microcode Sequencer (MS) idq_bubbles.core frontend Uops not delivered by IDQ when backend of the machine is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CORE] event=0x9c,period=1000003,umask=1  00    Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CORE] idq_bubbles.cycles_0_uops_deliv.core frontend Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE] event=0x9c,cmask=6,period=1000003,umask=1  00    Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE] idq_bubbles.cycles_fe_was_ok frontend Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK] event=0x9c,cmask=1,inv=1,period=1000003,umask=1  00    Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK] idq_uops_not_delivered.core frontend Uops not delivered by IDQ when backend of the machine is not stalled [This event is alias to IDQ_BUBBLES.CORE] event=0x9c,period=1000003,umask=1  00    Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLES.CORE] idq_uops_not_delivered.cycles_0_uops_deliv.core frontend Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE] event=0x9c,cmask=6,period=1000003,umask=1  00    Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE] idq_uops_not_delivered.cycles_fe_was_ok frontend Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_FE_WAS_OK] event=0x9c,cmask=1,inv=1,period=1000003,umask=1  00    Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLES.CYCLES_FE_WAS_OK] cycle_activity.stalls_l3_miss memory Execution stalls while L3 cache miss demand load is outstanding event=0xa3,cmask=6,period=1000003,umask=6  00     ld_head.any_at_ret memory Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires event=5,period=1000003,umask=0xff  00     ld_head.l1_bound_at_ret memory Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring event=5,period=1000003,umask=0xf4  00     ld_head.l1_miss_at_ret memory Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss event=5,period=1000003,umask=0x81  00     ld_head.other_at_ret memory Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases event=5,period=1000003,umask=0xc0  00    Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases such as pipeline conflicts, fences, etc ld_head.pgwalk_at_ret memory Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk event=5,period=1000003,umask=0xa0  00     ld_head.st_addr_at_ret memory Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match event=5,period=1000003,umask=0x84  00     machine_clears.memory_ordering memory Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation event=0xc3,period=20003,umask=2  00     machine_clears.memory_ordering memory Number of machine clears due to memory ordering conflicts event=0xc3,period=100003,umask=2  00    Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture memory_activity.cycles_l1d_miss memory Cycles while L1 cache miss demand load is outstanding event=0x47,cmask=2,period=1000003,umask=2  00     memory_activity.stalls_l1d_miss memory Execution stalls while L1 cache miss demand load is outstanding event=0x47,cmask=3,period=1000003,umask=3  00     memory_activity.stalls_l2_miss memory Execution stalls while L2 cache miss demand cacheable load request is outstanding event=0x47,cmask=5,period=1000003,umask=5  00    Execution stalls while L2 cache miss demand cacheable load request is outstanding (will not count for uncacheable demand requests e.g. bus lock) memory_activity.stalls_l3_miss memory Execution stalls while L3 cache miss demand cacheable load request is outstanding event=0x47,cmask=9,period=1000003,umask=9  00    Execution stalls while L3 cache miss demand cacheable load request is outstanding (will not count for uncacheable demand requests e.g. bus lock) mem_trans_retired.load_latency_gt_1024 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles  Supports address when precise event=0xcd,period=53,umask=1,ldlat=0x400  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise mem_trans_retired.load_latency_gt_128 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles  Supports address when precise event=0xcd,period=1009,umask=1,ldlat=0x80  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise mem_trans_retired.load_latency_gt_16 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles  Supports address when precise event=0xcd,period=20011,umask=1,ldlat=0x10  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise mem_trans_retired.load_latency_gt_256 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles  Supports address when precise event=0xcd,period=503,umask=1,ldlat=0x100  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise mem_trans_retired.load_latency_gt_32 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles  Supports address when precise event=0xcd,period=100007,umask=1,ldlat=0x20  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise mem_trans_retired.load_latency_gt_4 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles  Supports address when precise event=0xcd,period=100003,umask=1,ldlat=0x4  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise mem_trans_retired.load_latency_gt_512 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles  Supports address when precise event=0xcd,period=101,umask=1,ldlat=0x200  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise mem_trans_retired.load_latency_gt_64 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles  Supports address when precise event=0xcd,period=2003,umask=1,ldlat=0x40  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise mem_trans_retired.load_latency_gt_8 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles  Supports address when precise event=0xcd,period=50021,umask=1,ldlat=0x8  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise mem_trans_retired.store_sample memory Retired memory store access operations. A PDist event for PEBS Store Latency Facility  Supports address when precise event=0xcd,period=1000003,umask=2  00    Counts Retired memory accesses with at least 1 store operation. This PEBS event is the precisely-distributed (PDist) trigger covering all stores uops for sampling by the PEBS Store Latency Facility. The facility is described in Intel SDM Volume 3 section 19.9.8 Available PDIST counters: 0  Supports address when precise ocr.demand_code_rd.dram memory Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x784000004  00    Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM. Available PDIST counters: 0 ocr.demand_code_rd.l3_miss memory Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84400004  00    Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.demand_data_rd.dram memory Counts demand data reads that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x784000001  00    Counts demand data reads that were supplied by DRAM. Available PDIST counters: 0 ocr.demand_data_rd.dram memory Counts demand data reads that were supplied by DRAM event=0x2a,period=100003,umask=1,offcore_rsp=0x184000001  00    Counts demand data reads that were supplied by DRAM. Available PDIST counters: 0 ocr.demand_data_rd.l3_miss memory Counts demand data reads that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84400001  00    Counts demand data reads that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.demand_data_rd.l3_miss memory Counts demand data reads that were not supplied by the L3 cache event=0x2a,period=100003,umask=1,offcore_rsp=0x3FBFC00001  00    Counts demand data reads that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.demand_data_rd.l3_miss_local memory Counts demand data reads that were not supplied by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS] event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84400001  00    Counts demand data reads that were not supplied by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS] Available PDIST counters: 0 ocr.demand_rfo.dram memory Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x784000002  00    Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM. Available PDIST counters: 0 ocr.demand_rfo.l3_miss memory Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84400002  00    Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.demand_rfo.l3_miss memory Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache event=0x2a,period=100003,umask=1,offcore_rsp=0x3FBFC00002  00    Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.demand_rfo.l3_miss_local memory Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS] event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84400002  00    Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS] Available PDIST counters: 0 ocr.swpf_rd.dram memory Counts L1 data cache software prefetches which include T0/T1/T2 and NTA (except PREFETCHW) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x784004000  00    Counts L1 data cache software prefetches which include T0/T1/T2 and NTA (except PREFETCHW) that were supplied by DRAM. Available PDIST counters: 0 ocr.swpf_rd.l3_miss memory Counts L1 data cache software prefetches which include T0/T1/T2 and NTA (except PREFETCHW) that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84404000  00    Counts L1 data cache software prefetches which include T0/T1/T2 and NTA (except PREFETCHW) that were not supplied by the L3 cache. Available PDIST counters: 0 offcore_requests.l3_miss_demand_data_rd memory Counts demand data read requests that miss the L3 cache event=0x21,period=100003,umask=0x10  00     offcore_requests_outstanding.l3_miss_demand_data_rd memory For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache event=0x20,period=2000003,umask=0x10  00    For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache.  Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known by the requesting core to have missed the L3 cache assists.hardware other Count all other hardware assists or traps that are not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and A/D assists who are counted by dedicated sub-events. the event also counts for Machine Ordering count event=0xc1,period=100003,umask=4  00    Count all other hardware assists or traps that are not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and A/D assists who are counted by dedicated sub-events.  This includes, but not limited to, assists at EXE or MEM uop writeback like AVX* load/store/gather/scatter (non-FP GSSE-assist ) , assists generated by ROB like PEBS and RTIT, Uncore trap, RAR (Remote Action Request) and CET (Control flow Enforcement Technology) assists. the event also counts for Machine Ordering count assists.page_fault other ASSISTS.PAGE_FAULT event=0xc1,period=1000003,umask=8  00     core_power.license_1 other CORE_POWER.LICENSE_1 event=0x28,period=200003,umask=2  00     core_power.license_2 other CORE_POWER.LICENSE_2 event=0x28,period=200003,umask=4  00     core_power.license_3 other CORE_POWER.LICENSE_3 event=0x28,period=200003,umask=8  00     lbr_inserts.any other This event is deprecated. [This event is alias to MISC_RETIRED.LBR_INSERTS] event=0xe4,period=1000003,umask=1  10     ocr.full_streaming_wr.any_response other Counts streaming stores which modify a full 64 byte cacheline that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x800000010000  00    Counts streaming stores which modify a full 64 byte cacheline that have any type of response. Available PDIST counters: 0 ocr.partial_streaming_wr.any_response other Counts streaming stores which modify only part of a 64 byte cacheline that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x400000010000  00    Counts streaming stores which modify only part of a 64 byte cacheline that have any type of response. Available PDIST counters: 0 ocr.streaming_wr.any_response other Counts streaming stores that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10800  00    Counts streaming stores that have any type of response. Available PDIST counters: 0 ocr.streaming_wr.any_response other Counts streaming stores that have any type of response event=0x2a,period=100003,umask=1,offcore_rsp=0x10800  00    Counts streaming stores that have any type of response. Available PDIST counters: 0 xq.full_cycles other Cycles the uncore cannot take further requests event=0x2d,cmask=1,period=1000003,umask=1  00    number of cycles when the thread is active and the uncore cannot take any further requests (for example prefetches, loads or stores initiated by the Core that miss the L2 cache) arith.divider_active pipeline This event is deprecated. Refer to new event ARITH.DIV_ACTIVE event=0xb0,cmask=1,period=1000003,umask=9  10     arith.div_active pipeline Counts the number of cycles when any of the floating point or integer dividers are active event=0xcd,cmask=1,period=1000003,umask=3  00     arith.div_active pipeline Cycles when divide unit is busy executing divide or square root operations event=0xb0,cmask=1,period=1000003,umask=9  00    Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations arith.div_occupancy pipeline This event is deprecated event=0xcd,period=1000003,umask=3  10     arith.div_uops pipeline This event is deprecated event=0xcd,period=1000003,umask=0xc  10     arith.fp_divider_active pipeline This event is deprecated. Refer to new event ARITH.FPDIV_ACTIVE event=0xb0,cmask=1,period=1000003,umask=1  10     arith.idiv_active pipeline Counts the number of cycles any of the two integer dividers are active event=0xcd,cmask=1,period=1000003,umask=1  00     arith.idiv_active pipeline This event counts the cycles the integer divider is busy event=0xb0,cmask=1,period=1000003,umask=8  00     arith.idiv_occupancy pipeline Counts the number of active integer dividers per cycle event=0xcd,period=1000003,umask=1  00     arith.idiv_uops pipeline Counts the number of integer divider uops executed per cycle event=0xcd,period=1000003,umask=4  00     arith.int_divider_active pipeline This event is deprecated. Refer to new event ARITH.IDIV_ACTIVE event=0xb0,cmask=1,period=1000003,umask=8  10     assists.any pipeline Number of occurrences where a microcode assist is invoked by hardware event=0xc1,period=100003,umask=0x1b  00    Counts the number of occurrences where a microcode assist is invoked by hardware. Examples include AD (page Access Dirty), FP and AVX related assists br_inst_retired.all_branches pipeline Counts the total number of branch instructions retired for all branch types event=0xc4,period=200003  00    Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires.  All branch type instructions are accounted for br_inst_retired.all_branches pipeline All branch instructions retired event=0xc4,period=400009  00    Counts all branch instructions retired. Available PDIST counters: 0 br_inst_retired.call pipeline This event is deprecated. Refer to new event BR_INST_RETIRED.NEAR_CALL event=0xc4,period=200003,umask=0xf9  10     br_inst_retired.cond pipeline Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches event=0xc4,period=200003,umask=0x7e  00     br_inst_retired.cond pipeline Conditional branch instructions retired event=0xc4,period=400009,umask=0x11  00    Counts conditional branch instructions retired. Available PDIST counters: 0 br_inst_retired.cond_ntaken pipeline Not taken branch instructions retired event=0xc4,period=400009,umask=0x10  00    Counts not taken branch instructions retired. Available PDIST counters: 0 br_inst_retired.cond_taken pipeline Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired event=0xc4,period=200003,umask=0xfe  00     br_inst_retired.cond_taken pipeline Taken conditional branch instructions retired event=0xc4,period=400009,umask=1  00    Counts taken conditional branch instructions retired. Available PDIST counters: 0 br_inst_retired.far_branch pipeline Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return event=0xc4,period=200003,umask=0xbf  00     br_inst_retired.far_branch pipeline Far branch instructions retired event=0xc4,period=100007,umask=0x40  00    Counts far branch instructions retired. Available PDIST counters: 0 br_inst_retired.indirect pipeline Counts the number of near indirect JMP and near indirect CALL branch instructions retired event=0xc4,period=200003,umask=0xeb  00     br_inst_retired.indirect pipeline Indirect near branch instructions retired (excluding returns) event=0xc4,period=100003,umask=0x80  00    Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch. Available PDIST counters: 0 br_inst_retired.indirect_call pipeline Counts the number of near indirect CALL branch instructions retired event=0xc4,period=200003,umask=0xfb  00     br_inst_retired.ind_call pipeline This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT_CALL event=0xc4,period=200003,umask=0xfb  10     br_inst_retired.jcc pipeline This event is deprecated. Refer to new event BR_INST_RETIRED.COND event=0xc4,period=200003,umask=0x7e  10     br_inst_retired.near_call pipeline Counts the number of near CALL branch instructions retired event=0xc4,period=200003,umask=0xf9  00     br_inst_retired.near_call pipeline Direct and indirect near call instructions retired event=0xc4,period=100007,umask=2  00    Counts both direct and indirect near call instructions retired. Available PDIST counters: 0 br_inst_retired.near_return pipeline Counts the number of near RET branch instructions retired event=0xc4,period=200003,umask=0xf7  00     br_inst_retired.near_return pipeline Return instructions retired event=0xc4,period=100007,umask=8  00    Counts return instructions retired. Available PDIST counters: 0 br_inst_retired.near_taken pipeline Counts the number of near taken branch instructions retired event=0xc4,period=200003,umask=0xc0  00     br_inst_retired.near_taken pipeline Taken branch instructions retired event=0xc4,period=400009,umask=0x20  00    Counts taken branch instructions retired. Available PDIST counters: 0 br_inst_retired.non_return_ind pipeline This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT event=0xc4,period=200003,umask=0xeb  10     br_inst_retired.rel_call pipeline Counts the number of near relative CALL branch instructions retired event=0xc4,period=200003,umask=0xfd  00     br_inst_retired.return pipeline This event is deprecated. Refer to new event BR_INST_RETIRED.NEAR_RETURN event=0xc4,period=200003,umask=0xf7  10     br_inst_retired.taken_jcc pipeline This event is deprecated. Refer to new event BR_INST_RETIRED.COND_TAKEN event=0xc4,period=200003,umask=0xfe  10     br_misp_retired.all_branches pipeline Counts the total number of mispredicted branch instructions retired for all branch types event=0xc5,period=200003  00    Counts the total number of mispredicted branch instructions retired.  All branch type instructions are accounted for.  Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP.    A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path br_misp_retired.all_branches pipeline All mispredicted branch instructions retired event=0xc5,period=400009  00    Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch.  When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path. Available PDIST counters: 0 br_misp_retired.cond pipeline Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired event=0xc5,period=200003,umask=0x7e  00     br_misp_retired.cond pipeline Mispredicted conditional branch instructions retired event=0xc5,period=400009,umask=0x11  00    Counts mispredicted conditional branch instructions retired. Available PDIST counters: 0 br_misp_retired.cond_ntaken pipeline Mispredicted non-taken conditional branch instructions retired event=0xc5,period=400009,umask=0x10  00    Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken. Available PDIST counters: 0 br_misp_retired.cond_taken pipeline Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired event=0xc5,period=200003,umask=0xfe  00     br_misp_retired.cond_taken pipeline number of branch instructions retired that were mispredicted and taken event=0xc5,period=400009,umask=1  00    Counts taken conditional mispredicted branch instructions retired. Available PDIST counters: 0 br_misp_retired.indirect pipeline Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired event=0xc5,period=200003,umask=0xeb  00     br_misp_retired.indirect pipeline Miss-predicted near indirect branch instructions retired (excluding returns) event=0xc5,period=100003,umask=0x80  00    Counts miss-predicted near indirect branch instructions retired excluding returns. TSX abort is an indirect branch. Available PDIST counters: 0 br_misp_retired.indirect_call pipeline Counts the number of mispredicted near indirect CALL branch instructions retired event=0xc5,period=200003,umask=0xfb  00     br_misp_retired.indirect_call pipeline Mispredicted indirect CALL retired event=0xc5,period=400009,umask=2  00    Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect. Available PDIST counters: 0 br_misp_retired.ind_call pipeline This event is deprecated. Refer to new event BR_MISP_RETIRED.INDIRECT_CALL event=0xc5,period=200003,umask=0xfb  10     br_misp_retired.jcc pipeline This event is deprecated. Refer to new event BR_MISP_RETIRED.COND event=0xc5,period=200003,umask=0x7e  10     br_misp_retired.near_taken pipeline Counts the number of mispredicted near taken branch instructions retired event=0xc5,period=200003,umask=0x80  00     br_misp_retired.near_taken pipeline Number of near branch instructions retired that were mispredicted and taken event=0xc5,period=400009,umask=0x20  00    Counts number of near branch instructions retired that were mispredicted and taken. Available PDIST counters: 0 br_misp_retired.non_return_ind pipeline This event is deprecated. Refer to new event BR_MISP_RETIRED.INDIRECT event=0xc5,period=200003,umask=0xeb  10     br_misp_retired.ret pipeline This event counts the number of mispredicted ret instructions retired. Non PEBS event=0xc5,period=100007,umask=8  00    This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired. Available PDIST counters: 0 br_misp_retired.return pipeline Counts the number of mispredicted near RET branch instructions retired event=0xc5,period=200003,umask=0xf7  00     br_misp_retired.taken_jcc pipeline This event is deprecated. Refer to new event BR_MISP_RETIRED.COND_TAKEN event=0xc5,period=200003,umask=0xfe  10     cpu_clk_unhalted.c01 pipeline Core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state event=0xec,period=2000003,umask=0x10  00    Counts core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state.  This state can be entered via the TPAUSE or UMWAIT instructions cpu_clk_unhalted.c02 pipeline Core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state event=0xec,period=2000003,umask=0x20  00    Counts core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state.  This state can be entered via the TPAUSE or UMWAIT instructions cpu_clk_unhalted.c0_wait pipeline Core clocks when the thread is in the C0.1 or C0.2 or running a PAUSE in C0 ACPI state event=0xec,period=2000003,umask=0x70  00    Counts core clocks when the thread is in the C0.1 or C0.2 power saving optimized states (TPAUSE or UMWAIT instructions) or running the PAUSE instruction cpu_clk_unhalted.core pipeline Counts the number of unhalted core clock cycles. (Fixed event) event=0x3c,period=2000003  00    Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1 cpu_clk_unhalted.core_p pipeline Counts the number of unhalted core clock cycles event=0x3c,period=2000003  00    Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter cpu_clk_unhalted.distributed pipeline Cycle counts are evenly distributed between active threads in the Core event=0xec,period=2000003,umask=2  00    This event distributes cycle counts between active hyperthreads, i.e., those in C0.  A hyperthread becomes inactive when it executes the HLT or MWAIT instructions.  If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread cpu_clk_unhalted.one_thread_active pipeline Core crystal clock cycles when this thread is unhalted and the other thread is halted event=0x3c,period=25003,umask=2  00    Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted cpu_clk_unhalted.pause pipeline CPU_CLK_UNHALTED.PAUSE event=0xec,period=2000003,umask=0x40  00     cpu_clk_unhalted.pause_inst pipeline CPU_CLK_UNHALTED.PAUSE_INST event=0xec,cmask=1,edge=1,period=2000003,umask=0x40  00     cpu_clk_unhalted.ref pipeline This event is deprecated. Refer to new event CPU_CLK_UNHALTED.REF_TSC_P event=0x0,umask=0x03,period=2000003  10     cpu_clk_unhalted.ref_distributed pipeline Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core event=0x3c,period=2000003,umask=8  00    This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread cpu_clk_unhalted.ref_tsc pipeline Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event) event=0,period=2000003,umask=3  00    Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2 cpu_clk_unhalted.ref_tsc pipeline Reference cycles when the core is not in halt state event=0,period=2000003,umask=3  00    Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case cpu_clk_unhalted.ref_tsc_p pipeline Counts the number of unhalted reference clock cycles at TSC frequency event=0x3c,period=2000003,umask=1  00    Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter cpu_clk_unhalted.ref_tsc_p pipeline Reference cycles when the core is not in halt state event=0x3c,period=2000003,umask=1  00    Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case cpu_clk_unhalted.thread pipeline Counts the number of unhalted core clock cycles. (Fixed event) event=0x3c,period=2000003  00    Counts the number of core cycles while the core is not in a halt state.  The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time.  This event uses fixed counter 1 cpu_clk_unhalted.thread pipeline Core cycles when the thread is not in halt state event=0x3c,period=2000003  00    Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events cpu_clk_unhalted.thread_p pipeline Counts the number of unhalted core clock cycles event=0x3c,period=2000003  00    Counts the number of core cycles while the core is not in a halt state.  The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter cpu_clk_unhalted.thread_p pipeline Thread cycles when thread is not in halt state event=0x3c,period=2000003  00    This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time cycle_activity.cycles_l1d_miss pipeline Cycles while L1 cache miss demand load is outstanding event=0xa3,cmask=8,period=1000003,umask=8  00     cycle_activity.cycles_l2_miss pipeline Cycles while L2 cache miss demand load is outstanding event=0xa3,cmask=1,period=1000003,umask=1  00     cycle_activity.cycles_mem_any pipeline Cycles while memory subsystem has an outstanding load event=0xa3,cmask=16,period=1000003,umask=0x10  00     cycle_activity.stalls_l1d_miss pipeline Execution stalls while L1 cache miss demand load is outstanding event=0xa3,cmask=12,period=1000003,umask=0xc  00     cycle_activity.stalls_l2_miss pipeline Execution stalls while L2 cache miss demand load is outstanding event=0xa3,cmask=5,period=1000003,umask=5  00     cycle_activity.stalls_total pipeline Total execution stalls event=0xa3,cmask=4,period=1000003,umask=4  00     exe_activity.1_ports_util pipeline Cycles total of 1 uop is executed on all ports and Reservation Station was not empty event=0xa6,period=2000003,umask=2  00    Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty exe_activity.2_3_ports_util pipeline Cycles total of 2 or 3 uops are executed on all ports and Reservation Station (RS) was not empty event=0xa6,period=2000003,umask=0xc  00     exe_activity.2_ports_util pipeline Cycles total of 2 uops are executed on all ports and Reservation Station was not empty event=0xa6,period=2000003,umask=4  00    Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty exe_activity.3_ports_util pipeline Cycles total of 3 uops are executed on all ports and Reservation Station was not empty event=0xa6,period=2000003,umask=8  00    Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty exe_activity.4_ports_util pipeline Cycles total of 4 uops are executed on all ports and Reservation Station was not empty event=0xa6,period=2000003,umask=0x10  00    Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty exe_activity.bound_on_loads pipeline Execution stalls while memory subsystem has an outstanding load event=0xa6,cmask=5,period=2000003,umask=0x21  00     exe_activity.bound_on_stores pipeline Cycles where the Store Buffer was full and no loads caused an execution stall event=0xa6,cmask=2,period=1000003,umask=0x40  00    Counts cycles where the Store Buffer was full and no loads caused an execution stall exe_activity.exe_bound_0_ports pipeline Cycles no uop executed while RS was not empty, the SB was not full and there was no outstanding load event=0xa6,period=1000003,umask=0x80  00    Number of cycles total of 0 uops executed on all ports, Reservation Station (RS) was not empty, the Store Buffer (SB) was not full and there was no outstanding load inst_decoded.decoders pipeline Instruction decoders utilized in a cycle event=0x75,period=2000003,umask=1  00    Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions inst_retired.any pipeline Counts the total number of instructions retired. (Fixed event) event=0xc0,period=2000003  00    Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. Available PDIST counters: 32 inst_retired.any pipeline Number of instructions retired. Fixed Counter - architectural event event=0xc0,period=2000003  00    Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter. Available PDIST counters: 32 inst_retired.any_p pipeline Counts the total number of instructions retired event=0xc0,period=2000003  00    Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses a programmable general purpose performance counter inst_retired.any_p pipeline Number of instructions retired. General Counter - architectural event event=0xc0,period=2000003  00    Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter inst_retired.macro_fused pipeline INST_RETIRED.MACRO_FUSED event=0xc0,period=2000003,umask=0x10  00     inst_retired.nop pipeline Retired NOP instructions event=0xc0,period=2000003,umask=2  00    Counts all retired NOP or ENDBR32/64 instructions inst_retired.prec_dist pipeline Precise instruction retired with PEBS precise-distribution event=0,period=2000003,umask=1  00    A version of INST_RETIRED that allows for a precise distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR++) feature to fix bias in how retired instructions get sampled. Use on Fixed Counter 0. Available PDIST counters: 32 inst_retired.rep_iteration pipeline Iterations of Repeat string retired instructions event=0xc0,period=2000003,umask=8  00    Number of iterations of Repeat (REP) string retired instructions such as MOVS, CMPS, and SCAS. Each has a byte, word, and doubleword version and string instructions can be repeated using a repetition prefix, REP, that allows their architectural execution to be repeated a number of times as specified by the RCX register. Note the number of iterations is implementation-dependent int_misc.clears_count pipeline Clears speculative count event=0xad,cmask=1,edge=1,period=500009,umask=1  00    Counts the number of speculative clears due to any type of branch misprediction or machine clears int_misc.clear_resteer_cycles pipeline Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path event=0xad,period=500009,umask=0x80  00    Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path int_misc.recovery_cycles pipeline Core cycles the allocator was stalled due to recovery from earlier clear event for this thread event=0xad,period=500009,umask=1  00    Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event int_misc.unknown_branch_cycles pipeline Bubble cycles of BAClear (Unknown Branch) event=0xad,period=1000003,umask=0x40,frontend=0x7  00     int_misc.uop_dropping pipeline TMA slots where uops got dropped event=0xad,period=1000003,umask=0x10  00    Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons int_vec_retired.128bit pipeline INT_VEC_RETIRED.128BIT event=0xe7,period=1000003,umask=0x13  00     int_vec_retired.256bit pipeline INT_VEC_RETIRED.256BIT event=0xe7,period=1000003,umask=0xac  00     int_vec_retired.add_128 pipeline integer ADD, SUB, SAD 128-bit vector instructions event=0xe7,period=1000003,umask=3  00    Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vector instructions int_vec_retired.add_256 pipeline integer ADD, SUB, SAD 256-bit vector instructions event=0xe7,period=1000003,umask=0xc  00    Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vector instructions int_vec_retired.mul_256 pipeline INT_VEC_RETIRED.MUL_256 event=0xe7,period=1000003,umask=0x80  00     int_vec_retired.shuffles pipeline INT_VEC_RETIRED.SHUFFLES event=0xe7,period=1000003,umask=0x40  00     int_vec_retired.vnni_128 pipeline INT_VEC_RETIRED.VNNI_128 event=0xe7,period=1000003,umask=0x10  00     int_vec_retired.vnni_256 pipeline INT_VEC_RETIRED.VNNI_256 event=0xe7,period=1000003,umask=0x20  00     ld_blocks.4k_alias pipeline This event is deprecated. Refer to new event LD_BLOCKS.ADDRESS_ALIAS event=3,period=1000003,umask=4  10     ld_blocks.address_alias pipeline Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check event=3,period=1000003,umask=4  00     ld_blocks.address_alias pipeline False dependencies in MOB due to partial compare on address event=3,period=100003,umask=4  00    Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on address ld_blocks.data_unknown pipeline Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready event=3,period=1000003,umask=1  00     ld_blocks.no_sr pipeline The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use event=3,period=100003,umask=0x88  00    Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use ld_blocks.store_forward pipeline Loads blocked due to overlapping with a preceding store that cannot be forwarded event=3,period=100003,umask=0x82  00    Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide load_hit_prefetch.swpf pipeline Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch event=0x4c,period=100003,umask=1  00    Counts all software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions lsd.cycles_active pipeline Cycles Uops delivered by the LSD, but didn't come from the decoder event=0xa8,cmask=1,period=2000003,umask=1  00    Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector) lsd.cycles_ok pipeline Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder event=0xa8,cmask=6,period=2000003,umask=1  00    Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector) lsd.uops pipeline Number of Uops delivered by the LSD event=0xa8,period=2000003,umask=1  00    Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector) machine_clears.count pipeline Number of machine clears (nukes) of any type event=0xc3,cmask=1,edge=1,period=100003,umask=1  00    Counts the number of machine clears (nukes) of any type machine_clears.disambiguation pipeline Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU event=0xc3,period=20003,umask=8  00     machine_clears.mrn_nuke pipeline Counts the number of machines clears due to memory renaming event=0xc3,period=1000003,umask=0x80  00     machine_clears.page_fault pipeline Counts the number of machine clears due to a page fault.  Counts both I-Side and D-Side (Loads/Stores) page faults.  A page fault occurs when either the page is not present, or an access violation occurs event=0xc3,period=20003,umask=0x20  00     machine_clears.slow pipeline This event is deprecated event=0xc3,period=20003,umask=0x6f  10     machine_clears.smc pipeline Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page event=0xc3,period=20003,umask=1  00     machine_clears.smc pipeline Self-modifying code (SMC) detected event=0xc3,period=100003,umask=4  00    Counts self-modifying code (SMC) detected, which causes a machine clear misc2_retired.lfence pipeline LFENCE instructions retired event=0xe0,period=400009,umask=0x20  00    number of LFENCE retired instructions misc_retired.lbr_inserts pipeline Counts the number of LBR entries recorded. Requires LBRs to be enabled in IA32_LBR_CTL. [This event is alias to LBR_INSERTS.ANY] event=0xe4,period=1000003,umask=1  00    Counts the number of LBR entries recorded. Requires LBRs to be enabled in IA32_LBR_CTL. This event is PDIR on GP0 and NPEBS on all other GPs [This event is alias to LBR_INSERTS.ANY] misc_retired.lbr_inserts pipeline Increments whenever there is an update to the LBR array event=0xcc,period=100003,umask=0x20  00    Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT resource_stalls.sb pipeline Cycles stalled due to no store buffers available. (not including draining form sync) event=0xa2,period=100003,umask=8  00    Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end resource_stalls.scoreboard pipeline Counts cycles where the pipeline is stalled due to serializing operations event=0xa2,period=100003,umask=2  00     rs.empty pipeline Cycles when Reservation Station (RS) is empty for the thread event=0xa5,period=1000003,umask=7  00    Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses) rs.empty_count pipeline Counts end of periods where the Reservation Station (RS) was empty event=0xa5,cmask=1,edge=1,inv=1,period=100003,umask=7  00    Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events) rs.empty_resource pipeline Cycles when Reservation Station (RS) is empty due to a resource in the back-end event=0xa5,period=1000003,umask=1  00     rs_empty.count pipeline This event is deprecated. Refer to new event RS.EMPTY_COUNT event=0xa5,cmask=1,edge=1,inv=1,period=100003,umask=7  10     rs_empty.cycles pipeline This event is deprecated. Refer to new event RS.EMPTY event=0xa5,period=1000003,umask=7  10     serialization.c01_ms_scb pipeline Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state. For Tremont, UMWAIT and TPAUSE will only put the CPU into C0.1 activity state (not C0.2 activity state) event=0x75,period=200003,umask=4  00     serialization.non_c01_ms_scb pipeline Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires event=0x75,period=200003,umask=2  00    Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires. The most commonly executed instruction with an MS scoreboard is PAUSE topdown.backend_bound_slots pipeline TMA slots where no uops were being issued due to lack of back-end resources event=0xa4,period=10000003,umask=2  00    Number of slots in TMA method where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources topdown.bad_spec_slots pipeline TMA slots wasted due to incorrect speculations event=0xa4,period=10000003,umask=4  00    Number of slots of TMA method that were wasted due to incorrect speculation. It covers all types of control-flow or data-related mis-speculations topdown.br_mispredict_slots pipeline TMA slots wasted due to incorrect speculation by branch mispredictions event=0xa4,period=10000003,umask=8  00    Number of TMA slots that were wasted due to incorrect speculation by (any type of) branch mispredictions. This event estimates number of speculative operations that were issued but not retired as well as the out-of-order engine recovery past a branch misprediction topdown.memory_bound_slots pipeline TOPDOWN.MEMORY_BOUND_SLOTS event=0xa4,period=10000003,umask=0x10  00     topdown.slots pipeline TMA slots available for an unhalted logical processor. Fixed counter - architectural event event=0,period=10000003,umask=4  00    Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3) topdown.slots_p pipeline TMA slots available for an unhalted logical processor. General counter - architectural event event=0xa4,period=10000003,umask=1  00    Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core topdown_bad_speculation.all pipeline Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear event=0x73,period=1000003  00    Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ) even if an FE_bound event occurs during this period. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear topdown_bad_speculation.fastnuke pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears event=0x73,period=1000003,umask=2  00     topdown_bad_speculation.machine_clears pipeline Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation event=0x73,period=1000003,umask=3  00     topdown_bad_speculation.mispredict pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts event=0x73,period=1000003,umask=4  00     topdown_bad_speculation.nuke pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke) event=0x73,period=1000003,umask=1  00     topdown_be_bound.all pipeline Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls event=0x74,period=1000003  00     topdown_be_bound.alloc_restrictions pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions event=0x74,period=1000003,umask=1  00     topdown_be_bound.mem_scheduler pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops event=0x74,period=1000003,umask=2  00     topdown_be_bound.non_mem_scheduler pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops event=0x74,period=1000003,umask=8  00     topdown_be_bound.register pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls) event=0x74,period=1000003,umask=0x20  00     topdown_be_bound.reorder_buffer pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls) event=0x74,period=1000003,umask=0x40  00     topdown_be_bound.serialization pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS) event=0x74,period=1000003,umask=0x10  00     topdown_fe_bound.all pipeline Counts the total number of issue slots every cycle that were not consumed by the backend due to frontend stalls event=0x71,period=1000003  00     topdown_fe_bound.branch_detect pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS event=0x71,period=1000003,umask=2  00    Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches topdown_fe_bound.branch_resteer pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS event=0x71,period=1000003,umask=0x40  00    Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch topdown_fe_bound.cisc pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS) event=0x71,period=1000003,umask=1  00     topdown_fe_bound.decode pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls event=0x71,period=1000003,umask=8  00     topdown_fe_bound.frontend_bandwidth pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations event=0x71,period=1000003,umask=0x8d  00     topdown_fe_bound.frontend_latency pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to a latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses event=0x71,period=1000003,umask=0x72  00     topdown_fe_bound.itlb pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses event=0x71,period=1000003,umask=0x10  00    Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses topdown_fe_bound.other pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized event=0x71,period=1000003,umask=0x80  00     topdown_fe_bound.predecode pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes event=0x71,period=1000003,umask=4  00     topdown_retiring.all pipeline Counts the total number of consumed retirement slots event=0xc2,period=1000003  00     uops_decoded.dec0_uops pipeline UOPS_DECODED.DEC0_UOPS event=0x76,period=1000003,umask=1  00     uops_dispatched.port_0 pipeline Uops executed on port 0 event=0xb2,period=2000003,umask=1  00    Number of uops dispatch to execution  port 0 uops_dispatched.port_1 pipeline Uops executed on port 1 event=0xb2,period=2000003,umask=2  00    Number of uops dispatch to execution  port 1 uops_dispatched.port_2_3_10 pipeline Uops executed on ports 2, 3 and 10 event=0xb2,period=2000003,umask=4  00    Number of uops dispatch to execution ports 2, 3 and 10 uops_dispatched.port_4_9 pipeline Uops executed on ports 4 and 9 event=0xb2,period=2000003,umask=0x10  00    Number of uops dispatch to execution ports 4 and 9 uops_dispatched.port_5_11 pipeline Uops executed on ports 5 and 11 event=0xb2,period=2000003,umask=0x20  00    Number of uops dispatch to execution ports 5 and 11 uops_dispatched.port_6 pipeline Uops executed on port 6 event=0xb2,period=2000003,umask=0x40  00    Number of uops dispatch to execution  port 6 uops_dispatched.port_7_8 pipeline Uops executed on ports 7 and 8 event=0xb2,period=2000003,umask=0x80  00    Number of uops dispatch to execution  ports 7 and 8 uops_executed.core_cycles_ge_1 pipeline Cycles at least 1 micro-op is executed from any thread on physical core event=0xb1,cmask=1,period=2000003,umask=2  00    Counts cycles when at least 1 micro-op is executed from any thread on physical core uops_executed.core_cycles_ge_2 pipeline Cycles at least 2 micro-op is executed from any thread on physical core event=0xb1,cmask=2,period=2000003,umask=2  00    Counts cycles when at least 2 micro-ops are executed from any thread on physical core uops_executed.core_cycles_ge_3 pipeline Cycles at least 3 micro-op is executed from any thread on physical core event=0xb1,cmask=3,period=2000003,umask=2  00    Counts cycles when at least 3 micro-ops are executed from any thread on physical core uops_executed.core_cycles_ge_4 pipeline Cycles at least 4 micro-op is executed from any thread on physical core event=0xb1,cmask=4,period=2000003,umask=2  00    Counts cycles when at least 4 micro-ops are executed from any thread on physical core uops_executed.cycles_ge_1 pipeline Cycles where at least 1 uop was executed per-thread event=0xb1,cmask=1,period=2000003,umask=1  00     uops_executed.cycles_ge_2 pipeline Cycles where at least 2 uops were executed per-thread event=0xb1,cmask=2,period=2000003,umask=1  00     uops_executed.cycles_ge_3 pipeline Cycles where at least 3 uops were executed per-thread event=0xb1,cmask=3,period=2000003,umask=1  00     uops_executed.cycles_ge_4 pipeline Cycles where at least 4 uops were executed per-thread event=0xb1,cmask=4,period=2000003,umask=1  00     uops_executed.stalls pipeline Counts number of cycles no uops were dispatched to be executed on this thread event=0xb1,cmask=1,inv=1,period=2000003,umask=1  00    Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread uops_executed.stall_cycles pipeline This event is deprecated. Refer to new event UOPS_EXECUTED.STALLS event=0xb1,cmask=1,inv=1,period=2000003,umask=1  10     uops_executed.thread pipeline Counts the number of uops to be executed per-thread each cycle event=0xb1,period=2000003,umask=1  00     uops_executed.x87 pipeline Counts the number of x87 uops dispatched event=0xb1,period=2000003,umask=0x10  00    Counts the number of x87 uops executed uops_issued.any pipeline Counts the number of uops issued by the front end every cycle event=0xe,period=200003  00    Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2.  Uops_issued correlates to the number of ROB entries.  If uop takes 2 ROB slots it counts as 2 uops_issued uops_issued.any pipeline Uops that RAT issues to RS event=0xae,period=2000003,umask=1  00    Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS) uops_issued.cycles pipeline UOPS_ISSUED.CYCLES event=0xae,cmask=1,period=2000003,umask=1  00     uops_retired.all pipeline Counts the total number of uops retired event=0xc2,period=2000003  00     uops_retired.cycles pipeline Cycles with retired uop(s) event=0xc2,cmask=1,period=1000003,umask=2  00    Counts cycles where at least one uop has retired uops_retired.heavy pipeline Retired uops except the last uop of each instruction event=0xc2,period=2000003,umask=1  00    Counts the number of retired micro-operations (uops) except the last uop of each instruction. An instruction that is decoded into less than two uops does not contribute to the count uops_retired.idiv pipeline Counts the number of integer divide uops retired event=0xc2,period=2000003,umask=0x10  00     uops_retired.ms pipeline Counts the number of uops that are from complex flows issued by the micro-sequencer (MS) event=0xc2,period=2000003,umask=1  00    Counts the number of uops that are from complex flows issued by the Microcode Sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows uops_retired.ms pipeline UOPS_RETIRED.MS event=0xc2,period=2000003,umask=4,frontend=0x8  00     uops_retired.slots pipeline Retirement slots used event=0xc2,period=2000003,umask=2  00    Counts the retirement slots used each cycle uops_retired.stalls pipeline Cycles without actually retired uops event=0xc2,cmask=1,inv=1,period=1000003,umask=2  00    This event counts cycles without actually retired uops uops_retired.stall_cycles pipeline This event is deprecated. Refer to new event UOPS_RETIRED.STALLS event=0xc2,cmask=1,inv=1,period=1000003,umask=2  10     uops_retired.x87 pipeline Counts the number of x87 uops retired, includes those in MS flows event=0xc2,period=2000003,umask=2  00     uncore_arb unc_arb_coh_trk_requests.all uncore interconnect Number of requests allocated in Coherency Tracker event=0x84,umask=1  01     unc_arb_dat_occupancy.all uncore interconnect Each cycle counts number of any coherent request at memory controller that were issued by any core event=0x85,umask=1  01     unc_arb_dat_occupancy.rd uncore interconnect Each cycle counts number of coherent reads pending on data return from memory controller that were issued by any core event=0x85,umask=2  01     unc_arb_dat_requests.rd uncore interconnect This event is deprecated. Refer to new event UNC_ARB_REQ_TRK_REQUEST.DRD event=0x81,umask=2  11     unc_arb_ifa_occupancy.all uncore interconnect This event is deprecated. Refer to new event UNC_ARB_DAT_OCCUPANCY.ALL event=0x85,umask=1  11     unc_arb_req_trk_occupancy.drd uncore interconnect Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_OCCUPANCY.RD] event=0x80,umask=2  01     unc_arb_req_trk_request.drd uncore interconnect Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_REQUESTS.RD] event=0x81,umask=2  01     unc_arb_trk_occupancy.all uncore interconnect Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic event=0x80,umask=1  01     unc_arb_trk_occupancy.rd uncore interconnect Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_OCCUPANCY.DRD] event=0x80,umask=2  01     unc_arb_trk_requests.all uncore interconnect Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC event=0x81,umask=1  01     unc_arb_trk_requests.rd uncore interconnect Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_REQUEST.DRD] event=0x81,umask=2  01     uncore_imc_free_running_0 unc_mc0_rdcas_count_freerun uncore memory Counts every 64B read  request entering the Memory Controller 0 to DRAM (sum of all channels) event=0xff,umask=0x20  01    Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels) unc_mc0_wrcas_count_freerun uncore memory Counts every 64B write request entering the Memory Controller 0 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM event=0xff,umask=0x30  01     uncore_imc_free_running_1 unc_mc1_rdcas_count_freerun uncore memory Counts every 64B read request entering the Memory Controller 1 to DRAM (sum of all channels) event=0xff,umask=0x20  01    Counts every 64B read entering the Memory Controller 1 to DRAM (sum of all channels) unc_mc1_wrcas_count_freerun uncore memory Counts every 64B write request entering the Memory Controller 1 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM event=0xff,umask=0x30  01     unc_m_act_count_rd uncore memory ACT command for a read request sent to DRAM event=0x24  01     unc_m_act_count_total uncore memory ACT command sent to DRAM event=0x26  01     unc_m_act_count_wr uncore memory ACT command for a write request sent to DRAM event=0x25  01     unc_m_cas_count_rd uncore memory Read CAS command sent to DRAM event=0x22  01     unc_m_cas_count_wr uncore memory Write CAS command sent to DRAM event=0x23  01     unc_m_clockticks uncore memory Number of clocks event=1  01     unc_m_dram_page_empty_rd uncore memory incoming read request page status is Page Empty event=0x1d  01     unc_m_dram_page_empty_wr uncore memory incoming write request page status is Page Empty event=0x20  01     unc_m_dram_page_hit_rd uncore memory incoming read request page status is Page Hit event=0x1c  01     unc_m_dram_page_hit_wr uncore memory incoming write request page status is Page Hit event=0x1f  01     unc_m_dram_page_miss_rd uncore memory incoming read request page status is Page Miss event=0x1e  01     unc_m_dram_page_miss_wr uncore memory incoming write request page status is Page Miss event=0x21  01     unc_m_dram_thermal_hot uncore memory Any Rank at Hot state event=0x19  01     unc_m_dram_thermal_warm uncore memory Any Rank at Warm state event=0x1a  01     unc_m_prefetch_rd uncore memory Incoming read prefetch request from IA event=0xa  01     unc_m_pre_count_idle uncore memory PRE command sent to DRAM due to page table idle timer expiration event=0x28  01     unc_m_pre_count_page_miss uncore memory PRE command sent to DRAM for a read/write request event=0x27  01     unc_m_vc0_requests_rd uncore memory Incoming VC0 read request event=2  01     unc_m_vc0_requests_wr uncore memory Incoming VC0 write request event=3  01     unc_m_vc1_requests_rd uncore memory Incoming VC1 read request event=4  01     unc_m_vc1_requests_wr uncore memory Incoming VC1 write request event=5  01     uncore_clock unc_clock.socket uncore other This 48-bit fixed counter counts the UCLK cycles event=0xff  01     dtlb_load_misses.stlb_hit virtual memory Loads that miss the DTLB and hit the STLB event=0x12,period=100003,umask=0x20  00    Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB) dtlb_load_misses.walk_active virtual memory Cycles when at least one PMH is busy with a page walk for a demand load event=0x12,cmask=1,period=100003,umask=0x10  00    Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load dtlb_load_misses.walk_completed virtual memory Counts the number of page walks completed due to load DTLB misses to any page size event=8,period=200003,umask=0xe  00    Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault dtlb_load_misses.walk_completed virtual memory Load miss in all TLB levels causes a page walk that completes. (All page sizes) event=0x12,period=100003,umask=0xe  00    Counts completed page walks  (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_load_misses.walk_completed_1g virtual memory Page walks completed due to a demand data load to a 1G page event=0x12,period=100003,umask=8  00    Counts completed page walks  (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_load_misses.walk_completed_2m_4m virtual memory Page walks completed due to a demand data load to a 2M/4M page event=0x12,period=100003,umask=4  00    Counts completed page walks  (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_load_misses.walk_completed_4k virtual memory Page walks completed due to a demand data load to a 4K page event=0x12,period=100003,umask=2  00    Counts completed page walks  (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_load_misses.walk_pending virtual memory Number of page walks outstanding for a demand load in the PMH each cycle event=0x12,period=100003,umask=0x10  00    Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle dtlb_store_misses.stlb_hit virtual memory Stores that miss the DTLB and hit the STLB event=0x13,period=100003,umask=0x20  00    Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB) dtlb_store_misses.walk_active virtual memory Cycles when at least one PMH is busy with a page walk for a store event=0x13,cmask=1,period=100003,umask=0x10  00    Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store dtlb_store_misses.walk_completed virtual memory Counts the number of page walks completed due to store DTLB misses to any page size event=0x49,period=2000003,umask=0xe  00    Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size.  Includes page walks that page fault dtlb_store_misses.walk_completed virtual memory Store misses in all TLB levels causes a page walk that completes. (All page sizes) event=0x13,period=100003,umask=0xe  00    Counts completed page walks  (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_completed_1g virtual memory Page walks completed due to a demand data store to a 1G page event=0x13,period=100003,umask=8  00    Counts completed page walks  (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_completed_2m_4m virtual memory Page walks completed due to a demand data store to a 2M/4M page event=0x13,period=100003,umask=4  00    Counts completed page walks  (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_completed_4k virtual memory Page walks completed due to a demand data store to a 4K page event=0x13,period=100003,umask=2  00    Counts completed page walks  (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_pending virtual memory Number of page walks outstanding for a store in the PMH each cycle event=0x13,period=100003,umask=0x10  00    Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle itlb_misses.miss_caused_walk virtual memory Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs event=0x85,period=1000003,umask=1  00     itlb_misses.pde_cache_miss virtual memory Counts the number of page walks due to an instruction fetch that miss the PDE (Page Directory Entry) cache event=0x85,period=2000003,umask=0x80  00     itlb_misses.stlb_hit virtual memory Instruction fetch requests that miss the ITLB and hit the STLB event=0x11,period=100003,umask=0x20  00    Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB) itlb_misses.walk_active virtual memory Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request event=0x11,cmask=1,period=100003,umask=0x10  00    Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request itlb_misses.walk_completed virtual memory Counts the number of page walks completed due to instruction fetch misses to any page size event=0x85,period=200003,umask=0xe  00    Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size.  Includes page walks that page fault itlb_misses.walk_completed virtual memory Code miss in all TLB levels causes a page walk that completes. (All page sizes) event=0x11,period=100003,umask=0xe  00    Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault itlb_misses.walk_completed_2m_4m virtual memory Code miss in all TLB levels causes a page walk that completes. (2M/4M) event=0x11,period=100003,umask=4  00    Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault itlb_misses.walk_completed_4k virtual memory Code miss in all TLB levels causes a page walk that completes. (4K) event=0x11,period=100003,umask=2  00    Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault itlb_misses.walk_pending virtual memory Number of page walks outstanding for an outstanding code request in the PMH each cycle event=0x11,period=100003,umask=0x10  00    Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle ld_head.dtlb_miss_at_ret virtual memory Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss event=5,period=1000003,umask=0x90  00     mem_uops_retired.dtlb_miss virtual memory This event is deprecated. Refer to new event MEM_UOPS_RETIRED.STLB_MISS  Supports address when precise event=0xd0,period=200003,umask=0x13  10     mem_uops_retired.dtlb_miss_loads virtual memory This event is deprecated. Refer to new event MEM_UOPS_RETIRED.STLB_MISS_LOADS  Supports address when precise event=0xd0,period=200003,umask=0x11  10     mem_uops_retired.dtlb_miss_stores virtual memory This event is deprecated. Refer to new event MEM_UOPS_RETIRED.STLB_MISS_STORES  Supports address when precise event=0xd0,period=200003,umask=0x12  10     bp_dyn_ind_pred branch Dynamic Indirect Predictions event=0x8e  00    Indirect Branch Prediction for potential multi-target branch (speculative) bp_de_redirect branch Decoder Overrides Existing Branch Prediction (speculative) event=0x91  00     bp_l1_tlb_fetch_hit branch The number of instruction fetches that hit in the L1 ITLB event=0x94  00     ic_fw32 cache The number of 32B fetch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheable fill responses) event=0x80  00     ic_fw32_miss cache The number of 32B fetch windows tried to read the L1 IC and missed in the full tag event=0x81  00     ic_cache_fill_l2 cache The number of 64 byte instruction cache line was fulfilled from the L2 cache event=0x82  00     ic_cache_fill_sys cache The number of 64 byte instruction cache line fulfilled from system memory or another cache event=0x83  00     bp_l1_tlb_miss_l2_hit cache The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB event=0x84  00     bp_l1_tlb_miss_l2_miss cache The number of instruction fetches that miss in both the L1 and L2 TLBs event=0x85  00     bp_snp_re_sync cache The number of pipeline restarts caused by invalidating probes that hit on the instruction stream currently being executed. This would happen if the active instruction stream was being modified by another processor in an MP system - typically a highly unlikely event event=0x86  00     ic_fetch_stall.ic_stall_any cache Instruction Pipe Stall. IC pipe was stalled during this clock cycle for any reason (nothing valid in pipe ICM1) event=0x87,umask=4  00     ic_fetch_stall.ic_stall_dq_empty cache Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to DQ empty event=0x87,umask=2  00     ic_fetch_stall.ic_stall_back_pressure cache Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure event=0x87,umask=1  00     ic_cache_inval.l2_invalidating_probe cache IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another core event=0x8c,umask=2  00     ic_cache_inval.fill_invalidated cache IC line invalidated due to overwriting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another core event=0x8c,umask=1  00     bp_tlb_rel cache The number of ITLB reload requests event=0x99  00     l2_request_g1.rd_blk_l cache All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including hardware and software prefetch) event=0x60,umask=0x80  00     l2_request_g1.rd_blk_x cache All L2 Cache Requests (Breakdown 1 - Common). Data cache stores event=0x60,umask=0x40  00     l2_request_g1.ls_rd_blk_c_s cache All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads event=0x60,umask=0x20  00     l2_request_g1.cacheable_ic_read cache All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads event=0x60,umask=0x10  00     l2_request_g1.change_to_x cache All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Request change to writable, check L2 for current state event=0x60,umask=8  00     l2_request_g1.prefetch_l2_cmd cache All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd event=0x60,umask=4  00     l2_request_g1.l2_hw_pf cache All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2 pipeline, hit or miss. Types of PF and L2 hit/miss broken out in a separate perfmon event event=0x60,umask=2  00     l2_request_g1.group2 cache Miscellaneous events covered in more detail by l2_request_g2 (PMCx061) event=0x60,umask=1  00     l2_request_g1.all_no_prefetch cache  event=0x60,umask=0xf9  00     l2_request_g2.group1 cache Miscellaneous events covered in more detail by l2_request_g1 (PMCx060) event=0x61,umask=0x80  00     l2_request_g2.ls_rd_sized cache All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized event=0x61,umask=0x40  00     l2_request_g2.ls_rd_sized_nc cache All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheable event=0x61,umask=0x20  00     l2_request_g2.ic_rd_sized cache All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized event=0x61,umask=0x10  00     l2_request_g2.ic_rd_sized_nc cache All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized non-cacheable event=0x61,umask=8  00     l2_request_g2.smc_inval cache All L2 Cache Requests (Breakdown 2 - Rare). Self-modifying code invalidates event=0x61,umask=4  00     l2_request_g2.bus_locks_originator cache All L2 Cache Requests (Breakdown 2 - Rare). Bus locks event=0x61,umask=2  00     l2_request_g2.bus_locks_responses cache All L2 Cache Requests (Breakdown 2 - Rare). Bus lock response event=0x61,umask=1  00     l2_latency.l2_cycles_waiting_on_fills cache Total cycles spent waiting for L2 fills to complete from L3 or memory, divided by four. Event counts are for both threads. To calculate average latency, the number of fills from both threads must be used event=0x62,umask=1  00     l2_wcb_req.wcb_write cache LS to L2 WCB write requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) write requests event=0x63,umask=0x40  00     l2_wcb_req.wcb_close cache LS to L2 WCB close requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) close requests event=0x63,umask=0x20  00     l2_wcb_req.zero_byte_store cache LS to L2 WCB zero byte store requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) zero byte store requests event=0x63,umask=4  00     l2_wcb_req.cl_zero cache LS to L2 WCB cache line zeroing requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) cache line zeroing requests event=0x63,umask=1  00     l2_cache_req_stat.ls_rd_blk_cs cache Core to L2 cacheable request access status (not including L2 Prefetch). Data cache shared read hit in L2 event=0x64,umask=0x80  00     l2_cache_req_stat.ls_rd_blk_l_hit_x cache Core to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit in L2 event=0x64,umask=0x40  00     l2_cache_req_stat.ls_rd_blk_l_hit_s cache Core to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit on shared line in L2 event=0x64,umask=0x20  00     l2_cache_req_stat.ls_rd_blk_x cache Core to L2 cacheable request access status (not including L2 Prefetch). Data cache store or state change hit in L2 event=0x64,umask=0x10  00     l2_cache_req_stat.ls_rd_blk_c cache Core to L2 cacheable request access status (not including L2 Prefetch). Data cache request miss in L2 (all types) event=0x64,umask=8  00     l2_cache_req_stat.ic_fill_hit_x cache Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit modifiable line in L2 event=0x64,umask=4  00     l2_cache_req_stat.ic_fill_hit_s cache Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit clean line in L2 event=0x64,umask=2  00     l2_cache_req_stat.ic_fill_miss cache Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2 event=0x64,umask=1  00     l2_cache_req_stat.ic_access_in_l2 cache Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache requests in L2 event=0x64,umask=7  00     l2_cache_req_stat.ic_dc_miss_in_l2 cache Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2 and Data cache request miss in L2 (all types) event=0x64,umask=9  00     l2_cache_req_stat.ic_dc_hit_in_l2 cache Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request hit in L2 and Data cache request hit in L2 (all types) event=0x64,umask=0xf6  00     l2_fill_pending.l2_fill_busy cache Cycles with fill pending from L2. Total cycles spent with one or more fill requests in flight from L2 event=0x6d,umask=1  00     l2_pf_hit_l2 cache L2 prefetch hit in L2. Use l2_cache_hits_from_l2_hwpf instead event=0x70,umask=0xff  00     l2_pf_miss_l2_hit_l3 cache L2 prefetcher hits in L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3 event=0x71,umask=0xff  00     l2_pf_miss_l2_l3 cache L2 prefetcher misses in L3. All L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches event=0x72,umask=0xff  00     amd_l3 l3_request_g1.caching_l3_cache_accesses cache Caching: L3 cache accesses event=1,umask=0x80  00     l3_lookup_state.all_l3_req_typs cache All L3 Request Types event=4,umask=0xff  00     l3_comb_clstr_state.other_l3_miss_typs cache Other L3 Miss Request Types event=6,umask=0xfe  00     l3_comb_clstr_state.request_miss cache L3 cache misses event=6,umask=1  00     xi_sys_fill_latency cache L3 Cache Miss Latency. Total cycles for all transactions divided by 16. Ignores SliceMask and ThreadMask event=0x90  00     xi_ccx_sdp_req1.all_l3_miss_req_typs cache All L3 Miss Request Types. Ignores SliceMask and ThreadMask event=0x9a,umask=0x3f  00     ex_ret_instr core Retired Instructions event=0xc0  00     ex_ret_cops core Retired Uops event=0xc1  00    The number of uOps retired. This includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 4 ex_ret_brn core Retired Branch Instructions event=0xc2  00    The number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interrupts ex_ret_brn_misp core Retired Branch Instructions Mispredicted event=0xc3  00    The number of branch instructions retired, of any type, that were not correctly predicted. This includes those for which prediction is not attempted (far control transfers, exceptions and interrupts) ex_ret_brn_tkn core Retired Taken Branch Instructions event=0xc4  00    The number of taken branches that were retired. This includes all types of architectural control flow changes, including exceptions and interrupts ex_ret_brn_tkn_misp core Retired Taken Branch Instructions Mispredicted event=0xc5  00    The number of retired taken branch instructions that were mispredicted ex_ret_brn_far core Retired Far Control Transfers event=0xc6  00    The number of far control transfers retired including far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts. Far control transfers are not subject to branch prediction ex_ret_brn_resync core Retired Branch Resyncs event=0xc7  00    The number of resync branches. These reflect pipeline restarts due to certain microcode assists and events such as writes to the active instruction stream, among other things. Each occurrence reflects a restart penalty similar to a branch mispredict. This is relatively rare ex_ret_near_ret core Retired Near Returns event=0xc8  00    The number of near return instructions (RET or RET Iw) retired ex_ret_near_ret_mispred core Retired Near Returns Mispredicted event=0xc9  00    The number of near returns retired that were not correctly predicted by the return address predictor. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction ex_ret_brn_ind_misp core Retired Indirect Branch Instructions Mispredicted event=0xca  00     ex_ret_mmx_fp_instr.sse_instr core SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX) event=0xcb,umask=4  00    The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX) ex_ret_mmx_fp_instr.mmx_instr core MMX instructions event=0xcb,umask=2  00    The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. MMX instructions ex_ret_mmx_fp_instr.x87_instr core x87 instructions event=0xcb,umask=1  00    The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. x87 instructions ex_ret_cond core Retired Conditional Branch Instructions event=0xd1  00     ex_div_busy core Div Cycles Busy count event=0xd3  00     ex_div_count core Div Op Count event=0xd4  00     ex_tagged_ibs_ops.ibs_count_rollover core Tagged IBS Ops. Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired event=0x1cf,umask=4  00     ex_tagged_ibs_ops.ibs_tagged_ops_ret core Tagged IBS Ops. Number of Ops tagged by IBS that retired event=0x1cf,umask=2  00     ex_tagged_ibs_ops.ibs_tagged_ops core Tagged IBS Ops. Number of Ops tagged by IBS event=0x1cf,umask=1  00     ex_ret_fus_brnch_inst core The number of fused retired branch instructions retired per cycle. The number of events logged per cycle can vary from 0 to 3 event=0x1d0  00     amd_df remote_outbound_data_controller_0 data fabric  event=0x7c7,umask=2  01    Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 0 remote_outbound_data_controller_1 data fabric  event=0x807,umask=2  01    Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 1 remote_outbound_data_controller_2 data fabric  event=0x847,umask=2  01    Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 2 remote_outbound_data_controller_3 data fabric  event=0x887,umask=2  01    Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 3 dram_channel_data_controller_0 data fabric  event=7,umask=0x38  01    DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0 dram_channel_data_controller_1 data fabric  event=0x47,umask=0x38  01    DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0 dram_channel_data_controller_2 data fabric  event=0x87,umask=0x38  01    DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0 dram_channel_data_controller_3 data fabric  event=0xc7,umask=0x38  01    DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0 dram_channel_data_controller_4 data fabric  event=0x107,umask=0x38  01    DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0 dram_channel_data_controller_5 data fabric  event=0x147,umask=0x38  01    DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0 dram_channel_data_controller_6 data fabric  event=0x187,umask=0x38  01    DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0 dram_channel_data_controller_7 data fabric  event=0x1c7,umask=0x38  01    DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0 fpu_pipe_assignment.dual floating point Total number multi-pipe uOps assigned to all pipes event=0,umask=0xf0  00    The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to all pipes fpu_pipe_assignment.dual3 floating point Total number multi-pipe uOps assigned to pipe 3 event=0,umask=0x80  00    The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 3 fpu_pipe_assignment.dual2 floating point Total number multi-pipe uOps assigned to pipe 2 event=0,umask=0x40  00    The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 2 fpu_pipe_assignment.dual1 floating point Total number multi-pipe uOps assigned to pipe 1 event=0,umask=0x20  00    The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 1 fpu_pipe_assignment.dual0 floating point Total number multi-pipe uOps assigned to pipe 0 event=0,umask=0x10  00    The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 0 fpu_pipe_assignment.total floating point Total number uOps assigned to all fpu pipes event=0,umask=0xf  00    The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to all pipes fpu_pipe_assignment.total3 floating point Total number of fp uOps on pipe 3 event=0,umask=8  00    The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one-cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 3 fpu_pipe_assignment.total2 floating point Total number of fp uOps on pipe 2 event=0,umask=4  00    The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 2 fpu_pipe_assignment.total1 floating point Total number of fp uOps on pipe 1 event=0,umask=2  00    The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 1 fpu_pipe_assignment.total0 floating point Total number of fp uOps  on pipe 0 event=0,umask=1  00    The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 0 fp_sched_empty floating point This is a speculative event. The number of cycles in which the FPU scheduler is empty. Note that some Ops like FP loads bypass the scheduler event=1  00     fp_retx87_fp_ops.all floating point All Ops event=2,umask=7  00    The number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8 fp_retx87_fp_ops.div_sqr_r_ops floating point Divide and square root Ops event=2,umask=4  00    The number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8. Divide and square root Ops fp_retx87_fp_ops.mul_ops floating point Multiply Ops event=2,umask=2  00    The number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8. Multiply Ops fp_retx87_fp_ops.add_sub_ops floating point Add/subtract Ops event=2,umask=1  00    The number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8. Add/subtract Ops fp_ret_sse_avx_ops.all floating point All FLOPS event=3,umask=0xff  00    This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 fp_ret_sse_avx_ops.dp_mult_add_flops floating point Double precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS event=3,umask=0x80  00    This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS fp_ret_sse_avx_ops.dp_div_flops floating point Double precision divide/square root FLOPS event=3,umask=0x40  00    This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision divide/square root FLOPS fp_ret_sse_avx_ops.dp_mult_flops floating point Double precision multiply FLOPS event=3,umask=0x20  00    This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision multiply FLOPS fp_ret_sse_avx_ops.dp_add_sub_flops floating point Double precision add/subtract FLOPS event=3,umask=0x10  00    This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision add/subtract FLOPS fp_ret_sse_avx_ops.sp_mult_add_flops floating point Single precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS event=3,umask=8  00    This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS fp_ret_sse_avx_ops.sp_div_flops floating point Single-precision divide/square root FLOPS event=3,umask=4  00    This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single-precision divide/square root FLOPS fp_ret_sse_avx_ops.sp_mult_flops floating point Single-precision multiply FLOPS event=3,umask=2  00    This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single-precision multiply FLOPS fp_ret_sse_avx_ops.sp_add_sub_flops floating point Single-precision add/subtract FLOPS event=3,umask=1  00    This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single-precision add/subtract FLOPS fp_num_mov_elim_scal_op.optimized floating point Number of Scalar Ops optimized event=4,umask=8  00    This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of Scalar Ops optimized fp_num_mov_elim_scal_op.opt_potential floating point Number of Ops that are candidates for optimization (have Z-bit either set or pass) event=4,umask=4  00    This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of Ops that are candidates for optimization (have Z-bit either set or pass) fp_num_mov_elim_scal_op.sse_mov_ops_elim floating point Number of SSE Move Ops eliminated event=4,umask=2  00    This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of SSE Move Ops eliminated fp_num_mov_elim_scal_op.sse_mov_ops floating point Number of SSE Move Ops event=4,umask=1  00    This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of SSE Move Ops fp_retired_ser_ops.x87_ctrl_ret floating point x87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bits event=5,umask=8  00    The number of serializing Ops retired. x87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bits fp_retired_ser_ops.x87_bot_ret floating point x87 bottom-executing uOps retired event=5,umask=4  00    The number of serializing Ops retired. x87 bottom-executing uOps retired fp_retired_ser_ops.sse_ctrl_ret floating point SSE control word mispredict traps due to mispredictions in RC, FTZ or DAZ, or changes in mask bits event=5,umask=2  00    The number of serializing Ops retired. SSE control word mispredict traps due to mispredictions in RC, FTZ or DAZ, or changes in mask bits fp_retired_ser_ops.sse_bot_ret floating point SSE bottom-executing uOps retired event=5,umask=1  00    The number of serializing Ops retired. SSE bottom-executing uOps retired ls_locks.bus_lock memory Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory type event=0x25,umask=1  00     ls_dispatch.ld_st_dispatch memory Counts the number of operations dispatched to the LS unit. Unit Masks ADDed. Load-op-Stores event=0x29,umask=4  00     ls_dispatch.store_dispatch memory Counts the number of stores dispatched to the LS unit. Unit Masks ADDed event=0x29,umask=2  00     ls_dispatch.ld_dispatch memory Counts the number of loads dispatched to the LS unit. Unit Masks ADDed event=0x29,umask=1  00     ls_stlf memory Number of STLF hits event=0x35  00     ls_dc_accesses memory The number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative event event=0x40  00     ls_mab_alloc.dc_prefetcher memory LS MAB allocates by type - DC prefetcher event=0x41,umask=8  00     ls_mab_alloc.stores memory LS MAB allocates by type - stores event=0x41,umask=2  00     ls_mab_alloc.loads memory LS MAB allocates by type - loads event=0x41,umask=1  00     ls_l1_d_tlb_miss.all memory L1 DTLB Miss or Reload off all sizes event=0x45,umask=0xff  00     ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss memory L1 DTLB Miss of a page of 1G size event=0x45,umask=0x80  00     ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss memory L1 DTLB Miss of a page of 2M size event=0x45,umask=0x40  00     ls_l1_d_tlb_miss.tlb_reload_32k_l2_miss memory L1 DTLB Miss of a page of 32K size event=0x45,umask=0x20  00     ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss memory L1 DTLB Miss of a page of 4K size event=0x45,umask=0x10  00     ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit memory L1 DTLB Reload of a page of 1G size event=0x45,umask=8  00     ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit memory L1 DTLB Reload of a page of 2M size event=0x45,umask=4  00     ls_l1_d_tlb_miss.tlb_reload_32k_l2_hit memory L1 DTLB Reload of a page of 32K size event=0x45,umask=2  00     ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit memory L1 DTLB Reload of a page of 4K size event=0x45,umask=1  00     ls_tablewalker.iside memory Total Page Table Walks on I-side event=0x46,umask=0xc  00     ls_tablewalker.ic_type1 memory Total Page Table Walks IC Type 1 event=0x46,umask=8  00     ls_tablewalker.ic_type0 memory Total Page Table Walks IC Type 0 event=0x46,umask=4  00     ls_tablewalker.dside memory Total Page Table Walks on D-side event=0x46,umask=3  00     ls_tablewalker.dc_type1 memory Total Page Table Walks DC Type 1 event=0x46,umask=2  00     ls_tablewalker.dc_type0 memory Total Page Table Walks DC Type 0 event=0x46,umask=1  00     ls_misal_accesses memory Misaligned loads event=0x47  00     ls_pref_instr_disp.prefetch_nta memory Software Prefetch Instructions (PREFETCHNTA instruction) Dispatched event=0x4b,umask=4  00     ls_pref_instr_disp.store_prefetch_w memory Software Prefetch Instructions (3DNow PREFETCHW instruction) Dispatched event=0x4b,umask=2  00     ls_pref_instr_disp.load_prefetch_w memory Software Prefetch Instructions Dispatched. Prefetch, Prefetch_T0_T1_T2 event=0x4b,umask=1  00     ls_inef_sw_pref.mab_mch_cnt memory The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a match on an already-allocated miss request buffer event=0x52,umask=2  00     ls_inef_sw_pref.data_pipe_sw_pf_dc_hit memory The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a DC hit event=0x52,umask=1  00     ls_not_halted_cyc memory Cycles not in Halt event=0x76  00     ic_oc_mode_switch.oc_ic_mode_switch other OC Mode Switch. OC to IC mode switch event=0x28a,umask=2  00     ic_oc_mode_switch.ic_oc_mode_switch other OC Mode Switch. IC to OC mode switch event=0x28a,umask=1  00     de_dis_dispatch_token_stalls0.retire_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. RETIRE Tokens unavailable event=0xaf,umask=0x40  00     de_dis_dispatch_token_stalls0.agsq_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. AGSQ Tokens unavailable event=0xaf,umask=0x20  00     de_dis_dispatch_token_stalls0.alu_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALU tokens total unavailable event=0xaf,umask=0x10  00     de_dis_dispatch_token_stalls0.alsq3_0_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 3_0 Tokens unavailable event=0xaf,umask=8  00     de_dis_dispatch_token_stalls0.alsq3_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 3 Tokens unavailable event=0xaf,umask=4  00     de_dis_dispatch_token_stalls0.alsq2_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 2 Tokens unavailable event=0xaf,umask=2  00     de_dis_dispatch_token_stalls0.alsq1_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 1 Tokens unavailable event=0xaf,umask=1  00     all_dc_accesses recommended All L1 Data Cache Accesses event=0x29,umask=7  00     l2_cache_accesses_from_ic_misses recommended L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch) event=0x60,umask=0x10  00     l2_cache_accesses_from_dc_misses recommended L2 Cache Accesses from L1 Data Cache Misses (including prefetch) event=0x60,umask=0xc8  00     l2_cache_misses_from_ic_miss recommended L2 Cache Misses from L1 Instruction Cache Misses event=0x64,umask=1  00     l2_cache_misses_from_dc_misses recommended L2 Cache Misses from L1 Data Cache Misses event=0x64,umask=8  00     l2_cache_hits_from_ic_misses recommended L2 Cache Hits from L1 Instruction Cache Misses event=0x64,umask=6  00     l2_cache_hits_from_dc_misses recommended L2 Cache Hits from L1 Data Cache Misses event=0x64,umask=0x70  00     l2_cache_hits_from_l2_hwpf recommended L2 Cache Hits from L2 HWPF event=0x70,umask=0xff  00     l3_accesses recommended L3 Accesses event=4,umask=0xff  00     l3_misses recommended L3 Misses (includes Chg2X) event=4,umask=1  00     l2_itlb_misses recommended L2 ITLB Misses & Instruction page walks event=0x85,umask=7  00     l1_dtlb_misses recommended L1 DTLB Misses event=0x45,umask=0xff  00     l2_dtlb_misses recommended L2 DTLB Misses & Data page walks event=0x45,umask=0xf0  00     all_tlbs_flushed recommended All TLBs Flushed event=0x78,umask=0xdf  00     uops_dispatched recommended Micro-ops Dispatched event=0xaa,umask=3  00     sse_avx_stalls recommended Mixed SSE/AVX Stalls event=0xe,umask=0xe  00     uops_retired recommended Micro-ops Retired event=0xc1  00     bp_l1_btb_correct branch L1 Branch Prediction Overrides Existing Prediction (speculative) event=0x8a  00     bp_l2_btb_correct branch L2 Branch Prediction Overrides Existing Prediction (speculative) event=0x8b  00     bp_l1_tlb_fetch_hit branch The number of instruction fetches that hit in the L1 ITLB event=0x94,umask=0xff  00     bp_l1_tlb_fetch_hit.if1g branch The number of instruction fetches that hit in the L1 ITLB. Instruction fetches to a 1GB page event=0x94,umask=4  00     bp_l1_tlb_fetch_hit.if2m branch The number of instruction fetches that hit in the L1 ITLB. Instruction fetches to a 2MB page event=0x94,umask=2  00     bp_l1_tlb_fetch_hit.if4k branch The number of instruction fetches that hit in the L1 ITLB. Instruction fetches to a 4KB page event=0x94,umask=1  00     bp_tlb_rel branch The number of ITLB reload requests event=0x99  00     bp_l1_tlb_miss_l2_tlb_miss cache The number of instruction fetches that miss in both the L1 and L2 TLBs event=0x85,umask=0xff  00     bp_l1_tlb_miss_l2_tlb_miss.if1g cache The number of instruction fetches that miss in both the L1 and L2 TLBs. Instruction fetches to a 1GB page event=0x85,umask=4  00     bp_l1_tlb_miss_l2_tlb_miss.if2m cache The number of instruction fetches that miss in both the L1 and L2 TLBs. Instruction fetches to a 2MB page event=0x85,umask=2  00     bp_l1_tlb_miss_l2_tlb_miss.if4k cache The number of instruction fetches that miss in both the L1 and L2 TLBs. Instruction fetches to a 4KB page event=0x85,umask=1  00     ic_oc_mode_switch.oc_ic_mode_switch cache OC Mode Switch. OC to IC mode switch event=0x28a,umask=2  00     ic_oc_mode_switch.ic_oc_mode_switch cache OC Mode Switch. IC to OC mode switch event=0x28a,umask=1  00     ex_ret_cops core Retired Uops event=0xc1  00    The number of micro-ops retired. This count includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 8 ex_ret_cond_misp core Retired Conditional Branch Instructions Mispredicted event=0xd2  00     ex_ret_fus_brnch_inst core Retired Fused Instructions. The number of fuse-branch instructions retired per cycle. The number of events logged per cycle can vary from 0-8 event=0x1d0  00     fpu_pipe_assignment.total floating point Total number of fp uOps event=0,umask=0xf  00    Total number of fp uOps. The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS fpu_pipe_assignment.total3 floating point Total number uOps assigned to pipe 3 event=0,umask=8  00    The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one-cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 3 fpu_pipe_assignment.total2 floating point Total number uOps assigned to pipe 2 event=0,umask=4  00    The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 2 fpu_pipe_assignment.total1 floating point Total number uOps assigned to pipe 1 event=0,umask=2  00    The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 1 fp_ret_sse_avx_ops.all floating point All FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 event=3,umask=0xff  00     fp_ret_sse_avx_ops.mac_flops floating point Multiply-add FLOPS. Multiply-add counts as 2 FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 event=3,umask=8  00     fp_ret_sse_avx_ops.div_flops floating point Divide/square root FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 event=3,umask=4  00     fp_ret_sse_avx_ops.mult_flops floating point Multiply FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 event=3,umask=2  00     fp_ret_sse_avx_ops.add_sub_flops floating point Add/subtract FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 event=3,umask=1  00     fp_num_mov_elim_scal_op.optimized floating point Number of Scalar Ops optimized. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes event=4,umask=8  00     fp_num_mov_elim_scal_op.opt_potential floating point Number of Ops that are candidates for optimization (have Z-bit either set or pass). This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes event=4,umask=4  00     fp_num_mov_elim_scal_op.sse_mov_ops_elim floating point Number of SSE Move Ops eliminated. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes event=4,umask=2  00     fp_num_mov_elim_scal_op.sse_mov_ops floating point Number of SSE Move Ops. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes event=4,umask=1  00     fp_retired_ser_ops.sse_bot_ret floating point SSE bottom-executing uOps retired. The number of serializing Ops retired event=5,umask=8  00     fp_retired_ser_ops.sse_ctrl_ret floating point The number of serializing Ops retired. SSE control word mispredict traps due to mispredictions in RC, FTZ or DAZ, or changes in mask bits event=5,umask=4  00     fp_retired_ser_ops.x87_bot_ret floating point x87 bottom-executing uOps retired. The number of serializing Ops retired event=5,umask=2  00     fp_retired_ser_ops.x87_ctrl_ret floating point x87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bits. The number of serializing Ops retired event=5,umask=1  00     fp_disp_faults.ymm_spill_fault floating point Floating Point Dispatch Faults. YMM spill fault event=0xe,umask=8  00     fp_disp_faults.ymm_fill_fault floating point Floating Point Dispatch Faults. YMM fill fault event=0xe,umask=4  00     fp_disp_faults.xmm_fill_fault floating point Floating Point Dispatch Faults. XMM fill fault event=0xe,umask=2  00     fp_disp_faults.x87_fill_fault floating point Floating Point Dispatch Faults. x87 fill fault event=0xe,umask=1  00     ls_bad_status2.stli_other memory Non-forwardable conflict; used to reduce STLI's via software. All reasons. Store To Load Interlock (STLI) are loads that were unable to complete because of a possible match with an older store, and the older store could not do STLF for some reason event=0x24,umask=2  00    Store-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older store. Most commonly, a load's address range partially but not completely overlaps with an uncompleted older store. Software can avoid this problem by using same-size and same-alignment loads and stores when accessing the same data. Vector/SIMD code is particularly susceptible to this problem; software should construct wide vector stores by manipulating vector elements in registers using shuffle/blend/swap instructions prior to storing to memory, instead of using narrow element-by-element stores ls_locks.spec_lock_hi_spec memory Retired lock instructions. High speculative cacheable lock speculation succeeded event=0x25,umask=8  00     ls_locks.spec_lock_lo_spec memory Retired lock instructions. Low speculative cacheable lock speculation succeeded event=0x25,umask=4  00     ls_locks.non_spec_lock memory Retired lock instructions. Non-speculative lock succeeded event=0x25,umask=2  00     ls_locks.bus_lock memory Retired lock instructions. Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory type. Comparable to legacy bus lock event=0x25,umask=1  00     ls_ret_cl_flush memory Number of retired CLFLUSH instructions event=0x26  00     ls_ret_cpuid memory Number of retired CPUID instructions event=0x27  00     ls_dispatch.ld_st_dispatch memory Dispatch of a single op that performs a load from and store to the same memory address. Number of single ops that do load/store to an address event=0x29,umask=4  00     ls_dispatch.store_dispatch memory Number of stores dispatched. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed event=0x29,umask=2  00     ls_dispatch.ld_dispatch memory Number of loads dispatched. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed event=0x29,umask=1  00     ls_smi_rx memory Number of SMIs received event=0x2b  00     ls_int_taken memory Number of interrupts taken event=0x2c  00     ls_rdtsc memory Number of reads of the TSC (RDTSC instructions). The count is speculative event=0x2d  00     ls_st_commit_cancel2.st_commit_cancel_wcb_full memory A non-cacheable store and the non-cacheable commit buffer is full event=0x37  00     ls_dc_accesses memory Number of accesses to the dcache for load/store references event=0x40  00    The number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative event ls_mab_alloc.dc_prefetcher memory LS MAB Allocates by Type. DC prefetcher event=0x41,umask=8  00     ls_mab_alloc.stores memory LS MAB Allocates by Type. Stores event=0x41,umask=2  00     ls_mab_alloc.loads memory LS MAB Allocates by Type. Loads event=0x41,umask=1  00     ls_refills_from_sys.ls_mabresp_rmt_dram memory Demand Data Cache Fills by Data Source. DRAM or IO from different die event=0x43,umask=0x40  00     ls_refills_from_sys.ls_mabresp_rmt_cache memory Demand Data Cache Fills by Data Source. Hit in cache; Remote CCX and the address's Home Node is on a different die event=0x43,umask=0x10  00     ls_refills_from_sys.ls_mabresp_lcl_dram memory Demand Data Cache Fills by Data Source. DRAM or IO from this thread's die event=0x43,umask=8  00     ls_refills_from_sys.ls_mabresp_lcl_cache memory Demand Data Cache Fills by Data Source. Hit in cache; local CCX (not Local L2), or Remote CCX and the address's Home Node is on this thread's die event=0x43,umask=2  00     ls_refills_from_sys.ls_mabresp_lcl_l2 memory Demand Data Cache Fills by Data Source. Local L2 hit event=0x43,umask=1  00     ls_l1_d_tlb_miss.all memory All L1 DTLB Misses or Reloads event=0x45,umask=0xff  00     ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss memory L1 DTLB Miss. DTLB reload to a 1G page that miss in the L2 TLB event=0x45,umask=0x80  00     ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss memory L1 DTLB Miss. DTLB reload to a 2M page that miss in the L2 TLB event=0x45,umask=0x40  00     ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss memory L1 DTLB Miss. DTLB reload coalesced page miss event=0x45,umask=0x20  00     ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss memory L1 DTLB Miss. DTLB reload to a 4K page that miss the L2 TLB event=0x45,umask=0x10  00     ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit memory L1 DTLB Miss. DTLB reload to a 1G page that hit in the L2 TLB event=0x45,umask=8  00     ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit memory L1 DTLB Miss. DTLB reload to a 2M page that hit in the L2 TLB event=0x45,umask=4  00     ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit memory L1 DTLB Miss. DTLB reload hit a coalesced page event=0x45,umask=2  00     ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit memory L1 DTLB Miss. DTLB reload to a 4K page that hit in the L2 TLB event=0x45,umask=1  00     ls_pref_instr_disp memory Software Prefetch Instructions Dispatched (Speculative) event=0x4b,umask=0xff  00     ls_pref_instr_disp.prefetch_nta memory Software Prefetch Instructions Dispatched (Speculative). PrefetchNTA instruction. See docAPM3 PREFETCHlevel event=0x4b,umask=4  00     ls_pref_instr_disp.prefetch_w memory Software Prefetch Instructions Dispatched (Speculative). See docAPM3 PREFETCHW event=0x4b,umask=2  00     ls_pref_instr_disp.prefetch memory Software Prefetch Instructions Dispatched (Speculative). Prefetch_T0_T1_T2. PrefetchT0, T1 and T2 instructions. See docAPM3 PREFETCHlevel event=0x4b,umask=1  00     ls_sw_pf_dc_fill.ls_mabresp_rmt_dram memory Software Prefetch Data Cache Fills by Data Source. From DRAM (home node remote) event=0x59,umask=0x40  00     ls_sw_pf_dc_fill.ls_mabresp_rmt_cache memory Software Prefetch Data Cache Fills by Data Source. From another cache (home node remote) event=0x59,umask=0x10  00     ls_sw_pf_dc_fill.ls_mabresp_lcl_dram memory Software Prefetch Data Cache Fills by Data Source. DRAM or IO from this thread's die.  From DRAM (home node local) event=0x59,umask=8  00     ls_sw_pf_dc_fill.ls_mabresp_lcl_cache memory Software Prefetch Data Cache Fills by Data Source. From another cache (home node local) event=0x59,umask=2  00     ls_sw_pf_dc_fill.ls_mabresp_lcl_l2 memory Software Prefetch Data Cache Fills by Data Source. Local L2 hit event=0x59,umask=1  00     ls_hw_pf_dc_fill.ls_mabresp_rmt_dram memory Hardware Prefetch Data Cache Fills by Data Source. From DRAM (home node remote) event=0x5a,umask=0x40  00     ls_hw_pf_dc_fill.ls_mabresp_rmt_cache memory Hardware Prefetch Data Cache Fills by Data Source. From another cache (home node remote) event=0x5a,umask=0x10  00     ls_hw_pf_dc_fill.ls_mabresp_lcl_dram memory Hardware Prefetch Data Cache Fills by Data Source. From DRAM (home node local) event=0x5a,umask=8  00     ls_hw_pf_dc_fill.ls_mabresp_lcl_cache memory Hardware Prefetch Data Cache Fills by Data Source. From another cache (home node local) event=0x5a,umask=2  00     ls_hw_pf_dc_fill.ls_mabresp_lcl_l2 memory Hardware Prefetch Data Cache Fills by Data Source. Local L2 hit event=0x5a,umask=1  00     ls_tlb_flush memory All TLB Flushes event=0x78  00     de_dis_uop_queue_empty_di0 other Cycles where the Micro-Op Queue is empty event=0xa9  00     de_dis_uops_from_decoder other Ops dispatched from either the decoders, OpCache or both event=0xaa,umask=0xff  00     de_dis_uops_from_decoder.opcache_dispatched other Count of dispatched Ops from OpCache event=0xaa,umask=2  00     de_dis_uops_from_decoder.decoder_dispatched other Count of dispatched Ops from Decoder event=0xaa,umask=1  00     de_dis_dispatch_token_stalls1.fp_misc_rsrc_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. FP Miscellaneous resource unavailable. Applies to the recovery of mispredicts with FP ops event=0xae,umask=0x80  00     de_dis_dispatch_token_stalls1.fp_sch_rsrc_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. FP scheduler resource stall. Applies to ops that use the FP scheduler event=0xae,umask=0x40  00     de_dis_dispatch_token_stalls1.fp_reg_file_rsrc_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Floating point register file resource stall. Applies to all FP ops that have a destination register event=0xae,umask=0x20  00     de_dis_dispatch_token_stalls1.taken_branch_buffer_rsrc_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Taken branch buffer resource stall event=0xae,umask=0x10  00     de_dis_dispatch_token_stalls1.int_sched_misc_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Integer Scheduler miscellaneous resource stall event=0xae,umask=8  00     de_dis_dispatch_token_stalls1.store_queue_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Store queue resource stall. Applies to all ops with store semantics event=0xae,umask=4  00     de_dis_dispatch_token_stalls1.load_queue_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Load queue resource stall. Applies to all ops with load semantics event=0xae,umask=2  00     de_dis_dispatch_token_stalls1.int_phy_reg_file_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Integer Physical Register File resource stall. Applies to all ops that have an integer destination register event=0xae,umask=1  00     de_dis_dispatch_token_stalls0.sc_agu_dispatch_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. SC AGU dispatch stall event=0xaf,umask=0x40  00     de_dis_dispatch_token_stalls0.retire_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. RETIRE Tokens unavailable event=0xaf,umask=0x20  00     de_dis_dispatch_token_stalls0.agsq_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. AGSQ Tokens unavailable event=0xaf,umask=0x10  00     de_dis_dispatch_token_stalls0.alu_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALU tokens total unavailable event=0xaf,umask=8  00     de_dis_dispatch_token_stalls0.alsq3_0_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ3_0_TokenStall event=0xaf,umask=4  00     bp_dyn_ind_pred branch Dynamic Indirect Predictions event=0x8e  00    The number of times a branch used the indirect predictor to make a prediction bp_de_redirect branch Decode Redirects event=0x91  00    The number of times the instruction decoder overrides the predicted target bp_l1_tlb_fetch_hit.if1g branch The number of instruction fetches that hit in the L1 ITLB. L1 Instruction TLB hit (1G page size) event=0x94,umask=4  00     bp_l1_tlb_fetch_hit.if2m branch The number of instruction fetches that hit in the L1 ITLB. L1 Instruction TLB hit (2M page size) event=0x94,umask=2  00     bp_l1_tlb_fetch_hit.if4k branch The number of instruction fetches that hit in the L1 ITLB. L1 Instrcution TLB hit (4K or 16K page size) event=0x94,umask=1  00     l2_cache_req_stat.ls_rd_blk_l_hit_x cache Core to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit in L2. Modifiable event=0x64,umask=0x40  00     l2_cache_req_stat.ls_rd_blk_l_hit_s cache Core to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit non-modifiable line in L2 event=0x64,umask=0x20  00     l2_cache_req_stat.ls_rd_blk_c cache Core to L2 cacheable request access status (not including L2 Prefetch). Data cache request miss in L2 (all types). Use l2_cache_misses_from_dc_misses instead event=0x64,umask=8  00     l2_cache_req_stat.ic_fill_hit_s cache Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit non-modifiable line in L2 event=0x64,umask=2  00     l2_cache_req_stat.ic_fill_miss cache Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2. Use l2_cache_misses_from_ic_miss instead event=0x64,umask=1  00     l2_pf_miss_l2_l3 cache L2 prefetcher misses in L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches event=0x72,umask=0xff  00     ic_cache_fill_l2 cache Instruction Cache Refills from L2. The number of 64 byte instruction cache line was fulfilled from the L2 cache event=0x82  00     ic_cache_fill_sys cache Instruction Cache Refills from System. The number of 64 byte instruction cache line fulfilled from system memory or another cache event=0x83  00     bp_l1_tlb_miss_l2_tlb_hit cache L1 ITLB Miss, L2 ITLB Hit. The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB event=0x84  00     bp_l1_tlb_miss_l2_tlb_miss.coalesced_4k cache The number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses. Walk for >4K Coalesced page event=0x85,umask=8  00     bp_l1_tlb_miss_l2_tlb_miss.if1g cache The number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses. Walk for 1G page event=0x85,umask=4  00     bp_l1_tlb_miss_l2_tlb_miss.if2m cache The number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses. Walk for 2M page event=0x85,umask=2  00     bp_l1_tlb_miss_l2_tlb_miss.if4k cache The number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses. Walk to 4K page event=0x85,umask=1  00     ic_tag_hit_miss.all_instruction_cache_accesses cache All Instruction Cache Accesses. Counts various IC tag related hit and miss events event=0x18e,umask=0x1f  00     ic_tag_hit_miss.instruction_cache_miss cache Instruction Cache Miss. Counts various IC tag related hit and miss events event=0x18e,umask=0x18  00     ic_tag_hit_miss.instruction_cache_hit cache Instruction Cache Hit. Counts various IC tag related hit and miss events event=0x18e,umask=7  00     op_cache_hit_miss.all_op_cache_accesses cache All Op Cache accesses. Counts Op Cache micro-tag hit/miss events event=0x28f,umask=7  00     op_cache_hit_miss.op_cache_miss cache Op Cache Miss. Counts Op Cache micro-tag hit/miss events event=0x28f,umask=4  00     op_cache_hit_miss.op_cache_hit cache Op Cache Hit. Counts Op Cache micro-tag hit/miss events event=0x28f,umask=3  00     l3_lookup_state.all_l3_req_typs cache All L3 Request Types. All L3 cache Requests event=4,umask=0xff  00     xi_ccx_sdp_req1 cache L3 Misses by Request Type. Ignores SliceID, EnAllSlices, CoreID, EnAllCores and ThreadMask. Requires unit mask 0xFF to engage event for counting event=0x9a,umask=0xff  00     ex_ret_ops core Retired Ops. Use macro_ops_retired instead event=0xc1  00    The number of macro-ops retired ex_ret_brn_misp core Retired Branch Instructions Mispredicted event=0xc3  00    The number of retired branch instructions, that were mispredicted ex_ret_brn_ind_misp core Retired Indirect Branch Instructions Mispredicted event=0xca  00    The number of indirect branches retired that were not correctly predicted. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction. Note that only EX mispredicts are counted ex_ret_mmx_fp_instr.sse_instr core SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX) event=0xcb,umask=4  00    The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS ex_ret_ind_brch_instr core Retired Indirect Branch Instructions. The number of indirect branches retired event=0xcc  00     ex_ret_msprd_brnch_instr_dir_msmtch core Retired Mispredicted Branch Instructions due to Direction Mismatch event=0x1c7  00    The number of retired conditional branch instructions that were not correctly predicted because of a branch direction mismatch ex_ret_fused_instr core Counts retired Fused Instructions event=0x1d0  00     fp_ret_sse_avx_ops.mac_flops floating point Multiply-Accumulate FLOPs. Each MAC operation is counted as 2 FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEvent event=3,umask=8  00     fp_ret_sse_avx_ops.div_flops floating point Divide/square root FLOPs. This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEvent event=3,umask=4  00     fp_ret_sse_avx_ops.mult_flops floating point Multiply FLOPs. This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEvent event=3,umask=2  00     fp_ret_sse_avx_ops.add_sub_flops floating point Add/subtract FLOPs. This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEvent event=3,umask=1  00     fp_retired_ser_ops.sse_bot_ret floating point SSE/AVX bottom-executing ops retired. The number of serializing Ops retired event=5,umask=8  00     fp_retired_ser_ops.sse_ctrl_ret floating point SSE/AVX control word mispredict traps. The number of serializing Ops retired event=5,umask=4  00     fp_retired_ser_ops.x87_bot_ret floating point x87 bottom-executing ops retired. The number of serializing Ops retired event=5,umask=2  00     ls_locks.bus_lock memory Retired lock instructions. Comparable to legacy bus lock event=0x25,umask=1  00     ls_ret_cl_flush memory The number of retired CLFLUSH instructions. This is a non-speculative event event=0x26  00     ls_ret_cpuid memory The number of CPUID instructions retired event=0x27  00     ls_dispatch.ld_st_dispatch memory Load-op-Store Dispatch. Dispatch of a single op that performs a load from and store to the same memory address. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed event=0x29,umask=4  00     ls_dispatch.store_dispatch memory Dispatch of a single op that performs a memory store. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed event=0x29,umask=2  00     ls_dispatch.ld_dispatch memory Dispatch of a single op that performs a memory load. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed event=0x29,umask=1  00     ls_smi_rx memory Counts the number of SMIs received event=0x2b  00     ls_int_taken memory Counts the number of interrupts taken event=0x2c  00     ls_st_commit_cancel2.st_commit_cancel_wcb_full memory A non-cacheable store and the non-cacheable commit buffer is full event=0x37,umask=1  00     ls_mab_alloc.all_allocations memory All Allocations. Counts when a LS pipe allocates a MAB entry event=0x41,umask=0x7f  00     ls_mab_alloc.hardware_prefetcher_allocations memory Hardware Prefetcher Allocations. Counts when a LS pipe allocates a MAB entry event=0x41,umask=0x40  00     ls_mab_alloc.load_store_allocations memory Load Store Allocations. Counts when a LS pipe allocates a MAB entry event=0x41,umask=0x3f  00     ls_dmnd_fills_from_sys.mem_io_remote memory Demand Data Cache Fills by Data Source. From DRAM or IO connected in different Node event=0x43,umask=0x40  00     ls_dmnd_fills_from_sys.ext_cache_remote memory Demand Data Cache Fills by Data Source. From CCX Cache in different Node event=0x43,umask=0x10  00     ls_dmnd_fills_from_sys.mem_io_local memory Demand Data Cache Fills by Data Source. From DRAM or IO connected in same node event=0x43,umask=8  00     ls_dmnd_fills_from_sys.ext_cache_local memory Demand Data Cache Fills by Data Source. From cache of different CCX in same node event=0x43,umask=4  00     ls_dmnd_fills_from_sys.int_cache memory Demand Data Cache Fills by Data Source. From L3 or different L2 in same CCX event=0x43,umask=2  00     ls_dmnd_fills_from_sys.lcl_l2 memory Demand Data Cache Fills by Data Source. From Local L2 to the core event=0x43,umask=1  00     ls_any_fills_from_sys.mem_io_remote memory Any Data Cache Fills by Data Source. From DRAM or IO connected in different Node event=0x44,umask=0x40  00     ls_any_fills_from_sys.ext_cache_remote memory Any Data Cache Fills by Data Source. From CCX Cache in different Node event=0x44,umask=0x10  00     ls_any_fills_from_sys.mem_io_local memory Any Data Cache Fills by Data Source. From DRAM or IO connected in same node event=0x44,umask=8  00     ls_any_fills_from_sys.ext_cache_local memory Any Data Cache Fills by Data Source. From cache of different CCX in same node event=0x44,umask=4  00     ls_any_fills_from_sys.int_cache memory Any Data Cache Fills by Data Source. From L3 or different L2 in same CCX event=0x44,umask=2  00     ls_any_fills_from_sys.lcl_l2 memory Any Data Cache Fills by Data Source. From Local L2 to the core event=0x44,umask=1  00     ls_l1_d_tlb_miss.all memory All L1 DTLB Misses or Reloads. Use l1_dtlb_misses instead event=0x45,umask=0xff  00     ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss memory L1 DTLB Miss. DTLB reload to a 1G page that also missed in the L2 TLB event=0x45,umask=0x80  00     ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss memory L1 DTLB Miss. DTLB reload to a 2M page that also missed in the L2 TLB event=0x45,umask=0x40  00     ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss memory L1 DTLB Miss. DTLB reload coalesced page that also missed in the L2 TLB event=0x45,umask=0x20  00     ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss memory L1 DTLB Miss. DTLB reload to a 4K page that missed the L2 TLB event=0x45,umask=0x10  00     ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit memory L1 DTLB Miss. DTLB reload to a coalesced page that hit in the L2 TLB event=0x45,umask=2  00     ls_misal_loads.ma4k memory The number of 4KB misaligned (i.e., page crossing) loads event=0x47,umask=2  00     ls_misal_loads.ma64 memory The number of 64B misaligned (i.e., cacheline crossing) loads event=0x47,umask=1  00     ls_pref_instr_disp.prefetch_w memory Software Prefetch Instructions Dispatched (Speculative). PrefetchW instruction. See docAPM3 PREFETCHW event=0x4b,umask=2  00     ls_pref_instr_disp.prefetch memory Software Prefetch Instructions Dispatched (Speculative). PrefetchT0, T1 and T2 instructions. See docAPM3 PREFETCHlevel event=0x4b,umask=1  00     ls_sw_pf_dc_fills.mem_io_remote memory Software Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in different Node event=0x59,umask=0x40  00     ls_sw_pf_dc_fills.ext_cache_remote memory Software Prefetch Data Cache Fills by Data Source. From CCX Cache in different Node event=0x59,umask=0x10  00     ls_sw_pf_dc_fills.mem_io_local memory Software Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in same node event=0x59,umask=8  00     ls_sw_pf_dc_fills.ext_cache_local memory Software Prefetch Data Cache Fills by Data Source. From cache of different CCX in same node event=0x59,umask=4  00     ls_sw_pf_dc_fills.int_cache memory Software Prefetch Data Cache Fills by Data Source. From L3 or different L2 in same CCX event=0x59,umask=2  00     ls_sw_pf_dc_fills.lcl_l2 memory Software Prefetch Data Cache Fills by Data Source. From Local L2 to the core event=0x59,umask=1  00     ls_hw_pf_dc_fills.mem_io_remote memory Hardware Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in different Node event=0x5a,umask=0x40  00     ls_hw_pf_dc_fills.ext_cache_remote memory Hardware Prefetch Data Cache Fills by Data Source. From CCX Cache in different Node event=0x5a,umask=0x10  00     ls_hw_pf_dc_fills.mem_io_local memory Hardware Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in same node event=0x5a,umask=8  00     ls_hw_pf_dc_fills.ext_cache_local memory Hardware Prefetch Data Cache Fills by Data Source. From cache of different CCX in same node event=0x5a,umask=4  00     ls_hw_pf_dc_fills.int_cache memory Hardware Prefetch Data Cache Fills by Data Source. From L3 or different L2 in same CCX event=0x5a,umask=2  00     ls_hw_pf_dc_fills.lcl_l2 memory Hardware Prefetch Data Cache Fills by Data Source. From Local L2 to the core event=0x5a,umask=1  00     ls_alloc_mab_count memory Count of Allocated Mabs event=0x5f  00    This event counts the in-flight L1 data cache misses (allocated Miss Address Buffers) divided by 4 and rounded down each cycle unless used with the MergeEvent functionality. If the MergeEvent is used, it counts the exact number of outstanding L1 data cache misses. See 2.1.17.3 [Large Increment per Cycle Events] ls_tlb_flush.all_tlb_flushes memory All TLB Flushes. Requires unit mask 0xFF to engage event for counting. Use all_tlbs_flushed instead event=0x78,umask=0xff  00     de_dis_cops_from_decoder.disp_op_type.any_integer_dispatch other Any Integer dispatch. Types of Oops Dispatched from Decoder event=0xab,umask=8  00     de_dis_cops_from_decoder.disp_op_type.any_fp_dispatch other Any FP dispatch. Types of Oops Dispatched from Decoder event=0xab,umask=4  00     de_dis_dispatch_token_stalls1.fp_flush_recovery_stall other Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. FP Flush recovery stall event=0xae,umask=0x80  00     de_dis_dispatch_token_stalls1.fp_sch_rsrc_stall other Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. FP scheduler resource stall. Applies to ops that use the FP scheduler event=0xae,umask=0x40  00     de_dis_dispatch_token_stalls1.fp_reg_file_rsrc_stall other Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Floating point register file resource stall. Applies to all FP ops that have a destination register event=0xae,umask=0x20  00     de_dis_dispatch_token_stalls1.taken_brnch_buffer_rsrc other Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Taken branch buffer resource stall event=0xae,umask=0x10  00     de_dis_dispatch_token_stalls1.store_queue_rsrc_stall other Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Store Queue resource stall. Applies to all ops with store semantics event=0xae,umask=4  00     de_dis_dispatch_token_stalls1.load_queue_rsrc_stall other Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Load Queue resource stall. Applies to all ops with load semantics event=0xae,umask=2  00     de_dis_dispatch_token_stalls1.int_phy_reg_file_rsrc_stall other Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Integer Physical Register File resource stall. Integer Physical Register File, applies to all ops that have an integer destination register event=0xae,umask=1  00     de_dis_dispatch_token_stalls2.retire_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Insufficient Retire Queue tokens available event=0xaf,umask=0x20  00     de_dis_dispatch_token_stalls2.agsq_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. AGSQ Tokens unavailable event=0xaf,umask=0x10  00     de_dis_dispatch_token_stalls2.int_sch3_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. No tokens for Integer Scheduler Queue 3 available event=0xaf,umask=8  00     de_dis_dispatch_token_stalls2.int_sch2_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. No tokens for Integer Scheduler Queue 2 available event=0xaf,umask=4  00     de_dis_dispatch_token_stalls2.int_sch1_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. No tokens for Integer Scheduler Queue 1 available event=0xaf,umask=2  00     de_dis_dispatch_token_stalls2.int_sch0_token_stall other Cycles where a dispatch group is valid but does not get dispatched due to a token stall. No tokens for Integer Scheduler Queue 0 available event=0xaf,umask=1  00     all_data_cache_accesses recommended All L1 Data Cache Accesses event=0x29,umask=7  00     l2_cache_accesses_from_dc_misses recommended L2 Cache Accesses from L1 Data Cache Misses (including prefetch) event=0x60,umask=0xe8  00     l2_cache_hits_from_dc_misses recommended L2 Cache Hits from L1 Data Cache Misses event=0x64,umask=0xf0  00     l2_cache_hits_from_l2_hwpf recommended L2 Cache Hits from L2 Cache HWPF event=0x70,umask=0xff  00     l3_cache_accesses recommended L3 Cache Accesses event=4,umask=0xff  00     l3_misses recommended L3 Misses (includes cacheline state change requests) event=4,umask=1  00     l1_data_cache_fills_from_memory recommended L1 Data Cache Fills: From Memory event=0x44,umask=0x48  00     l1_data_cache_fills_from_remote_node recommended L1 Data Cache Fills: From Remote Node event=0x44,umask=0x50  00     l1_data_cache_fills_from_within_same_ccx recommended L1 Data Cache Fills: From within same CCX event=0x44,umask=3  00     l1_data_cache_fills_from_external_ccx_cache recommended L1 Data Cache Fills: From External CCX Cache event=0x44,umask=0x14  00     l1_data_cache_fills_all recommended L1 Data Cache Fills: All event=0x44,umask=0xff  00     all_tlbs_flushed recommended All TLBs Flushed event=0x78,umask=0xff  00     macro_ops_retired recommended Macro-ops Retired event=0xc1  00     bp_l2_btb_correct branch L2 branch prediction overrides existing prediction (speculative) event=0x8b  00     bp_dyn_ind_pred branch Dynamic indirect predictions (branch used the indirect predictor to make a prediction) event=0x8e  00     bp_de_redirect branch Instruction decoder corrects the predicted target and resteers the branch predictor event=0x91  00     ex_ret_brn branch Retired branch instructions (all types of architectural control flow changes, including exceptions and interrupts) event=0xc2  00     ex_ret_brn_misp branch Retired branch instructions mispredicted event=0xc3  00     ex_ret_brn_tkn branch Retired taken branch instructions (all types of architectural control flow changes, including exceptions and interrupts) event=0xc4  00     ex_ret_brn_tkn_misp branch Retired taken branch instructions mispredicted event=0xc5  00     ex_ret_brn_far branch Retired far control transfers (far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts). Far control transfers are not subject to branch prediction event=0xc6  00     ex_ret_near_ret branch Retired near returns (RET or RET Iw) event=0xc8  00     ex_ret_near_ret_mispred branch Retired near returns mispredicted. Each misprediction incurs the same penalty as a mispredicted conditional branch instruction event=0xc9  00     ex_ret_brn_ind_misp branch Retired indirect branch instructions mispredicted (only EX mispredicts). Each misprediction incurs the same penalty as a mispredicted conditional branch instruction event=0xca  00     ex_ret_ind_brch_instr branch Retired indirect branch instructions event=0xcc  00     ex_ret_cond branch Retired conditional branch instructions event=0xd1  00     ex_ret_msprd_brnch_instr_dir_msmtch branch Retired branch instructions mispredicted due to direction mismatch event=0x1c7  00     ex_ret_uncond_brnch_instr_mispred branch Retired unconditional indirect branch instructions mispredicted event=0x1c8  00     ex_ret_uncond_brnch_instr branch Retired unconditional branch instructions event=0x1c9  00     ls_mab_alloc.load_store_allocations cache Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for load-store allocations event=0x41,umask=0x3f  00     ls_mab_alloc.hardware_prefetcher_allocations cache Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for hardware prefetcher allocations event=0x41,umask=0x40  00     ls_mab_alloc.all_allocations cache Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for all types of allocations event=0x41,umask=0x7f  00     ls_dmnd_fills_from_sys.local_l2 cache Demand data cache fills from local L2 cache event=0x43,umask=1  00     ls_dmnd_fills_from_sys.local_ccx cache Demand data cache fills from L3 cache or different L2 cache in the same CCX event=0x43,umask=2  00     ls_dmnd_fills_from_sys.near_cache cache Demand data cache fills from cache of another CCX when the address was in the same NUMA node event=0x43,umask=4  00     ls_dmnd_fills_from_sys.dram_io_near cache Demand data cache fills from either DRAM or MMIO in the same NUMA node event=0x43,umask=8  00     ls_dmnd_fills_from_sys.far_cache cache Demand data cache fills from cache of another CCX when the address was in a different NUMA node event=0x43,umask=0x10  00     ls_dmnd_fills_from_sys.dram_io_far cache Demand data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket) event=0x43,umask=0x40  00     ls_dmnd_fills_from_sys.alternate_memories cache Demand data cache fills from extension memory event=0x43,umask=0x80  00     ls_dmnd_fills_from_sys.all cache Demand data cache fills from all types of data sources event=0x43,umask=0xff  00     ls_any_fills_from_sys.local_l2 cache Any data cache fills from local L2 cache event=0x44,umask=1  00     ls_any_fills_from_sys.local_ccx cache Any data cache fills from L3 cache or different L2 cache in the same CCX event=0x44,umask=2  00     ls_any_fills_from_sys.local_all cache Any data cache fills from local L2 cache or L3 cache or different L2 cache in the same CCX event=0x44,umask=3  00     ls_any_fills_from_sys.near_cache cache Any data cache fills from cache of another CCX when the address was in the same NUMA node event=0x44,umask=4  00     ls_any_fills_from_sys.dram_io_near cache Any data cache fills from either DRAM or MMIO in the same NUMA node event=0x44,umask=8  00     ls_any_fills_from_sys.far_cache cache Any data cache fills from cache of another CCX when the address was in a different NUMA node event=0x44,umask=0x10  00     ls_any_fills_from_sys.remote_cache cache Any data cache fills from cache of another CCX when the address was in the same or a different NUMA node event=0x44,umask=0x14  00     ls_any_fills_from_sys.dram_io_far cache Any data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket) event=0x44,umask=0x40  00     ls_any_fills_from_sys.dram_io_all cache Any data cache fills from either DRAM or MMIO in any NUMA node (same or different socket) event=0x44,umask=0x48  00     ls_any_fills_from_sys.far_all cache Any data cache fills from either cache of another CCX, DRAM or MMIO when the address was in a different NUMA node (same or different socket) event=0x44,umask=0x50  00     ls_any_fills_from_sys.all_dram_io cache Any data cache fills from either DRAM or MMIO in any NUMA node (same or different socket) event=0x44,umask=0x48  00     ls_any_fills_from_sys.alternate_memories cache Any data cache fills from extension memory event=0x44,umask=0x80  00     ls_any_fills_from_sys.all cache Any data cache fills from all types of data sources event=0x44,umask=0xff  00     ls_pref_instr_disp.prefetch cache Software prefetch instructions dispatched (speculative) of type PrefetchT0 (move data to all cache levels), T1 (move data to all cache levels except L1) and T2 (move data to all cache levels except L1 and L2) event=0x4b,umask=1  00     ls_pref_instr_disp.prefetch_w cache Software prefetch instructions dispatched (speculative) of type PrefetchW (move data to L1 cache and mark it modifiable) event=0x4b,umask=2  00     ls_pref_instr_disp.prefetch_nta cache Software prefetch instructions dispatched (speculative) of type PrefetchNTA (move data with minimum cache pollution i.e. non-temporal access) event=0x4b,umask=4  00     ls_pref_instr_disp.all cache Software prefetch instructions dispatched (speculative) of all types event=0x4b,umask=7  00     ls_inef_sw_pref.data_pipe_sw_pf_dc_hit cache Software prefetches that did not fetch data outside of the processor core as the PREFETCH instruction saw a data cache hit event=0x52,umask=1  00     ls_inef_sw_pref.mab_mch_cnt cache Software prefetches that did not fetch data outside of the processor core as the PREFETCH instruction saw a match on an already allocated Miss Address Buffer (MAB) event=0x52,umask=2  00     ls_inef_sw_pref.all cache  event=0x52,umask=3  00     ls_sw_pf_dc_fills.local_l2 cache Software prefetch data cache fills from local L2 cache event=0x59,umask=1  00     ls_sw_pf_dc_fills.local_ccx cache Software prefetch data cache fills from L3 cache or different L2 cache in the same CCX event=0x59,umask=2  00     ls_sw_pf_dc_fills.near_cache cache Software prefetch data cache fills from cache of another CCX in the same NUMA node event=0x59,umask=4  00     ls_sw_pf_dc_fills.dram_io_near cache Software prefetch data cache fills from either DRAM or MMIO in the same NUMA node event=0x59,umask=8  00     ls_sw_pf_dc_fills.far_cache cache Software prefetch data cache fills from cache of another CCX in a different NUMA node event=0x59,umask=0x10  00     ls_sw_pf_dc_fills.dram_io_far cache Software prefetch data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket) event=0x59,umask=0x40  00     ls_sw_pf_dc_fills.alternate_memories cache Software prefetch data cache fills from extension memory event=0x59,umask=0x80  00     ls_sw_pf_dc_fills.all cache Software prefetch data cache fills from all types of data sources event=0x59,umask=0xdf  00     ls_hw_pf_dc_fills.local_l2 cache Hardware prefetch data cache fills from local L2 cache event=0x5a,umask=1  00     ls_hw_pf_dc_fills.local_ccx cache Hardware prefetch data cache fills from L3 cache or different L2 cache in the same CCX event=0x5a,umask=2  00     ls_hw_pf_dc_fills.near_cache cache Hardware prefetch data cache fills from cache of another CCX when the address was in the same NUMA node event=0x5a,umask=4  00     ls_hw_pf_dc_fills.dram_io_near cache Hardware prefetch data cache fills from either DRAM or MMIO in the same NUMA node event=0x5a,umask=8  00     ls_hw_pf_dc_fills.far_cache cache Hardware prefetch data cache fills from cache of another CCX when the address was in a different NUMA node event=0x5a,umask=0x10  00     ls_hw_pf_dc_fills.dram_io_far cache Hardware prefetch data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket) event=0x5a,umask=0x40  00     ls_hw_pf_dc_fills.alternate_memories cache Hardware prefetch data cache fills from extension memory event=0x5a,umask=0x80  00     ls_hw_pf_dc_fills.all cache Hardware prefetch data cache fills from all types of data sources event=0x5a,umask=0xdf  00     ls_alloc_mab_count cache In-flight L1 data cache misses i.e. Miss Address Buffer (MAB) allocations each cycle event=0x5f  00     l2_request_g1.group2 cache L2 cache requests of non-cacheable type (non-cached data and instructions reads, self-modifying code checks) event=0x60,umask=1  00     l2_request_g1.l2_hw_pf cache L2 cache requests: from hardware prefetchers to prefetch directly into L2 (hit or miss) event=0x60,umask=2  00     l2_request_g1.prefetch_l2_cmd cache L2 cache requests: prefetch directly into L2 event=0x60,umask=4  00     l2_request_g1.change_to_x cache L2 cache requests: data cache state change to writable, check L2 for current state event=0x60,umask=8  00     l2_request_g1.cacheable_ic_read cache L2 cache requests: instruction cache reads event=0x60,umask=0x10  00     l2_request_g1.ls_rd_blk_c_s cache L2 cache requests: data cache shared reads event=0x60,umask=0x20  00     l2_request_g1.rd_blk_x cache L2 cache requests: data cache stores event=0x60,umask=0x40  00     l2_request_g1.rd_blk_l cache L2 cache requests: data cache reads including hardware and software prefetch event=0x60,umask=0x80  00     l2_request_g1.all_dc cache L2 cache requests of common types from L1 data cache (including prefetches) event=0x60,umask=0xe8  00     l2_request_g1.all_no_prefetch cache L2 cache requests of common types not including prefetches event=0x60,umask=0xf9  00     l2_request_g1.all cache L2 cache requests of all types event=0x60,umask=0xff  00     l2_cache_req_stat.ic_fill_miss cache Core to L2 cache requests (not including L2 prefetch) with status: instruction cache request miss in L2 event=0x64,umask=1  00     l2_cache_req_stat.ic_fill_hit_s cache Core to L2 cache requests (not including L2 prefetch) with status: instruction cache hit non-modifiable line in L2 event=0x64,umask=2  00     l2_cache_req_stat.ic_fill_hit_x cache Core to L2 cache requests (not including L2 prefetch) with status: instruction cache hit modifiable line in L2 event=0x64,umask=4  00     l2_cache_req_stat.ic_hit_in_l2 cache Core to L2 cache requests (not including L2 prefetch) for instruction cache hits event=0x64,umask=6  00     l2_cache_req_stat.ic_access_in_l2 cache Core to L2 cache requests (not including L2 prefetch) for instruction cache access event=0x64,umask=7  00     l2_cache_req_stat.ls_rd_blk_c cache Core to L2 cache requests (not including L2 prefetch) with status: data cache request miss in L2 event=0x64,umask=8  00     l2_cache_req_stat.ic_dc_miss_in_l2 cache Core to L2 cache requests (not including L2 prefetch) for data and instruction cache misses event=0x64,umask=9  00     l2_cache_req_stat.ls_rd_blk_x cache Core to L2 cache requests (not including L2 prefetch) with status: data cache store or state change hit in L2 event=0x64,umask=0x10  00     l2_cache_req_stat.ls_rd_blk_l_hit_s cache Core to L2 cache requests (not including L2 prefetch) with status: data cache read hit non-modifiable line in L2 event=0x64,umask=0x20  00     l2_cache_req_stat.ls_rd_blk_l_hit_x cache Core to L2 cache requests (not including L2 prefetch) with status: data cache read hit modifiable line in L2 event=0x64,umask=0x40  00     l2_cache_req_stat.ls_rd_blk_cs cache Core to L2 cache requests (not including L2 prefetch) with status: data cache shared read hit in L2 event=0x64,umask=0x80  00     l2_cache_req_stat.dc_hit_in_l2 cache Core to L2 cache requests (not including L2 prefetch) for data cache hits event=0x64,umask=0xf0  00     l2_cache_req_stat.ic_dc_hit_in_l2 cache Core to L2 cache requests (not including L2 prefetch) for data and instruction cache hits event=0x64,umask=0xf6  00     l2_cache_req_stat.dc_access_in_l2 cache Core to L2 cache requests (not including L2 prefetch) for data cache access event=0x64,umask=0xf8  00     l2_cache_req_stat.all cache Core to L2 cache requests (not including L2 prefetch) for data and instruction cache access event=0x64,umask=0xff  00     l2_pf_hit_l2.l2_stream cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2Stream (fetch additional sequential lines into L2 cache) event=0x70,umask=1  00     l2_pf_hit_l2.l2_next_line cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2NextLine (fetch the next line into L2 cache) event=0x70,umask=2  00     l2_pf_hit_l2.l2_up_down cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2UpDown (fetch the next or previous line into L2 cache for all memory accesses) event=0x70,umask=4  00     l2_pf_hit_l2.l2_burst cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2Burst (aggressively fetch additional sequential lines into L2 cache) event=0x70,umask=8  00     l2_pf_hit_l2.l2_stride cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2Stride (fetch additional lines into L2 cache when each access is at a constant distance from the previous) event=0x70,umask=0x10  00     l2_pf_hit_l2.l1_stream cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L1Stream (fetch additional sequential lines into L1 cache) event=0x70,umask=0x20  00     l2_pf_hit_l2.l1_stride cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L1Stride (fetch additional lines into L1 cache when each access is a constant distance from the previous) event=0x70,umask=0x40  00     l2_pf_hit_l2.l1_region cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L1Region (fetch additional lines into L1 cache when the data access for a given instruction tends to be followed by a consistent pattern of other accesses within a localized region) event=0x70,umask=0x80  00     l2_pf_hit_l2.all cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of all types event=0x70,umask=0xff  00     l2_pf_miss_l2_hit_l3.l2_stream cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2Stream (fetch additional sequential lines into L2 cache) event=0x71,umask=1  00     l2_pf_miss_l2_hit_l3.l2_next_line cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2NextLine (fetch the next line into L2 cache) event=0x71,umask=2  00     l2_pf_miss_l2_hit_l3.l2_up_down cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2UpDown (fetch the next or previous line into L2 cache for all memory accesses) event=0x71,umask=4  00     l2_pf_miss_l2_hit_l3.l2_burst cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2Burst (aggressively fetch additional sequential lines into L2 cache) event=0x71,umask=8  00     l2_pf_miss_l2_hit_l3.l2_stride cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2Stride (fetch additional lines into L2 cache when each access is a constant distance from the previous) event=0x71,umask=0x10  00     l2_pf_miss_l2_hit_l3.l1_stream cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L1Stream (fetch additional sequential lines into L1 cache) event=0x71,umask=0x20  00     l2_pf_miss_l2_hit_l3.l1_stride cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L1Stride (fetch additional lines into L1 cache when each access is a constant distance from the previous) event=0x71,umask=0x40  00     l2_pf_miss_l2_hit_l3.l1_region cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L1Region (fetch additional lines into L1 cache when the data access for a given instruction tends to be followed by a consistent pattern of other accesses within a localized region) event=0x71,umask=0x80  00     l2_pf_miss_l2_hit_l3.all cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache cache of all types event=0x71,umask=0xff  00     l2_pf_miss_l2_l3.l2_stream cache L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2Stream (fetch additional sequential lines into L2 cache) event=0x72,umask=1  00     l2_pf_miss_l2_l3.l2_next_line cache L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2NextLine (fetch the next line into L2 cache) event=0x72,umask=2  00     l2_pf_miss_l2_l3.l2_up_down cache L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2UpDown (fetch the next or previous line into L2 cache for all memory accesses) event=0x72,umask=4  00     l2_pf_miss_l2_l3.l2_burst cache L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2Burst (aggressively fetch additional sequential lines into L2 cache) event=0x72,umask=8  00     l2_pf_miss_l2_l3.l2_stride cache L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2Stride (fetch additional lines into L2 cache when each access is a constant distance from the previous) event=0x72,umask=0x10  00     l2_pf_miss_l2_l3.l1_stream cache L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L1Stream (fetch additional sequential lines into L1 cache) event=0x72,umask=0x20  00     l2_pf_miss_l2_l3.l1_stride cache L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L1Stride (fetch additional lines into L1 cache when each access is a constant distance from the previous) event=0x72,umask=0x40  00     l2_pf_miss_l2_l3.l1_region cache L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L1Region (fetch additional lines into L1 cache when the data access for a given instruction tends to be followed by a consistent pattern of other accesses within a localized region) event=0x72,umask=0x80  00     l2_pf_miss_l2_l3.all cache L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of all types event=0x72,umask=0xff  00     ic_cache_fill_l2 cache Instruction cache lines (64 bytes) fulfilled from the L2 cache event=0x82  00     ic_cache_fill_sys cache Instruction cache lines (64 bytes) fulfilled from system memory or another cache event=0x83  00     ic_tag_hit_miss.instruction_cache_hit cache Instruction cache hits event=0x18e,umask=7  00     ic_tag_hit_miss.instruction_cache_miss cache Instruction cache misses event=0x18e,umask=0x18  00     ic_tag_hit_miss.all_instruction_cache_accesses cache Instruction cache accesses of all types event=0x18e,umask=0x1f  00     op_cache_hit_miss.op_cache_hit cache Op cache hits event=0x28f,umask=3  00     op_cache_hit_miss.op_cache_miss cache Op cache misses event=0x28f,umask=4  00     op_cache_hit_miss.all_op_cache_accesses cache Op cache accesses of all types event=0x28f,umask=7  00     l3_lookup_state.l3_miss cache L3 cache misses event=4,umask=1  00     l3_lookup_state.l3_hit cache L3 cache hits event=4,umask=0xfe  00     l3_lookup_state.all_coherent_accesses_to_l3 cache L3 cache requests for all coherent accesses event=4,umask=0xff  00     l3_xi_sampled_latency.dram_near cache Average sampled latency when data is sourced from DRAM in the same NUMA node event=0xac,umask=1,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency.dram_far cache Average sampled latency when data is sourced from DRAM in a different NUMA node event=0xac,umask=2,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency.near_cache cache Average sampled latency when data is sourced from another CCX's cache when the address was in the same NUMA node event=0xac,umask=4,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency.far_cache cache Average sampled latency when data is sourced from another CCX's cache when the address was in a different NUMA node event=0xac,umask=8,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency.ext_near cache Average sampled latency when data is sourced from extension memory (CXL) in the same NUMA node event=0xac,umask=0x10,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency.ext_far cache Average sampled latency when data is sourced from extension memory (CXL) in a different NUMA node event=0xac,umask=0x20,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency.all cache Average sampled latency from all data sources event=0xac,umask=0x3f,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency_requests.dram_near cache L3 cache fill requests sourced from DRAM in the same NUMA node event=0xad,umask=1,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency_requests.dram_far cache L3 cache fill requests sourced from DRAM in a different NUMA node event=0xad,umask=2,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency_requests.near_cache cache L3 cache fill requests sourced from another CCX's cache when the address was in the same NUMA node event=0xad,umask=4,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency_requests.far_cache cache L3 cache fill requests sourced from another CCX's cache when the address was in a different NUMA node event=0xad,umask=8,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency_requests.ext_near cache L3 cache fill requests sourced from extension memory (CXL) in the same NUMA node event=0xad,umask=0x10,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency_requests.ext_far cache L3 cache fill requests sourced from extension memory (CXL) in a different NUMA node event=0xad,umask=0x20,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency_requests.all cache L3 cache fill requests sourced from all data sources event=0xad,umask=0x3f,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     ls_locks.bus_lock core Retired Lock instructions which caused a bus lock event=0x25,umask=1  00     ls_ret_cl_flush core Retired CLFLUSH instructions event=0x26  00     ls_ret_cpuid core Retired CPUID instructions event=0x27  00     ls_smi_rx core SMIs received event=0x2b  00     ls_int_taken core Interrupts taken event=0x2c  00     ls_not_halted_cyc core Core cycles not in halt event=0x76  00     ex_ret_instr core Retired instructions event=0xc0  00     ex_ret_ops core Retired macro-ops event=0xc1  00     ex_div_busy core Number of cycles the divider is busy event=0xd3  00     ex_div_count core Divide ops executed event=0xd4  00     ex_no_retire.empty core Cycles with no retire due  to the lack of valid ops in the retire queue (may be caused by front-end bottlenecks or pipeline redirects) event=0xd6,umask=1  00     ex_no_retire.not_complete core Cycles with no retire while the oldest op is waiting to be executed event=0xd6,umask=2  00     ex_no_retire.other core Cycles with no retire caused by other reasons (retire breaks, traps, faults, etc.) event=0xd6,umask=8  00     ex_no_retire.thread_not_selected core Cycles with no retire because thread arbitration did not select the thread event=0xd6,umask=0x10  00     ex_no_retire.load_not_complete core Cycles with no retire while the oldest op is waiting for load data event=0xd6,umask=0xa2  00     ex_no_retire.all core Cycles with no retire for any reason event=0xd6,umask=0x1b  00     ls_not_halted_p0_cyc.p0_freq_cyc core Reference cycles (P0 frequency) not in halt  event=0x120,umask=1  00     ex_ret_ucode_instr core Retired microcoded instructions event=0x1c1  00     ex_ret_ucode_ops core Retired microcode ops event=0x1c2  00     ex_tagged_ibs_ops.ibs_tagged_ops core Ops tagged by IBS event=0x1cf,umask=1  00     ex_tagged_ibs_ops.ibs_tagged_ops_ret core Ops tagged by IBS that retired event=0x1cf,umask=2  00     ex_ret_fused_instr core Retired fused instructions event=0x1d0  00     local_processor_read_data_beats_cs0 data fabric  event=0x1f,umask=0x7fe  01    Read data beats (64 bytes) for local processor at Coherent Station (CS) 0 local_processor_read_data_beats_cs1 data fabric  event=0x5f,umask=0x7fe  01    Read data beats (64 bytes) for local processor at Coherent Station (CS) 1 local_processor_read_data_beats_cs2 data fabric  event=0x9f,umask=0x7fe  01    Read data beats (64 bytes) for local processor at Coherent Station (CS) 2 local_processor_read_data_beats_cs3 data fabric  event=0xdf,umask=0x7fe  01    Read data beats (64 bytes) for local processor at Coherent Station (CS) 3 local_processor_read_data_beats_cs4 data fabric  event=0x11f,umask=0x7fe  01    Read data beats (64 bytes) for local processor at Coherent Station (CS) 4 local_processor_read_data_beats_cs5 data fabric  event=0x15f,umask=0x7fe  01    Read data beats (64 bytes) for local processor at Coherent Station (CS) 5 local_processor_read_data_beats_cs6 data fabric  event=0x19f,umask=0x7fe  01    Read data beats (64 bytes) for local processor at Coherent Station (CS) 6 local_processor_read_data_beats_cs7 data fabric  event=0x1df,umask=0x7fe  01    Read data beats (64 bytes) for local processor at Coherent Station (CS) 7 local_processor_read_data_beats_cs8 data fabric  event=0x21f,umask=0x7fe  01    Read data beats (64 bytes) for local processor at Coherent Station (CS) 8 local_processor_read_data_beats_cs9 data fabric  event=0x25f,umask=0x7fe  01    Read data beats (64 bytes) for local processor at Coherent Station (CS) 9 local_processor_read_data_beats_cs10 data fabric  event=0x29f,umask=0x7fe  01    Read data beats (64 bytes) for local processor at Coherent Station (CS) 10 local_processor_read_data_beats_cs11 data fabric  event=0x2df,umask=0x7fe  01    Read data beats (64 bytes) for local processor at Coherent Station (CS) 11 local_processor_write_data_beats_cs0 data fabric  event=0x1f,umask=0x7ff  01    Write data beats (64 bytes) for local processor at Coherent Station (CS) 0 local_processor_write_data_beats_cs1 data fabric  event=0x5f,umask=0x7ff  01    Write data beats (64 bytes) for local processor at Coherent Station (CS) 1 local_processor_write_data_beats_cs2 data fabric  event=0x9f,umask=0x7ff  01    Write data beats (64 bytes) for local processor at Coherent Station (CS) 2 local_processor_write_data_beats_cs3 data fabric  event=0xdf,umask=0x7ff  01    Write data beats (64 bytes) for local processor at Coherent Station (CS) 3 local_processor_write_data_beats_cs4 data fabric  event=0x11f,umask=0x7ff  01    Write data beats (64 bytes) for local processor at Coherent Station (CS) 4 local_processor_write_data_beats_cs5 data fabric  event=0x15f,umask=0x7ff  01    Write data beats (64 bytes) for local processor at Coherent Station (CS) 5 local_processor_write_data_beats_cs6 data fabric  event=0x19f,umask=0x7ff  01    Write data beats (64 bytes) for local processor at Coherent Station (CS) 6 local_processor_write_data_beats_cs7 data fabric  event=0x1df,umask=0x7ff  01    Write data beats (64 bytes) for local processor at Coherent Station (CS) 7 local_processor_write_data_beats_cs8 data fabric  event=0x21f,umask=0x7ff  01    Write data beats (64 bytes) for local processor at Coherent Station (CS) 8 local_processor_write_data_beats_cs9 data fabric  event=0x25f,umask=0x7ff  01    Write data beats (64 bytes) for local processor at Coherent Station (CS) 9 local_processor_write_data_beats_cs10 data fabric  event=0x29f,umask=0x7ff  01    Write data beats (64 bytes) for local processor at Coherent Station (CS) 10 local_processor_write_data_beats_cs11 data fabric  event=0x2df,umask=0x7ff  01    Write data beats (64 bytes) for local processor at Coherent Station (CS) 11 remote_processor_read_data_beats_cs0 data fabric  event=0x1f,umask=0xbfe  01    Read data beats (64 bytes) for remote processor at Coherent Station (CS) 0 remote_processor_read_data_beats_cs1 data fabric  event=0x5f,umask=0xbfe  01    Read data beats (64 bytes) for remote processor at Coherent Station (CS) 1 remote_processor_read_data_beats_cs2 data fabric  event=0x9f,umask=0xbfe  01    Read data beats (64 bytes) for remote processor at Coherent Station (CS) 2 remote_processor_read_data_beats_cs3 data fabric  event=0xdf,umask=0xbfe  01    Read data beats (64 bytes) for remote processor at Coherent Station (CS) 3 remote_processor_read_data_beats_cs4 data fabric  event=0x11f,umask=0xbfe  01    Read data beats (64 bytes) for remote processor at Coherent Station (CS) 4 remote_processor_read_data_beats_cs5 data fabric  event=0x15f,umask=0xbfe  01    Read data beats (64 bytes) for remote processor at Coherent Station (CS) 5 remote_processor_read_data_beats_cs6 data fabric  event=0x19f,umask=0xbfe  01    Read data beats (64 bytes) for remote processor at Coherent Station (CS) 6 remote_processor_read_data_beats_cs7 data fabric  event=0x1df,umask=0xbfe  01    Read data beats (64 bytes) for remote processor at Coherent Station (CS) 7 remote_processor_read_data_beats_cs8 data fabric  event=0x21f,umask=0xbfe  01    Read data beats (64 bytes) for remote processor at Coherent Station (CS) 8 remote_processor_read_data_beats_cs9 data fabric  event=0x25f,umask=0xbfe  01    Read data beats (64 bytes) for remote processor at Coherent Station (CS) 9 remote_processor_read_data_beats_cs10 data fabric  event=0x29f,umask=0xbfe  01    Read data beats (64 bytes) for remote processor at Coherent Station (CS) 10 remote_processor_read_data_beats_cs11 data fabric  event=0x2df,umask=0xbfe  01    Read data beats (64 bytes) for remote processor at Coherent Station (CS) 11 remote_processor_write_data_beats_cs0 data fabric  event=0x1f,umask=0xbff  01    Write data beats (64 bytes) for remote processor at Coherent Station (CS) 0 remote_processor_write_data_beats_cs1 data fabric  event=0x5f,umask=0xbff  01    Write data beats (64 bytes) for remote processor at Coherent Station (CS) 1 remote_processor_write_data_beats_cs2 data fabric  event=0x9f,umask=0xbff  01    Write data beats (64 bytes) for remote processor at Coherent Station (CS) 2 remote_processor_write_data_beats_cs3 data fabric  event=0xdf,umask=0xbff  01    Write data beats (64 bytes) for remote processor at Coherent Station (CS) 3 remote_processor_write_data_beats_cs4 data fabric  event=0x11f,umask=0xbff  01    Write data beats (64 bytes) for remote processor at Coherent Station (CS) 4 remote_processor_write_data_beats_cs5 data fabric  event=0x15f,umask=0xbff  01    Write data beats (64 bytes) for remote processor at Coherent Station (CS) 5 remote_processor_write_data_beats_cs6 data fabric  event=0x19f,umask=0xbff  01    Write data beats (64 bytes) for remote processor at Coherent Station (CS) 6 remote_processor_write_data_beats_cs7 data fabric  event=0x1df,umask=0xbff  01    Write data beats (64 bytes) for remote processor at Coherent Station (CS) 7 remote_processor_write_data_beats_cs8 data fabric  event=0x21f,umask=0xbff  01    Write data beats (64 bytes) for remote processor at Coherent Station (CS) 8 remote_processor_write_data_beats_cs9 data fabric  event=0x25f,umask=0xbff  01    Write data beats (64 bytes) for remote processor at Coherent Station (CS) 9 remote_processor_write_data_beats_cs10 data fabric  event=0x29f,umask=0xbff  01    Write data beats (64 bytes) for remote processor at Coherent Station (CS) 10 remote_processor_write_data_beats_cs11 data fabric  event=0x2df,umask=0xbff  01    Write data beats (64 bytes) for remote processor at Coherent Station (CS) 11 local_socket_upstream_read_beats_iom0 data fabric  event=0x81f,umask=0x7fe  01    Read data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 0 local_socket_upstream_read_beats_iom1 data fabric  event=0x85f,umask=0x7fe  01    Read data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 1 local_socket_upstream_read_beats_iom2 data fabric  event=0x89f,umask=0x7fe  01    Read data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 2 local_socket_upstream_read_beats_iom3 data fabric  event=0x8df,umask=0x7fe  01    Read data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 3 local_socket_upstream_write_beats_iom0 data fabric  event=0x81f,umask=0x7ff  01    Write data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 0 local_socket_upstream_write_beats_iom1 data fabric  event=0x85f,umask=0x7ff  01    Write data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 1 local_socket_upstream_write_beats_iom2 data fabric  event=0x89f,umask=0x7ff  01    Write data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 2 local_socket_upstream_write_beats_iom3 data fabric  event=0x8df,umask=0x7ff  01    Write data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 3 remote_socket_upstream_read_beats_iom0 data fabric  event=0x81f,umask=0xbfe  01    Read data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 0 remote_socket_upstream_read_beats_iom1 data fabric  event=0x85f,umask=0xbfe  01    Read data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 1 remote_socket_upstream_read_beats_iom2 data fabric  event=0x89f,umask=0xbfe  01    Read data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 2 remote_socket_upstream_read_beats_iom3 data fabric  event=0x8df,umask=0xbfe  01    Read data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 3 remote_socket_upstream_write_beats_iom0 data fabric  event=0x81f,umask=0xbff  01    Write data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 0 remote_socket_upstream_write_beats_iom1 data fabric  event=0x85f,umask=0xbff  01    Write data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 1 remote_socket_upstream_write_beats_iom2 data fabric  event=0x89f,umask=0xbff  01    Write data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 2 remote_socket_upstream_write_beats_iom3 data fabric  event=0x8df,umask=0xbff  01    Write data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 3 local_socket_inf0_inbound_data_beats_ccm0 data fabric  event=0x41e,umask=0x7fe  01    Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 0 local_socket_inf0_inbound_data_beats_ccm1 data fabric  event=0x45e,umask=0x7fe  01    Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 1 local_socket_inf0_inbound_data_beats_ccm2 data fabric  event=0x49e,umask=0x7fe  01    Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 2 local_socket_inf0_inbound_data_beats_ccm3 data fabric  event=0x4de,umask=0x7fe  01    Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 3 local_socket_inf0_inbound_data_beats_ccm4 data fabric  event=0x51e,umask=0x7fe  01    Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 4 local_socket_inf0_inbound_data_beats_ccm5 data fabric  event=0x55e,umask=0x7fe  01    Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 5 local_socket_inf0_inbound_data_beats_ccm6 data fabric  event=0x59e,umask=0x7fe  01    Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 6 local_socket_inf0_inbound_data_beats_ccm7 data fabric  event=0x5de,umask=0x7fe  01    Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 7 local_socket_inf1_inbound_data_beats_ccm0 data fabric  event=0x41f,umask=0x7fe  01    Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 0 local_socket_inf1_inbound_data_beats_ccm1 data fabric  event=0x45f,umask=0x7fe  01    Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 1 local_socket_inf1_inbound_data_beats_ccm2 data fabric  event=0x49f,umask=0x7fe  01    Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 2 local_socket_inf1_inbound_data_beats_ccm3 data fabric  event=0x4df,umask=0x7fe  01    Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 3 local_socket_inf1_inbound_data_beats_ccm4 data fabric  event=0x51f,umask=0x7fe  01    Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 4 local_socket_inf1_inbound_data_beats_ccm5 data fabric  event=0x55f,umask=0x7fe  01    Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 5 local_socket_inf1_inbound_data_beats_ccm6 data fabric  event=0x59f,umask=0x7fe  01    Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 6 local_socket_inf1_inbound_data_beats_ccm7 data fabric  event=0x5df,umask=0x7fe  01    Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 7 local_socket_inf0_outbound_data_beats_ccm0 data fabric  event=0x41e,umask=0x7ff  01    Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 0 local_socket_inf0_outbound_data_beats_ccm1 data fabric  event=0x45e,umask=0x7ff  01    Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 1 local_socket_inf0_outbound_data_beats_ccm2 data fabric  event=0x49e,umask=0x7ff  01    Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 2 local_socket_inf0_outbound_data_beats_ccm3 data fabric  event=0x4de,umask=0x7ff  01    Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 3 local_socket_inf0_outbound_data_beats_ccm4 data fabric  event=0x51e,umask=0x7ff  01    Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 4 local_socket_inf0_outbound_data_beats_ccm5 data fabric  event=0x55e,umask=0x7ff  01    Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 5 local_socket_inf0_outbound_data_beats_ccm6 data fabric  event=0x59e,umask=0x7ff  01    Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 6 local_socket_inf0_outbound_data_beats_ccm7 data fabric  event=0x5de,umask=0x7ff  01    Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 7 local_socket_inf1_outbound_data_beats_ccm0 data fabric  event=0x41f,umask=0x7ff  01    Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 0 local_socket_inf1_outbound_data_beats_ccm1 data fabric  event=0x45f,umask=0x7ff  01    Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 1 local_socket_inf1_outbound_data_beats_ccm2 data fabric  event=0x49f,umask=0x7ff  01    Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 2 local_socket_inf1_outbound_data_beats_ccm3 data fabric  event=0x4df,umask=0x7ff  01    Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 3 local_socket_inf1_outbound_data_beats_ccm4 data fabric  event=0x51f,umask=0x7ff  01    Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 4 local_socket_inf1_outbound_data_beats_ccm5 data fabric  event=0x55f,umask=0x7ff  01    Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 5 local_socket_inf1_outbound_data_beats_ccm6 data fabric  event=0x59f,umask=0x7ff  01    Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 6 local_socket_inf1_outbound_data_beats_ccm7 data fabric  event=0x5df,umask=0x7ff  01    Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 7 remote_socket_inf0_inbound_data_beats_ccm0 data fabric  event=0x41e,umask=0xbfe  01    Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 0 remote_socket_inf0_inbound_data_beats_ccm1 data fabric  event=0x45e,umask=0xbfe  01    Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 1 remote_socket_inf0_inbound_data_beats_ccm2 data fabric  event=0x49e,umask=0xbfe  01    Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 2 remote_socket_inf0_inbound_data_beats_ccm3 data fabric  event=0x4de,umask=0xbfe  01    Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 3 remote_socket_inf0_inbound_data_beats_ccm4 data fabric  event=0x51e,umask=0xbfe  01    Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 4 remote_socket_inf0_inbound_data_beats_ccm5 data fabric  event=0x55e,umask=0xbfe  01    Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 5 remote_socket_inf0_inbound_data_beats_ccm6 data fabric  event=0x59e,umask=0xbfe  01    Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 6 remote_socket_inf0_inbound_data_beats_ccm7 data fabric  event=0x5de,umask=0xbfe  01    Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 7 remote_socket_inf1_inbound_data_beats_ccm0 data fabric  event=0x41f,umask=0xbfe  01    Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 0 remote_socket_inf1_inbound_data_beats_ccm1 data fabric  event=0x45f,umask=0xbfe  01    Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 1 remote_socket_inf1_inbound_data_beats_ccm2 data fabric  event=0x49f,umask=0xbfe  01    Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 2 remote_socket_inf1_inbound_data_beats_ccm3 data fabric  event=0x4df,umask=0xbfe  01    Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 3 remote_socket_inf1_inbound_data_beats_ccm4 data fabric  event=0x51f,umask=0xbfe  01    Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 4 remote_socket_inf1_inbound_data_beats_ccm5 data fabric  event=0x55f,umask=0xbfe  01    Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 5 remote_socket_inf1_inbound_data_beats_ccm6 data fabric  event=0x59f,umask=0xbfe  01    Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 6 remote_socket_inf1_inbound_data_beats_ccm7 data fabric  event=0x5df,umask=0xbfe  01    Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 7 remote_socket_inf0_outbound_data_beats_ccm0 data fabric  event=0x41e,umask=0xbff  01    Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 0 remote_socket_inf0_outbound_data_beats_ccm1 data fabric  event=0x45e,umask=0xbff  01    Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 1 remote_socket_inf0_outbound_data_beats_ccm2 data fabric  event=0x49e,umask=0xbff  01    Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 2 remote_socket_inf0_outbound_data_beats_ccm3 data fabric  event=0x4de,umask=0xbff  01    Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 3 remote_socket_inf0_outbound_data_beats_ccm4 data fabric  event=0x51e,umask=0xbff  01    Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 4 remote_socket_inf0_outbound_data_beats_ccm5 data fabric  event=0x55e,umask=0xbff  01    Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 5 remote_socket_inf0_outbound_data_beats_ccm6 data fabric  event=0x59e,umask=0xbff  01    Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 6 remote_socket_inf0_outbound_data_beats_ccm7 data fabric  event=0x5de,umask=0xbff  01    Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 7 remote_socket_inf1_outbound_data_beats_ccm0 data fabric  event=0x41f,umask=0xbff  01    Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 0 remote_socket_inf1_outbound_data_beats_ccm1 data fabric  event=0x45f,umask=0xbff  01    Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 1 remote_socket_inf1_outbound_data_beats_ccm2 data fabric  event=0x49f,umask=0xbff  01    Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 2 remote_socket_inf1_outbound_data_beats_ccm3 data fabric  event=0x4df,umask=0xbff  01    Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 3 remote_socket_inf1_outbound_data_beats_ccm4 data fabric  event=0x51f,umask=0xbff  01    Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 4 remote_socket_inf1_outbound_data_beats_ccm5 data fabric  event=0x55f,umask=0xbff  01    Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 5 remote_socket_inf1_outbound_data_beats_ccm6 data fabric  event=0x59f,umask=0xbff  01    Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 6 remote_socket_inf1_outbound_data_beats_ccm7 data fabric  event=0x5df,umask=0xbff  01    Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 7 local_socket_outbound_data_beats_link0 data fabric  event=0xb5f,umask=0xf3e  01    Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 0 local_socket_outbound_data_beats_link1 data fabric  event=0xb9f,umask=0xf3e  01    Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 1 local_socket_outbound_data_beats_link2 data fabric  event=0xbdf,umask=0xf3e  01    Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 2 local_socket_outbound_data_beats_link3 data fabric  event=0xc1f,umask=0xf3e  01    Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 3 local_socket_outbound_data_beats_link4 data fabric  event=0xc5f,umask=0xf3e  01    Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 4 local_socket_outbound_data_beats_link5 data fabric  event=0xc9f,umask=0xf3e  01    Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 5 local_socket_outbound_data_beats_link6 data fabric  event=0xcdf,umask=0xf3e  01    Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 6 local_socket_outbound_data_beats_link7 data fabric  event=0xd1f,umask=0xf3e  01    Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 7 fp_ret_x87_fp_ops.add_sub_ops floating point Retired x87 floating-point add and subtract ops event=2,umask=1  00     fp_ret_x87_fp_ops.mul_ops floating point Retired x87 floating-point multiply ops event=2,umask=2  00     fp_ret_x87_fp_ops.div_sqrt_ops floating point Retired x87 floating-point divide and square root ops event=2,umask=4  00     fp_ret_x87_fp_ops.all floating point Retired x87 floating-point ops of all types event=2,umask=7  00     fp_ret_sse_avx_ops.add_sub_flops floating point Retired SSE and AVX floating-point add and subtract ops event=3,umask=1  00     fp_ret_sse_avx_ops.mult_flops floating point Retired SSE and AVX floating-point multiply ops event=3,umask=2  00     fp_ret_sse_avx_ops.div_flops floating point Retired SSE and AVX floating-point divide and square root ops event=3,umask=4  00     fp_ret_sse_avx_ops.mac_flops floating point Retired SSE and AVX floating-point multiply-accumulate ops (each operation is counted as 2 ops) event=3,umask=8  00     fp_ret_sse_avx_ops.bfloat_mac_flops floating point Retired SSE and AVX floating-point bfloat multiply-accumulate ops (each operation is counted as 2 ops) event=3,umask=0x10  00     fp_ret_sse_avx_ops.all floating point Retired SSE and AVX floating-point ops of all types event=3,umask=0x1f  00     fp_retired_ser_ops.x87_ctrl_ret floating point Retired x87 control word mispredict traps due to mispredictions in RC or PC, or changes in exception mask bits event=5,umask=1  00     fp_retired_ser_ops.x87_bot_ret floating point Retired x87 bottom-executing ops. Bottom-executing ops wait for all older ops to retire before executing event=5,umask=2  00     fp_retired_ser_ops.sse_ctrl_ret floating point Retired SSE and AVX control word mispredict traps event=5,umask=4  00     fp_retired_ser_ops.sse_bot_ret floating point Retired SSE and AVX bottom-executing ops. Bottom-executing ops wait for all older ops to retire before executing event=5,umask=8  00     fp_retired_ser_ops.all floating point Retired SSE and AVX serializing ops of all types event=5,umask=0xf  00     fp_ops_retired_by_width.x87_uops_retired floating point Retired x87 floating-point ops event=8,umask=1  00     fp_ops_retired_by_width.mmx_uops_retired floating point Retired MMX floating-point ops event=8,umask=2  00     fp_ops_retired_by_width.scalar_uops_retired floating point Retired scalar floating-point ops event=8,umask=4  00     fp_ops_retired_by_width.pack_128_uops_retired floating point Retired packed 128-bit floating-point ops event=8,umask=8  00     fp_ops_retired_by_width.pack_256_uops_retired floating point Retired packed 256-bit floating-point ops event=8,umask=0x10  00     fp_ops_retired_by_width.pack_512_uops_retired floating point Retired packed 512-bit floating-point ops event=8,umask=0x20  00     fp_ops_retired_by_width.all floating point Retired floating-point ops of all widths event=8,umask=0x3f  00     fp_ops_retired_by_type.scalar_add floating point Retired scalar floating-point add ops event=0xa,umask=1  00     fp_ops_retired_by_type.scalar_sub floating point Retired scalar floating-point subtract ops event=0xa,umask=2  00     fp_ops_retired_by_type.scalar_mul floating point Retired scalar floating-point multiply ops event=0xa,umask=3  00     fp_ops_retired_by_type.scalar_mac floating point Retired scalar floating-point multiply-accumulate ops event=0xa,umask=4  00     fp_ops_retired_by_type.scalar_div floating point Retired scalar floating-point divide ops event=0xa,umask=5  00     fp_ops_retired_by_type.scalar_sqrt floating point Retired scalar floating-point square root ops event=0xa,umask=6  00     fp_ops_retired_by_type.scalar_cmp floating point Retired scalar floating-point compare ops event=0xa,umask=7  00     fp_ops_retired_by_type.scalar_cvt floating point Retired scalar floating-point convert ops event=0xa,umask=8  00     fp_ops_retired_by_type.scalar_blend floating point Retired scalar floating-point blend ops event=0xa,umask=9  00     fp_ops_retired_by_type.scalar_other floating point Retired scalar floating-point ops of other types event=0xa,umask=0xe  00     fp_ops_retired_by_type.scalar_all floating point Retired scalar floating-point ops of all types event=0xa,umask=0xf  00     fp_ops_retired_by_type.vector_add floating point Retired vector floating-point add ops event=0xa,umask=0x10  00     fp_ops_retired_by_type.vector_sub floating point Retired vector floating-point subtract ops event=0xa,umask=0x20  00     fp_ops_retired_by_type.vector_mul floating point Retired vector floating-point multiply ops event=0xa,umask=0x30  00     fp_ops_retired_by_type.vector_mac floating point Retired vector floating-point multiply-accumulate ops event=0xa,umask=0x40  00     fp_ops_retired_by_type.vector_div floating point Retired vector floating-point divide ops event=0xa,umask=0x50  00     fp_ops_retired_by_type.vector_sqrt floating point Retired vector floating-point square root ops event=0xa,umask=0x60  00     fp_ops_retired_by_type.vector_cmp floating point Retired vector floating-point compare ops event=0xa,umask=0x70  00     fp_ops_retired_by_type.vector_cvt floating point Retired vector floating-point convert ops event=0xa,umask=0x80  00     fp_ops_retired_by_type.vector_blend floating point Retired vector floating-point blend ops event=0xa,umask=0x90  00     fp_ops_retired_by_type.vector_shuffle floating point Retired vector floating-point shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xa,umask=0xb0  00     fp_ops_retired_by_type.vector_logical floating point Retired vector floating-point logical ops event=0xa,umask=0xd0  00     fp_ops_retired_by_type.vector_other floating point Retired vector floating-point ops of other types event=0xa,umask=0xe0  00     fp_ops_retired_by_type.vector_all floating point Retired vector floating-point ops of all types event=0xa,umask=0xf0  00     fp_ops_retired_by_type.all floating point Retired floating-point ops of all types event=0xa,umask=0xff  00     sse_avx_ops_retired.mmx_add floating point Retired MMX integer add event=0xb,umask=1  00     sse_avx_ops_retired.mmx_sub floating point Retired MMX integer subtract ops event=0xb,umask=2  00     sse_avx_ops_retired.mmx_mul floating point Retired MMX integer multiply ops event=0xb,umask=3  00     sse_avx_ops_retired.mmx_mac floating point Retired MMX integer multiply-accumulate ops event=0xb,umask=4  00     sse_avx_ops_retired.mmx_cmp floating point Retired MMX integer compare ops event=0xb,umask=7  00     sse_avx_ops_retired.mmx_shift floating point Retired MMX integer shift ops event=0xb,umask=9  00     sse_avx_ops_retired.mmx_mov floating point Retired MMX integer MOV ops event=0xb,umask=0xa  00     sse_avx_ops_retired.mmx_shuffle floating point Retired MMX integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xb,umask=0xb  00     sse_avx_ops_retired.mmx_pack floating point Retired MMX integer pack ops event=0xb,umask=0xc  00     sse_avx_ops_retired.mmx_logical floating point Retired MMX integer logical ops event=0xb,umask=0xd  00     sse_avx_ops_retired.mmx_other floating point Retired MMX integer multiply ops of other types event=0xb,umask=0xe  00     sse_avx_ops_retired.mmx_all floating point Retired MMX integer ops of all types event=0xb,umask=0xf  00     sse_avx_ops_retired.sse_avx_add floating point Retired SSE and AVX integer add ops event=0xb,umask=0x10  00     sse_avx_ops_retired.sse_avx_sub floating point Retired SSE and AVX integer subtract ops event=0xb,umask=0x20  00     sse_avx_ops_retired.sse_avx_mul floating point Retired SSE and AVX integer multiply ops event=0xb,umask=0x30  00     sse_avx_ops_retired.sse_avx_mac floating point Retired SSE and AVX integer multiply-accumulate ops event=0xb,umask=0x40  00     sse_avx_ops_retired.sse_avx_aes floating point Retired SSE and AVX integer AES ops event=0xb,umask=0x50  00     sse_avx_ops_retired.sse_avx_sha floating point Retired SSE and AVX integer SHA ops event=0xb,umask=0x60  00     sse_avx_ops_retired.sse_avx_cmp floating point Retired SSE and AVX integer compare ops event=0xb,umask=0x70  00     sse_avx_ops_retired.sse_avx_clm floating point Retired SSE and AVX integer CLM ops event=0xb,umask=0x80  00     sse_avx_ops_retired.sse_avx_shift floating point Retired SSE and AVX integer shift ops event=0xb,umask=0x90  00     sse_avx_ops_retired.sse_avx_mov floating point Retired SSE and AVX integer MOV ops event=0xb,umask=0xa0  00     sse_avx_ops_retired.sse_avx_shuffle floating point Retired SSE and AVX integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xb,umask=0xb0  00     sse_avx_ops_retired.sse_avx_pack floating point Retired SSE and AVX integer pack ops event=0xb,umask=0xc0  00     sse_avx_ops_retired.sse_avx_logical floating point Retired SSE and AVX integer logical ops event=0xb,umask=0xd0  00     sse_avx_ops_retired.sse_avx_other floating point Retired SSE and AVX integer ops of other types event=0xb,umask=0xe0  00     sse_avx_ops_retired.sse_avx_all floating point Retired SSE and AVX integer ops of all types event=0xb,umask=0xf0  00     sse_avx_ops_retired.all floating point Retired SSE, AVX and MMX integer ops of all types event=0xb,umask=0xff  00     fp_pack_ops_retired.fp128_add floating point Retired 128-bit packed floating-point add ops event=0xc,umask=1  00     fp_pack_ops_retired.fp128_sub floating point Retired 128-bit packed floating-point subtract ops event=0xc,umask=2  00     fp_pack_ops_retired.fp128_mul floating point Retired 128-bit packed floating-point multiply ops event=0xc,umask=3  00     fp_pack_ops_retired.fp128_mac floating point Retired 128-bit packed floating-point multiply-accumulate ops event=0xc,umask=4  00     fp_pack_ops_retired.fp128_div floating point Retired 128-bit packed floating-point divide ops event=0xc,umask=5  00     fp_pack_ops_retired.fp128_sqrt floating point Retired 128-bit packed floating-point square root ops event=0xc,umask=6  00     fp_pack_ops_retired.fp128_cmp floating point Retired 128-bit packed floating-point compare ops event=0xc,umask=7  00     fp_pack_ops_retired.fp128_cvt floating point Retired 128-bit packed floating-point convert ops event=0xc,umask=8  00     fp_pack_ops_retired.fp128_blend floating point Retired 128-bit packed floating-point blend ops event=0xc,umask=9  00     fp_pack_ops_retired.fp128_shuffle floating point Retired 128-bit packed floating-point shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xc,umask=0xb  00     fp_pack_ops_retired.fp128_logical floating point Retired 128-bit packed floating-point logical ops event=0xc,umask=0xd  00     fp_pack_ops_retired.fp128_other floating point Retired 128-bit packed floating-point ops of other types event=0xc,umask=0xe  00     fp_pack_ops_retired.fp128_all floating point Retired 128-bit packed floating-point ops of all types event=0xc,umask=0xf  00     fp_pack_ops_retired.fp256_add floating point Retired 256-bit packed floating-point add ops event=0xc,umask=0x10  00     fp_pack_ops_retired.fp256_sub floating point Retired 256-bit packed floating-point subtract ops event=0xc,umask=0x20  00     fp_pack_ops_retired.fp256_mul floating point Retired 256-bit packed floating-point multiply ops event=0xc,umask=0x30  00     fp_pack_ops_retired.fp256_mac floating point Retired 256-bit packed floating-point multiply-accumulate ops event=0xc,umask=0x40  00     fp_pack_ops_retired.fp256_div floating point Retired 256-bit packed floating-point divide ops event=0xc,umask=0x50  00     fp_pack_ops_retired.fp256_sqrt floating point Retired 256-bit packed floating-point square root ops event=0xc,umask=0x60  00     fp_pack_ops_retired.fp256_cmp floating point Retired 256-bit packed floating-point compare ops event=0xc,umask=0x70  00     fp_pack_ops_retired.fp256_cvt floating point Retired 256-bit packed floating-point convert ops event=0xc,umask=0x80  00     fp_pack_ops_retired.fp256_blend floating point Retired 256-bit packed floating-point blend ops event=0xc,umask=0x90  00     fp_pack_ops_retired.fp256_shuffle floating point Retired 256-bit packed floating-point shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xc,umask=0xb0  00     fp_pack_ops_retired.fp256_logical floating point Retired 256-bit packed floating-point logical ops event=0xc,umask=0xd0  00     fp_pack_ops_retired.fp256_other floating point Retired 256-bit packed floating-point ops of other types event=0xc,umask=0xe0  00     fp_pack_ops_retired.fp256_all floating point Retired 256-bit packed floating-point ops of all types event=0xc,umask=0xf0  00     fp_pack_ops_retired.all floating point Retired packed floating-point ops of all types event=0xc,umask=0xff  00     packed_int_op_type.int128_add floating point Retired 128-bit packed integer add ops event=0xd,umask=1  00     packed_int_op_type.int128_sub floating point Retired 128-bit packed integer subtract ops event=0xd,umask=2  00     packed_int_op_type.int128_mul floating point Retired 128-bit packed integer multiply ops event=0xd,umask=3  00     packed_int_op_type.int128_mac floating point Retired 128-bit packed integer multiply-accumulate ops event=0xd,umask=4  00     packed_int_op_type.int128_aes floating point Retired 128-bit packed integer AES ops event=0xd,umask=5  00     packed_int_op_type.int128_sha floating point Retired 128-bit packed integer SHA ops event=0xd,umask=6  00     packed_int_op_type.int128_cmp floating point Retired 128-bit packed integer compare ops event=0xd,umask=7  00     packed_int_op_type.int128_clm floating point Retired 128-bit packed integer CLM ops event=0xd,umask=8  00     packed_int_op_type.int128_shift floating point Retired 128-bit packed integer shift ops event=0xd,umask=9  00     packed_int_op_type.int128_mov floating point Retired 128-bit packed integer MOV ops event=0xd,umask=0xa  00     packed_int_op_type.int128_shuffle floating point Retired 128-bit packed integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xd,umask=0xb  00     packed_int_op_type.int128_pack floating point Retired 128-bit packed integer pack ops event=0xd,umask=0xc  00     packed_int_op_type.int128_logical floating point Retired 128-bit packed integer logical ops event=0xd,umask=0xd  00     packed_int_op_type.int128_other floating point Retired 128-bit packed integer ops of other types event=0xd,umask=0xe  00     packed_int_op_type.int128_all floating point Retired 128-bit packed integer ops of all types event=0xd,umask=0xf  00     packed_int_op_type.int256_add floating point Retired 256-bit packed integer add ops event=0xd,umask=0x10  00     packed_int_op_type.int256_sub floating point Retired 256-bit packed integer subtract ops event=0xd,umask=0x20  00     packed_int_op_type.int256_mul floating point Retired 256-bit packed integer multiply ops event=0xd,umask=0x30  00     packed_int_op_type.int256_mac floating point Retired 256-bit packed integer multiply-accumulate ops event=0xd,umask=0x40  00     packed_int_op_type.int256_cmp floating point Retired 256-bit packed integer compare ops event=0xd,umask=0x70  00     packed_int_op_type.int256_shift floating point Retired 256-bit packed integer shift ops event=0xd,umask=0x90  00     packed_int_op_type.int256_mov floating point Retired 256-bit packed integer MOV ops event=0xd,umask=0xa0  00     packed_int_op_type.int256_shuffle floating point Retired 256-bit packed integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xd,umask=0xb0  00     packed_int_op_type.int256_pack floating point Retired 256-bit packed integer pack ops event=0xd,umask=0xc0  00     packed_int_op_type.int256_logical floating point Retired 256-bit packed integer logical ops event=0xd,umask=0xd0  00     packed_int_op_type.int256_other floating point Retired 256-bit packed integer ops of other types event=0xd,umask=0xe0  00     packed_int_op_type.int256_all floating point Retired 256-bit packed integer ops of all types event=0xd,umask=0xf0  00     packed_int_op_type.all floating point Retired packed integer ops of all types event=0xd,umask=0xff  00     fp_disp_faults.x87_fill_fault floating point Floating-point dispatch faults for x87 fills event=0xe,umask=1  00     fp_disp_faults.xmm_fill_fault floating point Floating-point dispatch faults for XMM fills event=0xe,umask=2  00     fp_disp_faults.ymm_fill_fault floating point Floating-point dispatch faults for YMM fills event=0xe,umask=4  00     fp_disp_faults.ymm_spill_fault floating point Floating-point dispatch faults for YMM spills event=0xe,umask=8  00     fp_disp_faults.sse_avx_all floating point Floating-point dispatch faults of all types for SSE and AVX ops event=0xe,umask=0xe  00     fp_disp_faults.all floating point Floating-point dispatch faults of all types event=0xe,umask=0xf  00     amd_umc umc_mem_clk memory controller  event=0  01    Number of memory clock cycles umc_act_cmd.all memory controller  event=5  01    Number of ACTIVATE commands sent umc_act_cmd.rd memory controller  event=5,rdwrmask=1  01    Number of ACTIVATE commands sent for reads umc_act_cmd.wr memory controller  event=5,rdwrmask=2  01    Number of ACTIVATE commands sent for writes umc_pchg_cmd.all memory controller  event=6  01    Number of PRECHARGE commands sent umc_pchg_cmd.rd memory controller  event=6,rdwrmask=1  01    Number of PRECHARGE commands sent for reads umc_pchg_cmd.wr memory controller  event=6,rdwrmask=2  01    Number of PRECHARGE commands sent for writes umc_cas_cmd.all memory controller  event=0xa  01    Number of CAS commands sent umc_cas_cmd.rd memory controller  event=0xa,rdwrmask=1  01    Number of CAS commands sent for reads umc_cas_cmd.wr memory controller  event=0xa,rdwrmask=2  01    Number of CAS commands sent for writes umc_data_slot_clks.all memory controller  event=0x14  01    Number of clocks used by the data bus umc_data_slot_clks.rd memory controller  event=0x14,rdwrmask=1  01    Number of clocks used by the data bus for reads umc_data_slot_clks.wr memory controller  event=0x14,rdwrmask=2  01    Number of clocks used by the data bus for writes ls_bad_status2.stli_other memory Store-to-load conflicts (load unable to complete due to a non-forwardable conflict with an older store) event=0x24,umask=2  00     ls_dispatch.ld_dispatch memory Number of memory load operations dispatched to the load-store unit event=0x29,umask=1  00     ls_dispatch.store_dispatch memory Number of memory store operations dispatched to the load-store unit event=0x29,umask=2  00     ls_dispatch.ld_st_dispatch memory Number of memory load-store operations dispatched to the load-store unit event=0x29,umask=4  00     ls_stlf memory Store-to-load-forward (STLF) hits event=0x35  00     ls_st_commit_cancel2.st_commit_cancel_wcb_full memory Non-cacheable store commits cancelled due to the non-cacheable commit buffer being full event=0x37,umask=1  00     ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit memory L1 DTLB misses with L2 DTLB hits for 4k pages event=0x45,umask=1  00     ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit memory L1 DTLB misses with L2 DTLB hits for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages event=0x45,umask=2  00     ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit memory L1 DTLB misses with L2 DTLB hits for 2M pages event=0x45,umask=4  00     ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit memory L1 DTLB misses with L2 DTLB hits for 1G pages event=0x45,umask=8  00     ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss memory L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 4k pages event=0x45,umask=0x10  00     ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss memory L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages event=0x45,umask=0x20  00     ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss memory L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 2M pages event=0x45,umask=0x40  00     ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss memory L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 1G pages event=0x45,umask=0x80  00     ls_l1_d_tlb_miss.all_l2_miss memory L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for all page sizes event=0x45,umask=0xf0  00     ls_l1_d_tlb_miss.all memory L1 DTLB misses for all page sizes event=0x45,umask=0xff  00     ls_misal_loads.ma64 memory 64B misaligned (cacheline crossing) loads event=0x47,umask=1  00     ls_misal_loads.ma4k memory 4kB misaligned (page crossing) loads event=0x47,umask=2  00     ls_tlb_flush.all memory All TLB Flushes event=0x78,umask=0xff  00     bp_l1_tlb_miss_l2_tlb_hit memory Instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB event=0x84  00     bp_l1_tlb_miss_l2_tlb_miss.if4k memory Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 4k pages event=0x85,umask=1  00     bp_l1_tlb_miss_l2_tlb_miss.if2m memory Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 2M pages event=0x85,umask=2  00     bp_l1_tlb_miss_l2_tlb_miss.if1g memory Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 1G pages event=0x85,umask=4  00     bp_l1_tlb_miss_l2_tlb_miss.coalesced_4k memory Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages event=0x85,umask=8  00     bp_l1_tlb_miss_l2_tlb_miss.all memory Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for all page sizes event=0x85,umask=0xf  00     bp_l1_tlb_fetch_hit.if4k memory Instruction fetches that hit in the L1 ITLB for 4k or coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages event=0x94,umask=1  00     bp_l1_tlb_fetch_hit.if2m memory Instruction fetches that hit in the L1 ITLB for 2M pages event=0x94,umask=2  00     bp_l1_tlb_fetch_hit.if1g memory Instruction fetches that hit in the L1 ITLB for 1G pages event=0x94,umask=4  00     bp_l1_tlb_fetch_hit.all memory Instruction fetches that hit in the L1 ITLB for all page sizes event=0x94,umask=7  00     resyncs_or_nc_redirects other Pipeline restarts not caused by branch mispredicts event=0x96  00     de_op_queue_empty other Cycles when the op queue is empty. Such cycles indicate that the front-end is not delivering instructions fast enough event=0xa9  00     de_src_op_disp.decoder other Ops fetched from instruction cache and dispatched event=0xaa,umask=1  00     de_src_op_disp.op_cache other Ops fetched from op cache and dispatched event=0xaa,umask=2  00     de_src_op_disp.loop_buffer other Ops dispatched from loop buffer event=0xaa,umask=4  00     de_src_op_disp.all other Ops dispatched from any source event=0xaa,umask=7  00     de_dis_ops_from_decoder.any_fp_dispatch other Number of ops dispatched to the floating-point unit event=0xab,umask=4  00     de_dis_ops_from_decoder.disp_op_type.any_integer_dispatch other Number of ops dispatched to the integer execution unit event=0xab,umask=8  00     de_dis_dispatch_token_stalls1.int_phy_reg_file_rsrc_stall other Number of cycles dispatch is stalled for integer physical register file tokens event=0xae,umask=1  00     de_dis_dispatch_token_stalls1.load_queue_rsrc_stall other Number of cycles dispatch is stalled for Load queue token event=0xae,umask=2  00     de_dis_dispatch_token_stalls1.store_queue_rsrc_stall other Number of cycles dispatch is stalled for store queue tokens event=0xae,umask=4  00     de_dis_dispatch_token_stalls1.taken_brnch_buffer_rsrc other Number of cycles dispatch is stalled for taken branch buffer tokens event=0xae,umask=0x10  00     de_dis_dispatch_token_stalls1.fp_reg_file_rsrc_stall other Number of cycles dispatch is stalled for floating-point register file tokens event=0xae,umask=0x20  00     de_dis_dispatch_token_stalls1.fp_sch_rsrc_stall other Number of cycles dispatch is stalled for floating-point scheduler tokens event=0xae,umask=0x40  00     de_dis_dispatch_token_stalls1.fp_flush_recovery_stall other Number of cycles dispatch is stalled for floating-point flush recovery event=0xae,umask=0x80  00     de_dis_dispatch_token_stalls2.int_sch0_token_stall other Number of cycles dispatch is stalled for integer scheduler queue 0 tokens event=0xaf,umask=1  00     de_dis_dispatch_token_stalls2.int_sch1_token_stall other Number of cycles dispatch is stalled for integer scheduler queue 1 tokens event=0xaf,umask=2  00     de_dis_dispatch_token_stalls2.int_sch2_token_stall other Number of cycles dispatch is stalled for integer scheduler queue 2 tokens event=0xaf,umask=4  00     de_dis_dispatch_token_stalls2.int_sch3_token_stall other Number of cycles dispatch is stalled for integer scheduler queue 3 tokens event=0xaf,umask=8  00     de_dis_dispatch_token_stalls2.retire_token_stall other Number of cycles dispatch is stalled for retire queue tokens event=0xaf,umask=0x20  00     de_no_dispatch_per_slot.no_ops_from_frontend other In each cycle counts dispatch slots left empty because the front-end did not supply ops event=0x1a0,umask=1  00     de_no_dispatch_per_slot.backend_stalls other In each cycle counts ops unable to dispatch because of back-end stalls event=0x1a0,umask=0x1e  00     de_no_dispatch_per_slot.smt_contention other In each cycle counts ops unable to dispatch because the dispatch cycle was granted to the other SMT thread event=0x1a0,umask=0x60  00     all_data_cache_accesses recommended All data cache accesses event=0x29,umask=7  00     bp_l1_tlb_miss_l2_tlb_hit branch prediction Instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB event=0x84  00     bp_l1_tlb_miss_l2_tlb_miss.if4k branch prediction Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 4k pages event=0x85,umask=1  00     bp_l1_tlb_miss_l2_tlb_miss.if2m branch prediction Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 2M pages event=0x85,umask=2  00     bp_l1_tlb_miss_l2_tlb_miss.if1g branch prediction Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 1G pages event=0x85,umask=4  00     bp_l1_tlb_miss_l2_tlb_miss.coalesced_4k branch prediction Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages event=0x85,umask=8  00     bp_l1_tlb_miss_l2_tlb_miss.all branch prediction Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for all page sizes event=0x85,umask=0xf  00     bp_l2_btb_correct branch prediction L2 branch prediction overrides existing prediction (speculative) event=0x8b  00     bp_dyn_ind_pred branch prediction Dynamic indirect predictions (branch used the indirect predictor to make a prediction) event=0x8e  00     bp_de_redirect branch prediction Number of times an early redirect is sent to branch predictor. This happens when either the decoder or dispatch logic is able to detect that the branch predictor needs to be redirected event=0x91  00     bp_l1_tlb_fetch_hit.if4k branch prediction Instruction fetches that hit in the L1 ITLB for 4k or coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages event=0x94,umask=1  00     bp_l1_tlb_fetch_hit.if2m branch prediction Instruction fetches that hit in the L1 ITLB for 2M pages event=0x94,umask=2  00     bp_l1_tlb_fetch_hit.if1g branch prediction Instruction fetches that hit in the L1 ITLB for 1G pages event=0x94,umask=4  00     bp_l1_tlb_fetch_hit.all branch prediction Instruction fetches that hit in the L1 ITLB for all page sizes event=0x94,umask=7  00     bp_redirects.resync branch prediction Redirects of the branch predictor caused by resyncs event=0x9f,umask=1  00     bp_redirects.ex_redir branch prediction Redirects of the branch predictor caused by mispredicts event=0x9f,umask=2  00     bp_redirects.all branch prediction Redirects of the branch predictor event=0x9f  00     local_or_remote_socket_read_data_beats_dram_0 data fabric  event=0x1f,umask=0xffe  01    Read data beats (64 bytes) for transactions between local or remote socket and DRAM Channel 0 local_or_remote_socket_read_data_beats_dram_1 data fabric  event=0x5f,umask=0xffe  01    Read data beats (64 bytes) for transactions between local or remote socket and DRAM Channel 1 local_or_remote_socket_read_data_beats_dram_2 data fabric  event=0x9f,umask=0xffe  01    Read data beats (64 bytes) for transactions between local or remote socket and DRAM Channel 2 local_or_remote_socket_read_data_beats_dram_3 data fabric  event=0xdf,umask=0xffe  01    Read data beats (64 bytes) for transactions between local or remote socket and DRAM Channel 3 local_or_remote_socket_read_data_beats_dram_4 data fabric  event=0x11f,umask=0xffe  01    Read data beats (64 bytes) for transactions between local or remote socket and DRAM Channel 4 local_or_remote_socket_read_data_beats_dram_5 data fabric  event=0x15f,umask=0xffe  01    Read data beats (64 bytes) for transactions between local or remote socket and DRAM Channel 5 local_or_remote_socket_read_data_beats_dram_6 data fabric  event=0x19f,umask=0xffe  01    Read data beats (64 bytes) for transactions between local or remote socket and DRAM Channel 6 local_or_remote_socket_read_data_beats_dram_7 data fabric  event=0x1df,umask=0xffe  01    Read data beats (64 bytes) for transactions between local or remote socket and DRAM Channel 7 local_or_remote_socket_read_data_beats_dram_8 data fabric  event=0x21f,umask=0xffe  01    Read data beats (64 bytes) for transactions between local or remote socket and DRAM Channel 8 local_or_remote_socket_read_data_beats_dram_9 data fabric  event=0x25f,umask=0xffe  01    Read data beats (64 bytes) for transactions between local or remote socket and DRAM Channel 9 local_or_remote_socket_read_data_beats_dram_10 data fabric  event=0x29f,umask=0xffe  01    Read data beats (64 bytes) for transactions between local or remote socket and DRAM Channel 10 local_or_remote_socket_read_data_beats_dram_11 data fabric  event=0x2df,umask=0xffe  01    Read data beats (64 bytes) for transactions between local or remote socket and DRAM Channel 11 local_socket_write_data_beats_dram_0 data fabric  event=0x1f,umask=0x7ff  01    Write data beats (64 bytes) for transactions between local socket and DRAM Channel 0 local_socket_write_data_beats_dram_1 data fabric  event=0x5f,umask=0x7ff  01    Write data beats (64 bytes) for transactions between local socket and DRAM Channel 1 local_socket_write_data_beats_dram_2 data fabric  event=0x9f,umask=0x7ff  01    Write data beats (64 bytes) for transactions between local socket and DRAM Channel 2 local_socket_write_data_beats_dram_3 data fabric  event=0xdf,umask=0x7ff  01    Write data beats (64 bytes) for transactions between local socket and DRAM Channel 3 local_socket_write_data_beats_dram_4 data fabric  event=0x11f,umask=0x7ff  01    Write data beats (64 bytes) for transactions between local socket and DRAM Channel 4 local_socket_write_data_beats_dram_5 data fabric  event=0x15f,umask=0x7ff  01    Write data beats (64 bytes) for transactions between local socket and DRAM Channel 5 local_socket_write_data_beats_dram_6 data fabric  event=0x19f,umask=0x7ff  01    Write data beats (64 bytes) for transactions between local socket and DRAM Channel 6 local_socket_write_data_beats_dram_7 data fabric  event=0x1df,umask=0x7ff  01    Write data beats (64 bytes) for transactions between local socket and DRAM Channel 7 local_socket_write_data_beats_dram_8 data fabric  event=0x21f,umask=0x7ff  01    Write data beats (64 bytes) for transactions between local socket and DRAM Channel 8 local_socket_write_data_beats_dram_9 data fabric  event=0x25f,umask=0x7ff  01    Write data beats (64 bytes) for transactions between local socket and DRAM Channel 9 local_socket_write_data_beats_dram_10 data fabric  event=0x29f,umask=0x7ff  01    Write data beats (64 bytes) for transactions between local socket and DRAM Channel 10 local_socket_write_data_beats_dram_11 data fabric  event=0x2df,umask=0x7ff  01    Write data beats (64 bytes) for transactions between local socket and DRAM Channel 11 remote_socket_write_data_beats_dram_0 data fabric  event=0x1f,umask=0xbff  01    Write data beats (64 bytes) for transactions between remote socket and DRAM Channel 0 remote_socket_write_data_beats_dram_1 data fabric  event=0x5f,umask=0xbff  01    Write data beats (64 bytes) for transactions between remote socket and DRAM Channel 1 remote_socket_write_data_beats_dram_2 data fabric  event=0x9f,umask=0xbff  01    Write data beats (64 bytes) for transactions between remote socket and DRAM Channel 2 remote_socket_write_data_beats_dram_3 data fabric  event=0xdf,umask=0xbff  01    Write data beats (64 bytes) for transactions between remote socket and DRAM Channel 3 remote_socket_write_data_beats_dram_4 data fabric  event=0x11f,umask=0xbff  01    Write data beats (64 bytes) for transactions between remote socket and DRAM Channel 4 remote_socket_write_data_beats_dram_5 data fabric  event=0x15f,umask=0xbff  01    Write data beats (64 bytes) for transactions between remote socket and DRAM Channel 5 remote_socket_write_data_beats_dram_6 data fabric  event=0x19f,umask=0xbff  01    Write data beats (64 bytes) for transactions between remote socket and DRAM Channel 6 remote_socket_write_data_beats_dram_7 data fabric  event=0x1df,umask=0xbff  01    Write data beats (64 bytes) for transactions between remote socket and DRAM Channel 7 remote_socket_write_data_beats_dram_8 data fabric  event=0x21f,umask=0xbff  01    Write data beats (64 bytes) for transactions between remote socket and DRAM Channel 8 remote_socket_write_data_beats_dram_9 data fabric  event=0x25f,umask=0xbff  01    Write data beats (64 bytes) for transactions between remote socket and DRAM Channel 9 remote_socket_write_data_beats_dram_10 data fabric  event=0x29f,umask=0xbff  01    Write data beats (64 bytes) for transactions between remote socket and DRAM Channel 10 remote_socket_write_data_beats_dram_11 data fabric  event=0x2df,umask=0xbff  01    Write data beats (64 bytes) for transactions between remote socket and DRAM Channel 11 local_or_remote_socket_write_data_beats_dram_0 data fabric  event=0x1f,umask=0xfff  01    Write data beats (64 bytes) for transactions between local or remote socket and DRAM Channel 0 local_or_remote_socket_write_data_beats_dram_1 data fabric  event=0x5f,umask=0xfff  01    Write data beats (64 bytes) for transactions between local or remote socket and DRAM Channel 1 local_or_remote_socket_write_data_beats_dram_2 data fabric  event=0x9f,umask=0xfff  01    Write data beats (64 bytes) for transactions between local or remote socket and DRAM Channel 2 local_or_remote_socket_write_data_beats_dram_3 data fabric  event=0xdf,umask=0xfff  01    Write data beats (64 bytes) for transactions between local or remote socket and DRAM Channel 3 local_or_remote_socket_write_data_beats_dram_4 data fabric  event=0x11f,umask=0xfff  01    Write data beats (64 bytes) for transactions between local or remote socket and DRAM Channel 4 local_or_remote_socket_write_data_beats_dram_5 data fabric  event=0x15f,umask=0xfff  01    Write data beats (64 bytes) for transactions between local or remote socket and DRAM Channel 5 local_or_remote_socket_write_data_beats_dram_6 data fabric  event=0x19f,umask=0xfff  01    Write data beats (64 bytes) for transactions between local or remote socket and DRAM Channel 6 local_or_remote_socket_write_data_beats_dram_7 data fabric  event=0x1df,umask=0xfff  01    Write data beats (64 bytes) for transactions between local or remote socket and DRAM Channel 7 local_or_remote_socket_write_data_beats_dram_8 data fabric  event=0x21f,umask=0xfff  01    Write data beats (64 bytes) for transactions between local or remote socket and DRAM Channel 8 local_or_remote_socket_write_data_beats_dram_9 data fabric  event=0x25f,umask=0xfff  01    Write data beats (64 bytes) for transactions between local or remote socket and DRAM Channel 9 local_or_remote_socket_write_data_beats_dram_10 data fabric  event=0x29f,umask=0xfff  01    Write data beats (64 bytes) for transactions between local or remote socket and DRAM Channel 10 local_or_remote_socket_write_data_beats_dram_11 data fabric  event=0x2df,umask=0xfff  01    Write data beats (64 bytes) for transactions between local or remote socket and DRAM Channel 11 local_socket_upstream_read_data_beats_io_0 data fabric  event=0x81f,umask=0x7fe  01    Upstream DMA read data beats (64 bytes) for transactions between local socket and IO Root Complex 0 local_socket_upstream_read_data_beats_io_1 data fabric  event=0x85f,umask=0x7fe  01    Upstream DMA read data beats (64 bytes) for transactions between local socket and IO Root Complex 1 local_socket_upstream_read_data_beats_io_2 data fabric  event=0x89f,umask=0x7fe  01    Upstream DMA read data beats (64 bytes) for transactions between local socket and IO Root Complex 2 local_socket_upstream_read_data_beats_io_3 data fabric  event=0x8df,umask=0x7fe  01    Upstream DMA read data beats (64 bytes) for transactions between local socket and IO Root Complex 3 local_socket_upstream_read_data_beats_io_4 data fabric  event=0x91f,umask=0x7fe  01    Upstream DMA read data beats (64 bytes) for transactions between local socket and IO Root Complex 4 local_socket_upstream_read_data_beats_io_5 data fabric  event=0x95f,umask=0x7fe  01    Upstream DMA read data beats (64 bytes) for transactions between local socket and IO Root Complex 5 local_socket_upstream_read_data_beats_io_6 data fabric  event=0x99f,umask=0x7fe  01    Upstream DMA read data beats (64 bytes) for transactions between local socket and IO Root Complex 6 local_socket_upstream_read_data_beats_io_7 data fabric  event=0x9df,umask=0x7fe  01    Upstream DMA read data beats (64 bytes) for transactions between local socket and IO Root Complex 7 local_socket_upstream_write_data_beats_io_0 data fabric  event=0x81f,umask=0x7ff  01    Upstream DMA write data beats (64 bytes) for transactions between local socket and IO Root Complex 0 local_socket_upstream_write_data_beats_io_1 data fabric  event=0x85f,umask=0x7ff  01    Upstream DMA write data beats (64 bytes) for transactions between local socket and IO Root Complex 1 local_socket_upstream_write_data_beats_io_2 data fabric  event=0x89f,umask=0x7ff  01    Upstream DMA write data beats (64 bytes) for transactions between local socket and IO Root Complex 2 local_socket_upstream_write_data_beats_io_3 data fabric  event=0x8df,umask=0x7ff  01    Upstream DMA write data beats (64 bytes) for transactions between local socket and IO Root Complex 3 local_socket_upstream_write_data_beats_io_4 data fabric  event=0x91f,umask=0x7ff  01    Upstream DMA write data beats (64 bytes) for transactions between local socket and IO Root Complex 4 local_socket_upstream_write_data_beats_io_5 data fabric  event=0x95f,umask=0x7ff  01    Upstream DMA write data beats (64 bytes) for transactions between local socket and IO Root Complex 5 local_socket_upstream_write_data_beats_io_6 data fabric  event=0x99f,umask=0x7ff  01    Upstream DMA write data beats (64 bytes) for transactions between local socket and IO Root Complex 6 local_socket_upstream_write_data_beats_io_7 data fabric  event=0x9df,umask=0x7ff  01    Upstream DMA write data beats (64 bytes) for transactions between local socket and IO Root Complex 7 remote_socket_upstream_read_data_beats_io_0 data fabric  event=0x81f,umask=0xbfe  01    Upstream DMA read data beats (64 bytes) for transactions between remote socket and IO Root Complex 0 remote_socket_upstream_read_data_beats_io_1 data fabric  event=0x85f,umask=0xbfe  01    Upstream DMA read data beats (64 bytes) for transactions between remote socket and IO Root Complex 1 remote_socket_upstream_read_data_beats_io_2 data fabric  event=0x89f,umask=0xbfe  01    Upstream DMA read data beats (64 bytes) for transactions between remote socket and IO Root Complex 2 remote_socket_upstream_read_data_beats_io_3 data fabric  event=0x8df,umask=0xbfe  01    Upstream DMA read data beats (64 bytes) for transactions between remote socket and IO Root Complex 3 remote_socket_upstream_read_data_beats_io_4 data fabric  event=0x91f,umask=0xbfe  01    Upstream DMA read data beats (64 bytes) for transactions between remote socket and IO Root Complex 4 remote_socket_upstream_read_data_beats_io_5 data fabric  event=0x95f,umask=0xbfe  01    Upstream DMA read data beats (64 bytes) for transactions between remote socket and IO Root Complex 5 remote_socket_upstream_read_data_beats_io_6 data fabric  event=0x99f,umask=0xbfe  01    Upstream DMA read data beats (64 bytes) for transactions between remote socket and IO Root Complex 6 remote_socket_upstream_read_data_beats_io_7 data fabric  event=0x9df,umask=0xbfe  01    Upstream DMA read data beats (64 bytes) for transactions between remote socket and IO Root Complex 7 remote_socket_upstream_write_data_beats_io_0 data fabric  event=0x81f,umask=0xbff  01    Upstream DMA write data beats (64 bytes) for transactions between remote socket and IO Root Complex 0 remote_socket_upstream_write_data_beats_io_1 data fabric  event=0x85f,umask=0xbff  01    Upstream DMA write data beats (64 bytes) for transactions between remote socket and IO Root Complex 1 remote_socket_upstream_write_data_beats_io_2 data fabric  event=0x89f,umask=0xbff  01    Upstream DMA write data beats (64 bytes) for transactions between remote socket and IO Root Complex 2 remote_socket_upstream_write_data_beats_io_3 data fabric  event=0x8df,umask=0xbff  01    Upstream DMA write data beats (64 bytes) for transactions between remote socket and IO Root Complex 3 remote_socket_upstream_write_data_beats_io_4 data fabric  event=0x91f,umask=0xbff  01    Upstream DMA write data beats (64 bytes) for transactions between remote socket and IO Root Complex 4 remote_socket_upstream_write_data_beats_io_5 data fabric  event=0x95f,umask=0xbff  01    Upstream DMA write data beats (64 bytes) for transactions between remote socket and IO Root Complex 5 remote_socket_upstream_write_data_beats_io_6 data fabric  event=0x99f,umask=0xbff  01    Upstream DMA write data beats (64 bytes) for transactions between remote socket and IO Root Complex 6 remote_socket_upstream_write_data_beats_io_7 data fabric  event=0x9df,umask=0xbff  01    Upstream DMA write data beats (64 bytes) for transactions between remote socket and IO Root Complex 7 local_or_remote_socket_upstream_read_data_beats_io_0 data fabric  event=0x81f,umask=0xffe  01    Upstream DMA read data beats (64 bytes) for transactions between local or remote socket and IO Root Complex 0 local_or_remote_socket_upstream_read_data_beats_io_1 data fabric  event=0x85f,umask=0xffe  01    Upstream DMA read data beats (64 bytes) for transactions between local or remote socket and IO Root Complex 1 local_or_remote_socket_upstream_read_data_beats_io_2 data fabric  event=0x89f,umask=0xffe  01    Upstream DMA read data beats (64 bytes) for transactions between local or remote socket and IO Root Complex 2 local_or_remote_socket_upstream_read_data_beats_io_3 data fabric  event=0x8df,umask=0xffe  01    Upstream DMA read data beats (64 bytes) for transactions between local or remote socket and IO Root Complex 3 local_or_remote_socket_upstream_read_data_beats_io_4 data fabric  event=0x91f,umask=0xffe  01    Upstream DMA read data beats (64 bytes) for transactions between local or remote socket and IO Root Complex 4 local_or_remote_socket_upstream_read_data_beats_io_5 data fabric  event=0x95f,umask=0xffe  01    Upstream DMA read data beats (64 bytes) for transactions between local or remote socket and IO Root Complex 5 local_or_remote_socket_upstream_read_data_beats_io_6 data fabric  event=0x99f,umask=0xffe  01    Upstream DMA read data beats (64 bytes) for transactions between local or remote socket and IO Root Complex 6 local_or_remote_socket_upstream_read_data_beats_io_7 data fabric  event=0x9df,umask=0xffe  01    Upstream DMA read data beats (64 bytes) for transactions between local or remote socket and IO Root Complex 7 local_or_remote_socket_upstream_write_data_beats_io_0 data fabric  event=0x81f,umask=0xfff  01    Upstream DMA write data beats (64 bytes) for transactions between local or remote socket and IO Root Complex 0 local_or_remote_socket_upstream_write_data_beats_io_1 data fabric  event=0x85f,umask=0xfff  01    Upstream DMA write data beats (64 bytes) for transactions between local or remote socket and IO Root Complex 1 local_or_remote_socket_upstream_write_data_beats_io_2 data fabric  event=0x89f,umask=0xfff  01    Upstream DMA write data beats (64 bytes) for transactions between local or remote socket and IO Root Complex 2 local_or_remote_socket_upstream_write_data_beats_io_3 data fabric  event=0x8df,umask=0xfff  01    Upstream DMA write data beats (64 bytes) for transactions between local or remote socket and IO Root Complex 3 local_or_remote_socket_upstream_write_data_beats_io_4 data fabric  event=0x91f,umask=0xfff  01    Upstream DMA write data beats (64 bytes) for transactions between local or remote socket and IO Root Complex 4 local_or_remote_socket_upstream_write_data_beats_io_5 data fabric  event=0x95f,umask=0xfff  01    Upstream DMA write data beats (64 bytes) for transactions between local or remote socket and IO Root Complex 5 local_or_remote_socket_upstream_write_data_beats_io_6 data fabric  event=0x99f,umask=0xfff  01    Upstream DMA write data beats (64 bytes) for transactions between local or remote socket and IO Root Complex 6 local_or_remote_socket_upstream_write_data_beats_io_7 data fabric  event=0x9df,umask=0xfff  01    Upstream DMA write data beats (64 bytes) for transactions between local or remote socket and IO Root Complex 7 local_socket_inbound_data_beats_cfi_0 data fabric  event=0x41e,umask=0x7fe  01    Inbound data beats (32 bytes) for transactions between local socket and Core-to-Fabric Interface 0 local_socket_inbound_data_beats_cfi_1 data fabric  event=0x45e,umask=0x7fe  01    Inbound data beats (32 bytes) for transactions between local socket and Core-to-Fabric Interface 1 local_socket_inbound_data_beats_cfi_2 data fabric  event=0x49e,umask=0x7fe  01    Inbound data beats (32 bytes) for transactions between local socket and Core-to-Fabric Interface 2 local_socket_inbound_data_beats_cfi_3 data fabric  event=0x4de,umask=0x7fe  01    Inbound data beats (32 bytes) for transactions between local socket and Core-to-Fabric Interface 3 local_socket_inbound_data_beats_cfi_4 data fabric  event=0x51e,umask=0x7fe  01    Inbound data beats (32 bytes) for transactions between local socket and Core-to-Fabric Interface 4 local_socket_inbound_data_beats_cfi_5 data fabric  event=0x55e,umask=0x7fe  01    Inbound data beats (32 bytes) for transactions between local socket and Core-to-Fabric Interface 5 local_socket_inbound_data_beats_cfi_6 data fabric  event=0x59e,umask=0x7fe  01    Inbound data beats (32 bytes) for transactions between local socket and Core-to-Fabric Interface 6 local_socket_inbound_data_beats_cfi_7 data fabric  event=0x5de,umask=0x7fe  01    Inbound data beats (32 bytes) for transactions between local socket and Core-to-Fabric Interface 7 local_socket_inbound_data_beats_cfi_8 data fabric  event=0x41f,umask=0x7fe  01    Inbound data beats (32 bytes) for transactions between local socket and Core-to-Fabric Interface 8 local_socket_inbound_data_beats_cfi_9 data fabric  event=0x45f,umask=0x7fe  01    Inbound data beats (32 bytes) for transactions between local socket and Core-to-Fabric Interface 9 local_socket_inbound_data_beats_cfi_10 data fabric  event=0x49f,umask=0x7fe  01    Inbound data beats (32 bytes) for transactions between local socket and Core-to-Fabric Interface 10 local_socket_inbound_data_beats_cfi_11 data fabric  event=0x4df,umask=0x7fe  01    Inbound data beats (32 bytes) for transactions between local socket and Core-to-Fabric Interface 11 local_socket_inbound_data_beats_cfi_12 data fabric  event=0x51f,umask=0x7fe  01    Inbound data beats (32 bytes) for transactions between local socket and Core-to-Fabric Interface 12 local_socket_inbound_data_beats_cfi_13 data fabric  event=0x55f,umask=0x7fe  01    Inbound data beats (32 bytes) for transactions between local socket and Core-to-Fabric Interface 13 local_socket_inbound_data_beats_cfi_14 data fabric  event=0x59f,umask=0x7fe  01    Inbound data beats (32 bytes) for transactions between local socket and Core-to-Fabric Interface 14 local_socket_inbound_data_beats_cfi_15 data fabric  event=0x5df,umask=0x7fe  01    Inbound data beats (32 bytes) for transactions between local socket and Core-to-Fabric Interface 15 local_socket_outbound_data_beats_cfi_0 data fabric  event=0x41e,umask=0x7ff  01    Outbound data beats (64 bytes) for transactions between local socket and Core-to-Fabric Interface 0 local_socket_outbound_data_beats_cfi_1 data fabric  event=0x45e,umask=0x7ff  01    Outbound data beats (64 bytes) for transactions between local socket and Core-to-Fabric Interface 1 local_socket_outbound_data_beats_cfi_2 data fabric  event=0x49e,umask=0x7ff  01    Outbound data beats (64 bytes) for transactions between local socket and Core-to-Fabric Interface 2 local_socket_outbound_data_beats_cfi_3 data fabric  event=0x4de,umask=0x7ff  01    Outbound data beats (64 bytes) for transactions between local socket and Core-to-Fabric Interface 3 local_socket_outbound_data_beats_cfi_4 data fabric  event=0x51e,umask=0x7ff  01    Outbound data beats (64 bytes) for transactions between local socket and Core-to-Fabric Interface 4 local_socket_outbound_data_beats_cfi_5 data fabric  event=0x55e,umask=0x7ff  01    Outbound data beats (64 bytes) for transactions between local socket and Core-to-Fabric Interface 5 local_socket_outbound_data_beats_cfi_6 data fabric  event=0x59e,umask=0x7ff  01    Outbound data beats (64 bytes) for transactions between local socket and Core-to-Fabric Interface 6 local_socket_outbound_data_beats_cfi_7 data fabric  event=0x5de,umask=0x7ff  01    Outbound data beats (64 bytes) for transactions between local socket and Core-to-Fabric Interface 7 local_socket_outbound_data_beats_cfi_8 data fabric  event=0x41f,umask=0x7ff  01    Outbound data beats (64 bytes) for transactions between local socket and Core-to-Fabric Interface 8 local_socket_outbound_data_beats_cfi_9 data fabric  event=0x45f,umask=0x7ff  01    Outbound data beats (64 bytes) for transactions between local socket and Core-to-Fabric Interface 9 local_socket_outbound_data_beats_cfi_10 data fabric  event=0x49f,umask=0x7ff  01    Outbound data beats (64 bytes) for transactions between local socket and Core-to-Fabric Interface 10 local_socket_outbound_data_beats_cfi_11 data fabric  event=0x4df,umask=0x7ff  01    Outbound data beats (64 bytes) for transactions between local socket and Core-to-Fabric Interface 11 local_socket_outbound_data_beats_cfi_12 data fabric  event=0x51f,umask=0x7ff  01    Outbound data beats (64 bytes) for transactions between local socket and Core-to-Fabric Interface 12 local_socket_outbound_data_beats_cfi_13 data fabric  event=0x55f,umask=0x7ff  01    Outbound data beats (64 bytes) for transactions between local socket and Core-to-Fabric Interface 13 local_socket_outbound_data_beats_cfi_14 data fabric  event=0x59f,umask=0x7ff  01    Outbound data beats (64 bytes) for transactions between local socket and Core-to-Fabric Interface 14 local_socket_outbound_data_beats_cfi_15 data fabric  event=0x5df,umask=0x7ff  01    Outbound data beats (64 bytes) for transactions between local socket and Core-to-Fabric Interface 15 remote_socket_inbound_data_beats_cfi_0 data fabric  event=0x41e,umask=0xbfe  01    Inbound data beats (32 bytes) for transactions between remote socket and Core-to-Fabric Interface 0 remote_socket_inbound_data_beats_cfi_1 data fabric  event=0x45e,umask=0xbfe  01    Inbound data beats (32 bytes) for transactions between remote socket and Core-to-Fabric Interface 1 remote_socket_inbound_data_beats_cfi_2 data fabric  event=0x49e,umask=0xbfe  01    Inbound data beats (32 bytes) for transactions between remote socket and Core-to-Fabric Interface 2 remote_socket_inbound_data_beats_cfi_3 data fabric  event=0x4de,umask=0xbfe  01    Inbound data beats (32 bytes) for transactions between remote socket and Core-to-Fabric Interface 3 remote_socket_inbound_data_beats_cfi_4 data fabric  event=0x51e,umask=0xbfe  01    Inbound data beats (32 bytes) for transactions between remote socket and Core-to-Fabric Interface 4 remote_socket_inbound_data_beats_cfi_5 data fabric  event=0x55e,umask=0xbfe  01    Inbound data beats (32 bytes) for transactions between remote socket and Core-to-Fabric Interface 5 remote_socket_inbound_data_beats_cfi_6 data fabric  event=0x59e,umask=0xbfe  01    Inbound data beats (32 bytes) for transactions between remote socket and Core-to-Fabric Interface 6 remote_socket_inbound_data_beats_cfi_7 data fabric  event=0x5de,umask=0xbfe  01    Inbound data beats (32 bytes) for transactions between remote socket and Core-to-Fabric Interface 7 remote_socket_inbound_data_beats_cfi_8 data fabric  event=0x41f,umask=0xbfe  01    Inbound data beats (32 bytes) for transactions between remote socket and Core-to-Fabric Interface 8 remote_socket_inbound_data_beats_cfi_9 data fabric  event=0x45f,umask=0xbfe  01    Inbound data beats (32 bytes) for transactions between remote socket and Core-to-Fabric Interface 9 remote_socket_inbound_data_beats_cfi_10 data fabric  event=0x49f,umask=0xbfe  01    Inbound data beats (32 bytes) for transactions between remote socket and Core-to-Fabric Interface 10 remote_socket_inbound_data_beats_cfi_11 data fabric  event=0x4df,umask=0xbfe  01    Inbound data beats (32 bytes) for transactions between remote socket and Core-to-Fabric Interface 11 remote_socket_inbound_data_beats_cfi_12 data fabric  event=0x51f,umask=0xbfe  01    Inbound data beats (32 bytes) for transactions between remote socket and Core-to-Fabric Interface 12 remote_socket_inbound_data_beats_cfi_13 data fabric  event=0x55f,umask=0xbfe  01    Inbound data beats (32 bytes) for transactions between remote socket and Core-to-Fabric Interface 13 remote_socket_inbound_data_beats_cfi_14 data fabric  event=0x59f,umask=0xbfe  01    Inbound data beats (32 bytes) for transactions between remote socket and Core-to-Fabric Interface 14 remote_socket_inbound_data_beats_cfi_15 data fabric  event=0x5df,umask=0xbfe  01    Inbound data beats (32 bytes) for transactions between remote socket and Core-to-Fabric Interface 15 remote_socket_outbound_data_beats_cfi_0 data fabric  event=0x41e,umask=0xbff  01    Outbound data beats (64 bytes) for transactions between remote socket and Core-to-Fabric Interface 0 remote_socket_outbound_data_beats_cfi_1 data fabric  event=0x45e,umask=0xbff  01    Outbound data beats (64 bytes) for transactions between remote socket and Core-to-Fabric Interface 1 remote_socket_outbound_data_beats_cfi_2 data fabric  event=0x49e,umask=0xbff  01    Outbound data beats (64 bytes) for transactions between remote socket and Core-to-Fabric Interface 2 remote_socket_outbound_data_beats_cfi_3 data fabric  event=0x4de,umask=0xbff  01    Outbound data beats (64 bytes) for transactions between remote socket and Core-to-Fabric Interface 3 remote_socket_outbound_data_beats_cfi_4 data fabric  event=0x51e,umask=0xbff  01    Outbound data beats (64 bytes) for transactions between remote socket and Core-to-Fabric Interface 4 remote_socket_outbound_data_beats_cfi_5 data fabric  event=0x55e,umask=0xbff  01    Outbound data beats (64 bytes) for transactions between remote socket and Core-to-Fabric Interface 5 remote_socket_outbound_data_beats_cfi_6 data fabric  event=0x59e,umask=0xbff  01    Outbound data beats (64 bytes) for transactions between remote socket and Core-to-Fabric Interface 6 remote_socket_outbound_data_beats_cfi_7 data fabric  event=0x5de,umask=0xbff  01    Outbound data beats (64 bytes) for transactions between remote socket and Core-to-Fabric Interface 7 remote_socket_outbound_data_beats_cfi_8 data fabric  event=0x41f,umask=0xbff  01    Outbound data beats (64 bytes) for transactions between remote socket and Core-to-Fabric Interface 8 remote_socket_outbound_data_beats_cfi_9 data fabric  event=0x45f,umask=0xbff  01    Outbound data beats (64 bytes) for transactions between remote socket and Core-to-Fabric Interface 9 remote_socket_outbound_data_beats_cfi_10 data fabric  event=0x49f,umask=0xbff  01    Outbound data beats (64 bytes) for transactions between remote socket and Core-to-Fabric Interface 10 remote_socket_outbound_data_beats_cfi_11 data fabric  event=0x4df,umask=0xbff  01    Outbound data beats (64 bytes) for transactions between remote socket and Core-to-Fabric Interface 11 remote_socket_outbound_data_beats_cfi_12 data fabric  event=0x51f,umask=0xbff  01    Outbound data beats (64 bytes) for transactions between remote socket and Core-to-Fabric Interface 12 remote_socket_outbound_data_beats_cfi_13 data fabric  event=0x55f,umask=0xbff  01    Outbound data beats (64 bytes) for transactions between remote socket and Core-to-Fabric Interface 13 remote_socket_outbound_data_beats_cfi_14 data fabric  event=0x59f,umask=0xbff  01    Outbound data beats (64 bytes) for transactions between remote socket and Core-to-Fabric Interface 14 remote_socket_outbound_data_beats_cfi_15 data fabric  event=0x5df,umask=0xbff  01    Outbound data beats (64 bytes) for transactions between remote socket and Core-to-Fabric Interface 15 local_or_remote_socket_inbound_data_beats_cfi_0 data fabric  event=0x41e,umask=0xffe  01    Inbound data beats (32 bytes) for transactions between local or remote socket and Core-to-Fabric Interface 0 local_or_remote_socket_inbound_data_beats_cfi_1 data fabric  event=0x45e,umask=0xffe  01    Inbound data beats (32 bytes) for transactions between local or remote socket and Core-to-Fabric Interface 1 local_or_remote_socket_inbound_data_beats_cfi_2 data fabric  event=0x49e,umask=0xffe  01    Inbound data beats (32 bytes) for transactions between local or remote socket and Core-to-Fabric Interface 2 local_or_remote_socket_inbound_data_beats_cfi_3 data fabric  event=0x4de,umask=0xffe  01    Inbound data beats (32 bytes) for transactions between local or remote socket and Core-to-Fabric Interface 3 local_or_remote_socket_inbound_data_beats_cfi_4 data fabric  event=0x51e,umask=0xffe  01    Inbound data beats (32 bytes) for transactions between local or remote socket and Core-to-Fabric Interface 4 local_or_remote_socket_inbound_data_beats_cfi_5 data fabric  event=0x55e,umask=0xffe  01    Inbound data beats (32 bytes) for transactions between local or remote socket and Core-to-Fabric Interface 5 local_or_remote_socket_inbound_data_beats_cfi_6 data fabric  event=0x59e,umask=0xffe  01    Inbound data beats (32 bytes) for transactions between local or remote socket and Core-to-Fabric Interface 6 local_or_remote_socket_inbound_data_beats_cfi_7 data fabric  event=0x5de,umask=0xffe  01    Inbound data beats (32 bytes) for transactions between local or remote socket and Core-to-Fabric Interface 7 local_or_remote_socket_inbound_data_beats_cfi_8 data fabric  event=0x41f,umask=0xffe  01    Inbound data beats (32 bytes) for transactions between local or remote socket and Core-to-Fabric Interface 8 local_or_remote_socket_inbound_data_beats_cfi_9 data fabric  event=0x45f,umask=0xffe  01    Inbound data beats (32 bytes) for transactions between local or remote socket and Core-to-Fabric Interface 9 local_or_remote_socket_inbound_data_beats_cfi_10 data fabric  event=0x49f,umask=0xffe  01    Inbound data beats (32 bytes) for transactions between local or remote socket and Core-to-Fabric Interface 10 local_or_remote_socket_inbound_data_beats_cfi_11 data fabric  event=0x4df,umask=0xffe  01    Inbound data beats (32 bytes) for transactions between local or remote socket and Core-to-Fabric Interface 11 local_or_remote_socket_inbound_data_beats_cfi_12 data fabric  event=0x51f,umask=0xffe  01    Inbound data beats (32 bytes) for transactions between local or remote socket and Core-to-Fabric Interface 12 local_or_remote_socket_inbound_data_beats_cfi_13 data fabric  event=0x55f,umask=0xffe  01    Inbound data beats (32 bytes) for transactions between local or remote socket and Core-to-Fabric Interface 13 local_or_remote_socket_inbound_data_beats_cfi_14 data fabric  event=0x59f,umask=0xffe  01    Inbound data beats (32 bytes) for transactions between local or remote socket and Core-to-Fabric Interface 14 local_or_remote_socket_inbound_data_beats_cfi_15 data fabric  event=0x5df,umask=0xffe  01    Inbound data beats (32 bytes) for transactions between local or remote socket and Core-to-Fabric Interface 15 local_or_remote_socket_outbound_data_beats_cfi_0 data fabric  event=0x41e,umask=0xfff  01    Outbound data beats (64 bytes) for transactions between local or remote socket and Core-to-Fabric Interface 0 local_or_remote_socket_outbound_data_beats_cfi_1 data fabric  event=0x45e,umask=0xfff  01    Outbound data beats (64 bytes) for transactions between local or remote socket and Core-to-Fabric Interface 1 local_or_remote_socket_outbound_data_beats_cfi_2 data fabric  event=0x49e,umask=0xfff  01    Outbound data beats (64 bytes) for transactions between local or remote socket and Core-to-Fabric Interface 2 local_or_remote_socket_outbound_data_beats_cfi_3 data fabric  event=0x4de,umask=0xfff  01    Outbound data beats (64 bytes) for transactions between local or remote socket and Core-to-Fabric Interface 3 local_or_remote_socket_outbound_data_beats_cfi_4 data fabric  event=0x51e,umask=0xfff  01    Outbound data beats (64 bytes) for transactions between local or remote socket and Core-to-Fabric Interface 4 local_or_remote_socket_outbound_data_beats_cfi_5 data fabric  event=0x55e,umask=0xfff  01    Outbound data beats (64 bytes) for transactions between local or remote socket and Core-to-Fabric Interface 5 local_or_remote_socket_outbound_data_beats_cfi_6 data fabric  event=0x59e,umask=0xfff  01    Outbound data beats (64 bytes) for transactions between local or remote socket and Core-to-Fabric Interface 6 local_or_remote_socket_outbound_data_beats_cfi_7 data fabric  event=0x5de,umask=0xfff  01    Outbound data beats (64 bytes) for transactions between local or remote socket and Core-to-Fabric Interface 7 local_or_remote_socket_outbound_data_beats_cfi_8 data fabric  event=0x41f,umask=0xfff  01    Outbound data beats (64 bytes) for transactions between local or remote socket and Core-to-Fabric Interface 8 local_or_remote_socket_outbound_data_beats_cfi_9 data fabric  event=0x45f,umask=0xfff  01    Outbound data beats (64 bytes) for transactions between local or remote socket and Core-to-Fabric Interface 9 local_or_remote_socket_outbound_data_beats_cfi_10 data fabric  event=0x49f,umask=0xfff  01    Outbound data beats (64 bytes) for transactions between local or remote socket and Core-to-Fabric Interface 10 local_or_remote_socket_outbound_data_beats_cfi_11 data fabric  event=0x4df,umask=0xfff  01    Outbound data beats (64 bytes) for transactions between local or remote socket and Core-to-Fabric Interface 11 local_or_remote_socket_outbound_data_beats_cfi_12 data fabric  event=0x51f,umask=0xfff  01    Outbound data beats (64 bytes) for transactions between local or remote socket and Core-to-Fabric Interface 12 local_or_remote_socket_outbound_data_beats_cfi_13 data fabric  event=0x55f,umask=0xfff  01    Outbound data beats (64 bytes) for transactions between local or remote socket and Core-to-Fabric Interface 13 local_or_remote_socket_outbound_data_beats_cfi_14 data fabric  event=0x59f,umask=0xfff  01    Outbound data beats (64 bytes) for transactions between local or remote socket and Core-to-Fabric Interface 14 local_or_remote_socket_outbound_data_beats_cfi_15 data fabric  event=0x5df,umask=0xfff  01    Outbound data beats (64 bytes) for transactions between local or remote socket and Core-to-Fabric Interface 15 local_socket_inbound_data_beats_link_0 data fabric  event=0xd5f,umask=0xf3f  01    Inbound data beats (64 bytes) for transactions between local socket and remote socket over Cross-socket Link 0 local_socket_inbound_data_beats_link_1 data fabric  event=0xd9f,umask=0xf3f  01    Inbound data beats (64 bytes) for transactions between local socket and remote socket over Cross-socket Link 1 local_socket_inbound_data_beats_link_2 data fabric  event=0xddf,umask=0xf3f  01    Inbound data beats (64 bytes) for transactions between local socket and remote socket over Cross-socket Link 2 local_socket_inbound_data_beats_link_3 data fabric  event=0xe1f,umask=0xf3f  01    Inbound data beats (64 bytes) for transactions between local socket and remote socket over Cross-socket Link 3 local_socket_inbound_data_beats_link_4 data fabric  event=0xe5f,umask=0xf3f  01    Inbound data beats (64 bytes) for transactions between local socket and remote socket over Cross-socket Link 4 local_socket_inbound_data_beats_link_5 data fabric  event=0xe9f,umask=0xf3f  01    Inbound data beats (64 bytes) for transactions between local socket and remote socket over Cross-socket Link 5 local_socket_outbound_data_beats_link_0 data fabric  event=0xd5f,umask=0xf3e  01    Outbound data beats (64 bytes) for transactions between local socket and remote socket over Cross-socket Link 0 local_socket_outbound_data_beats_link_1 data fabric  event=0xd9f,umask=0xf3e  01    Outbound data beats (64 bytes) for transactions between local socket and remote socket over Cross-socket Link 1 local_socket_outbound_data_beats_link_2 data fabric  event=0xddf,umask=0xf3e  01    Outbound data beats (64 bytes) for transactions between local socket and remote socket over Cross-socket Link 2 local_socket_outbound_data_beats_link_3 data fabric  event=0xe1f,umask=0xf3e  01    Outbound data beats (64 bytes) for transactions between local socket and remote socket over Cross-socket Link 3 local_socket_outbound_data_beats_link_4 data fabric  event=0xe5f,umask=0xf3e  01    Outbound data beats (64 bytes) for transactions between local socket and remote socket over Cross-socket Link 4 local_socket_outbound_data_beats_link_5 data fabric  event=0xe9f,umask=0xf3e  01    Outbound data beats (64 bytes) for transactions between local socket and remote socket over Cross-socket Link 5 de_op_queue_empty decode Cycles where the op queue is empty. Such cycles indicate that the front-end is not delivering instructions fast enough event=0xa9  00     de_src_op_disp.x86_decoder decode Ops dispatched from x86 decoder event=0xaa,umask=1  00     de_src_op_disp.op_cache decode Ops dispatched from op cache event=0xaa,umask=2  00     de_src_op_disp.all decode Ops dispatched from any source event=0xaa,umask=7  00     de_dis_ops_from_decoder.any_fp_dispatch decode Number of ops dispatched to the floating-point unit event=0xab,umask=4  00     de_dis_ops_from_decoder.any_integer_dispatch decode Number of ops dispatched to the integer execution unit event=0xab,umask=8  00     de_dispatch_stall_cycle_dynamic_tokens_part1.int_phy_reg_file_rsrc_stall decode Cycles where a dispatch group is valid but does not get dispatched due to an integer physical register file resource stall event=0xae,umask=1  00     de_dispatch_stall_cycle_dynamic_tokens_part1.load_queue_rsrc_stall decode Cycles where a dispatch group is valid but does not get dispatched due to a lack of load queue tokens event=0xae,umask=2  00     de_dispatch_stall_cycle_dynamic_tokens_part1.store_queue_rsrc_stall decode Cycles where a dispatch group is valid but does not get dispatched due to a lack of store queue tokens event=0xae,umask=4  00     de_dispatch_stall_cycle_dynamic_tokens_part1.taken_brnch_buffer_rsrc decode Cycles where a dispatch group is valid but does not get dispatched due to a taken branch buffer resource stall event=0xae,umask=0x10  00     de_dispatch_stall_cycle_dynamic_tokens_part1.fp_sch_rsrc_stall decode Cycles where a dispatch group is valid but does not get dispatched due to a floating-point non-schedulable queue token stall event=0xae,umask=0x40  00     de_dispatch_stall_cycle_dynamic_tokens_part2.al_tokens decode Cycles where a dispatch group is valid but does not get dispatched due to unavailability of ALU tokens event=0xaf,umask=1  00     de_dispatch_stall_cycle_dynamic_tokens_part2.ag_tokens decode Cycles where a dispatch group is valid but does not get dispatched due to unavailability of agen tokens event=0xaf,umask=2  00     de_dispatch_stall_cycle_dynamic_tokens_part2.ex_flush_recovery decode Cycles where a dispatch group is valid but does not get dispatched due to a pending integer execution flush recovery event=0xaf,umask=4  00     de_dispatch_stall_cycle_dynamic_tokens_part2.retq decode Cycles where a dispatch group is valid but does not get dispatched due to unavailability of retire queue tokens event=0xaf,umask=0x20  00     de_no_dispatch_per_slot.no_ops_from_frontend decode In each cycle counts dispatch slots left empty because the front-end did not supply ops event=0x1a0,umask=1  00     de_no_dispatch_per_slot.backend_stalls decode In each cycle counts ops unable to dispatch because of back-end stalls event=0x1a0,umask=0x1e  00     de_no_dispatch_per_slot.smt_contention decode In each cycle counts ops unable to dispatch because the dispatch cycle was granted to the other SMT thread event=0x1a0,umask=0x60  00     de_additional_resource_stalls.dispatch_stalls decode Counts additional cycles where dispatch is stalled due to a lack of dispatch resources event=0x1a2,umask=0x30  00     ex_ret_instr execution Retired instructions event=0xc0  00     ex_ret_ops execution Retired macro-ops event=0xc1  00     ex_ret_brn execution Retired branch instructions (all types of architectural control flow changes, including exceptions and interrupts) event=0xc2  00     ex_ret_brn_misp execution Retired branch instructions mispredicted event=0xc3  00     ex_ret_brn_tkn execution Retired taken branch instructions (all types of architectural control flow changes, including exceptions and interrupts) event=0xc4  00     ex_ret_brn_tkn_misp execution Retired taken branch instructions mispredicted event=0xc5  00     ex_ret_brn_far execution Retired far control transfers (far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts). Far control transfers are not subject to branch prediction event=0xc6  00     ex_ret_near_ret execution Retired near returns (RET or RET Iw) event=0xc8  00     ex_ret_near_ret_mispred execution Retired near returns mispredicted. Each misprediction incurs the same penalty as a mispredicted conditional branch instruction event=0xc9  00     ex_ret_brn_ind_misp execution Retired indirect branch instructions mispredicted (only EX mispredicts). Each misprediction incurs the same penalty as a mispredicted conditional branch instruction event=0xca  00     ex_ret_mmx_fp_instr.x87 execution Retired x87 instructions event=0xcb,umask=1  00     ex_ret_mmx_fp_instr.mmx execution Retired MMX instructions event=0xcb,umask=2  00     ex_ret_mmx_fp_instr.sse execution Retired SSE instructions (includes SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42 and AVX) event=0xcb,umask=4  00     ex_ret_ind_brch_instr execution Retired indirect branch instructions event=0xcc  00     ex_ret_cond execution Retired conditional branch instructions event=0xd1  00     ex_div_busy execution Number of cycles the divider is busy event=0xd3  00     ex_div_count execution Divide ops executed event=0xd4  00     ex_no_retire.empty execution Cycles with no retire due  to the lack of valid ops in the retire queue (may be caused by front-end bottlenecks or pipeline redirects) event=0xd6,umask=1  00     ex_no_retire.not_complete execution Cycles with no retire while the oldest op is waiting to be executed event=0xd6,umask=2  00     ex_no_retire.other execution Cycles with no retire caused by other reasons (retire breaks, traps, faults, etc.) event=0xd6,umask=8  00     ex_no_retire.thread_not_selected execution Cycles with no retire because thread arbitration did not select the thread event=0xd6,umask=0x10  00     ex_no_retire.load_not_complete execution Cycles with no retire while the oldest op is waiting for load data event=0xd6,umask=0xa2  00     ex_no_retire.all execution Cycles with no retire for any reason event=0xd6,umask=0x1b  00     ex_ret_ucode_instr execution Retired microcoded instructions event=0x1c1  00     ex_ret_ucode_ops execution Retired microcode ops event=0x1c2  00     ex_ret_msprd_brnch_instr_dir_msmtch execution Retired branch instructions mispredicted due to direction mismatch event=0x1c7  00     ex_ret_uncond_brnch_instr_mispred execution Retired unconditional indirect branch instructions mispredicted event=0x1c8  00     ex_ret_uncond_brnch_instr execution Retired unconditional branch instructions event=0x1c9  00     ex_tagged_ibs_ops.ibs_tagged_ops execution Ops tagged by IBS event=0x1cf,umask=1  00     ex_tagged_ibs_ops.ibs_tagged_ops_ret execution Ops tagged by IBS that retired event=0x1cf,umask=2  00     ex_tagged_ibs_ops.ibs_count_rollover execution Ops not tagged by IBS due to a previous tagged op that has not yet signaled interrupt event=0x1cf,umask=4  00     ex_ret_fused_instr execution Retired fused instructions event=0x1d0  00     fp_ret_sse_avx_ops.bfloat16_flops floating point Retired SSE and AVX floating-point bfloat16 ops event=3,umask=0x20  00     fp_ret_sse_avx_ops.scalar_single_flops floating point Retired SSE and AVX floating-point scalar single-precision ops event=3,umask=0x40  00     fp_ret_sse_avx_ops.packed_single_flops floating point Retired SSE and AVX floating-point packed single-precision ops event=3,umask=0x60  00     fp_ret_sse_avx_ops.scalar_double_flops floating point Retired SSE and AVX floating-point scalar double-precision ops event=3,umask=0x80  00     fp_ret_sse_avx_ops.packed_double_flops floating point Retired SSE and AVX floating-point packed double-precision ops event=3,umask=0xa0  00     fp_ret_sse_avx_ops.all floating point Retired SSE and AVX floating-point ops of all types event=3,umask=0xf  00     ic_cache_fill_l2 inst cache Instruction cache lines (64 bytes) fulfilled from the L2 cache event=0x82  00     ic_cache_fill_sys inst cache Instruction cache lines (64 bytes) fulfilled from system memory or another cache event=0x83  00     ic_fetch_ibs_events.fetch_tagged inst cache Fetches tagged by Fetch IBS. Not all tagged fetches result in a valid sample and an IBS interrupt event=0x188,umask=2  00     ic_fetch_ibs_events.sample_discarded inst cache Fetches discarded after being tagged by Fetch IBS due to reasons other than IBS filtering event=0x188,umask=4  00     ic_fetch_ibs_events.sample_filtered inst cache Fetches discarded after being tagged by Fetch IBS due to IBS filtering event=0x188,umask=8  00     ic_fetch_ibs_events.sample_valid inst cache Fetches tagged by Fetch IBS that result in a valid sample and an IBS interrupt event=0x188,umask=0x10  00     ic_tag_hit_miss.instruction_cache_hit inst cache Instruction cache hits event=0x18e,umask=7  00     ic_tag_hit_miss.instruction_cache_miss inst cache Instruction cache misses event=0x18e,umask=0x18  00     ic_tag_hit_miss.all_instruction_cache_accesses inst cache Instruction cache accesses of all types event=0x18e,umask=0x1f  00     op_cache_hit_miss.op_cache_hit inst cache Op cache hits event=0x28f,umask=3  00     op_cache_hit_miss.op_cache_miss inst cache Op cache misses event=0x28f,umask=4  00     op_cache_hit_miss.all_op_cache_accesses inst cache Op cache accesses of all types event=0x28f,umask=7  00     l2_request_g1.group2 l2 cache L2 cache requests of non-cacheable type (non-cached data and instructions reads, self-modifying code checks) event=0x60,umask=1  00     l2_request_g1.l2_hw_pf l2 cache L2 cache requests: from hardware prefetchers to prefetch directly into L2 (hit or miss) event=0x60,umask=2  00     l2_request_g1.prefetch_l2_cmd l2 cache L2 cache requests: prefetch directly into L2 event=0x60,umask=4  00     l2_request_g1.cacheable_ic_read l2 cache L2 cache requests: instruction cache reads event=0x60,umask=0x10  00     l2_request_g1.ls_rd_blk_c_s l2 cache L2 cache requests: data cache shared reads event=0x60,umask=0x20  00     l2_request_g1.rd_blk_x l2 cache L2 cache requests: data cache stores event=0x60,umask=0x40  00     l2_request_g1.rd_blk_l l2 cache L2 cache requests: data cache reads including hardware and software prefetch event=0x60,umask=0x80  00     l2_request_g1.all_dc l2 cache L2 cache requests of common types from L1 data cache (including prefetches) event=0x60,umask=0xe0  00     l2_request_g1.all_no_prefetch l2 cache L2 cache requests of common types not including prefetches event=0x60,umask=0xf1  00     l2_request_g1.all l2 cache L2 cache requests of all types event=0x60,umask=0xf7  00     l2_request_g2.ls_rd_sized_nc l2 cache L2 cache requests: non-coherent, non-cacheable LS sized reads event=0x61,umask=0x20  00     l2_request_g2.ls_rd_sized l2 cache L2 cache requests: coherent, non-cacheable LS sized reads event=0x61,umask=0x40  00     l2_wcb_req.wcb_close l2 cache Write Combining Buffer (WCB) closures event=0x63,umask=0x20  00     l2_cache_req_stat.ic_fill_miss l2 cache Core to L2 cache requests (not including L2 prefetch) with status: instruction cache request miss in L2 event=0x64,umask=1  00     l2_cache_req_stat.ic_fill_hit_s l2 cache Core to L2 cache requests (not including L2 prefetch) with status: instruction cache hit non-modifiable line in L2 event=0x64,umask=2  00     l2_cache_req_stat.ic_fill_hit_x l2 cache Core to L2 cache requests (not including L2 prefetch) with status: instruction cache hit modifiable line in L2 event=0x64,umask=4  00     l2_cache_req_stat.ic_hit_in_l2 l2 cache Core to L2 cache requests (not including L2 prefetch) for instruction cache hits event=0x64,umask=6  00     l2_cache_req_stat.ic_access_in_l2 l2 cache Core to L2 cache requests (not including L2 prefetch) for instruction cache access event=0x64,umask=7  00     l2_cache_req_stat.ls_rd_blk_c l2 cache Core to L2 cache requests (not including L2 prefetch) with status: data cache request miss in L2 event=0x64,umask=8  00     l2_cache_req_stat.ic_dc_miss_in_l2 l2 cache Core to L2 cache requests (not including L2 prefetch) for data and instruction cache misses event=0x64,umask=9  00     l2_cache_req_stat.ls_rd_blk_x l2 cache Core to L2 cache requests (not including L2 prefetch) with status: data cache store or state change hit in L2 event=0x64,umask=0x10  00     l2_cache_req_stat.ls_rd_blk_l_hit_s l2 cache Core to L2 cache requests (not including L2 prefetch) with status: data cache read hit non-modifiable line in L2 event=0x64,umask=0x20  00     l2_cache_req_stat.ls_rd_blk_l_hit_x l2 cache Core to L2 cache requests (not including L2 prefetch) with status: data cache read hit modifiable line in L2 event=0x64,umask=0x40  00     l2_cache_req_stat.ls_rd_blk_cs l2 cache Core to L2 cache requests (not including L2 prefetch) with status: data cache shared read hit in L2 event=0x64,umask=0x80  00     l2_cache_req_stat.dc_hit_in_l2 l2 cache Core to L2 cache requests (not including L2 prefetch) for data cache hits event=0x64,umask=0xf0  00     l2_cache_req_stat.ic_dc_hit_in_l2 l2 cache Core to L2 cache requests (not including L2 prefetch) for data and instruction cache hits event=0x64,umask=0xf6  00     l2_cache_req_stat.dc_access_in_l2 l2 cache Core to L2 cache requests (not including L2 prefetch) for data cache access event=0x64,umask=0xf8  00     l2_cache_req_stat.all l2 cache Core to L2 cache requests (not including L2 prefetch) for data and instruction cache access event=0x64,umask=0xff  00     l2_pf_hit_l2.l2_hwpf l2 cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache and are generated from L2 hardware prefetchers event=0x70,umask=0x1f  00     l2_pf_hit_l2.l1_dc_hwpf l2 cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache and are generated from L1 data hardware prefetchers event=0x70,umask=0xe0  00     l2_pf_hit_l2.l1_dc_l2_hwpf l2 cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache and are generated from L1 data and L2 hardware prefetchers event=0x70,umask=0xff  00     l2_pf_miss_l2_hit_l3.l2_hwpf l2 cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache but hit in the L3 cache and are generated from L2 hardware prefetchers event=0x71,umask=0x1f  00     l2_pf_miss_l2_hit_l3.l1_dc_hwpf l2 cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache but hit in the L3 cache and are generated from L1 data hardware prefetchers event=0x71,umask=0xe0  00     l2_pf_miss_l2_hit_l3.l1_dc_l2_hwpf l2 cache L2 prefetches accepted by the L2 pipeline which miss the L2 cache but hit in the L3 cache and are generated from L1 data and L2 hardware prefetchers event=0x71,umask=0xff  00     l2_pf_miss_l2_l3.l2_hwpf l2 cache L2 prefetches accepted by the L2 pipeline which miss the L2 as well as the L3 caches and are generated from L2 hardware prefetchers event=0x72,umask=0x1f  00     l2_pf_miss_l2_l3.l1_dc_hwpf l2 cache L2 prefetches accepted by the L2 pipeline which miss the L2 as well as the L3 caches and are generated from L1 data hardware prefetchers event=0x72,umask=0xe0  00     l2_pf_miss_l2_l3.l1_dc_l2_hwpf l2 cache L2 prefetches accepted by the L2 pipeline which miss the L2 as well as the L3 caches and are generated from L1 data and L2 hardware prefetchers event=0x72,umask=0xff  00     l2_fill_rsp_src.local_ccx l2 cache L2 cache fills from L3 cache or different L2 cache in the same CCX event=0x165,umask=2  00     l2_fill_rsp_src.near_cache l2 cache L2 cache fills from cache of another CCX when the address was in the same NUMA node event=0x165,umask=4  00     l2_fill_rsp_src.dram_io_near l2 cache L2 cache fills from either DRAM or MMIO in the same NUMA node event=0x165,umask=8  00     l2_fill_rsp_src.far_cache l2 cache L2 cache fills from cache of another CCX when the address was in a different NUMA node event=0x165,umask=0x10  00     l2_fill_rsp_src.dram_io_far l2 cache L2 cache fills from either DRAM or MMIO in a different NUMA node (same or different socket) event=0x165,umask=0x40  00     l2_fill_rsp_src.alternate_memories l2 cache L2 cache fills from extension memory event=0x165,umask=0x80  00     l2_fill_rsp_src.all l2 cache L2 cache fills from all types of data sources event=0x165,umask=0xde  00     l3_lookup_state.l3_miss l3 cache L3 cache misses event=4,umask=1  00     l3_lookup_state.l3_hit l3 cache L3 cache hits event=4,umask=0xfe  00     l3_lookup_state.all_coherent_accesses_to_l3 l3 cache L3 cache requests for all coherent accesses event=4,umask=0xff  00     l3_xi_sampled_latency.dram_near l3 cache Average sampled latency when data is sourced from DRAM in the same NUMA node event=0xac,umask=1,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency.dram_far l3 cache Average sampled latency when data is sourced from DRAM in a different NUMA node event=0xac,umask=2,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency.near_cache l3 cache Average sampled latency when data is sourced from another CCX's cache when the address was in the same NUMA node event=0xac,umask=4,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency.far_cache l3 cache Average sampled latency when data is sourced from another CCX's cache when the address was in a different NUMA node event=0xac,umask=8,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency.ext_near l3 cache Average sampled latency when data is sourced from extension memory (CXL) in the same NUMA node event=0xac,umask=0x10,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency.ext_far l3 cache Average sampled latency when data is sourced from extension memory (CXL) in a different NUMA node event=0xac,umask=0x20,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency.all l3 cache Average sampled latency from all data sources event=0xac,umask=0x3f,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency_requests.dram_near l3 cache L3 cache fill requests sourced from DRAM in the same NUMA node event=0xad,umask=1,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency_requests.dram_far l3 cache L3 cache fill requests sourced from DRAM in a different NUMA node event=0xad,umask=2,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency_requests.near_cache l3 cache L3 cache fill requests sourced from another CCX's cache when the address was in the same NUMA node event=0xad,umask=4,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency_requests.far_cache l3 cache L3 cache fill requests sourced from another CCX's cache when the address was in a different NUMA node event=0xad,umask=8,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency_requests.ext_near l3 cache L3 cache fill requests sourced from extension memory (CXL) in the same NUMA node event=0xad,umask=0x10,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency_requests.ext_far l3 cache L3 cache fill requests sourced from extension memory (CXL) in a different NUMA node event=0xad,umask=0x20,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency_requests.all l3 cache L3 cache fill requests sourced from all data sources event=0xad,umask=0x3f,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     ls_bad_status2.stli_other load store Store-to-load conflicts (load unable to complete due to a non-forwardable conflict with an older store) event=0x24,umask=2  00     ls_locks.bus_lock load store Retired Lock instructions which caused a bus lock event=0x25,umask=1  00     ls_ret_cl_flush load store Retired CLFLUSH instructions event=0x26  00     ls_ret_cpuid load store Retired CPUID instructions event=0x27  00     ls_dispatch.ld_dispatch load store Number of memory load operations dispatched to the load-store unit event=0x29,umask=1  00     ls_dispatch.store_dispatch load store Number of memory store operations dispatched to the load-store unit event=0x29,umask=2  00     ls_dispatch.ld_st_dispatch load store Number of memory load-store operations dispatched to the load-store unit event=0x29,umask=4  00     ls_dispatch.all load store Number of memory operations dispatched to the load-store unit event=0x29,umask=7  00     ls_smi_rx load store SMIs received event=0x2b  00     ls_int_taken load store Interrupts taken event=0x2c  00     ls_stlf load store Store-to-load-forward (STLF) hits event=0x35  00     ls_st_commit_cancel2.st_commit_cancel_wcb_full load store Non-cacheable store commits cancelled due to the non-cacheable commit buffer being full event=0x37,umask=1  00     ls_mab_alloc.load_store_allocations load store Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for load-store allocations event=0x41,umask=7  00     ls_mab_alloc.hardware_prefetcher_allocations load store Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for hardware prefetcher allocations event=0x41,umask=8  00     ls_mab_alloc.all_allocations load store Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for all types of allocations event=0x41,umask=0xf  00     ls_dmnd_fills_from_sys.local_l2 load store Demand data cache fills from local L2 cache event=0x43,umask=1  00     ls_dmnd_fills_from_sys.local_ccx load store Demand data cache fills from L3 cache or different L2 cache in the same CCX event=0x43,umask=2  00     ls_dmnd_fills_from_sys.local_all load store Demand data cache fills from local L2 cache, L3 cache or different L2 cache in the same CCX event=0x43,umask=3  00     ls_dmnd_fills_from_sys.near_cache load store Demand data cache fills from cache of another CCX when the address was in the same NUMA node event=0x43,umask=4  00     ls_dmnd_fills_from_sys.dram_io_near load store Demand data cache fills from either DRAM or MMIO in the same NUMA node event=0x43,umask=8  00     ls_dmnd_fills_from_sys.far_cache load store Demand data cache fills from cache of another CCX when the address was in a different NUMA node event=0x43,umask=0x10  00     ls_dmnd_fills_from_sys.remote_cache load store Demand data cache fills from cache of another CCX when the address was in the same or a different NUMA node event=0x43,umask=0x14  00     ls_dmnd_fills_from_sys.dram_io_far load store Demand data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket) event=0x43,umask=0x40  00     ls_dmnd_fills_from_sys.dram_io_all load store Demand data cache fills from either DRAM or MMIO in the same or a different NUMA node (same or different socket) event=0x43,umask=0x48  00     ls_dmnd_fills_from_sys.far_all load store Demand data cache fills from either cache of another CCX, DRAM or MMIO when the address was in a different NUMA node (same or different socket) event=0x43,umask=0x50  00     ls_dmnd_fills_from_sys.alternate_memories load store Demand data cache fills from extension memory event=0x43,umask=0x80  00     ls_dmnd_fills_from_sys.all load store Demand data cache fills from all types of data sources event=0x43,umask=0xff  00     ls_any_fills_from_sys.local_l2 load store Any data cache fills from local L2 cache event=0x44,umask=1  00     ls_any_fills_from_sys.local_ccx load store Any data cache fills from L3 cache or different L2 cache in the same CCX event=0x44,umask=2  00     ls_any_fills_from_sys.local_all load store Any data cache fills from local L2 cache or L3 cache or different L2 cache in the same CCX event=0x44,umask=3  00     ls_any_fills_from_sys.near_cache load store Any data cache fills from cache of another CCX when the address was in the same NUMA node event=0x44,umask=4  00     ls_any_fills_from_sys.dram_io_near load store Any data cache fills from either DRAM or MMIO in the same NUMA node event=0x44,umask=8  00     ls_any_fills_from_sys.far_cache load store Any data cache fills from cache of another CCX when the address was in a different NUMA node event=0x44,umask=0x10  00     ls_any_fills_from_sys.remote_cache load store Any data cache fills from cache of another CCX when the address was in the same or a different NUMA node event=0x44,umask=0x14  00     ls_any_fills_from_sys.dram_io_far load store Any data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket) event=0x44,umask=0x40  00     ls_any_fills_from_sys.dram_io_all load store Any data cache fills from either DRAM or MMIO in any NUMA node (same or different socket) event=0x44,umask=0x48  00     ls_any_fills_from_sys.far_all load store Any data cache fills from either cache of another CCX, DRAM or MMIO when the address was in a different NUMA node (same or different socket) event=0x44,umask=0x50  00     ls_any_fills_from_sys.alternate_memories load store Any data cache fills from extension memory event=0x44,umask=0x80  00     ls_any_fills_from_sys.all load store Any data cache fills from all types of data sources event=0x44,umask=0xff  00     ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit load store L1 DTLB misses with L2 DTLB hits for 4k pages event=0x45,umask=1  00     ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit load store L1 DTLB misses with L2 DTLB hits for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages event=0x45,umask=2  00     ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit load store L1 DTLB misses with L2 DTLB hits for 2M pages event=0x45,umask=4  00     ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit load store L1 DTLB misses with L2 DTLB hits for 1G pages event=0x45,umask=8  00     ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss load store L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 4k pages event=0x45,umask=0x10  00     ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss load store L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages event=0x45,umask=0x20  00     ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss load store L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 2M pages event=0x45,umask=0x40  00     ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss load store L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 1G pages event=0x45,umask=0x80  00     ls_l1_d_tlb_miss.all_l2_miss load store L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for all page sizes event=0x45,umask=0xf0  00     ls_l1_d_tlb_miss.all load store L1 DTLB misses for all page sizes event=0x45,umask=0xff  00     ls_misal_loads.ma64 load store 64B misaligned (cacheline crossing) loads event=0x47,umask=1  00     ls_misal_loads.ma4k load store 4kB misaligned (page crossing) loads event=0x47,umask=2  00     ls_pref_instr_disp.prefetch load store Software prefetch instructions dispatched (speculative) of type PrefetchT0 (move data to all cache levels), T1 (move data to all cache levels except L1) and T2 (move data to all cache levels except L1 and L2) event=0x4b,umask=1  00     ls_pref_instr_disp.prefetch_w load store Software prefetch instructions dispatched (speculative) of type PrefetchW (move data to L1 cache and mark it modifiable) event=0x4b,umask=2  00     ls_pref_instr_disp.prefetch_nta load store Software prefetch instructions dispatched (speculative) of type PrefetchNTA (move data with minimum cache pollution i.e. non-temporal access) event=0x4b,umask=4  00     ls_pref_instr_disp.all load store Software prefetch instructions dispatched (speculative) of all types event=0x4b,umask=7  00     wcb_close.full_line_64b load store Number of events that caused a Write Combining Buffer (WCB) entry to close because all 64 bytes of the entry have been written to event=0x50,umask=1  00     ls_inef_sw_pref.data_pipe_sw_pf_dc_hit load store Software prefetches that did not fetch data outside of the processor core as the PREFETCH instruction saw a data cache hit event=0x52,umask=1  00     ls_inef_sw_pref.mab_mch_cnt load store Software prefetches that did not fetch data outside of the processor core as the PREFETCH instruction saw a match on an already allocated Miss Address Buffer (MAB) event=0x52,umask=2  00     ls_inef_sw_pref.all load store  event=0x52,umask=3  00     ls_sw_pf_dc_fills.local_l2 load store Software prefetch data cache fills from local L2 cache event=0x59,umask=1  00     ls_sw_pf_dc_fills.local_ccx load store Software prefetch data cache fills from L3 cache or different L2 cache in the same CCX event=0x59,umask=2  00     ls_sw_pf_dc_fills.local_all load store Software prefetch data cache fills from local L2 cache, L3 cache or different L2 cache in the same CCX event=0x59,umask=3  00     ls_sw_pf_dc_fills.near_cache load store Software prefetch data cache fills from cache of another CCX in the same NUMA node event=0x59,umask=4  00     ls_sw_pf_dc_fills.dram_io_near load store Software prefetch data cache fills from either DRAM or MMIO in the same NUMA node event=0x59,umask=8  00     ls_sw_pf_dc_fills.far_cache load store Software prefetch data cache fills from cache of another CCX in a different NUMA node event=0x59,umask=0x10  00     ls_sw_pf_dc_fills.remote_cache load store Software prefetch data cache fills from cache of another CCX when the address was in the same or a different NUMA node event=0x59,umask=0x14  00     ls_sw_pf_dc_fills.dram_io_far load store Software prefetch data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket) event=0x59,umask=0x40  00     ls_sw_pf_dc_fills.dram_io_all load store Software prefetch data cache fills from either DRAM or MMIO in the same or a different NUMA node (same or different socket) event=0x59,umask=0x48  00     ls_sw_pf_dc_fills.far_all load store Software prefetch data cache fills from either cache of another CCX, DRAM or MMIO when the address was in a different NUMA node (same or different socket) event=0x59,umask=0x50  00     ls_sw_pf_dc_fills.alternate_memories load store Software prefetch data cache fills from extension memory event=0x59,umask=0x80  00     ls_sw_pf_dc_fills.all load store Software prefetch data cache fills from all types of data sources event=0x59,umask=0xdf  00     ls_hw_pf_dc_fills.local_l2 load store Hardware prefetch data cache fills from local L2 cache event=0x5a,umask=1  00     ls_hw_pf_dc_fills.local_ccx load store Hardware prefetch data cache fills from L3 cache or different L2 cache in the same CCX event=0x5a,umask=2  00     ls_hw_pf_dc_fills.local_all load store Hardware prefetch data cache fills from local L2 cache, L3 cache or different L2 cache in the same CCX event=0x5a,umask=3  00     ls_hw_pf_dc_fills.near_cache load store Hardware prefetch data cache fills from cache of another CCX when the address was in the same NUMA node event=0x5a,umask=4  00     ls_hw_pf_dc_fills.dram_io_near load store Hardware prefetch data cache fills from either DRAM or MMIO in the same NUMA node event=0x5a,umask=8  00     ls_hw_pf_dc_fills.far_cache load store Hardware prefetch data cache fills from cache of another CCX when the address was in a different NUMA node event=0x5a,umask=0x10  00     ls_hw_pf_dc_fills.remote_cache load store Hardware prefetch data cache fills from cache of another CCX when the address was in the same or a different NUMA node event=0x5a,umask=0x14  00     ls_hw_pf_dc_fills.dram_io_far load store Hardware prefetch data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket) event=0x5a,umask=0x40  00     ls_hw_pf_dc_fills.dram_io_all load store Hardware prefetch data cache fills from either DRAM or MMIO in the same or a different NUMA node (same or different socket) event=0x5a,umask=0x48  00     ls_hw_pf_dc_fills.far_all load store Hardware prefetch data cache fills from either cache of another CCX, DRAM or MMIO when the address was in a different NUMA node (same or different socket) event=0x5a,umask=0x50  00     ls_hw_pf_dc_fills.alternate_memories load store Hardware prefetch data cache fills from extension memory event=0x5a,umask=0x80  00     ls_hw_pf_dc_fills.all load store Hardware prefetch data cache fills from all types of data sources event=0x5a,umask=0xdf  00     ls_alloc_mab_count load store In-flight L1 data cache misses i.e. Miss Address Buffer (MAB) allocations each cycle event=0x5f  00     ls_not_halted_cyc load store Core cycles not in halt event=0x76  00     ls_tlb_flush.all load store All TLB Flushes event=0x78,umask=0xff  00     ls_not_halted_p0_cyc.p0_freq_cyc load store Reference cycles (P0 frequency) not in halt  event=0x120,umask=1  00     umc_mem_clk memory controller  event=0  01    Number of memory clock (MEMCLK) cycles umc_data_slot_clks.all memory controller  event=0x14  01    Number of clock cycles used by the data bus umc_data_slot_clks.rd memory controller  event=0x14,rdwrmask=1  01    Number of clock cycles used by the data bus for reads umc_data_slot_clks.wr memory controller  event=0x14,rdwrmask=2  01    Number of clock cycles used by the data bus for writes bp_l1_tlb_miss_l2_tlb_miss.if4k branch prediction Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks requested) for 4k pages event=0x85,umask=1  00     bp_l1_tlb_miss_l2_tlb_miss.if2m branch prediction Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks requested) for 2M pages event=0x85,umask=2  00     bp_l1_tlb_miss_l2_tlb_miss.if1g branch prediction Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks requested) for 1G pages event=0x85,umask=4  00     bp_l1_tlb_miss_l2_tlb_miss.coalesced_4k branch prediction Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks requested) for coalesced pages (16k pages created from four adjacent 4k pages) event=0x85,umask=8  00     bp_l1_tlb_miss_l2_tlb_miss.all branch prediction Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks requested) for all page sizes event=0x85,umask=0xf  00     bp_pipe_correct branch prediction Branch predictor pipeline flushes due to internal conditions such as a second level prediction structure event=0x8b  00     bp_var_target_pred branch prediction Indirect predictions (branch used the indirect predictor to make a prediction) event=0x8e  00     bp_early_redir branch prediction Early redirects sent to branch predictor. This happens when either the decoder or dispatch logic is able to detect that the branch predictor needs to be redirected event=0x91  00     bp_l1_tlb_fetch_hit.if4k branch prediction Instruction fetches that hit in the L1 ITLB for 4k or coalesced pages (16k pages created from four adjacent 4k pages) event=0x94,umask=1  00     bp_fe_redir.resync branch prediction Redirects of the pipeline frontend caused by resyncs. These are retire time pipeline restarts event=0x9f,umask=1  00     bp_fe_redir.ex_redir branch prediction Redirects of the pipeline frontend caused by mispredicts. These are used for branch direction correction and handling indirect branch target mispredicts event=0x9f,umask=2  00     bp_fe_redir.all branch prediction Redirects of the pipeline frontend caused by any reason event=0x9f  00     de_op_queue_empty decode Cycles where the op queue is empty. Such cycles indicate that the frontend is not delivering instructions fast enough event=0xa9  00     de_dis_ops_from_decoder.any_fp decode Ops dispatched from the decoder to a floating-point unit event=0xab,umask=4  00     de_dis_ops_from_decoder.any_int decode Ops dispatched from the decoder to an integer unit event=0xab,umask=8  00     de_disp_stall_cycles_dynamic_tokens_part1.int_phy_reg_file_rsrc_stall decode Cycles where a dispatch group is valid but does not get dispatched due to integer physical register file resource stalls event=0xae,umask=1  00     de_dispatch_stall_cycle_dynamic_tokens_part1.load_queue_rsrc_stall decode Cycles where a dispatch group is valid but does not get dispatched due to load queue token stalls event=0xae,umask=2  00     de_dispatch_stall_cycle_dynamic_tokens_part1.store_queue_rsrc_stall decode Cycles where a dispatch group is valid but does not get dispatched due to store queue token stalls event=0xae,umask=4  00     de_dispatch_stall_cycle_dynamic_tokens_part1.taken_brnch_buffer_rsrc decode Cycles where a dispatch group is valid but does not get dispatched due to taken branch buffer resource stalls event=0xae,umask=0x10  00     de_dispatch_stall_cycle_dynamic_tokens_part1.fp_sch_rsrc_stall decode Cycles where a dispatch group is valid but does not get dispatched due to floating-point non-schedulable queue token stalls event=0xae,umask=0x40  00     de_dispatch_stall_cycle_dynamic_tokens_part2.int_sq0 decode Cycles where a dispatch group is valid but does not get dispatched due to unavailability of integer scheduler 0 tokens event=0xaf,umask=1  00     de_dispatch_stall_cycle_dynamic_tokens_part2.int_sq1 decode Cycles where a dispatch group is valid but does not get dispatched due to unavailability of integer scheduler 1 tokens event=0xaf,umask=2  00     de_dispatch_stall_cycle_dynamic_tokens_part2.int_sq2 decode Cycles where a dispatch group is valid but does not get dispatched due to unavailability of integer scheduler 2 tokens event=0xaf,umask=4  00     de_dispatch_stall_cycle_dynamic_tokens_part2.int_sq3 decode Cycles where a dispatch group is valid but does not get dispatched due to unavailability of integer scheduler 3 tokens event=0xaf,umask=8  00     de_dispatch_stall_cycle_dynamic_tokens_part2.int_sq4 decode Cycles where a dispatch group is valid but does not get dispatched due to unavailability of integer scheduler 4 tokens event=0xaf,umask=0x10  00     de_dispatch_stall_cycle_dynamic_tokens_part2.int_sq5 decode Cycles where a dispatch group is valid but does not get dispatched due to unavailability of integer scheduler 5 tokens event=0xaf,umask=0x20  00     de_dispatch_stall_cycle_dynamic_tokens_part2.ret_q decode Cycles where a dispatch group is valid but does not get dispatched due to unavailability of retire queue tokens event=0xaf,umask=0x80  00     de_dispatch_stall_cycle_dynamic_tokens_part2.all decode Cycles where a dispatch group is valid but does not get dispatched due to any token stalls event=0xaf,umask=0xbf  00     de_no_dispatch_per_slot.no_ops_from_frontend decode Dispatch slots in each cycle that were empty because the frontend did not supply ops event=0x1a0,umask=1  00     de_no_dispatch_per_slot.backend_stalls decode Dispatch slots in each cycle that were unused because of backend stalls event=0x1a0,umask=0x1e  00     de_no_dispatch_per_slot.smt_contention decode Dispatch slots in each cycle that were unused because the dispatch cycle was granted to the other SMT thread event=0x1a0,umask=0x60  00     ex_ret_brn_misp execution Retired branch instructions that were mispredicted event=0xc3  00     ex_ret_brn_tkn_misp execution Retired taken branch instructions that were mispredicted event=0xc5  00     ex_ret_brn_far execution Retired far control transfers (far call, far jump, far return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts). Far control transfers are not subject to branch prediction event=0xc6  00     ex_ret_near_ret_mispred execution Retired near returns that were mispredicted. Each misprediction incurs the same penalty as that of a mispredicted conditional branch instruction event=0xc9  00     ex_ret_brn_ind_misp execution Retired indirect branch instructions that were mispredicted (only EX mispredicts). Each misprediction incurs the same penalty as that of a mispredicted conditional branch instruction event=0xca  00     ex_ret_brn_ind execution Retired indirect branch instructions event=0xcc  00     ex_ret_brn_cond execution Retired conditional branch instructions event=0xd1  00     ex_div_busy execution Cycles where the divider is busy event=0xd3  00     ex_no_retire.empty execution Cycles where the thread does not retire any ops due to a lack of valid ops in the retire queue (may be caused by front-end bottlenecks or pipeline redirects) event=0xd6,umask=1  00     ex_no_retire.not_complete execution Cycles where the thread does not retire any ops as the oldest retire slot is waiting to be marked as completed event=0xd6,umask=2  00     ex_no_retire.other execution Cycles where the thread does not retire any ops due to other reasons (retire breaks, traps, faults, etc.) event=0xd6,umask=8  00     ex_no_retire.thread_not_selected execution Cycles where the thread does not retire any ops as thread arbitration did not select the current thread event=0xd6,umask=0x10  00     ex_no_retire.load_not_complete execution Cycles where the thread does not retire any ops due to missing load completion event=0xd6,umask=0xa2  00     ex_ret_brn_cond_misp execution Retired conditional branch instructions that were mispredicted due to direction mismatch event=0x1c7  00     ex_ret_brn_uncond_ind_near_misp execution Retired unconditional indirect near branch instructions that were mispredicted event=0x1c8  00     ex_ret_brn_uncond execution Retired unconditional branch instructions event=0x1c9  00     ex_tagged_ibs_ops.tagged execution Execution IBS tagged ops event=0x1cf,umask=1  00     ex_tagged_ibs_ops.tagged_ret execution Execution IBS tagged ops that retired event=0x1cf,umask=2  00     ex_tagged_ibs_ops.rollovers execution Execution IBS periodic counter rollovers due to a previous tagged op not being IBS complete event=0x1cf,umask=4  00     ex_tagged_ibs_ops.filtered execution Execution IBS tagged ops that retired but were discarded due to IBS filtering event=0x1cf,umask=8  00     ex_tagged_ibs_ops.valid execution Execution IBS tagged ops that resulted in a valid sample and an IBS interrupt event=0x1cf,umask=0x10  00     ex_mprof_ibs_ops.tagged execution Memory Profiler IBS tagged ops event=0x2c0,umask=1  00     ex_mprof_ibs_ops.tagged_ret execution Memory Profiler IBS tagged ops that retired event=0x2c0,umask=2  00     ex_mprof_ibs_ops.rollovers execution Memory Profiler IBS periodic counter rollovers due to a previous tagged op not being IBS complete event=0x2c0,umask=4  00     ex_mprof_ibs_ops.filtered execution Memory Profiler IBS tagged ops that retired but were discarded due to IBS filtering event=0x2c0,umask=8  00     ex_mprof_ibs_ops.valid execution Memory Profiler IBS tagged ops that resulted in a valid sample and an IBS interrupt event=0x2c0,umask=0x10  00     fp_ret_x87_fp_ops.add_sub_ops floating point Retired x87 floating-point add and subtract uops event=2,umask=1  00     fp_ret_x87_fp_ops.mul_ops floating point Retired x87 floating-point multiply uops event=2,umask=2  00     fp_ret_x87_fp_ops.div_sqrt_ops floating point Retired x87 floating-point divide and square root uops event=2,umask=4  00     fp_ret_x87_fp_ops.all floating point Retired x87 floating-point uops of all types event=2,umask=7  00     fp_ret_sse_avx_ops.add_sub_flops floating point Retired SSE and AVX add and subtract FLOPs event=3,umask=1  00     fp_ret_sse_avx_ops.mult_flops floating point Retired SSE and AVX multiply FLOPs event=3,umask=2  00     fp_ret_sse_avx_ops.div_flops floating point Retired SSE and AVX divide and square root FLOPs event=3,umask=4  00     fp_ret_sse_avx_ops.mac_flops floating point Retired SSE and AVX multiply-accumulate FLOPs (each operation is counted as 2 FLOPs, bfloat operations are not included) event=3,umask=8  00     fp_ret_sse_avx_ops.bfloat16_flops floating point Retired SSE and AVX bfloat16 FLOPs event=3,umask=0x20  00     fp_ret_sse_avx_ops.scalar_single_flops floating point Retired SSE and AVX scalar single-precision (FP32) FLOPs event=3,umask=0x40  00     fp_ret_sse_avx_ops.packed_single_flops floating point Retired SSE and AVX packed single-precision (FP32) FLOPs event=3,umask=0x60  00     fp_ret_sse_avx_ops.scalar_double_flops floating point Retired SSE and AVX scalar double-precision (FP64) FLOPs event=3,umask=0x80  00     fp_ret_sse_avx_ops.packed_double_flops floating point Retired SSE and AVX packed double-precision (FP64) FLOPs event=3,umask=0xa0  00     fp_ret_sse_avx_ops.scalar_half_flops floating point Retired SSE and AVX scalar half-precision (FP16) FLOPs event=3,umask=0xa0  00     fp_ret_sse_avx_ops.packed_half_flops floating point Retired SSE and AVX packed half-precision (FP16) FLOPs event=3,umask=0xa0  00     fp_ret_sse_avx_ops.all floating point Retired SSE and AVX FLOPs of all types event=3,umask=0xf  00     fp_ops_ret_by_width.x87 floating point Retired x87 floating-point uops event=8,umask=1  00     fp_ops_ret_by_width.mmx floating point Retired MMX floating-point uops event=8,umask=2  00     fp_ops_ret_by_width.scalar floating point Retired scalar floating-point uops event=8,umask=4  00     fp_ops_ret_by_width.pack_128 floating point Retired packed 128-bit floating-point uops event=8,umask=8  00     fp_ops_ret_by_width.pack_256 floating point Retired packed 256-bit floating-point uops event=8,umask=0x10  00     fp_ops_ret_by_width.pack_512 floating point Retired packed 512-bit floating-point uops event=8,umask=0x20  00     fp_ops_ret_by_width.all floating point Retired floating-point uops of all widths event=8,umask=0x3f  00     fp_ops_ret_by_type.scalar_add floating point Retired scalar floating-point add uops event=0xa,umask=1  00     fp_ops_ret_by_type.scalar_sub floating point Retired scalar floating-point subtract uops event=0xa,umask=2  00     fp_ops_ret_by_type.scalar_mul floating point Retired scalar floating-point multiply uops event=0xa,umask=3  00     fp_ops_ret_by_type.scalar_mac floating point Retired scalar floating-point multiply-accumulate uops event=0xa,umask=4  00     fp_ops_ret_by_type.scalar_div floating point Retired scalar floating-point divide uops event=0xa,umask=5  00     fp_ops_ret_by_type.scalar_sqrt floating point Retired scalar floating-point square root uops event=0xa,umask=6  00     fp_ops_ret_by_type.scalar_cmp floating point Retired scalar floating-point compare uops event=0xa,umask=7  00     fp_ops_ret_by_type.scalar_cvt floating point Retired scalar floating-point convert uops event=0xa,umask=8  00     fp_ops_ret_by_type.scalar_blend floating point Retired scalar floating-point blend uops event=0xa,umask=9  00     fp_ops_ret_by_type.scalar_move floating point Retired scalar floating-point move uops event=0xa,umask=0xa  00     fp_ops_ret_by_type.scalar_shuffle floating point Retired scalar floating-point shuffle uops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xa,umask=0xb  00     fp_ops_ret_by_type.scalar_bfloat floating point Retired scalar floating-point bfloat uops event=0xa,umask=0xc  00     fp_ops_ret_by_type.scalar_logical floating point Retired scalar floating-point move uops event=0xa,umask=0xd  00     fp_ops_ret_by_type.scalar_other floating point Retired scalar floating-point uops of other types event=0xa,umask=0xe  00     fp_ops_ret_by_type.scalar_all floating point Retired scalar floating-point uops of all types event=0xa,umask=0xf  00     fp_ops_ret_by_type.vector_add floating point Retired vector floating-point add uops event=0xa,umask=0x10  00     fp_ops_ret_by_type.vector_sub floating point Retired vector floating-point subtract uops event=0xa,umask=0x20  00     fp_ops_ret_by_type.vector_mul floating point Retired vector floating-point multiply uops event=0xa,umask=0x30  00     fp_ops_ret_by_type.vector_mac floating point Retired vector floating-point multiply-accumulate uops event=0xa,umask=0x40  00     fp_ops_ret_by_type.vector_div floating point Retired vector floating-point divide uops event=0xa,umask=0x50  00     fp_ops_ret_by_type.vector_sqrt floating point Retired vector floating-point square root uops event=0xa,umask=0x60  00     fp_ops_ret_by_type.vector_cmp floating point Retired vector floating-point compare uops event=0xa,umask=0x70  00     fp_ops_ret_by_type.vector_cvt floating point Retired vector floating-point convert uops event=0xa,umask=0x80  00     fp_ops_ret_by_type.vector_blend floating point Retired vector floating-point blend uops event=0xa,umask=0x90  00     fp_ops_ret_by_type.vector_move floating point Retired vector floating-point move uops event=0xa,umask=0xa0  00     fp_ops_ret_by_type.vector_shuffle floating point Retired vector floating-point shuffle uops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xa,umask=0xb0  00     fp_ops_ret_by_type.vector_bfloat floating point Retired vector floating-point bfloat uops event=0xa,umask=0xc0  00     fp_ops_ret_by_type.vector_logical floating point Retired vector floating-point logical uops event=0xa,umask=0xd0  00     fp_ops_ret_by_type.vector_other floating point Retired vector floating-point uops of other types event=0xa,umask=0xe0  00     fp_ops_ret_by_type.vector_all floating point Retired vector floating-point uops of all types event=0xa,umask=0xf0  00     fp_ops_ret_by_type.all floating point Retired floating-point uops of all types event=0xa,umask=0xff  00     fp_sse_avx_ops_ret.mmx_add floating point Retired MMX integer add uops event=0xb,umask=1  00     fp_sse_avx_ops_ret.mmx_sub floating point Retired MMX integer subtract uops event=0xb,umask=2  00     fp_sse_avx_ops_ret.mmx_mul floating point Retired MMX integer multiply uops event=0xb,umask=3  00     fp_sse_avx_ops_ret.mmx_mac floating point Retired MMX integer multiply-accumulate uops event=0xb,umask=4  00     fp_sse_avx_ops_ret.mmx_aes floating point Retired MMX integer AES uops event=0xb,umask=5  00     fp_sse_avx_ops_ret.mmx_sha floating point Retired MMX integer SHA uops event=0xb,umask=6  00     fp_sse_avx_ops_ret.mmx_cmp floating point Retired MMX integer compare uops event=0xb,umask=7  00     fp_sse_avx_ops_ret.mmx_cvt floating point Retired MMX integer convert or pack uops event=0xb,umask=8  00     fp_sse_avx_ops_ret.mmx_shift floating point Retired MMX integer shift or rotate uops event=0xb,umask=9  00     fp_sse_avx_ops_ret.mmx_mov floating point Retired MMX integer move uops event=0xb,umask=0xa  00     fp_sse_avx_ops_ret.mmx_shuffle floating point Retired MMX integer shuffle uops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xb,umask=0xb  00     fp_sse_avx_ops_ret.mmx_vnni floating point Retired MMX integer VNNI uops event=0xb,umask=0xc  00     fp_sse_avx_ops_ret.mmx_logical floating point Retired MMX integer logical uops event=0xb,umask=0xd  00     fp_sse_avx_ops_ret.mmx_other floating point Retired MMX integer multiply uops of other types event=0xb,umask=0xe  00     fp_sse_avx_ops_ret.mmx_all floating point Retired MMX integer uops of all types event=0xb,umask=0xf  00     fp_sse_avx_ops_ret.sse_avx_add floating point Retired SSE and AVX integer add uops event=0xb,umask=0x10  00     fp_sse_avx_ops_ret.sse_avx_sub floating point Retired SSE and AVX integer subtract uops event=0xb,umask=0x20  00     fp_sse_avx_ops_ret.sse_avx_mul floating point Retired SSE and AVX integer multiply uops event=0xb,umask=0x30  00     fp_sse_avx_ops_ret.sse_avx_mac floating point Retired SSE and AVX integer multiply-accumulate uops event=0xb,umask=0x40  00     fp_sse_avx_ops_ret.sse_avx_aes floating point Retired SSE and AVX integer AES uops event=0xb,umask=0x50  00     fp_sse_avx_ops_ret.sse_avx_sha floating point Retired SSE and AVX integer SHA uops event=0xb,umask=0x60  00     fp_sse_avx_ops_ret.sse_avx_cmp floating point Retired SSE and AVX integer compare uops event=0xb,umask=0x70  00     fp_sse_avx_ops_ret.sse_avx_cvt floating point Retired SSE and AVX integer convert or pack uops event=0xb,umask=0x80  00     fp_sse_avx_ops_ret.sse_avx_shift floating point Retired SSE and AVX integer shift or rotate uops event=0xb,umask=0x90  00     fp_sse_avx_ops_ret.sse_avx_mov floating point Retired SSE and AVX integer move uops event=0xb,umask=0xa0  00     fp_sse_avx_ops_ret.sse_avx_shuffle floating point Retired SSE and AVX integer shuffle uops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xb,umask=0xb0  00     fp_sse_avx_ops_ret.sse_avx_vnni floating point Retired SSE and AVX integer VNNI uops event=0xb,umask=0xc0  00     fp_sse_avx_ops_ret.sse_avx_logical floating point Retired SSE and AVX integer logical uops event=0xb,umask=0xd0  00     fp_sse_avx_ops_ret.sse_avx_other floating point Retired SSE and AVX integer uops of other types event=0xb,umask=0xe0  00     fp_sse_avx_ops_ret.sse_avx_all floating point Retired SSE and AVX integer uops of all types event=0xb,umask=0xf0  00     fp_sse_avx_ops_ret.all floating point Retired MMX, SSE and AVX integer uops of all types event=0xb,umask=0xff  00     fp_pack_ops_ret.fp128_add floating point Retired 128-bit packed floating-point add uops event=0xc,umask=1  00     fp_pack_ops_ret.fp128_sub floating point Retired 128-bit packed floating-point subtract uops event=0xc,umask=2  00     fp_pack_ops_ret.fp128_mul floating point Retired 128-bit packed floating-point multiply uops event=0xc,umask=3  00     fp_pack_ops_ret.fp128_mac floating point Retired 128-bit packed floating-point multiply-accumulate uops event=0xc,umask=4  00     fp_pack_ops_ret.fp128_div floating point Retired 128-bit packed floating-point divide uops event=0xc,umask=5  00     fp_pack_ops_ret.fp128_sqrt floating point Retired 128-bit packed floating-point square root uops event=0xc,umask=6  00     fp_pack_ops_ret.fp128_cmp floating point Retired 128-bit packed floating-point compare uops event=0xc,umask=7  00     fp_pack_ops_ret.fp128_cvt floating point Retired 128-bit packed floating-point convert uops event=0xc,umask=8  00     fp_pack_ops_ret.fp128_blend floating point Retired 128-bit packed floating-point blend uops event=0xc,umask=9  00     fp_pack_ops_ret.fp128_mov floating point Retired 128-bit packed floating-point move uops event=0xc,umask=0xa  00     fp_pack_ops_ret.fp128_shuffle floating point Retired 128-bit packed floating-point shuffle uops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xc,umask=0xb  00     fp_pack_ops_ret.fp128_bfloat floating point Retired 128-bit packed floating-point bfloat uops event=0xc,umask=0xc  00     fp_pack_ops_ret.fp128_logical floating point Retired 128-bit packed floating-point logical uops event=0xc,umask=0xd  00     fp_pack_ops_ret.fp128_other floating point Retired 128-bit packed floating-point uops of other types event=0xc,umask=0xe  00     fp_pack_ops_ret.fp128_all floating point Retired 128-bit packed floating-point uops of all types event=0xc,umask=0xf  00     fp_pack_ops_ret.fp256_add floating point Retired 256-bit packed floating-point add uops event=0xc,umask=0x10  00     fp_pack_ops_ret.fp256_sub floating point Retired 256-bit packed floating-point subtract uops event=0xc,umask=0x20  00     fp_pack_ops_ret.fp256_mul floating point Retired 256-bit packed floating-point multiply uops event=0xc,umask=0x30  00     fp_pack_ops_ret.fp256_mac floating point Retired 256-bit packed floating-point multiply-accumulate uops event=0xc,umask=0x40  00     fp_pack_ops_ret.fp256_div floating point Retired 256-bit packed floating-point divide uops event=0xc,umask=0x50  00     fp_pack_ops_ret.fp256_sqrt floating point Retired 256-bit packed floating-point square root uops event=0xc,umask=0x60  00     fp_pack_ops_ret.fp256_cmp floating point Retired 256-bit packed floating-point compare uops event=0xc,umask=0x70  00     fp_pack_ops_ret.fp256_cvt floating point Retired 256-bit packed floating-point convert uops event=0xc,umask=0x80  00     fp_pack_ops_ret.fp256_blend floating point Retired 256-bit packed floating-point blend uops event=0xc,umask=0x90  00     fp_pack_ops_ret.fp256_mov floating point Retired 256-bit packed floating-point move uops event=0xc,umask=0xa0  00     fp_pack_ops_ret.fp256_shuffle floating point Retired 256-bit packed floating-point shuffle uops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xc,umask=0xb0  00     fp_pack_ops_ret.fp256_logical floating point Retired 256-bit packed floating-point logical uops event=0xc,umask=0xd0  00     fp_pack_ops_ret.fp256_other floating point Retired 256-bit packed floating-point uops of other types event=0xc,umask=0xe0  00     fp_pack_ops_ret.fp256_all floating point Retired 256-bit packed floating-point uops of all types event=0xc,umask=0xf0  00     fp_pack_ops_ret.fp_all floating point Retired packed floating-point uops of all types event=0xc,umask=0xff  00     fp_pack_int_ops_ret.int128_add floating point Retired 128-bit packed integer add uops event=0xd,umask=1  00     fp_pack_int_ops_ret.int128_sub floating point Retired 128-bit packed integer subtract uops event=0xd,umask=2  00     fp_pack_int_ops_ret.int128_mul floating point Retired 128-bit packed integer multiply uops event=0xd,umask=3  00     fp_pack_int_ops_ret.int128_mac floating point Retired 128-bit packed integer multiply-accumulate uops event=0xd,umask=4  00     fp_pack_int_ops_ret.int128_aes floating point Retired 128-bit packed integer AES uops event=0xd,umask=5  00     fp_pack_int_ops_ret.int128_sha floating point Retired 128-bit packed integer SHA uops event=0xd,umask=6  00     fp_pack_int_ops_ret.int128_cmp floating point Retired 128-bit packed integer compare uops event=0xd,umask=7  00     fp_pack_int_ops_ret.int128_cvt floating point Retired 128-bit packed integer convert or pack uops event=0xd,umask=8  00     fp_pack_int_ops_ret.int128_shift floating point Retired 128-bit packed integer shift or rotate uops event=0xd,umask=9  00     fp_pack_int_ops_ret.int128_mov floating point Retired 128-bit packed integer move uops event=0xd,umask=0xa  00     fp_pack_int_ops_ret.int128_shuffle floating point Retired 128-bit packed integer shuffle uops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xd,umask=0xb  00     fp_pack_int_ops_ret.int128_vnni floating point Retired 128-bit packed integer VNNI ops event=0xd,umask=0xc  00     fp_pack_int_ops_ret.int128_logical floating point Retired 128-bit packed integer logical uops event=0xd,umask=0xd  00     fp_pack_int_ops_ret.int128_other floating point Retired 128-bit packed integer uops of other types event=0xd,umask=0xe  00     fp_pack_int_ops_ret.int128_all floating point Retired 128-bit packed integer uops of all types event=0xd,umask=0xf  00     fp_pack_int_ops_ret.int256_add floating point Retired 256-bit packed integer add uops event=0xd,umask=0x10  00     fp_pack_int_ops_ret.int256_sub floating point Retired 256-bit packed integer subtract uops event=0xd,umask=0x20  00     fp_pack_int_ops_ret.int256_mul floating point Retired 256-bit packed integer multiply uops event=0xd,umask=0x30  00     fp_pack_int_ops_ret.int256_mac floating point Retired 256-bit packed integer multiply-accumulate uops event=0xd,umask=0x40  00     fp_pack_int_ops_ret.int256_cmp floating point Retired 256-bit packed integer compare uops event=0xd,umask=0x70  00     fp_pack_int_ops_ret.int256_shift floating point Retired 256-bit packed integer shift or rotate uops event=0xd,umask=0x90  00     fp_pack_int_ops_ret.int256_mov floating point Retired 256-bit packed integer move uops event=0xd,umask=0xa0  00     fp_pack_int_ops_ret.int256_shuffle floating point Retired 256-bit packed integer shuffle uops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xd,umask=0xb0  00     fp_pack_int_ops_ret.int256_vnni floating point Retired 256-bit packed integer VNNI uops event=0xd,umask=0xc0  00     fp_pack_int_ops_ret.int256_logical floating point Retired 256-bit packed integer logical uops event=0xd,umask=0xd0  00     fp_pack_int_ops_ret.int256_other floating point Retired 256-bit packed integer uops of other types event=0xd,umask=0xe0  00     fp_pack_int_ops_ret.int256_all floating point Retired 256-bit packed integer uops of all types event=0xd,umask=0xf0  00     fp_pack_int_ops_ret.int_all floating point Retired packed integer uops of all types event=0xd,umask=0xff  00     fp_pack_512b_ops_ret.fp512_add floating point Retired 512-bit packed floating-point add uops event=0xf,umask=1  00     fp_pack_512b_ops_ret.fp512_sub floating point Retired 512-bit packed floating-point subtract uops event=0xf,umask=2  00     fp_pack_512b_ops_ret.fp512_mul floating point Retired 512-bit packed floating-point multiply uops event=0xf,umask=3  00     fp_pack_512b_ops_ret.fp512_mac floating point Retired 512-bit packed floating-point multiply-accumulate uops event=0xf,umask=4  00     fp_pack_512b_ops_ret.fp512_div floating point Retired 512-bit packed floating-point divide uops event=0xf,umask=5  00     fp_pack_512b_ops_ret.fp512_sqrt floating point Retired 512-bit packed floating-point square root uops event=0xf,umask=6  00     fp_pack_512b_ops_ret.fp512_cmp floating point Retired 512-bit packed floating-point compare uops event=0xf,umask=7  00     fp_pack_512b_ops_ret.fp512_cvt floating point Retired 512-bit packed floating-point convert uops event=0xf,umask=8  00     fp_pack_512b_ops_ret.fp512_blend floating point Retired 512-bit packed floating-point blend uops event=0xf,umask=9  00     fp_pack_512b_ops_ret.fp512_mov floating point Retired 512-bit packed floating-point move uops event=0xf,umask=0xa  00     fp_pack_512b_ops_ret.fp512_shuffle floating point Retired 512-bit packed floating-point shuffle uops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xf,umask=0xb  00     fp_pack_512b_ops_ret.fp512_bfloat floating point Retired 512-bit packed floating-point bfloat uops event=0xf,umask=0xc  00     fp_pack_512b_ops_ret.fp512_logical floating point Retired 512-bit packed floating-point logical uops event=0xf,umask=0xd  00     fp_pack_512b_ops_ret.fp512_other floating point Retired 512-bit packed floating-point uops of other types event=0xf,umask=0xe  00     fp_pack_512b_ops_ret.fp512_all floating point Retired 512-bit packed floating-point uops of all types event=0xf,umask=0xf  00     fp_pack_512b_ops_ret.int512_add floating point Retired 512-bit packed integer add uops event=0xf,umask=0x10  00     fp_pack_512b_ops_ret.int512_sub floating point Retired 512-bit packed integer subtract uops event=0xf,umask=0x20  00     fp_pack_512b_ops_ret.int512_mul floating point Retired 512-bit packed integer multiply uops event=0xf,umask=0x30  00     fp_pack_512b_ops_ret.int512_mac floating point Retired 512-bit packed integer multiply-accumulate uops event=0xf,umask=0x40  00     fp_pack_512b_ops_ret.int512_aes floating point Retired 512-bit packed integer AES uops event=0xf,umask=0x50  00     fp_pack_512b_ops_ret.int512_sha floating point Retired 512-bit packed integer SHA uops event=0xf,umask=0x60  00     fp_pack_512b_ops_ret.int512_cmp floating point Retired 512-bit packed integer compare uops event=0xf,umask=0x70  00     fp_pack_512b_ops_ret.int512_cvt floating point Retired 512-bit packed integer convert or pack uops event=0xf,umask=0x80  00     fp_pack_512b_ops_ret.int512_shift floating point Retired 512-bit packed integer shift or rotate uops event=0xf,umask=0x90  00     fp_pack_512b_ops_ret.int512_mov floating point Retired 512-bit packed integer move uops event=0xf,umask=0xa0  00     fp_pack_512b_ops_ret.int512_shuffle floating point Retired 512-bit packed integer shuffle uops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xf,umask=0xb0  00     fp_pack_512b_ops_ret.int512_vnni floating point Retired 512-bit packed integer VNNI uops event=0xf,umask=0xc0  00     fp_pack_512b_ops_ret.int512_logical floating point Retired 512-bit packed integer logical uops event=0xf,umask=0xd0  00     fp_pack_512b_ops_ret.int512_other floating point Retired 512-bit packed integer uops of other types event=0xf,umask=0xe0  00     fp_pack_512b_ops_ret.int512_all floating point Retired 512-bit packed integer uops of all types event=0xf,umask=0xf0  00     fp_pack_512b_ops_ret.512b_all floating point Retired 512-bit packed uops of all types event=0xf,umask=0xff  00     fp_nsq_read_stalls.fp_prf floating point Cycles when reads of the NSQ and writes to the floating-point or SIMD schedulers are stalled due to insufficient free physical register file (FP-PRF) entries event=0x13,umask=0xe  00     fp_nsq_read_stalls.k_prf floating point Cycles when reads of the NSQ and writes to the floating-point or SIMD schedulers are stalled due to insufficient free mask physical register file (K-PRF) entries event=0x13,umask=0xe  00     fp_nsq_read_stalls.fp_sq floating point Cycles when reads of the NSQ and writes to the floating-point or SIMD schedulers are stalled due to insufficient free scheduler entries event=0x13,umask=0xe  00     fp_nsq_read_stalls.all floating point Cycles when reads of the NSQ and writes to the floating-point or SIMD schedulers are stalled due to any reason event=0x13,umask=0xe  00     ic_fetch_ibs_events.tagged inst cache Fetch IBS tagged fetches. Not all tagged fetches result in a valid sample and an IBS interrupt event=0x188,umask=2  00     ic_fetch_ibs_events.filtered inst cache Fetch IBS tagged fetches that were discarded due to IBS filtering event=0x188,umask=8  00     ic_fetch_ibs_events.valid inst cache Fetch IBS tagged fetches that resulted in a valid sample and an IBS interrupt event=0x188,umask=0x10  00     op_cache_hit_miss.hit inst cache Op cache fetch hits event=0x28f,umask=3  00     op_cache_hit_miss.miss inst cache Op cache fetch misses event=0x28f,umask=4  00     op_cache_hit_miss.all inst cache Op cache fetches of all types event=0x28f,umask=7  00     ic_fills_from_sys.local_l2 inst cache Instruction cache fills where data is returned from local L2 cache event=0x29c,umask=1  00     ic_fills_from_sys.local_ccx inst cache Instruction cache fills where data is returned from L3 cache or different L2 cache in the same CCX event=0x29c,umask=2  00     ic_fills_from_sys.local_all inst cache Instruction cache fills where data is returned from local L2 cache, L3 cache or different L2 cache in the same CCX event=0x29c,umask=3  00     ic_fills_from_sys.near_cache inst cache Instruction cache fills where data is returned from cache of another CCX in the same NUMA node event=0x29c,umask=4  00     ic_fills_from_sys.dram_io_near inst cache Instruction cache fills where data is returned from either DRAM or MMIO in the same NUMA node event=0x29c,umask=8  00     ic_fills_from_sys.far_cache inst cache Instruction cache fills where data is returned from cache of another CCX in a different NUMA node event=0x29c,umask=0x10  00     ic_fills_from_sys.remote_cache inst cache Instruction cache fills where data is returned from cache of another CCX in the same or a different NUMA node event=0x29c,umask=0x14  00     ic_fills_from_sys.dram_io_far inst cache Instruction cache fills where data is returned from either DRAM or MMIO in a different NUMA node event=0x29c,umask=0x40  00     ic_fills_from_sys.dram_io_all inst cache Instruction cache fills where data is returned from either DRAM or MMIO in the same or a different NUMA node event=0x29c,umask=0x48  00     ic_fills_from_sys.far_all inst cache Instruction cache fills where data is returned from either cache of another CCX, DRAM or MMIO in a different NUMA node event=0x29c,umask=0x50  00     ic_fills_from_sys.alt_mem inst cache Instruction cache fills where data is returned from extension memory (CXL) event=0x29c,umask=0x80  00     ic_fills_from_sys.all inst cache Instruction cache fills where data is returned from all types of sources event=0x29c,umask=0xdf  00     l2_request_g1.l2_hwpf l2 cache L2 cache requests from hardware prefetchers to prefetch directly into L2 (hit or miss) event=0x60,umask=2  00     l2_request_g1.prefetch_l2_cmd l2 cache L2 cache requests to prefetch directly into L2 event=0x60,umask=4  00     l2_request_g1.cacheable_ic_read l2 cache L2 cache requests for instruction cache reads event=0x60,umask=0x10  00     l2_request_g1.ls_rd_blk_c_s l2 cache L2 cache requests for data cache shared reads event=0x60,umask=0x20  00     l2_request_g1.rd_blk_x l2 cache L2 cache requests for data cache stores event=0x60,umask=0x40  00     l2_request_g1.rd_blk_l l2 cache L2 cache requests for data cache reads (includes hardware and software prefetches) event=0x60,umask=0x80  00     l2_request_g1.dc_all l2 cache L2 cache requests of common types from data cache (includes prefetches) event=0x60,umask=0xe0  00     l2_request_g1.no_pf_all l2 cache L2 cache requests of common types not including prefetches event=0x60,umask=0xf1  00     l2_request_g2.ls_rd_sized_nc l2 cache L2 cache requests for non-coherent, non-cacheable LS sized reads event=0x61,umask=0x20  00     l2_request_g2.ls_rd_sized l2 cache L2 cache requests for coherent, non-cacheable LS sized reads event=0x61,umask=0x40  00     l2_request_g2.all l2 cache L2 cache requests of all rare types event=0x61,umask=0x40  00     l2_cache_req_stat.ic_fill_miss l2 cache Core to L2 cache requests (not including L2 prefetch) from the instruction cache that result in L2 misses event=0x64,umask=1  00     l2_cache_req_stat.ic_fill_hit_s l2 cache Core to L2 cache requests (not including L2 prefetch) from the instruction cache that result in L2 hits on non-modifiable lines event=0x64,umask=2  00     l2_cache_req_stat.ic_fill_hit_x l2 cache Core to L2 cache requests (not including L2 prefetch) from the instruction cache that result in L2 hits on modifiable lines event=0x64,umask=4  00     l2_cache_req_stat.ic_hit_in_l2 l2 cache Core to L2 cache requests (not including L2 prefetch) from the instruction cache that result in L2 hits event=0x64,umask=6  00     l2_cache_req_stat.ic_access_in_l2 l2 cache Core to L2 cache requests (not including L2 prefetch) from the instruction cache that result in L2 accesses event=0x64,umask=7  00     l2_cache_req_stat.ls_rd_blk_c l2 cache Core to L2 cache requests (not including L2 prefetch) from the data cache that result in L2 misses event=0x64,umask=8  00     l2_cache_req_stat.ic_dc_miss_in_l2 l2 cache Core to L2 cache requests (not including L2 prefetch) from the data cache and the instruction cache that result in L2 misses event=0x64,umask=9  00     l2_cache_req_stat.ls_rd_blk_x l2 cache Core to L2 cache requests (not including L2 prefetch) that result in data cache stores or L2 state change hits event=0x64,umask=0x10  00     l2_cache_req_stat.ls_rd_blk_l_hit_s l2 cache Core to L2 cache requests (not including L2 prefetch) from the data cache that result in L2 hits on non-modifiable lines event=0x64,umask=0x20  00     l2_cache_req_stat.ls_rd_blk_l_hit_x l2 cache Core to L2 cache requests (not including L2 prefetch) from the data cache that result in L2 hits on modifiable lines event=0x64,umask=0x40  00     l2_cache_req_stat.ls_rd_blk_cs l2 cache Core to L2 cache requests (not including L2 prefetch) from the data cache that result in L2 read hits on shared lines event=0x64,umask=0x80  00     l2_cache_req_stat.dc_hit_in_l2 l2 cache Core to L2 cache requests (not including L2 prefetch) from the data cache that result in L2 hits event=0x64,umask=0xf0  00     l2_cache_req_stat.ic_dc_hit_in_l2 l2 cache Core to L2 cache requests (not including L2 prefetch) from the data cache and the instruction cache that result in L2 hits event=0x64,umask=0xf6  00     l2_cache_req_stat.dc_access_in_l2 l2 cache Core to L2 cache requests (not including L2 prefetch) from the data cache that result in L2 accesses event=0x64,umask=0xf8  00     l2_cache_req_stat.all l2 cache Core to L2 cache requests (not including L2 prefetch) from the data cache and the instruction cache that result in L2 accesses event=0x64,umask=0xff  00     l2_fill_rsp_src.local_ccx l2 cache L2 cache fills where data is returned from L3 cache or different L2 cache in the same CCX event=0x165,umask=2  00     l2_fill_rsp_src.near_cache l2 cache L2 cache fills where data is returned from cache of another CCX in the same NUMA node event=0x165,umask=4  00     l2_fill_rsp_src.dram_io_near l2 cache L2 cache fills where data is returned from either DRAM or MMIO in the same NUMA node event=0x165,umask=8  00     l2_fill_rsp_src.far_cache l2 cache L2 cache fills where data is returned from cache of another CCX in a different NUMA node event=0x165,umask=0x10  00     l2_fill_rsp_src.dram_io_far l2 cache L2 cache fills where data is returned from either DRAM or MMIO in a different NUMA node event=0x165,umask=0x40  00     l2_fill_rsp_src.dram_io_all l2 cache L2 cache fills where data is returned from either DRAM or MMIO in the same or a different NUMA node event=0x165,umask=0x48  00     l2_fill_rsp_src.far_all l2 cache L2 cache fills where data is returned from either cache of another CCX, DRAM or MMIO in a different NUMA node event=0x165,umask=0x50  00     l2_fill_rsp_src.alt_mem l2 cache L2 cache fills where data is returned from extension memory (CXL) event=0x165,umask=0x80  00     l2_fill_rsp_src.all l2 cache L2 cache fills where data is returned from all types of sources event=0x165,umask=0xde  00     l2_sys_bw.local_dram_fill l2 cache System bandwidth utilization for fill events that target the same NUMA node and return from DRAM in the same NUMA node event=0x175,umask=1  00     l2_sys_bw.remote_dram_fill l2 cache System bandwidth utilization for fill events that target a different NUMA node and return from DRAM in a different NUMA node event=0x175,umask=2  00     l2_sys_bw.nt_write l2 cache System bandwidth utilization for non-temporal write events that target all NUMA nodes event=0x175,umask=4  00     l2_sys_bw.local_scm_fill l2 cache System bandwidth utilization for fill events that target the same NUMA node and return from extension memory (CXL) in the same NUMA node event=0x175,umask=0x10  00     l2_sys_bw.remote_scm_fill l2 cache System bandwidth utilization for fill events that target a different NUMA node and return from extension memory (CXL) in a different NUMA node event=0x175,umask=0x20  00     l2_sys_bw.victim l2 cache System bandwidth utilization for cache victim events that target all NUMA nodes event=0x175,umask=0x40  00     l2_sys_bw.all l2 cache System bandwidth utilization for all types of events (total utilization) event=0x175,umask=0xff  00     l3_xi_sampled_latency.dram_near l3 cache Average sampled latency for L3 requests where data is returned from DRAM in the same NUMA node event=0xac,umask=1,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency.dram_far l3 cache Average sampled latency for L3 requests where data is returned from DRAM in a different NUMA node event=0xac,umask=2,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency.near_cache l3 cache Average sampled latency for L3 requests where data is returned from cache of another CCX in the same NUMA node event=0xac,umask=4,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency.far_cache l3 cache Average sampled latency for L3 requests where data is returned from cache of another CCX in a different NUMA node event=0xac,umask=8,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency.ext_near l3 cache Average sampled latency for L3 requests where data is returned from extension memory (CXL) in the same NUMA node event=0xac,umask=0x10,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency.ext_far l3 cache Average sampled latency for L3 requests where data is returned from extension memory (CXL) in a different NUMA node event=0xac,umask=0x20,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency.all l3 cache Average sampled latency for L3 requests where data is returned from all types of sources event=0xac,umask=0x3f,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency_requests.dram_near l3 cache Average sampled L3 requests where data is returned from DRAM in the same NUMA node event=0xad,umask=1,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency_requests.dram_far l3 cache Average sampled L3 requests where data is returned from DRAM in a different NUMA node event=0xad,umask=2,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency_requests.near_cache l3 cache Average sampled L3 requests where data is returned from cache of another CCX in the same NUMA node event=0xad,umask=4,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency_requests.far_cache l3 cache Average sampled L3 requests where data is returned from cache of another CCX in a different NUMA node event=0xad,umask=8,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency_requests.ext_near l3 cache Average sampled L3 requests where data is returned from extension memory (CXL) in the same NUMA node event=0xad,umask=0x10,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency_requests.ext_far l3 cache Average sampled L3 requests where data is returned from extension memory (CXL) in a different NUMA node event=0xad,umask=0x20,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     l3_xi_sampled_latency_requests.all l3 cache Average sampled L3 requests where data is returned from all types of sources event=0xad,umask=0x3f,enallcores=1,enallslices=1,sliceid=3,threadmask=3  00     ls_bad_status2.stli_other load store Store-to-load conflicts (loads unable to complete due to a non-forwardable conflict with an older store) event=0x24,umask=2  00     ls_locks.bus_lock load store Retired lock instructions which caused a bus lock (non-cacheable or cache-misaligned lock) event=0x25,umask=1  00     ls_locks.all load store Retired lock instructions of all types event=0x25,umask=0x1f  00     ls_dispatch.pure_ld load store Memory load operations dispatched to the load-store unit event=0x29,umask=1  00     ls_dispatch.pure_st load store Memory store operations dispatched to the load-store unit event=0x29,umask=2  00     ls_dispatch.ld_st load store Memory load-store operations (load from and store to the same memory address) dispatched to the load-store unit event=0x29,umask=4  00     ls_dispatch.all load store Memory operations dispatched to the load-store unit of all types event=0x29,umask=7  00     ls_smi_rx load store System Management Interrupts (SMIs) received event=0x2b  00     ls_st_commit_cancel.older_st_vis_dep load store Store commits cancelled due to an older store, that the thread was waiting on to become globally visible, was unable to become globally visible event=0x37,umask=1  00     ls_mab_alloc.ls load store Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for load-store allocations event=0x41,umask=7  00     ls_mab_alloc.hwpf load store Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for hardware prefetcher allocations event=0x41,umask=8  00     ls_mab_alloc.all load store Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for all types of allocations event=0x41,umask=0xf  00     ls_dmnd_fills_from_sys.local_l2 load store Demand data cache fills where data is returned from local L2 cache event=0x43,umask=1  00     ls_dmnd_fills_from_sys.local_ccx load store Demand data cache fills where data is returned from L3 cache or different L2 cache in the same CCX event=0x43,umask=2  00     ls_dmnd_fills_from_sys.local_all load store Demand data cache fills where data is returned from local L2 cache, L3 cache or different L2 cache in the same CCX event=0x43,umask=3  00     ls_dmnd_fills_from_sys.near_cache load store Demand data cache fills where data is returned from cache of another CCX in the same NUMA node event=0x43,umask=4  00     ls_dmnd_fills_from_sys.dram_io_near load store Demand data cache fills where data is returned from either DRAM or MMIO in the same NUMA node event=0x43,umask=8  00     ls_dmnd_fills_from_sys.far_cache load store Demand data cache fills where data is returned from cache of another CCX in a different NUMA node event=0x43,umask=0x10  00     ls_dmnd_fills_from_sys.remote_cache load store Demand data cache fills where data is returned from cache of another CCX in the same or a different NUMA node event=0x43,umask=0x14  00     ls_dmnd_fills_from_sys.dram_io_far load store Demand data cache fills where data is returned from either DRAM or MMIO in a different NUMA node event=0x43,umask=0x40  00     ls_dmnd_fills_from_sys.dram_io_all load store Demand data cache fills where data is returned from either DRAM or MMIO in the same or a different NUMA node event=0x43,umask=0x48  00     ls_dmnd_fills_from_sys.far_all load store Demand data cache fills where data is returned from either cache of another CCX, DRAM or MMIO in a different NUMA node event=0x43,umask=0x50  00     ls_dmnd_fills_from_sys.alt_mem load store Demand data cache fills where data is returned from extension memory (CXL) event=0x43,umask=0x80  00     ls_dmnd_fills_from_sys.all load store Demand data cache fills where data is returned from all types of sources event=0x43,umask=0xdf  00     ls_any_fills_from_sys.local_l2 load store Any data cache fills where data is returned from local L2 cache event=0x44,umask=1  00     ls_any_fills_from_sys.local_ccx load store Any data cache fills where data is returned from L3 cache or different L2 cache in the same CCX event=0x44,umask=2  00     ls_any_fills_from_sys.local_all load store Any data cache fills where data is returned from local L2 cache, L3 cache or different L2 cache in the same CCX event=0x44,umask=3  00     ls_any_fills_from_sys.near_cache load store Any data cache fills where data is returned from cache of another CCX in the same NUMA node event=0x44,umask=4  00     ls_any_fills_from_sys.dram_io_near load store Any data cache fills where data is returned from either DRAM or MMIO in the same NUMA node event=0x44,umask=8  00     ls_any_fills_from_sys.far_cache load store Any data cache fills where data is returned from cache of another CCX in a different NUMA node event=0x44,umask=0x10  00     ls_any_fills_from_sys.remote_cache load store Any data cache fills where data is returned from cache of another CCX in the same or a different NUMA node event=0x44,umask=0x14  00     ls_any_fills_from_sys.dram_io_far load store Any data cache fills where data is returned from either DRAM or MMIO in a different NUMA node event=0x44,umask=0x40  00     ls_any_fills_from_sys.dram_io_all load store Any data cache fills where data is returned from either DRAM or MMIO in the same or a different NUMA node event=0x44,umask=0x48  00     ls_any_fills_from_sys.far_all load store Any data cache fills where data is returned from either cache of another CCX, DRAM or MMIO when the address was in a different NUMA node event=0x44,umask=0x50  00     ls_any_fills_from_sys.alt_mem load store Any data cache fills where data is returned from extension memory (CXL) event=0x44,umask=0x80  00     ls_any_fills_from_sys.all load store Any data cache fills where data is returned from all types of data sources event=0x44,umask=0xff  00     ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit load store L1 DTLB misses with L2 DTLB hits for coalesced pages (16k pages created from four adjacent 4k pages) event=0x45,umask=2  00     ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss load store L1 DTLB misses with L2 DTLB misses (page-table walks requested) for 4k pages event=0x45,umask=0x10  00     ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss load store L1 DTLB misses with L2 DTLB misses (page-table walks requested) for coalesced pages (16k pages created from four adjacent 4k pages) event=0x45,umask=0x20  00     ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss load store L1 DTLB misses with L2 DTLB misses (page-table walks requested) for 2M pages event=0x45,umask=0x40  00     ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss load store L1 DTLB misses with L2 DTLB misses (page-table walks requested) for 1G pages event=0x45,umask=0x80  00     ls_l1_d_tlb_miss.l2_miss_all load store L1 DTLB misses with L2 DTLB misses (page-table walks requested) for all page sizes event=0x45,umask=0xf0  00     wcb_close.full_line_64b load store Events that caused a Write Combining Buffer (WCB) entry to close because all 64 bytes of the entry have been written to event=0x50,umask=1  00     ls_inef_sw_pref.dc_hit load store Software prefetches that did not fetch data outside of the processor core as the PREFETCH instruction saw a data cache hit event=0x52,umask=1  00     ls_inef_sw_pref.mab_hit load store Software prefetches that did not fetch data outside of the processor core as the PREFETCH instruction saw a match on an already allocated miss request (MAB) event=0x52,umask=2  00     ls_sw_pf_dc_fills.local_l2 load store Software prefetch data cache fills where data is returned from local L2 cache event=0x59,umask=1  00     ls_sw_pf_dc_fills.local_ccx load store Software prefetch data cache fills where data is returned from L3 cache or different L2 cache in the same CCX event=0x59,umask=2  00     ls_sw_pf_dc_fills.local_all load store Software prefetch data cache fills where data is returned from local L2 cache, L3 cache or different L2 cache in the same CCX event=0x59,umask=3  00     ls_sw_pf_dc_fills.near_cache load store Software prefetch data cache fills where data is returned from cache of another CCX in the same NUMA node event=0x59,umask=4  00     ls_sw_pf_dc_fills.dram_io_near load store Software prefetch data cache fills where data is returned from either DRAM or MMIO in the same NUMA node event=0x59,umask=8  00     ls_sw_pf_dc_fills.far_cache load store Software prefetch data cache fills where data is returned from cache of another CCX in a different NUMA node event=0x59,umask=0x10  00     ls_sw_pf_dc_fills.remote_cache load store Software prefetch data cache fills where data is returned from cache of another CCX in the same or a different NUMA node event=0x59,umask=0x14  00     ls_sw_pf_dc_fills.dram_io_far load store Software prefetch data cache fills where data is returned from either DRAM or MMIO in a different NUMA node event=0x59,umask=0x40  00     ls_sw_pf_dc_fills.dram_io_all load store Software prefetch data cache fills where data is returned from either DRAM or MMIO in the same or a different NUMA node event=0x59,umask=0x48  00     ls_sw_pf_dc_fills.far_all load store Software prefetch data cache fills where data is returned from either cache of another CCX, DRAM or MMIO in a different NUMA node event=0x59,umask=0x50  00     ls_sw_pf_dc_fills.alt_mem load store Software prefetch data cache fills where data is returned from extension memory (CXL) event=0x59,umask=0x80  00     ls_sw_pf_dc_fills.all load store Software prefetch data cache fills where data is returned from all types of data sources event=0x59,umask=0xdf  00     ls_hw_pf_dc_fills.local_l2 load store Hardware prefetch data cache fills where data is returned from local L2 cache event=0x5a,umask=1  00     ls_hw_pf_dc_fills.local_ccx load store Hardware prefetch data cache fills where data is returned from L3 cache or different L2 cache in the same CCX event=0x5a,umask=2  00     ls_hw_pf_dc_fills.local_all load store Hardware prefetch data cache fills where data is returned from local L2 cache, L3 cache or different L2 cache in the same CCX event=0x5a,umask=3  00     ls_hw_pf_dc_fills.near_cache load store Hardware prefetch data cache fills where data is returned from cache of another CCX in the same NUMA node event=0x5a,umask=4  00     ls_hw_pf_dc_fills.dram_io_near load store Hardware prefetch data cache fills where data is returned from either DRAM or MMIO in the same NUMA node event=0x5a,umask=8  00     ls_hw_pf_dc_fills.far_cache load store Hardware prefetch data cache fills where data is returned from cache of another CCX in a different NUMA node event=0x5a,umask=0x10  00     ls_hw_pf_dc_fills.remote_cache load store Hardware prefetch data cache fills where data is returned from cache of another CCX in the same or a different NUMA node event=0x5a,umask=0x14  00     ls_hw_pf_dc_fills.dram_io_far load store Hardware prefetch data cache fills where data is returned from either DRAM or MMIO in a different NUMA node event=0x5a,umask=0x40  00     ls_hw_pf_dc_fills.dram_io_all load store Hardware prefetch data cache fills where data is returned from either DRAM or MMIO in the same or a different NUMA node event=0x5a,umask=0x48  00     ls_hw_pf_dc_fills.far_all load store Hardware prefetch data cache fills where data is returned from either cache of another CCX, DRAM or MMIO in a different NUMA node event=0x5a,umask=0x50  00     ls_hw_pf_dc_fills.alt_mem load store Hardware prefetch data cache fills where data is returned from extension memory (CXL) event=0x5a,umask=0x80  00     ls_hw_pf_dc_fills.all load store Hardware prefetch data cache fills where data is returned from all types of data sources event=0x5a,umask=0xdf  00     ls_not_halted_cyc load store Core cycles where the thread is not in halted state event=0x76  00     ls_tlb_flush.all load store All TLB flushes event=0x78,umask=0xff  00     ls_not_halted_p0_cyc.p0_freq_cyc load store Reference cycles (P0 frequency) where the thread is not in halted state event=0x120,umask=1  00     umc_mem_clk memory controller  event=0  01    Memory clock (MEMCLK) cycles umc_act_cmd.all memory controller  event=5  01    ACTIVATE commands sent umc_act_cmd.rd memory controller  event=5,rdwrmask=1  01    ACTIVATE commands sent for reads umc_act_cmd.wr memory controller  event=5,rdwrmask=2  01    ACTIVATE commands sent for writes umc_pchg_cmd.all memory controller  event=6  01    PRECHARGE commands sent umc_pchg_cmd.rd memory controller  event=6,rdwrmask=1  01    PRECHARGE commands sent for reads umc_pchg_cmd.wr memory controller  event=6,rdwrmask=2  01    PRECHARGE commands sent for writes umc_cas_cmd.all memory controller  event=0xa  01    CAS commands sent umc_cas_cmd.rd memory controller  event=0xa,rdwrmask=1  01    CAS commands sent for reads umc_cas_cmd.wr memory controller  event=0xa,rdwrmask=2  01    CAS commands sent for writes umc_data_slot_clks.all memory controller  event=0x14  01    Clock cycles where the data bus is utilized umc_data_slot_clks.rd memory controller  event=0x14,rdwrmask=1  01    Clock cycles where the data bus is utilized for reads umc_data_slot_clks.wr memory controller  event=0x14,rdwrmask=2  01    Clock cycles where the data bus is utilized for writes core_reject_l2q.any cache Counts the number of request that were not accepted into the L2Q because the L2Q is FULL event=0x31,period=1000003  00    Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q.  It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link.  The L2Q may also reject transactions  from a core to insure fairness between cores, or to delay a cores dirty eviction when the address conflicts incoming external snoops.  (Note that L2 prefetcher requests that are dropped are not counted by this event.) dl1.dirty_eviction cache Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches event=0x51,period=200003,umask=1  00    Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches.  Does not count evictions or dirty writebacks caused by snoops.  Does not count a replacement unless a (dirty) line was written back uncore_cpu_lowpower l1d.l0_replacement cache Counts the number of cache lines replaced in L0 data cache event=0x51,period=100003,umask=1  00    Counts L0 data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace l1d.l1_replacement cache Cachelines replaced into the L1 d-cache. Successful replacements only (not blocked) and exclude WB-miss case event=0x51,period=1000003,umask=4  00    Counts cachelines replaced into the L1 d-cache l1d.replacement cache Cachelines replaced into the L0 and L1 d-cache. Successful replacements only (not blocked) and exclude WB-miss case event=0x51,period=1000003,umask=5  00    Counts cachelines replaced into the L0 and L1 d-cache l1d_miss.fb_full cache Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability event=0x49,period=1000003,umask=2  00    Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses l1d_miss.l2_stalls cache Number of cycles a demand request has waited due to L1D due to lack of L2 resources event=0x49,period=1000003,umask=4  00    Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses l1d_miss.load cache Number of demand requests that missed L1D cache event=0x49,period=1000003,umask=1  00    Count occurrences (rising-edge) of DCACHE_PENDING sub-event0. Impl. sends per-port binary inc-bit the occupancy increases* (at FB alloc or promotion) l1d_pending.load cache Number of L1D misses that are outstanding event=0x48,period=1000003,umask=1  00    Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type l1d_pending.load_cycles cache Cycles with L1D load Misses outstanding event=0x48,cmask=1,period=1000003,umask=1  00    Counts duration of L1D miss outstanding in cycles l2_lines_in.e cache Counts the number of cache lines filled into the L2 cache that are in Exclusive state event=0x25,period=1000003,umask=4  00     l2_lines_in.e cache Counts the number of cache lines filled into the L2 cache that are in Exclusive state event=0x25,period=1000003,umask=4  00    Counts the number of cache lines filled into the L2 cache that are in Exclusive state. Counts on a per core basis l2_lines_in.f cache Counts the number of cache lines filled into the L2 cache that are in Forward state event=0x25,period=1000003,umask=0x10  00     l2_lines_in.f cache Counts the number of cache lines filled into the L2 cache that are in Forward state event=0x25,period=1000003,umask=0x10  00    Counts the number of cache lines filled into the L2 cache that are in Forward state. Counts on a per core basis l2_lines_in.i cache Counts the number of cache lines filled into the L2 cache that are in Invalid state event=0x25,period=1000003,umask=1  00    Counts the number of cache lines filled into the L2 cache that are in Invalid state, does not count lines that go Invalid due to an eviction l2_lines_in.m cache Counts the number of cache lines filled into the L2 cache that are in Modified state event=0x25,period=1000003,umask=8  00     l2_lines_in.m cache Counts the number of cache lines filled into the L2 cache that are in Modified state event=0x25,period=1000003,umask=8  00    Counts the number of cache lines filled into the L2 cache that are in Modified state. Counts on a per core basis l2_lines_in.s cache Counts the number of cache lines filled into the L2 cache that are in Shared state event=0x25,period=1000003,umask=2  00     l2_lines_in.s cache Counts the number of cache lines filled into the L2 cache that are in Shared state event=0x25,period=1000003,umask=2  00    Counts the number of cache lines filled into the L2 cache that are in Shared state. Counts on a per core basis l2_lines_out.non_silent cache Counts the number of L2 cache lines that are evicted due to an L2 cache fill event=0x26,period=1000003,umask=2  00    Counts the number of L2 cache lines that are evicted due to an L2 cache fill. Increments on the core that brought the line in originally l2_lines_out.silent cache Counts the number of L2 cache lines that are silently dropped due to an L2 cache fill event=0x26,period=1000003,umask=1  00    Counts the number of L2 cache lines that are silently dropped due to an L2 cache fill.  Increments on the core that brought the line in originally l2_lines_out.useless_hwpf cache Counts the number of L2 cache lines that have been L2 hardware prefetched but not used by demand accesses event=0x26,period=1000003,umask=4  00    Counts the number of L2 cache lines that have been L2 hardware prefetched but not used by demand accesses.  Increments on the core that brought the line in originally l2_prefetches_throttled.dpt cache Counts the number of L2 prefetches initiated by either the L2 Stream or AMP that were  throttled due to Dynamic Prefetch Throttling. The throttle requestor/source could be from the uncore/SOC or the Dead Block Predictor.  Counts on a per core basis event=0x28,period=1000003,umask=1  00     l2_prefetches_throttled.dtp cache Counts the number of L2 prefetches initiated by the L2 Stream that were throttled due to Demand Throttle Prefetcher.  DTP Global Triggered with no Local Override. Counts on a per core basis event=0x28,period=1000003,umask=2  00     l2_prefetches_throttled.dtp_override cache Counts the number of L2 prefetches initiated by the L2 Stream and not throttled by DTP due to local override.  These prefetches may still be throttled due to another throttler mechanism besides DTP. Counts on a per core basis event=0x28,period=1000003,umask=4  00     l2_prefetches_throttled.xq_thresh cache Counts the number of L2 prefetches initiated by either the L2 Stream or AMP that were throttled due to exceeding the XQ threshold set by either XQ_THRESHOLD_DTP or XQ_THRESHOLD. Counts on a per core basis event=0x28,period=1000003,umask=8  00     l2_reject_xq.any cache Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition event=0x30,period=1000003  00    Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition which likely indicates back pressure from the IDI link.  The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 write-back victims) l2_request.all cache Counts the number of L2 Cache Accesses Counts the total number of L2 Cache Accesses - sum of hits, misses, rejects  front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only, per core event event=0x24,period=1000003,umask=7  00    Counts the number of L2 Cache Accesses Counts the total number of L2 Cache Accesses - sum of hits, misses, rejects  front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only l2_request.all cache All accesses to L2 cache [This event is alias to L2_RQSTS.REFERENCES, L2_RQSTS.ANY] event=0x24,period=200003,umask=0xff  00    Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.REFERENCES, L2_RQSTS.ANY] l2_request.hit cache Counts the number of L2 Cache Accesses that resulted in a Hit from a front door request only (does not include rejects or recycles), per core event event=0x24,period=1000003,umask=2  00     l2_request.hit cache Counts the number of L2 Cache Accesses that resulted in a Hit from a front door request only (does not include rejects or recycles), per core event event=0x24,period=200003,umask=2  00     l2_request.miss cache Counts the number of total L2 Cache Accesses that resulted in a Miss from a front door request only (does not include rejects or recycles), per core event event=0x24,period=1000003,umask=1  00     l2_request.miss cache Read requests with true-miss in L2 cache [This event is alias to L2_RQSTS.MISS] event=0x24,period=200003,umask=0x3f  00    Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.MISS] l2_request.miss cache Counts the number of total L2 Cache Accesses that resulted in a Miss from a front door request only (does not include rejects or recycles), per core event event=0x24,period=200003,umask=1  00     l2_request.rejects cache Counts the number of L2 Cache Accesses that miss the L2 and get BBL reject  short and long rejects (includes those counted in L2_reject_XQ.any), per core event event=0x24,period=1000003,umask=4  00     l2_request.rejects cache Counts the number of L2 Cache Accesses that miss the L2 and get BBL reject  short and long rejects, per core event event=0x24,period=200003,umask=4  00     l2_rqsts.any cache All accesses to L2 cache [This event is alias to L2_RQSTS.REFERENCES, L2_REQUEST.ALL] event=0x24,period=200003,umask=0xff  00    Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.REFERENCES, L2_REQUEST.ALL] l2_rqsts.code_rd_hit cache L2 cache hits when fetching instructions, code reads event=0x24,period=200003,umask=0x44  00    Counts L2 cache hits when fetching instructions, code reads l2_rqsts.demand_data_rd_hit cache Demand Data Read requests that hit L2 cache event=0x24,period=200003,umask=0x41  00    Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache l2_rqsts.miss cache Read requests with true-miss in L2 cache [This event is alias to L2_REQUEST.MISS] event=0x24,period=200003,umask=0x3f  00    Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.MISS] l2_rqsts.references cache All accesses to L2 cache [This event is alias to L2_REQUEST.ALL,L2_RQSTS.ANY] event=0x24,period=200003,umask=0xff  00    Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.ALL,L2_RQSTS.ANY] l2_rqsts.rfo_hit cache RFO requests that hit L2 cache event=0x24,period=200003,umask=0x42  00    Counts the RFO (Read-for-Ownership) requests that hit L2 cache llc_prefetches_throttled.dpt cache Counts the number of LLC prefetches that were  throttled due to Dynamic Prefetch Throttling.  The throttle requestor/source could be from the uncore/SOC or the Dead Block Predictor. Counts on a per core basis event=0x29,period=1000003,umask=1  00     llc_prefetches_throttled.dtp cache Counts the number of LLC prefetches throttled due to Demand Throttle Prefetcher.  DTP Global Triggered with no Local Override. Counts on a per core basis event=0x29,period=1000003,umask=2  00     llc_prefetches_throttled.dtp_override cache Counts the number of LLC prefetches not throttled by DTP due to local override.  These prefetches may still be throttled due to another throttler mechanism. Counts on a per core basis event=0x29,period=1000003,umask=4  00     llc_prefetches_throttled.hit_rate cache Counts the number of LLC prefetches throttled due to LLC hit rate in <insert knob name here>. Counts on a per core basis event=0x29,period=1000003,umask=0x10  00     llc_prefetches_throttled.xq_thresh cache Counts the number of LLC prefetches throttled due to exceeding the XQ threshold set by either XQ_THRESHOLD_DTP or LLC_XQ_THRESHOLD. Counts on a per core basis event=0x29,period=1000003,umask=8  00     lock_cycles.cache_lock_duration cache Cycles when L1D is locked event=0x42,period=2000003,umask=2  00    This event counts the number of cycles when the L1D is locked mem_bound_stalls_ifetch.all cache Counts the number of cycles the core is stalled due to an instruction cache or TLB miss event=0x35,period=1000003,umask=0x7f  00     mem_bound_stalls_ifetch.l2_hit cache Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache event=0x35,period=1000003,umask=1  00    Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.  Includes L2 Hit resulting from and L1D eviction of another core in the same module which is longer latency than a typical L2 hit mem_bound_stalls_ifetch.l2_hit cache Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache event=0x35,period=1000003,umask=1  00    Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache mem_bound_stalls_ifetch.l2_miss cache Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which missed in the L2 cache event=0x35,period=1000003,umask=0x7e  00     mem_bound_stalls_ifetch.llc_hit cache Counts the number of unhalted cycles when the core is stalled due to an icache or itlb miss which hit in the LLC event=0x35,period=1000003,umask=6  00     mem_bound_stalls_load.all cache Counts the number of unhalted cycles when the core is stalled due to an L1 demand load miss event=0x34,period=1000003,umask=0x7f  00     mem_bound_stalls_load.l2_hit cache Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache event=0x34,period=1000003,umask=1  00    Counts the number of cycles a core is stalled due to a demand load which hit in the L2 cache.  Includes L2 Hit resulting from and L1D eviction of another core in the same module which is longer latency than a typical L2 hit mem_bound_stalls_load.l2_hit cache Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache event=0x34,period=1000003,umask=1  00    Counts the number of cycles a core is stalled due to a demand load which hit in the L2 cache mem_bound_stalls_load.l2_miss cache Counts the number of cycles the core is stalled due to a demand load which missed in the L2 cache event=0x34,period=1000003,umask=0x7e  00     mem_bound_stalls_load.llc_hit cache Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC event=0x34,period=1000003,umask=6  00     mem_bound_stalls_load.llc_miss cache Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the local caches event=0x34,period=1000003,umask=0x78  00     mem_bound_stalls_load.llc_miss cache Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the local caches. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss event=0x34,period=1000003,umask=0x78  00     mem_bound_stalls_load.sbfull cache Counts the number of unhalted cycles when the core is stalled to a store buffer full condition event=0x34,period=1000003,umask=0x80  00     mem_inst_retired.all_loads cache Counts all retired load instructions  Supports address when precise event=0xd0,period=1000003,umask=0x81  00    Counts Instructions with at least one architecturally visible load retired. Available PDIST counters: 0,1  Supports address when precise mem_inst_retired.all_stores cache Retired store instructions  Supports address when precise event=0xd0,period=1000003,umask=0x82  00    Counts all retired store instructions. Available PDIST counters: 0,1  Supports address when precise mem_inst_retired.all_swpf cache Retired software prefetch instructions event=0xd0,period=1000003,umask=0x84  00    Counts all retired software prefetch instructions. Available PDIST counters: 0,1 mem_inst_retired.any cache All retired memory instructions  Supports address when precise event=0xd0,period=1000003,umask=0x87  00    Counts all retired memory instructions - loads and stores. Available PDIST counters: 0,1  Supports address when precise mem_inst_retired.lock_loads cache Retired load instructions with locked access  Supports address when precise event=0xd0,period=100007,umask=0x21  00    Counts retired load instructions with locked access. Available PDIST counters: 0,1  Supports address when precise mem_inst_retired.split_loads cache Retired load instructions that split across a cacheline boundary  Supports address when precise event=0xd0,period=100003,umask=0x41  00    Counts retired load instructions that split across a cacheline boundary. Available PDIST counters: 0,1  Supports address when precise mem_inst_retired.split_stores cache Retired store instructions that split across a cacheline boundary  Supports address when precise event=0xd0,period=100003,umask=0x42  00    Counts retired store instructions that split across a cacheline boundary. Available PDIST counters: 0,1  Supports address when precise mem_inst_retired.stlb_hit_any cache Retired instructions that hit the STLB  Supports address when precise event=0xd0,period=100003,umask=0xf  00    Number of retired instructions with a clean hit in the 2nd-level TLB (STLB). Available PDIST counters: 0,1  Supports address when precise mem_inst_retired.stlb_hit_loads cache Retired load instructions that hit the STLB  Supports address when precise event=0xd0,period=100003,umask=9  00    Number of retired load instructions with a clean hit in the 2nd-level TLB (STLB). Available PDIST counters: 0,1  Supports address when precise mem_inst_retired.stlb_hit_stores cache Retired store instructions that hit the STLB  Supports address when precise event=0xd0,period=100003,umask=0xa  00    Number of retired store instructions that hit in the 2nd-level TLB (STLB). Available PDIST counters: 0,1  Supports address when precise mem_inst_retired.stlb_hit_swpf cache Retired SWPF instructions that hit the STLB event=0xd0,period=1000003,umask=0xc  00    Number of retired SWPF instructions that hit in the 2nd-level TLB (STLB). Available PDIST counters: 0,1 mem_inst_retired.stlb_miss_any cache Retired instructions that miss the STLB  Supports address when precise event=0xd0,period=100003,umask=0x17  00    Retired instructions that miss the STLB. Available PDIST counters: 0,1  Supports address when precise mem_inst_retired.stlb_miss_loads cache Retired load instructions that miss the STLB  Supports address when precise event=0xd0,period=100003,umask=0x11  00    Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB). Available PDIST counters: 0,1  Supports address when precise mem_inst_retired.stlb_miss_stores cache Retired store instructions that miss the STLB  Supports address when precise event=0xd0,period=100003,umask=0x12  00    Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB). Available PDIST counters: 0,1  Supports address when precise mem_inst_retired.stlb_miss_swpf cache Retired SWPF instructions that miss the STLB event=0xd0,period=1000003,umask=0x14  00    Number of retired SWPF instructions that (start a) miss in the 2nd-level TLB (STLB). Available PDIST counters: 0,1 mem_load_l3_hit_retired.xsnp_fwd cache Retired load instructions whose data sources were a cross-core Snoop hits and forwards data from an in on-package core cache (induced by NI$)  Supports address when precise event=0xd2,period=20011,umask=0x10  00    Counts retired load instructions whose data sources were a cross-core Snoop hits and forwards data from an in on-package core cache (induced by NI$) Available PDIST counters: 0,1  Supports address when precise mem_load_l3_hit_retired.xsnp_hitm cache Retired load instructions whose data sources were HitM responses from shared L3, Hit-with-FWD is normally excluded  Supports address when precise event=0xd2,period=20011,umask=4  00    Counts retired load instructions whose data sources were HitM responses from shared L3, Hit-with-FWD is normally excluded. Available PDIST counters: 0,1  Supports address when precise mem_load_l3_hit_retired.xsnp_miss cache Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache  Supports address when precise event=0xd2,period=20011,umask=1  00    Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache. Available PDIST counters: 0,1  Supports address when precise mem_load_l3_hit_retired.xsnp_no_fwd cache Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache  Supports address when precise event=0xd2,period=20011,umask=2  00    Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache. Available PDIST counters: 0,1  Supports address when precise mem_load_misc_retired.uc cache Retired instructions with at least 1 uncacheable load or lock  Supports address when precise event=0xd4,period=100007,umask=4  00    Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock). Available PDIST counters: 0,1  Supports address when precise mem_load_retired.fb_hit cache Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1  Supports address when precise event=0xd1,period=100007,umask=0x40  00    Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready. Available PDIST counters: 0,1  Supports address when precise mem_load_retired.l1_hit cache Retired load instructions with L1 cache hits as data sources  Supports address when precise event=0xd1,period=1000003,umask=0x101  00    Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source. Available PDIST counters: 0,1  Supports address when precise mem_load_retired.l1_hit_l0 cache Counts retired load instructions with at least one uop that hit in the Level 0 of the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source  Supports address when precise event=0xd1,period=1000003,umask=1  00    Counts retired load instructions with at least one uop that hit in the Level 0 of the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source. Available PDIST counters: 0,1  Supports address when precise mem_load_retired.l1_hit_l1 cache Counts retired load instructions with at least one uop that hit in the Level 1 of the L1 data cache event=0xd1,period=1000003  00    Counts retired load instructions with at least one uop that hit in the Level 1 of the L1 data cache. Available PDIST counters: 0,1 mem_load_retired.l1_miss cache Retired load instructions missed L1 cache as data sources  Supports address when precise event=0xd1,period=200003,umask=8  00    Counts retired load instructions with at least one uop that missed in the L1 cache. Available PDIST counters: 0,1  Supports address when precise mem_load_retired.l2_hit cache Retired load instructions with L2 cache hits as data sources  Supports address when precise event=0xd1,period=200003,umask=2  00    Counts retired load instructions with L2 cache hits as data sources. Available PDIST counters: 0,1  Supports address when precise mem_load_retired.l2_miss cache Retired load instructions missed L2 cache as data sources  Supports address when precise event=0xd1,period=100021,umask=0x10  00    Counts retired load instructions missed L2 cache as data sources. Available PDIST counters: 0,1  Supports address when precise mem_load_retired.l3_hit cache Retired load instructions with L3 cache hits as data sources  Supports address when precise event=0xd1,period=100021,umask=4  00    Counts retired load instructions with at least one uop that hit in the L3 cache. Available PDIST counters: 0,1  Supports address when precise mem_load_retired.l3_miss cache Retired load instructions missed L3 cache as data sources  Supports address when precise event=0xd1,period=50021,umask=0x20  00    Counts retired load instructions with at least one uop that missed in the L3 cache. Available PDIST counters: 0,1  Supports address when precise mem_load_uops_misc_retired.local_dram cache Counts the number of load ops retired that miss the L3 cache and hit in DRAM event=0xd4,period=1000003,umask=2  00     mem_load_uops_retired.l1_hit cache Counts the number of load ops retired that hit the L1 data cache event=0xd1,period=1000003,umask=1  00     mem_load_uops_retired.l1_hit cache Counts the number of load ops retired that hit the L1 data cache event=0xd1,period=200003,umask=1  00     mem_load_uops_retired.l1_miss cache Counts the number of load ops retired that miss in the L1 data cache event=0xd1,period=1000003,umask=0x40  00     mem_load_uops_retired.l1_miss cache Counts the number of load ops retired that miss in the L1 data cache event=0xd1,period=200003,umask=0x40  00     mem_load_uops_retired.l2_hit cache Counts the number of load ops retired that hit in the L2 cache event=0xd1,period=1000003,umask=2  00    Counts the number of load ops retired that hit in the L2 cache.  Includes L2 Hit resulting from and L1D eviction of another core in the same module which is longer latency than a typical L2 hit mem_load_uops_retired.l2_hit cache Counts the number of load ops retired that hit in the L2 cache event=0xd1,period=200003,umask=2  00     mem_load_uops_retired.l2_miss cache Counts the number of load ops retired that miss in the L2 cache event=0xd1,period=1000003,umask=0x80  00     mem_load_uops_retired.l2_miss cache Counts the number of load ops retired that miss in the L2 cache event=0xd1,period=200003,umask=0x80  00     mem_load_uops_retired.l3_hit cache Counts the number of load ops retired that hit in the L3 cache event=0xd1,period=1000003,umask=0x1c  00     mem_load_uops_retired.l3_hit cache Counts the number of load ops retired that hit in the L3 cache event=0xd1,period=200003,umask=0x1c  00     mem_load_uops_retired.wcb_hit cache Counts the number of loads that hit in a write combining buffer (WCB), excluding the first load that caused the WCB to allocate event=0xd1,period=1000003,umask=0x20  00     mem_load_uops_retired.wcb_hit cache Counts the number of loads that hit in a write combining buffer (WCB), excluding the first load that caused the WCB to allocate event=0xd1,period=200003,umask=0x20  00     mem_scheduler_block.all cache Counts the number of cycles that uops are blocked for any of the following reasons:  load buffer, store buffer or RSV full event=4,period=1000003,umask=7  00     mem_scheduler_block.ld_buf cache Counts the number of cycles that uops are blocked due to load buffer full event=4,period=1000003,umask=2  00     mem_scheduler_block.rsv cache Counts the number of cycles that uops are blocked due to RSV full event=4,period=1000003,umask=4  00     mem_scheduler_block.st_buf cache Counts the number of cycles that uops are blocked due to store buffer full event=4,period=1000003,umask=1  00     mem_uops_retired.all cache Counts the number of memory uops retired.  A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST)  Supports address when precise event=0xd0,period=200003,umask=0x83  00     mem_uops_retired.all_loads cache Counts the number of load uops retired  Supports address when precise event=0xd0,period=200003,umask=0x81  00     mem_uops_retired.all_loads cache Counts the number of load ops retired  Supports address when precise event=0xd0,period=200003,umask=0x81  00     mem_uops_retired.all_stores cache Counts the number of store uops retired  Supports address when precise event=0xd0,period=200003,umask=0x82  00     mem_uops_retired.all_stores cache Counts the number of store ops retired  Supports address when precise event=0xd0,period=200003,umask=0x82  00     mem_uops_retired.load_latency_gt_1024 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled  Supports address when precise event=0xd0,period=1000003,umask=5,ldlat=0x400  00     mem_uops_retired.load_latency_gt_128 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled  Supports address when precise event=0xd0,period=200003,umask=5,ldlat=0x80  00     mem_uops_retired.load_latency_gt_128 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled  Supports address when precise event=0xd0,period=1000003,umask=5,ldlat=0x80  00     mem_uops_retired.load_latency_gt_16 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled  Supports address when precise event=0xd0,period=200003,umask=5,ldlat=0x10  00     mem_uops_retired.load_latency_gt_16 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled  Supports address when precise event=0xd0,period=1000003,umask=5,ldlat=0x10  00     mem_uops_retired.load_latency_gt_2048 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled  Supports address when precise event=0xd0,period=1000003,umask=5,ldlat=0x800  00     mem_uops_retired.load_latency_gt_256 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled  Supports address when precise event=0xd0,period=200003,umask=5,ldlat=0x100  00     mem_uops_retired.load_latency_gt_256 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled  Supports address when precise event=0xd0,period=1000003,umask=5,ldlat=0x100  00     mem_uops_retired.load_latency_gt_32 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled  Supports address when precise event=0xd0,period=200003,umask=5,ldlat=0x20  00     mem_uops_retired.load_latency_gt_32 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled  Supports address when precise event=0xd0,period=1000003,umask=5,ldlat=0x20  00     mem_uops_retired.load_latency_gt_4 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled  Supports address when precise event=0xd0,period=200003,umask=5,ldlat=0x4  00     mem_uops_retired.load_latency_gt_4 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled  Supports address when precise event=0xd0,period=1000003,umask=5,ldlat=0x4  00     mem_uops_retired.load_latency_gt_512 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled  Supports address when precise event=0xd0,period=200003,umask=5,ldlat=0x200  00     mem_uops_retired.load_latency_gt_512 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled  Supports address when precise event=0xd0,period=1000003,umask=5,ldlat=0x200  00     mem_uops_retired.load_latency_gt_64 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled  Supports address when precise event=0xd0,period=200003,umask=5,ldlat=0x40  00     mem_uops_retired.load_latency_gt_64 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled  Supports address when precise event=0xd0,period=1000003,umask=5,ldlat=0x40  00     mem_uops_retired.load_latency_gt_8 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled  Supports address when precise event=0xd0,period=200003,umask=5,ldlat=0x8  00     mem_uops_retired.load_latency_gt_8 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled  Supports address when precise event=0xd0,period=1000003,umask=5,ldlat=0x8  00     mem_uops_retired.mrn_loads cache Counts the number of memory renamed load uops retired  Supports address when precise event=0xd0,period=200003,umask=9  00     mem_uops_retired.mrn_stores cache Counts the number of memory renamed store uops retired  Supports address when precise event=0xd0,period=200003,umask=0xa  00     mem_uops_retired.split cache Counts the number of memory uops retired that were splits  Supports address when precise event=0xd0,period=200003,umask=0x43  00     mem_uops_retired.split_stores cache Counts the number of retired split store uops  Supports address when precise event=0xd0,period=200003,umask=0x42  00     mem_uops_retired.stlb_miss cache Counts the number of memory uops retired that missed in the second level TLB  Supports address when precise event=0xd0,period=200003,umask=0x13  00     mem_uops_retired.stlb_miss_loads cache Counts the number of load ops retired that filled the STLB - includes those in DTLB_LOAD_MISSES submasks  Supports address when precise event=0xd0,period=200003,umask=0x11  00     mem_uops_retired.stlb_miss_loads cache Counts the number of load uops retired that miss in the second Level TLB  Supports address when precise event=0xd0,period=200003,umask=0x11  00     mem_uops_retired.stlb_miss_stores cache Counts the number of store ops retired (store STLB miss)  Supports address when precise event=0xd0,period=200003,umask=0x12  00     mem_uops_retired.stlb_miss_stores cache Counts the number of store uops retired that miss in the second level TLB  Supports address when precise event=0xd0,period=200003,umask=0x12  00     mem_uops_retired.store_latency cache Counts the number of  stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES  Supports address when precise event=0xd0,period=200003,umask=6  00     mem_uops_retired.store_latency cache Counts the number of  stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES  Supports address when precise event=0xd0,period=1000003,umask=6  00     mem_uop_retired.any cache Retired memory uops for any access event=0xe5,period=1000003,umask=0xf  00    Number of retired micro-operations (uops) for load or store memory accesses ocr.corewb_m.l3_hit cache Counts writebacks of modified cachelines that hit in the L3 or were snooped from another core's caches event=0x2a,period=100003,umask=1,offcore_rsp=0x7E001E00008  00    Counts writebacks of modified cachelines that hit in the L3 or were snooped from another core's caches. Available PDIST counters: 0 ocr.corewb_nonm.l3_hit cache Counts writebacks of non-modified cachelines that hit in the L3 or were snooped from another core's caches event=0x2a,period=100003,umask=1,offcore_rsp=0x7E001E01000  00    Counts writebacks of non-modified cachelines that hit in the L3 or were snooped from another core's caches. Available PDIST counters: 0 ocr.demand_data_rd.l3_hit.snoop_hitm cache Counts demand data reads that were supplied by the L3 cache where a snoop hit in another cores caches, data forwarding is required as the data is modified event=0x2a,period=100003,umask=1,offcore_rsp=0x40001E00001  00    Counts demand data reads that were supplied by the L3 cache where a snoop hit in another cores caches, data forwarding is required as the data is modified. Available PDIST counters: 0 ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd cache Counts demand data reads that were supplied by the L3 cache where a snoop hit in another cores caches which forwarded the unmodified data to the requesting core event=0x2a,period=100003,umask=1,offcore_rsp=0x20001E00001  00    Counts demand data reads that were supplied by the L3 cache where a snoop hit in another cores caches which forwarded the unmodified data to the requesting core. Available PDIST counters: 0 ocr.demand_rfo.l3_hit.snoop_hitm cache Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop hit in another cores caches, data forwarding is required as the data is modified event=0x2a,period=100003,umask=1,offcore_rsp=0x40001E00002  00    Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop hit in another cores caches, data forwarding is required as the data is modified. Available PDIST counters: 0 ocr.reads_to_core.l3_hit cache Counts all data read, code read, RFO and ITOM requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches event=0x2a,period=100003,umask=1,offcore_rsp=0x7E001E04477  00    Counts all data read, code read, RFO and ITOM requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches. Available PDIST counters: 0 offcore_requests.all_requests cache Any memory transaction that reached the SQ event=0x21,period=100003,umask=0x80  00    Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc. offcore_requests.demand_code_rd cache Cacheable and Non-Cacheable code read requests event=0x21,period=100003,umask=2  00    Counts both cacheable and Non-Cacheable code read requests offcore_requests_outstanding.cycles_with_data_rd cache Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore event=0x20,cmask=1,period=1000003,umask=8  00    Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.data_rd cache Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore event=0x20,period=1000003,umask=8  00    Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.demand_rfo cache Store Read transactions pending for off-core. Highly correlated event=0x20,period=1000003,umask=4  00    Counts the number of off-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO transaction is considered to be in the Off-core outstanding state between L2 cache miss and transaction completion topdown_fe_bound.icache cache Counts the number of issue slots every cycle that were not delivered by the frontend due to an icache miss event=0x71,period=1000003,umask=0x20  00     arith.fpdiv_active floating point Counts the number of cycles when any of the floating point dividers are active event=0xcd,cmask=1,period=1000003,umask=2  00     arith.fpdiv_active floating point Cycles when floating-point divide unit is busy executing divide or square root operations event=0xb0,cmask=1,period=1000003,umask=1  00    Counts cycles when divide unit is busy executing divide or square root operations. Accounts for floating-point operations only arith.fpdiv_occupancy floating point Counts the number of active floating point dividers per cycle in the loop stage event=0xcd,period=1000003,umask=2  00     fp_arith_dispatched.v0 floating point Number of FP-arith-uops dispatched on 1st VEC port (port 0). FP-arith-uops are of type ADD* / SUB* / MUL / FMA* / DPP event=0xb3,period=2000003,umask=1  00     fp_arith_dispatched.v1 floating point Number of FP-arith-uops dispatched on 2nd VEC port (port 1) event=0xb3,period=2000003,umask=2  00     fp_arith_dispatched.v2 floating point Number of FP-arith-uops dispatched on 3rd VEC port (port 5) event=0xb3,period=2000003,umask=4  00     fp_arith_dispatched.v3 floating point Number of FP-arith-uops dispatched on 4th VEC port event=0xb3,period=2000003,umask=8  00     fp_arith_inst_retired.128b_packed_double floating point This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.128B_PACKED_DOUBLE event=0xc7,period=100003,umask=4  10     fp_arith_inst_retired.128b_packed_single floating point This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.128B_PACKED_SINGLE event=0xc7,period=100003,umask=8  10     fp_arith_inst_retired.256b_packed_double floating point This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.256B_PACKED_DOUBLE event=0xc7,period=100003,umask=0x10  10     fp_arith_inst_retired.256b_packed_single floating point This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.256B_PACKED_SINGLE event=0xc7,period=100003,umask=0x20  10     fp_arith_inst_retired.4_flops floating point This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.4_FLOPS event=0xc7,period=100003,umask=0x18  10     fp_arith_inst_retired.scalar floating point This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.SCALAR event=0xc7,period=1000003,umask=3  10     fp_arith_inst_retired.scalar_double floating point This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.SCALAR_DOUBLE event=0xc7,period=100003,umask=1  10     fp_arith_inst_retired.scalar_single floating point This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.SCALAR_SINGLE event=0xc7,period=100003,umask=2  10     fp_arith_inst_retired.vector floating point This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.VECTOR event=0xc7,period=1000003,umask=0x3c  10     fp_arith_inst_retired.vector_128b floating point FP_ARITH_INST_RETIRED.VECTOR_128B [This event is alias to FP_ARITH_OPS_RETIRED.VECTOR_128B] event=0xc7,period=100003,umask=0xc  00     fp_arith_inst_retired.vector_256b floating point FP_ARITH_INST_RETIRED.VECTOR_256B [This event is alias to FP_ARITH_OPS_RETIRED.VECTOR_256B] event=0xc7,period=100003,umask=0x30  00     fp_arith_ops_retired.128b_packed_double floating point Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=4  00    Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_ops_retired.128b_packed_single floating point Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=8  00    Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_ops_retired.256b_packed_double floating point Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=0x10  00    Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_ops_retired.256b_packed_single floating point Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=0x20  00    Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_ops_retired.4_flops floating point Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below.  Each count represents 2 or/and 4 computation operations, 1 for each element.  Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=0x18  00    Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision  floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 or/and 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_ops_retired.scalar floating point Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below.  Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element event=0xc7,period=1000003,umask=3  00    Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_ops_retired.scalar_double floating point Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=1  00    Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_ops_retired.scalar_single floating point Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=2  00    Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_ops_retired.vector floating point Number of any Vector retired FP arithmetic instructions event=0xc7,period=1000003,umask=0x3c  00    Number of any Vector retired FP arithmetic instructions.  The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_ops_retired.vector_128b floating point FP_ARITH_OPS_RETIRED.VECTOR_128B [This event is alias to FP_ARITH_INST_RETIRED.VECTOR_128B] event=0xc7,period=100003,umask=0xc  00     fp_arith_ops_retired.vector_256b floating point FP_ARITH_OPS_RETIRED.VECTOR_256B [This event is alias to FP_ARITH_INST_RETIRED.VECTOR_256B] event=0xc7,period=100003,umask=0x30  00     fp_flops_retired.all floating point Counts the number of all types of floating point operations per uop with all default weighting event=0xc8,period=1000003,umask=3  00     fp_flops_retired.dp floating point This event is deprecated. [This event is alias to FP_FLOPS_RETIRED.FP64] event=0xc8,period=1000003,umask=1  10     fp_flops_retired.fp32 floating point Counts the number of floating point operations that produce 32 bit single precision results event=0xc8,period=1000003,umask=2  00     fp_flops_retired.fp32 floating point Counts the number of floating point operations that produce 32 bit single precision results [This event is alias to FP_FLOPS_RETIRED.SP] event=0xc8,period=1000003,umask=2  00     fp_flops_retired.fp64 floating point Counts the number of floating point operations that produce 64 bit double precision results event=0xc8,period=1000003,umask=1  00     fp_flops_retired.fp64 floating point Counts the number of floating point operations that produce 64 bit double precision results [This event is alias to FP_FLOPS_RETIRED.DP] event=0xc8,period=1000003,umask=1  00     fp_flops_retired.sp floating point This event is deprecated. [This event is alias to FP_FLOPS_RETIRED.FP32] event=0xc8,period=1000003,umask=2  10     fp_inst_retired.128b_dp floating point Counts the number of retired instructions whose sources are a packed 128 bit double precision floating point. This may be SSE or AVX.128 operations event=0xc7,period=1000003,umask=8  00     fp_inst_retired.128b_dp floating point Counts the total number of  floating point retired instructions event=0xc7,period=1000003,umask=8  00     fp_inst_retired.128b_sp floating point Counts the number of retired instructions whose sources are a packed 128 bit single precision floating point. This may be SSE or AVX.128 operations event=0xc7,period=1000003,umask=4  00     fp_inst_retired.256b_dp floating point Counts the number of retired instructions whose sources are a packed 256 bit double precision floating point event=0xc7,period=1000003,umask=0x20  00     fp_inst_retired.256b_sp floating point Counts the number of retired instructions whose sources are a packed 256 bit single precision floating point event=0xc7,period=1000003,umask=0x10  00     fp_inst_retired.32b_sp floating point Counts the number of retired instructions whose sources are a scalar 32bit single precision floating point event=0xc7,period=1000003,umask=1  00     fp_inst_retired.64b_dp floating point Counts the number of retired instructions whose sources are a scalar 64 bit double precision floating point event=0xc7,period=1000003,umask=2  00     fp_inst_retired.all floating point Counts the total number of  floating point retired instructions event=0xc7,period=1000003,umask=0x3f  00     fp_vint_uops_executed.all floating point Counts the number of uops executed on all floating point ports event=0xb2,period=1000003,umask=0x1f  00     fp_vint_uops_executed.p0 floating point Counts the number of uops executed on floating point and vector integer port 0 event=0xb2,period=1000003,umask=2  00     fp_vint_uops_executed.p1 floating point Counts the number of uops executed on floating point and vector integer port 1 event=0xb2,period=1000003,umask=4  00     fp_vint_uops_executed.p2 floating point Counts the number of uops executed on floating point and vector integer port 2 event=0xb2,period=1000003,umask=8  00     fp_vint_uops_executed.p3 floating point Counts the number of uops executed on floating point and vector integer port 3 event=0xb2,period=1000003,umask=0x10  00     fp_vint_uops_executed.primary floating point Counts the number of uops executed on floating point and vector integer port 0, 1, 2, 3 event=0xb2,period=1000003,umask=0x1e  00     fp_vint_uops_executed.std floating point Counts the number of uops executed on floating point and vector integer store data port event=0xb2,period=1000003,umask=1  00     uops_retired.fpdiv floating point Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt) event=0xc2,period=2000003,umask=8  00     baclears.any frontend Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches event=0xe6,period=200003,umask=1  00    Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend.  Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches baclears.cond frontend Counts the number of BACLEARS due to a conditional jump event=0xe6,period=200003,umask=0x10  00     baclears.indirect frontend Counts the number of BACLEARS due to an indirect branch event=0xe6,period=200003,umask=2  00     baclears.return frontend Counts the number of BACLEARS due to a return branch event=0xe6,period=200003,umask=8  00     baclears.uncond frontend Counts the number of BACLEARS due to a direct, unconditional jump event=0xe6,period=200003,umask=4  00     decode_restriction.predecode_wrong frontend Counts the number of times a decode restriction reduces the decode throughput due to wrong instruction length prediction event=0xe9,period=200003,umask=1  00     frontend_retired.all frontend Counts the number of instructions retired that were tagged with having preceded with frontend bound behavior event=0xc6,period=1000003  00     frontend_retired.any_ant frontend Retired ANT branches event=0xc6,period=100007,umask=3,frontend=0x9  00    Always Not Taken (ANT) conditional retired branches (no BTB entry and not mispredicted) Available PDIST counters: 0,1 frontend_retired.any_dsb_miss frontend Retired Instructions who experienced DSB miss event=0xc6,period=100007,umask=3,frontend=0x1  00    Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Available PDIST counters: 0,1 frontend_retired.branch_detect frontend Counts the number of instruction retired that are tagged after a branch instruction causes bubbles/empty issue slots due to a baclear event=0xc6,period=1000003,umask=2  00     frontend_retired.branch_resteer frontend Counts the number of instruction retired that are tagged after a branch instruction causes bubbles /empty issue slots due to a btclear event=0xc6,period=1000003,umask=0x40  00     frontend_retired.cisc frontend Counts the number of instructions retired that were tagged following an ms flow due to the bubble/wasted issue slot from exiting long ms flow event=0xc6,period=1000003,umask=1  00    Counts the number of  instructions retired that were tagged following an ms flow due to the bubble/wasted issue slot from exiting long ms flow frontend_retired.decode frontend Counts the number of instructions retired that were tagged every cycle the decoder is unable to send 4 uops event=0xc6,period=1000003,umask=8  00     frontend_retired.decode frontend Counts the number of instructions retired that were tagged every cycle the decoder is unable to send 3 uops per cycle event=0xc6,period=1000003,umask=8  00     frontend_retired.dsb_miss frontend Retired Instructions who experienced a critical DSB miss event=0xc6,period=100007,umask=3,frontend=0x11  00    Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss. Available PDIST counters: 0,1 frontend_retired.icache frontend Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to icache miss event=0xc6,period=1000003,umask=0x20  00     frontend_retired.itlb_miss frontend Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss event=0xc6,period=1000003,umask=0x10  00     frontend_retired.itlb_miss frontend Retired Instructions who experienced iTLB true miss event=0xc6,period=100007,umask=3,frontend=0x14  00    Counts retired Instructions that experienced iTLB (Instruction TLB) true miss. Available PDIST counters: 0,1 frontend_retired.l1i_miss frontend Retired Instructions who experienced Instruction L1 Cache true miss event=0xc6,period=100007,umask=3,frontend=0x12  00    Counts retired Instructions who experienced Instruction L1 Cache true miss. Available PDIST counters: 0,1 frontend_retired.l2_miss frontend Retired Instructions who experienced Instruction L2 Cache true miss event=0xc6,period=100007,umask=3,frontend=0x13  00    Counts retired Instructions who experienced Instruction L2 Cache true miss. Available PDIST counters: 0,1 frontend_retired.latency_ge_128 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=3,frontend=0x608006  00    Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall. Available PDIST counters: 0,1 frontend_retired.latency_ge_16 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=3,frontend=0x601006  00    Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops. Available PDIST counters: 0,1 frontend_retired.latency_ge_2 frontend Retired instructions after front-end starvation of at least 2 cycles event=0xc6,period=100007,umask=3,frontend=0x600206  00    Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall. Available PDIST counters: 0,1 frontend_retired.latency_ge_256 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=3,frontend=0x610006  00    Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall. Available PDIST counters: 0,1 frontend_retired.latency_ge_2_bubbles_ge_1 frontend Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=3,frontend=0x100206  00    Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall. Available PDIST counters: 0,1 frontend_retired.latency_ge_32 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=3,frontend=0x602006  00    Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops. Available PDIST counters: 0,1 frontend_retired.latency_ge_4 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=3,frontend=0x600406  00    Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall. Available PDIST counters: 0,1 frontend_retired.latency_ge_512 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=3,frontend=0x620006  00    Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall. Available PDIST counters: 0,1 frontend_retired.latency_ge_64 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=3,frontend=0x604006  00    Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall. Available PDIST counters: 0,1 frontend_retired.latency_ge_8 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=3,frontend=0x600806  00    Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops. Available PDIST counters: 0,1 frontend_retired.misp_ant frontend Mispredicted Retired ANT branches event=0xc6,period=100007,umask=2,frontend=0x9  00    ANT retired branches that got just mispredicted Available PDIST counters: 0,1 frontend_retired.ms_flows frontend Counts flows delivered by the Microcode Sequencer event=0xc6,period=100007,umask=3,frontend=0x8  00    Counts flows delivered by the Microcode Sequencer Available PDIST counters: 0,1 frontend_retired.other frontend Counts the number of instruction retired tagged after a wasted issue slot if none of the previous events occurred event=0xc6,period=1000003,umask=0x80  00     frontend_retired.predecode frontend Counts the number of instruction retired that are tagged after a branch instruction causes bubbles/empty issue slots due to a predecode wrong event=0xc6,period=1000003,umask=4  00     frontend_retired.stlb_miss frontend Retired Instructions who experienced STLB (2nd level TLB) true miss event=0xc6,period=100007,umask=3,frontend=0x15  00    Counts retired Instructions that experienced STLB (2nd level TLB) true miss. Available PDIST counters: 0,1 frontend_retired.unknown_branch frontend Retired instructions that caused clears due to being Unknown Branches event=0xc6,period=100007,umask=3,frontend=0x17  00    Number retired branch instructions that caused the front-end to be resteered when it finds the instruction in a fetch line. This is called Unknown Branch which occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore. Available PDIST counters: 0,1 frontend_retired_source.icache_l2_hit frontend Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that hit in the L2 cache event=0xc9,period=1000003,umask=1  00    Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that hit in the L2 cache.  Includes L2 Hit resulting from and L1D eviction of another core in the same module which is longer latency than a typical L2 hit frontend_retired_source.icache_l2_miss frontend Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that missed in the L2 cache event=0xc9,period=1000003,umask=0xe  00     frontend_retired_source.icache_l3_hit frontend Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that hit in the L3 cache event=0xc9,period=1000003,umask=6  00     frontend_retired_source.itlb_stlb_hit frontend Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss that hit in the second level TLB event=0xc9,period=1000003,umask=0x10  00     frontend_retired_source.itlb_stlb_miss frontend Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss that also missed the second level TLB event=0xc9,period=1000003,umask=0x20  00     icache.accesses frontend Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump event=0x80,period=200003,umask=3  00     icache.hit frontend Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are present event=0x80,period=200003,umask=1  00     icache.misses frontend Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. - event=0x80,period=200003,umask=2  00     idq.dsb_cycles_ok frontend Cycles DSB is delivering optimal number of Uops event=0x79,cmask=8,period=2000003,umask=8  00    Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the DSB (Decode Stream Buffer) path. Count includes uops that may 'bypass' the IDQ idq.mite_cycles_ok frontend Cycles MITE is delivering optimal number of Uops event=0x79,cmask=8,period=2000003,umask=4  00    Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB) idq.ms_uops frontend Uops initiated by MITE or Decode Stream Buffer (DSB) and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=1000003,umask=0x20  00    Counts the number of uops initiated by MITE or Decode Stream Buffer (DSB) and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ idq_bubbles.core frontend This event counts a subset of the Topdown Slots event that when no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations event=0x9c,period=1000003,umask=1  00    This event counts a subset of the Topdown Slots event that when no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations. Software can use this event as the numerator for the Frontend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method idq_bubbles.cycles_0_uops_deliv.core frontend This event is deprecated. [This event is alias to IDQ_BUBBLES.STARVATION_CYCLES] event=0x9c,cmask=8,period=1000003,umask=1  10     idq_bubbles.cycles_fe_was_ok frontend Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled event=0x9c,cmask=1,inv=1,period=1000003,umask=1  00    Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls idq_bubbles.fetch_latency frontend Cycles when no uops are delivered by the IDQ for 2 or more cycles when backend of the machine is not stalled - normally indicating a Fetch Latency issue event=0x9c,period=1000003,umask=4  00    Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls for 2 or more cycles - normally indicating a Fetch Latency issue idq_bubbles.starvation_cycles frontend Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE] event=0x9c,cmask=8,period=1000003,umask=1  00    Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE] ms_decoded.ms_busy frontend Counts the number of cycles that the micro-sequencer is busy event=0xe7,period=200003,umask=4  00     ms_decoded.ms_busy frontend Counts the number of cycles that the micro-sequencer is busy event=0xe7,period=1000003,umask=4  00     ms_decoded.ms_entry frontend Counts the number of times entered into a ucode flow in the FEC.  Includes inserted flows due to front-end detected faults or assists event=0xe7,period=200003,umask=1  00     ms_decoded.nano_code frontend Counts the number of times nanocode flow is executed event=0xe7,period=200003,umask=2  00     ld_head.any memory Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block event=5,period=1000003,umask=0x7f  00     ld_head.l1_miss memory Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a DL1 miss event=5,period=1000003,umask=1  00     ld_head.other memory Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to other block cases event=5,period=1000003,umask=0x40  00    Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to other block cases such as pipeline conflicts, fences, etc ld_head.pgwalk memory Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a pagewalk event=5,period=1000003,umask=0x20  00     ld_head.st_addr memory Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a store address match event=5,period=1000003,umask=4  00     ld_head.st_data memory Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to store data forward block event=5,period=1000003,umask=8  00     ld_head.wcb_full memory Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to request buffers full or lock in progress event=5,period=1000003,umask=2  00     ld_head.wcb_full_at_ret memory Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to request buffers full or lock in progress event=5,period=1000003,umask=0x82  00     machine_clears.memory_ordering memory Counts the number of memory ordering machine clears triggered due to a snoop from an external agent. Does not count internally generated machine clears such as those due to disambiguations event=0xc3,period=20003,umask=2  00     machine_clears.memory_ordering_fast memory Counts the number of machine clears that flush the pipeline and restart the machine without the use of microcode event=0xc3,period=20003,umask=0x82  00     mem_trans_retired.load_latency_gt_2048 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles  Supports address when precise event=0xcd,period=23,umask=1,ldlat=0x800  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise mem_trans_retired.store_sample memory Retired memory store access operations. A PDist event for PEBS Store Latency Facility  Supports address when precise event=0xcd,period=1000003,umask=2  00    Counts Retired memory accesses with at least 1 store operation. This PEBS event is the precisely-distributed (PDist) trigger covering all stores uops for sampling by the PEBS Store Latency Facility. The facility is described in Intel SDM Volume 3 section 19.9.8 Available PDIST counters: 0,1  Supports address when precise misalign_mem_ref.load_page_split memory Counts misaligned loads that are 4K page splits event=0x13,period=200003,umask=2  00     misalign_mem_ref.store_page_split memory Counts misaligned stores that are 4K page splits event=0x13,period=200003,umask=4  00     ocr.demand_data_rd.dram memory Counts demand data reads that were supplied by DRAM event=0x2a,period=100003,umask=1,offcore_rsp=0x1E780000001  00    Counts demand data reads that were supplied by DRAM. Available PDIST counters: 0 ocr.demand_data_rd.l3_miss memory Counts demand data reads that were not supplied by the L3 cache event=0x2a,period=100003,umask=1,offcore_rsp=0xFE7F8000001  00    Counts demand data reads that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.demand_rfo.l3_miss memory Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache event=0x2a,period=100003,umask=1,offcore_rsp=0xFE7F8000002  00    Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. Available PDIST counters: 0 offcore_requests_outstanding.cycles_with_l3_miss_demand_data_rd memory Cycles where data return is pending for a Demand Data Read request who miss L3 cache event=0x20,cmask=1,period=1000003,umask=0x10  00    Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ assists.hardware other Count all other hardware assists or traps that are not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and A/D assists who are counted by dedicated sub-events event=0xc1,period=100003,umask=4  00    Count all other hardware assists or traps that are not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and A/D assists who are counted by dedicated sub-events.  This includes, but not limited to, assists at EXE or MEM uop writeback like AVX* load/store/gather/scatter (non-FP GSSE-assist ) , assists generated by ROB like PEBS and RTIT, Uncore trap, RAR (Remote Action Request) and CET (Control flow Enforcement Technology) assists bus_lock.blocked_cycles other Counts the number of unhalted cycles a Core is blocked due to a lock In Progress issued by another core event=0x63,period=1000003,umask=1  00    Counts the number of unhalted cycles a Core is blocked due to a lock In Progress issued by another core. Counts on a per core basis bus_lock.lock_cycles other Counts the number of unhalted cycles a Core is blocked due to an Accepted lock it issued, includes both split and non-split lock cycles event=0x63,period=1000003,umask=2  00    Counts the number of unhalted cycles a Core is blocked due to an Accepted lock it issued, includes both split and non-split lock cycles. Counts on a per core basis bus_lock.non_split_locks other Counts the number of non-split locks such as UC locks issued by a Core (does not include cache locks) event=0x63,period=1000003,umask=4  00     bus_lock.split_locks other Counts the number of split locks issued by a Core event=0x63,period=1000003,umask=8  00     dynamic_prefetch_throttler.level0_soc other Counts the number of cycles the L2 Prefetchers are at throttle level 0 event=0x32,period=1000003,umask=1  00     dynamic_prefetch_throttler.level1_soc other Counts the number of cycles the L2 Prefetcher throttle level is at 1 event=0x32,period=1000003,umask=2  00     dynamic_prefetch_throttler.level2_soc other Counts the number of cycles the L2 Prefetcher throttle level is at 2 event=0x32,period=1000003,umask=4  00     dynamic_prefetch_throttler.level3_soc other Counts the number of cycles the L2 Prefetcher throttle level is at 3 event=0x32,period=1000003,umask=8  00     dynamic_prefetch_throttler.level4_soc other Counts the number of cycles the L2 Prefetcher throttle level is at 4 event=0x32,period=1000003,umask=0x10  00     xq.full other Cycles the uncore cannot take further requests event=0x2d,cmask=1,period=1000003,umask=1  00    number of cycles when the thread is active and the uncore cannot take any further requests (for example prefetches, loads or stores initiated by the Core that miss the L2 cache) xq_promotion.all other Counts the number of prefetch requests that were promoted in the XQ to a demand request event=0xf4,period=1000003,umask=7  00     xq_promotion.crds other Counts the number of prefetch requests that were promoted in the XQ to a demand code read event=0xf4,period=1000003,umask=4  00     xq_promotion.drds other Counts the number of prefetch requests that were promoted in the XQ to a demand read event=0xf4,period=1000003,umask=1  00     xq_promotion.rfos other Counts the number of prefetch requests that were promoted in the XQ to a demand RFO event=0xf4,period=1000003,umask=2  00     arith.idiv_active pipeline Counts the number of cycles when any of the integer dividers are active event=0xcd,cmask=1,period=1000003,umask=1  00     arith.idiv_active pipeline Cycles when integer divide unit is busy executing divide or square root operations event=0xb0,cmask=1,period=1000003,umask=8  00    Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer operations only assists.any pipeline Number of occurrences where a microcode assist is invoked by hardware event=0xc1,period=100003,umask=0x1f  00    Counts the number of occurrences where a microcode assist is invoked by hardware. Examples include AD (page Access Dirty), FP and AVX related assists be_stalls.scoreboard pipeline Counts cycles where the pipeline is stalled due to serializing operations event=0xa2,period=100003,umask=2  00     br_inst_retired.all_branches pipeline All branch instructions retired event=0xc4,period=400009  00    Counts all branch instructions retired. Available PDIST counters: 0,1 br_inst_retired.all_branches pipeline Counts the total number of branch instructions retired for all branch types  Spec update: ARL010, ARL011 event=0xc4,period=200003  00    Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires.  All branch type instructions are accounted for  Spec update: ARL010, ARL011 br_inst_retired.cond pipeline Counts retired JCC (Jump on Conditional Code) branch instructions retired includes both taken and not taken branches event=0xc4,period=200003,umask=0x7e  00     br_inst_retired.cond pipeline Conditional branch instructions retired event=0xc4,period=400009,umask=0x111  00    Counts conditional branch instructions retired. Available PDIST counters: 0,1 br_inst_retired.cond pipeline Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches  Spec update: ARL011 event=0xc4,period=200003,umask=0x7e  00     br_inst_retired.cond_ntaken pipeline Counts the number of not taken JCC branch instructions retired event=0xc4,period=200003,umask=0x7f  00     br_inst_retired.cond_ntaken pipeline Not taken branch instructions retired event=0xc4,period=400009,umask=0x10  00    Counts not taken branch instructions retired. Available PDIST counters: 0,1 br_inst_retired.cond_taken pipeline Counts the number of taken JCC branch instructions retired event=0xc4,period=200003,umask=0xfe  00     br_inst_retired.cond_taken pipeline Taken conditional branch instructions retired event=0xc4,period=400009,umask=0x101  00    Counts taken conditional branch instructions retired. Available PDIST counters: 0,1 br_inst_retired.cond_taken_bwd pipeline Taken backward conditional branch instructions retired event=0xc4,period=400009,umask=1  00    Counts taken backward conditional branch instructions retired. Available PDIST counters: 0,1 br_inst_retired.cond_taken_fwd pipeline Taken forward conditional branch instructions retired event=0xc4,period=400009,umask=0x102  00    Counts taken forward conditional branch instructions retired. Available PDIST counters: 0,1 br_inst_retired.far_branch pipeline Counts the number of far branch instructions retired, includes far jump, far call and return, and Interrupt call and return event=0xc4,period=200003,umask=0xbf  00     br_inst_retired.far_branch pipeline Far branch instructions retired event=0xc4,period=100007,umask=0x40  00    Counts far branch instructions retired. Available PDIST counters: 0,1 br_inst_retired.far_branch pipeline Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return  Spec update: ARL011 event=0xc4,period=200003,umask=0xbf  00     br_inst_retired.indirect pipeline Indirect near branch instructions retired (excluding returns) event=0xc4,period=100003,umask=0x80  00    Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch. Available PDIST counters: 0,1 br_inst_retired.indirect pipeline Counts the number of near indirect JMP and near indirect CALL branch instructions retired  Spec update: ARL011 event=0xc4,period=200003,umask=0xeb  00     br_inst_retired.indirect_call pipeline Counts the number of near indirect CALL branch instructions retired  Spec update: ARL011 event=0xc4,period=200003,umask=0xfb  00     br_inst_retired.indirect_jmp pipeline Counts the number of near indirect JMP branch instructions retired event=0xc4,period=200003,umask=0xef  00     br_inst_retired.ind_call pipeline This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT_CALL  Spec update: ARL011 event=0xc4,period=200003,umask=0xfb  10     br_inst_retired.near_call pipeline Direct and indirect near call instructions retired event=0xc4,period=100007,umask=2  00    Counts both direct and indirect near call instructions retired. Available PDIST counters: 0,1 br_inst_retired.near_call pipeline Counts the number of near CALL branch instructions retired  Spec update: ARL010, ARL011 event=0xc4,period=200003,umask=0xf9  00     br_inst_retired.near_return pipeline Return instructions retired event=0xc4,period=100007,umask=8  00    Counts return instructions retired. Available PDIST counters: 0,1 br_inst_retired.near_taken pipeline Counts the number of taken branch instructions retired event=0xc4,period=200003,umask=0xc0  00     br_inst_retired.near_taken pipeline Taken branch instructions retired event=0xc4,period=400009,umask=0x20  00    Counts taken branch instructions retired. Available PDIST counters: 0,1 br_inst_retired.near_taken pipeline Counts the number of near taken branch instructions retired  Spec update: ARL011 event=0xc4,period=200003,umask=0xc0  00     br_inst_retired.rel_jmp pipeline Counts the number of near relative JMP branch instructions retired event=0xc4,period=200003,umask=0xdf  00     br_misp_retired.all_branches pipeline All mispredicted branch instructions retired event=0xc5,period=400009  00    Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch.  When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path. Available PDIST counters: 0,1 br_misp_retired.all_branches_cost pipeline All mispredicted branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch event=0xc5,period=400009,umask=0x44  00    All mispredicted branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0,1 br_misp_retired.cond pipeline Counts the number of mispredicted JCC branch instructions retired event=0xc5,period=200003,umask=0x7e  00     br_misp_retired.cond pipeline Mispredicted conditional branch instructions retired event=0xc5,period=400009,umask=0x111  00    Counts mispredicted conditional branch instructions retired. Available PDIST counters: 0,1 br_misp_retired.cond_cost pipeline Mispredicted conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch event=0xc5,period=400009,umask=0x151  00    Mispredicted conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0,1 br_misp_retired.cond_ntaken pipeline Counts the number of mispredicted not taken JCC branch instructions retired event=0xc5,period=200003,umask=0x7f  00     br_misp_retired.cond_ntaken pipeline Mispredicted non-taken conditional branch instructions retired event=0xc5,period=400009,umask=0x10  00    Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken. Available PDIST counters: 0,1 br_misp_retired.cond_ntaken_cost pipeline Mispredicted non-taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch event=0xc5,period=400009,umask=0x50  00    Mispredicted non-taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0,1 br_misp_retired.cond_taken pipeline Counts the number of mispredicted taken JCC branch instructions retired event=0xc5,period=200003,umask=0xfe  00     br_misp_retired.cond_taken pipeline number of branch instructions retired that were mispredicted and taken event=0xc5,period=400009,umask=0x101  00    Counts taken conditional mispredicted branch instructions retired. Available PDIST counters: 0,1 br_misp_retired.cond_taken_bwd pipeline number of branch instructions retired that were mispredicted and taken backward event=0xc5,period=400009,umask=1  00    Counts taken backward conditional mispredicted branch instructions retired. Available PDIST counters: 0,1 br_misp_retired.cond_taken_bwd_cost pipeline number of branch instructions retired that were mispredicted and taken backward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch event=0xc5,period=400009,umask=0x8001  00    number of branch instructions retired that were mispredicted and taken backward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0,1 br_misp_retired.cond_taken_cost pipeline Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch event=0xc5,period=400009,umask=0x141  00    Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0,1 br_misp_retired.cond_taken_fwd pipeline number of branch instructions retired that were mispredicted and taken forward event=0xc5,period=400009  00    Counts taken forward conditional mispredicted branch instructions retired. Available PDIST counters: 0,1 br_misp_retired.cond_taken_fwd_cost pipeline number of branch instructions retired that were mispredicted and taken forward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch event=0xc5,period=400009,umask=0x8002  00    number of branch instructions retired that were mispredicted and taken forward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0,1 br_misp_retired.indirect pipeline Miss-predicted near indirect branch instructions retired (excluding returns) event=0xc5,period=100003,umask=0x80  00    Counts miss-predicted near indirect branch instructions retired excluding returns. TSX abort is an indirect branch. Available PDIST counters: 0,1 br_misp_retired.indirect_call pipeline Mispredicted indirect CALL retired event=0xc5,period=400009,umask=2  00    Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect. Available PDIST counters: 0,1 br_misp_retired.indirect_call_cost pipeline Mispredicted indirect CALL retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch event=0xc5,period=400009,umask=0x42  00    Mispredicted indirect CALL retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0,1 br_misp_retired.indirect_cost pipeline Mispredicted near indirect branch instructions retired (excluding returns). This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch event=0xc5,period=100003,umask=0xc0  00    Mispredicted near indirect branch instructions retired (excluding returns). This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0,1 br_misp_retired.indirect_jmp pipeline Counts the number of mispredicted near indirect JMP branch instructions retired event=0xc5,period=200003,umask=0xef  00     br_misp_retired.near_taken pipeline Number of near branch instructions retired that were mispredicted and taken event=0xc5,period=400009,umask=0x20  00    Counts number of near branch instructions retired that were mispredicted and taken. Available PDIST counters: 0,1 br_misp_retired.near_taken_cost pipeline Mispredicted taken near branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch event=0xc5,period=400009,umask=0x60  00    Mispredicted taken near branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0,1 br_misp_retired.ret pipeline This event counts the number of mispredicted ret instructions retired. Non PEBS event=0xc5,period=100007,umask=8  00    This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired. Available PDIST counters: 0,1 br_misp_retired.ret_cost pipeline Mispredicted ret instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch event=0xc5,period=100007,umask=0x48  00    Mispredicted ret instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0,1 btclear.any pipeline Counts the total number of BTCLEARS event=0xe8,period=1000003  00    Counts the total number of BTCLEARS which occurs when the Branch Target Buffer (BTB) predicts a taken branch cpu_clk_unhalted.core pipeline Fixed Counter: Counts the number of unhalted core clock cycles event=0x3c,period=2000003  00     cpu_clk_unhalted.core pipeline Core cycles when the core is not in a halt state event=0x3c,period=2000003  00    Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the programmable counters available for other events cpu_clk_unhalted.core_p pipeline Counts the number of unhalted core clock cycles [This event is alias to CPU_CLK_UNHALTED.THREAD_P] event=0x3c,period=2000003  00     cpu_clk_unhalted.core_p pipeline Thread cycles when thread is not in halt state [This event is alias to CPU_CLK_UNHALTED.THREAD_P] event=0x3c,period=2000003  00    This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time. [This event is alias to CPU_CLK_UNHALTED.THREAD_P] cpu_clk_unhalted.pause pipeline Core clocks when a PAUSE is pending event=0xec,period=2000003,umask=0x40  00     cpu_clk_unhalted.pause_inst pipeline Number of Pause instructions event=0xec,cmask=1,edge=1,period=2000003,umask=0x40  00     cpu_clk_unhalted.ref_tsc pipeline Fixed Counter: Counts the number of unhalted reference clock cycles event=0,period=2000003,umask=3  00     cpu_clk_unhalted.ref_tsc pipeline Reference cycles when the core is not in halt state event=0,period=2000003,umask=3  00    Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case cpu_clk_unhalted.ref_tsc_p pipeline Counts the number of unhalted reference clock cycles event=0x3c,period=2000003,umask=1  00    Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter cpu_clk_unhalted.ref_tsc_p pipeline Reference cycles when the core is not in halt state event=0x3c,period=2000003,umask=1  00    Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case cpu_clk_unhalted.thread pipeline Fixed Counter: Counts the number of unhalted core clock cycles event=0x3c,period=2000003  00     cpu_clk_unhalted.thread pipeline Core cycles when the thread is not in a halt state event=0x3c,period=2000003  00    Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the programmable counters available for other events cpu_clk_unhalted.thread_p pipeline Counts the number of unhalted core clock cycles [This event is alias to CPU_CLK_UNHALTED.CORE_P] event=0x3c,period=2000003  00     cpu_clk_unhalted.thread_p pipeline Thread cycles when thread is not in halt state [This event is alias to CPU_CLK_UNHALTED.CORE_P] event=0x3c,period=2000003  00    This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time. [This event is alias to CPU_CLK_UNHALTED.CORE_P] dependent_loads.any pipeline Count number of times a load is depending on another load that had just write back its data or in previous or  2 cycles back. This event supports in-direct dependency through a single uop event=2,period=1000003,umask=7  00     inst_retired.any pipeline Fixed Counter: Counts the number of instructions retired event=0xc0,period=2000003  00    Fixed Counter: Counts the number of instructions retired. Available PDIST counters: 32 inst_retired.any pipeline Fixed Counter: Counts the number of instructions retired event=0xc0,period=2000003  00    Fixed Counter: Counts the number of instructions retired Available PDIST counters: 32 inst_retired.any_p pipeline Counts the number of instructions retired event=0xc0,period=2000003  00     inst_retired.any_p pipeline Number of instructions retired. General Counter - architectural event event=0xc0,period=2000003  00    Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter. Available PDIST counters: 0,1 inst_retired.br_fused pipeline retired macro-fused uops when there is a branch in the macro-fused pair (the two instructions that got macro-fused count once in this pmon) event=0xc0,period=1000003,umask=0x10  00    retired macro-fused uops when there is a branch in the macro-fused pair (the two instructions that got macro-fused count once in this pmon) Available PDIST counters: 0,1 inst_retired.macro_fused pipeline INST_RETIRED.MACRO_FUSED event=0xc0,period=2000003,umask=0x30  00    INST_RETIRED.MACRO_FUSED Available PDIST counters: 0,1 inst_retired.nop pipeline Retired NOP instructions event=0xc0,period=2000003,umask=2  00    Counts all retired NOP or ENDBR32/64 or PREFETCHIT0/1 instructions Available PDIST counters: 0,1 inst_retired.rep_iteration pipeline Iterations of Repeat string retired instructions event=0xc0,period=2000003,umask=8  00    Number of iterations of Repeat (REP) string retired instructions such as MOVS, CMPS, and SCAS. Each has a byte, word, and doubleword version and string instructions can be repeated using a repetition prefix, REP, that allows their architectural execution to be repeated a number of times as specified by the RCX register. Note the number of iterations is implementation-dependent. Available PDIST counters: 0,1 int_misc.bpclear_cycles pipeline Bubble cycles of BPClear event=0xad,period=1000003,umask=0x40,frontend=0xB  00     int_uops_executed.2nd pipeline Counts the number of uops executed on secondary integer ports 0,1,2,3 event=0xb3,period=1000003,umask=0x80  00     int_uops_executed.all pipeline Counts the number of uops executed on all Integer ports event=0xb3,period=1000003,umask=0xff  00     int_uops_executed.ld pipeline Counts the number of uops executed on a load port event=0xb3,period=1000003,umask=1  00    Counts the number of uops executed on a load port.  This event counts for integer uops even if the destination is FP/vector int_uops_executed.p0 pipeline Counts the number of uops executed on integer port 0 event=0xb3,period=1000003,umask=8  00     int_uops_executed.p1 pipeline Counts the number of uops executed on integer port 1 event=0xb3,period=1000003,umask=0x10  00     int_uops_executed.p2 pipeline Counts the number of uops executed on integer port 2 event=0xb3,period=1000003,umask=0x20  00     int_uops_executed.p3 pipeline Counts the number of uops executed on integer port 3 event=0xb3,period=1000003,umask=0x40  00     int_uops_executed.primary pipeline Counts the number of uops executed on integer port  0,1, 2, 3 event=0xb3,period=1000003,umask=0x78  00     int_uops_executed.sta pipeline Counts the number of uops executed on a Store address port event=0xb3,period=1000003,umask=2  00    Counts the number of uops executed on a Store address port. This event counts integer uops even if the data source is FP/vector int_uops_executed.std_jmp pipeline Counts the number of uops executed on an integer store data and jump port event=0xb3,period=1000003,umask=4  00     int_vec_retired.128bit pipeline Number of vector integer instructions retired of 128-bit vector-width event=0xe7,period=1000003,umask=0x13  00     int_vec_retired.256bit pipeline Number of vector integer instructions retired of 256-bit vector-width event=0xe7,period=1000003,umask=0xac  00     ld_blocks.all pipeline Counts the number of occurrences a retired load was blocked for any of the following reasons:  utlb_miss, 4k_alias, unknown_sta/bad_fwd, unready_fwd (includes md blocks and esp consuming load blocks) event=3,period=1000003,umask=0x1f  00     ld_blocks.data_unknown pipeline Counts the number of occurrences a retired load gets blocked because its address exactly matches an older store whose data is not ready (a.k.a. unknown).  unready_fwd event=3,period=1000003,umask=1  00     ld_blocks.store_early pipeline Counts the number of times a load got early blocked due to preceding store operation with unknown address or unknown data. Excluding in-line (immediate) wakeups event=3,period=100003,umask=0xa1  00     ld_blocks.store_forward pipeline Counts the number of occurrences a retired load gets blocked because its address partially overlaps with an older store (size mismatch) - unknown_sta/bad_forward event=3,period=1000003,umask=2  00     ld_blocks.store_forward pipeline Counts the number of retired loads that are blocked because its address partially overlapped with an older store event=3,period=1000003,umask=2  00     load_hit_prefetch.hwpf pipeline Counts the number of demand loads that match on a wcb (request buffer) allocated by an L1 hardware prefetch [This event is alias to LOAD_HIT_PREFETCH.HW_PF] event=0x4c,period=1000003,umask=2  00     load_hit_prefetch.hw_pf pipeline This event is deprecated. [This event is alias to LOAD_HIT_PREFETCH.HWPF] event=0x4c,period=1000003,umask=2  10     lsd.cycles_ok pipeline Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder event=0xa8,cmask=8,period=2000003,umask=1  00    Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector) machine_clears.any pipeline Counts all machine clears for any reason including, but not limited to memory ordering, SMC, and FP assist event=0xc3,period=20003  00     machine_clears.any_fast pipeline Counts the number of machine clears that flush the pipeline and restart the machine without the use of microcode event=0xc3,period=20003,umask=0xff  00     machine_clears.disambiguation pipeline Counts the number of memory ordering machine clears triggered due to an internal load passing an older store within the same CPU event=0xc3,period=20003,umask=8  00     machine_clears.disambiguation_fast pipeline Counts the number of machine clears that flush the pipeline and restart the machine without the use of microcode event=0xc3,period=20003,umask=0x88  00     machine_clears.mrn_nuke pipeline Counts the number of nukes due to memory renaming event=0xc3,period=20003,umask=0x10  00     machine_clears.mrn_nuke_fast pipeline Counts the number of machine clears that flush the pipeline and restart the machine without the use of microcode event=0xc3,period=20003,umask=0x90  00     machine_clears.page_fault pipeline Counts the number of times that the machine clears due to a page fault.  Covers both I-Side and D-Side (Loads/Stores) page faults.  A page fault occurs when either the page is not present, or an access violation event=0xc3,period=20003,umask=0x20  00     machine_clears.slow pipeline This event is deprecated event=0xc3,period=20003,umask=0x6e  10     memory_stalls.l1 pipeline Counts cycles where no execution is happening due to loads waiting for L1 cache (that is: no execution & load in flight & no load missed L1 cache) event=0x46,period=1000003,umask=1  00     memory_stalls.l2 pipeline Counts cycles where no execution is happening due to loads waiting for L2 cache (that is: no execution & load in flight & load missed L1 & no load missed L2 cache) event=0x46,period=1000003,umask=2  00     memory_stalls.l3 pipeline Counts cycles where no execution is happening due to loads waiting for L3 cache (that is: no execution & load in flight & load missed L1 & load missed L2 cache & no load missed L3 Cache) event=0x46,period=1000003,umask=4  00     memory_stalls.mem pipeline Counts cycles where no execution is happening due to loads waiting for Memory (that is: no execution & load in flight & a load missed L3 cache) event=0x46,period=1000003,umask=8  00     misc_retired.lbr_inserts pipeline Counts the number of LBR entries recorded. Requires LBRs to be enabled in IA32_LBR_CTL event=0xe4,period=1000003,umask=1  00     misc_retired.lbr_inserts pipeline LBR record is inserted event=0xe4,period=1000003,umask=1  00    LBR record is inserted Available PDIST counters: 0,1 misc_retired.lbr_inserts pipeline Counts the number of Last Branch Record (LBR) entries. Requires LBRs to be enabled and configured in IA32_LBR_CTL. [This event is alias to LBR_INSERTS.ANY] event=0xe4,period=1000003,umask=1  00     misc_retired1.cl_inst pipeline Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired event=0xe0,period=1000003,umask=0xff  00     misc_retired1.lfence pipeline Counts the number of LFENCE instructions retired event=0xe0,period=1000003,umask=2  00     misc_retired1.rdpmc_rdtsc_p pipeline Counts the number of RDPMC, RDTSC, and RDTSCP instructions retired event=0xe0,period=1000003,umask=1  00     misc_retired1.wrmsr pipeline Count the number of WRMSR instructions retired event=0xe0,period=1000003  00     misc_retired2.fault_all pipeline Counts the number of faults and software interrupts with vector < 32 event=0xe1,period=1000003  00    Counts the number of faults and software interrupts with vector < 32, including VOE cases misc_retired2.intel_pt_clears pipeline Counts the number of PSB+ nuke events and ToPA trap events event=0xe1,period=1000003,umask=2  00     misc_retired2.uli_delivery pipeline Counts the number of user interrupts delivered event=0xe1,period=1000003,umask=8  00     misc_retired2.uli_senduipi pipeline Counts the number of SENDUIPI instructions retired event=0xe1,period=1000003,umask=9  00     misc_retired2.vm_exit pipeline Counts the number of VM exits event=0xe1,period=1000003,umask=1  00     rs.empty_resource pipeline Cycles when RS was empty and a resource allocation stall is asserted event=0xa5,period=1000003,umask=1  00     serialization.c01_ms_scb pipeline Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state event=0x75,period=1000003,umask=4  00     serialization.c01_ms_scb pipeline Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state event=0x75,period=200003,umask=4  00     serialization.color_stalls pipeline Counts the number issue slots not consumed  due to a  color request for an FCW or MXCSR control register when all 4 colors (copies) are already in use event=0x75,period=1000003,umask=8  00     serialization.iq_jeu_scb pipeline Counts the number of issue slots where no uop could issue due to an IQ scoreboard that stalls allocation until a specified older uop retires or (in the case of jump scoreboard) executes. Commonly executed instructions with IQ scoreboards include LFENCE and MFENCE event=0x75,period=1000003,umask=1  00     serialization.non_c01_ms_scb pipeline Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires event=0x75,period=1000003,umask=2  00    Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires. The most commonly executed instruction with an MS scoreboard is PAUSE topdown.backend_bound_slots pipeline This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions event=0xa4,period=10000003,umask=2  00    This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions. Software can use this event as the numerator for the Backend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method topdown.slots pipeline TMA slots available for an unhalted logical processor. Fixed counter - architectural event event=0,period=10000003,umask=4  00    Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3) topdown.slots_p pipeline TMA slots available for an unhalted logical processor. General counter - architectural event event=0xa4,period=10000003,umask=1  00    Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method topdown_bad_speculation.all pipeline Fixed Counter: Counts the number of issue slots not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear event=0,period=1000003,umask=5  00    Fixed Counter: Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.  Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the IQ. Also, includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear topdown_bad_speculation.all_p pipeline Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear event=0x73,period=1000003  00     topdown_bad_speculation.all_p pipeline Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear event=0x73,period=1000003  00    Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear topdown_bad_speculation.fastnuke pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to Fast Nukes such as  Memory Ordering Machine clears and MRN nukes event=0x73,period=1000003,umask=2  00     topdown_bad_speculation.mispredict pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to Branch Mispredict event=0x73,period=1000003,umask=4  00     topdown_be_bound.all pipeline Counts the number of retirement slots not consumed due to backend stalls [This event is alias to TOPDOWN_BE_BOUND.ALL_P] event=0xa4,period=1000003,umask=2  00     topdown_be_bound.alloc_restrictions pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to due to certain allocation restrictions event=0x74,period=1000003,umask=1  00     topdown_be_bound.all_non_arch pipeline Counts the number of retirement slots not consumed due to backend stalls event=0x74,period=1000003  00     topdown_be_bound.all_p pipeline Counts the number of retirement slots not consumed due to backend stalls [This event is alias to TOPDOWN_BE_BOUND.ALL] event=0xa4,period=1000003,umask=2  00     topdown_be_bound.all_p pipeline Counts the number of retirement slots not consumed due to backend stalls event=0x74,period=1000003  00     topdown_be_bound.mem_scheduler pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stall (scheduler not being able to accept another uop).  This could be caused by RSV full or load/store buffer block event=0x74,period=1000003,umask=2  00     topdown_be_bound.non_mem_scheduler pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to IEC and FPC RAT stalls - which can be due to the FIQ and IEC reservation station stall (integer, FP and SIMD scheduler not being able to accept another uop. ) event=0x74,period=1000003,umask=8  00     topdown_be_bound.register pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to mrbl stall.  A 'marble' refers to a physical register file entry, also known as the physical destination (PDST) event=0x74,period=1000003,umask=0x20  00     topdown_be_bound.reorder_buffer pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to ROB full event=0x74,period=1000003,umask=0x40  00     topdown_be_bound.serialization pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to iq/jeu scoreboards or ms scb event=0x74,period=1000003,umask=0x10  00     topdown_fe_bound.all pipeline Fixed Counter: Counts the number of retirement slots not consumed due to front end stalls event=0,period=1000003,umask=6  00     topdown_fe_bound.all_non_arch pipeline Counts the number of retirement slots not consumed due to front end stalls event=0x71,period=1000003  00     topdown_fe_bound.all_p pipeline Counts the number of retirement slots not consumed due to front end stalls event=0x9c,period=1000003,umask=1  00     topdown_fe_bound.all_p pipeline Counts the number of retirement slots not consumed due to front end stalls event=0x71,period=1000003  00     topdown_fe_bound.branch_detect pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to BAClear event=0x71,period=1000003,umask=2  00     topdown_fe_bound.branch_resteer pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to BTClear event=0x71,period=1000003,umask=0x40  00     topdown_fe_bound.cisc pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to ms event=0x71,period=1000003,umask=1  00     topdown_fe_bound.decode pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stall event=0x71,period=1000003,umask=8  00     topdown_fe_bound.frontend_latency pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses event=0x71,period=1000003,umask=0x72  00     topdown_fe_bound.itlb pipeline This event is deprecated. [This event is alias to TOPDOWN_FE_BOUND.ITLB_MISS] event=0x71,period=1000003,umask=0x10  10     topdown_fe_bound.itlb_miss pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to itlb miss event=0x71,period=1000003,umask=0x10  00     topdown_fe_bound.itlb_miss pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to itlb miss [This event is alias to TOPDOWN_FE_BOUND.ITLB] event=0x71,period=1000003,umask=0x10  00     topdown_fe_bound.other pipeline Counts the number of issue slots every cycle that were not delivered by the frontend that do not categorize into any other common frontend stall event=0x71,period=1000003,umask=0x80  00     topdown_fe_bound.predecode pipeline Counts the number of issue slots every cycle that were not delivered by the frontend due to predecode wrong event=0x71,period=1000003,umask=4  00     topdown_retiring.all pipeline Fixed Counter: Counts the number of consumed retirement slots event=0,period=1000003,umask=7  00     topdown_retiring.all_non_arch pipeline Counts the number of consumed retirement slots event=0x72,period=1000003  00     topdown_retiring.all_p pipeline Counts the number of consumed retirement slots event=0xc2,period=1000003,umask=2  00     topdown_retiring.all_p pipeline Counts the number of consumed retirement slots event=0x72,period=1000003  00     uops_decoded.dec0_uops pipeline Number of non dec-by-all uops decoded by decoder event=0x76,period=1000003,umask=1  00    This event counts the number of not dec-by-all uops decoded by decoder 0 uops_dispatched.alu pipeline Uops executed on INT EU ALU ports event=0xb2,period=2000003,umask=2  00    Number of ALU integer uops dispatch to execution uops_dispatched.int_eu_all pipeline Uops executed on any INT EU ports event=0xb2,period=2000003,umask=1  00    Number of integer uops dispatched to execution uops_dispatched.jmp pipeline Number of Uops dispatched/executed by any of the 3 JEUs (all ups that hold the JEU including macro; micro jumps; fetch-from-eip) event=0xb2,period=2000003,umask=0x40  00    Number of jump uops dispatch to execution uops_dispatched.load pipeline Uops executed on Load ports event=0xb2,period=2000003,umask=4  00    Number of Load uops dispatched to execution uops_dispatched.shift pipeline Number of (shift) 1-cycle Uops dispatched/executed by any of the Shift Eus event=0xb2,period=2000003,umask=0x20  00    Number of SHIFT integer uops dispatch to execution uops_dispatched.slow pipeline Number of Uops dispatched/executed by Slow EU (e.g. 3+ cycles LEA, >1 cycles shift, iDIVs, CR; *H operation) event=0xb2,period=2000003,umask=8  00    Number of Slow integer uops dispatch to execution uops_dispatched.sta pipeline Number of Uops dispatched on STA ports event=0xb2,period=2000003,umask=0x80  00    Number of STA (Store Address) uops dispatch to execution uops_dispatched.std pipeline Uops executed on STD ports event=0xb2,period=2000003,umask=0x10  00    Number of STD (Store Data) uops dispatch to execution uops_issued.any pipeline When 4-uops are requested and only 2-uops are delivered, the event counts 2.  Uops_issued correlates to the number of ROB entries.  If uop takes 2 ROB slots it counts as 2 uops_issued event=0xe,period=200003  00     uops_issued.any pipeline Counts the number of uops issued by the front end every cycle event=0xe,period=1000003  00    Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2.  Uops_issued correlates to the number of ROB entries.  If uop takes 2 ROB slots it counts as 2 uops_issued uops_retired.all pipeline Counts the number of uops retired event=0xc2,period=2000003  00     uops_retired.lsd pipeline Counts the number of uops retired that were delivered by the loop stream detector (LSD) event=0xc2,period=2000003,umask=4  00     uops_retired.ms pipeline Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS).  This includes uops from flows due to complex instructions, faults, assists, and inserted flows event=0xc2,period=2000003,umask=1  00     uops_retired.ms_switches pipeline Number of non-speculative switches to the Microcode Sequencer (MS) event=0xc2,cmask=1,edge=1,period=2000003,umask=4,frontend=0x8  00    Switches to the Microcode Sequencer uops_retired.slots pipeline This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance  for example, as measured by the instructions-per-cycle metric event=0xc2,period=2000003,umask=2  00    This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance  for example, as measured by the instructions-per-cycle metric. Software can use this event as the numerator for the Retiring metric (or top-level category) of the Top-down Microarchitecture Analysis method uops_retired.x87 pipeline Counts the number of x87 uops retired, includes those in ms flows event=0xc2,period=2000003,umask=0x20  00     uops_retired.x87 pipeline Counts the number of x87 uops retired, includes those in ms flows event=0xc2,period=2000003,umask=2  00     uncore_hac_cbo unc_hac_cbo_tor_allocation.all uncore cache Number of all entries allocated. Includes also retries event=0x35,umask=8  01     unc_hac_cbo_tor_allocation.drd uncore cache Asserted on coherent DRD + DRdPref  allocations into the queue. Cacheable only event=0x35,umask=1  01     uncore_hac_arb unc_hac_arb_req_trk_request.drd uncore interconnect Number of all coherent Data Read entries. Doesn't include prefetches event=0x81,umask=2  01     unc_hac_arb_transactions.all uncore interconnect Number of all CMI transactions event=0x8a,umask=1  01     unc_hac_arb_transactions.reads uncore interconnect Number of all CMI reads event=0x8a,umask=2  01     unc_hac_arb_transactions.writes uncore interconnect Number of all CMI writes not including Mflush event=0x8a,umask=4  01     unc_hac_arb_trk_requests.all uncore interconnect Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic event=0x81,umask=1  01     unc_mc0_rdcas_count_freerun uncore memory Counts every CAS read command sent from the Memory Controller 0 to DRAM (sum of all channels) event=0xff,umask=0x20  01    Counts every CAS read command sent from the Memory Controller 0 to DRAM (sum of all channels). Each CAS commands can be for 32B or 64B of data unc_mc0_total_reqcount_freerun uncore memory Counts every read and write request entering the Memory Controller 0 event=0xff,umask=0x10  01    Counts every read and write request entering the Memory Controller 0 (sum of all channels). All requests are counted as one, whether they are 32B or 64B Read/Write or partial/full line writes. Some write requests to the same address may merge to a single write command to DRAM. Therefore, the total request count may be higher than total DRAM BW unc_mc0_wrcas_count_freerun uncore memory Counts every CAS write command sent from the Memory Controller 0 to DRAM (sum of all channels) event=0xff,umask=0x30  01    Counts every CAS write command sent from the Memory Controller 0 to DRAM (sum of all channels).  Each CAS commands can be for 32B or 64B of data unc_mc1_rdcas_count_freerun uncore memory Counts every CAS read command sent from the Memory Controller 1 to DRAM (sum of all channels) event=0xff,umask=0x20  01    Counts every CAS read command sent from the Memory Controller 1 to DRAM (sum of all channels). Each CAS commands can be for 32B or 64B of data unc_mc1_total_reqcount_freerun uncore memory Counts every read and write request entering the Memory Controller 1 event=0xff,umask=0x10  01    Counts every read and write request entering the Memory Controller 1 (sum of all channels). All requests are counted as one, whether they are 32B or 64B Read/Write or partial/full line writes. Some write requests to the same address may merge to a single write command to DRAM. Therefore, the total request count may be higher than total DRAM BW unc_mc1_wrcas_count_freerun uncore memory Counts every CAS write command sent from the Memory Controller 1 to DRAM (sum of all channels) event=0xff,umask=0x30  01    Counts every CAS write command sent from the Memory Controller 1 to DRAM (sum of all channels).  Each CAS commands can be for 32B or 64B of data unc_m_rd_data uncore memory Number of bytes read from DRAM, in 32B chunks. Counter increments by 1 after receiving 32B chunk data event=0x3a  01     unc_m_total_data uncore memory Total number of read and write byte transfers to/from DRAM, in 32B chunks. Counter increments by 1 after sending or receiving 32B chunk data event=0x3c  01     unc_m_wr_data uncore memory Number of bytes written to DRAM, in 32B chunks. Counter increments by 1 after sending 32B chunk data event=0x3b  01     uncore_cncu dtlb_load_misses.miss_caused_walk virtual memory Counts the number of page walks initiated by a demand load that missed the first and second level TLBs event=8,period=200003,umask=1  00     dtlb_load_misses.pde_cache_miss virtual memory Counts walks that miss the PDE_CACHE event=8,period=200003,umask=0x80  00     dtlb_load_misses.stlb_hit virtual memory Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB event=8,period=200003,umask=0x20  00     dtlb_load_misses.stlb_hit virtual memory Loads that miss the DTLB and hit the STLB event=0x12,period=100003,umask=0x320  00    Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB) dtlb_load_misses.walk_completed virtual memory Counts the number of page walks completed due to load DTLB misses event=8,period=200003,umask=0xe  00     dtlb_load_misses.walk_completed_2m_4m virtual memory Counts the number of page walks completed due to load DTLB misses to a 2M or 4M page event=8,period=200003,umask=4  00    Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault dtlb_load_misses.walk_completed_4k virtual memory Counts the number of page walks completed due to load DTLB misses to a 4K page event=8,period=200003,umask=2  00    Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault dtlb_load_misses.walk_pending virtual memory Counts the number of page walks outstanding for Loads (demand or SW prefetch) in PMH every cycle event=8,period=200003,umask=0x10  00    Counts the number of page walks outstanding for Loads (demand or SW prefetch) in PMH every cycle.  A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals dtlb_store_misses.miss_caused_walk virtual memory Counts the number of page walks initiated by a store that missed the first and second level TLBs event=0x49,period=2000003,umask=1  00     dtlb_store_misses.pde_cache_miss virtual memory Counts walks that miss the PDE_CACHE event=0x49,period=2000003,umask=0x80  00     dtlb_store_misses.stlb_hit virtual memory Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB event=0x49,period=2000003,umask=0x20  00    Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB dtlb_store_misses.stlb_hit virtual memory Stores that miss the DTLB and hit the STLB event=0x13,period=100003,umask=0x320  00    Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB) dtlb_store_misses.stlb_hit virtual memory Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Accounts for all pages sizes. Will result in a DTLB write from STLB event=0x49,period=2000003,umask=0x20  00     dtlb_store_misses.walk_completed virtual memory Counts the number of page walks completed due to store DTLB misses to a 1G page event=0x49,period=2000003,umask=0xe  00     dtlb_store_misses.walk_completed_2m_4m virtual memory Counts the number of page walks completed due to store DTLB misses to a 2M or 4M page event=0x49,period=2000003,umask=4  00    Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages.  Includes page walks that page fault dtlb_store_misses.walk_completed_4k virtual memory Counts the number of page walks completed due to store DTLB misses to a 4K page event=0x49,period=2000003,umask=2  00    Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages.  Includes page walks that page fault dtlb_store_misses.walk_pending virtual memory Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle event=0x49,period=200003,umask=0x10  00    Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals itlb.fills virtual memory Counts the number of times there was an ITLB miss and a new translation was filled into the ITLB event=0x81,period=200003,umask=4  00    Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) and a new translation was filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB itlb_misses.miss_caused_walk virtual memory Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs event=0x85,period=2000003,umask=1  00     itlb_misses.pde_cache_miss virtual memory Counts walks that miss the PDE_CACHE event=0x85,period=2000003,umask=0x80  00     itlb_misses.stlb_hit virtual memory Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will result in an ITLB write from STLB event=0x85,period=2000003,umask=0x20  00     itlb_misses.stlb_hit virtual memory Instruction fetch requests that miss the ITLB and hit the STLB event=0x11,period=100003,umask=0x120  00    Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB) itlb_misses.walk_completed virtual memory Counts the number of page walks completed due to instruction fetch misses to any page size event=0x85,period=2000003,umask=0xe  00    Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size.  Includes page walks that page fault itlb_misses.walk_completed_2m_4m virtual memory Counts the number of page walks completed due to instruction fetch misses to a 2M or 4M page event=0x85,period=2000003,umask=4  00    Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages.  Includes page walks that page fault itlb_misses.walk_completed_4k virtual memory Counts the number of page walks completed due to instruction fetch misses to a 4K page event=0x85,period=2000003,umask=2  00    Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages.  Includes page walks that page fault itlb_misses.walk_pending virtual memory Counts the number of page walks outstanding for iside in PMH every cycle event=0x85,period=200003,umask=0x10  00    Counts the number of page walks outstanding for iside in PMH every cycle.  A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.  Walks could be counted by edge detecting on this event, but would count restarted suspended walks ld_blocks.dtlb_miss virtual memory Counts the number of occurrences a load gets blocked because of a micro TLB miss event=3,period=1000003,umask=8  00     ld_head.dtlb_miss virtual memory Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a DTLB miss event=5,period=1000003,umask=0x10  00     page_walker_loads.dtlb_l1_hit virtual memory Counts the number of PMH walks that hit in the L1 or WCBs event=0xbc,period=1000003,umask=1  00     page_walker_loads.dtlb_l2_hit virtual memory Counts the number of PMH walks that hit in the L2 event=0xbc,period=1000003,umask=2  00    Counts the number of PMH walks that hit in the L2.  Includes L2 Hit resulting from and L1D eviction of another core in the same module which is longer latency than a typical L2 hit tlb_flushes.stlb_any virtual memory Count number of any STLB flush attempts (Entire, PCID, InvPage, CR3 write, etc) event=0xbd,period=20003,umask=0x20  00     l1d_cache.all_cache_ref cache L1 Data Cacheable reads and writes event=0x40,period=2000000,umask=0xa3  00     l1d_cache.all_ref cache L1 Data reads and writes event=0x40,period=2000000,umask=0x83  00     l1d_cache.evict cache Modified cache lines evicted from the L1 data cache event=0x40,period=200000,umask=0x10  00     l1d_cache.ld cache L1 Cacheable Data Reads event=0x40,period=2000000,umask=0xa1  00     l1d_cache.repl cache L1 Data line replacements event=0x40,period=200000,umask=8  00     l1d_cache.replm cache Modified cache lines allocated in the L1 data cache event=0x40,period=200000,umask=0x48  00     l1d_cache.st cache L1 Cacheable Data Writes event=0x40,period=2000000,umask=0xa2  00     l2_ads.self cache Cycles L2 address bus is in use event=0x21,period=200000,umask=0x40  00     l2_data_rqsts.self.e_state cache All data requests from the L1 data cache event=0x2c,period=200000,umask=0x44  00     l2_data_rqsts.self.i_state cache All data requests from the L1 data cache event=0x2c,period=200000,umask=0x41  00     l2_data_rqsts.self.mesi cache All data requests from the L1 data cache event=0x2c,period=200000,umask=0x4f  00     l2_data_rqsts.self.m_state cache All data requests from the L1 data cache event=0x2c,period=200000,umask=0x48  00     l2_data_rqsts.self.s_state cache All data requests from the L1 data cache event=0x2c,period=200000,umask=0x42  00     l2_dbus_busy.self cache Cycles the L2 cache data bus is busy event=0x22,period=200000,umask=0x40  00     l2_dbus_busy_rd.self cache Cycles the L2 transfers data to the core event=0x23,period=200000,umask=0x40  00     l2_ifetch.self.e_state cache L2 cacheable instruction fetch requests event=0x28,period=200000,umask=0x44  00     l2_ifetch.self.i_state cache L2 cacheable instruction fetch requests event=0x28,period=200000,umask=0x41  00     l2_ifetch.self.mesi cache L2 cacheable instruction fetch requests event=0x28,period=200000,umask=0x4f  00     l2_ifetch.self.m_state cache L2 cacheable instruction fetch requests event=0x28,period=200000,umask=0x48  00     l2_ifetch.self.s_state cache L2 cacheable instruction fetch requests event=0x28,period=200000,umask=0x42  00     l2_ld.self.any.e_state cache L2 cache reads event=0x29,period=200000,umask=0x74  00     l2_ld.self.any.i_state cache L2 cache reads event=0x29,period=200000,umask=0x71  00     l2_ld.self.any.mesi cache L2 cache reads event=0x29,period=200000,umask=0x7f  00     l2_ld.self.any.m_state cache L2 cache reads event=0x29,period=200000,umask=0x78  00     l2_ld.self.any.s_state cache L2 cache reads event=0x29,period=200000,umask=0x72  00     l2_ld.self.demand.e_state cache L2 cache reads event=0x29,period=200000,umask=0x44  00     l2_ld.self.demand.i_state cache L2 cache reads event=0x29,period=200000,umask=0x41  00     l2_ld.self.demand.mesi cache L2 cache reads event=0x29,period=200000,umask=0x4f  00     l2_ld.self.demand.m_state cache L2 cache reads event=0x29,period=200000,umask=0x48  00     l2_ld.self.demand.s_state cache L2 cache reads event=0x29,period=200000,umask=0x42  00     l2_ld.self.prefetch.e_state cache L2 cache reads event=0x29,period=200000,umask=0x54  00     l2_ld.self.prefetch.i_state cache L2 cache reads event=0x29,period=200000,umask=0x51  00     l2_ld.self.prefetch.mesi cache L2 cache reads event=0x29,period=200000,umask=0x5f  00     l2_ld.self.prefetch.m_state cache L2 cache reads event=0x29,period=200000,umask=0x58  00     l2_ld.self.prefetch.s_state cache L2 cache reads event=0x29,period=200000,umask=0x52  00     l2_ld_ifetch.self.e_state cache All read requests from L1 instruction and data caches event=0x2d,period=200000,umask=0x44  00     l2_ld_ifetch.self.i_state cache All read requests from L1 instruction and data caches event=0x2d,period=200000,umask=0x41  00     l2_ld_ifetch.self.mesi cache All read requests from L1 instruction and data caches event=0x2d,period=200000,umask=0x4f  00     l2_ld_ifetch.self.m_state cache All read requests from L1 instruction and data caches event=0x2d,period=200000,umask=0x48  00     l2_ld_ifetch.self.s_state cache All read requests from L1 instruction and data caches event=0x2d,period=200000,umask=0x42  00     l2_lines_in.self.any cache L2 cache misses event=0x24,period=200000,umask=0x70  00     l2_lines_in.self.demand cache L2 cache misses event=0x24,period=200000,umask=0x40  00     l2_lines_in.self.prefetch cache L2 cache misses event=0x24,period=200000,umask=0x50  00     l2_lines_out.self.any cache L2 cache lines evicted event=0x26,period=200000,umask=0x70  00     l2_lines_out.self.demand cache L2 cache lines evicted event=0x26,period=200000,umask=0x40  00     l2_lines_out.self.prefetch cache L2 cache lines evicted event=0x26,period=200000,umask=0x50  00     l2_lock.self.e_state cache L2 locked accesses event=0x2b,period=200000,umask=0x44  00     l2_lock.self.i_state cache L2 locked accesses event=0x2b,period=200000,umask=0x41  00     l2_lock.self.mesi cache L2 locked accesses event=0x2b,period=200000,umask=0x4f  00     l2_lock.self.m_state cache L2 locked accesses event=0x2b,period=200000,umask=0x48  00     l2_lock.self.s_state cache L2 locked accesses event=0x2b,period=200000,umask=0x42  00     l2_m_lines_in.self cache L2 cache line modifications event=0x25,period=200000,umask=0x40  00     l2_m_lines_out.self.any cache Modified lines evicted from the L2 cache event=0x27,period=200000,umask=0x70  00     l2_m_lines_out.self.demand cache Modified lines evicted from the L2 cache event=0x27,period=200000,umask=0x40  00     l2_m_lines_out.self.prefetch cache Modified lines evicted from the L2 cache event=0x27,period=200000,umask=0x50  00     l2_no_req.self cache Cycles no L2 cache requests are pending event=0x32,period=200000,umask=0x40  00     l2_reject_busq.self.any.e_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x74  00     l2_reject_busq.self.any.i_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x71  00     l2_reject_busq.self.any.mesi cache Rejected L2 cache requests event=0x30,period=200000,umask=0x7f  00     l2_reject_busq.self.any.m_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x78  00     l2_reject_busq.self.any.s_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x72  00     l2_reject_busq.self.demand.e_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x44  00     l2_reject_busq.self.demand.i_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x41  00     l2_reject_busq.self.demand.mesi cache Rejected L2 cache requests event=0x30,period=200000,umask=0x4f  00     l2_reject_busq.self.demand.m_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x48  00     l2_reject_busq.self.demand.s_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x42  00     l2_reject_busq.self.prefetch.e_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x54  00     l2_reject_busq.self.prefetch.i_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x51  00     l2_reject_busq.self.prefetch.mesi cache Rejected L2 cache requests event=0x30,period=200000,umask=0x5f  00     l2_reject_busq.self.prefetch.m_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x58  00     l2_reject_busq.self.prefetch.s_state cache Rejected L2 cache requests event=0x30,period=200000,umask=0x52  00     l2_rqsts.self.any.e_state cache L2 cache requests event=0x2e,period=200000,umask=0x74  00     l2_rqsts.self.any.i_state cache L2 cache requests event=0x2e,period=200000,umask=0x71  00     l2_rqsts.self.any.mesi cache L2 cache requests event=0x2e,period=200000,umask=0x7f  00     l2_rqsts.self.any.m_state cache L2 cache requests event=0x2e,period=200000,umask=0x78  00     l2_rqsts.self.any.s_state cache L2 cache requests event=0x2e,period=200000,umask=0x72  00     l2_rqsts.self.demand.e_state cache L2 cache requests event=0x2e,period=200000,umask=0x44  00     l2_rqsts.self.demand.i_state cache L2 cache demand requests from this core that missed the L2 event=0x2e,period=200000,umask=0x41  00     l2_rqsts.self.demand.mesi cache L2 cache demand requests from this core event=0x2e,period=200000,umask=0x4f  00     l2_rqsts.self.demand.m_state cache L2 cache requests event=0x2e,period=200000,umask=0x48  00     l2_rqsts.self.demand.s_state cache L2 cache requests event=0x2e,period=200000,umask=0x42  00     l2_rqsts.self.prefetch.e_state cache L2 cache requests event=0x2e,period=200000,umask=0x54  00     l2_rqsts.self.prefetch.i_state cache L2 cache requests event=0x2e,period=200000,umask=0x51  00     l2_rqsts.self.prefetch.mesi cache L2 cache requests event=0x2e,period=200000,umask=0x5f  00     l2_rqsts.self.prefetch.m_state cache L2 cache requests event=0x2e,period=200000,umask=0x58  00     l2_rqsts.self.prefetch.s_state cache L2 cache requests event=0x2e,period=200000,umask=0x52  00     l2_st.self.e_state cache L2 store requests event=0x2a,period=200000,umask=0x44  00     l2_st.self.i_state cache L2 store requests event=0x2a,period=200000,umask=0x41  00     l2_st.self.mesi cache L2 store requests event=0x2a,period=200000,umask=0x4f  00     l2_st.self.m_state cache L2 store requests event=0x2a,period=200000,umask=0x48  00     l2_st.self.s_state cache L2 store requests event=0x2a,period=200000,umask=0x42  00     mem_load_retired.l2_hit cache Retired loads that hit the L2 cache (precise event) event=0xcb,period=200000,umask=1  00     mem_load_retired.l2_miss cache Retired loads that miss the L2 cache event=0xcb,period=10000,umask=2  00     fp_assist.ar floating point Floating point assists for retired operations event=0x11,period=10000,umask=0x81  00     fp_assist.s floating point Floating point assists event=0x11,period=10000,umask=1  00     simd_assist floating point SIMD assists invoked event=0xcd,period=100000  00     simd_comp_inst_retired.packed_single floating point Retired computational Streaming SIMD Extensions (SSE) packed-single instructions event=0xca,period=2000000,umask=1  00     simd_comp_inst_retired.scalar_double floating point Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions event=0xca,period=2000000,umask=8  00     simd_comp_inst_retired.scalar_single floating point Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions event=0xca,period=2000000,umask=2  00     simd_instr_retired floating point SIMD Instructions retired event=0xce,period=2000000  00     simd_inst_retired.packed_single floating point Retired Streaming SIMD Extensions (SSE) packed-single instructions event=0xc7,period=2000000,umask=1  00     simd_inst_retired.scalar_double floating point Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions event=0xc7,period=2000000,umask=8  00     simd_inst_retired.scalar_single floating point Retired Streaming SIMD Extensions (SSE) scalar-single instructions event=0xc7,period=2000000,umask=2  00     simd_inst_retired.vector floating point Retired Streaming SIMD Extensions 2 (SSE2) vector instructions event=0xc7,period=2000000,umask=0x10  00     simd_sat_instr_retired floating point Saturated arithmetic instructions retired event=0xcf,period=2000000  00     simd_sat_uop_exec.ar floating point SIMD saturated arithmetic micro-ops retired event=0xb1,period=2000000,umask=0x80  00     simd_sat_uop_exec.s floating point SIMD saturated arithmetic micro-ops executed event=0xb1,period=2000000  00     simd_uops_exec.ar floating point SIMD micro-ops retired (excluding stores) (Must be precise) event=0xb0,period=2000000,umask=0x80  00     simd_uops_exec.s floating point SIMD micro-ops executed (excluding stores) event=0xb0,period=2000000  00     simd_uop_type_exec.arithmetic.ar floating point SIMD packed arithmetic micro-ops retired event=0xb3,period=2000000,umask=0xa0  00     simd_uop_type_exec.arithmetic.s floating point SIMD packed arithmetic micro-ops executed event=0xb3,period=2000000,umask=0x20  00     simd_uop_type_exec.logical.ar floating point SIMD packed logical micro-ops retired event=0xb3,period=2000000,umask=0x90  00     simd_uop_type_exec.logical.s floating point SIMD packed logical micro-ops executed event=0xb3,period=2000000,umask=0x10  00     simd_uop_type_exec.mul.ar floating point SIMD packed multiply micro-ops retired event=0xb3,period=2000000,umask=0x81  00     simd_uop_type_exec.mul.s floating point SIMD packed multiply micro-ops executed event=0xb3,period=2000000,umask=1  00     simd_uop_type_exec.pack.ar floating point SIMD packed micro-ops retired event=0xb3,period=2000000,umask=0x84  00     simd_uop_type_exec.pack.s floating point SIMD packed micro-ops executed event=0xb3,period=2000000,umask=4  00     simd_uop_type_exec.shift.ar floating point SIMD packed shift micro-ops retired event=0xb3,period=2000000,umask=0x82  00     simd_uop_type_exec.shift.s floating point SIMD packed shift micro-ops executed event=0xb3,period=2000000,umask=2  00     simd_uop_type_exec.unpack.ar floating point SIMD unpacked micro-ops retired event=0xb3,period=2000000,umask=0x88  00     simd_uop_type_exec.unpack.s floating point SIMD unpacked micro-ops executed event=0xb3,period=2000000,umask=8  00     x87_comp_ops_exe.any.ar floating point Floating point computational micro-ops retired (Must be precise) event=0x10,period=2000000,umask=0x81  00     x87_comp_ops_exe.any.s floating point Floating point computational micro-ops executed event=0x10,period=2000000,umask=1  00     x87_comp_ops_exe.fxch.ar floating point FXCH uops retired (Must be precise) event=0x10,period=2000000,umask=0x82  00     x87_comp_ops_exe.fxch.s floating point FXCH uops executed event=0x10,period=2000000,umask=2  00     baclears.any frontend BACLEARS asserted event=0xe6,period=2000000,umask=1  00     cycles_icache_mem_stalled.icache_mem_stalled frontend Cycles during which instruction fetches are  stalled event=0x86,period=2000000,umask=1  00     decode_stall.iq_full frontend Decode stall due to IQ full event=0x87,period=2000000,umask=2  00     decode_stall.pfb_empty frontend Decode stall due to PFB empty event=0x87,period=2000000,umask=1  00     icache.accesses frontend Instruction fetches event=0x80,period=200000,umask=3  00     icache.hit frontend Icache hit event=0x80,period=200000,umask=1  00     icache.misses frontend Icache miss event=0x80,period=200000,umask=2  00     macro_insts.all_decoded frontend All Instructions decoded event=0xaa,period=2000000,umask=3  00     macro_insts.cisc_decoded frontend CISC macro instructions decoded event=0xaa,period=2000000,umask=2  00     macro_insts.non_cisc_decoded frontend Non-CISC macro instructions decoded event=0xaa,period=2000000,umask=1  00     uops.ms_cycles frontend This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ event=0xa9,cmask=1,period=2000000,umask=1  00     misalign_mem_ref.bubble memory Nonzero segbase 1 bubble event=5,period=200000,umask=0x97  00     misalign_mem_ref.ld_bubble memory Nonzero segbase load 1 bubble event=5,period=200000,umask=0x91  00     misalign_mem_ref.ld_split memory Load splits event=5,period=200000,umask=9  00     misalign_mem_ref.ld_split.ar memory Load splits (At Retirement) event=5,period=200000,umask=0x89  00     misalign_mem_ref.rmw_bubble memory Nonzero segbase ld-op-st 1 bubble event=5,period=200000,umask=0x94  00     misalign_mem_ref.rmw_split memory ld-op-st splits event=5,period=200000,umask=0x8c  00     misalign_mem_ref.split memory Memory references that cross an 8-byte boundary event=5,period=200000,umask=0xf  00     misalign_mem_ref.split.ar memory Memory references that cross an 8-byte boundary (At Retirement) event=5,period=200000,umask=0x8f  00     misalign_mem_ref.st_bubble memory Nonzero segbase store 1 bubble event=5,period=200000,umask=0x92  00     misalign_mem_ref.st_split memory Store splits event=5,period=200000,umask=0xa  00     misalign_mem_ref.st_split.ar memory Store splits (Ar Retirement) event=5,period=200000,umask=0x8a  00     prefetch.hw_prefetch memory L1 hardware prefetch request event=7,period=2000000,umask=0x10  00     prefetch.prefetchnta memory Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed event=7,period=200000,umask=0x88  00     prefetch.prefetcht0 memory Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed event=7,period=200000,umask=0x81  00     prefetch.prefetcht1 memory Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed event=7,period=200000,umask=0x82  00     prefetch.prefetcht2 memory Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed event=7,period=200000,umask=0x84  00     prefetch.software_prefetch memory Any Software prefetch event=7,period=200000,umask=0xf  00     prefetch.software_prefetch.ar memory Any Software prefetch event=7,period=200000,umask=0x8f  00     prefetch.sw_l2 memory Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed event=7,period=200000,umask=0x86  00     busq_empty.self other Bus queue is empty event=0x7d,period=200000,umask=0x40  00     bus_bnr_drv.all_agents other Number of Bus Not Ready signals asserted event=0x61,period=200000,umask=0x20  00     bus_bnr_drv.this_agent other Number of Bus Not Ready signals asserted event=0x61,period=200000  00     bus_data_rcv.self other Bus cycles while processor receives data event=0x64,period=200000,umask=0x40  00     bus_drdy_clocks.all_agents other Bus cycles when data is sent on the bus event=0x62,period=200000,umask=0x20  00     bus_drdy_clocks.this_agent other Bus cycles when data is sent on the bus event=0x62,period=200000  00     bus_hitm_drv.all_agents other HITM signal asserted event=0x7b,period=200000,umask=0x20  00     bus_hitm_drv.this_agent other HITM signal asserted event=0x7b,period=200000  00     bus_hit_drv.all_agents other HIT signal asserted event=0x7a,period=200000,umask=0x20  00     bus_hit_drv.this_agent other HIT signal asserted event=0x7a,period=200000  00     bus_io_wait.self other IO requests waiting in the bus queue event=0x7f,period=200000,umask=0x40  00     bus_lock_clocks.all_agents other Bus cycles when a LOCK signal is asserted event=0x63,period=200000,umask=0xe0  00     bus_lock_clocks.self other Bus cycles when a LOCK signal is asserted event=0x63,period=200000,umask=0x40  00     bus_request_outstanding.all_agents other Outstanding cacheable data read bus requests duration event=0x60,period=200000,umask=0xe0  00     bus_request_outstanding.self other Outstanding cacheable data read bus requests duration event=0x60,period=200000,umask=0x40  00     bus_trans_any.all_agents other All bus transactions event=0x70,period=200000,umask=0xe0  00     bus_trans_any.self other All bus transactions event=0x70,period=200000,umask=0x40  00     bus_trans_brd.all_agents other Burst read bus transactions event=0x65,period=200000,umask=0xe0  00     bus_trans_brd.self other Burst read bus transactions event=0x65,period=200000,umask=0x40  00     bus_trans_burst.all_agents other Burst (full cache-line) bus transactions event=0x6e,period=200000,umask=0xe0  00     bus_trans_burst.self other Burst (full cache-line) bus transactions event=0x6e,period=200000,umask=0x40  00     bus_trans_def.all_agents other Deferred bus transactions event=0x6d,period=200000,umask=0xe0  00     bus_trans_def.self other Deferred bus transactions event=0x6d,period=200000,umask=0x40  00     bus_trans_ifetch.all_agents other Instruction-fetch bus transactions event=0x68,period=200000,umask=0xe0  00     bus_trans_ifetch.self other Instruction-fetch bus transactions event=0x68,period=200000,umask=0x40  00     bus_trans_inval.all_agents other Invalidate bus transactions event=0x69,period=200000,umask=0xe0  00     bus_trans_inval.self other Invalidate bus transactions event=0x69,period=200000,umask=0x40  00     bus_trans_io.all_agents other IO bus transactions event=0x6c,period=200000,umask=0xe0  00     bus_trans_io.self other IO bus transactions event=0x6c,period=200000,umask=0x40  00     bus_trans_mem.all_agents other Memory bus transactions event=0x6f,period=200000,umask=0xe0  00     bus_trans_mem.self other Memory bus transactions event=0x6f,period=200000,umask=0x40  00     bus_trans_p.all_agents other Partial bus transactions event=0x6b,period=200000,umask=0xe0  00     bus_trans_p.self other Partial bus transactions event=0x6b,period=200000,umask=0x40  00     bus_trans_pwr.all_agents other Partial write bus transaction event=0x6a,period=200000,umask=0xe0  00     bus_trans_pwr.self other Partial write bus transaction event=0x6a,period=200000,umask=0x40  00     bus_trans_rfo.all_agents other RFO bus transactions event=0x66,period=200000,umask=0xe0  00     bus_trans_rfo.self other RFO bus transactions event=0x66,period=200000,umask=0x40  00     bus_trans_wb.all_agents other Explicit writeback bus transactions event=0x67,period=200000,umask=0xe0  00     bus_trans_wb.self other Explicit writeback bus transactions event=0x67,period=200000,umask=0x40  00     cycles_int_masked.cycles_int_masked other Cycles during which interrupts are disabled event=0xc6,period=2000000,umask=1  00     cycles_int_masked.cycles_int_pending_and_masked other Cycles during which interrupts are pending and disabled event=0xc6,period=2000000,umask=2  00     ext_snoop.all_agents.any other External snoops event=0x77,period=200000,umask=0x2b  00     ext_snoop.all_agents.clean other External snoops event=0x77,period=200000,umask=0x21  00     ext_snoop.all_agents.hit other External snoops event=0x77,period=200000,umask=0x22  00     ext_snoop.all_agents.hitm other External snoops event=0x77,period=200000,umask=0x28  00     ext_snoop.this_agent.any other External snoops event=0x77,period=200000,umask=0xb  00     ext_snoop.this_agent.clean other External snoops event=0x77,period=200000,umask=1  00     ext_snoop.this_agent.hit other External snoops event=0x77,period=200000,umask=2  00     ext_snoop.this_agent.hitm other External snoops event=0x77,period=200000,umask=8  00     hw_int_rcv other Hardware interrupts received event=0xc8,period=200000  00     snoop_stall_drv.all_agents other Bus stalled for snoops event=0x7e,period=200000,umask=0xe0  00     snoop_stall_drv.self other Bus stalled for snoops event=0x7e,period=200000,umask=0x40  00     thermal_trip other Number of thermal trips event=0x3b,period=200000,umask=0xc0  00     bogus_br pipeline Bogus branches event=0xe4,period=2000000,umask=1  00     br_inst_decoded pipeline Branch instructions decoded event=0xe0,period=2000000,umask=1  00     br_inst_retired.any pipeline Retired branch instructions event=0xc4,period=2000000  00     br_inst_retired.any1 pipeline Retired branch instructions event=0xc4,period=2000000,umask=0xf  00     br_inst_retired.mispred pipeline Retired mispredicted branch instructions (precise event) (Precise event) event=0xc5,period=200000  00     br_inst_retired.mispred_not_taken pipeline Retired branch instructions that were mispredicted not-taken event=0xc4,period=200000,umask=2  00     br_inst_retired.mispred_taken pipeline Retired branch instructions that were mispredicted taken event=0xc4,period=200000,umask=8  00     br_inst_retired.pred_not_taken pipeline Retired branch instructions that were predicted not-taken event=0xc4,period=2000000,umask=1  00     br_inst_retired.pred_taken pipeline Retired branch instructions that were predicted taken event=0xc4,period=2000000,umask=4  00     br_inst_retired.taken pipeline Retired taken branch instructions event=0xc4,period=2000000,umask=0xc  00     br_inst_type_retired.cond pipeline All macro conditional branch instructions event=0x88,period=2000000,umask=1  00     br_inst_type_retired.cond_taken pipeline Only taken macro conditional branch instructions event=0x88,period=2000000,umask=0x41  00     br_inst_type_retired.dir_call pipeline All non-indirect calls event=0x88,period=2000000,umask=0x10  00     br_inst_type_retired.ind pipeline All indirect branches that are not calls event=0x88,period=2000000,umask=4  00     br_inst_type_retired.ind_call pipeline All indirect calls, including both register and memory indirect event=0x88,period=2000000,umask=0x20  00     br_inst_type_retired.ret pipeline All indirect branches that have a return mnemonic event=0x88,period=2000000,umask=8  00     br_inst_type_retired.uncond pipeline All macro unconditional branch instructions, excluding calls and indirects event=0x88,period=2000000,umask=2  00     br_missp_type_retired.cond pipeline Mispredicted cond branch instructions retired event=0x89,period=200000,umask=1  00     br_missp_type_retired.cond_taken pipeline Mispredicted and taken cond branch instructions retired event=0x89,period=200000,umask=0x11  00     br_missp_type_retired.ind pipeline Mispredicted ind branches that are not calls event=0x89,period=200000,umask=2  00     br_missp_type_retired.ind_call pipeline Mispredicted indirect calls, including both register and memory indirect event=0x89,period=200000,umask=8  00     br_missp_type_retired.return pipeline Mispredicted return branches event=0x89,period=200000,umask=4  00     cpu_clk_unhalted.bus pipeline Bus cycles when core is not halted event=0x3c,period=200000,umask=1  00     cpu_clk_unhalted.core pipeline Core cycles when core is not halted event=0x3c,period=2000003  00     cpu_clk_unhalted.core_p pipeline Core cycles when core is not halted event=0x3c,period=2000000  00     cpu_clk_unhalted.ref pipeline Reference cycles when core is not halted event=0x0,umask=0x03,period=2000003  00     dispatch_blocked.any pipeline Memory cluster signals to block micro-op dispatch for any reason event=9,period=200000,umask=0x20  00     div.ar pipeline Divide operations retired event=0x13,period=2000000,umask=0x81  00     div.s pipeline Divide operations executed event=0x13,period=2000000,umask=1  00     inst_retired.any pipeline Instructions retired event=0xc0,period=2000003  00     inst_retired.any_p pipeline Instructions retired (precise event) (Must be precise) event=0xc0,period=2000003  00     machine_clears.smc pipeline Self-Modifying Code detected event=0xc3,period=200000,umask=1  00     mul.ar pipeline Multiply operations retired event=0x12,period=2000000,umask=0x81  00     mul.s pipeline Multiply operations executed event=0x12,period=2000000,umask=1  00     reissue.any pipeline Micro-op reissues for any cause event=3,period=200000,umask=0x7f  00     reissue.any.ar pipeline Micro-op reissues for any cause (At Retirement) event=3,period=200000,umask=0xff  00     reissue.overlap_store pipeline Micro-op reissues on a store-load collision event=3,period=200000,umask=1  00     reissue.overlap_store.ar pipeline Micro-op reissues on a store-load collision (At Retirement) event=3,period=200000,umask=0x81  00     resource_stalls.div_busy pipeline Cycles issue is stalled due to div busy event=0xdc,period=2000000,umask=2  00     store_forwards.any pipeline All store forwards event=2,period=200000,umask=0x83  00     store_forwards.good pipeline Good store forwards event=2,period=200000,umask=0x81  00     uops_retired.any pipeline Micro-ops retired event=0xc2,period=2000000,umask=0x10  00     uops_retired.stalled_cycles pipeline Cycles no micro-ops retired event=0xc2,period=2000000,umask=0x10  00     uops_retired.stalls pipeline Periods no micro-ops retired event=0xc2,period=2000000,umask=0x10  00     data_tlb_misses.dtlb_miss virtual memory Memory accesses that missed the DTLB event=8,period=200000,umask=7  00     data_tlb_misses.dtlb_miss_ld virtual memory DTLB misses due to load operations event=8,period=200000,umask=5  00     data_tlb_misses.dtlb_miss_st virtual memory DTLB misses due to store operations event=8,period=200000,umask=6  00     data_tlb_misses.l0_dtlb_miss_ld virtual memory L0 DTLB misses due to load operations event=8,period=200000,umask=9  00     data_tlb_misses.l0_dtlb_miss_st virtual memory L0 DTLB misses due to store operations event=8,period=200000,umask=0xa  00     itlb.flush virtual memory ITLB flushes event=0x82,period=200000,umask=4  00     itlb.hit virtual memory ITLB hits event=0x82,period=200000,umask=1  00     itlb.misses virtual memory ITLB misses (Must be precise) event=0x82,period=200000,umask=2  00     mem_load_retired.dtlb_miss virtual memory Retired loads that miss the DTLB (precise event) (Precise event) event=0xcb,period=200000,umask=4  00     page_walks.cycles virtual memory Duration of page-walks in core cycles event=0xc,period=2000000,umask=3  00     page_walks.d_side_cycles virtual memory Duration of D-side only page walks event=0xc,period=2000000,umask=1  00     page_walks.d_side_walks virtual memory Number of D-side only page walks event=0xc,period=200000,umask=1  00     page_walks.i_side_cycles virtual memory Duration of I-Side page walks event=0xc,period=2000000,umask=2  00     page_walks.i_side_walks virtual memory Number of I-Side page walks event=0xc,period=200000,umask=2  00     page_walks.walks virtual memory Number of page-walks executed event=0xc,period=200000,umask=3  00     l1d.replacement cache L1D data line replacements event=0x51,period=2000003,umask=1  00    This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace l1d_pend_miss.fb_full cache Cycles a demand request was blocked due to Fill Buffers unavailability event=0x48,cmask=1,period=2000003,umask=2  00     l1d_pend_miss.pending cache L1D miss outstandings duration in cycles event=0x48,period=2000003,umask=1  00    This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type l1d_pend_miss.pending_cycles cache Cycles with L1D load Misses outstanding event=0x48,cmask=1,period=2000003,umask=1  00    This event counts duration of L1D miss outstanding in cycles l1d_pend_miss.pending_cycles_any cache Cycles with L1D load Misses outstanding from any thread on physical core event=0x48,any=1,cmask=1,period=2000003,umask=1  00     l2_demand_rqsts.wb_hit cache Not rejected writebacks that hit L2 cache event=0x27,period=200003,umask=0x50  00    This event counts the number of WB requests that hit L2 cache l2_lines_in.all cache L2 cache lines filling L2 event=0xf1,period=100003,umask=7  00    This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects l2_lines_in.e cache L2 cache lines in E state filling L2 event=0xf1,period=100003,umask=4  00    This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects l2_lines_in.i cache L2 cache lines in I state filling L2 event=0xf1,period=100003,umask=1  00    This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects l2_lines_in.s cache L2 cache lines in S state filling L2 event=0xf1,period=100003,umask=2  00    This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects l2_lines_out.demand_clean cache Clean L2 cache lines evicted by demand event=0xf2,period=100003,umask=5  00     l2_rqsts.all_code_rd cache L2 code requests event=0x24,period=200003,umask=0xe4  00    This event counts the total number of L2 code requests l2_rqsts.all_demand_data_rd cache Demand Data Read requests event=0x24,period=200003,umask=0xe1  00    This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted l2_rqsts.all_demand_miss cache Demand requests that miss L2 cache event=0x24,period=200003,umask=0x27  00     l2_rqsts.all_demand_references cache Demand requests to L2 cache event=0x24,period=200003,umask=0xe7  00     l2_rqsts.all_pf cache Requests from L2 hardware prefetchers event=0x24,period=200003,umask=0xf8  00    This event counts the total number of requests from the L2 hardware prefetchers l2_rqsts.all_rfo cache RFO requests to L2 cache event=0x24,period=200003,umask=0xe2  00    This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches l2_rqsts.code_rd_hit cache L2 cache hits when fetching instructions, code reads event=0x24,period=200003,umask=0xc4  00     l2_rqsts.code_rd_miss cache L2 cache misses when fetching instructions event=0x24,period=200003,umask=0x24  00     l2_rqsts.demand_data_rd_hit cache Demand Data Read requests that hit L2 cache event=0x24,period=200003,umask=0xc1  00    Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache l2_rqsts.demand_data_rd_miss cache Demand Data Read miss L2, no rejects event=0x24,period=200003,umask=0x21  00    This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted l2_rqsts.l2_pf_hit cache L2 prefetch requests that hit L2 cache event=0x24,period=200003,umask=0xd0  00    This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types l2_rqsts.l2_pf_miss cache L2 prefetch requests that miss L2 cache event=0x24,period=200003,umask=0x30  00    This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache l2_rqsts.miss cache All requests that miss L2 cache event=0x24,period=200003,umask=0x3f  00     l2_rqsts.references cache All L2 requests event=0x24,period=200003,umask=0xff  00     l2_rqsts.rfo_hit cache RFO requests that hit L2 cache event=0x24,period=200003,umask=0xc2  00     l2_rqsts.rfo_miss cache RFO requests that miss L2 cache event=0x24,period=200003,umask=0x22  00     l2_trans.all_pf cache L2 or L3 HW prefetches that access L2 cache event=0xf0,period=200003,umask=8  00    This event counts L2 or L3 HW prefetches that access L2 cache including rejects l2_trans.all_requests cache Transactions accessing L2 pipe event=0xf0,period=200003,umask=0x80  00    This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on l2_trans.code_rd cache L2 cache accesses when fetching instructions event=0xf0,period=200003,umask=4  00    This event counts the number of L2 cache accesses when fetching instructions l2_trans.demand_data_rd cache Demand Data Read requests that access L2 cache event=0xf0,period=200003,umask=1  00    This event counts Demand Data Read requests that access L2 cache, including rejects l2_trans.l1d_wb cache L1D writebacks that access L2 cache event=0xf0,period=200003,umask=0x10  00    This event counts L1D writebacks that access L2 cache l2_trans.l2_fill cache L2 fill requests that access L2 cache event=0xf0,period=200003,umask=0x20  00    This event counts L2 fill requests that access L2 cache l2_trans.l2_wb cache L2 writebacks that access L2 cache event=0xf0,period=200003,umask=0x40  00    This event counts L2 writebacks that access L2 cache l2_trans.rfo cache RFO requests that access L2 cache event=0xf0,period=200003,umask=2  00    This event counts Read for Ownership (RFO) requests that access L2 cache lock_cycles.cache_lock_duration cache Cycles when L1D is locked event=0x63,period=2000003,umask=2  00    This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION) longest_lat_cache.miss cache Core-originated cacheable demand requests missed L3 event=0x2e,period=100003,umask=0x41  00    This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU longest_lat_cache.reference cache Core-originated cacheable demand requests that refer to L3 event=0x2e,period=100003,umask=0x4f  00    This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU mem_load_uops_l3_hit_retired.xsnp_hit cache Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache  Supports address when precise.  Spec update: BDM100 (Precise event) event=0xd2,period=20011,umask=2  00    This event counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache  Supports address when precise.  Spec update: BDM100 (Precise event) mem_load_uops_l3_hit_retired.xsnp_hitm cache Retired load uops which data sources were HitM responses from shared L3  Supports address when precise.  Spec update: BDM100 (Precise event) event=0xd2,period=20011,umask=4  00    This event counts retired load uops which data sources were HitM responses from a core on same socket (shared L3)  Supports address when precise.  Spec update: BDM100 (Precise event) mem_load_uops_l3_hit_retired.xsnp_miss cache Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache  Supports address when precise.  Spec update: BDM100 (Precise event) event=0xd2,period=20011,umask=1  00    This event counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache  Supports address when precise.  Spec update: BDM100 (Precise event) mem_load_uops_l3_hit_retired.xsnp_none cache Retired load uops which data sources were hits in L3 without snoops required  Supports address when precise.  Spec update: BDM100 (Precise event) event=0xd2,period=100003,umask=8  00    This event counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required  Supports address when precise.  Spec update: BDM100 (Precise event) mem_load_uops_l3_miss_retired.local_dram cache Data from local DRAM either Snoop not needed or Snoop Miss (RspI)  Supports address when precise.  Spec update: BDE70, BDM100 (Precise event) event=0xd3,period=100007,umask=1  00    Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI)  Supports address when precise.  Spec update: BDE70, BDM100 (Precise event) mem_load_uops_retired.hit_lfb cache Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready  Supports address when precise (Precise event) event=0xd1,period=100003,umask=0x40  00    This event counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready. Note: Only two data-sources of L1/FB are applicable for AVX-256bit  even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load  Supports address when precise (Precise event) mem_load_uops_retired.l1_hit cache Retired load uops with L1 cache hits as data sources  Supports address when precise (Precise event) event=0xd1,period=2000003,umask=1  00    This event counts retired load uops which data sources were hits in the nearest-level (L1) cache. Note: Only two data-sources of L1/FB are applicable for AVX-256bit  even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source  Supports address when precise (Precise event) mem_load_uops_retired.l1_miss cache Retired load uops misses in L1 cache as data sources  Supports address when precise (Precise event) event=0xd1,period=100003,umask=8  00    This event counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source  Supports address when precise (Precise event) mem_load_uops_retired.l2_hit cache Retired load uops with L2 cache hits as data sources  Supports address when precise.  Spec update: BDM35 (Precise event) event=0xd1,period=100003,umask=2  00    This event counts retired load uops which data sources were hits in the mid-level (L2) cache  Supports address when precise.  Spec update: BDM35 (Precise event) mem_load_uops_retired.l2_miss cache Miss in mid-level (L2) cache. Excludes Unknown data-source  Supports address when precise (Precise event) event=0xd1,period=50021,umask=0x10  00    This event counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source  Supports address when precise (Precise event) mem_load_uops_retired.l3_hit cache Retired load uops which data sources were data hits in L3 without snoops required  Supports address when precise.  Spec update: BDM100 (Precise event) event=0xd1,period=50021,umask=4  00    This event counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required  Supports address when precise.  Spec update: BDM100 (Precise event) mem_load_uops_retired.l3_miss cache Miss in last-level (L3) cache. Excludes Unknown data-source  Supports address when precise.  Spec update: BDM100, BDE70 (Precise event) event=0xd1,period=100007,umask=0x20  00     mem_uops_retired.all_loads cache Retired load uops  Supports address when precise (Precise event) event=0xd0,period=2000003,umask=0x81  00    Counts all retired load uops. This event accounts for SW prefetch uops of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW  Supports address when precise (Precise event) mem_uops_retired.all_stores cache Retired store uops  Supports address when precise (Precise event) event=0xd0,period=2000003,umask=0x82  00    Counts all retired store uops  Supports address when precise (Precise event) mem_uops_retired.lock_loads cache Retired load uops with locked access  Supports address when precise.  Spec update: BDM35 (Precise event) event=0xd0,period=100007,umask=0x21  00    This event counts load uops with locked access retired to the architected path  Supports address when precise.  Spec update: BDM35 (Precise event) mem_uops_retired.split_loads cache Retired load uops that split across a cacheline boundary  Supports address when precise (Precise event) event=0xd0,period=100003,umask=0x41  00    This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K)  Supports address when precise (Precise event) mem_uops_retired.split_stores cache Retired store uops that split across a cacheline boundary  Supports address when precise (Precise event) event=0xd0,period=100003,umask=0x42  00    This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K)  Supports address when precise (Precise event) mem_uops_retired.stlb_miss_loads cache Retired load uops that miss the STLB  Supports address when precise (Precise event) event=0xd0,period=100003,umask=0x11  00    This event counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault  Supports address when precise (Precise event) mem_uops_retired.stlb_miss_stores cache Retired store uops that miss the STLB  Supports address when precise (Precise event) event=0xd0,period=100003,umask=0x12  00    This event counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault  Supports address when precise (Precise event) offcore_requests.all_data_rd cache Demand and prefetch data reads event=0xb0,period=100003,umask=8  00    This event counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type offcore_requests.all_requests cache Any memory transaction that reached the SQ event=0xb0,period=100003,umask=0x80  00    This event counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, and so on offcore_requests.demand_code_rd cache Cacheable and non-cacheable code read requests event=0xb0,period=100003,umask=2  00    This event counts both cacheable and non-cacheable code read requests offcore_requests.demand_data_rd cache Demand Data Read requests sent to uncore event=0xb0,period=100003,umask=1  00    This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore offcore_requests.demand_rfo cache Demand RFO requests including regular RFOs, locks, ItoM event=0xb0,period=100003,umask=4  00    This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM offcore_requests_buffer.sq_full cache Offcore requests buffer cannot take more entries for this thread core event=0xb2,period=2000003,umask=1  00    This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full. Note: Writeback pending FIFO has six entries offcore_requests_outstanding.all_data_rd cache Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore  Spec update: BDM76 event=0x60,period=2000003,umask=8  00    This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS  Spec update: BDM76 offcore_requests_outstanding.cycles_with_data_rd cache Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore  Spec update: BDM76 event=0x60,cmask=1,period=2000003,umask=8  00    This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS  Spec update: BDM76 offcore_requests_outstanding.cycles_with_demand_data_rd cache Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore  Spec update: BDM76 event=0x60,cmask=1,period=2000003,umask=1  00    This event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation)  Spec update: BDM76 offcore_requests_outstanding.cycles_with_demand_rfo cache Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle  Spec update: BDM76 event=0x60,cmask=1,period=2000003,umask=4  00    This event counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS  Spec update: BDM76 offcore_requests_outstanding.demand_code_rd cache Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle  Spec update: BDM76 event=0x60,period=2000003,umask=2  00    This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS  Spec update: BDM76 offcore_requests_outstanding.demand_data_rd cache Offcore outstanding Demand Data Read transactions in uncore queue  Spec update: BDM76 event=0x60,period=2000003,umask=1  00    This event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS. Note: A prefetch promoted to Demand is counted from the promotion point  Spec update: BDM76 offcore_requests_outstanding.demand_data_rd_ge_6 cache Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue  Spec update: BDM76 event=0x60,cmask=6,period=2000003,umask=1  00     offcore_requests_outstanding.demand_rfo cache Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore  Spec update: BDM76 event=0x60,period=2000003,umask=4  00    This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS  Spec update: BDM76 offcore_response cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction event=0xb7,period=100003,umask=1  00     offcore_response.all_data_rd.any_response cache Counts all demand & prefetch data reads have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10091  00     offcore_response.all_data_rd.l3_hit.any_snoop cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0091  00     offcore_response.all_data_rd.l3_hit.snoop_hitm cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0091  00     offcore_response.all_data_rd.l3_hit.snoop_hit_no_fwd cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0091  00     offcore_response.all_data_rd.l3_hit.snoop_miss cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0091  00     offcore_response.all_data_rd.l3_hit.snoop_none cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0091  00     offcore_response.all_data_rd.l3_hit.snoop_not_needed cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0091  00     offcore_response.all_data_rd.supplier_none.any_snoop cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020091  00     offcore_response.all_data_rd.supplier_none.snoop_hitm cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020091  00     offcore_response.all_data_rd.supplier_none.snoop_hit_no_fwd cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400020091  00     offcore_response.all_data_rd.supplier_none.snoop_miss cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200020091  00     offcore_response.all_data_rd.supplier_none.snoop_none cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80020091  00     offcore_response.all_data_rd.supplier_none.snoop_not_needed cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100020091  00     offcore_response.all_pf_code_rd.any_response cache Counts all prefetch code reads have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10240  00     offcore_response.all_pf_code_rd.l3_hit.any_snoop cache Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0240  00     offcore_response.all_pf_code_rd.l3_hit.snoop_hitm cache Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0240  00     offcore_response.all_pf_code_rd.l3_hit.snoop_hit_no_fwd cache Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0240  00     offcore_response.all_pf_code_rd.l3_hit.snoop_miss cache Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0240  00     offcore_response.all_pf_code_rd.l3_hit.snoop_none cache Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0240  00     offcore_response.all_pf_code_rd.l3_hit.snoop_not_needed cache Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0240  00     offcore_response.all_pf_code_rd.supplier_none.any_snoop cache Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020240  00     offcore_response.all_pf_code_rd.supplier_none.snoop_hitm cache Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020240  00     offcore_response.all_pf_code_rd.supplier_none.snoop_hit_no_fwd cache Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400020240  00     offcore_response.all_pf_code_rd.supplier_none.snoop_miss cache Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200020240  00     offcore_response.all_pf_code_rd.supplier_none.snoop_none cache Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80020240  00     offcore_response.all_pf_code_rd.supplier_none.snoop_not_needed cache Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100020240  00     offcore_response.all_pf_data_rd.any_response cache Counts all prefetch data reads have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10090  00     offcore_response.all_pf_data_rd.l3_hit.any_snoop cache Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0090  00     offcore_response.all_pf_data_rd.l3_hit.snoop_hitm cache Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0090  00     offcore_response.all_pf_data_rd.l3_hit.snoop_hit_no_fwd cache Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0090  00     offcore_response.all_pf_data_rd.l3_hit.snoop_miss cache Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0090  00     offcore_response.all_pf_data_rd.l3_hit.snoop_none cache Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0090  00     offcore_response.all_pf_data_rd.l3_hit.snoop_not_needed cache Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0090  00     offcore_response.all_pf_data_rd.supplier_none.any_snoop cache Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020090  00     offcore_response.all_pf_data_rd.supplier_none.snoop_hitm cache Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020090  00     offcore_response.all_pf_data_rd.supplier_none.snoop_hit_no_fwd cache Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400020090  00     offcore_response.all_pf_data_rd.supplier_none.snoop_miss cache Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200020090  00     offcore_response.all_pf_data_rd.supplier_none.snoop_none cache Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80020090  00     offcore_response.all_pf_data_rd.supplier_none.snoop_not_needed cache Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100020090  00     offcore_response.all_pf_rfo.any_response cache Counts prefetch RFOs have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10120  00     offcore_response.all_pf_rfo.l3_hit.any_snoop cache Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0120  00     offcore_response.all_pf_rfo.l3_hit.snoop_hitm cache Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0120  00     offcore_response.all_pf_rfo.l3_hit.snoop_hit_no_fwd cache Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0120  00     offcore_response.all_pf_rfo.l3_hit.snoop_miss cache Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0120  00     offcore_response.all_pf_rfo.l3_hit.snoop_none cache Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0120  00     offcore_response.all_pf_rfo.l3_hit.snoop_not_needed cache Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0120  00     offcore_response.all_pf_rfo.supplier_none.any_snoop cache Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020120  00     offcore_response.all_pf_rfo.supplier_none.snoop_hitm cache Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020120  00     offcore_response.all_pf_rfo.supplier_none.snoop_hit_no_fwd cache Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x400020120  00     offcore_response.all_pf_rfo.supplier_none.snoop_miss cache Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x200020120  00     offcore_response.all_pf_rfo.supplier_none.snoop_none cache Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x80020120  00     offcore_response.all_pf_rfo.supplier_none.snoop_not_needed cache Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x100020120  00     offcore_response.all_rfo.any_response cache Counts all demand & prefetch RFOs have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10122  00     offcore_response.all_rfo.l3_hit.any_snoop cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0122  00     offcore_response.all_rfo.l3_hit.snoop_hitm cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0122  00     offcore_response.all_rfo.l3_hit.snoop_hit_no_fwd cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0122  00     offcore_response.all_rfo.l3_hit.snoop_miss cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0122  00     offcore_response.all_rfo.l3_hit.snoop_none cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0122  00     offcore_response.all_rfo.l3_hit.snoop_not_needed cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0122  00     offcore_response.all_rfo.supplier_none.any_snoop cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020122  00     offcore_response.all_rfo.supplier_none.snoop_hitm cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020122  00     offcore_response.all_rfo.supplier_none.snoop_hit_no_fwd cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x400020122  00     offcore_response.all_rfo.supplier_none.snoop_miss cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x200020122  00     offcore_response.all_rfo.supplier_none.snoop_none cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x80020122  00     offcore_response.all_rfo.supplier_none.snoop_not_needed cache Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x100020122  00     offcore_response.corewb.any_response cache Counts writebacks (modified to exclusive) have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10008  00     offcore_response.corewb.l3_hit.any_snoop cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0008  00     offcore_response.corewb.l3_hit.snoop_hitm cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0008  00     offcore_response.corewb.l3_hit.snoop_hit_no_fwd cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0008  00     offcore_response.corewb.l3_hit.snoop_miss cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0008  00     offcore_response.corewb.l3_hit.snoop_none cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0008  00     offcore_response.corewb.l3_hit.snoop_not_needed cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0008  00     offcore_response.corewb.supplier_none.any_snoop cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020008  00     offcore_response.corewb.supplier_none.snoop_hitm cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020008  00     offcore_response.corewb.supplier_none.snoop_hit_no_fwd cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x400020008  00     offcore_response.corewb.supplier_none.snoop_miss cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x200020008  00     offcore_response.corewb.supplier_none.snoop_none cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x80020008  00     offcore_response.corewb.supplier_none.snoop_not_needed cache Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x100020008  00     offcore_response.demand_code_rd.any_response cache Counts all demand code reads have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10004  00     offcore_response.demand_code_rd.l3_hit.any_snoop cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0004  00     offcore_response.demand_code_rd.l3_hit.snoop_hitm cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0004  00     offcore_response.demand_code_rd.l3_hit.snoop_hit_no_fwd cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0004  00     offcore_response.demand_code_rd.l3_hit.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0004  00     offcore_response.demand_code_rd.l3_hit.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0004  00     offcore_response.demand_code_rd.l3_hit.snoop_not_needed cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0004  00     offcore_response.demand_code_rd.supplier_none.any_snoop cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020004  00     offcore_response.demand_code_rd.supplier_none.snoop_hitm cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020004  00     offcore_response.demand_code_rd.supplier_none.snoop_hit_no_fwd cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400020004  00     offcore_response.demand_code_rd.supplier_none.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200020004  00     offcore_response.demand_code_rd.supplier_none.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80020004  00     offcore_response.demand_code_rd.supplier_none.snoop_not_needed cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100020004  00     offcore_response.demand_data_rd.any_response cache Counts demand data reads have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10001  00     offcore_response.demand_data_rd.l3_hit.any_snoop cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0001  00     offcore_response.demand_data_rd.l3_hit.snoop_hitm cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0001  00     offcore_response.demand_data_rd.l3_hit.snoop_hit_no_fwd cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0001  00     offcore_response.demand_data_rd.l3_hit.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0001  00     offcore_response.demand_data_rd.l3_hit.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0001  00     offcore_response.demand_data_rd.l3_hit.snoop_not_needed cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0001  00     offcore_response.demand_data_rd.supplier_none.any_snoop cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020001  00     offcore_response.demand_data_rd.supplier_none.snoop_hitm cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020001  00     offcore_response.demand_data_rd.supplier_none.snoop_hit_no_fwd cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400020001  00     offcore_response.demand_data_rd.supplier_none.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200020001  00     offcore_response.demand_data_rd.supplier_none.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80020001  00     offcore_response.demand_data_rd.supplier_none.snoop_not_needed cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100020001  00     offcore_response.demand_rfo.any_response cache Counts all demand data writes (RFOs) have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10002  00     offcore_response.demand_rfo.l3_hit.any_snoop cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0002  00     offcore_response.demand_rfo.l3_hit.snoop_hitm cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0002  00     offcore_response.demand_rfo.l3_hit.snoop_hit_no_fwd cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0002  00     offcore_response.demand_rfo.l3_hit.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0002  00     offcore_response.demand_rfo.l3_hit.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0002  00     offcore_response.demand_rfo.l3_hit.snoop_not_needed cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0002  00     offcore_response.other.any_response cache Counts any other requests have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x18000  00     offcore_response.other.l3_hit.any_snoop cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C8000  00     offcore_response.other.l3_hit.snoop_hitm cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C8000  00     offcore_response.other.l3_hit.snoop_hit_no_fwd cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C8000  00     offcore_response.other.l3_hit.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C8000  00     offcore_response.other.l3_hit.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x803C8000  00     offcore_response.other.l3_hit.snoop_not_needed cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C8000  00     offcore_response.other.supplier_none.any_snoop cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80028000  00     offcore_response.other.supplier_none.snoop_hitm cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x1000028000  00     offcore_response.other.supplier_none.snoop_hit_no_fwd cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x400028000  00     offcore_response.other.supplier_none.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x200028000  00     offcore_response.other.supplier_none.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x80028000  00     offcore_response.other.supplier_none.snoop_not_needed cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x100028000  00     offcore_response.pf_l2_code_rd.any_response cache Counts all prefetch (that bring data to LLC only) code reads have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10040  00     offcore_response.pf_l2_code_rd.l3_hit.any_snoop cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0040  00     offcore_response.pf_l2_code_rd.l3_hit.snoop_hitm cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0040  00     offcore_response.pf_l2_code_rd.l3_hit.snoop_hit_no_fwd cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0040  00     offcore_response.pf_l2_code_rd.l3_hit.snoop_miss cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0040  00     offcore_response.pf_l2_code_rd.l3_hit.snoop_none cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0040  00     offcore_response.pf_l2_code_rd.l3_hit.snoop_not_needed cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0040  00     offcore_response.pf_l2_code_rd.supplier_none.any_snoop cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020040  00     offcore_response.pf_l2_code_rd.supplier_none.snoop_hitm cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020040  00     offcore_response.pf_l2_code_rd.supplier_none.snoop_hit_no_fwd cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400020040  00     offcore_response.pf_l2_code_rd.supplier_none.snoop_miss cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200020040  00     offcore_response.pf_l2_code_rd.supplier_none.snoop_none cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80020040  00     offcore_response.pf_l2_code_rd.supplier_none.snoop_not_needed cache Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100020040  00     offcore_response.pf_l2_data_rd.any_response cache Counts prefetch (that bring data to L2) data reads have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10010  00     offcore_response.pf_l2_data_rd.l3_hit.any_snoop cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0010  00     offcore_response.pf_l2_data_rd.l3_hit.snoop_hitm cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0010  00     offcore_response.pf_l2_data_rd.l3_hit.snoop_hit_no_fwd cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0010  00     offcore_response.pf_l2_data_rd.l3_hit.snoop_miss cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0010  00     offcore_response.pf_l2_data_rd.l3_hit.snoop_none cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0010  00     offcore_response.pf_l2_data_rd.l3_hit.snoop_not_needed cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0010  00     offcore_response.pf_l2_data_rd.supplier_none.any_snoop cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020010  00     offcore_response.pf_l2_data_rd.supplier_none.snoop_hitm cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020010  00     offcore_response.pf_l2_data_rd.supplier_none.snoop_hit_no_fwd cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400020010  00     offcore_response.pf_l2_data_rd.supplier_none.snoop_miss cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200020010  00     offcore_response.pf_l2_data_rd.supplier_none.snoop_none cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80020010  00     offcore_response.pf_l2_data_rd.supplier_none.snoop_not_needed cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100020010  00     offcore_response.pf_l2_rfo.any_response cache Counts all prefetch (that bring data to L2) RFOs have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10020  00     offcore_response.pf_l2_rfo.l3_hit.any_snoop cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0020  00     offcore_response.pf_l2_rfo.l3_hit.snoop_hitm cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0020  00     offcore_response.pf_l2_rfo.l3_hit.snoop_hit_no_fwd cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0020  00     offcore_response.pf_l2_rfo.l3_hit.snoop_miss cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0020  00     offcore_response.pf_l2_rfo.l3_hit.snoop_none cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0020  00     offcore_response.pf_l2_rfo.l3_hit.snoop_not_needed cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0020  00     offcore_response.pf_l2_rfo.supplier_none.any_snoop cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020020  00     offcore_response.pf_l2_rfo.supplier_none.snoop_hitm cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020020  00     offcore_response.pf_l2_rfo.supplier_none.snoop_hit_no_fwd cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x400020020  00     offcore_response.pf_l2_rfo.supplier_none.snoop_miss cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x200020020  00     offcore_response.pf_l2_rfo.supplier_none.snoop_none cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x80020020  00     offcore_response.pf_l2_rfo.supplier_none.snoop_not_needed cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x100020020  00     offcore_response.pf_l3_code_rd.any_response cache Counts prefetch (that bring data to LLC only) code reads have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10200  00     offcore_response.pf_l3_code_rd.l3_hit.any_snoop cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0200  00     offcore_response.pf_l3_code_rd.l3_hit.snoop_hitm cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0200  00     offcore_response.pf_l3_code_rd.l3_hit.snoop_hit_no_fwd cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0200  00     offcore_response.pf_l3_code_rd.l3_hit.snoop_miss cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0200  00     offcore_response.pf_l3_code_rd.l3_hit.snoop_none cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0200  00     offcore_response.pf_l3_code_rd.l3_hit.snoop_not_needed cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0200  00     offcore_response.pf_l3_code_rd.supplier_none.any_snoop cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020200  00     offcore_response.pf_l3_code_rd.supplier_none.snoop_hitm cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020200  00     offcore_response.pf_l3_code_rd.supplier_none.snoop_hit_no_fwd cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400020200  00     offcore_response.pf_l3_code_rd.supplier_none.snoop_miss cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200020200  00     offcore_response.pf_l3_code_rd.supplier_none.snoop_none cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80020200  00     offcore_response.pf_l3_code_rd.supplier_none.snoop_not_needed cache Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100020200  00     offcore_response.pf_l3_data_rd.any_response cache Counts all prefetch (that bring data to LLC only) data reads have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10080  00     offcore_response.pf_l3_data_rd.l3_hit.any_snoop cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0080  00     offcore_response.pf_l3_data_rd.l3_hit.snoop_hitm cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0080  00     offcore_response.pf_l3_data_rd.l3_hit.snoop_hit_no_fwd cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0080  00     offcore_response.pf_l3_data_rd.l3_hit.snoop_miss cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0080  00     offcore_response.pf_l3_data_rd.l3_hit.snoop_none cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0080  00     offcore_response.pf_l3_data_rd.l3_hit.snoop_not_needed cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0080  00     offcore_response.pf_l3_data_rd.supplier_none.any_snoop cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020080  00     offcore_response.pf_l3_data_rd.supplier_none.snoop_hitm cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020080  00     offcore_response.pf_l3_data_rd.supplier_none.snoop_hit_no_fwd cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400020080  00     offcore_response.pf_l3_data_rd.supplier_none.snoop_miss cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200020080  00     offcore_response.pf_l3_data_rd.supplier_none.snoop_none cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80020080  00     offcore_response.pf_l3_data_rd.supplier_none.snoop_not_needed cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100020080  00     offcore_response.pf_l3_rfo.any_response cache Counts all prefetch (that bring data to LLC only) RFOs have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10100  00     offcore_response.pf_l3_rfo.l3_hit.any_snoop cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0100  00     offcore_response.pf_l3_rfo.l3_hit.snoop_hitm cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0100  00     offcore_response.pf_l3_rfo.l3_hit.snoop_hit_no_fwd cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0100  00     offcore_response.pf_l3_rfo.l3_hit.snoop_miss cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0100  00     offcore_response.pf_l3_rfo.l3_hit.snoop_none cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0100  00     offcore_response.pf_l3_rfo.l3_hit.snoop_not_needed cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0100  00     offcore_response.pf_l3_rfo.supplier_none.any_snoop cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020100  00     offcore_response.pf_l3_rfo.supplier_none.snoop_hitm cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020100  00     offcore_response.pf_l3_rfo.supplier_none.snoop_hit_no_fwd cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x400020100  00     offcore_response.pf_l3_rfo.supplier_none.snoop_miss cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x200020100  00     offcore_response.pf_l3_rfo.supplier_none.snoop_none cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x80020100  00     offcore_response.pf_l3_rfo.supplier_none.snoop_not_needed cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x100020100  00     sq_misc.split_lock cache Split locks in SQ event=0xf4,period=100003,umask=0x10  00    This event counts the number of split locks in the super queue fp_arith_inst_retired.128b_packed_double floating point Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=2000003,umask=4  00    Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.128b_packed_single floating point Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element event=0xc7,period=2000003,umask=8  00    Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.256b_packed_double floating point Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element event=0xc7,period=2000003,umask=0x10  00    Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.256b_packed_single floating point Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element event=0xc7,period=2000003,umask=0x20  00    Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.4_flops floating point Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below.  Each count represents 2 or/and 4 computation operations, 1 for each element.  Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element event=0xc7,period=2000003,umask=0x18  00    Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision  floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 or/and 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.double floating point Number of SSE/AVX computational double precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element event=0xc7,period=2000006,umask=0x15  00     fp_arith_inst_retired.packed floating point Number of SSE/AVX computational packed floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* packed double and single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element event=0xc7,period=2000004,umask=0x3c  00     fp_arith_inst_retired.scalar floating point Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation operation.   Applies to SSE* and AVX* scalar double and single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element event=0xc7,period=2000003,umask=3  00    Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.scalar_double floating point Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element event=0xc7,period=2000003,umask=1  00    Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.scalar_single floating point Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element event=0xc7,period=2000003,umask=2  00    Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.single floating point Number of SSE/AVX computational single precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element event=0xc7,period=2000005,umask=0x2a  00     fp_arith_inst_retired.vector floating point Number of any Vector retired FP arithmetic instructions event=0xc7,period=2000003,umask=0xfc  00     fp_assist.any floating point Cycles with any input/output SSE or FP assist event=0xca,cmask=1,period=100003,umask=0x1e  00    This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1 fp_assist.simd_input floating point Number of SIMD FP assists due to input values event=0xca,period=100003,umask=0x10  00    This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention fp_assist.simd_output floating point Number of SIMD FP assists due to Output values event=0xca,period=100003,umask=8  00    This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention fp_assist.x87_input floating point Number of X87 assists due to input value event=0xca,period=100003,umask=4  00    This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid fp_assist.x87_output floating point Number of X87 assists due to output value event=0xca,period=100003,umask=2  00    This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid move_elimination.simd_eliminated floating point Number of SIMD Move Elimination candidate uops that were eliminated event=0x58,period=1000003,umask=2  00     move_elimination.simd_not_eliminated floating point Number of SIMD Move Elimination candidate uops that were not eliminated event=0x58,period=1000003,umask=8  00     other_assists.avx_to_sse floating point Number of transitions from AVX-256 to legacy SSE when penalty applicable  Spec update: BDM30 event=0xc1,period=100003,umask=8  00    This event counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable  Spec update: BDM30 other_assists.sse_to_avx floating point Number of transitions from SSE to AVX-256 when penalty applicable  Spec update: BDM30 event=0xc1,period=100003,umask=0x10  00    This event counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable  Spec update: BDM30 uop_dispatches_cancelled.simd_prf floating point Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports event=0xa0,period=2000003,umask=3  00    This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file.  The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*.  See the Broadwell Optimization Guide for more information baclears.any frontend Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end event=0xe6,period=100003,umask=0x1f  00     dsb2mite_switches.penalty_cycles frontend Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles event=0xab,period=2000003,umask=2  00    This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop.  MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs. Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles icache.hit frontend Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches event=0x80,period=2000003,umask=1  00    This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches icache.ifdata_stall frontend Cycles where a code fetch is stalled due to L1 instruction-cache miss event=0x80,period=2000003,umask=4  00    This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit) icache.misses frontend Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses event=0x80,period=200003,umask=2  00    This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses idq.all_dsb_cycles_4_uops frontend Cycles Decode Stream Buffer (DSB) is delivering 4 Uops event=0x79,cmask=4,period=2000003,umask=0x18  00    This event counts the number of cycles 4  uops were  delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ idq.all_dsb_cycles_any_uops frontend Cycles Decode Stream Buffer (DSB) is delivering any Uop event=0x79,cmask=1,period=2000003,umask=0x18  00    This event counts the number of cycles  uops were  delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ idq.all_mite_cycles_4_uops frontend Cycles MITE is delivering 4 Uops event=0x79,cmask=4,period=2000003,umask=0x24  00    This event counts the number of cycles 4  uops were  delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) idq.all_mite_cycles_any_uops frontend Cycles MITE is delivering any Uop event=0x79,cmask=1,period=2000003,umask=0x24  00    This event counts the number of cycles  uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) idq.dsb_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path event=0x79,cmask=1,period=2000003,umask=8  00    This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ idq.dsb_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path event=0x79,period=2000003,umask=8  00    This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ idq.empty frontend Instruction Decode Queue (IDQ) empty cycles event=0x79,period=2000003,umask=2  00    This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end.  It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty idq.mite_all_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,period=2000003,umask=0x3c  00    This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) idq.mite_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,cmask=1,period=2000003,umask=4  00    This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ idq.mite_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,period=2000003,umask=4  00    This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) idq.ms_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,period=2000003,umask=0x30  00    This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE idq.ms_dsb_cycles frontend Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,period=2000003,umask=0x10  00    This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ idq.ms_dsb_occur frontend Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,edge=1,period=2000003,umask=0x10  00    This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ idq.ms_dsb_uops frontend Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x10  00    This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ idq.ms_mite_uops frontend Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x20  00    This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ idq.ms_switches frontend Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer event=0x79,cmask=1,edge=1,period=2000003,umask=0x30  00     idq.ms_uops frontend Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x30  00    This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE idq_uops_not_delivered.core frontend Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled event=0x9c,period=2000003,umask=1  00    This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4  x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:  a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;  b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions);   c. Instruction Decode Queue (IDQ) delivers four uops idq_uops_not_delivered.cycles_0_uops_deliv.core frontend Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled event=0x9c,cmask=4,period=2000003,umask=1  00    This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4 idq_uops_not_delivered.cycles_fe_was_ok frontend Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE event=0x9c,cmask=1,inv=1,period=2000003,umask=1  00     idq_uops_not_delivered.cycles_le_1_uop_deliv.core frontend Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled event=0x9c,cmask=3,period=2000003,umask=1  00    This event counts, on the per-thread basis, cycles when less than 1 uop is  delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3 idq_uops_not_delivered.cycles_le_2_uop_deliv.core frontend Cycles with less than 2 uops delivered by the front end event=0x9c,cmask=2,period=2000003,umask=1  00     idq_uops_not_delivered.cycles_le_3_uop_deliv.core frontend Cycles with less than 3 uops delivered by the front end event=0x9c,cmask=1,period=2000003,umask=1  00     hle_retired.aborted memory Number of times HLE abort was triggered (Precise event) event=0xc8,period=2000003,umask=4  00     hle_retired.aborted_misc1 memory Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts) event=0xc8,period=2000003,umask=8  00    Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details) hle_retired.aborted_misc2 memory Number of times an HLE execution aborted due to uncommon conditions event=0xc8,period=2000003,umask=0x10  00    Number of times the TSX watchdog signaled an HLE abort hle_retired.aborted_misc3 memory Number of times an HLE execution aborted due to HLE-unfriendly instructions event=0xc8,period=2000003,umask=0x20  00    Number of times a disallowed operation caused an HLE abort hle_retired.aborted_misc4 memory Number of times an HLE execution aborted due to incompatible memory type event=0xc8,period=2000003,umask=0x40  00    Number of times HLE caused a fault hle_retired.aborted_misc5 memory Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts) event=0xc8,period=2000003,umask=0x80  00    Number of times HLE aborted and was not due to the abort conditions in subevents 3-6 hle_retired.commit memory Number of times HLE commit succeeded event=0xc8,period=2000003,umask=2  00     hle_retired.start memory Number of times we entered an HLE region; does not count nested transactions event=0xc8,period=2000003,umask=1  00    Number of times we entered an HLE region  does not count nested transactions machine_clears.memory_ordering memory Counts the number of machine clears due to memory order conflicts event=0xc3,period=100003,umask=2  00    This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following: 1. memory disambiguation, 2. external snoop, or 3. cross SMT-HW-thread snoop (stores) hitting load buffer mem_trans_retired.load_latency_gt_128 memory Randomly selected loads with latency value being above 128  Supports address when precise.  Spec update: BDM100, BDM35 (Must be precise) event=0xcd,period=1009,umask=1,ldlat=0x80  00    Counts randomly selected loads with latency value being above 128  Supports address when precise.  Spec update: BDM100, BDM35 (Must be precise) mem_trans_retired.load_latency_gt_16 memory Randomly selected loads with latency value being above 16  Supports address when precise.  Spec update: BDM100, BDM35 (Must be precise) event=0xcd,period=20011,umask=1,ldlat=0x10  00    Counts randomly selected loads with latency value being above 16  Supports address when precise.  Spec update: BDM100, BDM35 (Must be precise) mem_trans_retired.load_latency_gt_256 memory Randomly selected loads with latency value being above 256  Supports address when precise.  Spec update: BDM100, BDM35 (Must be precise) event=0xcd,period=503,umask=1,ldlat=0x100  00    Counts randomly selected loads with latency value being above 256  Supports address when precise.  Spec update: BDM100, BDM35 (Must be precise) mem_trans_retired.load_latency_gt_32 memory Randomly selected loads with latency value being above 32  Supports address when precise.  Spec update: BDM100, BDM35 (Must be precise) event=0xcd,period=100007,umask=1,ldlat=0x20  00    Counts randomly selected loads with latency value being above 32  Supports address when precise.  Spec update: BDM100, BDM35 (Must be precise) mem_trans_retired.load_latency_gt_4 memory Randomly selected loads with latency value being above 4  Supports address when precise.  Spec update: BDM100, BDM35 (Must be precise) event=0xcd,period=100003,umask=1,ldlat=0x4  00    Counts randomly selected loads with latency value being above four  Supports address when precise.  Spec update: BDM100, BDM35 (Must be precise) mem_trans_retired.load_latency_gt_512 memory Randomly selected loads with latency value being above 512  Supports address when precise.  Spec update: BDM100, BDM35 (Must be precise) event=0xcd,period=101,umask=1,ldlat=0x200  00    Counts randomly selected loads with latency value being above 512  Supports address when precise.  Spec update: BDM100, BDM35 (Must be precise) mem_trans_retired.load_latency_gt_64 memory Randomly selected loads with latency value being above 64  Supports address when precise.  Spec update: BDM100, BDM35 (Must be precise) event=0xcd,period=2003,umask=1,ldlat=0x40  00    Counts randomly selected loads with latency value being above 64  Supports address when precise.  Spec update: BDM100, BDM35 (Must be precise) mem_trans_retired.load_latency_gt_8 memory Randomly selected loads with latency value being above 8  Supports address when precise.  Spec update: BDM100, BDM35 (Must be precise) event=0xcd,period=50021,umask=1,ldlat=0x8  00    Counts randomly selected loads with latency value being above eight  Supports address when precise.  Spec update: BDM100, BDM35 (Must be precise) misalign_mem_ref.loads memory Speculative cache line split load uops dispatched to L1 cache event=5,period=2000003,umask=1  00    This event counts speculative cache-line split load uops dispatched to the L1 cache misalign_mem_ref.stores memory Speculative cache line split STA uops dispatched to L1 cache event=5,period=2000003,umask=2  00    This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache offcore_response.all_data_rd.l3_hit.snoop_non_dram memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x20003C0091  00     offcore_response.all_data_rd.l3_miss.snoop_hit_no_fwd memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000091  00     offcore_response.all_data_rd.l3_miss.snoop_miss memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000091  00     offcore_response.all_data_rd.l3_miss.snoop_none memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000091  00     offcore_response.all_data_rd.l3_miss.snoop_not_needed memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000091  00     offcore_response.all_data_rd.l3_miss_local_dram.any_snoop memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000091  00     offcore_response.all_data_rd.l3_miss_local_dram.snoop_hitm memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000091  00     offcore_response.all_data_rd.l3_miss_local_dram.snoop_hit_no_fwd memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x404000091  00     offcore_response.all_data_rd.l3_miss_local_dram.snoop_miss memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x204000091  00     offcore_response.all_data_rd.l3_miss_local_dram.snoop_none memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x84000091  00     offcore_response.all_data_rd.l3_miss_local_dram.snoop_non_dram memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2004000091  00     offcore_response.all_data_rd.l3_miss_local_dram.snoop_not_needed memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x104000091  00     offcore_response.all_data_rd.supplier_none.snoop_non_dram memory Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000020091  00     offcore_response.all_pf_code_rd.l3_hit.snoop_non_dram memory Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x20003C0240  00     offcore_response.all_pf_code_rd.l3_miss.snoop_hit_no_fwd memory Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000240  00     offcore_response.all_pf_code_rd.l3_miss.snoop_miss memory Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000240  00     offcore_response.all_pf_code_rd.l3_miss.snoop_none memory Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000240  00     offcore_response.all_pf_code_rd.l3_miss.snoop_not_needed memory Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000240  00     offcore_response.all_pf_code_rd.l3_miss_local_dram.any_snoop memory Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000240  00     offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_hitm memory Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000240  00     offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_hit_no_fwd memory Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x404000240  00     offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_miss memory Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x204000240  00     offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_none memory Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x84000240  00     offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_non_dram memory Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2004000240  00     offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_not_needed memory Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x104000240  00     offcore_response.all_pf_code_rd.supplier_none.snoop_non_dram memory Counts all prefetch code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000020240  00     offcore_response.all_pf_data_rd.l3_hit.snoop_non_dram memory Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x20003C0090  00     offcore_response.all_pf_data_rd.l3_miss.snoop_hit_no_fwd memory Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000090  00     offcore_response.all_pf_data_rd.l3_miss.snoop_miss memory Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000090  00     offcore_response.all_pf_data_rd.l3_miss.snoop_none memory Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000090  00     offcore_response.all_pf_data_rd.l3_miss.snoop_not_needed memory Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000090  00     offcore_response.all_pf_data_rd.l3_miss_local_dram.any_snoop memory Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000090  00     offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_hitm memory Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000090  00     offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_hit_no_fwd memory Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x404000090  00     offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_miss memory Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x204000090  00     offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_none memory Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x84000090  00     offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_non_dram memory Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2004000090  00     offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_not_needed memory Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x104000090  00     offcore_response.all_pf_data_rd.supplier_none.snoop_non_dram memory Counts all prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000020090  00     offcore_response.all_pf_rfo.l3_hit.snoop_non_dram memory Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x20003C0120  00     offcore_response.all_pf_rfo.l3_miss.snoop_hit_no_fwd memory Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000120  00     offcore_response.all_pf_rfo.l3_miss.snoop_miss memory Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000120  00     offcore_response.all_pf_rfo.l3_miss.snoop_none memory Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000120  00     offcore_response.all_pf_rfo.l3_miss.snoop_not_needed memory Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000120  00     offcore_response.all_pf_rfo.l3_miss_local_dram.any_snoop memory Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000120  00     offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_hitm memory Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000120  00     offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_hit_no_fwd memory Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x404000120  00     offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_miss memory Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x204000120  00     offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_none memory Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x84000120  00     offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_non_dram memory Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x2004000120  00     offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_not_needed memory Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x104000120  00     offcore_response.all_pf_rfo.supplier_none.snoop_non_dram memory Counts prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x2000020120  00     offcore_response.all_rfo.l3_hit.snoop_non_dram memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x20003C0122  00     offcore_response.all_rfo.l3_miss.snoop_hit_no_fwd memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000122  00     offcore_response.all_rfo.l3_miss.snoop_miss memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000122  00     offcore_response.all_rfo.l3_miss.snoop_none memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000122  00     offcore_response.all_rfo.l3_miss.snoop_not_needed memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000122  00     offcore_response.all_rfo.l3_miss_local_dram.any_snoop memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000122  00     offcore_response.all_rfo.l3_miss_local_dram.snoop_hitm memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000122  00     offcore_response.all_rfo.l3_miss_local_dram.snoop_hit_no_fwd memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x404000122  00     offcore_response.all_rfo.l3_miss_local_dram.snoop_miss memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x204000122  00     offcore_response.all_rfo.l3_miss_local_dram.snoop_none memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x84000122  00     offcore_response.all_rfo.l3_miss_local_dram.snoop_non_dram memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x2004000122  00     offcore_response.all_rfo.l3_miss_local_dram.snoop_not_needed memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x104000122  00     offcore_response.all_rfo.supplier_none.snoop_non_dram memory Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x2000020122  00     offcore_response.corewb.l3_hit.snoop_non_dram memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x20003C0008  00     offcore_response.corewb.l3_miss.snoop_hit_no_fwd memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000008  00     offcore_response.corewb.l3_miss.snoop_miss memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000008  00     offcore_response.corewb.l3_miss.snoop_none memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000008  00     offcore_response.corewb.l3_miss.snoop_not_needed memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000008  00     offcore_response.corewb.l3_miss_local_dram.any_snoop memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000008  00     offcore_response.corewb.l3_miss_local_dram.snoop_hitm memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000008  00     offcore_response.corewb.l3_miss_local_dram.snoop_hit_no_fwd memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x404000008  00     offcore_response.corewb.l3_miss_local_dram.snoop_miss memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x204000008  00     offcore_response.corewb.l3_miss_local_dram.snoop_none memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x84000008  00     offcore_response.corewb.l3_miss_local_dram.snoop_non_dram memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x2004000008  00     offcore_response.corewb.l3_miss_local_dram.snoop_not_needed memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x104000008  00     offcore_response.corewb.supplier_none.snoop_non_dram memory Counts writebacks (modified to exclusive) event=0xb7,period=100003,umask=1,offcore_rsp=0x2000020008  00     offcore_response.demand_code_rd.l3_hit.snoop_non_dram memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x20003C0004  00     offcore_response.demand_code_rd.l3_miss.snoop_hit_no_fwd memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000004  00     offcore_response.demand_code_rd.l3_miss.snoop_miss memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000004  00     offcore_response.demand_code_rd.l3_miss.snoop_none memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000004  00     offcore_response.demand_code_rd.l3_miss.snoop_not_needed memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000004  00     offcore_response.demand_code_rd.l3_miss_local_dram.any_snoop memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000004  00     offcore_response.demand_code_rd.l3_miss_local_dram.snoop_hitm memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000004  00     offcore_response.demand_code_rd.l3_miss_local_dram.snoop_hit_no_fwd memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x404000004  00     offcore_response.demand_code_rd.l3_miss_local_dram.snoop_miss memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x204000004  00     offcore_response.demand_code_rd.l3_miss_local_dram.snoop_none memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x84000004  00     offcore_response.demand_code_rd.l3_miss_local_dram.snoop_non_dram memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2004000004  00     offcore_response.demand_code_rd.l3_miss_local_dram.snoop_not_needed memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x104000004  00     offcore_response.demand_code_rd.supplier_none.snoop_non_dram memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000020004  00     offcore_response.demand_data_rd.l3_hit.snoop_non_dram memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x20003C0001  00     offcore_response.demand_data_rd.l3_miss.snoop_hit_no_fwd memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000001  00     offcore_response.demand_data_rd.l3_miss.snoop_miss memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000001  00     offcore_response.demand_data_rd.l3_miss.snoop_none memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000001  00     offcore_response.demand_data_rd.l3_miss.snoop_not_needed memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000001  00     offcore_response.demand_data_rd.l3_miss_local_dram.any_snoop memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000001  00     offcore_response.demand_data_rd.l3_miss_local_dram.snoop_hitm memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000001  00     offcore_response.demand_data_rd.l3_miss_local_dram.snoop_hit_no_fwd memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x404000001  00     offcore_response.demand_data_rd.l3_miss_local_dram.snoop_miss memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x204000001  00     offcore_response.demand_data_rd.l3_miss_local_dram.snoop_none memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x84000001  00     offcore_response.demand_data_rd.l3_miss_local_dram.snoop_non_dram memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2004000001  00     offcore_response.demand_data_rd.l3_miss_local_dram.snoop_not_needed memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x104000001  00     offcore_response.demand_data_rd.supplier_none.snoop_non_dram memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000020001  00     offcore_response.demand_rfo.l3_hit.snoop_non_dram memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x20003C0002  00     offcore_response.demand_rfo.l3_miss.snoop_hit_no_fwd memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000002  00     offcore_response.demand_rfo.l3_miss.snoop_miss memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000002  00     offcore_response.demand_rfo.l3_miss.snoop_none memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000002  00     offcore_response.demand_rfo.l3_miss.snoop_not_needed memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000002  00     offcore_response.demand_rfo.l3_miss_local_dram.any_snoop memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000002  00     offcore_response.other.l3_hit.snoop_non_dram memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x20003C8000  00     offcore_response.other.l3_miss.snoop_hit_no_fwd memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x43C008000  00     offcore_response.other.l3_miss.snoop_miss memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x23C008000  00     offcore_response.other.l3_miss.snoop_none memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0xBC008000  00     offcore_response.other.l3_miss.snoop_not_needed memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x13C008000  00     offcore_response.other.l3_miss_local_dram.any_snoop memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84008000  00     offcore_response.other.l3_miss_local_dram.snoop_hitm memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x1004008000  00     offcore_response.other.l3_miss_local_dram.snoop_hit_no_fwd memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x404008000  00     offcore_response.other.l3_miss_local_dram.snoop_miss memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x204008000  00     offcore_response.other.l3_miss_local_dram.snoop_none memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x84008000  00     offcore_response.other.l3_miss_local_dram.snoop_non_dram memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x2004008000  00     offcore_response.other.l3_miss_local_dram.snoop_not_needed memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x104008000  00     offcore_response.other.supplier_none.snoop_non_dram memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x2000028000  00     offcore_response.pf_l2_code_rd.l3_hit.snoop_non_dram memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x20003C0040  00     offcore_response.pf_l2_code_rd.l3_miss.snoop_hit_no_fwd memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000040  00     offcore_response.pf_l2_code_rd.l3_miss.snoop_miss memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000040  00     offcore_response.pf_l2_code_rd.l3_miss.snoop_none memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000040  00     offcore_response.pf_l2_code_rd.l3_miss.snoop_not_needed memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000040  00     offcore_response.pf_l2_code_rd.l3_miss_local_dram.any_snoop memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000040  00     offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_hitm memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000040  00     offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_hit_no_fwd memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x404000040  00     offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_miss memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x204000040  00     offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_none memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x84000040  00     offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_non_dram memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2004000040  00     offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_not_needed memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x104000040  00     offcore_response.pf_l2_code_rd.supplier_none.snoop_non_dram memory Counts all prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000020040  00     offcore_response.pf_l2_data_rd.l3_hit.snoop_non_dram memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x20003C0010  00     offcore_response.pf_l2_data_rd.l3_miss.snoop_hit_no_fwd memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000010  00     offcore_response.pf_l2_data_rd.l3_miss.snoop_miss memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000010  00     offcore_response.pf_l2_data_rd.l3_miss.snoop_none memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000010  00     offcore_response.pf_l2_data_rd.l3_miss.snoop_not_needed memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000010  00     offcore_response.pf_l2_data_rd.l3_miss_local_dram.any_snoop memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000010  00     offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_hitm memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000010  00     offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_hit_no_fwd memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x404000010  00     offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_miss memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x204000010  00     offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_none memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x84000010  00     offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_non_dram memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2004000010  00     offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_not_needed memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x104000010  00     offcore_response.pf_l2_data_rd.supplier_none.snoop_non_dram memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000020010  00     offcore_response.pf_l2_rfo.l3_hit.snoop_non_dram memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x20003C0020  00     offcore_response.pf_l2_rfo.l3_miss.snoop_hit_no_fwd memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000020  00     offcore_response.pf_l2_rfo.l3_miss.snoop_miss memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000020  00     offcore_response.pf_l2_rfo.l3_miss.snoop_none memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000020  00     offcore_response.pf_l2_rfo.l3_miss.snoop_not_needed memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000020  00     offcore_response.pf_l2_rfo.l3_miss_local_dram.any_snoop memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000020  00     offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_hitm memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000020  00     offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_hit_no_fwd memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x404000020  00     offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_miss memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x204000020  00     offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_none memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x84000020  00     offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_non_dram memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x2004000020  00     offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_not_needed memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x104000020  00     offcore_response.pf_l2_rfo.supplier_none.snoop_non_dram memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x2000020020  00     offcore_response.pf_l3_code_rd.l3_hit.snoop_non_dram memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x20003C0200  00     offcore_response.pf_l3_code_rd.l3_miss.snoop_hit_no_fwd memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000200  00     offcore_response.pf_l3_code_rd.l3_miss.snoop_miss memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000200  00     offcore_response.pf_l3_code_rd.l3_miss.snoop_none memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000200  00     offcore_response.pf_l3_code_rd.l3_miss.snoop_not_needed memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000200  00     offcore_response.pf_l3_code_rd.l3_miss_local_dram.any_snoop memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000200  00     offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_hitm memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000200  00     offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_hit_no_fwd memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x404000200  00     offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_miss memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x204000200  00     offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_none memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x84000200  00     offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_non_dram memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2004000200  00     offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_not_needed memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x104000200  00     offcore_response.pf_l3_code_rd.supplier_none.snoop_non_dram memory Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000020200  00     offcore_response.pf_l3_data_rd.l3_hit.snoop_non_dram memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x20003C0080  00     offcore_response.pf_l3_data_rd.l3_miss.snoop_hit_no_fwd memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000080  00     offcore_response.pf_l3_data_rd.l3_miss.snoop_miss memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000080  00     offcore_response.pf_l3_data_rd.l3_miss.snoop_none memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000080  00     offcore_response.pf_l3_data_rd.l3_miss.snoop_not_needed memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000080  00     offcore_response.pf_l3_data_rd.l3_miss_local_dram.any_snoop memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000080  00     offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_hitm memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000080  00     offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_hit_no_fwd memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x404000080  00     offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_miss memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x204000080  00     offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_none memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x84000080  00     offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_non_dram memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2004000080  00     offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_not_needed memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x104000080  00     offcore_response.pf_l3_data_rd.supplier_none.snoop_non_dram memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000020080  00     offcore_response.pf_l3_rfo.l3_hit.snoop_non_dram memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x20003C0100  00     offcore_response.pf_l3_rfo.l3_miss.snoop_hit_no_fwd memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000100  00     offcore_response.pf_l3_rfo.l3_miss.snoop_miss memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000100  00     offcore_response.pf_l3_rfo.l3_miss.snoop_none memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000100  00     offcore_response.pf_l3_rfo.l3_miss.snoop_not_needed memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000100  00     offcore_response.pf_l3_rfo.l3_miss_local_dram.any_snoop memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000100  00     offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_hitm memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000100  00     offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_hit_no_fwd memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x404000100  00     offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_miss memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x204000100  00     offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_none memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x84000100  00     offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_non_dram memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x2004000100  00     offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_not_needed memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x104000100  00     offcore_response.pf_l3_rfo.supplier_none.snoop_non_dram memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x2000020100  00     rtm_retired.aborted memory Number of times RTM abort was triggered (Precise event) event=0xc9,period=2000003,umask=4  00    Number of times RTM abort was triggered  (Precise event) rtm_retired.aborted_misc1 memory Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts) event=0xc9,period=2000003,umask=8  00    Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details) rtm_retired.aborted_misc2 memory Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts) event=0xc9,period=2000003,umask=0x10  00    Number of times the TSX watchdog signaled an RTM abort rtm_retired.aborted_misc3 memory Number of times an RTM execution aborted due to HLE-unfriendly instructions event=0xc9,period=2000003,umask=0x20  00    Number of times a disallowed operation caused an RTM abort rtm_retired.aborted_misc4 memory Number of times an RTM execution aborted due to incompatible memory type event=0xc9,period=2000003,umask=0x40  00    Number of times a RTM caused a fault rtm_retired.aborted_misc5 memory Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt) event=0xc9,period=2000003,umask=0x80  00    Number of times RTM aborted and was not due to the abort conditions in subevents 3-6 rtm_retired.commit memory Number of times RTM commit succeeded event=0xc9,period=2000003,umask=2  00     rtm_retired.start memory Number of times we entered an RTM region; does not count nested transactions event=0xc9,period=2000003,umask=1  00    Number of times we entered an RTM region  does not count nested transactions tx_exec.misc1 memory Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort event=0x5d,period=2000003,umask=1  00     tx_exec.misc2 memory Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region event=0x5d,period=2000003,umask=2  00    Unfriendly TSX abort triggered by  a vzeroupper instruction tx_exec.misc3 memory Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded event=0x5d,period=2000003,umask=4  00    Unfriendly TSX abort triggered by a nest count that is too deep tx_exec.misc4 memory Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region event=0x5d,period=2000003,umask=8  00    RTM region detected inside HLE tx_exec.misc5 memory Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region event=0x5d,period=2000003,umask=0x10  00     tx_mem.abort_capacity_write memory Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow event=0x54,period=2000003,umask=2  00     tx_mem.abort_conflict memory Number of times a TSX line had a cache conflict event=0x54,period=2000003,umask=1  00     tx_mem.abort_hle_elision_buffer_mismatch memory Number of times a TSX Abort was triggered due to release/commit but data and address mismatch event=0x54,period=2000003,umask=0x10  00     tx_mem.abort_hle_elision_buffer_not_empty memory Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty event=0x54,period=2000003,umask=8  00     tx_mem.abort_hle_elision_buffer_unsupported_alignment memory Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer event=0x54,period=2000003,umask=0x20  00     tx_mem.abort_hle_store_to_elided_lock memory Number of times a TSX Abort was triggered due to a non-release/commit store to lock event=0x54,period=2000003,umask=4  00     tx_mem.hle_elision_buffer_full memory Number of times we could not allocate Lock Buffer event=0x54,period=2000003,umask=0x40  00     cpl_cycles.ring0 other Unhalted core cycles when the thread is in ring 0 event=0x5c,period=2000003,umask=1  00    This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode cpl_cycles.ring0_trans other Number of intervals between processor halts while thread is in ring 0 event=0x5c,cmask=1,edge=1,period=100007,umask=1  00    This event counts when there is a transition from ring 1,2 or 3 to ring0 cpl_cycles.ring123 other Unhalted core cycles when thread is in rings 1, 2, or 3 event=0x5c,period=2000003,umask=2  00    This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3 lock_cycles.split_lock_uc_lock_duration other Cycles when L1 and L2 are locked due to UC or split lock event=0x63,period=2000003,umask=1  00    This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access arith.fpu_div_active pipeline Cycles when divider is busy executing divide operations event=0x14,period=2000003,umask=1  00    This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed br_inst_exec.all_branches pipeline Speculative and retired  branches event=0x88,period=200003,umask=0xff  00    This event counts both taken and not taken speculative and retired branch instructions br_inst_exec.all_conditional pipeline Speculative and retired macro-conditional branches event=0x88,period=200003,umask=0xc1  00    This event counts both taken and not taken speculative and retired macro-conditional branch instructions br_inst_exec.all_direct_jmp pipeline Speculative and retired macro-unconditional branches excluding calls and indirects event=0x88,period=200003,umask=0xc2  00    This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects br_inst_exec.all_direct_near_call pipeline Speculative and retired direct near calls event=0x88,period=200003,umask=0xd0  00    This event counts both taken and not taken speculative and retired direct near calls br_inst_exec.all_indirect_jump_non_call_ret pipeline Speculative and retired indirect branches excluding calls and returns event=0x88,period=200003,umask=0xc4  00    This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches br_inst_exec.all_indirect_near_return pipeline Speculative and retired indirect return branches event=0x88,period=200003,umask=0xc8  00    This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic br_inst_exec.nontaken_conditional pipeline Not taken macro-conditional branches event=0x88,period=200003,umask=0x41  00    This event counts not taken macro-conditional branch instructions br_inst_exec.taken_conditional pipeline Taken speculative and retired macro-conditional branches event=0x88,period=200003,umask=0x81  00    This event counts taken speculative and retired macro-conditional branch instructions br_inst_exec.taken_direct_jump pipeline Taken speculative and retired macro-conditional branch instructions excluding calls and indirects event=0x88,period=200003,umask=0x82  00    This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches br_inst_exec.taken_direct_near_call pipeline Taken speculative and retired direct near calls event=0x88,period=200003,umask=0x90  00    This event counts taken speculative and retired direct near calls br_inst_exec.taken_indirect_jump_non_call_ret pipeline Taken speculative and retired indirect branches excluding calls and returns event=0x88,period=200003,umask=0x84  00    This event counts taken speculative and retired indirect branches excluding calls and return branches br_inst_exec.taken_indirect_near_call pipeline Taken speculative and retired indirect calls event=0x88,period=200003,umask=0xa0  00    This event counts taken speculative and retired indirect calls including both register and memory indirect br_inst_exec.taken_indirect_near_return pipeline Taken speculative and retired indirect branches with return mnemonic event=0x88,period=200003,umask=0x88  00    This event counts taken speculative and retired indirect branches that have a return mnemonic br_inst_retired.all_branches pipeline All (macro) branch instructions retired event=0xc4,period=400009  00    This event counts all (macro) branch instructions retired br_inst_retired.all_branches_pebs pipeline All (macro) branch instructions retired. (Precise Event - PEBS)  Spec update: BDW98 (Must be precise) event=0xc4,period=400009,umask=4  00    This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired  Spec update: BDW98 (Must be precise) br_inst_retired.conditional pipeline Conditional branch instructions retired (Precise event) event=0xc4,period=400009,umask=1  00    This event counts conditional branch instructions retired (Precise event) br_inst_retired.far_branch pipeline Far branch instructions retired  Spec update: BDW98 event=0xc4,period=100007,umask=0x40  00    This event counts far branch instructions retired  Spec update: BDW98 br_inst_retired.near_call pipeline Direct and indirect near call instructions retired (Precise event) event=0xc4,period=100007,umask=2  00    This event counts both direct and indirect near call instructions retired (Precise event) br_inst_retired.near_call_r3 pipeline Direct and indirect macro near call instructions retired (captured in ring 3) (Precise event) event=0xc4,period=100007,umask=2  00    This event counts both direct and indirect macro near call instructions retired (captured in ring 3) (Precise event) br_inst_retired.near_return pipeline Return instructions retired (Precise event) event=0xc4,period=100007,umask=8  00    This event counts return instructions retired (Precise event) br_inst_retired.near_taken pipeline Taken branch instructions retired (Precise event) event=0xc4,period=400009,umask=0x20  00    This event counts taken branch instructions retired (Precise event) br_inst_retired.not_taken pipeline Not taken branch instructions retired event=0xc4,period=400009,umask=0x10  00    This event counts not taken branch instructions retired br_misp_exec.all_branches pipeline Speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0xff  00    This event counts both taken and not taken speculative and retired mispredicted branch instructions br_misp_exec.all_conditional pipeline Speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0xc1  00    This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions br_misp_exec.all_indirect_jump_non_call_ret pipeline Mispredicted indirect branches excluding calls and returns event=0x89,period=200003,umask=0xc4  00    This event counts both taken and not taken mispredicted indirect branches excluding calls and returns br_misp_exec.indirect pipeline Speculative mispredicted indirect branches event=0x89,period=200003,umask=0xe4  00    Counts speculatively miss-predicted indirect branches at execution time. Counts for indirect near CALL or JMP instructions (RET excluded) br_misp_exec.nontaken_conditional pipeline Not taken speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0x41  00    This event counts not taken speculative and retired mispredicted macro conditional branch instructions br_misp_exec.taken_conditional pipeline Taken speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0x81  00    This event counts taken speculative and retired mispredicted macro conditional branch instructions br_misp_exec.taken_indirect_jump_non_call_ret pipeline Taken speculative and retired mispredicted indirect branches excluding calls and returns event=0x89,period=200003,umask=0x84  00    This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns br_misp_exec.taken_indirect_near_call pipeline Taken speculative and retired mispredicted indirect calls event=0x89,period=200003,umask=0xa0  00     br_misp_exec.taken_return_near pipeline Taken speculative and retired mispredicted indirect branches with return mnemonic event=0x89,period=200003,umask=0x88  00    This event counts taken speculative and retired mispredicted indirect branches that have a return mnemonic br_misp_retired.all_branches pipeline All mispredicted macro branch instructions retired event=0xc5,period=400009  00    This event counts all mispredicted macro branch instructions retired br_misp_retired.all_branches_pebs pipeline Mispredicted macro branch instructions retired. (Precise Event - PEBS) (Must be precise) event=0xc5,period=400009,umask=4  00    This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired (Must be precise) br_misp_retired.conditional pipeline Mispredicted conditional branch instructions retired (Precise event) event=0xc5,period=400009,umask=1  00    This event counts mispredicted conditional branch instructions retired (Precise event) br_misp_retired.near_taken pipeline number of near branch instructions retired that were mispredicted and taken (Precise event) event=0xc5,period=400009,umask=0x20  00    Number of near branch instructions retired that were mispredicted and taken (Precise event) br_misp_retired.ret pipeline This event counts the number of mispredicted ret instructions retired. Non PEBS (Precise event) event=0xc5,period=100007,umask=8  00    This event counts mispredicted return instructions retired (Precise event) cpu_clk_thread_unhalted.one_thread_active pipeline Count XClk pulses when this thread is unhalted and the other thread is halted event=0x3c,period=100003,umask=2  00     cpu_clk_thread_unhalted.ref_xclk pipeline Reference cycles when the thread is unhalted (counts at 100 MHz rate) event=0x3c,period=100003,umask=1  00    This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz cpu_clk_thread_unhalted.ref_xclk_any pipeline Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate) event=0x3c,any=1,period=100003,umask=1  00     cpu_clk_unhalted.one_thread_active pipeline Count XClk pulses when this thread is unhalted and the other thread is halted event=0x3c,period=100003,umask=2  00     cpu_clk_unhalted.ref_tsc pipeline Reference cycles when the core is not in halt state event=0,period=2000003,umask=3  00    This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.  Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case cpu_clk_unhalted.ref_xclk pipeline Reference cycles when the thread is unhalted (counts at 100 MHz rate) event=0x3c,period=100003,umask=1  00     cpu_clk_unhalted.ref_xclk_any pipeline Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate) event=0x3c,any=1,period=100003,umask=1  00     cpu_clk_unhalted.thread pipeline Core cycles when the thread is not in halt state event=0x3c,period=2000003  00    This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events cpu_clk_unhalted.thread_any pipeline Core cycles when at least one thread on the physical core is not in halt state event=0x3c,any=1,period=2000003  00     cpu_clk_unhalted.thread_p_any pipeline Core cycles when at least one thread on the physical core is not in halt state event=0x3c,any=1,period=2000003  00     cycle_activity.cycles_l1d_miss pipeline Cycles while L1 cache miss demand load is outstanding event=0xa3,cmask=8,period=2000003,umask=8  00     cycle_activity.cycles_l1d_pending pipeline Cycles while L1 cache miss demand load is outstanding event=0xa3,cmask=8,period=2000003,umask=8  00    Counts number of cycles the CPU has at least one pending  demand load request missing the L1 data cache cycle_activity.cycles_l2_miss pipeline Cycles while L2 cache miss demand load is outstanding event=0xa3,cmask=1,period=2000003,umask=1  00     cycle_activity.cycles_l2_pending pipeline Cycles while L2 cache miss demand load is outstanding event=0xa3,cmask=1,period=2000003,umask=1  00    Counts number of cycles the CPU has at least one pending  demand* load request missing the L2 cache cycle_activity.cycles_ldm_pending pipeline Cycles while memory subsystem has an outstanding load event=0xa3,cmask=2,period=2000003,umask=2  00    Counts number of cycles the CPU has at least one pending  demand load request (that is cycles with non-completed load waiting for its data from memory subsystem) cycle_activity.cycles_mem_any pipeline Cycles while memory subsystem has an outstanding load event=0xa3,cmask=2,period=2000003,umask=2  00     cycle_activity.cycles_no_execute pipeline This event increments by 1 for every cycle where there was no execute for this thread event=0xa3,cmask=4,period=2000003,umask=4  00    Counts number of cycles nothing is executed on any execution port cycle_activity.stalls_l1d_miss pipeline Execution stalls while L1 cache miss demand load is outstanding event=0xa3,cmask=12,period=2000003,umask=0xc  00     cycle_activity.stalls_l1d_pending pipeline Execution stalls while L1 cache miss demand load is outstanding event=0xa3,cmask=12,period=2000003,umask=0xc  00    Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request missing the L1 data cache cycle_activity.stalls_l2_miss pipeline Execution stalls while L2 cache miss demand load is outstanding event=0xa3,cmask=5,period=2000003,umask=5  00     cycle_activity.stalls_l2_pending pipeline Execution stalls while L2 cache miss demand load is outstanding event=0xa3,cmask=5,period=2000003,umask=5  00    Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand* load request missing the L2 cache.(as a footprint) * includes also L1 HW prefetch requests that may or may not be required by demands cycle_activity.stalls_ldm_pending pipeline Execution stalls while memory subsystem has an outstanding load event=0xa3,cmask=6,period=2000003,umask=6  00    Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request cycle_activity.stalls_mem_any pipeline Execution stalls while memory subsystem has an outstanding load event=0xa3,cmask=6,period=2000003,umask=6  00     cycle_activity.stalls_total pipeline Total execution stalls event=0xa3,cmask=4,period=2000003,umask=4  00     ild_stall.lcp pipeline Stalls caused by changing prefix length of the instruction event=0x87,period=2000003,umask=1  00    This event counts stalls occurred due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk inst_retired.any pipeline Instructions retired from execution event=0xc0,period=2000003  00    This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers.  Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event.  Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions inst_retired.any_p pipeline Number of instructions retired. General Counter   - architectural event  Spec update: BDM61 event=0xc0,period=2000003  00    This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two)  Spec update: BDM61 inst_retired.prec_dist pipeline Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution  Spec update: BDM11, BDM55 (Must be precise) event=0xc0,period=2000003,umask=1  00    This is a precise version (that is, uses PEBS) of the event that counts instructions retired  Spec update: BDM11, BDM55 (Must be precise) inst_retired.x87 pipeline FP operations  retired. X87 FP operations that have no exceptions: event=0xc0,period=2000003,umask=2  00    This event counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling int_misc.rat_stall_cycles pipeline Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread event=0xd,period=2000003,umask=8  00    This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread int_misc.recovery_cycles pipeline Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke) event=0xd,cmask=1,period=2000003,umask=3  00    Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clear int_misc.recovery_cycles_any pipeline Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke) event=0xd,any=1,cmask=1,period=2000003,umask=3  00     ld_blocks.no_sr pipeline This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use event=3,period=100003,umask=8  00     ld_blocks.store_forward pipeline Cases when loads get true Block-on-Store blocking code preventing store forwarding event=3,period=100003,umask=2  00    This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:  - preceding store conflicts with the load (incomplete overlap);  - store forwarding is impossible due to u-arch limitations;  - preceding lock RMW operations are not forwarded;  - store has the no-forward bit set (uncacheable/page-split/masked stores);  - all-blocking stores are used (mostly, fences and port I/O); and others. The most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events. See the table of not supported store forwards in the Optimization Guide ld_blocks_partial.address_alias pipeline False dependencies in MOB due to partial compare event=7,period=100003,umask=1  00    This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased load_hit_pre.hw_pf pipeline Not software-prefetch load dispatches that hit FB allocated for hardware prefetch event=0x4c,period=100003,umask=2  00    This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch load_hit_pre.sw_pf pipeline Not software-prefetch load dispatches that hit FB allocated for software prefetch event=0x4c,period=100003,umask=1  00    This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions lsd.cycles_4_uops pipeline Cycles 4 Uops delivered by the LSD, but didn't come from the decoder event=0xa8,cmask=4,period=2000003,umask=1  00     lsd.cycles_active pipeline Cycles Uops delivered by the LSD, but didn't come from the decoder event=0xa8,cmask=1,period=2000003,umask=1  00     lsd.uops pipeline Number of Uops delivered by the LSD event=0xa8,period=2000003,umask=1  00     machine_clears.count pipeline Number of machine clears (nukes) of any type event=0xc3,cmask=1,edge=1,period=100003,umask=1  00     machine_clears.cycles pipeline Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes event=0xc3,period=2000003,umask=1  00    This event counts both thread-specific (TS) and all-thread (AT) nukes machine_clears.maskmov pipeline This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0 event=0xc3,period=100003,umask=0x20  00    Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault machine_clears.smc pipeline Self-modifying code (SMC) detected event=0xc3,period=100003,umask=4  00    This event counts self-modifying code (SMC) detected, which causes a machine clear move_elimination.int_eliminated pipeline Number of integer Move Elimination candidate uops that were eliminated event=0x58,period=1000003,umask=1  00     move_elimination.int_not_eliminated pipeline Number of integer Move Elimination candidate uops that were not eliminated event=0x58,period=1000003,umask=4  00     other_assists.any_wb_assist pipeline Number of times any microcode assist is invoked by HW upon uop writeback event=0xc1,period=100003,umask=0x40  00     resource_stalls.any pipeline Resource-related stall cycles event=0xa2,period=2000003,umask=1  00    This event counts resource-related stall cycles resource_stalls.rob pipeline Cycles stalled due to re-order buffer full event=0xa2,period=2000003,umask=0x10  00    This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end resource_stalls.rs pipeline Cycles stalled due to no eligible RS entry available event=0xa2,period=2000003,umask=4  00    This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end resource_stalls.sb pipeline Cycles stalled due to no store buffers available. (not including draining form sync) event=0xa2,period=2000003,umask=8  00    This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end rob_misc_events.lbr_inserts pipeline Count cases of saving new LBR event=0xcc,period=2000003,umask=0x20  00    This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register rs_events.empty_cycles pipeline Cycles when Reservation Station (RS) is empty for the thread event=0x5e,period=2000003,umask=1  00    This event counts cycles during which the reservation station (RS) is empty for the thread. Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues rs_events.empty_end pipeline Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues event=0x5e,cmask=1,edge=1,inv=1,period=200003,umask=1  00     uops_dispatched_port.port_0 pipeline Cycles per thread when uops are executed in port 0 event=0xa1,period=2000003,umask=1  00    This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0 uops_dispatched_port.port_1 pipeline Cycles per thread when uops are executed in port 1 event=0xa1,period=2000003,umask=2  00    This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1 uops_dispatched_port.port_2 pipeline Cycles per thread when uops are executed in port 2 event=0xa1,period=2000003,umask=4  00    This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2 uops_dispatched_port.port_3 pipeline Cycles per thread when uops are executed in port 3 event=0xa1,period=2000003,umask=8  00    This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3 uops_dispatched_port.port_4 pipeline Cycles per thread when uops are executed in port 4 event=0xa1,period=2000003,umask=0x10  00    This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4 uops_dispatched_port.port_5 pipeline Cycles per thread when uops are executed in port 5 event=0xa1,period=2000003,umask=0x20  00    This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5 uops_dispatched_port.port_6 pipeline Cycles per thread when uops are executed in port 6 event=0xa1,period=2000003,umask=0x40  00    This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6 uops_dispatched_port.port_7 pipeline Cycles per thread when uops are executed in port 7 event=0xa1,period=2000003,umask=0x80  00    This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7 uops_executed.core pipeline Number of uops executed on the core event=0xb1,period=2000003,umask=2  00    Number of uops executed from any thread uops_executed.core_cycles_ge_1 pipeline Cycles at least 1 micro-op is executed from any thread on physical core event=0xb1,cmask=1,period=2000003,umask=2  00     uops_executed.core_cycles_ge_2 pipeline Cycles at least 2 micro-op is executed from any thread on physical core event=0xb1,cmask=2,period=2000003,umask=2  00     uops_executed.core_cycles_ge_3 pipeline Cycles at least 3 micro-op is executed from any thread on physical core event=0xb1,cmask=3,period=2000003,umask=2  00     uops_executed.core_cycles_ge_4 pipeline Cycles at least 4 micro-op is executed from any thread on physical core event=0xb1,cmask=4,period=2000003,umask=2  00     uops_executed.core_cycles_none pipeline Cycles with no micro-ops executed from any thread on physical core event=0xb1,inv=1,period=2000003,umask=2  00     uops_executed.cycles_ge_1_uop_exec pipeline Cycles where at least 1 uop was executed per-thread event=0xb1,cmask=1,period=2000003,umask=1  00     uops_executed.cycles_ge_2_uops_exec pipeline Cycles where at least 2 uops were executed per-thread event=0xb1,cmask=2,period=2000003,umask=1  00     uops_executed.cycles_ge_3_uops_exec pipeline Cycles where at least 3 uops were executed per-thread event=0xb1,cmask=3,period=2000003,umask=1  00     uops_executed.cycles_ge_4_uops_exec pipeline Cycles where at least 4 uops were executed per-thread event=0xb1,cmask=4,period=2000003,umask=1  00     uops_executed.stall_cycles pipeline Counts number of cycles no uops were dispatched to be executed on this thread event=0xb1,cmask=1,inv=1,period=2000003,umask=1  00    This event counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread uops_executed.thread pipeline Counts the number of uops to be executed per-thread each cycle event=0xb1,period=2000003,umask=1  00    Number of uops to be executed per-thread each cycle uops_executed_port.port_0 pipeline Cycles per thread when uops are executed in port 0 event=0xa1,period=2000003,umask=1  00    This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0 uops_executed_port.port_0_core pipeline Cycles per core when uops are executed in port 0 event=0xa1,any=1,period=2000003,umask=1  00     uops_executed_port.port_1 pipeline Cycles per thread when uops are executed in port 1 event=0xa1,period=2000003,umask=2  00    This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1 uops_executed_port.port_1_core pipeline Cycles per core when uops are executed in port 1 event=0xa1,any=1,period=2000003,umask=2  00     uops_executed_port.port_2 pipeline Cycles per thread when uops are executed in port 2 event=0xa1,period=2000003,umask=4  00    This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2 uops_executed_port.port_2_core pipeline Cycles per core when uops are dispatched to port 2 event=0xa1,any=1,period=2000003,umask=4  00     uops_executed_port.port_3 pipeline Cycles per thread when uops are executed in port 3 event=0xa1,period=2000003,umask=8  00    This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3 uops_executed_port.port_3_core pipeline Cycles per core when uops are dispatched to port 3 event=0xa1,any=1,period=2000003,umask=8  00     uops_executed_port.port_4 pipeline Cycles per thread when uops are executed in port 4 event=0xa1,period=2000003,umask=0x10  00    This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4 uops_executed_port.port_4_core pipeline Cycles per core when uops are executed in port 4 event=0xa1,any=1,period=2000003,umask=0x10  00     uops_executed_port.port_5 pipeline Cycles per thread when uops are executed in port 5 event=0xa1,period=2000003,umask=0x20  00    This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5 uops_executed_port.port_5_core pipeline Cycles per core when uops are executed in port 5 event=0xa1,any=1,period=2000003,umask=0x20  00     uops_executed_port.port_6 pipeline Cycles per thread when uops are executed in port 6 event=0xa1,period=2000003,umask=0x40  00    This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6 uops_executed_port.port_6_core pipeline Cycles per core when uops are executed in port 6 event=0xa1,any=1,period=2000003,umask=0x40  00     uops_executed_port.port_7 pipeline Cycles per thread when uops are executed in port 7 event=0xa1,period=2000003,umask=0x80  00    This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7 uops_executed_port.port_7_core pipeline Cycles per core when uops are dispatched to port 7 event=0xa1,any=1,period=2000003,umask=0x80  00     uops_issued.any pipeline Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS) event=0xe,period=2000003,umask=1  00    This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) uops_issued.flags_merge pipeline Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch event=0xe,period=2000003,umask=0x10  00    Number of flags-merge uops being allocated. Such uops considered perf sensitive  added by GSR u-arch uops_issued.single_mul pipeline Number of Multiply packed/scalar single precision uops allocated event=0xe,period=2000003,umask=0x40  00     uops_issued.slow_lea pipeline Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not event=0xe,period=2000003,umask=0x20  00     uops_issued.stall_cycles pipeline Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread event=0xe,cmask=1,inv=1,period=2000003,umask=1  00    This event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread uops_retired.all pipeline Actually retired uops (Precise event) event=0xc2,period=2000003,umask=1  00    This event counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight (Precise event) uops_retired.retire_slots pipeline Retirement slots used (Precise event) event=0xc2,period=2000003,umask=2  00    This event counts the number of retirement slots used (Precise event) uops_retired.stall_cycles pipeline Cycles without actually retired uops event=0xc2,cmask=1,inv=1,period=2000003,umask=1  00    This event counts cycles without actually retired uops uops_retired.total_cycles pipeline Cycles with less than 10 actually retired uops event=0xc2,cmask=16,inv=1,period=2000003,umask=1  00    Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event unc_cbo_cache_lookup.any_es uncore cache L3 Lookup any request that access cache and found line in E or S-state event=0x34,umask=0x86  01     unc_cbo_cache_lookup.any_i uncore cache L3 Lookup any request that access cache and found line in I-state event=0x34,umask=0x88  01     unc_cbo_cache_lookup.any_m uncore cache L3 Lookup any request that access cache and found line in M-state event=0x34,umask=0x81  01     unc_cbo_cache_lookup.any_mesi uncore cache L3 Lookup any request that access cache and found line in MESI-state event=0x34,umask=0x8f  01     unc_cbo_cache_lookup.read_es uncore cache L3 Lookup read request that access cache and found line in E or S-state event=0x34,umask=0x16  01     unc_cbo_cache_lookup.read_i uncore cache L3 Lookup read request that access cache and found line in I-state event=0x34,umask=0x18  01     unc_cbo_cache_lookup.read_m uncore cache L3 Lookup read request that access cache and found line in M-state event=0x34,umask=0x11  01     unc_cbo_cache_lookup.read_mesi uncore cache L3 Lookup read request that access cache and found line in any MESI-state event=0x34,umask=0x1f  01     unc_cbo_cache_lookup.write_es uncore cache L3 Lookup write request that access cache and found line in E or S-state event=0x34,umask=0x26  01     unc_cbo_cache_lookup.write_m uncore cache L3 Lookup write request that access cache and found line in M-state event=0x34,umask=0x21  01     unc_cbo_cache_lookup.write_mesi uncore cache L3 Lookup write request that access cache and found line in MESI-state event=0x34,umask=0x2f  01     unc_cbo_xsnp_response.hitm_xcore uncore cache A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core event=0x22,umask=0x48  01     unc_cbo_xsnp_response.hit_xcore uncore cache A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core event=0x22,umask=0x44  01     unc_cbo_xsnp_response.miss_eviction uncore cache A cross-core snoop resulted from L3 Eviction which misses in some processor core event=0x22,umask=0x81  01     unc_cbo_xsnp_response.miss_xcore uncore cache A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core event=0x22,umask=0x41  01     uncore_cbox_0 unc_clock.socket uncore cache This 48-bit fixed counter counts the UCLK cycles event=0xff  01     unc_arb_coh_trk_requests.all uncore interconnect Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc event=0x84,umask=1  01     unc_arb_trk_occupancy.all uncore interconnect Each cycle counts number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic event=0x80,umask=1  01     unc_arb_trk_occupancy.cycles_with_any_request uncore interconnect Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.; event=0x80,cmask=1,umask=1  01     unc_arb_trk_occupancy.drd_direct uncore interconnect Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case event=0x80,umask=2  01    Each cycle count number of valid coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case unc_arb_trk_requests.all uncore interconnect Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic event=0x81,umask=1  01     unc_arb_trk_requests.drd_direct uncore interconnect Number of Core coherent Data Read entries allocated in DirectData mode event=0x81,umask=2  01     unc_arb_trk_requests.writes uncore interconnect Number of Writes allocated - any write transactions: full/partials writes and evictions event=0x81,umask=0x20  01     dtlb_load_misses.miss_causes_a_walk virtual memory Load misses in all DTLB levels that cause page walks  Spec update: BDM69 event=8,period=100003,umask=1  00    This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G)  Spec update: BDM69 dtlb_load_misses.stlb_hit virtual memory Load operations that miss the first DTLB level but hit the second and do not cause page walks event=8,period=2000003,umask=0x60  00     dtlb_load_misses.stlb_hit_2m virtual memory Load misses that miss the  DTLB and hit the STLB (2M) event=8,period=2000003,umask=0x40  00     dtlb_load_misses.stlb_hit_4k virtual memory Load misses that miss the  DTLB and hit the STLB (4K) event=8,period=2000003,umask=0x20  00     dtlb_load_misses.walk_completed virtual memory Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size  Spec update: BDM69 event=8,period=100003,umask=0xe  00     dtlb_load_misses.walk_completed_1g virtual memory Load miss in all TLB levels causes a page walk that completes. (1G)  Spec update: BDM69 event=8,period=2000003,umask=8  00    This event counts load misses in all DTLB levels that cause a completed page walk (1G  page size). The page walk can end with or without a fault  Spec update: BDM69 dtlb_load_misses.walk_completed_2m_4m virtual memory Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M)  Spec update: BDM69 event=8,period=2000003,umask=4  00    This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault  Spec update: BDM69 dtlb_load_misses.walk_completed_4k virtual memory Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K)  Spec update: BDM69 event=8,period=2000003,umask=2  00    This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault  Spec update: BDM69 dtlb_load_misses.walk_duration virtual memory Cycles when PMH is busy with page walks  Spec update: BDM69 event=8,period=2000003,umask=0x10  00    This event counts the number of cycles while PMH is busy with the page walk  Spec update: BDM69 dtlb_store_misses.miss_causes_a_walk virtual memory Store misses in all DTLB levels that cause page walks  Spec update: BDM69 event=0x49,period=100003,umask=1  00    This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G)  Spec update: BDM69 dtlb_store_misses.stlb_hit virtual memory Store operations that miss the first TLB level but hit the second and do not cause page walks event=0x49,period=100003,umask=0x60  00     dtlb_store_misses.stlb_hit_2m virtual memory Store misses that miss the  DTLB and hit the STLB (2M) event=0x49,period=100003,umask=0x40  00     dtlb_store_misses.stlb_hit_4k virtual memory Store misses that miss the  DTLB and hit the STLB (4K) event=0x49,period=100003,umask=0x20  00     dtlb_store_misses.walk_completed virtual memory Store misses in all DTLB levels that cause completed page walks  Spec update: BDM69 event=0x49,period=100003,umask=0xe  00     dtlb_store_misses.walk_completed_1g virtual memory Store misses in all DTLB levels that cause completed page walks (1G)  Spec update: BDM69 event=0x49,period=100003,umask=8  00    This event counts store misses in all DTLB levels that cause a completed page walk (1G  page size). The page walk can end with or without a fault  Spec update: BDM69 dtlb_store_misses.walk_completed_2m_4m virtual memory Store misses in all DTLB levels that cause completed page walks (2M/4M)  Spec update: BDM69 event=0x49,period=100003,umask=4  00    This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault  Spec update: BDM69 dtlb_store_misses.walk_completed_4k virtual memory Store miss in all TLB levels causes a page walk that completes. (4K)  Spec update: BDM69 event=0x49,period=100003,umask=2  00    This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault  Spec update: BDM69 dtlb_store_misses.walk_duration virtual memory Cycles when PMH is busy with page walks  Spec update: BDM69 event=0x49,period=100003,umask=0x10  00    This event counts the number of cycles while PMH is busy with the page walk  Spec update: BDM69 ept.walk_cycles virtual memory Cycle count for an Extended Page table walk event=0x4f,period=2000003,umask=0x10  00    This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches itlb.itlb_flush virtual memory Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages event=0xae,period=100007,umask=1  00    This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific) itlb_misses.miss_causes_a_walk virtual memory Misses at all ITLB levels that cause page walks  Spec update: BDM69 event=0x85,period=100003,umask=1  00    This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G)  Spec update: BDM69 itlb_misses.stlb_hit virtual memory Operations that miss the first ITLB level but hit the second and do not cause any page walks event=0x85,period=100003,umask=0x60  00     itlb_misses.stlb_hit_2m virtual memory Code misses that miss the  DTLB and hit the STLB (2M) event=0x85,period=100003,umask=0x40  00     itlb_misses.stlb_hit_4k virtual memory Core misses that miss the  DTLB and hit the STLB (4K) event=0x85,period=100003,umask=0x20  00     itlb_misses.walk_completed virtual memory Misses in all ITLB levels that cause completed page walks  Spec update: BDM69 event=0x85,period=100003,umask=0xe  00     itlb_misses.walk_completed_1g virtual memory Store miss in all TLB levels causes a page walk that completes. (1G)  Spec update: BDM69 event=0x85,period=100003,umask=8  00    This event counts store misses in all DTLB levels that cause a completed page walk (1G  page size). The page walk can end with or without a fault  Spec update: BDM69 itlb_misses.walk_completed_2m_4m virtual memory Code miss in all TLB levels causes a page walk that completes. (2M/4M)  Spec update: BDM69 event=0x85,period=100003,umask=4  00    This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault  Spec update: BDM69 itlb_misses.walk_completed_4k virtual memory Code miss in all TLB levels causes a page walk that completes. (4K)  Spec update: BDM69 event=0x85,period=100003,umask=2  00    This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault  Spec update: BDM69 itlb_misses.walk_duration virtual memory Cycles when PMH is busy with page walks  Spec update: BDM69 event=0x85,period=100003,umask=0x10  00    This event counts the number of cycles while PMH is busy with the page walk  Spec update: BDM69 page_walker_loads.dtlb_l1 virtual memory Number of DTLB page walker hits in the L1+FB  Spec update: BDM69, BDM98 event=0xbc,period=2000003,umask=0x11  00     page_walker_loads.dtlb_l2 virtual memory Number of DTLB page walker hits in the L2  Spec update: BDM69, BDM98 event=0xbc,period=2000003,umask=0x12  00     page_walker_loads.dtlb_l3 virtual memory Number of DTLB page walker hits in the L3 + XSNP  Spec update: BDM69, BDM98 event=0xbc,period=2000003,umask=0x14  00     page_walker_loads.dtlb_memory virtual memory Number of DTLB page walker hits in Memory  Spec update: BDM69, BDM98 event=0xbc,period=2000003,umask=0x18  00     page_walker_loads.itlb_l1 virtual memory Number of ITLB page walker hits in the L1+FB  Spec update: BDM69, BDM98 event=0xbc,period=2000003,umask=0x21  00     page_walker_loads.itlb_l2 virtual memory Number of ITLB page walker hits in the L2  Spec update: BDM69, BDM98 event=0xbc,period=2000003,umask=0x22  00     page_walker_loads.itlb_l3 virtual memory Number of ITLB page walker hits in the L3 + XSNP  Spec update: BDM69, BDM98 event=0xbc,period=2000003,umask=0x24  00     tlb_flush.dtlb_thread virtual memory DTLB flush attempts of the thread-specific entries event=0xbd,period=100007,umask=1  00    This event counts the number of DTLB flush attempts of the thread-specific entries tlb_flush.stlb_any virtual memory STLB flush attempts event=0xbd,period=100007,umask=0x20  00    This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on) mem_load_uops_l3_miss_retired.remote_dram cache Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)  Supports address when precise.  Spec update: BDE70 (Precise event) event=0xd3,period=100007,umask=4  00     mem_load_uops_l3_miss_retired.remote_fwd cache Retired load uop whose Data Source was: forwarded from remote cache  Supports address when precise.  Spec update: BDE70 (Precise event) event=0xd3,period=100007,umask=0x20  00     mem_load_uops_l3_miss_retired.remote_hitm cache Retired load uop whose Data Source was: Remote cache HITM  Supports address when precise.  Spec update: BDE70 (Precise event) event=0xd3,period=100007,umask=0x10  00     unc_c_bounce_control uncore cache Bounce Control event=0xa  01     unc_c_clockticks uncore cache Uncore Clocks event=0  01     unc_c_counter0_occupancy uncore cache Counter 0 Occupancy event=0x1f  01    Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0.   The filtering available is found in the control register - threshold, invert and edge detect.   E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry unc_c_fast_asserted uncore cache FaST wire asserted event=9  01    Counts the number of cycles either the local distress or incoming distress signals are asserted.  Incoming distress includes both up and dn unc_c_llc_lookup.any uncore cache Cache Lookups; Any Request event=0x34,umask=0x11  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ.  This does not include lookups originating from the ISMQ unc_c_llc_lookup.data_read uncore cache Cache Lookups; Data Read Request event=0x34,umask=3  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions unc_c_llc_lookup.nid uncore cache Cache Lookups; Lookups that Match NID event=0x34,umask=0x41  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Qualify one of the other subevents by the Target NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.   In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system unc_c_llc_lookup.read uncore cache Cache Lookups; Any Read Request event=0x34,umask=0x21  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions unc_c_llc_lookup.remote_snoop uncore cache Cache Lookups; External Snoop Request event=0x34,umask=9  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ unc_c_llc_lookup.write uncore cache Cache Lookups; Write Requests event=0x34,umask=5  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC  This includes all write transactions -- both Cacheable and UC unc_c_llc_victims.e_state uncore cache Lines Victimized; Lines in E state event=0x37,umask=2  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_c_llc_victims.f_state uncore cache Lines Victimized event=0x37,umask=8  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_c_llc_victims.i_state uncore cache Lines Victimized; Lines in S State event=0x37,umask=4  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_c_llc_victims.miss uncore cache Lines Victimized event=0x37,umask=0x10  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_c_llc_victims.m_state uncore cache Lines Victimized; Lines in M state event=0x37,umask=1  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_c_llc_victims.nid uncore cache Lines Victimized; Victimized Lines that Match NID event=0x37,umask=0x40  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.; Qualify one of the other subevents by the Target NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.   In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system unc_c_misc.cvzero_prefetch_miss uncore cache Cbo Misc; DRd hitting non-M with raw CV=0 event=0x39,umask=0x20  01    Miscellaneous events in the Cbo unc_c_misc.cvzero_prefetch_victim uncore cache Cbo Misc; Clean Victim with raw CV=0 event=0x39,umask=0x10  01    Miscellaneous events in the Cbo unc_c_misc.rfo_hit_s uncore cache Cbo Misc; RFO HitS event=0x39,umask=8  01    Miscellaneous events in the Cbo.; Number of times that an RFO hit in S state.  This is useful for determining if it might be good for a workload to use RspIWB instead of RspSWB unc_c_misc.rspi_was_fse uncore cache Cbo Misc; Silent Snoop Eviction event=0x39,umask=1  01    Miscellaneous events in the Cbo.; Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction.  This is useful because this information is lost in the PRE encodings unc_c_misc.started uncore cache Cbo Misc event=0x39,umask=4  01    Miscellaneous events in the Cbo unc_c_misc.wc_aliasing uncore cache Cbo Misc; Write Combining Aliasing event=0x39,umask=2  01    Miscellaneous events in the Cbo.; Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write.  This occurs when there is WC aliasing unc_c_qlru.age0 uncore cache LRU Queue; LRU Age 0 event=0x3c,umask=1  01    How often age was set to 0 unc_c_qlru.age1 uncore cache LRU Queue; LRU Age 1 event=0x3c,umask=2  01    How often age was set to 1 unc_c_qlru.age2 uncore cache LRU Queue; LRU Age 2 event=0x3c,umask=4  01    How often age was set to 2 unc_c_qlru.age3 uncore cache LRU Queue; LRU Age 3 event=0x3c,umask=8  01    How often age was set to 3 unc_c_qlru.lru_decrement uncore cache LRU Queue; LRU Bits Decremented event=0x3c,umask=0x10  01    How often all LRU bits were decremented by 1 unc_c_qlru.victim_non_zero uncore cache LRU Queue; Non-0 Aged Victim event=0x3c,umask=0x20  01    How often we picked a victim that had a non-zero age unc_c_ring_ad_used.all uncore cache AD Ring In Use; All event=0x1b,umask=0xf  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.ccw uncore cache AD Ring In Use; Down event=0x1b,umask=0xc  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.cw uncore cache AD Ring In Use; Up event=0x1b,umask=3  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.down_even uncore cache AD Ring In Use; Down and Even event=0x1b,umask=4  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity unc_c_ring_ad_used.down_odd uncore cache AD Ring In Use; Down and Odd event=0x1b,umask=8  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_c_ring_ad_used.up_even uncore cache AD Ring In Use; Up and Even event=0x1b,umask=1  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_c_ring_ad_used.up_odd uncore cache AD Ring In Use; Up and Odd event=0x1b,umask=2  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_c_ring_ak_used.all uncore cache AK Ring In Use; All event=0x1c,umask=0xf  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.ccw uncore cache AK Ring In Use; Down event=0x1c,umask=0xc  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.cw uncore cache AK Ring In Use; Up event=0x1c,umask=3  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.down_even uncore cache AK Ring In Use; Down and Even event=0x1c,umask=4  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity unc_c_ring_ak_used.down_odd uncore cache AK Ring In Use; Down and Odd event=0x1c,umask=8  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_c_ring_ak_used.up_even uncore cache AK Ring In Use; Up and Even event=0x1c,umask=1  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_c_ring_ak_used.up_odd uncore cache AK Ring In Use; Up and Odd event=0x1c,umask=2  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_c_ring_bl_used.all uncore cache BL Ring in Use; Down event=0x1d,umask=0xf  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.ccw uncore cache BL Ring in Use; Down event=0x1d,umask=0xc  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.cw uncore cache BL Ring in Use; Up event=0x1d,umask=3  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.down_even uncore cache BL Ring in Use; Down and Even event=0x1d,umask=4  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity unc_c_ring_bl_used.down_odd uncore cache BL Ring in Use; Down and Odd event=0x1d,umask=8  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_c_ring_bl_used.up_even uncore cache BL Ring in Use; Up and Even event=0x1d,umask=1  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_c_ring_bl_used.up_odd uncore cache BL Ring in Use; Up and Odd event=0x1d,umask=2  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_c_ring_bounces.ad uncore cache Number of LLC responses that bounced on the Ring.; AD event=5,umask=1  01     unc_c_ring_bounces.ak uncore cache Number of LLC responses that bounced on the Ring.; AK event=5,umask=2  01     unc_c_ring_bounces.bl uncore cache Number of LLC responses that bounced on the Ring.; BL event=5,umask=4  01     unc_c_ring_bounces.iv uncore cache Number of LLC responses that bounced on the Ring.; Snoops of processor's cache event=5,umask=0x10  01     unc_c_ring_iv_used.any uncore cache BL Ring in Use; Any event=0x1e,umask=0xf  01    Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in BDX  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity unc_c_ring_iv_used.dn uncore cache BL Ring in Use; Any event=0x1e,umask=0xc  01    Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in BDX  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity unc_c_ring_iv_used.down uncore cache BL Ring in Use; Down event=0x1e,umask=0xcc  01    Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in BDX  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters for Down polarity unc_c_ring_iv_used.up uncore cache BL Ring in Use; Any event=0x1e,umask=3  01    Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in BDX  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity unc_c_ring_sink_starved.ad uncore cache AD event=6,umask=1  01     unc_c_ring_sink_starved.ak uncore cache AK event=6,umask=2  01     unc_c_ring_sink_starved.bl uncore cache BL event=6,umask=4  01     unc_c_ring_sink_starved.iv uncore cache IV event=6,umask=8  01     unc_c_ring_src_thrtl uncore cache Number of cycles the Cbo is actively throttling traffic onto the Ring in order to limit bounce traffic event=7  01     unc_c_rxr_ext_starved.ipq uncore cache Ingress Arbiter Blocking Cycles; IRQ event=0x12,umask=2  01    Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.; IPQ is externally starved and therefore we are blocking the IRQ unc_c_rxr_ext_starved.irq uncore cache Ingress Arbiter Blocking Cycles; IPQ event=0x12,umask=1  01    Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.; IRQ is externally starved and therefore we are blocking the IPQ unc_c_rxr_ext_starved.ismq_bids uncore cache Ingress Arbiter Blocking Cycles; ISMQ_BID event=0x12,umask=8  01    Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.; Number of times that the ISMQ Bid unc_c_rxr_ext_starved.prq uncore cache Ingress Arbiter Blocking Cycles; PRQ event=0x12,umask=4  01    Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues unc_c_rxr_inserts.ipq uncore cache Ingress Allocations; IPQ event=0x13,umask=4  01    Counts number of allocations per cycle into the specified Ingress queue unc_c_rxr_inserts.irq uncore cache Ingress Allocations; IRQ event=0x13,umask=1  01    Counts number of allocations per cycle into the specified Ingress queue unc_c_rxr_inserts.irq_rej uncore cache Ingress Allocations; IRQ Rejected event=0x13,umask=2  01    Counts number of allocations per cycle into the specified Ingress queue unc_c_rxr_inserts.prq uncore cache Ingress Allocations; PRQ event=0x13,umask=0x10  01    Counts number of allocations per cycle into the specified Ingress queue unc_c_rxr_inserts.prq_rej uncore cache Ingress Allocations; PRQ event=0x13,umask=0x20  01    Counts number of allocations per cycle into the specified Ingress queue unc_c_rxr_int_starved.ipq uncore cache Ingress Internal Starvation Cycles; IPQ event=0x14,umask=4  01    Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IPQ in Internal Starvation unc_c_rxr_int_starved.irq uncore cache Ingress Internal Starvation Cycles; IRQ event=0x14,umask=1  01    Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IRQ in Internal Starvation unc_c_rxr_int_starved.ismq uncore cache Ingress Internal Starvation Cycles; ISMQ event=0x14,umask=8  01    Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the ISMQ in Internal Starvation unc_c_rxr_int_starved.prq uncore cache Ingress Internal Starvation Cycles; PRQ event=0x14,umask=0x10  01    Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue unc_c_rxr_ipq_retry.addr_conflict uncore cache Probe Queue Retries; Address Conflict event=0x31,umask=4  01    Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from an address conflicts.  Address conflicts out of the IPQ should be rare.  They will generally only occur if two different sockets are sending requests to the same address at the same time.  This is a true conflict case, unlike the IPQ Address Conflict which is commonly caused by prefetching characteristics unc_c_rxr_ipq_retry.any uncore cache Probe Queue Retries; Any Reject event=0x31,umask=1  01    Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject.  TOR rejects from the IPQ can be caused by the Egress being full or Address Conflicts unc_c_rxr_ipq_retry.full uncore cache Probe Queue Retries; No Egress Credits event=0x31,umask=2  01    Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from the Egress being full.  IPQ requests make use of the AD Egress for regular responses, the BL egress to forward data, and the AK egress to return credits unc_c_rxr_ipq_retry.qpi_credits uncore cache Probe Queue Retries; No QPI Credits event=0x31,umask=0x10  01    Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries unc_c_rxr_ipq_retry2.ad_sbo uncore cache Probe Queue Retries; No AD Sbo Credits event=0x28,umask=1  01    Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an AD packet to the Sbo unc_c_rxr_ipq_retry2.target uncore cache Probe Queue Retries; Target Node Filter event=0x28,umask=0x40  01    Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request from the IPQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register unc_c_rxr_irq_retry.addr_conflict uncore cache Ingress Request Queue Rejects; Address Conflict event=0x32,umask=4  01    Counts the number of times that a request from the IRQ was retried because of an address match in the TOR.  In order to maintain coherency, requests to the same address are not allowed to pass each other up in the Cbo.  Therefore, if there is an outstanding request to a given address, one cannot issue another request to that address until it is complete.  This comes up most commonly with prefetches.  Outstanding prefetches occasionally will not complete their memory fetch and a demand request to the same address will then sit in the IRQ and get retried until the prefetch fills the data into the LLC.  Therefore, it will not be uncommon to see this case in high bandwidth streaming workloads when the LLC Prefetcher in the core is enabled unc_c_rxr_irq_retry.any uncore cache Ingress Request Queue Rejects; Any Reject event=0x32,umask=1  01    Counts the number of IRQ retries that occur.  Requests from the IRQ are retried if they are rejected from the TOR pipeline for a variety of reasons.  Some of the most common reasons include if the Egress is full, there are no RTIDs, or there is a Physical Address match to another outstanding request unc_c_rxr_irq_retry.full uncore cache Ingress Request Queue Rejects; No Egress Credits event=0x32,umask=2  01    Counts the number of times that a request from the IRQ was retried because it failed to acquire an entry in the Egress.  The egress is the buffer that queues up for allocating onto the ring.  IRQ requests can make use of all four rings and all four Egresses.  If any of the queues that a given request needs to make use of are full, the request will be retried unc_c_rxr_irq_retry.iio_credits uncore cache Ingress Request Queue Rejects; No IIO Credits event=0x32,umask=0x20  01    Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO.  There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO unc_c_rxr_irq_retry.nid uncore cache Ingress Request Queue Rejects event=0x32,umask=0x40  01    Qualify one of the other subevents by a given RTID destination NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid unc_c_rxr_irq_retry.qpi_credits uncore cache Ingress Request Queue Rejects; No QPI Credits event=0x32,umask=0x10  01    Number of requests rejects because of lack of QPI Ingress credits.  These credits are required in order to send transactions to the QPI agent.  Please see the QPI_IGR_CREDITS events for more information unc_c_rxr_irq_retry.rtid uncore cache Ingress Request Queue Rejects; No RTIDs event=0x32,umask=8  01    Counts the number of times that requests from the IRQ were retried because there were no RTIDs available.  RTIDs are required after a request misses the LLC and needs to send snoops and/or requests to memory.  If there are no RTIDs available, requests will queue up in the IRQ and retry until one becomes available.  Note that there are multiple RTID pools for the different sockets.  There may be cases where the local RTIDs are all used, but requests destined for remote memory can still acquire an RTID because there are remote RTIDs available.  This event does not provide any filtering for this case unc_c_rxr_irq_retry2.ad_sbo uncore cache Ingress Request Queue Rejects; No AD Sbo Credits event=0x29,umask=1  01    Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an AD packet to the Sbo unc_c_rxr_irq_retry2.bl_sbo uncore cache Ingress Request Queue Rejects; No BL Sbo Credits event=0x29,umask=2  01    Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an BL packet to the Sbo unc_c_rxr_irq_retry2.target uncore cache Ingress Request Queue Rejects; Target Node Filter event=0x29,umask=0x40  01    Counts the number of times that a request from the IPQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register unc_c_rxr_ismq_retry.any uncore cache ISMQ Retries; Any Reject event=0x33,umask=1  01    Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the total number of times that a request from the ISMQ retried because of a TOR reject.  ISMQ requests generally will not need to retry (or at least ISMQ retries are less common than IRQ retries).  ISMQ requests will retry if they are not able to acquire a needed Egress credit to get onto the ring, or for cache evictions that need to acquire an RTID.  Most ISMQ requests already have an RTID, so eviction retries will be less common here unc_c_rxr_ismq_retry.full uncore cache ISMQ Retries; No Egress Credits event=0x33,umask=2  01    Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by a lack of Egress credits. The egress is the buffer that queues up for allocating onto the ring.  If any of the Egress queues that a given request needs to make use of are full, the request will be retried unc_c_rxr_ismq_retry.iio_credits uncore cache ISMQ Retries; No IIO Credits event=0x33,umask=0x20  01    Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO.  There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO unc_c_rxr_ismq_retry.nid uncore cache ISMQ Retries event=0x33,umask=0x40  01    Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Qualify one of the other subevents by a given RTID destination NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid unc_c_rxr_ismq_retry.qpi_credits uncore cache ISMQ Retries; No QPI Credits event=0x33,umask=0x10  01    Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores unc_c_rxr_ismq_retry.rtid uncore cache ISMQ Retries; No RTIDs event=0x33,umask=8  01    Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by no RTIDs.  M-state cache evictions are serviced through the ISMQ, and must acquire an RTID in order to write back to memory.  If no RTIDs are available, they will be retried unc_c_rxr_ismq_retry.wb_credits uncore cache ISMQ Retries event=0x33,umask=0x80  01    Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Qualify one of the other subevents by a given RTID destination NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid unc_c_rxr_ismq_retry2.ad_sbo uncore cache ISMQ Request Queue Rejects; No AD Sbo Credits event=0x2a,umask=1  01    Counts the number of times that a request from the ISMQ was retried because of it lacked credits to send an AD packet to the Sbo unc_c_rxr_ismq_retry2.bl_sbo uncore cache ISMQ Request Queue Rejects; No BL Sbo Credits event=0x2a,umask=2  01    Counts the number of times that a request from the ISMQ was retried because of it lacked credits to send an BL packet to the Sbo unc_c_rxr_ismq_retry2.target uncore cache ISMQ Request Queue Rejects; Target Node Filter event=0x2a,umask=0x40  01    Counts the number of times that a request from the ISMQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register unc_c_rxr_occupancy.ipq uncore cache Ingress Occupancy; IPQ event=0x11,umask=4  01    Counts number of entries in the specified Ingress queue in each cycle unc_c_rxr_occupancy.irq uncore cache Ingress Occupancy; IRQ event=0x11,umask=1  01    Counts number of entries in the specified Ingress queue in each cycle unc_c_rxr_occupancy.irq_rej uncore cache Ingress Occupancy; IRQ Rejected event=0x11,umask=2  01    Counts number of entries in the specified Ingress queue in each cycle unc_c_rxr_occupancy.prq_rej uncore cache Ingress Occupancy; PRQ Rejects event=0x11,umask=0x20  01    Counts number of entries in the specified Ingress queue in each cycle unc_c_sbo_credits_acquired.ad uncore cache SBo Credits Acquired; For AD Ring event=0x3d,umask=1  01    Number of Sbo credits acquired in a given cycle, per ring.  Each Cbo is assigned an Sbo it can communicate with unc_c_sbo_credits_acquired.bl uncore cache SBo Credits Acquired; For BL Ring event=0x3d,umask=2  01    Number of Sbo credits acquired in a given cycle, per ring.  Each Cbo is assigned an Sbo it can communicate with unc_c_sbo_credit_occupancy.ad uncore cache SBo Credits Occupancy; For AD Ring event=0x3e,umask=1  01    Number of Sbo credits in use in a given cycle, per ring.  Each Cbo is assigned an Sbo it can communicate with unc_c_sbo_credit_occupancy.bl uncore cache SBo Credits Occupancy; For BL Ring event=0x3e,umask=2  01    Number of Sbo credits in use in a given cycle, per ring.  Each Cbo is assigned an Sbo it can communicate with unc_c_tor_inserts.all uncore cache TOR Inserts; All event=0x35,umask=8  01    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions inserted into the TOR.    This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues.  The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger.  Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20.  Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots unc_c_tor_inserts.eviction uncore cache TOR Inserts; Evictions event=0x35,umask=4  01    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Eviction transactions inserted into the TOR.  Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set.  They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory) unc_c_tor_inserts.local uncore cache TOR Inserts; Local Memory event=0x35,umask=0x28  01    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions inserted into the TOR that are satisfied by locally HOMed memory unc_c_tor_inserts.local_opcode uncore cache TOR Inserts; Local Memory - Opcode Matched event=0x35,umask=0x21  01    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions, satisfied by an opcode,  inserted into the TOR that are satisfied by locally HOMed memory unc_c_tor_inserts.miss_local uncore cache TOR Inserts; Misses to Local Memory event=0x35,umask=0x2a  01    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that are satisfied by locally HOMed memory unc_c_tor_inserts.miss_local_opcode uncore cache TOR Inserts; Misses to Local Memory - Opcode Matched event=0x35,umask=0x23  01    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions, satisfied by an opcode, inserted into the TOR that are satisfied by locally HOMed memory unc_c_tor_inserts.miss_opcode uncore cache TOR Inserts; Miss Opcode Match event=0x35,umask=3  01    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode unc_c_tor_inserts.miss_remote uncore cache TOR Inserts; Misses to Remote Memory event=0x35,umask=0x8a  01    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that are satisfied by remote caches or remote memory unc_c_tor_inserts.miss_remote_opcode uncore cache TOR Inserts; Misses to Remote Memory - Opcode Matched event=0x35,umask=0x83  01    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions, satisfied by an opcode,  inserted into the TOR that are satisfied by remote caches or remote memory unc_c_tor_inserts.nid_all uncore cache TOR Inserts; NID Matched event=0x35,umask=0x48  01    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All NID matched (matches an RTID destination) transactions inserted into the TOR.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.  In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system unc_c_tor_inserts.nid_eviction uncore cache TOR Inserts; NID Matched Evictions event=0x35,umask=0x44  01    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; NID matched eviction transactions inserted into the TOR unc_c_tor_inserts.nid_miss_all uncore cache TOR Inserts; NID Matched Miss All event=0x35,umask=0x4a  01    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All NID matched miss requests that were inserted into the TOR unc_c_tor_inserts.nid_miss_opcode uncore cache TOR Inserts; NID and Opcode Matched Miss event=0x35,umask=0x43  01    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match a NID and an opcode unc_c_tor_inserts.nid_opcode uncore cache TOR Inserts; NID and Opcode Matched event=0x35,umask=0x41  01    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match a NID and an opcode unc_c_tor_inserts.nid_wb uncore cache TOR Inserts; NID Matched Writebacks event=0x35,umask=0x50  01    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; NID matched write transactions inserted into the TOR unc_c_tor_inserts.opcode uncore cache TOR Inserts; Opcode Match event=0x35,umask=1  01    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc) unc_c_tor_inserts.remote uncore cache TOR Inserts; Remote Memory event=0x35,umask=0x88  01    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions inserted into the TOR that are satisfied by remote caches or remote memory unc_c_tor_inserts.remote_opcode uncore cache TOR Inserts; Remote Memory - Opcode Matched event=0x35,umask=0x81  01    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions, satisfied by an opcode,  inserted into the TOR that are satisfied by remote caches or remote memory unc_c_tor_inserts.wb uncore cache TOR Inserts; Writebacks event=0x35,umask=0x10  01    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Write transactions inserted into the TOR.   This does not include RFO, but actual operations that contain data being sent from the core unc_c_tor_occupancy.all uncore cache TOR Occupancy; Any event=0x36,umask=8  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All valid TOR entries.  This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues.  The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger.  Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20.  Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots unc_c_tor_occupancy.eviction uncore cache TOR Occupancy; Evictions event=0x36,umask=4  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding eviction transactions in the TOR.  Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set.  They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory) unc_c_tor_occupancy.local uncore cache TOR Occupancy event=0x36,umask=0x28  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.local_opcode uncore cache TOR Occupancy; Local Memory - Opcode Matched event=0x36,umask=0x21  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding  transactions, satisfied by an opcode,  in the TOR that are satisfied by locally HOMed memory unc_c_tor_occupancy.miss_all uncore cache TOR Occupancy; Miss All event=0x36,umask=0xa  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding miss requests in the TOR.  'Miss' means the allocation requires an RTID.  This generally means that the request was sent to memory or MMIO unc_c_tor_occupancy.miss_local uncore cache TOR Occupancy event=0x36,umask=0x2a  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.miss_local_opcode uncore cache TOR Occupancy; Misses to Local Memory - Opcode Matched event=0x36,umask=0x23  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisfied by an opcode, in the TOR that are satisfied by locally HOMed memory unc_c_tor_occupancy.miss_opcode uncore cache TOR Occupancy; Miss Opcode Match event=0x36,umask=3  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries for miss transactions that match an opcode. This generally means that the request was sent to memory or MMIO unc_c_tor_occupancy.miss_remote uncore cache TOR Occupancy event=0x36,umask=0x8a  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.miss_remote_opcode uncore cache TOR Occupancy; Misses to Remote Memory - Opcode Matched event=0x36,umask=0x83  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisfied by an opcode, in the TOR that are satisfied by remote caches or remote memory unc_c_tor_occupancy.nid_all uncore cache TOR Occupancy; NID Matched event=0x36,umask=0x48  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of NID matched outstanding requests in the TOR.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system unc_c_tor_occupancy.nid_eviction uncore cache TOR Occupancy; NID Matched Evictions event=0x36,umask=0x44  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding NID matched eviction transactions in the TOR  unc_c_tor_occupancy.nid_miss_all uncore cache TOR Occupancy; NID Matched event=0x36,umask=0x4a  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID unc_c_tor_occupancy.nid_miss_opcode uncore cache TOR Occupancy; NID and Opcode Matched Miss event=0x36,umask=0x43  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID and an opcode unc_c_tor_occupancy.nid_opcode uncore cache TOR Occupancy; NID and Opcode Matched event=0x36,umask=0x41  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match a NID and an opcode unc_c_tor_occupancy.nid_wb uncore cache TOR Occupancy; NID Matched Writebacks event=0x36,umask=0x50  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); NID matched write transactions int the TOR unc_c_tor_occupancy.opcode uncore cache TOR Occupancy; Opcode Match event=0x36,umask=1  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc) unc_c_tor_occupancy.remote uncore cache TOR Occupancy event=0x36,umask=0x88  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.remote_opcode uncore cache TOR Occupancy; Remote Memory - Opcode Matched event=0x36,umask=0x81  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding  transactions, satisfied by an opcode,  in the TOR that are satisfied by remote caches or remote memory unc_c_tor_occupancy.wb uncore cache TOR Occupancy; Writebacks event=0x36,umask=0x10  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Write transactions in the TOR.   This does not include RFO, but actual operations that contain data being sent from the core unc_c_txr_ads_used.ad uncore cache Onto AD Ring event=4,umask=1  01     unc_c_txr_ads_used.ak uncore cache Onto AK Ring event=4,umask=2  01     unc_c_txr_ads_used.bl uncore cache Onto BL Ring event=4,umask=4  01     unc_c_txr_inserts.ad_cache uncore cache Egress Allocations; AD - Cachebo event=2,umask=1  01    Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_c_txr_inserts.ad_core uncore cache Egress Allocations; AD - Corebo event=2,umask=0x10  01    Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AD ring.  This is commonly used for outbound requests unc_c_txr_inserts.ak_cache uncore cache Egress Allocations; AK - Cachebo event=2,umask=2  01    Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AK ring.  This is commonly used for credit returns and GO responses unc_c_txr_inserts.ak_core uncore cache Egress Allocations; AK - Corebo event=2,umask=0x20  01    Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AK ring.  This is commonly used for snoop responses coming from the core and destined for a Cachebo unc_c_txr_inserts.bl_cache uncore cache Egress Allocations; BL - Cacheno event=2,umask=4  01    Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the BL ring.  This is commonly used to send data from the cache to various destinations unc_c_txr_inserts.bl_core uncore cache Egress Allocations; BL - Corebo event=2,umask=0x40  01    Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the BL ring.  This is commonly used for transferring writeback data to the cache unc_c_txr_inserts.iv_cache uncore cache Egress Allocations; IV - Cachebo event=2,umask=8  01    Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the IV ring.  This is commonly used for snoops to the cores unc_c_txr_starved.ad_core uncore cache Injection Starvation; Onto AD Ring (to core) event=3,umask=0x10  01    Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the core AD egress spent in starvation unc_c_txr_starved.ak_both uncore cache Injection Starvation; Onto AK Ring event=3,umask=2  01    Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both AK egresses spent in starvation unc_c_txr_starved.bl_both uncore cache Injection Starvation; Onto BL Ring event=3,umask=4  01    Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both BL egresses spent in starvation unc_c_txr_starved.iv uncore cache Injection Starvation; Onto IV Ring event=3,umask=8  01    Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the cachebo IV egress spent in starvation uncore_ha unc_h_bt_cycles_ne uncore cache BT Cycles Not Empty event=0x42  01    Cycles the Backup Tracker (BT) is not empty. The BT is the actual HOM tracker in IVT unc_h_bt_to_ht_not_issued.incoming_bl_hazard uncore cache BT to HT Not Issued; Incoming Data Hazard event=0x51,umask=4  01    Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard unc_h_bt_to_ht_not_issued.incoming_snp_hazard uncore cache BT to HT Not Issued; Incoming Snoop Hazard event=0x51,umask=2  01    Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming snoop hazard unc_h_bt_to_ht_not_issued.rspackcflt_hazard uncore cache BT to HT Not Issued; Incoming Data Hazard event=0x51,umask=8  01    Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard unc_h_bt_to_ht_not_issued.wbmdata_hazard uncore cache BT to HT Not Issued; Incoming Data Hazard event=0x51,umask=0x10  01    Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard unc_h_bypass_imc.not_taken uncore cache HA to iMC Bypass; Not Taken event=0x14,umask=2  01    Counts the number of times when the HA was able to bypass was attempted.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass unc_h_bypass_imc.taken uncore cache HA to iMC Bypass; Taken event=0x14,umask=1  01    Counts the number of times when the HA was able to bypass was attempted.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the bypass unc_h_clockticks uncore cache uclks event=0  01    Counts the number of uclks in the HA.  This will be slightly different than the count in the Ubox because of enable/freeze delays.  The HA is on the other side of the die from the fixed Ubox uclk counter, so the drift could be somewhat larger than in units that are closer like the QPI Agent unc_h_direct2core_count uncore cache Direct2Core Messages Sent event=0x11  01    Number of Direct2Core messages sent unc_h_direct2core_cycles_disabled uncore cache Cycles when Direct2Core was Disabled event=0x12  01    Number of cycles in which Direct2Core was disabled unc_h_direct2core_txn_override uncore cache Number of Reads that had Direct2Core Overridden event=0x13  01    Number of Reads where Direct2Core overridden unc_h_directory_lat_opt uncore cache Directory Lat Opt Return event=0x41  01    Directory Latency Optimization Data Return Path Taken. When directory mode is enabled and the directory returned for a read is Dir=I, then data can be returned using a faster path if certain conditions are met (credits, free pipeline, etc) unc_h_directory_lookup.no_snp uncore cache Directory Lookups; Snoop Not Needed event=0xc,umask=2  01    Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.; Filters for transactions that did not have to send any snoops because the directory bit was clear unc_h_directory_lookup.snp uncore cache Directory Lookups; Snoop Needed event=0xc,umask=1  01    Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.; Filters for transactions that had to send one or more snoops because the directory bit was set unc_h_directory_update.any uncore cache Directory Updates; Any Directory Update event=0xd,umask=3  01    Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears unc_h_directory_update.clear uncore cache Directory Updates; Directory Clear event=0xd,umask=2  01    Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.; Filter for directory clears.  This occurs when snoops were sent and all returned with RspI unc_h_directory_update.set uncore cache Directory Updates; Directory Set event=0xd,umask=1  01    Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.; Filter for directory sets.  This occurs when a remote read transaction requests memory, bringing it to a remote cache unc_h_hitme_hit.ackcnfltwbi uncore cache Counts Number of Hits in HitMe Cache; op is AckCnfltWbI event=0x71,umask=4  01     unc_h_hitme_hit.all uncore cache Counts Number of Hits in HitMe Cache; All Requests event=0x71,umask=0xff  01     unc_h_hitme_hit.allocs uncore cache Counts Number of Hits in HitMe Cache; Allocations event=0x71,umask=0x70  01     unc_h_hitme_hit.evicts uncore cache Counts Number of Hits in HitMe Cache; Allocations event=0x71,umask=0x42  01     unc_h_hitme_hit.hom uncore cache Counts Number of Hits in HitMe Cache; HOM Requests event=0x71,umask=0xf  01     unc_h_hitme_hit.invals uncore cache Counts Number of Hits in HitMe Cache; Invalidations event=0x71,umask=0x26  01     unc_h_hitme_hit.read_or_invitoe uncore cache Counts Number of Hits in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE event=0x71,umask=1  01     unc_h_hitme_hit.rsp uncore cache Counts Number of Hits in HitMe Cache; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI event=0x71,umask=0x80  01     unc_h_hitme_hit.rspfwdi_local uncore cache Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a local request event=0x71,umask=0x20  01     unc_h_hitme_hit.rspfwdi_remote uncore cache Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request event=0x71,umask=0x10  01     unc_h_hitme_hit.rspfwds uncore cache Counts Number of Hits in HitMe Cache; op is RsSFwd or RspSFwdWb event=0x71,umask=0x40  01     unc_h_hitme_hit.wbmtoe_or_s uncore cache Counts Number of Hits in HitMe Cache; op is WbMtoE or WbMtoS event=0x71,umask=8  01     unc_h_hitme_hit.wbmtoi uncore cache Counts Number of Hits in HitMe Cache; op is WbMtoI event=0x71,umask=2  01     unc_h_hitme_hit_pv_bits_set.ackcnfltwbi uncore cache Accumulates Number of PV bits set on HitMe Cache Hits; op is AckCnfltWbI event=0x72,umask=4  01     unc_h_hitme_hit_pv_bits_set.all uncore cache Accumulates Number of PV bits set on HitMe Cache Hits; All Requests event=0x72,umask=0xff  01     unc_h_hitme_hit_pv_bits_set.hom uncore cache Accumulates Number of PV bits set on HitMe Cache Hits; HOM Requests event=0x72,umask=0xf  01     unc_h_hitme_hit_pv_bits_set.read_or_invitoe uncore cache Accumulates Number of PV bits set on HitMe Cache Hits; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE event=0x72,umask=1  01     unc_h_hitme_hit_pv_bits_set.rsp uncore cache Accumulates Number of PV bits set on HitMe Cache Hits; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI event=0x72,umask=0x80  01     unc_h_hitme_hit_pv_bits_set.rspfwdi_local uncore cache Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a local request event=0x72,umask=0x20  01     unc_h_hitme_hit_pv_bits_set.rspfwdi_remote uncore cache Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a remote request event=0x72,umask=0x10  01     unc_h_hitme_hit_pv_bits_set.rspfwds uncore cache Accumulates Number of PV bits set on HitMe Cache Hits; op is RsSFwd or RspSFwdWb event=0x72,umask=0x40  01     unc_h_hitme_hit_pv_bits_set.wbmtoe_or_s uncore cache Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoE or WbMtoS event=0x72,umask=8  01     unc_h_hitme_hit_pv_bits_set.wbmtoi uncore cache Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoI event=0x72,umask=2  01     unc_h_hitme_lookup.ackcnfltwbi uncore cache Counts Number of times HitMe Cache is accessed; op is AckCnfltWbI event=0x70,umask=4  01     unc_h_hitme_lookup.all uncore cache Counts Number of times HitMe Cache is accessed; All Requests event=0x70,umask=0xff  01     unc_h_hitme_lookup.allocs uncore cache Counts Number of times HitMe Cache is accessed; Allocations event=0x70,umask=0x70  01     unc_h_hitme_lookup.hom uncore cache Counts Number of times HitMe Cache is accessed; HOM Requests event=0x70,umask=0xf  01     unc_h_hitme_lookup.invals uncore cache Counts Number of times HitMe Cache is accessed; Invalidations event=0x70,umask=0x26  01     unc_h_hitme_lookup.read_or_invitoe uncore cache Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE event=0x70,umask=1  01     unc_h_hitme_lookup.rsp uncore cache Counts Number of times HitMe Cache is accessed; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI event=0x70,umask=0x80  01     unc_h_hitme_lookup.rspfwdi_local uncore cache Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a local request event=0x70,umask=0x20  01     unc_h_hitme_lookup.rspfwdi_remote uncore cache Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a remote request event=0x70,umask=0x10  01     unc_h_hitme_lookup.rspfwds uncore cache Counts Number of times HitMe Cache is accessed; op is RsSFwd or RspSFwdWb event=0x70,umask=0x40  01     unc_h_hitme_lookup.wbmtoe_or_s uncore cache Counts Number of times HitMe Cache is accessed; op is WbMtoE or WbMtoS event=0x70,umask=8  01     unc_h_hitme_lookup.wbmtoi uncore cache Counts Number of times HitMe Cache is accessed; op is WbMtoI event=0x70,umask=2  01     unc_h_igr_no_credit_cycles.ad_qpi0 uncore cache Cycles without QPI Ingress Credits; AD to QPI Link 0 event=0x22,umask=1  01    Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links unc_h_igr_no_credit_cycles.ad_qpi1 uncore cache Cycles without QPI Ingress Credits; AD to QPI Link 1 event=0x22,umask=2  01    Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links unc_h_igr_no_credit_cycles.ad_qpi2 uncore cache Cycles without QPI Ingress Credits; BL to QPI Link 0 event=0x22,umask=0x10  01    Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links unc_h_igr_no_credit_cycles.bl_qpi0 uncore cache Cycles without QPI Ingress Credits; BL to QPI Link 0 event=0x22,umask=4  01    Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links unc_h_igr_no_credit_cycles.bl_qpi1 uncore cache Cycles without QPI Ingress Credits; BL to QPI Link 1 event=0x22,umask=8  01    Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links unc_h_igr_no_credit_cycles.bl_qpi2 uncore cache Cycles without QPI Ingress Credits; BL to QPI Link 1 event=0x22,umask=0x20  01    Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links unc_h_imc_reads.normal uncore cache HA to iMC Normal Priority Reads Issued; Normal Priority event=0x17,umask=1  01    Count of the number of reads issued to any of the memory controller channels.  This can be filtered by the priority of the reads unc_h_imc_retry uncore cache Retry Events event=0x1e  01     unc_h_imc_writes.all uncore cache HA to iMC Full Line Writes Issued; All Writes event=0x1a,umask=0xf  01    Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH unc_h_imc_writes.full uncore cache HA to iMC Full Line Writes Issued; Full Line Non-ISOCH event=0x1a,umask=1  01    Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH unc_h_imc_writes.full_isoch uncore cache HA to iMC Full Line Writes Issued; ISOCH Full Line event=0x1a,umask=4  01    Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH unc_h_imc_writes.partial uncore cache HA to iMC Full Line Writes Issued; Partial Non-ISOCH event=0x1a,umask=2  01    Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH unc_h_imc_writes.partial_isoch uncore cache HA to iMC Full Line Writes Issued; ISOCH Partial event=0x1a,umask=8  01    Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH unc_h_iot_backpressure.hub uncore cache IOT Backpressure event=0x61,umask=2  01     unc_h_iot_backpressure.sat uncore cache IOT Backpressure event=0x61,umask=1  01     unc_h_iot_cts_east_lo.cts0 uncore cache IOT Common Trigger Sequencer - Lo event=0x64,umask=1  01    Debug Mask/Match Tie-Ins unc_h_iot_cts_east_lo.cts1 uncore cache IOT Common Trigger Sequencer - Lo event=0x64,umask=2  01    Debug Mask/Match Tie-Ins unc_h_iot_cts_hi.cts2 uncore cache IOT Common Trigger Sequencer - Hi event=0x65,umask=1  01    Debug Mask/Match Tie-Ins unc_h_iot_cts_hi.cts3 uncore cache IOT Common Trigger Sequencer - Hi event=0x65,umask=2  01    Debug Mask/Match Tie-Ins unc_h_iot_cts_west_lo.cts0 uncore cache IOT Common Trigger Sequencer - Lo event=0x62,umask=1  01    Debug Mask/Match Tie-Ins unc_h_iot_cts_west_lo.cts1 uncore cache IOT Common Trigger Sequencer - Lo event=0x62,umask=2  01    Debug Mask/Match Tie-Ins unc_h_osb.cancelled uncore cache OSB Snoop Broadcast; Cancelled event=0x53,umask=0x10  01    Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.; OSB Snoop broadcast cancelled due to D2C or Other. OSB cancel is counted when OSB local read is not allowed even when the transaction in local InItoE. It also counts D2C OSB cancel, but also includes the cases were D2C was not set in the first place for the transaction coming from the ring unc_h_osb.invitoe_local uncore cache OSB Snoop Broadcast; Local InvItoE event=0x53,umask=4  01    Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_h_osb.reads_local uncore cache OSB Snoop Broadcast; Local Reads event=0x53,umask=2  01    Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_h_osb.reads_local_useful uncore cache OSB Snoop Broadcast; Reads Local -  Useful event=0x53,umask=0x20  01    Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_h_osb.remote uncore cache OSB Snoop Broadcast; Remote event=0x53,umask=8  01    Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_h_osb.remote_useful uncore cache OSB Snoop Broadcast; Remote - Useful event=0x53,umask=0x40  01    Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_h_osb_edr.all uncore cache OSB Early Data Return; All event=0x54,umask=1  01    Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return unc_h_osb_edr.reads_local_i uncore cache OSB Early Data Return; Reads to Local  I event=0x54,umask=2  01    Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return unc_h_osb_edr.reads_local_s uncore cache OSB Early Data Return; Reads to Local S event=0x54,umask=8  01    Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return unc_h_osb_edr.reads_remote_i uncore cache OSB Early Data Return; Reads to Remote I event=0x54,umask=4  01    Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return unc_h_osb_edr.reads_remote_s uncore cache OSB Early Data Return; Reads to Remote S event=0x54,umask=0x10  01    Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return unc_h_requests.invitoe_local uncore cache Read and Write Requests; Local InvItoEs event=1,umask=0x10  01    Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only InvItoEs coming from the local socket unc_h_requests.invitoe_remote uncore cache Read and Write Requests; Remote InvItoEs event=1,umask=0x20  01    Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only InvItoEs coming from remote sockets unc_h_requests.reads uncore cache Read and Write Requests; Reads event=1,umask=3  01    Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; Incoming ead requests.  This is a good proxy for LLC Read Misses (including RFOs) unc_h_requests.reads_local uncore cache Read and Write Requests; Local Reads event=1,umask=1  01    Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only read requests coming from the local socket.  This is a good proxy for LLC Read Misses (including RFOs) from the local socket unc_h_requests.reads_remote uncore cache Read and Write Requests; Remote Reads event=1,umask=2  01    Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only read requests coming from the remote socket.  This is a good proxy for LLC Read Misses (including RFOs) from the remote socket unc_h_requests.writes uncore cache Read and Write Requests; Writes event=1,umask=0xc  01    Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; Incoming write requests unc_h_requests.writes_local uncore cache Read and Write Requests; Local Writes event=1,umask=4  01    Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only writes coming from the local socket unc_h_requests.writes_remote uncore cache Read and Write Requests; Remote Writes event=1,umask=8  01    Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only writes coming from remote sockets unc_h_ring_ad_used.ccw uncore cache HA AD Ring in Use; Counterclockwise event=0x3e,umask=0xc  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ad_used.ccw_even uncore cache HA AD Ring in Use; Counterclockwise and Even event=0x3e,umask=4  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity unc_h_ring_ad_used.ccw_odd uncore cache HA AD Ring in Use; Counterclockwise and Odd event=0x3e,umask=8  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity unc_h_ring_ad_used.cw uncore cache HA AD Ring in Use; Clockwise event=0x3e,umask=3  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ad_used.cw_even uncore cache HA AD Ring in Use; Clockwise and Even event=0x3e,umask=1  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity unc_h_ring_ad_used.cw_odd uncore cache HA AD Ring in Use; Clockwise and Odd event=0x3e,umask=2  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity unc_h_ring_ak_used.all uncore cache HA AK Ring in Use; All event=0x3f,umask=0xf  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ak_used.ccw uncore cache HA AK Ring in Use; Counterclockwise event=0x3f,umask=0xc  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ak_used.ccw_even uncore cache HA AK Ring in Use; Counterclockwise and Even event=0x3f,umask=4  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity unc_h_ring_ak_used.ccw_odd uncore cache HA AK Ring in Use; Counterclockwise and Odd event=0x3f,umask=8  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity unc_h_ring_ak_used.cw uncore cache HA AK Ring in Use; Clockwise event=0x3f,umask=3  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ak_used.cw_even uncore cache HA AK Ring in Use; Clockwise and Even event=0x3f,umask=1  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity unc_h_ring_ak_used.cw_odd uncore cache HA AK Ring in Use; Clockwise and Odd event=0x3f,umask=2  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity unc_h_ring_bl_used.all uncore cache HA BL Ring in Use; All event=0x40,umask=0xf  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_bl_used.ccw uncore cache HA BL Ring in Use; Counterclockwise event=0x40,umask=0xc  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_bl_used.ccw_even uncore cache HA BL Ring in Use; Counterclockwise and Even event=0x40,umask=4  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity unc_h_ring_bl_used.ccw_odd uncore cache HA BL Ring in Use; Counterclockwise and Odd event=0x40,umask=8  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity unc_h_ring_bl_used.cw uncore cache HA BL Ring in Use; Clockwise event=0x40,umask=3  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_bl_used.cw_even uncore cache HA BL Ring in Use; Clockwise and Even event=0x40,umask=1  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity unc_h_ring_bl_used.cw_odd uncore cache HA BL Ring in Use; Clockwise and Odd event=0x40,umask=2  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity unc_h_rpq_cycles_no_reg_credits.chn0 uncore cache iMC RPQ Credits Empty - Regular; Channel 0 event=0x15,umask=1  01    Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the regular credits  Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only unc_h_rpq_cycles_no_reg_credits.chn1 uncore cache iMC RPQ Credits Empty - Regular; Channel 1 event=0x15,umask=2  01    Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the regular credits  Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only unc_h_rpq_cycles_no_reg_credits.chn2 uncore cache iMC RPQ Credits Empty - Regular; Channel 2 event=0x15,umask=4  01    Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the regular credits  Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only unc_h_rpq_cycles_no_reg_credits.chn3 uncore cache iMC RPQ Credits Empty - Regular; Channel 3 event=0x15,umask=8  01    Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the regular credits  Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only unc_h_rpq_cycles_no_spec_credits.chn0 uncore cache iMC RPQ Credits Empty - Special; Channel 0 event=0x16,umask=1  01    Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the special credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only unc_h_rpq_cycles_no_spec_credits.chn1 uncore cache iMC RPQ Credits Empty - Special; Channel 1 event=0x16,umask=2  01    Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the special credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only unc_h_rpq_cycles_no_spec_credits.chn2 uncore cache iMC RPQ Credits Empty - Special; Channel 2 event=0x16,umask=4  01    Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the special credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only unc_h_rpq_cycles_no_spec_credits.chn3 uncore cache iMC RPQ Credits Empty - Special; Channel 3 event=0x16,umask=8  01    Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the special credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only unc_h_sbo0_credits_acquired.ad uncore cache SBo0 Credits Acquired; For AD Ring event=0x68,umask=1  01    Number of Sbo 0 credits acquired in a given cycle, per ring unc_h_sbo0_credits_acquired.bl uncore cache SBo0 Credits Acquired; For BL Ring event=0x68,umask=2  01    Number of Sbo 0 credits acquired in a given cycle, per ring unc_h_sbo0_credit_occupancy.ad uncore cache SBo0 Credits Occupancy; For AD Ring event=0x6a,umask=1  01    Number of Sbo 0 credits in use in a given cycle, per ring unc_h_sbo0_credit_occupancy.bl uncore cache SBo0 Credits Occupancy; For BL Ring event=0x6a,umask=2  01    Number of Sbo 0 credits in use in a given cycle, per ring unc_h_sbo1_credits_acquired.ad uncore cache SBo1 Credits Acquired; For AD Ring event=0x69,umask=1  01    Number of Sbo 1 credits acquired in a given cycle, per ring unc_h_sbo1_credits_acquired.bl uncore cache SBo1 Credits Acquired; For BL Ring event=0x69,umask=2  01    Number of Sbo 1 credits acquired in a given cycle, per ring unc_h_sbo1_credit_occupancy.ad uncore cache SBo1 Credits Occupancy; For AD Ring event=0x6b,umask=1  01    Number of Sbo 1 credits in use in a given cycle, per ring unc_h_sbo1_credit_occupancy.bl uncore cache SBo1 Credits Occupancy; For BL Ring event=0x6b,umask=2  01    Number of Sbo 1 credits in use in a given cycle, per ring unc_h_snoops_rsp_after_data.local uncore cache Data beat the Snoop Responses; Local Requests event=0xa,umask=1  01    Counts the number of reads when the snoop was on the critical path to the data return.; This filter includes only requests coming from the local socket unc_h_snoops_rsp_after_data.remote uncore cache Data beat the Snoop Responses; Remote Requests event=0xa,umask=2  01    Counts the number of reads when the snoop was on the critical path to the data return.; This filter includes only requests coming from remote sockets unc_h_snoop_cycles_ne.all uncore cache Cycles with Snoops Outstanding; All Requests event=8,umask=3  01    Counts cycles when one or more snoops are outstanding.; Tracked for snoops from both local and remote sockets unc_h_snoop_cycles_ne.local uncore cache Cycles with Snoops Outstanding; Local Requests event=8,umask=1  01    Counts cycles when one or more snoops are outstanding.; This filter includes only requests coming from the local socket unc_h_snoop_cycles_ne.remote uncore cache Cycles with Snoops Outstanding; Remote Requests event=8,umask=2  01    Counts cycles when one or more snoops are outstanding.; This filter includes only requests coming from remote sockets unc_h_snoop_occupancy.local uncore cache Tracker Snoops Outstanding Accumulator; Local Requests event=9,umask=1  01    Accumulates the occupancy of either the local HA tracker pool that have snoops pending in every cycle.    This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if an HT (HomeTracker) entry is available and this occupancy is decremented when all the snoop responses have returned.; This filter includes only requests coming from the local socket unc_h_snoop_occupancy.remote uncore cache Tracker Snoops Outstanding Accumulator; Remote Requests event=9,umask=2  01    Accumulates the occupancy of either the local HA tracker pool that have snoops pending in every cycle.    This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if an HT (HomeTracker) entry is available and this occupancy is decremented when all the snoop responses have returned.; This filter includes only requests coming from remote sockets unc_h_snoop_resp.rspcnflct uncore cache Snoop Responses Received; RSPCNFLCT* event=0x21,umask=0x40  01    Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoops responses of RspConflict.  This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent.  This triggers conflict resolution hardware.  This covers both RspCnflct and RspCnflctWbI unc_h_snoop_resp.rspi uncore cache Snoop Responses Received; RspI event=0x21,umask=1  01    Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoops responses of RspI.  RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data) unc_h_snoop_resp.rspifwd uncore cache Snoop Responses Received; RspIFwd event=0x21,umask=4  01    Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspIFwd.  This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states.  This is commonly returned with RFO transactions.  It can be either a HitM or a HitFE unc_h_snoop_resp.rsps uncore cache Snoop Responses Received; RspS event=0x21,umask=2  01    Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspS.  RspS is returned when a remote cache has data but is not forwarding it.  It is a way to let the requesting socket know that it cannot allocate the data in E state.  No data is sent with S RspS unc_h_snoop_resp.rspsfwd uncore cache Snoop Responses Received; RspSFwd event=0x21,umask=8  01    Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspSFwd.  This is returned when a remote caching agent forwards data but holds on to its current copy.  This is common for data and code reads that hit in a remote socket in E or F state unc_h_snoop_resp.rsp_fwd_wb uncore cache Snoop Responses Received; Rsp*Fwd*WB event=0x21,umask=0x20  01    Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of Rsp*Fwd*WB.  This snoop response is only used in 4s systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory unc_h_snoop_resp.rsp_wb uncore cache Snoop Responses Received; Rsp*WB event=0x21,umask=0x10  01    Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspIWB or RspSWB.  This is returned when a non-RFO request hits in M state.  Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured.  InvItoE transactions will also return RspIWB because they must acquire ownership unc_h_snp_resp_recv_local.other uncore cache Snoop Responses Received Local; Other event=0x60,umask=0x80  01    Number of snoop responses received for a Local  request; Filters for all other snoop responses unc_h_snp_resp_recv_local.rspcnflct uncore cache Snoop Responses Received Local; RspCnflct event=0x60,umask=0x40  01    Number of snoop responses received for a Local  request; Filters for snoops responses of RspConflict.  This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent.  This triggers conflict resolution hardware.  This covers both RspCnflct and RspCnflctWbI unc_h_snp_resp_recv_local.rspi uncore cache Snoop Responses Received Local; RspI event=0x60,umask=1  01    Number of snoop responses received for a Local  request; Filters for snoops responses of RspI.  RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data) unc_h_snp_resp_recv_local.rspifwd uncore cache Snoop Responses Received Local; RspIFwd event=0x60,umask=4  01    Number of snoop responses received for a Local  request; Filters for snoop responses of RspIFwd.  This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states.  This is commonly returned with RFO transactions.  It can be either a HitM or a HitFE unc_h_snp_resp_recv_local.rsps uncore cache Snoop Responses Received Local; RspS event=0x60,umask=2  01    Number of snoop responses received for a Local  request; Filters for snoop responses of RspS.  RspS is returned when a remote cache has data but is not forwarding it.  It is a way to let the requesting socket know that it cannot allocate the data in E state.  No data is sent with S RspS unc_h_snp_resp_recv_local.rspsfwd uncore cache Snoop Responses Received Local; RspSFwd event=0x60,umask=8  01    Number of snoop responses received for a Local  request; Filters for a snoop response of RspSFwd.  This is returned when a remote caching agent forwards data but holds on to its current copy.  This is common for data and code reads that hit in a remote socket in E or F state unc_h_snp_resp_recv_local.rspxfwdxwb uncore cache Snoop Responses Received Local; Rsp*FWD*WB event=0x60,umask=0x20  01    Number of snoop responses received for a Local  request; Filters for a snoop response of Rsp*Fwd*WB.  This snoop response is only used in 4s systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory unc_h_snp_resp_recv_local.rspxwb uncore cache Snoop Responses Received Local; Rsp*WB event=0x60,umask=0x10  01    Number of snoop responses received for a Local  request; Filters for a snoop response of RspIWB or RspSWB.  This is returned when a non-RFO request hits in M state.  Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured.  InvItoE transactions will also return RspIWB because they must acquire ownership unc_h_stall_no_sbo_credit.sbo0_ad uncore cache Stall on No Sbo Credits; For SBo0, AD Ring event=0x6c,umask=1  01    Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring unc_h_stall_no_sbo_credit.sbo0_bl uncore cache Stall on No Sbo Credits; For SBo0, BL Ring event=0x6c,umask=4  01    Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring unc_h_stall_no_sbo_credit.sbo1_ad uncore cache Stall on No Sbo Credits; For SBo1, AD Ring event=0x6c,umask=2  01    Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring unc_h_stall_no_sbo_credit.sbo1_bl uncore cache Stall on No Sbo Credits; For SBo1, BL Ring event=0x6c,umask=8  01    Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring unc_h_tad_requests_g0.region0 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 0 event=0x1b,umask=1  01    Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 0 unc_h_tad_requests_g0.region1 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 1 event=0x1b,umask=2  01    Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 1 unc_h_tad_requests_g0.region2 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 2 event=0x1b,umask=4  01    Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 2 unc_h_tad_requests_g0.region3 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 3 event=0x1b,umask=8  01    Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 3 unc_h_tad_requests_g0.region4 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 4 event=0x1b,umask=0x10  01    Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 4 unc_h_tad_requests_g0.region5 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 5 event=0x1b,umask=0x20  01    Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 5 unc_h_tad_requests_g0.region6 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 6 event=0x1b,umask=0x40  01    Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 6 unc_h_tad_requests_g0.region7 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 7 event=0x1b,umask=0x80  01    Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 7 unc_h_tad_requests_g1.region10 uncore cache HA Requests to a TAD Region - Group 1; TAD Region 10 event=0x1c,umask=4  01    Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 10 unc_h_tad_requests_g1.region11 uncore cache HA Requests to a TAD Region - Group 1; TAD Region 11 event=0x1c,umask=8  01    Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 11 unc_h_tad_requests_g1.region8 uncore cache HA Requests to a TAD Region - Group 1; TAD Region 8 event=0x1c,umask=1  01    Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 8 unc_h_tad_requests_g1.region9 uncore cache HA Requests to a TAD Region - Group 1; TAD Region 9 event=0x1c,umask=2  01    Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 9 unc_h_tracker_cycles_full.all uncore cache Tracker Cycles Full; Cycles Completely Used event=2,umask=2  01    Counts the number of cycles when the local HA tracker pool is completely used.  This can be used with edge detect to identify the number of situations when the pool became fully utilized.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, the system could be starved for RTIDs but not fill up the HA trackers.  HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Counts the number of cycles when the HA tracker pool (HT) is completely used including reserved HT entries.  It will not return valid count when BT is disabled unc_h_tracker_cycles_full.gp uncore cache Tracker Cycles Full; Cycles GP Completely Used event=2,umask=1  01    Counts the number of cycles when the local HA tracker pool is completely used.  This can be used with edge detect to identify the number of situations when the pool became fully utilized.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, the system could be starved for RTIDs but not fill up the HA trackers.  HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Counts the number of cycles when the general purpose (GP) HA tracker pool (HT) is completely used.  It will not return valid count when BT is disabled unc_h_tracker_cycles_ne.all uncore cache Tracker Cycles Not Empty; All Requests event=3,umask=3  01    Counts the number of cycles when the local HA tracker pool is not empty.  This can be used with edge detect to identify the number of situations when the pool became empty.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, this buffer could be completely empty, but there may still be credits in use by the CBos.  This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occupancy.  HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Requests coming from both local and remote sockets unc_h_tracker_cycles_ne.local uncore cache Tracker Cycles Not Empty; Local Requests event=3,umask=1  01    Counts the number of cycles when the local HA tracker pool is not empty.  This can be used with edge detect to identify the number of situations when the pool became empty.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, this buffer could be completely empty, but there may still be credits in use by the CBos.  This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occupancy.  HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from the local socket unc_h_tracker_cycles_ne.remote uncore cache Tracker Cycles Not Empty; Remote Requests event=3,umask=2  01    Counts the number of cycles when the local HA tracker pool is not empty.  This can be used with edge detect to identify the number of situations when the pool became empty.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, this buffer could be completely empty, but there may still be credits in use by the CBos.  This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occupancy.  HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from remote sockets unc_h_tracker_occupancy.invitoe_local uncore cache Tracker Occupancy Accumulator; Local InvItoE Requests event=4,umask=0x40  01    Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_tracker_occupancy.invitoe_remote uncore cache Tracker Occupancy Accumulator; Remote InvItoE Requests event=4,umask=0x80  01    Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_tracker_occupancy.reads_local uncore cache Tracker Occupancy Accumulator; Local Read Requests event=4,umask=4  01    Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_tracker_occupancy.reads_remote uncore cache Tracker Occupancy Accumulator; Remote Read Requests event=4,umask=8  01    Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_tracker_occupancy.writes_local uncore cache Tracker Occupancy Accumulator; Local Write Requests event=4,umask=0x10  01    Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_tracker_occupancy.writes_remote uncore cache Tracker Occupancy Accumulator; Remote Write Requests event=4,umask=0x20  01    Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_tracker_pending_occupancy.local uncore cache Data Pending Occupancy Accumulator; Local Requests event=5,umask=1  01    Accumulates the number of transactions that have data from the memory controller until they get scheduled to the Egress.  This can be used to calculate the queuing latency for two things.  (1) If the system is waiting for snoops, this will increase.  (2) If the system can't schedule to the Egress because of either (a) Egress Credits or (b) QPI BL IGR credits for remote requests.; This filter includes only requests coming from the local socket unc_h_tracker_pending_occupancy.remote uncore cache Data Pending Occupancy Accumulator; Remote Requests event=5,umask=2  01    Accumulates the number of transactions that have data from the memory controller until they get scheduled to the Egress.  This can be used to calculate the queuing latency for two things.  (1) If the system is waiting for snoops, this will increase.  (2) If the system can't schedule to the Egress because of either (a) Egress Credits or (b) QPI BL IGR credits for remote requests.; This filter includes only requests coming from remote sockets unc_h_txr_ad.hom uncore cache Outbound NDR Ring Transactions; Non-data Responses event=0xf,umask=4  01    Counts the number of outbound transactions on the AD ring.  This can be filtered by the NDR and SNP message classes.  See the filter descriptions for more details.; Filter for outbound NDR transactions sent on the AD ring.  NDR stands for non-data response and is generally used for completions that do not include data.  AD NDR is used for transactions to remote sockets unc_h_txr_ad_cycles_full.all uncore cache AD Egress Full; All event=0x2a,umask=3  01    AD Egress Full; Cycles full from both schedulers unc_h_txr_ad_cycles_full.sched0 uncore cache AD Egress Full; Scheduler 0 event=0x2a,umask=1  01    AD Egress Full; Filter for cycles full  from scheduler bank 0 unc_h_txr_ad_cycles_full.sched1 uncore cache AD Egress Full; Scheduler 1 event=0x2a,umask=2  01    AD Egress Full; Filter for cycles full  from scheduler bank 1 unc_h_txr_ad_cycles_ne.all uncore cache AD Egress Not Empty; All event=0x29,umask=3  01    AD Egress Not Empty; Cycles full from both schedulers unc_h_txr_ad_cycles_ne.sched0 uncore cache AD Egress Not Empty; Scheduler 0 event=0x29,umask=1  01    AD Egress Not Empty; Filter for cycles not empty  from scheduler bank 0 unc_h_txr_ad_cycles_ne.sched1 uncore cache AD Egress Not Empty; Scheduler 1 event=0x29,umask=2  01    AD Egress Not Empty; Filter for cycles not empty from scheduler bank 1 unc_h_txr_ad_inserts.all uncore cache AD Egress Allocations; All event=0x27,umask=3  01    AD Egress Allocations; Allocations from both schedulers unc_h_txr_ad_inserts.sched0 uncore cache AD Egress Allocations; Scheduler 0 event=0x27,umask=1  01    AD Egress Allocations; Filter for allocations from scheduler bank 0 unc_h_txr_ad_inserts.sched1 uncore cache AD Egress Allocations; Scheduler 1 event=0x27,umask=2  01    AD Egress Allocations; Filter for allocations from scheduler bank 1 unc_h_txr_ak_cycles_full.all uncore cache AK Egress Full; All event=0x32,umask=3  01    AK Egress Full; Cycles full from both schedulers unc_h_txr_ak_cycles_full.sched0 uncore cache AK Egress Full; Scheduler 0 event=0x32,umask=1  01    AK Egress Full; Filter for cycles full  from scheduler bank 0 unc_h_txr_ak_cycles_full.sched1 uncore cache AK Egress Full; Scheduler 1 event=0x32,umask=2  01    AK Egress Full; Filter for cycles full  from scheduler bank 1 unc_h_txr_ak_cycles_ne.all uncore cache AK Egress Not Empty; All event=0x31,umask=3  01    AK Egress Not Empty; Cycles full from both schedulers unc_h_txr_ak_cycles_ne.sched0 uncore cache AK Egress Not Empty; Scheduler 0 event=0x31,umask=1  01    AK Egress Not Empty; Filter for cycles not empty  from scheduler bank 0 unc_h_txr_ak_cycles_ne.sched1 uncore cache AK Egress Not Empty; Scheduler 1 event=0x31,umask=2  01    AK Egress Not Empty; Filter for cycles not empty from scheduler bank 1 unc_h_txr_ak_inserts.all uncore cache AK Egress Allocations; All event=0x2f,umask=3  01    AK Egress Allocations; Allocations from both schedulers unc_h_txr_ak_inserts.sched0 uncore cache AK Egress Allocations; Scheduler 0 event=0x2f,umask=1  01    AK Egress Allocations; Filter for allocations from scheduler bank 0 unc_h_txr_ak_inserts.sched1 uncore cache AK Egress Allocations; Scheduler 1 event=0x2f,umask=2  01    AK Egress Allocations; Filter for allocations from scheduler bank 1 unc_h_txr_bl.drs_cache uncore cache Outbound DRS Ring Transactions to Cache; Data to Cache event=0x10,umask=1  01    Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.; Filter for data being sent to the cache unc_h_txr_bl.drs_core uncore cache Outbound DRS Ring Transactions to Cache; Data to Core event=0x10,umask=2  01    Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.; Filter for data being sent directly to the requesting core unc_h_txr_bl.drs_qpi uncore cache Outbound DRS Ring Transactions to Cache; Data to QPI event=0x10,umask=4  01    Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.; Filter for data being sent to a remote socket over QPI unc_h_txr_bl_cycles_full.all uncore cache BL Egress Full; All event=0x36,umask=3  01    BL Egress Full; Cycles full from both schedulers unc_h_txr_bl_cycles_full.sched0 uncore cache BL Egress Full; Scheduler 0 event=0x36,umask=1  01    BL Egress Full; Filter for cycles full  from scheduler bank 0 unc_h_txr_bl_cycles_full.sched1 uncore cache BL Egress Full; Scheduler 1 event=0x36,umask=2  01    BL Egress Full; Filter for cycles full  from scheduler bank 1 unc_h_txr_bl_cycles_ne.all uncore cache BL Egress Not Empty; All event=0x35,umask=3  01    BL Egress Not Empty; Cycles full from both schedulers unc_h_txr_bl_cycles_ne.sched0 uncore cache BL Egress Not Empty; Scheduler 0 event=0x35,umask=1  01    BL Egress Not Empty; Filter for cycles not empty  from scheduler bank 0 unc_h_txr_bl_cycles_ne.sched1 uncore cache BL Egress Not Empty; Scheduler 1 event=0x35,umask=2  01    BL Egress Not Empty; Filter for cycles not empty from scheduler bank 1 unc_h_txr_bl_inserts.all uncore cache BL Egress Allocations; All event=0x33,umask=3  01    BL Egress Allocations; Allocations from both schedulers unc_h_txr_bl_inserts.sched0 uncore cache BL Egress Allocations; Scheduler 0 event=0x33,umask=1  01    BL Egress Allocations; Filter for allocations from scheduler bank 0 unc_h_txr_bl_inserts.sched1 uncore cache BL Egress Allocations; Scheduler 1 event=0x33,umask=2  01    BL Egress Allocations; Filter for allocations from scheduler bank 1 unc_h_txr_starved.ak uncore cache Injection Starvation; For AK Ring event=0x6d,umask=1  01    Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time unc_h_txr_starved.bl uncore cache Injection Starvation; For BL Ring event=0x6d,umask=2  01    Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time unc_h_wpq_cycles_no_reg_credits.chn0 uncore cache HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0 event=0x18,umask=1  01    Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the regular credits  Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only unc_h_wpq_cycles_no_reg_credits.chn1 uncore cache HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1 event=0x18,umask=2  01    Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the regular credits  Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only unc_h_wpq_cycles_no_reg_credits.chn2 uncore cache HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2 event=0x18,umask=4  01    Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the regular credits  Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only unc_h_wpq_cycles_no_reg_credits.chn3 uncore cache HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3 event=0x18,umask=8  01    Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the regular credits  Common high bandwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only unc_h_wpq_cycles_no_spec_credits.chn0 uncore cache HA iMC CHN0 WPQ Credits Empty - Special; Channel 0 event=0x19,umask=1  01    Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the special credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only unc_h_wpq_cycles_no_spec_credits.chn1 uncore cache HA iMC CHN0 WPQ Credits Empty - Special; Channel 1 event=0x19,umask=2  01    Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the special credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only unc_h_wpq_cycles_no_spec_credits.chn2 uncore cache HA iMC CHN0 WPQ Credits Empty - Special; Channel 2 event=0x19,umask=4  01    Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the special credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only unc_h_wpq_cycles_no_spec_credits.chn3 uncore cache HA iMC CHN0 WPQ Credits Empty - Special; Channel 3 event=0x19,umask=8  01    Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the special credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only uncore_irp unc_i_cache_total_occupancy.any uncore interconnect Total Write Cache Occupancy; Any Source event=0x12,umask=1  01    Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port unc_i_cache_total_occupancy.source uncore interconnect Total Write Cache Occupancy; Select Source event=0x12,umask=2  01    Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register.  This register allows one to select one specific queue.  It is not possible to monitor multiple queues at a time unc_i_clockticks uncore interconnect Clocks in the IRP event=0  01    Number of clocks in the IRP unc_i_coherent_ops.clflush uncore interconnect Coherent Ops; CLFlush event=0x13,umask=0x80  01    Counts the number of coherency related operations serviced by the IRP unc_i_coherent_ops.crd uncore interconnect Coherent Ops; CRd event=0x13,umask=2  01    Counts the number of coherency related operations serviced by the IRP unc_i_coherent_ops.drd uncore interconnect Coherent Ops; DRd event=0x13,umask=4  01    Counts the number of coherency related operations serviced by the IRP unc_i_coherent_ops.pcidcahint uncore interconnect Coherent Ops; PCIDCAHin5t event=0x13,umask=0x20  01    Counts the number of coherency related operations serviced by the IRP unc_i_coherent_ops.pcirdcur uncore interconnect Coherent Ops; PCIRdCur event=0x13,umask=1  01    Counts the number of coherency related operations serviced by the IRP unc_i_coherent_ops.pcitom uncore interconnect Coherent Ops; PCIItoM event=0x13,umask=0x10  01    Counts the number of coherency related operations serviced by the IRP unc_i_coherent_ops.rfo uncore interconnect Coherent Ops; RFO event=0x13,umask=8  01    Counts the number of coherency related operations serviced by the IRP unc_i_coherent_ops.wbmtoi uncore interconnect Coherent Ops; WbMtoI event=0x13,umask=0x40  01    Counts the number of coherency related operations serviced by the IRP unc_i_misc0.2nd_atomic_insert uncore interconnect Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary event=0x14,umask=0x10  01    Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary unc_i_misc0.2nd_rd_insert uncore interconnect Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary event=0x14,umask=4  01    Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary unc_i_misc0.2nd_wr_insert uncore interconnect Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary event=0x14,umask=8  01    Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary unc_i_misc0.fast_rej uncore interconnect Misc Events - Set 0; Fastpath Rejects event=0x14,umask=2  01    Counts Timeouts - Set 0 : Fastpath Rejects unc_i_misc0.fast_req uncore interconnect Misc Events - Set 0; Fastpath Requests event=0x14,umask=1  01    Counts Timeouts - Set 0 : Fastpath Requests unc_i_misc0.fast_xfer uncore interconnect Misc Events - Set 0; Fastpath Transfers From Primary to Secondary event=0x14,umask=0x20  01    Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary unc_i_misc0.pf_ack_hint uncore interconnect Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary event=0x14,umask=0x40  01    Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary unc_i_misc0.pf_timeout uncore interconnect Misc Events - Set 0; Prefetch TimeOut event=0x14,umask=0x80  01    Indicates the fetch for a previous prefetch wasn't accepted by the prefetch.   This happens in the case of a prefetch TimeOut unc_i_misc1.data_throttle uncore interconnect Misc Events - Set 1; Data Throttled event=0x15,umask=0x80  01    IRP throttled switch data unc_i_misc1.lost_fwd uncore interconnect Misc Events - Set 1 event=0x15,umask=0x10  01    Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed unc_i_misc1.sec_rcvd_invld uncore interconnect Misc Events - Set 1; Received Invalid event=0x15,umask=0x20  01    Secondary received a transfer that did not have sufficient MESI state unc_i_misc1.sec_rcvd_vld uncore interconnect Misc Events - Set 1; Received Valid event=0x15,umask=0x40  01    Secondary received a transfer that did have sufficient MESI state unc_i_misc1.slow_e uncore interconnect Misc Events - Set 1; Slow Transfer of E Line event=0x15,umask=4  01    Secondary received a transfer that did have sufficient MESI state unc_i_misc1.slow_i uncore interconnect Misc Events - Set 1; Slow Transfer of I Line event=0x15,umask=1  01    Snoop took cacheline ownership before write from data was committed unc_i_misc1.slow_m uncore interconnect Misc Events - Set 1; Slow Transfer of M Line event=0x15,umask=8  01    Snoop took cacheline ownership before write from data was committed unc_i_misc1.slow_s uncore interconnect Misc Events - Set 1; Slow Transfer of S Line event=0x15,umask=2  01    Secondary received a transfer that did not have sufficient MESI state unc_i_rxr_ak_inserts uncore interconnect AK Ingress Occupancy event=0xa  01    Counts the number of allocations into the AK Ingress.  This queue is where the IRP receives responses from R2PCIe (the ring) unc_i_rxr_bl_drs_cycles_full uncore interconnect UNC_I_RxR_BL_DRS_CYCLES_FULL event=4  01    Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_drs_inserts uncore interconnect BL Ingress Occupancy - DRS event=1  01    Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_drs_occupancy uncore interconnect UNC_I_RxR_BL_DRS_OCCUPANCY event=7  01    Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_ncb_cycles_full uncore interconnect UNC_I_RxR_BL_NCB_CYCLES_FULL event=5  01    Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_ncb_inserts uncore interconnect BL Ingress Occupancy - NCB event=2  01    Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_ncb_occupancy uncore interconnect UNC_I_RxR_BL_NCB_OCCUPANCY event=8  01    Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_ncs_cycles_full uncore interconnect UNC_I_RxR_BL_NCS_CYCLES_FULL event=6  01    Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_ncs_inserts uncore interconnect BL Ingress Occupancy - NCS event=3  01    Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_ncs_occupancy uncore interconnect UNC_I_RxR_BL_NCS_OCCUPANCY event=9  01    Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requests as well as outbound MMIO writes unc_i_snoop_resp.hit_es uncore interconnect Snoop Responses; Hit E or S event=0x17,umask=4  01    Snoop Responses : Hit E or S unc_i_snoop_resp.hit_i uncore interconnect Snoop Responses; Hit I event=0x17,umask=2  01    Snoop Responses : Hit I unc_i_snoop_resp.hit_m uncore interconnect Snoop Responses; Hit M event=0x17,umask=8  01    Snoop Responses : Hit M unc_i_snoop_resp.miss uncore interconnect Snoop Responses; Miss event=0x17,umask=1  01    Snoop Responses : Miss unc_i_snoop_resp.snpcode uncore interconnect Snoop Responses; SnpCode event=0x17,umask=0x10  01    Snoop Responses : SnpCode unc_i_snoop_resp.snpdata uncore interconnect Snoop Responses; SnpData event=0x17,umask=0x20  01    Snoop Responses : SnpData unc_i_snoop_resp.snpinv uncore interconnect Snoop Responses; SnpInv event=0x17,umask=0x40  01    Snoop Responses : SnpInv unc_i_transactions.atomic uncore interconnect Inbound Transaction Count; Atomic event=0x16,umask=0x10  01    Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of atomic transactions unc_i_transactions.other uncore interconnect Inbound Transaction Count; Other event=0x16,umask=0x20  01    Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of 'other' kinds of transactions unc_i_transactions.rd_pref uncore interconnect Inbound Transaction Count; Read Prefetches event=0x16,umask=4  01    Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches unc_i_transactions.reads uncore interconnect Inbound Transaction Count; Reads event=0x16,umask=1  01    Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches) unc_i_transactions.writes uncore interconnect Inbound Transaction Count; Writes event=0x16,umask=2  01    Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only write requests.  Each write request should have a prefetch, so there is no need to explicitly track these requests unc_i_transactions.wr_pref uncore interconnect Inbound Transaction Count; Write Prefetches event=0x16,umask=8  01    Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of write prefetches unc_i_txr_ad_stall_credit_cycles uncore interconnect No AD Egress Credit Stalls event=0x18  01    Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available unc_i_txr_bl_stall_credit_cycles uncore interconnect No BL Egress Credit Stalls event=0x19  01    Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available unc_i_txr_data_inserts_ncb uncore interconnect Outbound Read Requests event=0xe  01    Counts the number of requests issued to the switch (towards the devices) unc_i_txr_data_inserts_ncs uncore interconnect Outbound Read Requests event=0xf  01    Counts the number of requests issued to the switch (towards the devices) unc_i_txr_request_occupancy uncore interconnect Outbound Request Queue Occupancy event=0xd  01    Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices).  This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests uncore_ubox unc_u_event_msg.doorbell_rcvd uncore interconnect VLW Received event=0x42,umask=8  01    Virtual Logical Wire (legacy) message were received from Uncore.   Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID unc_u_filter_match.disable uncore interconnect Filter Match event=0x41,umask=2  01    Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID unc_u_filter_match.enable uncore interconnect Filter Match event=0x41,umask=1  01    Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID unc_u_filter_match.u2c_disable uncore interconnect Filter Match event=0x41,umask=8  01    Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID unc_u_filter_match.u2c_enable uncore interconnect Filter Match event=0x41,umask=4  01    Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID unc_u_phold_cycles.assert_to_ack uncore interconnect Cycles PHOLD Assert to Ack; Assert to ACK event=0x45,umask=1  01    PHOLD cycles.  Filter from source CoreID unc_u_racu_requests uncore interconnect RACU Request event=0x46  01    Number outstanding register requests within message channel tracker unc_u_u2c_events.cmc uncore interconnect Monitor Sent to T0; Correctable Machine Check event=0x43,umask=0x10  01    Events coming from Uncore can be sent to one or all cores unc_u_u2c_events.livelock uncore interconnect Monitor Sent to T0; Livelock event=0x43,umask=4  01    Events coming from Uncore can be sent to one or all cores; Filter by core unc_u_u2c_events.lterror uncore interconnect Monitor Sent to T0; LTError event=0x43,umask=8  01    Events coming from Uncore can be sent to one or all cores; Filter by core unc_u_u2c_events.monitor_t0 uncore interconnect Monitor Sent to T0; Monitor T0 event=0x43,umask=1  01    Events coming from Uncore can be sent to one or all cores; Filter by core unc_u_u2c_events.monitor_t1 uncore interconnect Monitor Sent to T0; Monitor T1 event=0x43,umask=2  01    Events coming from Uncore can be sent to one or all cores; Filter by core unc_u_u2c_events.other uncore interconnect Monitor Sent to T0; Other event=0x43,umask=0x80  01    Events coming from Uncore can be sent to one or all cores; PREQ, PSMI, P2U, Thermal, PCUSMI, PMI unc_u_u2c_events.trap uncore interconnect Monitor Sent to T0; Trap event=0x43,umask=0x40  01    Events coming from Uncore can be sent to one or all cores unc_u_u2c_events.umc uncore interconnect Monitor Sent to T0; Uncorrectable Machine Check event=0x43,umask=0x20  01    Events coming from Uncore can be sent to one or all cores uncore_r2pcie unc_r2_clockticks uncore io Number of uclks in domain event=1  01    Counts the number of uclks in the R2PCIe uclk domain.  This could be slightly different than the count in the Ubox because of enable/freeze delays.  However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles unc_r2_iio_credit.isoch_qpi0 uncore io UNC_R2_IIO_CREDIT.ISOCH_QPI0 event=0x2d,umask=4  01     unc_r2_iio_credit.isoch_qpi1 uncore io UNC_R2_IIO_CREDIT.ISOCH_QPI1 event=0x2d,umask=8  01     unc_r2_iio_credit.prq_qpi0 uncore io UNC_R2_IIO_CREDIT.PRQ_QPI0 event=0x2d,umask=1  01     unc_r2_iio_credit.prq_qpi1 uncore io UNC_R2_IIO_CREDIT.PRQ_QPI1 event=0x2d,umask=2  01     unc_r2_iio_credits_acquired.drs uncore io R2PCIe IIO Credit Acquired; DRS event=0x33,umask=8  01    Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class unc_r2_iio_credits_acquired.ncb uncore io R2PCIe IIO Credit Acquired; NCB event=0x33,umask=0x10  01    Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class unc_r2_iio_credits_acquired.ncs uncore io R2PCIe IIO Credit Acquired; NCS event=0x33,umask=0x20  01    Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class unc_r2_iio_credits_used.drs uncore io R2PCIe IIO Credits in Use; DRS event=0x32,umask=8  01    Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class unc_r2_iio_credits_used.ncb uncore io R2PCIe IIO Credits in Use; NCB event=0x32,umask=0x10  01    Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class unc_r2_iio_credits_used.ncs uncore io R2PCIe IIO Credits in Use; NCS event=0x32,umask=0x20  01    Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class unc_r2_ring_ad_used.all uncore io R2 AD Ring in Use; All event=7,umask=0xf  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ad_used.ccw uncore io R2 AD Ring in Use; Counterclockwise event=7,umask=0xc  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ad_used.ccw_even uncore io R2 AD Ring in Use; Counterclockwise and Even event=7,umask=4  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity unc_r2_ring_ad_used.ccw_odd uncore io R2 AD Ring in Use; Counterclockwise and Odd event=7,umask=8  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity unc_r2_ring_ad_used.cw uncore io R2 AD Ring in Use; Clockwise event=7,umask=3  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ad_used.cw_even uncore io R2 AD Ring in Use; Clockwise and Even event=7,umask=1  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity unc_r2_ring_ad_used.cw_odd uncore io R2 AD Ring in Use; Clockwise and Odd event=7,umask=2  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity unc_r2_ring_ak_bounces.dn uncore io AK Ingress Bounced; Dn event=0x12,umask=2  01    Counts the number of times when a request destined for the AK ingress bounced unc_r2_ring_ak_bounces.up uncore io AK Ingress Bounced; Up event=0x12,umask=1  01    Counts the number of times when a request destined for the AK ingress bounced unc_r2_ring_ak_used.all uncore io R2 AK Ring in Use; All event=8,umask=0xf  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ak_used.ccw uncore io R2 AK Ring in Use; Counterclockwise event=8,umask=0xc  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ak_used.ccw_even uncore io R2 AK Ring in Use; Counterclockwise and Even event=8,umask=4  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity unc_r2_ring_ak_used.ccw_odd uncore io R2 AK Ring in Use; Counterclockwise and Odd event=8,umask=8  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity unc_r2_ring_ak_used.cw uncore io R2 AK Ring in Use; Clockwise event=8,umask=3  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ak_used.cw_even uncore io R2 AK Ring in Use; Clockwise and Even event=8,umask=1  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity unc_r2_ring_ak_used.cw_odd uncore io R2 AK Ring in Use; Clockwise and Odd event=8,umask=2  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity unc_r2_ring_bl_used.all uncore io R2 BL Ring in Use; All event=9,umask=0xf  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_bl_used.ccw uncore io R2 BL Ring in Use; Counterclockwise event=9,umask=0xc  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_bl_used.ccw_even uncore io R2 BL Ring in Use; Counterclockwise and Even event=9,umask=4  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity unc_r2_ring_bl_used.ccw_odd uncore io R2 BL Ring in Use; Counterclockwise and Odd event=9,umask=8  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity unc_r2_ring_bl_used.cw uncore io R2 BL Ring in Use; Clockwise event=9,umask=3  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_bl_used.cw_even uncore io R2 BL Ring in Use; Clockwise and Even event=9,umask=1  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity unc_r2_ring_bl_used.cw_odd uncore io R2 BL Ring in Use; Clockwise and Odd event=9,umask=2  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity unc_r2_ring_iv_used.any uncore io R2 IV Ring in Use; Any event=0xa,umask=0xf  01    Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop unc_r2_ring_iv_used.ccw uncore io R2 IV Ring in Use; Counterclockwise event=0xa,umask=0xc  01    Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop unc_r2_ring_iv_used.cw uncore io R2 IV Ring in Use; Clockwise event=0xa,umask=3  01    Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop unc_r2_rxr_cycles_ne.ncb uncore io Ingress Cycles Not Empty; NCB event=0x10,umask=0x10  01    Counts the number of cycles when the R2PCIe Ingress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue unc_r2_rxr_cycles_ne.ncs uncore io Ingress Cycles Not Empty; NCS event=0x10,umask=0x20  01    Counts the number of cycles when the R2PCIe Ingress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue unc_r2_rxr_inserts.ncb uncore io Ingress Allocations; NCB event=0x11,umask=0x10  01    Counts the number of allocations into the R2PCIe Ingress.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue unc_r2_rxr_inserts.ncs uncore io Ingress Allocations; NCS event=0x11,umask=0x20  01    Counts the number of allocations into the R2PCIe Ingress.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue unc_r2_rxr_occupancy.drs uncore io Ingress Occupancy Accumulator; DRS event=0x13,umask=8  01    Accumulates the occupancy of a given R2PCIe Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the R2PCIe Ingress Not Empty event to calculate average occupancy or the R2PCIe Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue unc_r2_sbo0_credits_acquired.ad uncore io SBo0 Credits Acquired; For AD Ring event=0x28,umask=1  01    Number of Sbo 0 credits acquired in a given cycle, per ring unc_r2_sbo0_credits_acquired.bl uncore io SBo0 Credits Acquired; For BL Ring event=0x28,umask=2  01    Number of Sbo 0 credits acquired in a given cycle, per ring unc_r2_sbo0_credit_occupancy.ad uncore io SBo0 Credits Occupancy; For AD Ring event=0x2a,umask=1  01    Number of Sbo 0 credits in use in a given cycle, per ring unc_r2_sbo0_credit_occupancy.bl uncore io SBo0 Credits Occupancy; For BL Ring event=0x2a,umask=2  01    Number of Sbo 0 credits in use in a given cycle, per ring unc_r2_stall_no_sbo_credit.sbo0_ad uncore io Stall on No Sbo Credits; For SBo0, AD Ring event=0x2c,umask=1  01    Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring unc_r2_stall_no_sbo_credit.sbo0_bl uncore io Stall on No Sbo Credits; For SBo0, BL Ring event=0x2c,umask=4  01    Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring unc_r2_stall_no_sbo_credit.sbo1_ad uncore io Stall on No Sbo Credits; For SBo1, AD Ring event=0x2c,umask=2  01    Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring unc_r2_stall_no_sbo_credit.sbo1_bl uncore io Stall on No Sbo Credits; For SBo1, BL Ring event=0x2c,umask=8  01    Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring unc_r2_txr_cycles_full.ad uncore io Egress Cycles Full; AD event=0x25,umask=1  01    Counts the number of cycles when the R2PCIe Egress buffer is full.; AD Egress Queue unc_r2_txr_cycles_full.ak uncore io Egress Cycles Full; AK event=0x25,umask=2  01    Counts the number of cycles when the R2PCIe Egress buffer is full.; AK Egress Queue unc_r2_txr_cycles_full.bl uncore io Egress Cycles Full; BL event=0x25,umask=4  01    Counts the number of cycles when the R2PCIe Egress buffer is full.; BL Egress Queue unc_r2_txr_cycles_ne.ad uncore io Egress Cycles Not Empty; AD event=0x23,umask=1  01    Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.; AD Egress Queue unc_r2_txr_cycles_ne.ak uncore io Egress Cycles Not Empty; AK event=0x23,umask=2  01    Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.; AK Egress Queue unc_r2_txr_cycles_ne.bl uncore io Egress Cycles Not Empty; BL event=0x23,umask=4  01    Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.; BL Egress Queue unc_r2_txr_nack_cw.dn_ad uncore io Egress CCW NACK; AD CCW event=0x26,umask=1  01    AD CounterClockwise Egress Queue unc_r2_txr_nack_cw.dn_ak uncore io Egress CCW NACK; AK CCW event=0x26,umask=4  01    AK CounterClockwise Egress Queue unc_r2_txr_nack_cw.dn_bl uncore io Egress CCW NACK; BL CCW event=0x26,umask=2  01    BL CounterClockwise Egress Queue unc_r2_txr_nack_cw.up_ad uncore io Egress CCW NACK; AK CCW event=0x26,umask=8  01    BL CounterClockwise Egress Queue unc_r2_txr_nack_cw.up_ak uncore io Egress CCW NACK; BL CW event=0x26,umask=0x20  01    AD Clockwise Egress Queue unc_r2_txr_nack_cw.up_bl uncore io Egress CCW NACK; BL CCW event=0x26,umask=0x10  01    AD CounterClockwise Egress Queue unc_m_act_count.byp uncore memory DRAM Activate Count; Activate due to Write event=1,umask=8  01    Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_m_act_count.rd uncore memory DRAM Activate Count; Activate due to Read event=1,umask=1  01    Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_m_act_count.wr uncore memory DRAM Activate Count; Activate due to Write event=1,umask=2  01    Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_m_byp_cmds.act uncore memory ACT command issued by 2 cycle bypass event=0xa1,umask=1  01     unc_m_byp_cmds.cas uncore memory CAS command issued by 2 cycle bypass event=0xa1,umask=2  01     unc_m_byp_cmds.pre uncore memory PRE command issued by 2 cycle bypass event=0xa1,umask=4  01     unc_m_cas_count.all uncore memory DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre) event=4,umask=0xf  01    DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM CAS commands issued on this channel unc_m_cas_count.rd uncore memory DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills) event=4,umask=3  01    DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS commands issued on this channel (including underfills) unc_m_cas_count.rd_reg uncore memory DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre) event=4,umask=1  01    DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Read CAS commands issued on this channel.  This includes both regular RD CAS commands as well as those with implicit Precharge.  AutoPre is only used in systems that are using closed page policy.  We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills) unc_m_cas_count.rd_rmm uncore memory DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in RMM event=4,umask=0x20  01     unc_m_cas_count.rd_underfill uncore memory DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued event=4,umask=2  01    DRAM RD_CAS and WR_CAS Commands; Counts the number of underfill reads that are issued by the memory controller.  This will generally be about the same as the number of partial writes, but may be slightly less because of partials hitting in the WPQ.  While it is possible for underfills to be issed in both WMM and RMM, this event counts both unc_m_cas_count.rd_wmm uncore memory DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in WMM event=4,umask=0x10  01     unc_m_cas_count.wr uncore memory DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes) event=4,umask=0xc  01    DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS commands issued on this channel unc_m_cas_count.wr_rmm uncore memory DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode event=4,umask=8  01    DRAM RD_CAS and WR_CAS Commands; Counts the total number of Opportunistic DRAM Write CAS commands issued on this channel while in Read-Major-Mode unc_m_cas_count.wr_wmm uncore memory DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode event=4,umask=4  01    DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Mode unc_m_dclockticks uncore memory DRAM Clockticks event=0  01     unc_m_dram_pre_all uncore memory DRAM Precharge All Commands event=6  01    Counts the number of times that the precharge all command was sent unc_m_dram_refresh.high uncore memory Number of DRAM Refreshes Issued event=5,umask=4  01    Counts the number of refreshes issued unc_m_dram_refresh.panic uncore memory Number of DRAM Refreshes Issued event=5,umask=2  01    Counts the number of refreshes issued unc_m_ecc_correctable_errors uncore memory ECC Correctable Errors event=9  01    Counts the number of ECC errors detected and corrected by the iMC on this channel.  This counter is only useful with ECC DRAM devices.  This count will increment one time for each correction regardless of the number of bits corrected.  The iMC can correct up to 4 bit errors in independent channel mode and 8 bit errors in lockstep mode unc_m_major_modes.isoch uncore memory Cycles in a Major Mode; Isoch Major Mode event=7,umask=8  01    Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group these two modes together so that we can use four counters to track each of the major modes at one time.  These major modes are used whenever there is an ISOCH txn in the memory controller.  In these mode, only ISOCH transactions are processed unc_m_major_modes.partial uncore memory Cycles in a Major Mode; Partial Major Mode event=7,umask=4  01    Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major mode is used to drain starved underfill reads.  Regular reads and writes are blocked and only underfill reads will be processed unc_m_major_modes.read uncore memory Cycles in a Major Mode; Read Major Mode event=7,umask=1  01    Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major Mode is the default mode for the iMC, as reads are generally more critical to forward progress than writes unc_m_major_modes.write uncore memory Cycles in a Major Mode; Write Major Mode event=7,umask=2  01    Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode is triggered when the WPQ hits high occupancy and causes writes to be higher priority than reads.  This can cause blips in the available read bandwidth in the system and temporarily increase read latencies in order to achieve better bus utilizations and higher bandwidth unc_m_power_channel_dlloff uncore memory Channel DLLOFF Cycles event=0x84  01    Number of cycles when all the ranks in the channel are in CKE Slow (DLLOFF) mode unc_m_power_channel_ppd uncore memory Channel PPD Cycles event=0x85  01    Number of cycles when all the ranks in the channel are in PPD mode.  If IBT=off is enabled, then this can be used to count those cycles.  If it is not enabled, then this can count the number of cycles when that could have been taken advantage of unc_m_power_cke_cycles.rank0 uncore memory CKE_ON_CYCLES by Rank; DIMM ID event=0x83,umask=1  01    Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_cke_cycles.rank1 uncore memory CKE_ON_CYCLES by Rank; DIMM ID event=0x83,umask=2  01    Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_cke_cycles.rank2 uncore memory CKE_ON_CYCLES by Rank; DIMM ID event=0x83,umask=4  01    Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_cke_cycles.rank3 uncore memory CKE_ON_CYCLES by Rank; DIMM ID event=0x83,umask=8  01    Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_cke_cycles.rank4 uncore memory CKE_ON_CYCLES by Rank; DIMM ID event=0x83,umask=0x10  01    Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_cke_cycles.rank5 uncore memory CKE_ON_CYCLES by Rank; DIMM ID event=0x83,umask=0x20  01    Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_cke_cycles.rank6 uncore memory CKE_ON_CYCLES by Rank; DIMM ID event=0x83,umask=0x40  01    Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_cke_cycles.rank7 uncore memory CKE_ON_CYCLES by Rank; DIMM ID event=0x83,umask=0x80  01    Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_critical_throttle_cycles uncore memory Critical Throttle Cycles event=0x86  01    Counts the number of cycles when the iMC is in critical thermal throttling.  When this happens, all traffic is blocked.  This should be rare unless something bad is going on in the platform.  There is no filtering by rank for this event unc_m_power_pcu_throttling uncore memory UNC_M_POWER_PCU_THROTTLING event=0x42  01     unc_m_power_self_refresh uncore memory Clock-Enabled Self-Refresh event=0x43  01    Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock.  This happens in some package C-states.  For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing.  One use of this is for Monroe technology.  Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases unc_m_power_throttle_cycles.rank0 uncore memory Throttle Cycles for Rank 0; DIMM ID event=0x41,umask=1  01    Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.; Thermal throttling is performed per DIMM.  We support 3 DIMMs per channel.  This ID allows us to filter by ID unc_m_power_throttle_cycles.rank1 uncore memory Throttle Cycles for Rank 0; DIMM ID event=0x41,umask=2  01    Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1 unc_m_power_throttle_cycles.rank2 uncore memory Throttle Cycles for Rank 0; DIMM ID event=0x41,umask=4  01    Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1 unc_m_power_throttle_cycles.rank3 uncore memory Throttle Cycles for Rank 0; DIMM ID event=0x41,umask=8  01    Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1 unc_m_power_throttle_cycles.rank4 uncore memory Throttle Cycles for Rank 0; DIMM ID event=0x41,umask=0x10  01    Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1 unc_m_power_throttle_cycles.rank5 uncore memory Throttle Cycles for Rank 0; DIMM ID event=0x41,umask=0x20  01    Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1 unc_m_power_throttle_cycles.rank6 uncore memory Throttle Cycles for Rank 0; DIMM ID event=0x41,umask=0x40  01    Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1 unc_m_power_throttle_cycles.rank7 uncore memory Throttle Cycles for Rank 0; DIMM ID event=0x41,umask=0x80  01    Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1 unc_m_preemption.rd_preempt_rd uncore memory Read Preemption Count; Read over Read Preemption event=8,umask=1  01    Counts the number of times a read in the iMC preempts another read or write.  Generally reads to an open page are issued ahead of requests to closed pages.  This improves the page hit rate of the system.  However, high priority requests can cause pages of active requests to be closed in order to get them out.  This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts another read unc_m_preemption.rd_preempt_wr uncore memory Read Preemption Count; Read over Write Preemption event=8,umask=2  01    Counts the number of times a read in the iMC preempts another read or write.  Generally reads to an open page are issued ahead of requests to closed pages.  This improves the page hit rate of the system.  However, high priority requests can cause pages of active requests to be closed in order to get them out.  This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts a write unc_m_pre_count.byp uncore memory DRAM Precharge commands.; Precharge due to bypass event=2,umask=0x10  01    Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.page_close uncore memory DRAM Precharge commands.; Precharge due to timer expiration event=2,umask=2  01    Counts the number of DRAM Precharge commands sent on this channel.; Counts the number of DRAM Precharge commands sent on this channel as a result of the page close counter expiring.  This does not include implicit precharge commands sent in auto-precharge mode unc_m_pre_count.page_miss uncore memory DRAM Precharge commands.; Precharges due to page miss event=2,umask=1  01    Counts the number of DRAM Precharge commands sent on this channel.; Counts the number of DRAM Precharge commands sent on this channel as a result of page misses.  This does not include explicit precharge commands sent with CAS commands in Auto-Precharge mode.  This does not include PRE commands sent as a result of the page close counter expiration unc_m_pre_count.rd uncore memory DRAM Precharge commands.; Precharge due to read event=2,umask=4  01    Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.wr uncore memory DRAM Precharge commands.; Precharge due to write event=2,umask=8  01    Counts the number of DRAM Precharge commands sent on this channel unc_m_rd_cas_prio.high uncore memory Read CAS issued with HIGH priority event=0xa0,umask=4  01     unc_m_rd_cas_prio.low uncore memory Read CAS issued with LOW priority event=0xa0,umask=1  01     unc_m_rd_cas_prio.med uncore memory Read CAS issued with MEDIUM priority event=0xa0,umask=2  01     unc_m_rd_cas_prio.panic uncore memory Read CAS issued with PANIC NON ISOCH priority (starved) event=0xa0,umask=8  01     unc_m_rd_cas_rank0.allbanks uncore memory RD_CAS Access to Rank 0; All Banks event=0xb0,umask=0x10  01    RD_CAS Access to Rank 0 : All Banks unc_m_rd_cas_rank0.bank0 uncore memory RD_CAS Access to Rank 0; Bank 0 event=0xb0  01    RD_CAS Access to Rank 0 : Bank 0 unc_m_rd_cas_rank0.bank1 uncore memory RD_CAS Access to Rank 0; Bank 1 event=0xb0,umask=1  01    RD_CAS Access to Rank 0 : Bank 1 unc_m_rd_cas_rank0.bank10 uncore memory RD_CAS Access to Rank 0; Bank 10 event=0xb0,umask=0xa  01    RD_CAS Access to Rank 0 : Bank 10 unc_m_rd_cas_rank0.bank11 uncore memory RD_CAS Access to Rank 0; Bank 11 event=0xb0,umask=0xb  01    RD_CAS Access to Rank 0 : Bank 11 unc_m_rd_cas_rank0.bank12 uncore memory RD_CAS Access to Rank 0; Bank 12 event=0xb0,umask=0xc  01    RD_CAS Access to Rank 0 : Bank 12 unc_m_rd_cas_rank0.bank13 uncore memory RD_CAS Access to Rank 0; Bank 13 event=0xb0,umask=0xd  01    RD_CAS Access to Rank 0 : Bank 13 unc_m_rd_cas_rank0.bank14 uncore memory RD_CAS Access to Rank 0; Bank 14 event=0xb0,umask=0xe  01    RD_CAS Access to Rank 0 : Bank 14 unc_m_rd_cas_rank0.bank15 uncore memory RD_CAS Access to Rank 0; Bank 15 event=0xb0,umask=0xf  01    RD_CAS Access to Rank 0 : Bank 15 unc_m_rd_cas_rank0.bank2 uncore memory RD_CAS Access to Rank 0; Bank 2 event=0xb0,umask=2  01    RD_CAS Access to Rank 0 : Bank 2 unc_m_rd_cas_rank0.bank3 uncore memory RD_CAS Access to Rank 0; Bank 3 event=0xb0,umask=3  01    RD_CAS Access to Rank 0 : Bank 3 unc_m_rd_cas_rank0.bank4 uncore memory RD_CAS Access to Rank 0; Bank 4 event=0xb0,umask=4  01    RD_CAS Access to Rank 0 : Bank 4 unc_m_rd_cas_rank0.bank5 uncore memory RD_CAS Access to Rank 0; Bank 5 event=0xb0,umask=5  01    RD_CAS Access to Rank 0 : Bank 5 unc_m_rd_cas_rank0.bank6 uncore memory RD_CAS Access to Rank 0; Bank 6 event=0xb0,umask=6  01    RD_CAS Access to Rank 0 : Bank 6 unc_m_rd_cas_rank0.bank7 uncore memory RD_CAS Access to Rank 0; Bank 7 event=0xb0,umask=7  01    RD_CAS Access to Rank 0 : Bank 7 unc_m_rd_cas_rank0.bank8 uncore memory RD_CAS Access to Rank 0; Bank 8 event=0xb0,umask=8  01    RD_CAS Access to Rank 0 : Bank 8 unc_m_rd_cas_rank0.bank9 uncore memory RD_CAS Access to Rank 0; Bank 9 event=0xb0,umask=9  01    RD_CAS Access to Rank 0 : Bank 9 unc_m_rd_cas_rank0.bankg0 uncore memory RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3) event=0xb0,umask=0x11  01    RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_rd_cas_rank0.bankg1 uncore memory RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7) event=0xb0,umask=0x12  01    RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_rd_cas_rank0.bankg2 uncore memory RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11) event=0xb0,umask=0x13  01    RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_rd_cas_rank0.bankg3 uncore memory RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15) event=0xb0,umask=0x14  01    RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_rd_cas_rank1.allbanks uncore memory RD_CAS Access to Rank 1; All Banks event=0xb1,umask=0x10  01    RD_CAS Access to Rank 0 : All Banks unc_m_rd_cas_rank1.bank0 uncore memory RD_CAS Access to Rank 1; Bank 0 event=0xb1  01    RD_CAS Access to Rank 0 : Bank 0 unc_m_rd_cas_rank1.bank1 uncore memory RD_CAS Access to Rank 1; Bank 1 event=0xb1,umask=1  01    RD_CAS Access to Rank 0 : Bank 1 unc_m_rd_cas_rank1.bank10 uncore memory RD_CAS Access to Rank 1; Bank 10 event=0xb1,umask=0xa  01    RD_CAS Access to Rank 0 : Bank 10 unc_m_rd_cas_rank1.bank11 uncore memory RD_CAS Access to Rank 1; Bank 11 event=0xb1,umask=0xb  01    RD_CAS Access to Rank 0 : Bank 11 unc_m_rd_cas_rank1.bank12 uncore memory RD_CAS Access to Rank 1; Bank 12 event=0xb1,umask=0xc  01    RD_CAS Access to Rank 0 : Bank 12 unc_m_rd_cas_rank1.bank13 uncore memory RD_CAS Access to Rank 1; Bank 13 event=0xb1,umask=0xd  01    RD_CAS Access to Rank 0 : Bank 13 unc_m_rd_cas_rank1.bank14 uncore memory RD_CAS Access to Rank 1; Bank 14 event=0xb1,umask=0xe  01    RD_CAS Access to Rank 0 : Bank 14 unc_m_rd_cas_rank1.bank15 uncore memory RD_CAS Access to Rank 1; Bank 15 event=0xb1,umask=0xf  01    RD_CAS Access to Rank 0 : Bank 15 unc_m_rd_cas_rank1.bank2 uncore memory RD_CAS Access to Rank 1; Bank 2 event=0xb1,umask=2  01    RD_CAS Access to Rank 0 : Bank 2 unc_m_rd_cas_rank1.bank3 uncore memory RD_CAS Access to Rank 1; Bank 3 event=0xb1,umask=3  01    RD_CAS Access to Rank 0 : Bank 3 unc_m_rd_cas_rank1.bank4 uncore memory RD_CAS Access to Rank 1; Bank 4 event=0xb1,umask=4  01    RD_CAS Access to Rank 0 : Bank 4 unc_m_rd_cas_rank1.bank5 uncore memory RD_CAS Access to Rank 1; Bank 5 event=0xb1,umask=5  01    RD_CAS Access to Rank 0 : Bank 5 unc_m_rd_cas_rank1.bank6 uncore memory RD_CAS Access to Rank 1; Bank 6 event=0xb1,umask=6  01    RD_CAS Access to Rank 0 : Bank 6 unc_m_rd_cas_rank1.bank7 uncore memory RD_CAS Access to Rank 1; Bank 7 event=0xb1,umask=7  01    RD_CAS Access to Rank 0 : Bank 7 unc_m_rd_cas_rank1.bank8 uncore memory RD_CAS Access to Rank 1; Bank 8 event=0xb1,umask=8  01    RD_CAS Access to Rank 0 : Bank 8 unc_m_rd_cas_rank1.bank9 uncore memory RD_CAS Access to Rank 1; Bank 9 event=0xb1,umask=9  01    RD_CAS Access to Rank 0 : Bank 9 unc_m_rd_cas_rank1.bankg0 uncore memory RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3) event=0xb1,umask=0x11  01    RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_rd_cas_rank1.bankg1 uncore memory RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7) event=0xb1,umask=0x12  01    RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_rd_cas_rank1.bankg2 uncore memory RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11) event=0xb1,umask=0x13  01    RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_rd_cas_rank1.bankg3 uncore memory RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15) event=0xb1,umask=0x14  01    RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_rd_cas_rank2.bank0 uncore memory RD_CAS Access to Rank 2; Bank 0 event=0xb2  01    RD_CAS Access to Rank 0 : Bank 0 unc_m_rd_cas_rank4.allbanks uncore memory RD_CAS Access to Rank 4; All Banks event=0xb4,umask=0x10  01    RD_CAS Access to Rank 0 : All Banks unc_m_rd_cas_rank4.bank0 uncore memory RD_CAS Access to Rank 4; Bank 0 event=0xb4  01    RD_CAS Access to Rank 0 : Bank 0 unc_m_rd_cas_rank4.bank1 uncore memory RD_CAS Access to Rank 4; Bank 1 event=0xb4,umask=1  01    RD_CAS Access to Rank 0 : Bank 1 unc_m_rd_cas_rank4.bank10 uncore memory RD_CAS Access to Rank 4; Bank 10 event=0xb4,umask=0xa  01    RD_CAS Access to Rank 0 : Bank 10 unc_m_rd_cas_rank4.bank11 uncore memory RD_CAS Access to Rank 4; Bank 11 event=0xb4,umask=0xb  01    RD_CAS Access to Rank 0 : Bank 11 unc_m_rd_cas_rank4.bank12 uncore memory RD_CAS Access to Rank 4; Bank 12 event=0xb4,umask=0xc  01    RD_CAS Access to Rank 0 : Bank 12 unc_m_rd_cas_rank4.bank13 uncore memory RD_CAS Access to Rank 4; Bank 13 event=0xb4,umask=0xd  01    RD_CAS Access to Rank 0 : Bank 13 unc_m_rd_cas_rank4.bank14 uncore memory RD_CAS Access to Rank 4; Bank 14 event=0xb4,umask=0xe  01    RD_CAS Access to Rank 0 : Bank 14 unc_m_rd_cas_rank4.bank15 uncore memory RD_CAS Access to Rank 4; Bank 15 event=0xb4,umask=0xf  01    RD_CAS Access to Rank 0 : Bank 15 unc_m_rd_cas_rank4.bank2 uncore memory RD_CAS Access to Rank 4; Bank 2 event=0xb4,umask=2  01    RD_CAS Access to Rank 0 : Bank 2 unc_m_rd_cas_rank4.bank3 uncore memory RD_CAS Access to Rank 4; Bank 3 event=0xb4,umask=3  01    RD_CAS Access to Rank 0 : Bank 3 unc_m_rd_cas_rank4.bank4 uncore memory RD_CAS Access to Rank 4; Bank 4 event=0xb4,umask=4  01    RD_CAS Access to Rank 0 : Bank 4 unc_m_rd_cas_rank4.bank5 uncore memory RD_CAS Access to Rank 4; Bank 5 event=0xb4,umask=5  01    RD_CAS Access to Rank 0 : Bank 5 unc_m_rd_cas_rank4.bank6 uncore memory RD_CAS Access to Rank 4; Bank 6 event=0xb4,umask=6  01    RD_CAS Access to Rank 0 : Bank 6 unc_m_rd_cas_rank4.bank7 uncore memory RD_CAS Access to Rank 4; Bank 7 event=0xb4,umask=7  01    RD_CAS Access to Rank 0 : Bank 7 unc_m_rd_cas_rank4.bank8 uncore memory RD_CAS Access to Rank 4; Bank 8 event=0xb4,umask=8  01    RD_CAS Access to Rank 0 : Bank 8 unc_m_rd_cas_rank4.bank9 uncore memory RD_CAS Access to Rank 4; Bank 9 event=0xb4,umask=9  01    RD_CAS Access to Rank 0 : Bank 9 unc_m_rd_cas_rank4.bankg0 uncore memory RD_CAS Access to Rank 4; Bank Group 0 (Banks 0-3) event=0xb4,umask=0x11  01    RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_rd_cas_rank4.bankg1 uncore memory RD_CAS Access to Rank 4; Bank Group 1 (Banks 4-7) event=0xb4,umask=0x12  01    RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_rd_cas_rank4.bankg2 uncore memory RD_CAS Access to Rank 4; Bank Group 2 (Banks 8-11) event=0xb4,umask=0x13  01    RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_rd_cas_rank4.bankg3 uncore memory RD_CAS Access to Rank 4; Bank Group 3 (Banks 12-15) event=0xb4,umask=0x14  01    RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_rd_cas_rank5.allbanks uncore memory RD_CAS Access to Rank 5; All Banks event=0xb5,umask=0x10  01    RD_CAS Access to Rank 0 : All Banks unc_m_rd_cas_rank5.bank0 uncore memory RD_CAS Access to Rank 5; Bank 0 event=0xb5  01    RD_CAS Access to Rank 0 : Bank 0 unc_m_rd_cas_rank5.bank1 uncore memory RD_CAS Access to Rank 5; Bank 1 event=0xb5,umask=1  01    RD_CAS Access to Rank 0 : Bank 1 unc_m_rd_cas_rank5.bank10 uncore memory RD_CAS Access to Rank 5; Bank 10 event=0xb5,umask=0xa  01    RD_CAS Access to Rank 0 : Bank 10 unc_m_rd_cas_rank5.bank11 uncore memory RD_CAS Access to Rank 5; Bank 11 event=0xb5,umask=0xb  01    RD_CAS Access to Rank 0 : Bank 11 unc_m_rd_cas_rank5.bank12 uncore memory RD_CAS Access to Rank 5; Bank 12 event=0xb5,umask=0xc  01    RD_CAS Access to Rank 0 : Bank 12 unc_m_rd_cas_rank5.bank13 uncore memory RD_CAS Access to Rank 5; Bank 13 event=0xb5,umask=0xd  01    RD_CAS Access to Rank 0 : Bank 13 unc_m_rd_cas_rank5.bank14 uncore memory RD_CAS Access to Rank 5; Bank 14 event=0xb5,umask=0xe  01    RD_CAS Access to Rank 0 : Bank 14 unc_m_rd_cas_rank5.bank15 uncore memory RD_CAS Access to Rank 5; Bank 15 event=0xb5,umask=0xf  01    RD_CAS Access to Rank 0 : Bank 15 unc_m_rd_cas_rank5.bank2 uncore memory RD_CAS Access to Rank 5; Bank 2 event=0xb5,umask=2  01    RD_CAS Access to Rank 0 : Bank 2 unc_m_rd_cas_rank5.bank3 uncore memory RD_CAS Access to Rank 5; Bank 3 event=0xb5,umask=3  01    RD_CAS Access to Rank 0 : Bank 3 unc_m_rd_cas_rank5.bank4 uncore memory RD_CAS Access to Rank 5; Bank 4 event=0xb5,umask=4  01    RD_CAS Access to Rank 0 : Bank 4 unc_m_rd_cas_rank5.bank5 uncore memory RD_CAS Access to Rank 5; Bank 5 event=0xb5,umask=5  01    RD_CAS Access to Rank 0 : Bank 5 unc_m_rd_cas_rank5.bank6 uncore memory RD_CAS Access to Rank 5; Bank 6 event=0xb5,umask=6  01    RD_CAS Access to Rank 0 : Bank 6 unc_m_rd_cas_rank5.bank7 uncore memory RD_CAS Access to Rank 5; Bank 7 event=0xb5,umask=7  01    RD_CAS Access to Rank 0 : Bank 7 unc_m_rd_cas_rank5.bank8 uncore memory RD_CAS Access to Rank 5; Bank 8 event=0xb5,umask=8  01    RD_CAS Access to Rank 0 : Bank 8 unc_m_rd_cas_rank5.bank9 uncore memory RD_CAS Access to Rank 5; Bank 9 event=0xb5,umask=9  01    RD_CAS Access to Rank 0 : Bank 9 unc_m_rd_cas_rank5.bankg0 uncore memory RD_CAS Access to Rank 5; Bank Group 0 (Banks 0-3) event=0xb5,umask=0x11  01    RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_rd_cas_rank5.bankg1 uncore memory RD_CAS Access to Rank 5; Bank Group 1 (Banks 4-7) event=0xb5,umask=0x12  01    RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_rd_cas_rank5.bankg2 uncore memory RD_CAS Access to Rank 5; Bank Group 2 (Banks 8-11) event=0xb5,umask=0x13  01    RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_rd_cas_rank5.bankg3 uncore memory RD_CAS Access to Rank 5; Bank Group 3 (Banks 12-15) event=0xb5,umask=0x14  01    RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_rd_cas_rank6.allbanks uncore memory RD_CAS Access to Rank 6; All Banks event=0xb6,umask=0x10  01    RD_CAS Access to Rank 0 : All Banks unc_m_rd_cas_rank6.bank0 uncore memory RD_CAS Access to Rank 6; Bank 0 event=0xb6  01    RD_CAS Access to Rank 0 : Bank 0 unc_m_rd_cas_rank6.bank1 uncore memory RD_CAS Access to Rank 6; Bank 1 event=0xb6,umask=1  01    RD_CAS Access to Rank 0 : Bank 1 unc_m_rd_cas_rank6.bank10 uncore memory RD_CAS Access to Rank 6; Bank 10 event=0xb6,umask=0xa  01    RD_CAS Access to Rank 0 : Bank 10 unc_m_rd_cas_rank6.bank11 uncore memory RD_CAS Access to Rank 6; Bank 11 event=0xb6,umask=0xb  01    RD_CAS Access to Rank 0 : Bank 11 unc_m_rd_cas_rank6.bank12 uncore memory RD_CAS Access to Rank 6; Bank 12 event=0xb6,umask=0xc  01    RD_CAS Access to Rank 0 : Bank 12 unc_m_rd_cas_rank6.bank13 uncore memory RD_CAS Access to Rank 6; Bank 13 event=0xb6,umask=0xd  01    RD_CAS Access to Rank 0 : Bank 13 unc_m_rd_cas_rank6.bank14 uncore memory RD_CAS Access to Rank 6; Bank 14 event=0xb6,umask=0xe  01    RD_CAS Access to Rank 0 : Bank 14 unc_m_rd_cas_rank6.bank15 uncore memory RD_CAS Access to Rank 6; Bank 15 event=0xb6,umask=0xf  01    RD_CAS Access to Rank 0 : Bank 15 unc_m_rd_cas_rank6.bank2 uncore memory RD_CAS Access to Rank 6; Bank 2 event=0xb6,umask=2  01    RD_CAS Access to Rank 0 : Bank 2 unc_m_rd_cas_rank6.bank3 uncore memory RD_CAS Access to Rank 6; Bank 3 event=0xb6,umask=3  01    RD_CAS Access to Rank 0 : Bank 3 unc_m_rd_cas_rank6.bank4 uncore memory RD_CAS Access to Rank 6; Bank 4 event=0xb6,umask=4  01    RD_CAS Access to Rank 0 : Bank 4 unc_m_rd_cas_rank6.bank5 uncore memory RD_CAS Access to Rank 6; Bank 5 event=0xb6,umask=5  01    RD_CAS Access to Rank 0 : Bank 5 unc_m_rd_cas_rank6.bank6 uncore memory RD_CAS Access to Rank 6; Bank 6 event=0xb6,umask=6  01    RD_CAS Access to Rank 0 : Bank 6 unc_m_rd_cas_rank6.bank7 uncore memory RD_CAS Access to Rank 6; Bank 7 event=0xb6,umask=7  01    RD_CAS Access to Rank 0 : Bank 7 unc_m_rd_cas_rank6.bank8 uncore memory RD_CAS Access to Rank 6; Bank 8 event=0xb6,umask=8  01    RD_CAS Access to Rank 0 : Bank 8 unc_m_rd_cas_rank6.bank9 uncore memory RD_CAS Access to Rank 6; Bank 9 event=0xb6,umask=9  01    RD_CAS Access to Rank 0 : Bank 9 unc_m_rd_cas_rank6.bankg0 uncore memory RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3) event=0xb6,umask=0x11  01    RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_rd_cas_rank6.bankg1 uncore memory RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7) event=0xb6,umask=0x12  01    RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_rd_cas_rank6.bankg2 uncore memory RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11) event=0xb6,umask=0x13  01    RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_rd_cas_rank6.bankg3 uncore memory RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15) event=0xb6,umask=0x14  01    RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_rd_cas_rank7.allbanks uncore memory RD_CAS Access to Rank 7; All Banks event=0xb7,umask=0x10  01    RD_CAS Access to Rank 0 : All Banks unc_m_rd_cas_rank7.bank0 uncore memory RD_CAS Access to Rank 7; Bank 0 event=0xb7  01    RD_CAS Access to Rank 0 : Bank 0 unc_m_rd_cas_rank7.bank1 uncore memory RD_CAS Access to Rank 7; Bank 1 event=0xb7,umask=1  01    RD_CAS Access to Rank 0 : Bank 1 unc_m_rd_cas_rank7.bank10 uncore memory RD_CAS Access to Rank 7; Bank 10 event=0xb7,umask=0xa  01    RD_CAS Access to Rank 0 : Bank 10 unc_m_rd_cas_rank7.bank11 uncore memory RD_CAS Access to Rank 7; Bank 11 event=0xb7,umask=0xb  01    RD_CAS Access to Rank 0 : Bank 11 unc_m_rd_cas_rank7.bank12 uncore memory RD_CAS Access to Rank 7; Bank 12 event=0xb7,umask=0xc  01    RD_CAS Access to Rank 0 : Bank 12 unc_m_rd_cas_rank7.bank13 uncore memory RD_CAS Access to Rank 7; Bank 13 event=0xb7,umask=0xd  01    RD_CAS Access to Rank 0 : Bank 13 unc_m_rd_cas_rank7.bank14 uncore memory RD_CAS Access to Rank 7; Bank 14 event=0xb7,umask=0xe  01    RD_CAS Access to Rank 0 : Bank 14 unc_m_rd_cas_rank7.bank15 uncore memory RD_CAS Access to Rank 7; Bank 15 event=0xb7,umask=0xf  01    RD_CAS Access to Rank 0 : Bank 15 unc_m_rd_cas_rank7.bank2 uncore memory RD_CAS Access to Rank 7; Bank 2 event=0xb7,umask=2  01    RD_CAS Access to Rank 0 : Bank 2 unc_m_rd_cas_rank7.bank3 uncore memory RD_CAS Access to Rank 7; Bank 3 event=0xb7,umask=3  01    RD_CAS Access to Rank 0 : Bank 3 unc_m_rd_cas_rank7.bank4 uncore memory RD_CAS Access to Rank 7; Bank 4 event=0xb7,umask=4  01    RD_CAS Access to Rank 0 : Bank 4 unc_m_rd_cas_rank7.bank5 uncore memory RD_CAS Access to Rank 7; Bank 5 event=0xb7,umask=5  01    RD_CAS Access to Rank 0 : Bank 5 unc_m_rd_cas_rank7.bank6 uncore memory RD_CAS Access to Rank 7; Bank 6 event=0xb7,umask=6  01    RD_CAS Access to Rank 0 : Bank 6 unc_m_rd_cas_rank7.bank7 uncore memory RD_CAS Access to Rank 7; Bank 7 event=0xb7,umask=7  01    RD_CAS Access to Rank 0 : Bank 7 unc_m_rd_cas_rank7.bank8 uncore memory RD_CAS Access to Rank 7; Bank 8 event=0xb7,umask=8  01    RD_CAS Access to Rank 0 : Bank 8 unc_m_rd_cas_rank7.bank9 uncore memory RD_CAS Access to Rank 7; Bank 9 event=0xb7,umask=9  01    RD_CAS Access to Rank 0 : Bank 9 unc_m_rd_cas_rank7.bankg0 uncore memory RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3) event=0xb7,umask=0x11  01    RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_rd_cas_rank7.bankg1 uncore memory RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7) event=0xb7,umask=0x12  01    RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_rd_cas_rank7.bankg2 uncore memory RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11) event=0xb7,umask=0x13  01    RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_rd_cas_rank7.bankg3 uncore memory RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15) event=0xb7,umask=0x14  01    RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_rpq_cycles_ne uncore memory Read Pending Queue Not Empty event=0x11  01    Counts the number of cycles that the Read Pending Queue is not empty.  This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests unc_m_rpq_inserts uncore memory Read Pending Queue Allocations event=0x10  01    Counts the number of allocations into the Read Pending Queue.  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This includes both ISOCH and non-ISOCH requests unc_m_vmse_mxb_wr_occupancy uncore memory VMSE MXB write buffer occupancy event=0x91  01     unc_m_vmse_wr_push.rmm uncore memory VMSE WR PUSH issued; VMSE write PUSH issued in RMM event=0x90,umask=2  01     unc_m_vmse_wr_push.wmm uncore memory VMSE WR PUSH issued; VMSE write PUSH issued in WMM event=0x90,umask=1  01     unc_m_wmm_to_rmm.low_thresh uncore memory Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter event=0xc0,umask=1  01     unc_m_wmm_to_rmm.starve uncore memory Transition from WMM to RMM because of low threshold event=0xc0,umask=2  01     unc_m_wmm_to_rmm.vmse_retry uncore memory Transition from WMM to RMM because of low threshold event=0xc0,umask=4  01     unc_m_wpq_cycles_full uncore memory Write Pending Queue Full Cycles event=0x22  01    Counts the number of cycles when the Write Pending Queue is full.  When the WPQ is full, the HA will not be able to issue any additional read requests into the iMC.  This count should be similar count in the HA which tracks the number of cycles that the HA has no WPQ credits, just somewhat smaller to account for the credit return overhead unc_m_wpq_cycles_ne uncore memory Write Pending Queue Not Empty event=0x21  01    Counts the number of cycles that the Write Pending Queue is not empty.  This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies unc_m_wpq_read_hit uncore memory Write Pending Queue CAM Match event=0x23  01    Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_m_wpq_write_hit uncore memory Write Pending Queue CAM Match event=0x24  01    Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_m_wrong_mm uncore memory Not getting the requested Major Mode event=0xc1  01     unc_m_wr_cas_rank0.allbanks uncore memory WR_CAS Access to Rank 0; All Banks event=0xb8,umask=0x10  01    WR_CAS Access to Rank 0 : All Banks unc_m_wr_cas_rank0.bank0 uncore memory WR_CAS Access to Rank 0; Bank 0 event=0xb8  01    WR_CAS Access to Rank 0 : Bank 0 unc_m_wr_cas_rank0.bank1 uncore memory WR_CAS Access to Rank 0; Bank 1 event=0xb8,umask=1  01    WR_CAS Access to Rank 0 : Bank 1 unc_m_wr_cas_rank0.bank10 uncore memory WR_CAS Access to Rank 0; Bank 10 event=0xb8,umask=0xa  01    WR_CAS Access to Rank 0 : Bank 10 unc_m_wr_cas_rank0.bank11 uncore memory WR_CAS Access to Rank 0; Bank 11 event=0xb8,umask=0xb  01    WR_CAS Access to Rank 0 : Bank 11 unc_m_wr_cas_rank0.bank12 uncore memory WR_CAS Access to Rank 0; Bank 12 event=0xb8,umask=0xc  01    WR_CAS Access to Rank 0 : Bank 12 unc_m_wr_cas_rank0.bank13 uncore memory WR_CAS Access to Rank 0; Bank 13 event=0xb8,umask=0xd  01    WR_CAS Access to Rank 0 : Bank 13 unc_m_wr_cas_rank0.bank14 uncore memory WR_CAS Access to Rank 0; Bank 14 event=0xb8,umask=0xe  01    WR_CAS Access to Rank 0 : Bank 14 unc_m_wr_cas_rank0.bank15 uncore memory WR_CAS Access to Rank 0; Bank 15 event=0xb8,umask=0xf  01    WR_CAS Access to Rank 0 : Bank 15 unc_m_wr_cas_rank0.bank2 uncore memory WR_CAS Access to Rank 0; Bank 2 event=0xb8,umask=2  01    WR_CAS Access to Rank 0 : Bank 2 unc_m_wr_cas_rank0.bank3 uncore memory WR_CAS Access to Rank 0; Bank 3 event=0xb8,umask=3  01    WR_CAS Access to Rank 0 : Bank 3 unc_m_wr_cas_rank0.bank4 uncore memory WR_CAS Access to Rank 0; Bank 4 event=0xb8,umask=4  01    WR_CAS Access to Rank 0 : Bank 4 unc_m_wr_cas_rank0.bank5 uncore memory WR_CAS Access to Rank 0; Bank 5 event=0xb8,umask=5  01    WR_CAS Access to Rank 0 : Bank 5 unc_m_wr_cas_rank0.bank6 uncore memory WR_CAS Access to Rank 0; Bank 6 event=0xb8,umask=6  01    WR_CAS Access to Rank 0 : Bank 6 unc_m_wr_cas_rank0.bank7 uncore memory WR_CAS Access to Rank 0; Bank 7 event=0xb8,umask=7  01    WR_CAS Access to Rank 0 : Bank 7 unc_m_wr_cas_rank0.bank8 uncore memory WR_CAS Access to Rank 0; Bank 8 event=0xb8,umask=8  01    WR_CAS Access to Rank 0 : Bank 8 unc_m_wr_cas_rank0.bank9 uncore memory WR_CAS Access to Rank 0; Bank 9 event=0xb8,umask=9  01    WR_CAS Access to Rank 0 : Bank 9 unc_m_wr_cas_rank0.bankg0 uncore memory WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3) event=0xb8,umask=0x11  01    WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_wr_cas_rank0.bankg1 uncore memory WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7) event=0xb8,umask=0x12  01    WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_wr_cas_rank0.bankg2 uncore memory WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11) event=0xb8,umask=0x13  01    WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_wr_cas_rank0.bankg3 uncore memory WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15) event=0xb8,umask=0x14  01    WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_wr_cas_rank1.allbanks uncore memory WR_CAS Access to Rank 1; All Banks event=0xb9,umask=0x10  01    WR_CAS Access to Rank 0 : All Banks unc_m_wr_cas_rank1.bank0 uncore memory WR_CAS Access to Rank 1; Bank 0 event=0xb9  01    WR_CAS Access to Rank 0 : Bank 0 unc_m_wr_cas_rank1.bank1 uncore memory WR_CAS Access to Rank 1; Bank 1 event=0xb9,umask=1  01    WR_CAS Access to Rank 0 : Bank 1 unc_m_wr_cas_rank1.bank10 uncore memory WR_CAS Access to Rank 1; Bank 10 event=0xb9,umask=0xa  01    WR_CAS Access to Rank 0 : Bank 10 unc_m_wr_cas_rank1.bank11 uncore memory WR_CAS Access to Rank 1; Bank 11 event=0xb9,umask=0xb  01    WR_CAS Access to Rank 0 : Bank 11 unc_m_wr_cas_rank1.bank12 uncore memory WR_CAS Access to Rank 1; Bank 12 event=0xb9,umask=0xc  01    WR_CAS Access to Rank 0 : Bank 12 unc_m_wr_cas_rank1.bank13 uncore memory WR_CAS Access to Rank 1; Bank 13 event=0xb9,umask=0xd  01    WR_CAS Access to Rank 0 : Bank 13 unc_m_wr_cas_rank1.bank14 uncore memory WR_CAS Access to Rank 1; Bank 14 event=0xb9,umask=0xe  01    WR_CAS Access to Rank 0 : Bank 14 unc_m_wr_cas_rank1.bank15 uncore memory WR_CAS Access to Rank 1; Bank 15 event=0xb9,umask=0xf  01    WR_CAS Access to Rank 0 : Bank 15 unc_m_wr_cas_rank1.bank2 uncore memory WR_CAS Access to Rank 1; Bank 2 event=0xb9,umask=2  01    WR_CAS Access to Rank 0 : Bank 2 unc_m_wr_cas_rank1.bank3 uncore memory WR_CAS Access to Rank 1; Bank 3 event=0xb9,umask=3  01    WR_CAS Access to Rank 0 : Bank 3 unc_m_wr_cas_rank1.bank4 uncore memory WR_CAS Access to Rank 1; Bank 4 event=0xb9,umask=4  01    WR_CAS Access to Rank 0 : Bank 4 unc_m_wr_cas_rank1.bank5 uncore memory WR_CAS Access to Rank 1; Bank 5 event=0xb9,umask=5  01    WR_CAS Access to Rank 0 : Bank 5 unc_m_wr_cas_rank1.bank6 uncore memory WR_CAS Access to Rank 1; Bank 6 event=0xb9,umask=6  01    WR_CAS Access to Rank 0 : Bank 6 unc_m_wr_cas_rank1.bank7 uncore memory WR_CAS Access to Rank 1; Bank 7 event=0xb9,umask=7  01    WR_CAS Access to Rank 0 : Bank 7 unc_m_wr_cas_rank1.bank8 uncore memory WR_CAS Access to Rank 1; Bank 8 event=0xb9,umask=8  01    WR_CAS Access to Rank 0 : Bank 8 unc_m_wr_cas_rank1.bank9 uncore memory WR_CAS Access to Rank 1; Bank 9 event=0xb9,umask=9  01    WR_CAS Access to Rank 0 : Bank 9 unc_m_wr_cas_rank1.bankg0 uncore memory WR_CAS Access to Rank 1; Bank Group 0 (Banks 0-3) event=0xb9,umask=0x11  01    WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_wr_cas_rank1.bankg1 uncore memory WR_CAS Access to Rank 1; Bank Group 1 (Banks 4-7) event=0xb9,umask=0x12  01    WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_wr_cas_rank1.bankg2 uncore memory WR_CAS Access to Rank 1; Bank Group 2 (Banks 8-11) event=0xb9,umask=0x13  01    WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_wr_cas_rank1.bankg3 uncore memory WR_CAS Access to Rank 1; Bank Group 3 (Banks 12-15) event=0xb9,umask=0x14  01    WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_wr_cas_rank4.allbanks uncore memory WR_CAS Access to Rank 4; All Banks event=0xbc,umask=0x10  01    WR_CAS Access to Rank 0 : All Banks unc_m_wr_cas_rank4.bank0 uncore memory WR_CAS Access to Rank 4; Bank 0 event=0xbc  01    WR_CAS Access to Rank 0 : Bank 0 unc_m_wr_cas_rank4.bank1 uncore memory WR_CAS Access to Rank 4; Bank 1 event=0xbc,umask=1  01    WR_CAS Access to Rank 0 : Bank 1 unc_m_wr_cas_rank4.bank10 uncore memory WR_CAS Access to Rank 4; Bank 10 event=0xbc,umask=0xa  01    WR_CAS Access to Rank 0 : Bank 10 unc_m_wr_cas_rank4.bank11 uncore memory WR_CAS Access to Rank 4; Bank 11 event=0xbc,umask=0xb  01    WR_CAS Access to Rank 0 : Bank 11 unc_m_wr_cas_rank4.bank12 uncore memory WR_CAS Access to Rank 4; Bank 12 event=0xbc,umask=0xc  01    WR_CAS Access to Rank 0 : Bank 12 unc_m_wr_cas_rank4.bank13 uncore memory WR_CAS Access to Rank 4; Bank 13 event=0xbc,umask=0xd  01    WR_CAS Access to Rank 0 : Bank 13 unc_m_wr_cas_rank4.bank14 uncore memory WR_CAS Access to Rank 4; Bank 14 event=0xbc,umask=0xe  01    WR_CAS Access to Rank 0 : Bank 14 unc_m_wr_cas_rank4.bank15 uncore memory WR_CAS Access to Rank 4; Bank 15 event=0xbc,umask=0xf  01    WR_CAS Access to Rank 0 : Bank 15 unc_m_wr_cas_rank4.bank2 uncore memory WR_CAS Access to Rank 4; Bank 2 event=0xbc,umask=2  01    WR_CAS Access to Rank 0 : Bank 2 unc_m_wr_cas_rank4.bank3 uncore memory WR_CAS Access to Rank 4; Bank 3 event=0xbc,umask=3  01    WR_CAS Access to Rank 0 : Bank 3 unc_m_wr_cas_rank4.bank4 uncore memory WR_CAS Access to Rank 4; Bank 4 event=0xbc,umask=4  01    WR_CAS Access to Rank 0 : Bank 4 unc_m_wr_cas_rank4.bank5 uncore memory WR_CAS Access to Rank 4; Bank 5 event=0xbc,umask=5  01    WR_CAS Access to Rank 0 : Bank 5 unc_m_wr_cas_rank4.bank6 uncore memory WR_CAS Access to Rank 4; Bank 6 event=0xbc,umask=6  01    WR_CAS Access to Rank 0 : Bank 6 unc_m_wr_cas_rank4.bank7 uncore memory WR_CAS Access to Rank 4; Bank 7 event=0xbc,umask=7  01    WR_CAS Access to Rank 0 : Bank 7 unc_m_wr_cas_rank4.bank8 uncore memory WR_CAS Access to Rank 4; Bank 8 event=0xbc,umask=8  01    WR_CAS Access to Rank 0 : Bank 8 unc_m_wr_cas_rank4.bank9 uncore memory WR_CAS Access to Rank 4; Bank 9 event=0xbc,umask=9  01    WR_CAS Access to Rank 0 : Bank 9 unc_m_wr_cas_rank4.bankg0 uncore memory WR_CAS Access to Rank 4; Bank Group 0 (Banks 0-3) event=0xbc,umask=0x11  01    WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_wr_cas_rank4.bankg1 uncore memory WR_CAS Access to Rank 4; Bank Group 1 (Banks 4-7) event=0xbc,umask=0x12  01    WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_wr_cas_rank4.bankg2 uncore memory WR_CAS Access to Rank 4; Bank Group 2 (Banks 8-11) event=0xbc,umask=0x13  01    WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_wr_cas_rank4.bankg3 uncore memory WR_CAS Access to Rank 4; Bank Group 3 (Banks 12-15) event=0xbc,umask=0x14  01    WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_wr_cas_rank5.allbanks uncore memory WR_CAS Access to Rank 5; All Banks event=0xbd,umask=0x10  01    WR_CAS Access to Rank 0 : All Banks unc_m_wr_cas_rank5.bank0 uncore memory WR_CAS Access to Rank 5; Bank 0 event=0xbd  01    WR_CAS Access to Rank 0 : Bank 0 unc_m_wr_cas_rank5.bank1 uncore memory WR_CAS Access to Rank 5; Bank 1 event=0xbd,umask=1  01    WR_CAS Access to Rank 0 : Bank 1 unc_m_wr_cas_rank5.bank10 uncore memory WR_CAS Access to Rank 5; Bank 10 event=0xbd,umask=0xa  01    WR_CAS Access to Rank 0 : Bank 10 unc_m_wr_cas_rank5.bank11 uncore memory WR_CAS Access to Rank 5; Bank 11 event=0xbd,umask=0xb  01    WR_CAS Access to Rank 0 : Bank 11 unc_m_wr_cas_rank5.bank12 uncore memory WR_CAS Access to Rank 5; Bank 12 event=0xbd,umask=0xc  01    WR_CAS Access to Rank 0 : Bank 12 unc_m_wr_cas_rank5.bank13 uncore memory WR_CAS Access to Rank 5; Bank 13 event=0xbd,umask=0xd  01    WR_CAS Access to Rank 0 : Bank 13 unc_m_wr_cas_rank5.bank14 uncore memory WR_CAS Access to Rank 5; Bank 14 event=0xbd,umask=0xe  01    WR_CAS Access to Rank 0 : Bank 14 unc_m_wr_cas_rank5.bank15 uncore memory WR_CAS Access to Rank 5; Bank 15 event=0xbd,umask=0xf  01    WR_CAS Access to Rank 0 : Bank 15 unc_m_wr_cas_rank5.bank2 uncore memory WR_CAS Access to Rank 5; Bank 2 event=0xbd,umask=2  01    WR_CAS Access to Rank 0 : Bank 2 unc_m_wr_cas_rank5.bank3 uncore memory WR_CAS Access to Rank 5; Bank 3 event=0xbd,umask=3  01    WR_CAS Access to Rank 0 : Bank 3 unc_m_wr_cas_rank5.bank4 uncore memory WR_CAS Access to Rank 5; Bank 4 event=0xbd,umask=4  01    WR_CAS Access to Rank 0 : Bank 4 unc_m_wr_cas_rank5.bank5 uncore memory WR_CAS Access to Rank 5; Bank 5 event=0xbd,umask=5  01    WR_CAS Access to Rank 0 : Bank 5 unc_m_wr_cas_rank5.bank6 uncore memory WR_CAS Access to Rank 5; Bank 6 event=0xbd,umask=6  01    WR_CAS Access to Rank 0 : Bank 6 unc_m_wr_cas_rank5.bank7 uncore memory WR_CAS Access to Rank 5; Bank 7 event=0xbd,umask=7  01    WR_CAS Access to Rank 0 : Bank 7 unc_m_wr_cas_rank5.bank8 uncore memory WR_CAS Access to Rank 5; Bank 8 event=0xbd,umask=8  01    WR_CAS Access to Rank 0 : Bank 8 unc_m_wr_cas_rank5.bank9 uncore memory WR_CAS Access to Rank 5; Bank 9 event=0xbd,umask=9  01    WR_CAS Access to Rank 0 : Bank 9 unc_m_wr_cas_rank5.bankg0 uncore memory WR_CAS Access to Rank 5; Bank Group 0 (Banks 0-3) event=0xbd,umask=0x11  01    WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_wr_cas_rank5.bankg1 uncore memory WR_CAS Access to Rank 5; Bank Group 1 (Banks 4-7) event=0xbd,umask=0x12  01    WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_wr_cas_rank5.bankg2 uncore memory WR_CAS Access to Rank 5; Bank Group 2 (Banks 8-11) event=0xbd,umask=0x13  01    WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_wr_cas_rank5.bankg3 uncore memory WR_CAS Access to Rank 5; Bank Group 3 (Banks 12-15) event=0xbd,umask=0x14  01    WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_wr_cas_rank6.allbanks uncore memory WR_CAS Access to Rank 6; All Banks event=0xbe,umask=0x10  01    WR_CAS Access to Rank 0 : All Banks unc_m_wr_cas_rank6.bank0 uncore memory WR_CAS Access to Rank 6; Bank 0 event=0xbe  01    WR_CAS Access to Rank 0 : Bank 0 unc_m_wr_cas_rank6.bank1 uncore memory WR_CAS Access to Rank 6; Bank 1 event=0xbe,umask=1  01    WR_CAS Access to Rank 0 : Bank 1 unc_m_wr_cas_rank6.bank10 uncore memory WR_CAS Access to Rank 6; Bank 10 event=0xbe,umask=0xa  01    WR_CAS Access to Rank 0 : Bank 10 unc_m_wr_cas_rank6.bank11 uncore memory WR_CAS Access to Rank 6; Bank 11 event=0xbe,umask=0xb  01    WR_CAS Access to Rank 0 : Bank 11 unc_m_wr_cas_rank6.bank12 uncore memory WR_CAS Access to Rank 6; Bank 12 event=0xbe,umask=0xc  01    WR_CAS Access to Rank 0 : Bank 12 unc_m_wr_cas_rank6.bank13 uncore memory WR_CAS Access to Rank 6; Bank 13 event=0xbe,umask=0xd  01    WR_CAS Access to Rank 0 : Bank 13 unc_m_wr_cas_rank6.bank14 uncore memory WR_CAS Access to Rank 6; Bank 14 event=0xbe,umask=0xe  01    WR_CAS Access to Rank 0 : Bank 14 unc_m_wr_cas_rank6.bank15 uncore memory WR_CAS Access to Rank 6; Bank 15 event=0xbe,umask=0xf  01    WR_CAS Access to Rank 0 : Bank 15 unc_m_wr_cas_rank6.bank2 uncore memory WR_CAS Access to Rank 6; Bank 2 event=0xbe,umask=2  01    WR_CAS Access to Rank 0 : Bank 2 unc_m_wr_cas_rank6.bank3 uncore memory WR_CAS Access to Rank 6; Bank 3 event=0xbe,umask=3  01    WR_CAS Access to Rank 0 : Bank 3 unc_m_wr_cas_rank6.bank4 uncore memory WR_CAS Access to Rank 6; Bank 4 event=0xbe,umask=4  01    WR_CAS Access to Rank 0 : Bank 4 unc_m_wr_cas_rank6.bank5 uncore memory WR_CAS Access to Rank 6; Bank 5 event=0xbe,umask=5  01    WR_CAS Access to Rank 0 : Bank 5 unc_m_wr_cas_rank6.bank6 uncore memory WR_CAS Access to Rank 6; Bank 6 event=0xbe,umask=6  01    WR_CAS Access to Rank 0 : Bank 6 unc_m_wr_cas_rank6.bank7 uncore memory WR_CAS Access to Rank 6; Bank 7 event=0xbe,umask=7  01    WR_CAS Access to Rank 0 : Bank 7 unc_m_wr_cas_rank6.bank8 uncore memory WR_CAS Access to Rank 6; Bank 8 event=0xbe,umask=8  01    WR_CAS Access to Rank 0 : Bank 8 unc_m_wr_cas_rank6.bank9 uncore memory WR_CAS Access to Rank 6; Bank 9 event=0xbe,umask=9  01    WR_CAS Access to Rank 0 : Bank 9 unc_m_wr_cas_rank6.bankg0 uncore memory WR_CAS Access to Rank 6; Bank Group 0 (Banks 0-3) event=0xbe,umask=0x11  01    WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_wr_cas_rank6.bankg1 uncore memory WR_CAS Access to Rank 6; Bank Group 1 (Banks 4-7) event=0xbe,umask=0x12  01    WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_wr_cas_rank6.bankg2 uncore memory WR_CAS Access to Rank 6; Bank Group 2 (Banks 8-11) event=0xbe,umask=0x13  01    WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_wr_cas_rank6.bankg3 uncore memory WR_CAS Access to Rank 6; Bank Group 3 (Banks 12-15) event=0xbe,umask=0x14  01    WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) unc_m_wr_cas_rank7.allbanks uncore memory WR_CAS Access to Rank 7; All Banks event=0xbf,umask=0x10  01    WR_CAS Access to Rank 0 : All Banks unc_m_wr_cas_rank7.bank0 uncore memory WR_CAS Access to Rank 7; Bank 0 event=0xbf  01    WR_CAS Access to Rank 0 : Bank 0 unc_m_wr_cas_rank7.bank1 uncore memory WR_CAS Access to Rank 7; Bank 1 event=0xbf,umask=1  01    WR_CAS Access to Rank 0 : Bank 1 unc_m_wr_cas_rank7.bank10 uncore memory WR_CAS Access to Rank 7; Bank 10 event=0xbf,umask=0xa  01    WR_CAS Access to Rank 0 : Bank 10 unc_m_wr_cas_rank7.bank11 uncore memory WR_CAS Access to Rank 7; Bank 11 event=0xbf,umask=0xb  01    WR_CAS Access to Rank 0 : Bank 11 unc_m_wr_cas_rank7.bank12 uncore memory WR_CAS Access to Rank 7; Bank 12 event=0xbf,umask=0xc  01    WR_CAS Access to Rank 0 : Bank 12 unc_m_wr_cas_rank7.bank13 uncore memory WR_CAS Access to Rank 7; Bank 13 event=0xbf,umask=0xd  01    WR_CAS Access to Rank 0 : Bank 13 unc_m_wr_cas_rank7.bank14 uncore memory WR_CAS Access to Rank 7; Bank 14 event=0xbf,umask=0xe  01    WR_CAS Access to Rank 0 : Bank 14 unc_m_wr_cas_rank7.bank15 uncore memory WR_CAS Access to Rank 7; Bank 15 event=0xbf,umask=0xf  01    WR_CAS Access to Rank 0 : Bank 15 unc_m_wr_cas_rank7.bank2 uncore memory WR_CAS Access to Rank 7; Bank 2 event=0xbf,umask=2  01    WR_CAS Access to Rank 0 : Bank 2 unc_m_wr_cas_rank7.bank3 uncore memory WR_CAS Access to Rank 7; Bank 3 event=0xbf,umask=3  01    WR_CAS Access to Rank 0 : Bank 3 unc_m_wr_cas_rank7.bank4 uncore memory WR_CAS Access to Rank 7; Bank 4 event=0xbf,umask=4  01    WR_CAS Access to Rank 0 : Bank 4 unc_m_wr_cas_rank7.bank5 uncore memory WR_CAS Access to Rank 7; Bank 5 event=0xbf,umask=5  01    WR_CAS Access to Rank 0 : Bank 5 unc_m_wr_cas_rank7.bank6 uncore memory WR_CAS Access to Rank 7; Bank 6 event=0xbf,umask=6  01    WR_CAS Access to Rank 0 : Bank 6 unc_m_wr_cas_rank7.bank7 uncore memory WR_CAS Access to Rank 7; Bank 7 event=0xbf,umask=7  01    WR_CAS Access to Rank 0 : Bank 7 unc_m_wr_cas_rank7.bank8 uncore memory WR_CAS Access to Rank 7; Bank 8 event=0xbf,umask=8  01    WR_CAS Access to Rank 0 : Bank 8 unc_m_wr_cas_rank7.bank9 uncore memory WR_CAS Access to Rank 7; Bank 9 event=0xbf,umask=9  01    WR_CAS Access to Rank 0 : Bank 9 unc_m_wr_cas_rank7.bankg0 uncore memory WR_CAS Access to Rank 7; Bank Group 0 (Banks 0-3) event=0xbf,umask=0x11  01    WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3) unc_m_wr_cas_rank7.bankg1 uncore memory WR_CAS Access to Rank 7; Bank Group 1 (Banks 4-7) event=0xbf,umask=0x12  01    WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7) unc_m_wr_cas_rank7.bankg2 uncore memory WR_CAS Access to Rank 7; Bank Group 2 (Banks 8-11) event=0xbf,umask=0x13  01    WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11) unc_m_wr_cas_rank7.bankg3 uncore memory WR_CAS Access to Rank 7; Bank Group 3 (Banks 12-15) event=0xbf,umask=0x14  01    WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15) uncore_pcu unc_p_clockticks uncore power pclk Cycles event=0  01    The PCU runs off a fixed 1 GHz clock.  This event counts the number of pclk cycles measured while the counter was enabled.  The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time unc_p_core0_transition_cycles uncore power Core C State Transition Cycles event=0x60  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core10_transition_cycles uncore power Core C State Transition Cycles event=0x6a  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core11_transition_cycles uncore power Core C State Transition Cycles event=0x6b  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core12_transition_cycles uncore power Core C State Transition Cycles event=0x6c  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core13_transition_cycles uncore power Core C State Transition Cycles event=0x6d  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core14_transition_cycles uncore power Core C State Transition Cycles event=0x6e  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core15_transition_cycles uncore power Core C State Transition Cycles event=0x6f  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core16_transition_cycles uncore power Core C State Transition Cycles event=0x70  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core17_transition_cycles uncore power Core C State Transition Cycles event=0x71  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core1_transition_cycles uncore power Core C State Transition Cycles event=0x61  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core2_transition_cycles uncore power Core C State Transition Cycles event=0x62  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core3_transition_cycles uncore power Core C State Transition Cycles event=0x63  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core4_transition_cycles uncore power Core C State Transition Cycles event=0x64  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core5_transition_cycles uncore power Core C State Transition Cycles event=0x65  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core6_transition_cycles uncore power Core C State Transition Cycles event=0x66  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core7_transition_cycles uncore power Core C State Transition Cycles event=0x67  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core8_transition_cycles uncore power Core C State Transition Cycles event=0x68  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core9_transition_cycles uncore power Core C State Transition Cycles event=0x69  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_demotions_core0 uncore power Core C State Demotions event=0x30  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core1 uncore power Core C State Demotions event=0x31  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core10 uncore power Core C State Demotions event=0x3a  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core11 uncore power Core C State Demotions event=0x3b  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core12 uncore power Core C State Demotions event=0x3c  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core13 uncore power Core C State Demotions event=0x3d  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core14 uncore power Core C State Demotions event=0x3e  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core15 uncore power Core C State Demotions event=0x3f  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core16 uncore power Core C State Demotions event=0x40  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core17 uncore power Core C State Demotions event=0x41  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core2 uncore power Core C State Demotions event=0x32  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core3 uncore power Core C State Demotions event=0x33  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core4 uncore power Core C State Demotions event=0x34  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core5 uncore power Core C State Demotions event=0x35  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core6 uncore power Core C State Demotions event=0x36  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core7 uncore power Core C State Demotions event=0x37  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core8 uncore power Core C State Demotions event=0x38  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core9 uncore power Core C State Demotions event=0x39  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_freq_max_limit_thermal_cycles uncore power Thermal Strongest Upper Limit Cycles event=4  01    Counts the number of cycles when thermal conditions are the upper limit on frequency.  This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature.  This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input unc_p_freq_max_os_cycles uncore power OS Strongest Upper Limit Cycles event=6  01    Counts the number of cycles when the OS is the upper limit on frequency unc_p_freq_max_power_cycles uncore power Power Strongest Upper Limit Cycles event=5  01    Counts the number of cycles when power is the upper limit on frequency unc_p_freq_min_io_p_cycles uncore power IO P Limit Strongest Lower Limit Cycles event=0x73  01    Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower.  This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW.  This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth unc_p_freq_trans_cycles uncore power Cycles spent changing Frequency event=0x74  01    Counts the number of cycles when the system is changing frequency.  This can not be filtered by thread ID.  One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system unc_p_memory_phase_shedding_cycles uncore power Memory Phase Shedding Cycles event=0x2f  01    Counts the number of cycles that the PCU has triggered memory phase shedding.  This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency unc_p_pkg_residency_c0_cycles uncore power Package C State Residency - C0 event=0x2a  01    Counts the number of cycles when the package was in C0.  This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert).  Residency events do not include transition times unc_p_pkg_residency_c1e_cycles uncore power Package C State Residency - C1E event=0x4e  01    Counts the number of cycles when the package was in C1E.  This event can be used in conjunction with edge detect to count C1E entrances (or exits using invert).  Residency events do not include transition times unc_p_pkg_residency_c2e_cycles uncore power Package C State Residency - C2E event=0x2b  01    Counts the number of cycles when the package was in C2E.  This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert).  Residency events do not include transition times unc_p_pkg_residency_c3_cycles uncore power Package C State Residency - C3 event=0x2c  01    Counts the number of cycles when the package was in C3.  This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert).  Residency events do not include transition times unc_p_pkg_residency_c6_cycles uncore power Package C State Residency - C6 event=0x2d  01    Counts the number of cycles when the package was in C6.  This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert).  Residency events do not include transition times unc_p_pkg_residency_c7_cycles uncore power Package C7 State Residency event=0x2e  01    Counts the number of cycles when the package was in C7.  This event can be used in conjunction with edge detect to count C7 entrances (or exits using invert).  Residency events do not include transition times unc_p_power_state_occupancy.cores_c0 uncore power Number of cores in C-State; C0 and C1 event=0x80,occ_sel=1  01    This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_power_state_occupancy.cores_c3 uncore power Number of cores in C-State; C3 event=0x80,occ_sel=2  01    This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_power_state_occupancy.cores_c6 uncore power Number of cores in C-State; C6 and C7 event=0x80,occ_sel=3  01    This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_prochot_external_cycles uncore power External Prochot event=0xa  01    Counts the number of cycles that we are in external PROCHOT mode.  This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip unc_p_prochot_internal_cycles uncore power Internal Prochot event=9  01    Counts the number of cycles that we are in Internal PROCHOT mode.  This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip unc_p_total_transition_cycles uncore power Total Core C State Transition Cycles event=0x72  01    Number of cycles spent performing core C state transitions across all cores unc_p_ufs_transitions_ring_gv uncore power UNC_P_UFS_TRANSITIONS_RING_GV event=0x79  01    Ring GV with same final and initial frequency unc_p_vr_hot_cycles uncore power VR Hot event=0x42  01    VR Hot : Number of cycles that a CPU SVID VR is hot.  Does not cover DRAM VRs offcore_response.all_code_rd.llc_hit.hit_other_core_no_fwd cache Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0244  00     offcore_response.all_data_rd.llc_hit.hitm_other_core cache Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0091  00     offcore_response.all_data_rd.llc_hit.hit_other_core_no_fwd cache Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0091  00     offcore_response.all_reads.llc_hit.hitm_other_core cache Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C07F7  00     offcore_response.all_reads.llc_hit.hit_other_core_no_fwd cache Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C07F7  00     offcore_response.all_requests.llc_hit.any_response cache Counts all requests hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C8FFF  00     offcore_response.all_rfo.llc_hit.hitm_other_core cache Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0122  00     offcore_response.all_rfo.llc_hit.hit_other_core_no_fwd cache Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0122  00     offcore_response.demand_rfo.llc_hit.any_response cache Counts all demand data writes (RFOs) hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0002  00     offcore_response.demand_rfo.llc_hit.hitm_other_core cache Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0002  00     offcore_response.pf_llc_code_rd.llc_hit.any_response cache Counts prefetch (that bring data to LLC only) code reads hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0200  00     offcore_response.pf_llc_rfo.llc_hit.any_response cache Counts all prefetch (that bring data to LLC only) RFOs hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0100  00     offcore_response.all_code_rd.llc_miss.any_response memory Counts all demand & prefetch code reads miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00244  00     offcore_response.all_code_rd.llc_miss.local_dram memory Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x604000244  00     offcore_response.all_data_rd.llc_miss.any_response memory Counts all demand & prefetch data reads miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00091  00     offcore_response.all_data_rd.llc_miss.local_dram memory Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x604000091  00     offcore_response.all_data_rd.llc_miss.remote_dram memory Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63BC00091  00     offcore_response.all_data_rd.llc_miss.remote_hitm memory Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00091  00     offcore_response.all_data_rd.llc_miss.remote_hit_forward memory Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x87FC00091  00     offcore_response.all_reads.llc_miss.any_response memory Counts all data/code/rfo reads (demand & prefetch) miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC007F7  00     offcore_response.all_reads.llc_miss.local_dram memory Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x6040007F7  00     offcore_response.all_reads.llc_miss.remote_dram memory Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63BC007F7  00     offcore_response.all_reads.llc_miss.remote_hitm memory Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC007F7  00     offcore_response.all_reads.llc_miss.remote_hit_forward memory Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x87FC007F7  00     offcore_response.all_requests.llc_miss.any_response memory Counts all requests miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC08FFF  00     offcore_response.all_rfo.llc_miss.any_response memory Counts all demand & prefetch RFOs miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00122  00     offcore_response.all_rfo.llc_miss.local_dram memory Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x604000122  00     offcore_response.demand_rfo.llc_miss.any_response memory Counts all demand data writes (RFOs) miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00002  00     offcore_response.demand_rfo.llc_miss.remote_hitm memory Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00002  00     offcore_response.pf_llc_code_rd.llc_miss.any_response memory Counts prefetch (that bring data to LLC only) code reads miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00200  00     offcore_response.pf_llc_rfo.llc_miss.any_response memory Counts all prefetch (that bring data to LLC only) RFOs miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00100  00     llc_misses.code_llc_prefetch uncore cache LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcode event=0x35,umask=3,filter_opc=0x191  0164Bytes    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode llc_misses.data_llc_prefetch uncore cache LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcode event=0x35,umask=3,filter_opc=0x192  0164Bytes    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode llc_misses.data_read uncore cache LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode event=0x35,umask=3,filter_opc=0x182  0164Bytes    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode llc_misses.mmio_read uncore cache MMIO reads. Derived from unc_c_tor_inserts.miss_opcode event=0x35,umask=3,filter_opc=0x187,filter_nc=1  0164Bytes    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode llc_misses.mmio_write uncore cache MMIO writes. Derived from unc_c_tor_inserts.miss_opcode event=0x35,umask=3,filter_opc=0x18f,filter_nc=1  0164Bytes    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode llc_misses.pcie_non_snoop_write uncore cache PCIe write misses (full cache line). Derived from unc_c_tor_inserts.miss_opcode event=0x35,umask=3,filter_opc=0x1c8,filter_tid=0x3e  0164Bytes    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode llc_misses.pcie_read uncore cache LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode event=0x35,umask=3,filter_opc=0x19e  0164Bytes    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode llc_misses.pcie_write uncore cache ItoM write misses (as part of fast string memcpy stores) + PCIe full line writes. Derived from unc_c_tor_inserts.miss_opcode event=0x35,umask=3,filter_opc=0x1c8  0164Bytes    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode llc_misses.rfo_llc_prefetch uncore cache LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode event=0x35,umask=3,filter_opc=0x190  0164Bytes    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode llc_misses.uncacheable uncore cache LLC misses - Uncacheable reads (from cpu) . Derived from unc_c_tor_inserts.miss_opcode event=0x35,umask=3,filter_opc=0x187  0164Bytes    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode llc_references.code_llc_prefetch uncore cache L2 demand and L2 prefetch code references to LLC. Derived from unc_c_tor_inserts.opcode event=0x35,umask=1,filter_opc=0x181  0164Bytes    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc) llc_references.pcie_ns_partial_write uncore cache PCIe writes (partial cache line). Derived from unc_c_tor_inserts.opcode event=0x35,umask=1,filter_opc=0x180,filter_tid=0x3e  01    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc) llc_references.pcie_read uncore cache PCIe read current. Derived from unc_c_tor_inserts.opcode event=0x35,umask=1,filter_opc=0x19e  0164Bytes    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc) llc_references.pcie_write uncore cache PCIe write references (full cache line). Derived from unc_c_tor_inserts.opcode event=0x35,umask=1,filter_opc=0x1c8,filter_tid=0x3e  0164Bytes    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc) llc_references.streaming_full uncore cache Streaming stores (full cache line). Derived from unc_c_tor_inserts.opcode event=0x35,umask=1,filter_opc=0x18c  0164Bytes    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc) llc_references.streaming_partial uncore cache Streaming stores (partial cache line). Derived from unc_c_tor_inserts.opcode event=0x35,umask=1,filter_opc=0x18d  0164Bytes    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc) unc_c_llc_lookup.any uncore cache All LLC Misses (code+ data rd + data wr - including demand and prefetch) event=0x34,umask=0x11,filter_state=0x1  0164Bytes    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ.  This does not include lookups originating from the ISMQ unc_c_llc_victims.m_state uncore cache M line evictions from LLC (writebacks to memory) event=0x37,umask=1  0164Bytes    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_c_ring_ad_used.down uncore cache AD Ring In Use; Down event=0x1b,umask=0xc  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX-- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.up uncore cache AD Ring In Use; Up event=0x1b,umask=3  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.down uncore cache AK Ring In Use; Down event=0x1c,umask=0xc  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.up uncore cache AK Ring In Use; Up event=0x1c,umask=3  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.down uncore cache BL Ring in Use; Down event=0x1d,umask=0xc  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.up uncore cache BL Ring in Use; Up event=0x1d,umask=3  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_tor_occupancy.llc_data_read uncore cache Occupancy counter for LLC data reads (demand and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode event=0x36,umask=3,filter_opc=0x182  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries for miss transactions that match an opcode. This generally means that the request was sent to memory or MMIO unc_h_snoop_resp.rspifwd uncore cache M line forwarded from remote cache with no writeback to memory event=0x21,umask=4  0164Bytes    Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspIFwd.  This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states.  This is commonly returned with RFO transactions.  It can be either a HitM or a HitFE unc_h_snoop_resp.rsps uncore cache Shared line response from remote cache event=0x21,umask=2  0164Bytes    Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspS.  RspS is returned when a remote cache has data but is not forwarding it.  It is a way to let the requesting socket know that it cannot allocate the data in E state.  No data is sent with S RspS unc_h_snoop_resp.rspsfwd uncore cache Shared line forwarded from remote cache event=0x21,umask=8  0164Bytes    Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspSFwd.  This is returned when a remote caching agent forwards data but holds on to its current copy.  This is common for data and code reads that hit in a remote socket in E or F state unc_h_snoop_resp.rsp_fwd_wb uncore cache M line forwarded from remote cache along with writeback to memory event=0x21,umask=0x20  0164Bytes    Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of Rsp*Fwd*WB.  This snoop response is only used in 4s systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory uncore_qpi unc_q_clockticks uncore interconnect Number of qfclks event=0x14  01    Counts the number of clocks in the QPI LL.  This clock runs at 1/4th the GT/s speed of the QPI link.  For example, a 4GT/s link will have qfclk or 1GHz.  BDX does not support dynamic link speeds, so this frequency is fixed unc_q_cto_count uncore interconnect Count of CTO Events event=0x38  01    Counts the number of CTO (cluster trigger outs) events that were asserted across the two slots.  If both slots trigger in a given cycle, the event will increment by 2.  You can use edge detect to count the number of cases when both events triggered unc_q_direct2core.failure_credits uncore interconnect Direct 2 Core Spawning; Spawn Failure - Egress Credits event=0x13,umask=2  01    Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exclusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits.  Had there been enough credits, the spawn would have worked as the RBT bit was set and the RBT tag matched unc_q_direct2core.failure_credits_miss uncore interconnect Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss event=0x13,umask=0x20  01    Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exclusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and there weren't enough Egress credits.   The valid bit was set unc_q_direct2core.failure_credits_rbt uncore interconnect Direct 2 Core Spawning; Spawn Failure - Egress and RBT Invalid event=0x13,umask=8  01    Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exclusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits AND the RBT bit was not set, but the RBT tag matched unc_q_direct2core.failure_credits_rbt_miss uncore interconnect Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss, Invalid event=0x13,umask=0x80  01    Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exclusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match, the valid bit was not set and there weren't enough Egress credits unc_q_direct2core.failure_miss uncore interconnect Direct 2 Core Spawning; Spawn Failure - RBT Miss event=0x13,umask=0x10  01    Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exclusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match although the valid bit was set and there were enough Egress credits unc_q_direct2core.failure_rbt_hit uncore interconnect Direct 2 Core Spawning; Spawn Failure - RBT Invalid event=0x13,umask=4  01    Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exclusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the route-back table (RBT) specified that the transaction should not trigger a direct2core transaction.  This is common for IO transactions.  There were enough Egress credits and the RBT tag matched but the valid bit was not set unc_q_direct2core.failure_rbt_miss uncore interconnect Direct 2 Core Spawning; Spawn Failure - RBT Miss and Invalid event=0x13,umask=0x40  01    Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exclusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and the valid bit was not set although there were enough Egress credits unc_q_direct2core.success_rbt_hit uncore interconnect Direct 2 Core Spawning; Spawn Success event=0x13,umask=1  01    Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exclusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn was successful.  There were sufficient credits, the RBT valid bit was set and there was an RBT tag match.  The message was marked to spawn direct2core unc_q_l1_power_cycles uncore interconnect Cycles in L1 event=0x12  01    Number of QPI qfclk cycles spent in L1 power mode.  L1 is a mode that totally shuts down a QPI link.  Use edge detect to count the number of instances when the QPI link entered L1.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode unc_q_rxl0p_power_cycles uncore interconnect Cycles in L0p event=0x10  01    Number of QPI qfclk cycles spent in L0p power mode.  L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power.  It increases snoop and data transfer latencies and decreases overall bandwidth.  This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses.  Use edge detect to count the number of instances when the QPI link entered L0p.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another unc_q_rxl0_power_cycles uncore interconnect Cycles in L0 event=0xf  01    Number of QPI qfclk cycles spent in L0 power mode in the Link Layer.  L0 is the default mode which provides the highest performance with the most power.  Use edge detect to count the number of instances that the link entered L0.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.  The phy layer  sometimes leaves L0 for training, which will not be captured by this event unc_q_rxl_bypassed uncore interconnect Rx Flit Buffer Bypassed event=9  01    Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency unc_q_rxl_crc_errors.link_init uncore interconnect CRC Errors Detected; LinkInit event=3,umask=1  01    Number of CRC errors detected in the QPI Agent.  Each QPI flit incorporates 8 bits of CRC for error detection.  This counts the number of flits where the CRC was able to detect an error.  After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during link initialization unc_q_rxl_crc_errors.normal_op uncore interconnect UNC_Q_RxL_CRC_ERRORS.NORMAL_OP event=3,umask=2  01     unc_q_rxl_credits_consumed_vn0.drs uncore interconnect VN0 Credit Consumed; DRS event=0x1e,umask=1  01    Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the DRS message class unc_q_rxl_credits_consumed_vn0.hom uncore interconnect VN0 Credit Consumed; HOM event=0x1e,umask=8  01    Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the HOM message class unc_q_rxl_credits_consumed_vn0.ncb uncore interconnect VN0 Credit Consumed; NCB event=0x1e,umask=2  01    Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCB message class unc_q_rxl_credits_consumed_vn0.ncs uncore interconnect VN0 Credit Consumed; NCS event=0x1e,umask=4  01    Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCS message class unc_q_rxl_credits_consumed_vn0.ndr uncore interconnect VN0 Credit Consumed; NDR event=0x1e,umask=0x20  01    Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NDR message class unc_q_rxl_credits_consumed_vn0.snp uncore interconnect VN0 Credit Consumed; SNP event=0x1e,umask=0x10  01    Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the SNP message class unc_q_rxl_credits_consumed_vn1.drs uncore interconnect VN1 Credit Consumed; DRS event=0x39,umask=1  01    Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the DRS message class unc_q_rxl_credits_consumed_vn1.hom uncore interconnect VN1 Credit Consumed; HOM event=0x39,umask=8  01    Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the HOM message class unc_q_rxl_credits_consumed_vn1.ncb uncore interconnect VN1 Credit Consumed; NCB event=0x39,umask=2  01    Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCB message class unc_q_rxl_credits_consumed_vn1.ncs uncore interconnect VN1 Credit Consumed; NCS event=0x39,umask=4  01    Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCS message class unc_q_rxl_credits_consumed_vn1.ndr uncore interconnect VN1 Credit Consumed; NDR event=0x39,umask=0x20  01    Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NDR message class unc_q_rxl_credits_consumed_vn1.snp uncore interconnect VN1 Credit Consumed; SNP event=0x39,umask=0x10  01    Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the SNP message class unc_q_rxl_credits_consumed_vna uncore interconnect VNA Credit Consumed event=0x1d  01    Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed unc_q_rxl_cycles_ne uncore interconnect RxQ Cycles Not Empty event=0xa  01    Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy unc_q_rxl_cycles_ne_drs.vn0 uncore interconnect RxQ Cycles Not Empty - DRS; for VN0 event=0xf,umask=1  01    Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors DRS flits only unc_q_rxl_cycles_ne_drs.vn1 uncore interconnect RxQ Cycles Not Empty - DRS; for VN1 event=0xf,umask=2  01    Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors DRS flits only unc_q_rxl_cycles_ne_hom.vn0 uncore interconnect RxQ Cycles Not Empty - HOM; for VN0 event=0x12,umask=1  01    Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors HOM flits only unc_q_rxl_cycles_ne_hom.vn1 uncore interconnect RxQ Cycles Not Empty - HOM; for VN1 event=0x12,umask=2  01    Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors HOM flits only unc_q_rxl_cycles_ne_ncb.vn0 uncore interconnect RxQ Cycles Not Empty - NCB; for VN0 event=0x10,umask=1  01    Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NCB flits only unc_q_rxl_cycles_ne_ncb.vn1 uncore interconnect RxQ Cycles Not Empty - NCB; for VN1 event=0x10,umask=2  01    Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NCB flits only unc_q_rxl_cycles_ne_ncs.vn0 uncore interconnect RxQ Cycles Not Empty - NCS; for VN0 event=0x11,umask=1  01    Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NCS flits only unc_q_rxl_cycles_ne_ncs.vn1 uncore interconnect RxQ Cycles Not Empty - NCS; for VN1 event=0x11,umask=2  01    Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NCS flits only unc_q_rxl_cycles_ne_ndr.vn0 uncore interconnect RxQ Cycles Not Empty - NDR; for VN0 event=0x14,umask=1  01    Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NDR flits only unc_q_rxl_cycles_ne_ndr.vn1 uncore interconnect RxQ Cycles Not Empty - NDR; for VN1 event=0x14,umask=2  01    Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NDR flits only unc_q_rxl_cycles_ne_snp.vn0 uncore interconnect RxQ Cycles Not Empty - SNP; for VN0 event=0x13,umask=1  01    Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors SNP flits only unc_q_rxl_cycles_ne_snp.vn1 uncore interconnect RxQ Cycles Not Empty - SNP; for VN1 event=0x13,umask=2  01    Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors SNP flits only unc_q_rxl_flits_g0.idle uncore interconnect Flits Received - Group 0; Idle and Null Flits event=1,umask=1  01    Counts the number of flits received from the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of flits received over QPI that do not hold protocol payload.  When QPI is not in a power saving state, it continuously transmits flits across the link.  When there are no protocol flits to send, it will send IDLE and NULL flits  across.  These flits sometimes do carry a payload, such as credit returns, but are generally not considered part of the QPI bandwidth unc_q_rxl_flits_g1.drs uncore interconnect Flits Received - Group 1; DRS Flits (both Header and Data) event=2,umask=0x18  01    Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits received over the NCB channel which transmits non-coherent data unc_q_rxl_flits_g1.drs_data uncore interconnect Flits Received - Group 1; DRS Data Flits event=2,umask=8  01    Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits received over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits received over the NCB channel which transmits non-coherent data.  This includes only the data flits (not the header) unc_q_rxl_flits_g1.drs_nondata uncore interconnect Flits Received - Group 1; DRS Header Flits event=2,umask=0x10  01    Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits received over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits received over the NCB channel which transmits non-coherent data.  This includes only the header flits (not the data).  This includes extended headers unc_q_rxl_flits_g1.hom uncore interconnect Flits Received - Group 1; HOM Flits event=2,umask=6  01    Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits received over QPI on the home channel unc_q_rxl_flits_g1.hom_nonreq uncore interconnect Flits Received - Group 1; HOM Non-Request Flits event=2,umask=4  01    Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits received over QPI on the home channel.  These are most commonly snoop responses, and this event can be used as a proxy for that unc_q_rxl_flits_g1.hom_req uncore interconnect Flits Received - Group 1; HOM Request Flits event=2,umask=2  01    Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request received over QPI on the home channel.  This basically counts the number of remote memory requests received over QPI.  In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses unc_q_rxl_flits_g1.snp uncore interconnect Flits Received - Group 1; SNP Flits event=2,umask=1  01    Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits received over QPI.  These requests are contained in the snoop channel.  This does not include snoop responses, which are received on the home channel unc_q_rxl_flits_g2.ncb uncore interconnect Flits Received - Group 2; Non-Coherent Rx Flits event=3,umask=0xc  01    Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits.  These packets are generally used to transmit non-coherent data across QPI unc_q_rxl_flits_g2.ncb_data uncore interconnect Flits Received - Group 2; Non-Coherent data Rx Flits event=3,umask=4  01    Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits.  These flits are generally used to transmit non-coherent data across QPI.  This does not include a count of the DRS (coherent) data flits.  This only counts the data flits, not the NCB headers unc_q_rxl_flits_g2.ncb_nondata uncore interconnect Flits Received - Group 2; Non-Coherent non-data Rx Flits event=3,umask=8  01    Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits.  These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits.  This includes extended headers unc_q_rxl_flits_g2.ncs uncore interconnect Flits Received - Group 2; Non-Coherent standard Rx Flits event=3,umask=0x10  01    Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits received over QPI.    This includes extended headers unc_q_rxl_flits_g2.ndr_ad uncore interconnect Flits Received - Group 2; Non-Data Response Rx Flits - AD event=3,umask=1  01    Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel.  This channel is used to send a variety of protocol flits including grants and completions.  This is only for NDR packets to the local socket which use the AK ring unc_q_rxl_flits_g2.ndr_ak uncore interconnect Flits Received - Group 2; Non-Data Response Rx Flits - AK event=3,umask=2  01    Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel.  This channel is used to send a variety of protocol flits including grants and completions.  This is only for NDR packets destined for Route-thru to a remote socket unc_q_rxl_inserts uncore interconnect Rx Flit Buffer Allocations event=8  01    Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime unc_q_rxl_inserts_drs.vn0 uncore interconnect Rx Flit Buffer Allocations - DRS; for VN0 event=9,umask=1  01    Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only DRS flits unc_q_rxl_inserts_drs.vn1 uncore interconnect Rx Flit Buffer Allocations - DRS; for VN1 event=9,umask=2  01    Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only DRS flits unc_q_rxl_inserts_hom.vn0 uncore interconnect Rx Flit Buffer Allocations - HOM; for VN0 event=0xc,umask=1  01    Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only HOM flits unc_q_rxl_inserts_hom.vn1 uncore interconnect Rx Flit Buffer Allocations - HOM; for VN1 event=0xc,umask=2  01    Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only HOM flits unc_q_rxl_inserts_ncb.vn0 uncore interconnect Rx Flit Buffer Allocations - NCB; for VN0 event=0xa,umask=1  01    Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCB flits unc_q_rxl_inserts_ncb.vn1 uncore interconnect Rx Flit Buffer Allocations - NCB; for VN1 event=0xa,umask=2  01    Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCB flits unc_q_rxl_inserts_ncs.vn0 uncore interconnect Rx Flit Buffer Allocations - NCS; for VN0 event=0xb,umask=1  01    Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCS flits unc_q_rxl_inserts_ncs.vn1 uncore interconnect Rx Flit Buffer Allocations - NCS; for VN1 event=0xb,umask=2  01    Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCS flits unc_q_rxl_inserts_ndr.vn0 uncore interconnect Rx Flit Buffer Allocations - NDR; for VN0 event=0xe,umask=1  01    Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NDR flits unc_q_rxl_inserts_ndr.vn1 uncore interconnect Rx Flit Buffer Allocations - NDR; for VN1 event=0xe,umask=2  01    Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NDR flits unc_q_rxl_inserts_snp.vn0 uncore interconnect Rx Flit Buffer Allocations - SNP; for VN0 event=0xd,umask=1  01    Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only SNP flits unc_q_rxl_inserts_snp.vn1 uncore interconnect Rx Flit Buffer Allocations - SNP; for VN1 event=0xd,umask=2  01    Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only SNP flits unc_q_rxl_occupancy uncore interconnect RxQ Occupancy - All Packets event=0xb  01    Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime unc_q_rxl_occupancy_drs.vn0 uncore interconnect RxQ Occupancy - DRS; for VN0 event=0x15,umask=1  01    Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors DRS flits only unc_q_rxl_occupancy_drs.vn1 uncore interconnect RxQ Occupancy - DRS; for VN1 event=0x15,umask=2  01    Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors DRS flits only unc_q_rxl_occupancy_hom.vn0 uncore interconnect RxQ Occupancy - HOM; for VN0 event=0x18,umask=1  01    Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors HOM flits only unc_q_rxl_occupancy_hom.vn1 uncore interconnect RxQ Occupancy - HOM; for VN1 event=0x18,umask=2  01    Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors HOM flits only unc_q_rxl_occupancy_ncb.vn0 uncore interconnect RxQ Occupancy - NCB; for VN0 event=0x16,umask=1  01    Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCB flits only unc_q_rxl_occupancy_ncb.vn1 uncore interconnect RxQ Occupancy - NCB; for VN1 event=0x16,umask=2  01    Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCB flits only unc_q_rxl_occupancy_ncs.vn0 uncore interconnect RxQ Occupancy - NCS; for VN0 event=0x17,umask=1  01    Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCS flits only unc_q_rxl_occupancy_ncs.vn1 uncore interconnect RxQ Occupancy - NCS; for VN1 event=0x17,umask=2  01    Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCS flits only unc_q_rxl_occupancy_ndr.vn0 uncore interconnect RxQ Occupancy - NDR; for VN0 event=0x1a,umask=1  01    Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NDR flits only unc_q_rxl_occupancy_ndr.vn1 uncore interconnect RxQ Occupancy - NDR; for VN1 event=0x1a,umask=2  01    Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NDR flits only unc_q_rxl_occupancy_snp.vn0 uncore interconnect RxQ Occupancy - SNP; for VN0 event=0x19,umask=1  01    Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors SNP flits only unc_q_rxl_occupancy_snp.vn1 uncore interconnect RxQ Occupancy - SNP; for VN1 event=0x19,umask=2  01    Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors SNP flits only unc_q_rxl_stalls_vn0.bgf_drs uncore interconnect Stalls Sending to R3QPI on VN0; BGF Stall - HOM event=0x35,umask=1  01    Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the HOM message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn0.bgf_hom uncore interconnect Stalls Sending to R3QPI on VN0; BGF Stall - DRS event=0x35,umask=8  01    Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the DRS message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn0.bgf_ncb uncore interconnect Stalls Sending to R3QPI on VN0; BGF Stall - SNP event=0x35,umask=2  01    Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the SNP message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn0.bgf_ncs uncore interconnect Stalls Sending to R3QPI on VN0; BGF Stall - NDR event=0x35,umask=4  01    Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NDR message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn0.bgf_ndr uncore interconnect Stalls Sending to R3QPI on VN0; BGF Stall - NCS event=0x35,umask=0x20  01    Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCS message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn0.bgf_snp uncore interconnect Stalls Sending to R3QPI on VN0; BGF Stall - NCB event=0x35,umask=0x10  01    Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCB message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn0.egress_credits uncore interconnect Stalls Sending to R3QPI on VN0; Egress Credits event=0x35,umask=0x40  01    Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet because there were insufficient BGF credits.  For details on a message class granularity, use the Egress Credit Occupancy events unc_q_rxl_stalls_vn0.gv uncore interconnect Stalls Sending to R3QPI on VN0; GV event=0x35,umask=0x80  01    Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled because a GV transition (frequency transition) was taking place unc_q_rxl_stalls_vn1.bgf_drs uncore interconnect Stalls Sending to R3QPI on VN1; BGF Stall - HOM event=0x3a,umask=1  01    Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the HOM message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn1.bgf_hom uncore interconnect Stalls Sending to R3QPI on VN1; BGF Stall - DRS event=0x3a,umask=8  01    Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the DRS message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn1.bgf_ncb uncore interconnect Stalls Sending to R3QPI on VN1; BGF Stall - SNP event=0x3a,umask=2  01    Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the SNP message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn1.bgf_ncs uncore interconnect Stalls Sending to R3QPI on VN1; BGF Stall - NDR event=0x3a,umask=4  01    Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NDR message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn1.bgf_ndr uncore interconnect Stalls Sending to R3QPI on VN1; BGF Stall - NCS event=0x3a,umask=0x20  01    Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCS message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_rxl_stalls_vn1.bgf_snp uncore interconnect Stalls Sending to R3QPI on VN1; BGF Stall - NCB event=0x3a,umask=0x10  01    Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCB message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary unc_q_txl0p_power_cycles uncore interconnect Cycles in L0p event=0xd  01    Number of QPI qfclk cycles spent in L0p power mode.  L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power.  It increases snoop and data transfer latencies and decreases overall bandwidth.  This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses.  Use edge detect to count the number of instances when the QPI link entered L0p.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another unc_q_txl0_power_cycles uncore interconnect Cycles in L0 event=0xc  01    Number of QPI qfclk cycles spent in L0 power mode in the Link Layer.  L0 is the default mode which provides the highest performance with the most power.  Use edge detect to count the number of instances that the link entered L0.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.  The phy layer  sometimes leaves L0 for training, which will not be captured by this event unc_q_txl_bypassed uncore interconnect Tx Flit Buffer Bypassed event=5  01    Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the QPI Link. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link unc_q_txl_crc_no_credits.almost_full uncore interconnect Cycles Stalled with no LLR Credits; LLR is almost full event=2,umask=2  01    Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is almost full, we block some but not all packets unc_q_txl_crc_no_credits.full uncore interconnect Cycles Stalled with no LLR Credits; LLR is full event=2,umask=1  01    Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is totally full, we are not allowed to send any packets unc_q_txl_cycles_ne uncore interconnect Tx Flit Buffer Cycles not Empty event=6  01    Counts the number of cycles when the TxQ is not empty. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link unc_q_txl_flits_g0.data uncore interconnect Flits Transferred - Group 0; Data Tx Flits event=0,umask=2  01    Counts the number of flits transmitted across the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI.  Each flit contains 64b of data.  This includes both DRS and NCB data flits (coherent and non-coherent).  This can be used to calculate the data bandwidth of the QPI link.  One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits.  This does not include the header flits that go in data packets unc_q_txl_flits_g0.non_data uncore interconnect Flits Transferred - Group 0; Non-Data protocol Tx Flits event=0,umask=4  01    Counts the number of flits transmitted across the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI.  This basically tracks the protocol overhead on the QPI link.  One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits.  This includes the header flits for data packets unc_q_txl_flits_g1.drs uncore interconnect Flits Transferred - Group 1; DRS Flits (both Header and Data) event=0,umask=0x18  01    Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency unc_q_txl_flits_g1.drs_data uncore interconnect Flits Transferred - Group 1; DRS Data Flits event=0,umask=8  01    Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits transmitted over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits transmitted over the NCB channel which transmits non-coherent data.  This includes only the data flits (not the header) unc_q_txl_flits_g1.drs_nondata uncore interconnect Flits Transferred - Group 1; DRS Header Flits event=0,umask=0x10  01    Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits transmitted over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits transmitted over the NCB channel which transmits non-coherent data.  This includes only the header flits (not the data).  This includes extended headers unc_q_txl_flits_g1.hom uncore interconnect Flits Transferred - Group 1; HOM Flits event=0,umask=6  01    Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits transmitted over QPI on the home channel unc_q_txl_flits_g1.hom_nonreq uncore interconnect Flits Transferred - Group 1; HOM Non-Request Flits event=0,umask=4  01    Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits transmitted over QPI on the home channel.  These are most commonly snoop responses, and this event can be used as a proxy for that unc_q_txl_flits_g1.hom_req uncore interconnect Flits Transferred - Group 1; HOM Request Flits event=0,umask=2  01    Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request transmitted over QPI on the home channel.  This basically counts the number of remote memory requests transmitted over QPI.  In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses unc_q_txl_flits_g1.snp uncore interconnect Flits Transferred - Group 1; SNP Flits event=0,umask=1  01    Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits transmitted over QPI.  These requests are contained in the snoop channel.  This does not include snoop responses, which are transmitted on the home channel unc_q_txl_flits_g2.ncb uncore interconnect Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits event=1,umask=0xc  01    Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits.  These packets are generally used to transmit non-coherent data across QPI unc_q_txl_flits_g2.ncb_data uncore interconnect Flits Transferred - Group 2; Non-Coherent data Tx Flits event=1,umask=4  01    Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits.  These flits are generally used to transmit non-coherent data across QPI.  This does not include a count of the DRS (coherent) data flits.  This only counts the data flits, not the NCB headers unc_q_txl_flits_g2.ncb_nondata uncore interconnect Flits Transferred - Group 2; Non-Coherent non-data Tx Flits event=1,umask=8  01    Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits.  These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits.  This includes extended headers unc_q_txl_flits_g2.ncs uncore interconnect Flits Transferred - Group 2; Non-Coherent standard Tx Flits event=1,umask=0x10  01    Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits transmitted over QPI.    This includes extended headers unc_q_txl_flits_g2.ndr_ad uncore interconnect Flits Transferred - Group 2; Non-Data Response Tx Flits - AD event=1,umask=1  01    Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel.  This channel is used to send a variety of protocol flits including grants and completions.  This is only for NDR packets to the local socket which use the AK ring unc_q_txl_flits_g2.ndr_ak uncore interconnect Flits Transferred - Group 2; Non-Data Response Tx Flits - AK event=1,umask=2  01    Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel.  This channel is used to send a variety of protocol flits including grants and completions.  This is only for NDR packets destined for Route-thru to a remote socket unc_q_txl_inserts uncore interconnect Tx Flit Buffer Allocations event=4  01    Number of allocations into the QPI Tx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime unc_q_txl_occupancy uncore interconnect Tx Flit Buffer Occupancy event=7  01    Accumulates the number of flits in the TxQ.  Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ unc_q_txr_ad_hom_credit_acquired.vn0 uncore interconnect R3QPI Egress Credit Occupancy - HOM; for VN0 event=0x26,umask=1  01    Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD unc_q_txr_ad_hom_credit_acquired.vn1 uncore interconnect R3QPI Egress Credit Occupancy - HOM; for VN1 event=0x26,umask=2  01    Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD unc_q_txr_ad_hom_credit_occupancy.vn0 uncore interconnect R3QPI Egress Credit Occupancy - AD HOM; for VN0 event=0x22,umask=1  01    Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle.  Flow Control FIFO for HOM messages on AD unc_q_txr_ad_hom_credit_occupancy.vn1 uncore interconnect R3QPI Egress Credit Occupancy - AD HOM; for VN1 event=0x22,umask=2  01    Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle.  Flow Control FIFO for HOM messages on AD unc_q_txr_ad_ndr_credit_acquired.vn0 uncore interconnect R3QPI Egress Credit Occupancy - AD NDR; for VN0 event=0x28,umask=1  01    Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle.  Flow Control FIFO for NDR messages on AD unc_q_txr_ad_ndr_credit_acquired.vn1 uncore interconnect R3QPI Egress Credit Occupancy - AD NDR; for VN1 event=0x28,umask=2  01    Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle.  Flow Control FIFO for NDR messages on AD unc_q_txr_ad_ndr_credit_occupancy.vn0 uncore interconnect R3QPI Egress Credit Occupancy - AD NDR; for VN0 event=0x24,umask=1  01    Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO  for NDR messages on AD unc_q_txr_ad_ndr_credit_occupancy.vn1 uncore interconnect R3QPI Egress Credit Occupancy - AD NDR; for VN1 event=0x24,umask=2  01    Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO  for NDR messages on AD unc_q_txr_ad_snp_credit_acquired.vn0 uncore interconnect R3QPI Egress Credit Occupancy - SNP; for VN0 event=0x27,umask=1  01    Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle.  Flow Control FIFO for Snoop messages on AD unc_q_txr_ad_snp_credit_acquired.vn1 uncore interconnect R3QPI Egress Credit Occupancy - SNP; for VN1 event=0x27,umask=2  01    Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle.  Flow Control FIFO for Snoop messages on AD unc_q_txr_ad_snp_credit_occupancy.vn0 uncore interconnect R3QPI Egress Credit Occupancy - AD SNP; for VN0 event=0x23,umask=1  01    Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle.  Flow Control FIFO for Snoop messages on AD unc_q_txr_ad_snp_credit_occupancy.vn1 uncore interconnect R3QPI Egress Credit Occupancy - AD SNP; for VN1 event=0x23,umask=2  01    Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle.  Flow Control FIFO for Snoop messages on AD unc_q_txr_ak_ndr_credit_acquired uncore interconnect R3QPI Egress Credit Occupancy - AK NDR event=0x29  01    Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress unc_q_txr_ak_ndr_credit_occupancy uncore interconnect R3QPI Egress Credit Occupancy - AK NDR event=0x25  01    Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  Local NDR message class to AK Egress unc_q_txr_bl_drs_credit_acquired.vn0 uncore interconnect R3QPI Egress Credit Occupancy - DRS; for VN0 event=0x2a,umask=1  01    Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress unc_q_txr_bl_drs_credit_acquired.vn1 uncore interconnect R3QPI Egress Credit Occupancy - DRS; for VN1 event=0x2a,umask=2  01    Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress unc_q_txr_bl_drs_credit_acquired.vn_shr uncore interconnect R3QPI Egress Credit Occupancy - DRS; for Shared VN event=0x2a,umask=4  01    Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress unc_q_txr_bl_drs_credit_occupancy.vn0 uncore interconnect R3QPI Egress Credit Occupancy - BL DRS; for VN0 event=0x1f,umask=1  01    Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  DRS message class to BL Egress unc_q_txr_bl_drs_credit_occupancy.vn1 uncore interconnect R3QPI Egress Credit Occupancy - BL DRS; for VN1 event=0x1f,umask=2  01    Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  DRS message class to BL Egress unc_q_txr_bl_drs_credit_occupancy.vn_shr uncore interconnect R3QPI Egress Credit Occupancy - BL DRS; for Shared VN event=0x1f,umask=4  01    Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  DRS message class to BL Egress unc_q_txr_bl_ncb_credit_acquired.vn0 uncore interconnect R3QPI Egress Credit Occupancy - NCB; for VN0 event=0x2b,umask=1  01    Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress unc_q_txr_bl_ncb_credit_acquired.vn1 uncore interconnect R3QPI Egress Credit Occupancy - NCB; for VN1 event=0x2b,umask=2  01    Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress unc_q_txr_bl_ncb_credit_occupancy.vn0 uncore interconnect R3QPI Egress Credit Occupancy - BL NCB; for VN0 event=0x20,umask=1  01    Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  NCB message class to BL Egress unc_q_txr_bl_ncb_credit_occupancy.vn1 uncore interconnect R3QPI Egress Credit Occupancy - BL NCB; for VN1 event=0x20,umask=2  01    Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  NCB message class to BL Egress unc_q_txr_bl_ncs_credit_acquired.vn0 uncore interconnect R3QPI Egress Credit Occupancy - NCS; for VN0 event=0x2c,umask=1  01    Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress unc_q_txr_bl_ncs_credit_acquired.vn1 uncore interconnect R3QPI Egress Credit Occupancy - NCS; for VN1 event=0x2c,umask=2  01    Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress unc_q_txr_bl_ncs_credit_occupancy.vn0 uncore interconnect R3QPI Egress Credit Occupancy - BL NCS; for VN0 event=0x21,umask=1  01    Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  NCS message class to BL Egress unc_q_txr_bl_ncs_credit_occupancy.vn1 uncore interconnect R3QPI Egress Credit Occupancy - BL NCS; for VN1 event=0x21,umask=2  01    Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  NCS message class to BL Egress unc_q_vna_credit_returns uncore interconnect VNA Credits Returned event=0x1c  01    Number of VNA credits returned unc_q_vna_credit_return_occupancy uncore interconnect VNA Credits Pending Return - Occupancy event=0x1b  01    Number of VNA credits in the Rx side that are waitng to be returned back across the link uncore_r3qpi unc_r3_clockticks uncore interconnect Number of uclks in domain event=1  01    Counts the number of uclks in the QPI uclk domain.  This could be slightly different than the count in the Ubox because of enable/freeze delays.  However, because the QPI Agent is close to the Ubox, they generally should not diverge by more than a handful of cycles unc_r3_c_hi_ad_credits_empty.cbo10 uncore interconnect CBox AD Credits Empty event=0x1f,umask=4  01    No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 10 unc_r3_c_hi_ad_credits_empty.cbo11 uncore interconnect CBox AD Credits Empty event=0x1f,umask=8  01    No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 11 unc_r3_c_hi_ad_credits_empty.cbo12 uncore interconnect CBox AD Credits Empty event=0x1f,umask=0x10  01    No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 12 unc_r3_c_hi_ad_credits_empty.cbo13 uncore interconnect CBox AD Credits Empty event=0x1f,umask=0x20  01    No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 13 unc_r3_c_hi_ad_credits_empty.cbo14_16 uncore interconnect CBox AD Credits Empty event=0x1f,umask=0x40  01    No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 14&16 unc_r3_c_hi_ad_credits_empty.cbo8 uncore interconnect CBox AD Credits Empty event=0x1f,umask=1  01    No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 8 unc_r3_c_hi_ad_credits_empty.cbo9 uncore interconnect CBox AD Credits Empty event=0x1f,umask=2  01    No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 9 unc_r3_c_hi_ad_credits_empty.cbo_15_17 uncore interconnect CBox AD Credits Empty event=0x1f,umask=0x80  01    No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 15&17 unc_r3_c_lo_ad_credits_empty.cbo0 uncore interconnect CBox AD Credits Empty event=0x22,umask=1  01    No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 0 unc_r3_c_lo_ad_credits_empty.cbo1 uncore interconnect CBox AD Credits Empty event=0x22,umask=2  01    No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 1 unc_r3_c_lo_ad_credits_empty.cbo2 uncore interconnect CBox AD Credits Empty event=0x22,umask=4  01    No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 2 unc_r3_c_lo_ad_credits_empty.cbo3 uncore interconnect CBox AD Credits Empty event=0x22,umask=8  01    No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 3 unc_r3_c_lo_ad_credits_empty.cbo4 uncore interconnect CBox AD Credits Empty event=0x22,umask=0x10  01    No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 4 unc_r3_c_lo_ad_credits_empty.cbo5 uncore interconnect CBox AD Credits Empty event=0x22,umask=0x20  01    No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 5 unc_r3_c_lo_ad_credits_empty.cbo6 uncore interconnect CBox AD Credits Empty event=0x22,umask=0x40  01    No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 6 unc_r3_c_lo_ad_credits_empty.cbo7 uncore interconnect CBox AD Credits Empty event=0x22,umask=0x80  01    No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 7 unc_r3_ha_r2_bl_credits_empty.ha0 uncore interconnect HA/R2 AD Credits Empty event=0x2d,umask=1  01    No credits available to send to either HA or R2 on the BL Ring; HA0 unc_r3_ha_r2_bl_credits_empty.ha1 uncore interconnect HA/R2 AD Credits Empty event=0x2d,umask=2  01    No credits available to send to either HA or R2 on the BL Ring; HA1 unc_r3_ha_r2_bl_credits_empty.r2_ncb uncore interconnect HA/R2 AD Credits Empty event=0x2d,umask=4  01    No credits available to send to either HA or R2 on the BL Ring; R2 NCB Messages unc_r3_ha_r2_bl_credits_empty.r2_ncs uncore interconnect HA/R2 AD Credits Empty event=0x2d,umask=8  01    No credits available to send to either HA or R2 on the BL Ring; R2 NCS Messages unc_r3_iot_backpressure.hub uncore interconnect IOT Backpressure event=0xb,umask=2  01     unc_r3_iot_backpressure.sat uncore interconnect IOT Backpressure event=0xb,umask=1  01     unc_r3_iot_cts_hi.cts2 uncore interconnect IOT Common Trigger Sequencer - Hi event=0xd,umask=1  01    Debug Mask/Match Tie-Ins unc_r3_iot_cts_hi.cts3 uncore interconnect IOT Common Trigger Sequencer - Hi event=0xd,umask=2  01    Debug Mask/Match Tie-Ins unc_r3_iot_cts_lo.cts0 uncore interconnect IOT Common Trigger Sequencer - Lo event=0xc,umask=1  01    Debug Mask/Match Tie-Ins unc_r3_iot_cts_lo.cts1 uncore interconnect IOT Common Trigger Sequencer - Lo event=0xc,umask=2  01    Debug Mask/Match Tie-Ins unc_r3_qpi0_ad_credits_empty.vn0_hom uncore interconnect QPI0 AD Credits Empty event=0x20,umask=2  01    No credits available to send to QPI0 on the AD Ring; VN0 HOM Messages unc_r3_qpi0_ad_credits_empty.vn0_ndr uncore interconnect QPI0 AD Credits Empty event=0x20,umask=8  01    No credits available to send to QPI0 on the AD Ring; VN0 NDR Messages unc_r3_qpi0_ad_credits_empty.vn0_snp uncore interconnect QPI0 AD Credits Empty event=0x20,umask=4  01    No credits available to send to QPI0 on the AD Ring; VN0 SNP Messages unc_r3_qpi0_ad_credits_empty.vn1_hom uncore interconnect QPI0 AD Credits Empty event=0x20,umask=0x10  01    No credits available to send to QPI0 on the AD Ring; VN1 HOM Messages unc_r3_qpi0_ad_credits_empty.vn1_ndr uncore interconnect QPI0 AD Credits Empty event=0x20,umask=0x40  01    No credits available to send to QPI0 on the AD Ring; VN1 NDR Messages unc_r3_qpi0_ad_credits_empty.vn1_snp uncore interconnect QPI0 AD Credits Empty event=0x20,umask=0x20  01    No credits available to send to QPI0 on the AD Ring; VN1 SNP Messages unc_r3_qpi0_ad_credits_empty.vna uncore interconnect QPI0 AD Credits Empty event=0x20,umask=1  01    No credits available to send to QPI0 on the AD Ring; VNA unc_r3_qpi0_bl_credits_empty.vn1_hom uncore interconnect QPI0 BL Credits Empty event=0x21,umask=0x10  01    No credits available to send to QPI0 on the BL Ring; VN1 HOM Messages unc_r3_qpi0_bl_credits_empty.vn1_ndr uncore interconnect QPI0 BL Credits Empty event=0x21,umask=0x40  01    No credits available to send to QPI0 on the BL Ring; VN1 NDR Messages unc_r3_qpi0_bl_credits_empty.vn1_snp uncore interconnect QPI0 BL Credits Empty event=0x21,umask=0x20  01    No credits available to send to QPI0 on the BL Ring; VN1 SNP Messages unc_r3_qpi0_bl_credits_empty.vna uncore interconnect QPI0 BL Credits Empty event=0x21,umask=1  01    No credits available to send to QPI0 on the BL Ring; VNA unc_r3_qpi1_ad_credits_empty.vn1_hom uncore interconnect QPI1 AD Credits Empty event=0x2e,umask=0x10  01    No credits available to send to QPI1 on the AD Ring; VN1 HOM Messages unc_r3_qpi1_ad_credits_empty.vn1_ndr uncore interconnect QPI1 AD Credits Empty event=0x2e,umask=0x40  01    No credits available to send to QPI1 on the AD Ring; VN1 NDR Messages unc_r3_qpi1_ad_credits_empty.vn1_snp uncore interconnect QPI1 AD Credits Empty event=0x2e,umask=0x20  01    No credits available to send to QPI1 on the AD Ring; VN1 SNP Messages unc_r3_qpi1_ad_credits_empty.vna uncore interconnect QPI1 AD Credits Empty event=0x2e,umask=1  01    No credits available to send to QPI1 on the AD Ring; VNA unc_r3_qpi1_bl_credits_empty.vn0_hom uncore interconnect QPI1 BL Credits Empty event=0x2f,umask=2  01    No credits available to send to QPI1 on the BL Ring; VN0 HOM Messages unc_r3_qpi1_bl_credits_empty.vn0_ndr uncore interconnect QPI1 BL Credits Empty event=0x2f,umask=8  01    No credits available to send to QPI1 on the BL Ring; VN0 NDR Messages unc_r3_qpi1_bl_credits_empty.vn0_snp uncore interconnect QPI1 BL Credits Empty event=0x2f,umask=4  01    No credits available to send to QPI1 on the BL Ring; VN0 SNP Messages unc_r3_qpi1_bl_credits_empty.vn1_hom uncore interconnect QPI1 BL Credits Empty event=0x2f,umask=0x10  01    No credits available to send to QPI1 on the BL Ring; VN1 HOM Messages unc_r3_qpi1_bl_credits_empty.vn1_ndr uncore interconnect QPI1 BL Credits Empty event=0x2f,umask=0x40  01    No credits available to send to QPI1 on the BL Ring; VN1 NDR Messages unc_r3_qpi1_bl_credits_empty.vn1_snp uncore interconnect QPI1 BL Credits Empty event=0x2f,umask=0x20  01    No credits available to send to QPI1 on the BL Ring; VN1 SNP Messages unc_r3_qpi1_bl_credits_empty.vna uncore interconnect QPI1 BL Credits Empty event=0x2f,umask=1  01    No credits available to send to QPI1 on the BL Ring; VNA unc_r3_ring_ad_used.all uncore interconnect R3 AD Ring in Use; All event=7,umask=0xf  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ad_used.ccw uncore interconnect R3 AD Ring in Use; Counterclockwise event=7,umask=0xc  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ad_used.ccw_even uncore interconnect R3 AD Ring in Use; Counterclockwise and Even event=7,umask=4  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity unc_r3_ring_ad_used.ccw_odd uncore interconnect R3 AD Ring in Use; Counterclockwise and Odd event=7,umask=8  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity unc_r3_ring_ad_used.cw uncore interconnect R3 AD Ring in Use; Clockwise event=7,umask=3  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ad_used.cw_even uncore interconnect R3 AD Ring in Use; Clockwise and Even event=7,umask=1  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity unc_r3_ring_ad_used.cw_odd uncore interconnect R3 AD Ring in Use; Clockwise and Odd event=7,umask=2  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity unc_r3_ring_ak_used.all uncore interconnect R3 AK Ring in Use; All event=8,umask=0xf  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ak_used.ccw uncore interconnect R3 AK Ring in Use; Counterclockwise event=8,umask=0xc  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ak_used.ccw_even uncore interconnect R3 AK Ring in Use; Counterclockwise and Even event=8,umask=4  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity unc_r3_ring_ak_used.ccw_odd uncore interconnect R3 AK Ring in Use; Counterclockwise and Odd event=8,umask=8  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity unc_r3_ring_ak_used.cw uncore interconnect R3 AK Ring in Use; Clockwise event=8,umask=3  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ak_used.cw_even uncore interconnect R3 AK Ring in Use; Clockwise and Even event=8,umask=1  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity unc_r3_ring_ak_used.cw_odd uncore interconnect R3 AK Ring in Use; Clockwise and Odd event=8,umask=2  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity unc_r3_ring_bl_used.all uncore interconnect R3 BL Ring in Use; All event=9,umask=0xf  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_bl_used.ccw uncore interconnect R3 BL Ring in Use; Counterclockwise event=9,umask=0xc  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_bl_used.ccw_even uncore interconnect R3 BL Ring in Use; Counterclockwise and Even event=9,umask=4  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity unc_r3_ring_bl_used.ccw_odd uncore interconnect R3 BL Ring in Use; Counterclockwise and Odd event=9,umask=8  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity unc_r3_ring_bl_used.cw uncore interconnect R3 BL Ring in Use; Clockwise event=9,umask=3  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_bl_used.cw_even uncore interconnect R3 BL Ring in Use; Clockwise and Even event=9,umask=1  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity unc_r3_ring_bl_used.cw_odd uncore interconnect R3 BL Ring in Use; Clockwise and Odd event=9,umask=2  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity unc_r3_ring_iv_used.any uncore interconnect R3 IV Ring in Use; Any event=0xa,umask=0xf  01    Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop unc_r3_ring_iv_used.cw uncore interconnect R3 IV Ring in Use; Clockwise event=0xa,umask=3  01    Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop unc_r3_ring_sink_starved.ak uncore interconnect Ring Stop Starved; AK event=0xe,umask=2  01    Number of cycles the ringstop is in starvation (per ring) unc_r3_rxr_cycles_ne.hom uncore interconnect Ingress Cycles Not Empty; HOM event=0x10,umask=1  01    Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue unc_r3_rxr_cycles_ne.ndr uncore interconnect Ingress Cycles Not Empty; NDR event=0x10,umask=4  01    Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue unc_r3_rxr_cycles_ne.snp uncore interconnect Ingress Cycles Not Empty; SNP event=0x10,umask=2  01    Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue unc_r3_rxr_cycles_ne_vn1.drs uncore interconnect VN1 Ingress Cycles Not Empty; DRS event=0x14,umask=8  01    Counts the number of cycles when the QPI VN1  Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue unc_r3_rxr_cycles_ne_vn1.hom uncore interconnect VN1 Ingress Cycles Not Empty; HOM event=0x14,umask=1  01    Counts the number of cycles when the QPI VN1  Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue unc_r3_rxr_cycles_ne_vn1.ncb uncore interconnect VN1 Ingress Cycles Not Empty; NCB event=0x14,umask=0x10  01    Counts the number of cycles when the QPI VN1  Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue unc_r3_rxr_cycles_ne_vn1.ncs uncore interconnect VN1 Ingress Cycles Not Empty; NCS event=0x14,umask=0x20  01    Counts the number of cycles when the QPI VN1  Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue unc_r3_rxr_cycles_ne_vn1.ndr uncore interconnect VN1 Ingress Cycles Not Empty; NDR event=0x14,umask=4  01    Counts the number of cycles when the QPI VN1  Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue unc_r3_rxr_cycles_ne_vn1.snp uncore interconnect VN1 Ingress Cycles Not Empty; SNP event=0x14,umask=2  01    Counts the number of cycles when the QPI VN1  Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue unc_r3_rxr_inserts.drs uncore interconnect Ingress Allocations; DRS event=0x11,umask=8  01    Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue unc_r3_rxr_inserts.hom uncore interconnect Ingress Allocations; HOM event=0x11,umask=1  01    Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue unc_r3_rxr_inserts.ncb uncore interconnect Ingress Allocations; NCB event=0x11,umask=0x10  01    Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue unc_r3_rxr_inserts.ncs uncore interconnect Ingress Allocations; NCS event=0x11,umask=0x20  01    Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue unc_r3_rxr_inserts.ndr uncore interconnect Ingress Allocations; NDR event=0x11,umask=4  01    Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue unc_r3_rxr_inserts.snp uncore interconnect Ingress Allocations; SNP event=0x11,umask=2  01    Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue unc_r3_rxr_inserts_vn1.drs uncore interconnect VN1 Ingress Allocations; DRS event=0x15,umask=8  01    Counts the number of allocations into the QPI VN1  Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue unc_r3_rxr_inserts_vn1.hom uncore interconnect VN1 Ingress Allocations; HOM event=0x15,umask=1  01    Counts the number of allocations into the QPI VN1  Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue unc_r3_rxr_inserts_vn1.ncb uncore interconnect VN1 Ingress Allocations; NCB event=0x15,umask=0x10  01    Counts the number of allocations into the QPI VN1  Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue unc_r3_rxr_inserts_vn1.ncs uncore interconnect VN1 Ingress Allocations; NCS event=0x15,umask=0x20  01    Counts the number of allocations into the QPI VN1  Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue unc_r3_rxr_inserts_vn1.ndr uncore interconnect VN1 Ingress Allocations; NDR event=0x15,umask=4  01    Counts the number of allocations into the QPI VN1  Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue unc_r3_rxr_inserts_vn1.snp uncore interconnect VN1 Ingress Allocations; SNP event=0x15,umask=2  01    Counts the number of allocations into the QPI VN1  Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue unc_r3_rxr_occupancy_vn1.drs uncore interconnect VN1 Ingress Occupancy Accumulator; DRS event=0x13,umask=8  01    Accumulates the occupancy of a given QPI VN1  Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI VN1  Ingress Not Empty event to calculate average occupancy or the QPI VN1  Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue unc_r3_rxr_occupancy_vn1.hom uncore interconnect VN1 Ingress Occupancy Accumulator; HOM event=0x13,umask=1  01    Accumulates the occupancy of a given QPI VN1  Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI VN1  Ingress Not Empty event to calculate average occupancy or the QPI VN1  Ingress Allocations event in order to calculate average queuing latency.; HOM Ingress Queue unc_r3_rxr_occupancy_vn1.ncb uncore interconnect VN1 Ingress Occupancy Accumulator; NCB event=0x13,umask=0x10  01    Accumulates the occupancy of a given QPI VN1  Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI VN1  Ingress Not Empty event to calculate average occupancy or the QPI VN1  Ingress Allocations event in order to calculate average queuing latency.; NCB Ingress Queue unc_r3_rxr_occupancy_vn1.ncs uncore interconnect VN1 Ingress Occupancy Accumulator; NCS event=0x13,umask=0x20  01    Accumulates the occupancy of a given QPI VN1  Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI VN1  Ingress Not Empty event to calculate average occupancy or the QPI VN1  Ingress Allocations event in order to calculate average queuing latency.; NCS Ingress Queue unc_r3_rxr_occupancy_vn1.ndr uncore interconnect VN1 Ingress Occupancy Accumulator; NDR event=0x13,umask=4  01    Accumulates the occupancy of a given QPI VN1  Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI VN1  Ingress Not Empty event to calculate average occupancy or the QPI VN1  Ingress Allocations event in order to calculate average queuing latency.; NDR Ingress Queue unc_r3_rxr_occupancy_vn1.snp uncore interconnect VN1 Ingress Occupancy Accumulator; SNP event=0x13,umask=2  01    Accumulates the occupancy of a given QPI VN1  Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI VN1  Ingress Not Empty event to calculate average occupancy or the QPI VN1  Ingress Allocations event in order to calculate average queuing latency.; SNP Ingress Queue unc_r3_sbo0_credits_acquired.ad uncore interconnect SBo0 Credits Acquired; For AD Ring event=0x28,umask=1  01    Number of Sbo 0 credits acquired in a given cycle, per ring unc_r3_sbo0_credits_acquired.bl uncore interconnect SBo0 Credits Acquired; For BL Ring event=0x28,umask=2  01    Number of Sbo 0 credits acquired in a given cycle, per ring unc_r3_sbo0_credit_occupancy.ad uncore interconnect SBo0 Credits Occupancy; For AD Ring event=0x2a,umask=1  01    Number of Sbo 0 credits in use in a given cycle, per ring unc_r3_sbo0_credit_occupancy.bl uncore interconnect SBo0 Credits Occupancy; For BL Ring event=0x2a,umask=2  01    Number of Sbo 0 credits in use in a given cycle, per ring unc_r3_sbo1_credits_acquired.ad uncore interconnect SBo1 Credits Acquired; For AD Ring event=0x29,umask=1  01    Number of Sbo 1 credits acquired in a given cycle, per ring unc_r3_sbo1_credits_acquired.bl uncore interconnect SBo1 Credits Acquired; For BL Ring event=0x29,umask=2  01    Number of Sbo 1 credits acquired in a given cycle, per ring unc_r3_sbo1_credit_occupancy.ad uncore interconnect SBo1 Credits Occupancy; For AD Ring event=0x2b,umask=1  01    Number of Sbo 1 credits in use in a given cycle, per ring unc_r3_sbo1_credit_occupancy.bl uncore interconnect SBo1 Credits Occupancy; For BL Ring event=0x2b,umask=2  01    Number of Sbo 1 credits in use in a given cycle, per ring unc_r3_stall_no_sbo_credit.sbo0_ad uncore interconnect Stall on No Sbo Credits; For SBo0, AD Ring event=0x2c,umask=1  01    Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring unc_r3_stall_no_sbo_credit.sbo0_bl uncore interconnect Stall on No Sbo Credits; For SBo0, BL Ring event=0x2c,umask=4  01    Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring unc_r3_stall_no_sbo_credit.sbo1_ad uncore interconnect Stall on No Sbo Credits; For SBo1, AD Ring event=0x2c,umask=2  01    Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring unc_r3_stall_no_sbo_credit.sbo1_bl uncore interconnect Stall on No Sbo Credits; For SBo1, BL Ring event=0x2c,umask=8  01    Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring unc_r3_txr_nack.dn_ad uncore interconnect Egress CCW NACK; AD CCW event=0x26,umask=1  01    AD CounterClockwise Egress Queue unc_r3_txr_nack.dn_ak uncore interconnect Egress CCW NACK; AK CCW event=0x26,umask=4  01    AK CounterClockwise Egress Queue unc_r3_txr_nack.dn_bl uncore interconnect Egress CCW NACK; BL CCW event=0x26,umask=2  01    BL CounterClockwise Egress Queue unc_r3_txr_nack.up_ad uncore interconnect Egress CCW NACK; AK CCW event=0x26,umask=8  01    BL CounterClockwise Egress Queue unc_r3_txr_nack.up_ak uncore interconnect Egress CCW NACK; BL CW event=0x26,umask=0x20  01    AD Clockwise Egress Queue unc_r3_txr_nack.up_bl uncore interconnect Egress CCW NACK; BL CCW event=0x26,umask=0x10  01    AD CounterClockwise Egress Queue unc_r3_vn0_credits_reject.drs uncore interconnect VN0 Credit Acquisition Failed on DRS; DRS Message Class event=0x37,umask=8  01    Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; Filter for Data Response (DRS).  DRS is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS unc_r3_vn0_credits_reject.hom uncore interconnect VN0 Credit Acquisition Failed on DRS; HOM Message Class event=0x37,umask=1  01    Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses unc_r3_vn0_credits_reject.ncb uncore interconnect VN0 Credit Acquisition Failed on DRS; NCB Message Class event=0x37,umask=0x10  01    Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB).  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_r3_vn0_credits_reject.ncs uncore interconnect VN0 Credit Acquisition Failed on DRS; NCS Message Class event=0x37,umask=0x20  01    Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS).  NCS is commonly used for ? unc_r3_vn0_credits_reject.ndr uncore interconnect VN0 Credit Acquisition Failed on DRS; NDR Message Class event=0x37,umask=4  01    Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_r3_vn0_credits_reject.snp uncore interconnect VN0 Credit Acquisition Failed on DRS; SNP Message Class event=0x37,umask=2  01    Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; Filter for Snoop (SNP) message class.  SNP is used for outgoing snoops.  Note that snoop responses flow on the HOM message class unc_r3_vn0_credits_used.drs uncore interconnect VN0 Credit Used; DRS Message Class event=0x36,umask=8  01    Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS).  DRS is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS unc_r3_vn0_credits_used.hom uncore interconnect VN0 Credit Used; HOM Message Class event=0x36,umask=1  01    Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses unc_r3_vn0_credits_used.ncb uncore interconnect VN0 Credit Used; NCB Message Class event=0x36,umask=0x10  01    Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB).  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_r3_vn0_credits_used.ncs uncore interconnect VN0 Credit Used; NCS Message Class event=0x36,umask=0x20  01    Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS).  NCS is commonly used for ? unc_r3_vn0_credits_used.ndr uncore interconnect VN0 Credit Used; NDR Message Class event=0x36,umask=4  01    Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_r3_vn0_credits_used.snp uncore interconnect VN0 Credit Used; SNP Message Class event=0x36,umask=2  01    Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class.  SNP is used for outgoing snoops.  Note that snoop responses flow on the HOM message class unc_r3_vn1_credits_reject.drs uncore interconnect VN1 Credit Acquisition Failed on DRS; DRS Message Class event=0x39,umask=8  01    Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; Filter for Data Response (DRS).  DRS is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS unc_r3_vn1_credits_reject.hom uncore interconnect VN1 Credit Acquisition Failed on DRS; HOM Message Class event=0x39,umask=1  01    Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses unc_r3_vn1_credits_reject.ncb uncore interconnect VN1 Credit Acquisition Failed on DRS; NCB Message Class event=0x39,umask=0x10  01    Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB).  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_r3_vn1_credits_reject.ncs uncore interconnect VN1 Credit Acquisition Failed on DRS; NCS Message Class event=0x39,umask=0x20  01    Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS).  NCS is commonly used for ? unc_r3_vn1_credits_reject.ndr uncore interconnect VN1 Credit Acquisition Failed on DRS; NDR Message Class event=0x39,umask=4  01    Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_r3_vn1_credits_reject.snp uncore interconnect VN1 Credit Acquisition Failed on DRS; SNP Message Class event=0x39,umask=2  01    Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; Filter for Snoop (SNP) message class.  SNP is used for outgoing snoops.  Note that snoop responses flow on the HOM message class unc_r3_vn1_credits_used.drs uncore interconnect VN1 Credit Used; DRS Message Class event=0x38,umask=8  01    Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS).  DRS is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS unc_r3_vn1_credits_used.hom uncore interconnect VN1 Credit Used; HOM Message Class event=0x38,umask=1  01    Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses unc_r3_vn1_credits_used.ncb uncore interconnect VN1 Credit Used; NCB Message Class event=0x38,umask=0x10  01    Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB).  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_r3_vn1_credits_used.ncs uncore interconnect VN1 Credit Used; NCS Message Class event=0x38,umask=0x20  01    Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS).  NCS is commonly used for ? unc_r3_vn1_credits_used.ndr uncore interconnect VN1 Credit Used; NDR Message Class event=0x38,umask=4  01    Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_r3_vn1_credits_used.snp uncore interconnect VN1 Credit Used; SNP Message Class event=0x38,umask=2  01    Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class.  SNP is used for outgoing snoops.  Note that snoop responses flow on the HOM message class unc_r3_vna_credits_acquired.ad uncore interconnect VNA credit Acquisitions; HOM Message Class event=0x33,umask=1  01    Number of QPI VNA Credit acquisitions.  This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder.  VNA credits are used by all message classes in order to communicate across QPI.  If a packet is unable to acquire credits, it will then attempt to use credits from the VN0 pool.  Note that a single packet may require multiple flit buffers (i.e. when data is being transferred).  Therefore, this event will increment by the number of credits acquired in each cycle.  Filtering based on message class is not provided.  One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses unc_r3_vna_credits_acquired.bl uncore interconnect VNA credit Acquisitions; HOM Message Class event=0x33,umask=4  01    Number of QPI VNA Credit acquisitions.  This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder.  VNA credits are used by all message classes in order to communicate across QPI.  If a packet is unable to acquire credits, it will then attempt to use credits from the VN0 pool.  Note that a single packet may require multiple flit buffers (i.e. when data is being transferred).  Therefore, this event will increment by the number of credits acquired in each cycle.  Filtering based on message class is not provided.  One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses unc_r3_vna_credits_reject.drs uncore interconnect VNA Credit Reject; DRS Message Class event=0x34,umask=8  01    Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Data Response (DRS).  DRS is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS unc_r3_vna_credits_reject.hom uncore interconnect VNA Credit Reject; HOM Message Class event=0x34,umask=1  01    Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses unc_r3_vna_credits_reject.ncb uncore interconnect VNA Credit Reject; NCB Message Class event=0x34,umask=0x10  01    Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Broadcast (NCB).  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_r3_vna_credits_reject.ncs uncore interconnect VNA Credit Reject; NCS Message Class event=0x34,umask=0x20  01    Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Standard (NCS) unc_r3_vna_credits_reject.ndr uncore interconnect VNA Credit Reject; NDR Message Class event=0x34,umask=4  01    Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_r3_vna_credits_reject.snp uncore interconnect VNA Credit Reject; SNP Message Class event=0x34,umask=2  01    Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Snoop (SNP) message class.  SNP is used for outgoing snoops.  Note that snoop responses flow on the HOM message class uncore_sbox unc_s_bounce_control uncore interconnect Bounce Control event=0xa  01     unc_s_clockticks uncore interconnect Uncore Clocks event=0  01     unc_s_fast_asserted uncore interconnect FaST wire asserted event=9  01    Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across unc_s_ring_ad_used.all uncore interconnect AD Ring In Use; All event=0x1b,umask=0xf  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_s_ring_ad_used.down uncore interconnect AD Ring In Use; Down event=0x1b,umask=0xc  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_s_ring_ad_used.down_even uncore interconnect AD Ring In Use; Down and Event event=0x1b,umask=4  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity unc_s_ring_ad_used.down_odd uncore interconnect AD Ring In Use; Down and Odd event=0x1b,umask=8  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_s_ring_ad_used.up uncore interconnect AD Ring In Use; Up event=0x1b,umask=3  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_s_ring_ad_used.up_even uncore interconnect AD Ring In Use; Up and Even event=0x1b,umask=1  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_s_ring_ad_used.up_odd uncore interconnect AD Ring In Use; Up and Odd event=0x1b,umask=2  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_s_ring_ak_used.all uncore interconnect AK Ring In Use; All event=0x1c,umask=0xf  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_s_ring_ak_used.down uncore interconnect AK Ring In Use; Down event=0x1c,umask=0xc  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_s_ring_ak_used.down_even uncore interconnect AK Ring In Use; Down and Event event=0x1c,umask=4  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity unc_s_ring_ak_used.down_odd uncore interconnect AK Ring In Use; Down and Odd event=0x1c,umask=8  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_s_ring_ak_used.up uncore interconnect AK Ring In Use; Up event=0x1c,umask=3  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_s_ring_ak_used.up_even uncore interconnect AK Ring In Use; Up and Even event=0x1c,umask=1  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_s_ring_ak_used.up_odd uncore interconnect AK Ring In Use; Up and Odd event=0x1c,umask=2  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_s_ring_bl_used.all uncore interconnect BL Ring in Use; All event=0x1d,umask=0xf  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_s_ring_bl_used.down uncore interconnect BL Ring in Use; Down event=0x1d,umask=0xc  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_s_ring_bl_used.down_even uncore interconnect BL Ring in Use; Down and Event event=0x1d,umask=4  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity unc_s_ring_bl_used.down_odd uncore interconnect BL Ring in Use; Down and Odd event=0x1d,umask=8  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_s_ring_bl_used.up uncore interconnect BL Ring in Use; Up event=0x1d,umask=3  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_s_ring_bl_used.up_even uncore interconnect BL Ring in Use; Up and Even event=0x1d,umask=1  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_s_ring_bl_used.up_odd uncore interconnect BL Ring in Use; Up and Odd event=0x1d,umask=2  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_s_ring_bounces.ad_cache uncore interconnect Number of LLC responses that bounced on the Ring event=5,umask=1  01     unc_s_ring_bounces.ak_core uncore interconnect Number of LLC responses that bounced on the Ring.; Acknowledgements to core event=5,umask=2  01     unc_s_ring_bounces.bl_core uncore interconnect Number of LLC responses that bounced on the Ring.; Data Responses to core event=5,umask=4  01     unc_s_ring_bounces.iv_core uncore interconnect Number of LLC responses that bounced on the Ring.; Snoops of processor's cache event=5,umask=8  01     unc_s_ring_iv_used.dn uncore interconnect BL Ring in Use; Any event=0x1e,umask=0xc  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  There is only 1 IV ring in HSX.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity unc_s_ring_iv_used.up uncore interconnect BL Ring in Use; Any event=0x1e,umask=3  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  There is only 1 IV ring in HSX.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity unc_s_ring_sink_starved.ad_cache uncore interconnect UNC_S_RING_SINK_STARVED.AD_CACHE event=6,umask=1  01     unc_s_ring_sink_starved.ak_core uncore interconnect UNC_S_RING_SINK_STARVED.AK_CORE event=6,umask=2  01     unc_s_ring_sink_starved.bl_core uncore interconnect UNC_S_RING_SINK_STARVED.BL_CORE event=6,umask=4  01     unc_s_ring_sink_starved.iv_core uncore interconnect UNC_S_RING_SINK_STARVED.IV_CORE event=6,umask=8  01     unc_s_rxr_busy_starved.ad_bnc uncore interconnect Injection Starvation; AD - Bounces event=0x15,umask=2  01    Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is  being sent unc_s_rxr_busy_starved.ad_crd uncore interconnect Injection Starvation; AD - Credits event=0x15,umask=1  01    Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is  being sent unc_s_rxr_busy_starved.bl_bnc uncore interconnect Injection Starvation; BL - Bounces event=0x15,umask=8  01    Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is  being sent unc_s_rxr_busy_starved.bl_crd uncore interconnect Injection Starvation; BL - Credits event=0x15,umask=4  01    Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is  being sent unc_s_rxr_bypass.ad_bnc uncore interconnect Bypass; AD - Bounces event=0x12,umask=2  01    Bypass the Sbo Ingress unc_s_rxr_bypass.ad_crd uncore interconnect Bypass; AD - Credits event=0x12,umask=1  01    Bypass the Sbo Ingress unc_s_rxr_bypass.ak uncore interconnect Bypass; AK event=0x12,umask=0x10  01    Bypass the Sbo Ingress unc_s_rxr_bypass.bl_bnc uncore interconnect Bypass; BL - Bounces event=0x12,umask=8  01    Bypass the Sbo Ingress unc_s_rxr_bypass.bl_crd uncore interconnect Bypass; BL - Credits event=0x12,umask=4  01    Bypass the Sbo Ingress unc_s_rxr_bypass.iv uncore interconnect Bypass; IV event=0x12,umask=0x20  01    Bypass the Sbo Ingress unc_s_rxr_crd_starved.ad_bnc uncore interconnect Injection Starvation; AD - Bounces event=0x14,umask=2  01    Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress due to lack of credit unc_s_rxr_crd_starved.ad_crd uncore interconnect Injection Starvation; AD - Credits event=0x14,umask=1  01    Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress due to lack of credit unc_s_rxr_crd_starved.ak uncore interconnect Injection Starvation; AK event=0x14,umask=0x10  01    Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress due to lack of credit unc_s_rxr_crd_starved.bl_bnc uncore interconnect Injection Starvation; BL - Bounces event=0x14,umask=8  01    Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress due to lack of credit unc_s_rxr_crd_starved.bl_crd uncore interconnect Injection Starvation; BL - Credits event=0x14,umask=4  01    Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress due to lack of credit unc_s_rxr_crd_starved.ifv uncore interconnect Injection Starvation; IVF Credit event=0x14,umask=0x40  01    Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress due to lack of credit unc_s_rxr_crd_starved.iv uncore interconnect Injection Starvation; IV event=0x14,umask=0x20  01    Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress due to lack of credit unc_s_rxr_inserts.ad_bnc uncore interconnect Ingress Allocations; AD - Bounces event=0x13,umask=2  01    Number of allocations into the Sbo Ingress  The Ingress is used to queue up requests received from the ring unc_s_rxr_inserts.ad_crd uncore interconnect Ingress Allocations; AD - Credits event=0x13,umask=1  01    Number of allocations into the Sbo Ingress  The Ingress is used to queue up requests received from the ring unc_s_rxr_inserts.ak uncore interconnect Ingress Allocations; AK event=0x13,umask=0x10  01    Number of allocations into the Sbo Ingress  The Ingress is used to queue up requests received from the ring unc_s_rxr_inserts.bl_bnc uncore interconnect Ingress Allocations; BL - Bounces event=0x13,umask=8  01    Number of allocations into the Sbo Ingress  The Ingress is used to queue up requests received from the ring unc_s_rxr_inserts.bl_crd uncore interconnect Ingress Allocations; BL - Credits event=0x13,umask=4  01    Number of allocations into the Sbo Ingress  The Ingress is used to queue up requests received from the ring unc_s_rxr_inserts.iv uncore interconnect Ingress Allocations; IV event=0x13,umask=0x20  01    Number of allocations into the Sbo Ingress  The Ingress is used to queue up requests received from the ring unc_s_rxr_occupancy.ad_bnc uncore interconnect Ingress Occupancy; AD - Bounces event=0x11,umask=2  01    Occupancy event for the Ingress buffers in the Sbo.  The Ingress is used to queue up requests received from the ring unc_s_rxr_occupancy.ad_crd uncore interconnect Ingress Occupancy; AD - Credits event=0x11,umask=1  01    Occupancy event for the Ingress buffers in the Sbo.  The Ingress is used to queue up requests received from the ring unc_s_rxr_occupancy.ak uncore interconnect Ingress Occupancy; AK event=0x11,umask=0x10  01    Occupancy event for the Ingress buffers in the Sbo.  The Ingress is used to queue up requests received from the ring unc_s_rxr_occupancy.bl_bnc uncore interconnect Ingress Occupancy; BL - Bounces event=0x11,umask=8  01    Occupancy event for the Ingress buffers in the Sbo.  The Ingress is used to queue up requests received from the ring unc_s_rxr_occupancy.bl_crd uncore interconnect Ingress Occupancy; BL - Credits event=0x11,umask=4  01    Occupancy event for the Ingress buffers in the Sbo.  The Ingress is used to queue up requests received from the ring unc_s_rxr_occupancy.iv uncore interconnect Ingress Occupancy; IV event=0x11,umask=0x20  01    Occupancy event for the Ingress buffers in the Sbo.  The Ingress is used to queue up requests received from the ring unc_s_txr_ads_used.ad uncore interconnect UNC_S_TxR_ADS_USED.AD event=4,umask=1  01     unc_s_txr_ads_used.ak uncore interconnect UNC_S_TxR_ADS_USED.AK event=4,umask=2  01     unc_s_txr_ads_used.bl uncore interconnect UNC_S_TxR_ADS_USED.BL event=4,umask=4  01     unc_s_txr_inserts.ad_bnc uncore interconnect Egress Allocations; AD - Bounces event=2,umask=2  01    Number of allocations into the Sbo Egress.  The Egress is used to queue up requests destined for the ring unc_s_txr_inserts.ad_crd uncore interconnect Egress Allocations; AD - Credits event=2,umask=1  01    Number of allocations into the Sbo Egress.  The Egress is used to queue up requests destined for the ring unc_s_txr_inserts.ak uncore interconnect Egress Allocations; AK event=2,umask=0x10  01    Number of allocations into the Sbo Egress.  The Egress is used to queue up requests destined for the ring unc_s_txr_inserts.bl_bnc uncore interconnect Egress Allocations; BL - Bounces event=2,umask=8  01    Number of allocations into the Sbo Egress.  The Egress is used to queue up requests destined for the ring unc_s_txr_inserts.bl_crd uncore interconnect Egress Allocations; BL - Credits event=2,umask=4  01    Number of allocations into the Sbo Egress.  The Egress is used to queue up requests destined for the ring unc_s_txr_inserts.iv uncore interconnect Egress Allocations; IV event=2,umask=0x20  01    Number of allocations into the Sbo Egress.  The Egress is used to queue up requests destined for the ring unc_s_txr_occupancy.ad_bnc uncore interconnect Egress Occupancy; AD - Bounces event=1,umask=2  01    Occupancy event for the Egress buffers in the Sbo.  The egress is used to queue up requests destined for the ring unc_s_txr_occupancy.ad_crd uncore interconnect Egress Occupancy; AD - Credits event=1,umask=1  01    Occupancy event for the Egress buffers in the Sbo.  The egress is used to queue up requests destined for the ring unc_s_txr_occupancy.ak uncore interconnect Egress Occupancy; AK event=1,umask=0x10  01    Occupancy event for the Egress buffers in the Sbo.  The egress is used to queue up requests destined for the ring unc_s_txr_occupancy.bl_bnc uncore interconnect Egress Occupancy; BL - Bounces event=1,umask=8  01    Occupancy event for the Egress buffers in the Sbo.  The egress is used to queue up requests destined for the ring unc_s_txr_occupancy.bl_crd uncore interconnect Egress Occupancy; BL - Credits event=1,umask=4  01    Occupancy event for the Egress buffers in the Sbo.  The egress is used to queue up requests destined for the ring unc_s_txr_occupancy.iv uncore interconnect Egress Occupancy; IV event=1,umask=0x20  01    Occupancy event for the Egress buffers in the Sbo.  The egress is used to queue up requests destined for the ring unc_s_txr_starved.ad uncore interconnect Injection Starvation; Onto AD Ring event=3,umask=1  01    Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time unc_s_txr_starved.ak uncore interconnect Injection Starvation; Onto AK Ring event=3,umask=2  01    Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time unc_s_txr_starved.bl uncore interconnect Injection Starvation; Onto BL Ring event=3,umask=4  01    Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time unc_s_txr_starved.iv uncore interconnect Injection Starvation; Onto IV Ring event=3,umask=8  01    Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time unc_u_clockticks uncore interconnect Clockticks in the UBOX using a dedicated 48-bit Fixed Counter event=0xff  01     llc_misses.mem_read uncore memory read requests to memory controller. Derived from unc_m_cas_count.rd event=4,umask=3  0164Bytes    DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS commands issued on this channel (including underfills) llc_misses.mem_write uncore memory write requests to memory controller. Derived from unc_m_cas_count.wr event=4,umask=0xc  0164Bytes    DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS commands issued on this channel unc_m_clockticks uncore memory Clockticks in the Memory Controller using a dedicated 48-bit Fixed Counter event=0xff  01     unc_m_clockticks_p uncore memory Clockticks in the Memory Controller using one of the programmable counters event=0  01     unc_m_dclockticks uncore memory This event is deprecated. Refer to new event UNC_M_CLOCKTICKS_P event=0  11     core_snoop_response.rsp_ifwdfe cache CORE_SNOOP_RESPONSE.RSP_IFWDFE event=0xef,period=2000003,umask=0x20  00     core_snoop_response.rsp_ifwdm cache CORE_SNOOP_RESPONSE.RSP_IFWDM event=0xef,period=2000003,umask=0x10  00     core_snoop_response.rsp_ihitfse cache CORE_SNOOP_RESPONSE.RSP_IHITFSE event=0xef,period=2000003,umask=2  00     core_snoop_response.rsp_ihiti cache CORE_SNOOP_RESPONSE.RSP_IHITI event=0xef,period=2000003,umask=1  00     core_snoop_response.rsp_sfwdfe cache CORE_SNOOP_RESPONSE.RSP_SFWDFE event=0xef,period=2000003,umask=0x40  00     core_snoop_response.rsp_sfwdm cache CORE_SNOOP_RESPONSE.RSP_SFWDM event=0xef,period=2000003,umask=8  00     core_snoop_response.rsp_shitfse cache CORE_SNOOP_RESPONSE.RSP_SHITFSE event=0xef,period=2000003,umask=4  00     idi_misc.wb_downgrade cache Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly event=0xfe,period=100003,umask=4  00     idi_misc.wb_upgrade cache Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly event=0xfe,period=100003,umask=2  00     l1d.replacement cache L1D data line replacements event=0x51,period=2000003,umask=1  00    Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace l1d_pend_miss.fb_full cache Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch event=0x48,period=2000003,umask=2  00    Number of times a request needed a FB (Fill Buffer) entry but there was no entry available for it. A request includes cacheable/uncacheable demands that are load, store or SW prefetch instructions l1d_pend_miss.pending cache L1D miss outstandings duration in cycles event=0x48,period=2000003,umask=1  00    Counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch.Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type l1d_pend_miss.pending_cycles cache Cycles with L1D load Misses outstanding event=0x48,cmask=1,period=2000003,umask=1  00    Counts duration of L1D miss outstanding in cycles l2_lines_in.all cache L2 cache lines filling L2 event=0xf1,period=100003,umask=0x1f  00    Counts the number of L2 cache lines filling the L2. Counting does not cover rejects l2_lines_out.non_silent cache Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3.  Clean lines may either be allocated in L3 or dropped event=0xf2,period=200003,umask=2  00     l2_lines_out.silent cache Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared state. A non-threaded event event=0xf2,period=200003,umask=1  00     l2_lines_out.useless_hwpf cache Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cache event=0xf2,period=200003,umask=4  00     l2_lines_out.useless_pref cache This event is deprecated. Refer to new event L2_LINES_OUT.USELESS_HWPF event=0xf2,period=200003,umask=4  10     l2_rqsts.all_demand_data_rd cache Demand Data Read requests event=0x24,period=200003,umask=0xe1  00    Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted l2_rqsts.all_pf cache Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches event=0x24,period=200003,umask=0xf8  00    Counts the total number of requests from the L2 hardware prefetchers l2_rqsts.demand_data_rd_miss cache Demand Data Read miss L2, no rejects event=0x24,period=200003,umask=0x21  00    Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted l2_rqsts.pf_hit cache Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache event=0x24,period=200003,umask=0xd8  00    Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache l2_rqsts.pf_miss cache Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache event=0x24,period=200003,umask=0x38  00    Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache l2_trans.l2_wb cache L2 writebacks that access L2 cache event=0xf0,period=200003,umask=0x40  00    Counts L2 writebacks that access L2 cache longest_lat_cache.miss cache Core-originated cacheable demand requests missed L3  Spec update: SKL057 event=0x2e,period=100003,umask=0x41  00    Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all misses to the L3  Spec update: SKL057 longest_lat_cache.reference cache Core-originated cacheable demand requests that refer to L3  Spec update: SKL057 event=0x2e,period=100003,umask=0x4f  00    Counts core-originated cacheable requests to the  L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2.  It does not include all accesses to the L3  Spec update: SKL057 mem_inst_retired.all_loads cache Retired load instructions  Supports address when precise (Precise event) event=0xd0,period=2000003,umask=0x81  00    Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW  Supports address when precise (Precise event) mem_inst_retired.all_stores cache Retired store instructions  Supports address when precise (Precise event) event=0xd0,period=2000003,umask=0x82  00    Counts all retired store instructions  Supports address when precise (Precise event) mem_inst_retired.any cache All retired memory instructions  Supports address when precise (Precise event) event=0xd0,period=2000003,umask=0x83  00    Counts all retired memory instructions - loads and stores  Supports address when precise (Precise event) mem_inst_retired.lock_loads cache Retired load instructions with locked access  Supports address when precise (Precise event) event=0xd0,period=100007,umask=0x21  00     mem_inst_retired.split_loads cache Retired load instructions that split across a cacheline boundary  Supports address when precise (Precise event) event=0xd0,period=100003,umask=0x41  00    Counts retired load instructions that split across a cacheline boundary  Supports address when precise (Precise event) mem_inst_retired.split_stores cache Retired store instructions that split across a cacheline boundary  Supports address when precise (Precise event) event=0xd0,period=100003,umask=0x42  00    Counts retired store instructions that split across a cacheline boundary  Supports address when precise (Precise event) mem_inst_retired.stlb_miss_loads cache Retired load instructions that miss the STLB  Supports address when precise (Precise event) event=0xd0,period=100003,umask=0x11  00    Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB)  Supports address when precise (Precise event) mem_inst_retired.stlb_miss_stores cache Retired store instructions that miss the STLB  Supports address when precise (Precise event) event=0xd0,period=100003,umask=0x12  00    Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB)  Supports address when precise (Precise event) mem_load_l3_hit_retired.xsnp_hit cache Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache  Supports address when precise (Precise event) event=0xd2,period=20011,umask=2  00     mem_load_l3_hit_retired.xsnp_hitm cache Retired load instructions which data sources were HitM responses from shared L3  Supports address when precise (Precise event) event=0xd2,period=20011,umask=4  00     mem_load_l3_hit_retired.xsnp_miss cache Retired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache  Supports address when precise (Precise event) event=0xd2,period=20011,umask=1  00     mem_load_l3_hit_retired.xsnp_none cache Retired load instructions which data sources were hits in L3 without snoops required  Supports address when precise (Precise event) event=0xd2,period=100003,umask=8  00     mem_load_l3_miss_retired.local_dram cache Retired load instructions which data sources missed L3 but serviced from local dram  Supports address when precise (Precise event) event=0xd3,period=100007,umask=1  00    Retired load instructions which data sources missed L3 but serviced from local DRAM  Supports address when precise (Precise event) mem_load_l3_miss_retired.remote_dram cache Retired load instructions which data sources missed L3 but serviced from remote dram  Supports address when precise (Precise event) event=0xd3,period=100007,umask=2  00     mem_load_l3_miss_retired.remote_fwd cache Retired load instructions whose data sources was forwarded from a remote cache  Supports address when precise event=0xd3,period=100007,umask=8  00     mem_load_l3_miss_retired.remote_hitm cache Retired load instructions whose data sources was remote HITM  Supports address when precise (Precise event) event=0xd3,period=100007,umask=4  00     mem_load_l3_miss_retired.remote_pmm cache Retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches  Supports address when precise (Precise event) event=0xd3,period=100007,umask=0x10  00    Counts retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode)  Supports address when precise (Precise event) mem_load_misc_retired.uc cache Retired instructions with at least 1 uncacheable load or lock  Supports address when precise (Precise event) event=0xd4,period=100007,umask=4  00     mem_load_retired.fb_hit cache Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready  Supports address when precise (Precise event) event=0xd1,period=100007,umask=0x40  00    Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready  Supports address when precise (Precise event) mem_load_retired.l1_hit cache Retired load instructions with L1 cache hits as data sources  Supports address when precise (Precise event) event=0xd1,period=2000003,umask=1  00    Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source  Supports address when precise (Precise event) mem_load_retired.l1_miss cache Retired load instructions missed L1 cache as data sources  Supports address when precise (Precise event) event=0xd1,period=100003,umask=8  00    Counts retired load instructions with at least one uop that missed in the L1 cache  Supports address when precise (Precise event) mem_load_retired.l2_hit cache Retired load instructions with L2 cache hits as data sources  Supports address when precise (Precise event) event=0xd1,period=100003,umask=2  00     mem_load_retired.l2_miss cache Retired load instructions missed L2 cache as data sources  Supports address when precise (Precise event) event=0xd1,period=50021,umask=0x10  00     mem_load_retired.l3_hit cache Retired load instructions with L3 cache hits as data sources  Supports address when precise (Precise event) event=0xd1,period=50021,umask=4  00    Counts retired load instructions with at least one uop that hit in the L3 cache  Supports address when precise (Precise event) mem_load_retired.l3_miss cache Retired load instructions missed L3 cache as data sources  Supports address when precise (Precise event) event=0xd1,period=100007,umask=0x20  00    Counts retired load instructions with at least one uop that missed in the L3 cache  Supports address when precise (Precise event) mem_load_retired.local_pmm cache Retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches  Supports address when precise (Precise event) event=0xd1,period=100003,umask=0x80  00    Counts retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode)  Supports address when precise (Precise event) ocr.all_data_rd.l3_hit.any_snoop cache OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0491  00     ocr.all_data_rd.l3_hit.hitm_other_core cache OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0491  00     ocr.all_data_rd.l3_hit.hit_other_core_fwd cache OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0491  00     ocr.all_data_rd.l3_hit.hit_other_core_no_fwd cache OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0491  00     ocr.all_data_rd.l3_hit.no_snoop_needed cache OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0491  00     ocr.all_data_rd.l3_hit.snoop_hit_with_fwd cache OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0491  00     ocr.all_data_rd.l3_hit.snoop_miss cache OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0491  00     ocr.all_data_rd.l3_hit.snoop_none cache OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0491  00     ocr.all_data_rd.l3_hit_e.any_snoop cache OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP  OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080491  00     ocr.all_data_rd.l3_hit_e.hitm_other_core cache OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE  OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080491  00     ocr.all_data_rd.l3_hit_e.hit_other_core_fwd cache OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD  OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080491  00     ocr.all_data_rd.l3_hit_e.hit_other_core_no_fwd cache OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD  OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080491  00     ocr.all_data_rd.l3_hit_e.no_snoop_needed cache OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED  OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080491  00     ocr.all_data_rd.l3_hit_e.snoop_miss cache OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200080491  00     ocr.all_data_rd.l3_hit_e.snoop_none cache OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80080491  00     ocr.all_data_rd.l3_hit_f.any_snoop cache OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP  OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200491  00     ocr.all_data_rd.l3_hit_f.hitm_other_core cache OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE  OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200491  00     ocr.all_data_rd.l3_hit_f.hit_other_core_fwd cache OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD  OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200491  00     ocr.all_data_rd.l3_hit_f.hit_other_core_no_fwd cache OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD  OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200491  00     ocr.all_data_rd.l3_hit_f.no_snoop_needed cache OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED  OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200491  00     ocr.all_data_rd.l3_hit_f.snoop_miss cache OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200200491  00     ocr.all_data_rd.l3_hit_f.snoop_none cache OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80200491  00     ocr.all_data_rd.l3_hit_m.any_snoop cache OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP  OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040491  00     ocr.all_data_rd.l3_hit_m.hitm_other_core cache OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE  OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040491  00     ocr.all_data_rd.l3_hit_m.hit_other_core_fwd cache OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD  OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040491  00     ocr.all_data_rd.l3_hit_m.hit_other_core_no_fwd cache OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD  OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040491  00     ocr.all_data_rd.l3_hit_m.no_snoop_needed cache OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED  OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040491  00     ocr.all_data_rd.l3_hit_m.snoop_miss cache OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200040491  00     ocr.all_data_rd.l3_hit_m.snoop_none cache OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80040491  00     ocr.all_data_rd.l3_hit_s.any_snoop cache OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP  OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100491  00     ocr.all_data_rd.l3_hit_s.hitm_other_core cache OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE  OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100491  00     ocr.all_data_rd.l3_hit_s.hit_other_core_fwd cache OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD  OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100491  00     ocr.all_data_rd.l3_hit_s.hit_other_core_no_fwd cache OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD  OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100491  00     ocr.all_data_rd.l3_hit_s.no_snoop_needed cache OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED  OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100491  00     ocr.all_data_rd.l3_hit_s.snoop_miss cache OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200100491  00     ocr.all_data_rd.l3_hit_s.snoop_none cache OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80100491  00     ocr.all_pf_data_rd.l3_hit.any_snoop cache OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0490  00     ocr.all_pf_data_rd.l3_hit.hitm_other_core cache OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0490  00     ocr.all_pf_data_rd.l3_hit.hit_other_core_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0490  00     ocr.all_pf_data_rd.l3_hit.hit_other_core_no_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0490  00     ocr.all_pf_data_rd.l3_hit.no_snoop_needed cache OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0490  00     ocr.all_pf_data_rd.l3_hit.snoop_hit_with_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0490  00     ocr.all_pf_data_rd.l3_hit.snoop_miss cache OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0490  00     ocr.all_pf_data_rd.l3_hit.snoop_none cache OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0490  00     ocr.all_pf_data_rd.l3_hit_e.any_snoop cache OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP  OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080490  00     ocr.all_pf_data_rd.l3_hit_e.hitm_other_core cache OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE  OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080490  00     ocr.all_pf_data_rd.l3_hit_e.hit_other_core_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD  OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080490  00     ocr.all_pf_data_rd.l3_hit_e.hit_other_core_no_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080490  00     ocr.all_pf_data_rd.l3_hit_e.no_snoop_needed cache OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED  OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080490  00     ocr.all_pf_data_rd.l3_hit_e.snoop_miss cache OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200080490  00     ocr.all_pf_data_rd.l3_hit_e.snoop_none cache OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80080490  00     ocr.all_pf_data_rd.l3_hit_f.any_snoop cache OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP  OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200490  00     ocr.all_pf_data_rd.l3_hit_f.hitm_other_core cache OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE  OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200490  00     ocr.all_pf_data_rd.l3_hit_f.hit_other_core_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD  OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200490  00     ocr.all_pf_data_rd.l3_hit_f.hit_other_core_no_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200490  00     ocr.all_pf_data_rd.l3_hit_f.no_snoop_needed cache OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED  OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200490  00     ocr.all_pf_data_rd.l3_hit_f.snoop_miss cache OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200200490  00     ocr.all_pf_data_rd.l3_hit_f.snoop_none cache OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80200490  00     ocr.all_pf_data_rd.l3_hit_m.any_snoop cache OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP  OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040490  00     ocr.all_pf_data_rd.l3_hit_m.hitm_other_core cache OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE  OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040490  00     ocr.all_pf_data_rd.l3_hit_m.hit_other_core_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD  OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040490  00     ocr.all_pf_data_rd.l3_hit_m.hit_other_core_no_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040490  00     ocr.all_pf_data_rd.l3_hit_m.no_snoop_needed cache OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED  OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040490  00     ocr.all_pf_data_rd.l3_hit_m.snoop_miss cache OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200040490  00     ocr.all_pf_data_rd.l3_hit_m.snoop_none cache OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80040490  00     ocr.all_pf_data_rd.l3_hit_s.any_snoop cache OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP  OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100490  00     ocr.all_pf_data_rd.l3_hit_s.hitm_other_core cache OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE  OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100490  00     ocr.all_pf_data_rd.l3_hit_s.hit_other_core_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD  OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100490  00     ocr.all_pf_data_rd.l3_hit_s.hit_other_core_no_fwd cache OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100490  00     ocr.all_pf_data_rd.l3_hit_s.no_snoop_needed cache OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED  OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100490  00     ocr.all_pf_data_rd.l3_hit_s.snoop_miss cache OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200100490  00     ocr.all_pf_data_rd.l3_hit_s.snoop_none cache OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80100490  00     ocr.all_pf_rfo.l3_hit.any_snoop cache OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0120  00     ocr.all_pf_rfo.l3_hit.hitm_other_core cache OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0120  00     ocr.all_pf_rfo.l3_hit.hit_other_core_fwd cache OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0120  00     ocr.all_pf_rfo.l3_hit.hit_other_core_no_fwd cache OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0120  00     ocr.all_pf_rfo.l3_hit.no_snoop_needed cache OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0120  00     ocr.all_pf_rfo.l3_hit.snoop_hit_with_fwd cache OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0120  00     ocr.all_pf_rfo.l3_hit.snoop_miss cache OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0120  00     ocr.all_pf_rfo.l3_hit.snoop_none cache OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0120  00     ocr.all_pf_rfo.l3_hit_e.any_snoop cache OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP  OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080120  00     ocr.all_pf_rfo.l3_hit_e.hitm_other_core cache OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE  OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080120  00     ocr.all_pf_rfo.l3_hit_e.hit_other_core_fwd cache OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD  OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080120  00     ocr.all_pf_rfo.l3_hit_e.hit_other_core_no_fwd cache OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080120  00     ocr.all_pf_rfo.l3_hit_e.no_snoop_needed cache OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED  OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080120  00     ocr.all_pf_rfo.l3_hit_e.snoop_miss cache OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200080120  00     ocr.all_pf_rfo.l3_hit_e.snoop_none cache OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80080120  00     ocr.all_pf_rfo.l3_hit_f.any_snoop cache OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP  OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200120  00     ocr.all_pf_rfo.l3_hit_f.hitm_other_core cache OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE  OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200120  00     ocr.all_pf_rfo.l3_hit_f.hit_other_core_fwd cache OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD  OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200120  00     ocr.all_pf_rfo.l3_hit_f.hit_other_core_no_fwd cache OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200120  00     ocr.all_pf_rfo.l3_hit_f.no_snoop_needed cache OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED  OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200120  00     ocr.all_pf_rfo.l3_hit_f.snoop_miss cache OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200200120  00     ocr.all_pf_rfo.l3_hit_f.snoop_none cache OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80200120  00     ocr.all_pf_rfo.l3_hit_m.any_snoop cache OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP  OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040120  00     ocr.all_pf_rfo.l3_hit_m.hitm_other_core cache OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE  OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040120  00     ocr.all_pf_rfo.l3_hit_m.hit_other_core_fwd cache OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD  OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040120  00     ocr.all_pf_rfo.l3_hit_m.hit_other_core_no_fwd cache OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040120  00     ocr.all_pf_rfo.l3_hit_m.no_snoop_needed cache OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED  OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040120  00     ocr.all_pf_rfo.l3_hit_m.snoop_miss cache OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200040120  00     ocr.all_pf_rfo.l3_hit_m.snoop_none cache OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80040120  00     ocr.all_pf_rfo.l3_hit_s.any_snoop cache OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP  OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100120  00     ocr.all_pf_rfo.l3_hit_s.hitm_other_core cache OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE  OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100120  00     ocr.all_pf_rfo.l3_hit_s.hit_other_core_fwd cache OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD  OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100120  00     ocr.all_pf_rfo.l3_hit_s.hit_other_core_no_fwd cache OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100120  00     ocr.all_pf_rfo.l3_hit_s.no_snoop_needed cache OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED  OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100120  00     ocr.all_pf_rfo.l3_hit_s.snoop_miss cache OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200100120  00     ocr.all_pf_rfo.l3_hit_s.snoop_none cache OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80100120  00     ocr.all_reads.l3_hit.any_snoop cache OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C07F7  00     ocr.all_reads.l3_hit.hitm_other_core cache OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C07F7  00     ocr.all_reads.l3_hit.hit_other_core_fwd cache OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C07F7  00     ocr.all_reads.l3_hit.hit_other_core_no_fwd cache OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C07F7  00     ocr.all_reads.l3_hit.no_snoop_needed cache OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C07F7  00     ocr.all_reads.l3_hit.snoop_hit_with_fwd cache OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C07F7  00     ocr.all_reads.l3_hit.snoop_miss cache OCR.ALL_READS.L3_HIT.SNOOP_MISS OCR.ALL_READS.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C07F7  00     ocr.all_reads.l3_hit.snoop_none cache OCR.ALL_READS.L3_HIT.SNOOP_NONE OCR.ALL_READS.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C07F7  00     ocr.all_reads.l3_hit_e.any_snoop cache OCR.ALL_READS.L3_HIT_E.ANY_SNOOP  OCR.ALL_READS.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F800807F7  00     ocr.all_reads.l3_hit_e.hitm_other_core cache OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE  OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10000807F7  00     ocr.all_reads.l3_hit_e.hit_other_core_fwd cache OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD  OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8000807F7  00     ocr.all_reads.l3_hit_e.hit_other_core_no_fwd cache OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD  OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4000807F7  00     ocr.all_reads.l3_hit_e.no_snoop_needed cache OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED  OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1000807F7  00     ocr.all_reads.l3_hit_e.snoop_miss cache OCR.ALL_READS.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2000807F7  00     ocr.all_reads.l3_hit_e.snoop_none cache OCR.ALL_READS.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x800807F7  00     ocr.all_reads.l3_hit_f.any_snoop cache OCR.ALL_READS.L3_HIT_F.ANY_SNOOP  OCR.ALL_READS.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F802007F7  00     ocr.all_reads.l3_hit_f.hitm_other_core cache OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE  OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10002007F7  00     ocr.all_reads.l3_hit_f.hit_other_core_fwd cache OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD  OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8002007F7  00     ocr.all_reads.l3_hit_f.hit_other_core_no_fwd cache OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD  OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4002007F7  00     ocr.all_reads.l3_hit_f.no_snoop_needed cache OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED  OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1002007F7  00     ocr.all_reads.l3_hit_f.snoop_miss cache OCR.ALL_READS.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2002007F7  00     ocr.all_reads.l3_hit_f.snoop_none cache OCR.ALL_READS.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x802007F7  00     ocr.all_reads.l3_hit_m.any_snoop cache OCR.ALL_READS.L3_HIT_M.ANY_SNOOP  OCR.ALL_READS.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F800407F7  00     ocr.all_reads.l3_hit_m.hitm_other_core cache OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE  OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10000407F7  00     ocr.all_reads.l3_hit_m.hit_other_core_fwd cache OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD  OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8000407F7  00     ocr.all_reads.l3_hit_m.hit_other_core_no_fwd cache OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD  OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4000407F7  00     ocr.all_reads.l3_hit_m.no_snoop_needed cache OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED  OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1000407F7  00     ocr.all_reads.l3_hit_m.snoop_miss cache OCR.ALL_READS.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2000407F7  00     ocr.all_reads.l3_hit_m.snoop_none cache OCR.ALL_READS.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x800407F7  00     ocr.all_reads.l3_hit_s.any_snoop cache OCR.ALL_READS.L3_HIT_S.ANY_SNOOP  OCR.ALL_READS.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F801007F7  00     ocr.all_reads.l3_hit_s.hitm_other_core cache OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE  OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10001007F7  00     ocr.all_reads.l3_hit_s.hit_other_core_fwd cache OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD  OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8001007F7  00     ocr.all_reads.l3_hit_s.hit_other_core_no_fwd cache OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD  OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4001007F7  00     ocr.all_reads.l3_hit_s.no_snoop_needed cache OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED  OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1001007F7  00     ocr.all_reads.l3_hit_s.snoop_miss cache OCR.ALL_READS.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2001007F7  00     ocr.all_reads.l3_hit_s.snoop_none cache OCR.ALL_READS.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x801007F7  00     ocr.all_rfo.l3_hit.any_snoop cache OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0122  00     ocr.all_rfo.l3_hit.hitm_other_core cache OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0122  00     ocr.all_rfo.l3_hit.hit_other_core_fwd cache OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0122  00     ocr.all_rfo.l3_hit.hit_other_core_no_fwd cache OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0122  00     ocr.all_rfo.l3_hit.no_snoop_needed cache OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0122  00     ocr.all_rfo.l3_hit.snoop_hit_with_fwd cache OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0122  00     ocr.all_rfo.l3_hit.snoop_miss cache OCR.ALL_RFO.L3_HIT.SNOOP_MISS OCR.ALL_RFO.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0122  00     ocr.all_rfo.l3_hit.snoop_none cache OCR.ALL_RFO.L3_HIT.SNOOP_NONE OCR.ALL_RFO.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0122  00     ocr.all_rfo.l3_hit_e.any_snoop cache OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP  OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080122  00     ocr.all_rfo.l3_hit_e.hitm_other_core cache OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE  OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080122  00     ocr.all_rfo.l3_hit_e.hit_other_core_fwd cache OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD  OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080122  00     ocr.all_rfo.l3_hit_e.hit_other_core_no_fwd cache OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD  OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080122  00     ocr.all_rfo.l3_hit_e.no_snoop_needed cache OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED  OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080122  00     ocr.all_rfo.l3_hit_e.snoop_miss cache OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200080122  00     ocr.all_rfo.l3_hit_e.snoop_none cache OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80080122  00     ocr.all_rfo.l3_hit_f.any_snoop cache OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP  OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200122  00     ocr.all_rfo.l3_hit_f.hitm_other_core cache OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE  OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200122  00     ocr.all_rfo.l3_hit_f.hit_other_core_fwd cache OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD  OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200122  00     ocr.all_rfo.l3_hit_f.hit_other_core_no_fwd cache OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD  OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200122  00     ocr.all_rfo.l3_hit_f.no_snoop_needed cache OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED  OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200122  00     ocr.all_rfo.l3_hit_f.snoop_miss cache OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200200122  00     ocr.all_rfo.l3_hit_f.snoop_none cache OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80200122  00     ocr.all_rfo.l3_hit_m.any_snoop cache OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP  OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040122  00     ocr.all_rfo.l3_hit_m.hitm_other_core cache OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE  OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040122  00     ocr.all_rfo.l3_hit_m.hit_other_core_fwd cache OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD  OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040122  00     ocr.all_rfo.l3_hit_m.hit_other_core_no_fwd cache OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD  OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040122  00     ocr.all_rfo.l3_hit_m.no_snoop_needed cache OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED  OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040122  00     ocr.all_rfo.l3_hit_m.snoop_miss cache OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200040122  00     ocr.all_rfo.l3_hit_m.snoop_none cache OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80040122  00     ocr.all_rfo.l3_hit_s.any_snoop cache OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP  OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100122  00     ocr.all_rfo.l3_hit_s.hitm_other_core cache OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE  OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100122  00     ocr.all_rfo.l3_hit_s.hit_other_core_fwd cache OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD  OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100122  00     ocr.all_rfo.l3_hit_s.hit_other_core_no_fwd cache OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD  OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100122  00     ocr.all_rfo.l3_hit_s.no_snoop_needed cache OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED  OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100122  00     ocr.all_rfo.l3_hit_s.snoop_miss cache OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200100122  00     ocr.all_rfo.l3_hit_s.snoop_none cache OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80100122  00     ocr.demand_code_rd.any_response cache Counts all demand code reads have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10004  00     ocr.demand_code_rd.l3_hit.any_snoop cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0004  00     ocr.demand_code_rd.l3_hit.hitm_other_core cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0004  00     ocr.demand_code_rd.l3_hit.hit_other_core_fwd cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0004  00     ocr.demand_code_rd.l3_hit.hit_other_core_no_fwd cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0004  00     ocr.demand_code_rd.l3_hit.no_snoop_needed cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0004  00     ocr.demand_code_rd.l3_hit.snoop_hit_with_fwd cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0004  00     ocr.demand_code_rd.l3_hit.snoop_miss cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0004  00     ocr.demand_code_rd.l3_hit.snoop_none cache Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0004  00     ocr.demand_code_rd.l3_hit_e.any_snoop cache Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080004  00     ocr.demand_code_rd.l3_hit_e.hitm_other_core cache Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080004  00     ocr.demand_code_rd.l3_hit_e.hit_other_core_fwd cache Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080004  00     ocr.demand_code_rd.l3_hit_e.hit_other_core_no_fwd cache Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080004  00     ocr.demand_code_rd.l3_hit_e.no_snoop_needed cache Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080004  00     ocr.demand_code_rd.l3_hit_e.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200080004  00     ocr.demand_code_rd.l3_hit_e.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80080004  00     ocr.demand_code_rd.l3_hit_f.any_snoop cache Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200004  00     ocr.demand_code_rd.l3_hit_f.hitm_other_core cache Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200004  00     ocr.demand_code_rd.l3_hit_f.hit_other_core_fwd cache Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200004  00     ocr.demand_code_rd.l3_hit_f.hit_other_core_no_fwd cache Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200004  00     ocr.demand_code_rd.l3_hit_f.no_snoop_needed cache Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200004  00     ocr.demand_code_rd.l3_hit_f.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200200004  00     ocr.demand_code_rd.l3_hit_f.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80200004  00     ocr.demand_code_rd.l3_hit_m.any_snoop cache Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040004  00     ocr.demand_code_rd.l3_hit_m.hitm_other_core cache Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040004  00     ocr.demand_code_rd.l3_hit_m.hit_other_core_fwd cache Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040004  00     ocr.demand_code_rd.l3_hit_m.hit_other_core_no_fwd cache Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040004  00     ocr.demand_code_rd.l3_hit_m.no_snoop_needed cache Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040004  00     ocr.demand_code_rd.l3_hit_m.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200040004  00     ocr.demand_code_rd.l3_hit_m.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80040004  00     ocr.demand_code_rd.l3_hit_s.any_snoop cache Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100004  00     ocr.demand_code_rd.l3_hit_s.hitm_other_core cache Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100004  00     ocr.demand_code_rd.l3_hit_s.hit_other_core_fwd cache Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100004  00     ocr.demand_code_rd.l3_hit_s.hit_other_core_no_fwd cache Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100004  00     ocr.demand_code_rd.l3_hit_s.no_snoop_needed cache Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100004  00     ocr.demand_code_rd.l3_hit_s.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200100004  00     ocr.demand_code_rd.l3_hit_s.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80100004  00     ocr.demand_code_rd.pmm_hit_local_pmm.any_snoop cache Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400004  00     ocr.demand_code_rd.pmm_hit_local_pmm.snoop_none cache Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400004  00     ocr.demand_code_rd.pmm_hit_local_pmm.snoop_not_needed cache Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400004  00     ocr.demand_code_rd.supplier_none.any_snoop cache Counts all demand code reads  OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020004  00     ocr.demand_code_rd.supplier_none.hitm_other_core cache Counts all demand code reads  OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020004  00     ocr.demand_code_rd.supplier_none.hit_other_core_fwd cache Counts all demand code reads  OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020004  00     ocr.demand_code_rd.supplier_none.hit_other_core_no_fwd cache Counts all demand code reads  OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020004  00     ocr.demand_code_rd.supplier_none.no_snoop_needed cache Counts all demand code reads  OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020004  00     ocr.demand_code_rd.supplier_none.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200020004  00     ocr.demand_code_rd.supplier_none.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80020004  00     ocr.demand_data_rd.any_response cache Counts demand data reads have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10001  00     ocr.demand_data_rd.l3_hit.any_snoop cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0001  00     ocr.demand_data_rd.l3_hit.hitm_other_core cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0001  00     ocr.demand_data_rd.l3_hit.hit_other_core_fwd cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0001  00     ocr.demand_data_rd.l3_hit.hit_other_core_no_fwd cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0001  00     ocr.demand_data_rd.l3_hit.no_snoop_needed cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0001  00     ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0001  00     ocr.demand_data_rd.l3_hit.snoop_miss cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0001  00     ocr.demand_data_rd.l3_hit.snoop_none cache Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0001  00     ocr.demand_data_rd.l3_hit_e.any_snoop cache Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080001  00     ocr.demand_data_rd.l3_hit_e.hitm_other_core cache Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080001  00     ocr.demand_data_rd.l3_hit_e.hit_other_core_fwd cache Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080001  00     ocr.demand_data_rd.l3_hit_e.hit_other_core_no_fwd cache Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080001  00     ocr.demand_data_rd.l3_hit_e.no_snoop_needed cache Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080001  00     ocr.demand_data_rd.l3_hit_e.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200080001  00     ocr.demand_data_rd.l3_hit_e.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80080001  00     ocr.demand_data_rd.l3_hit_f.any_snoop cache Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200001  00     ocr.demand_data_rd.l3_hit_f.hitm_other_core cache Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200001  00     ocr.demand_data_rd.l3_hit_f.hit_other_core_fwd cache Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200001  00     ocr.demand_data_rd.l3_hit_f.hit_other_core_no_fwd cache Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200001  00     ocr.demand_data_rd.l3_hit_f.no_snoop_needed cache Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200001  00     ocr.demand_data_rd.l3_hit_f.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200200001  00     ocr.demand_data_rd.l3_hit_f.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80200001  00     ocr.demand_data_rd.l3_hit_m.any_snoop cache Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040001  00     ocr.demand_data_rd.l3_hit_m.hitm_other_core cache Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040001  00     ocr.demand_data_rd.l3_hit_m.hit_other_core_fwd cache Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040001  00     ocr.demand_data_rd.l3_hit_m.hit_other_core_no_fwd cache Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040001  00     ocr.demand_data_rd.l3_hit_m.no_snoop_needed cache Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040001  00     ocr.demand_data_rd.l3_hit_m.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200040001  00     ocr.demand_data_rd.l3_hit_m.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80040001  00     ocr.demand_data_rd.l3_hit_s.any_snoop cache Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100001  00     ocr.demand_data_rd.l3_hit_s.hitm_other_core cache Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100001  00     ocr.demand_data_rd.l3_hit_s.hit_other_core_fwd cache Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100001  00     ocr.demand_data_rd.l3_hit_s.hit_other_core_no_fwd cache Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100001  00     ocr.demand_data_rd.l3_hit_s.no_snoop_needed cache Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100001  00     ocr.demand_data_rd.l3_hit_s.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200100001  00     ocr.demand_data_rd.l3_hit_s.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80100001  00     ocr.demand_data_rd.pmm_hit_local_pmm.any_snoop cache Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400001  00     ocr.demand_data_rd.pmm_hit_local_pmm.snoop_none cache Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400001  00     ocr.demand_data_rd.pmm_hit_local_pmm.snoop_not_needed cache Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400001  00     ocr.demand_data_rd.supplier_none.any_snoop cache Counts demand data reads  OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020001  00     ocr.demand_data_rd.supplier_none.hitm_other_core cache Counts demand data reads  OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020001  00     ocr.demand_data_rd.supplier_none.hit_other_core_fwd cache Counts demand data reads  OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020001  00     ocr.demand_data_rd.supplier_none.hit_other_core_no_fwd cache Counts demand data reads  OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020001  00     ocr.demand_data_rd.supplier_none.no_snoop_needed cache Counts demand data reads  OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020001  00     ocr.demand_data_rd.supplier_none.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200020001  00     ocr.demand_data_rd.supplier_none.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80020001  00     ocr.demand_rfo.any_response cache Counts all demand data writes (RFOs) have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10002  00     ocr.demand_rfo.l3_hit.any_snoop cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0002  00     ocr.demand_rfo.l3_hit.hitm_other_core cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0002  00     ocr.demand_rfo.l3_hit.hit_other_core_fwd cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0002  00     ocr.demand_rfo.l3_hit.hit_other_core_no_fwd cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0002  00     ocr.demand_rfo.l3_hit.no_snoop_needed cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0002  00     ocr.demand_rfo.l3_hit.snoop_hit_with_fwd cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0002  00     ocr.demand_rfo.l3_hit.snoop_miss cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0002  00     ocr.demand_rfo.l3_hit.snoop_none cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0002  00     ocr.demand_rfo.l3_hit_e.any_snoop cache Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080002  00     ocr.demand_rfo.l3_hit_e.hitm_other_core cache Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080002  00     ocr.demand_rfo.l3_hit_e.hit_other_core_fwd cache Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080002  00     ocr.demand_rfo.l3_hit_e.hit_other_core_no_fwd cache Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080002  00     ocr.demand_rfo.l3_hit_e.no_snoop_needed cache Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080002  00     ocr.demand_rfo.l3_hit_e.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x200080002  00     ocr.demand_rfo.l3_hit_e.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x80080002  00     ocr.demand_rfo.l3_hit_f.any_snoop cache Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200002  00     ocr.demand_rfo.l3_hit_f.hitm_other_core cache Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200002  00     ocr.demand_rfo.l3_hit_f.hit_other_core_fwd cache Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200002  00     ocr.demand_rfo.l3_hit_f.hit_other_core_no_fwd cache Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200002  00     ocr.demand_rfo.l3_hit_f.no_snoop_needed cache Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200002  00     ocr.demand_rfo.l3_hit_f.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x200200002  00     ocr.demand_rfo.l3_hit_f.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x80200002  00     ocr.demand_rfo.l3_hit_m.any_snoop cache Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040002  00     ocr.demand_rfo.l3_hit_m.hitm_other_core cache Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040002  00     ocr.demand_rfo.l3_hit_m.hit_other_core_fwd cache Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040002  00     ocr.demand_rfo.l3_hit_m.hit_other_core_no_fwd cache Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040002  00     ocr.demand_rfo.l3_hit_m.no_snoop_needed cache Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040002  00     ocr.demand_rfo.l3_hit_m.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x200040002  00     ocr.demand_rfo.l3_hit_m.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x80040002  00     ocr.demand_rfo.l3_hit_s.any_snoop cache Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100002  00     ocr.demand_rfo.l3_hit_s.hitm_other_core cache Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100002  00     ocr.demand_rfo.l3_hit_s.hit_other_core_fwd cache Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100002  00     ocr.demand_rfo.l3_hit_s.hit_other_core_no_fwd cache Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100002  00     ocr.demand_rfo.l3_hit_s.no_snoop_needed cache Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100002  00     ocr.demand_rfo.l3_hit_s.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x200100002  00     ocr.demand_rfo.l3_hit_s.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x80100002  00     ocr.demand_rfo.pmm_hit_local_pmm.any_snoop cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400002  00     ocr.demand_rfo.pmm_hit_local_pmm.snoop_none cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400002  00     ocr.demand_rfo.pmm_hit_local_pmm.snoop_not_needed cache Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400002  00     ocr.demand_rfo.supplier_none.any_snoop cache Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020002  00     ocr.demand_rfo.supplier_none.hitm_other_core cache Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020002  00     ocr.demand_rfo.supplier_none.hit_other_core_fwd cache Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020002  00     ocr.demand_rfo.supplier_none.hit_other_core_no_fwd cache Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020002  00     ocr.demand_rfo.supplier_none.no_snoop_needed cache Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020002  00     ocr.demand_rfo.supplier_none.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x200020002  00     ocr.demand_rfo.supplier_none.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x80020002  00     ocr.other.l3_hit.any_snoop cache Counts any other requests OCR.OTHER.L3_HIT.ANY_SNOOP OCR.OTHER.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C8000  00     ocr.other.l3_hit.hitm_other_core cache Counts any other requests OCR.OTHER.L3_HIT.HITM_OTHER_CORE OCR.OTHER.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C8000  00     ocr.other.l3_hit.hit_other_core_fwd cache Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C8000  00     ocr.other.l3_hit.hit_other_core_no_fwd cache Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C8000  00     ocr.other.l3_hit.no_snoop_needed cache Counts any other requests OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C8000  00     ocr.other.l3_hit.snoop_hit_with_fwd cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C8000  00     ocr.other.l3_hit.snoop_miss cache Counts any other requests OCR.OTHER.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C8000  00     ocr.other.l3_hit.snoop_none cache Counts any other requests OCR.OTHER.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C8000  00     ocr.other.l3_hit_e.any_snoop cache Counts any other requests  OCR.OTHER.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80088000  00     ocr.other.l3_hit_e.hitm_other_core cache Counts any other requests  OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000088000  00     ocr.other.l3_hit_e.hit_other_core_fwd cache Counts any other requests  OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800088000  00     ocr.other.l3_hit_e.hit_other_core_no_fwd cache Counts any other requests  OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400088000  00     ocr.other.l3_hit_e.no_snoop_needed cache Counts any other requests  OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100088000  00     ocr.other.l3_hit_e.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x200088000  00     ocr.other.l3_hit_e.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x80088000  00     ocr.other.l3_hit_f.any_snoop cache Counts any other requests  OCR.OTHER.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80208000  00     ocr.other.l3_hit_f.hitm_other_core cache Counts any other requests  OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000208000  00     ocr.other.l3_hit_f.hit_other_core_fwd cache Counts any other requests  OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800208000  00     ocr.other.l3_hit_f.hit_other_core_no_fwd cache Counts any other requests  OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400208000  00     ocr.other.l3_hit_f.no_snoop_needed cache Counts any other requests  OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100208000  00     ocr.other.l3_hit_f.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x200208000  00     ocr.other.l3_hit_f.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x80208000  00     ocr.other.l3_hit_m.any_snoop cache Counts any other requests  OCR.OTHER.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80048000  00     ocr.other.l3_hit_m.hitm_other_core cache Counts any other requests  OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000048000  00     ocr.other.l3_hit_m.hit_other_core_fwd cache Counts any other requests  OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800048000  00     ocr.other.l3_hit_m.hit_other_core_no_fwd cache Counts any other requests  OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400048000  00     ocr.other.l3_hit_m.no_snoop_needed cache Counts any other requests  OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100048000  00     ocr.other.l3_hit_m.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x200048000  00     ocr.other.l3_hit_m.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x80048000  00     ocr.other.l3_hit_s.any_snoop cache Counts any other requests  OCR.OTHER.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80108000  00     ocr.other.l3_hit_s.hitm_other_core cache Counts any other requests  OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000108000  00     ocr.other.l3_hit_s.hit_other_core_fwd cache Counts any other requests  OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800108000  00     ocr.other.l3_hit_s.hit_other_core_no_fwd cache Counts any other requests  OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400108000  00     ocr.other.l3_hit_s.no_snoop_needed cache Counts any other requests  OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100108000  00     ocr.other.l3_hit_s.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x200108000  00     ocr.other.l3_hit_s.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x80108000  00     ocr.pf_l1d_and_sw.l3_hit.any_snoop cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0400  00     ocr.pf_l1d_and_sw.l3_hit.hitm_other_core cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0400  00     ocr.pf_l1d_and_sw.l3_hit.hit_other_core_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0400  00     ocr.pf_l1d_and_sw.l3_hit.hit_other_core_no_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0400  00     ocr.pf_l1d_and_sw.l3_hit.no_snoop_needed cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0400  00     ocr.pf_l1d_and_sw.l3_hit.snoop_hit_with_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0400  00     ocr.pf_l1d_and_sw.l3_hit.snoop_miss cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0400  00     ocr.pf_l1d_and_sw.l3_hit.snoop_none cache Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0400  00     ocr.pf_l1d_and_sw.l3_hit_e.any_snoop cache Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080400  00     ocr.pf_l1d_and_sw.l3_hit_e.hitm_other_core cache Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080400  00     ocr.pf_l1d_and_sw.l3_hit_e.hit_other_core_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080400  00     ocr.pf_l1d_and_sw.l3_hit_e.hit_other_core_no_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080400  00     ocr.pf_l1d_and_sw.l3_hit_e.no_snoop_needed cache Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080400  00     ocr.pf_l1d_and_sw.l3_hit_e.snoop_miss cache Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=1,offcore_rsp=0x200080400  00     ocr.pf_l1d_and_sw.l3_hit_e.snoop_none cache Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=1,offcore_rsp=0x80080400  00     ocr.pf_l1d_and_sw.l3_hit_f.any_snoop cache Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200400  00     ocr.pf_l1d_and_sw.l3_hit_f.hitm_other_core cache Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200400  00     ocr.pf_l1d_and_sw.l3_hit_f.hit_other_core_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200400  00     ocr.pf_l1d_and_sw.l3_hit_f.hit_other_core_no_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200400  00     ocr.pf_l1d_and_sw.l3_hit_f.no_snoop_needed cache Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200400  00     ocr.pf_l1d_and_sw.l3_hit_f.snoop_miss cache Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=1,offcore_rsp=0x200200400  00     ocr.pf_l1d_and_sw.l3_hit_f.snoop_none cache Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=1,offcore_rsp=0x80200400  00     ocr.pf_l1d_and_sw.l3_hit_m.any_snoop cache Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040400  00     ocr.pf_l1d_and_sw.l3_hit_m.hitm_other_core cache Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040400  00     ocr.pf_l1d_and_sw.l3_hit_m.hit_other_core_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040400  00     ocr.pf_l1d_and_sw.l3_hit_m.hit_other_core_no_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040400  00     ocr.pf_l1d_and_sw.l3_hit_m.no_snoop_needed cache Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040400  00     ocr.pf_l1d_and_sw.l3_hit_m.snoop_miss cache Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=1,offcore_rsp=0x200040400  00     ocr.pf_l1d_and_sw.l3_hit_m.snoop_none cache Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=1,offcore_rsp=0x80040400  00     ocr.pf_l1d_and_sw.l3_hit_s.any_snoop cache Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100400  00     ocr.pf_l1d_and_sw.l3_hit_s.hitm_other_core cache Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100400  00     ocr.pf_l1d_and_sw.l3_hit_s.hit_other_core_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100400  00     ocr.pf_l1d_and_sw.l3_hit_s.hit_other_core_no_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100400  00     ocr.pf_l1d_and_sw.l3_hit_s.no_snoop_needed cache Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100400  00     ocr.pf_l1d_and_sw.l3_hit_s.snoop_miss cache Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=1,offcore_rsp=0x200100400  00     ocr.pf_l1d_and_sw.l3_hit_s.snoop_none cache Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=1,offcore_rsp=0x80100400  00     ocr.pf_l2_data_rd.l3_hit.any_snoop cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0010  00     ocr.pf_l2_data_rd.l3_hit.hitm_other_core cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0010  00     ocr.pf_l2_data_rd.l3_hit.hit_other_core_fwd cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0010  00     ocr.pf_l2_data_rd.l3_hit.hit_other_core_no_fwd cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0010  00     ocr.pf_l2_data_rd.l3_hit.no_snoop_needed cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0010  00     ocr.pf_l2_data_rd.l3_hit.snoop_hit_with_fwd cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0010  00     ocr.pf_l2_data_rd.l3_hit.snoop_miss cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0010  00     ocr.pf_l2_data_rd.l3_hit.snoop_none cache Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0010  00     ocr.pf_l2_data_rd.l3_hit_e.any_snoop cache Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080010  00     ocr.pf_l2_data_rd.l3_hit_e.hitm_other_core cache Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080010  00     ocr.pf_l2_data_rd.l3_hit_e.hit_other_core_fwd cache Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080010  00     ocr.pf_l2_data_rd.l3_hit_e.hit_other_core_no_fwd cache Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080010  00     ocr.pf_l2_data_rd.l3_hit_e.no_snoop_needed cache Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080010  00     ocr.pf_l2_data_rd.l3_hit_e.snoop_miss cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200080010  00     ocr.pf_l2_data_rd.l3_hit_e.snoop_none cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80080010  00     ocr.pf_l2_data_rd.l3_hit_f.any_snoop cache Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200010  00     ocr.pf_l2_data_rd.l3_hit_f.hitm_other_core cache Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200010  00     ocr.pf_l2_data_rd.l3_hit_f.hit_other_core_fwd cache Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200010  00     ocr.pf_l2_data_rd.l3_hit_f.hit_other_core_no_fwd cache Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200010  00     ocr.pf_l2_data_rd.l3_hit_f.no_snoop_needed cache Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200010  00     ocr.pf_l2_data_rd.l3_hit_f.snoop_miss cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200200010  00     ocr.pf_l2_data_rd.l3_hit_f.snoop_none cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80200010  00     ocr.pf_l2_data_rd.l3_hit_m.any_snoop cache Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040010  00     ocr.pf_l2_data_rd.l3_hit_m.hitm_other_core cache Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040010  00     ocr.pf_l2_data_rd.l3_hit_m.hit_other_core_fwd cache Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040010  00     ocr.pf_l2_data_rd.l3_hit_m.hit_other_core_no_fwd cache Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040010  00     ocr.pf_l2_data_rd.l3_hit_m.no_snoop_needed cache Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040010  00     ocr.pf_l2_data_rd.l3_hit_m.snoop_miss cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200040010  00     ocr.pf_l2_data_rd.l3_hit_m.snoop_none cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80040010  00     ocr.pf_l2_data_rd.l3_hit_s.any_snoop cache Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100010  00     ocr.pf_l2_data_rd.l3_hit_s.hitm_other_core cache Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100010  00     ocr.pf_l2_data_rd.l3_hit_s.hit_other_core_fwd cache Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100010  00     ocr.pf_l2_data_rd.l3_hit_s.hit_other_core_no_fwd cache Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100010  00     ocr.pf_l2_data_rd.l3_hit_s.no_snoop_needed cache Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100010  00     ocr.pf_l2_data_rd.l3_hit_s.snoop_miss cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200100010  00     ocr.pf_l2_data_rd.l3_hit_s.snoop_none cache Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80100010  00     ocr.pf_l2_rfo.l3_hit.any_snoop cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0020  00     ocr.pf_l2_rfo.l3_hit.hitm_other_core cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0020  00     ocr.pf_l2_rfo.l3_hit.hit_other_core_fwd cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0020  00     ocr.pf_l2_rfo.l3_hit.hit_other_core_no_fwd cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0020  00     ocr.pf_l2_rfo.l3_hit.no_snoop_needed cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0020  00     ocr.pf_l2_rfo.l3_hit.snoop_hit_with_fwd cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0020  00     ocr.pf_l2_rfo.l3_hit.snoop_miss cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0020  00     ocr.pf_l2_rfo.l3_hit.snoop_none cache Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0020  00     ocr.pf_l2_rfo.l3_hit_e.any_snoop cache Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080020  00     ocr.pf_l2_rfo.l3_hit_e.hitm_other_core cache Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080020  00     ocr.pf_l2_rfo.l3_hit_e.hit_other_core_fwd cache Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080020  00     ocr.pf_l2_rfo.l3_hit_e.hit_other_core_no_fwd cache Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080020  00     ocr.pf_l2_rfo.l3_hit_e.no_snoop_needed cache Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080020  00     ocr.pf_l2_rfo.l3_hit_e.snoop_miss cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x200080020  00     ocr.pf_l2_rfo.l3_hit_e.snoop_none cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x80080020  00     ocr.pf_l2_rfo.l3_hit_f.any_snoop cache Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200020  00     ocr.pf_l2_rfo.l3_hit_f.hitm_other_core cache Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200020  00     ocr.pf_l2_rfo.l3_hit_f.hit_other_core_fwd cache Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200020  00     ocr.pf_l2_rfo.l3_hit_f.hit_other_core_no_fwd cache Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200020  00     ocr.pf_l2_rfo.l3_hit_f.no_snoop_needed cache Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200020  00     ocr.pf_l2_rfo.l3_hit_f.snoop_miss cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x200200020  00     ocr.pf_l2_rfo.l3_hit_f.snoop_none cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x80200020  00     ocr.pf_l2_rfo.l3_hit_m.any_snoop cache Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040020  00     ocr.pf_l2_rfo.l3_hit_m.hitm_other_core cache Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040020  00     ocr.pf_l2_rfo.l3_hit_m.hit_other_core_fwd cache Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040020  00     ocr.pf_l2_rfo.l3_hit_m.hit_other_core_no_fwd cache Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040020  00     ocr.pf_l2_rfo.l3_hit_m.no_snoop_needed cache Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040020  00     ocr.pf_l2_rfo.l3_hit_m.snoop_miss cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x200040020  00     ocr.pf_l2_rfo.l3_hit_m.snoop_none cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x80040020  00     ocr.pf_l2_rfo.l3_hit_s.any_snoop cache Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100020  00     ocr.pf_l2_rfo.l3_hit_s.hitm_other_core cache Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100020  00     ocr.pf_l2_rfo.l3_hit_s.hit_other_core_fwd cache Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100020  00     ocr.pf_l2_rfo.l3_hit_s.hit_other_core_no_fwd cache Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100020  00     ocr.pf_l2_rfo.l3_hit_s.no_snoop_needed cache Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100020  00     ocr.pf_l2_rfo.l3_hit_s.snoop_miss cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x200100020  00     ocr.pf_l2_rfo.l3_hit_s.snoop_none cache Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x80100020  00     ocr.pf_l3_data_rd.l3_hit.any_snoop cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0080  00     ocr.pf_l3_data_rd.l3_hit.hitm_other_core cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0080  00     ocr.pf_l3_data_rd.l3_hit.hit_other_core_fwd cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0080  00     ocr.pf_l3_data_rd.l3_hit.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0080  00     ocr.pf_l3_data_rd.l3_hit.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0080  00     ocr.pf_l3_data_rd.l3_hit.snoop_hit_with_fwd cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0080  00     ocr.pf_l3_data_rd.l3_hit.snoop_miss cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0080  00     ocr.pf_l3_data_rd.l3_hit.snoop_none cache Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0080  00     ocr.pf_l3_data_rd.l3_hit_e.any_snoop cache Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080080  00     ocr.pf_l3_data_rd.l3_hit_e.hitm_other_core cache Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080080  00     ocr.pf_l3_data_rd.l3_hit_e.hit_other_core_fwd cache Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080080  00     ocr.pf_l3_data_rd.l3_hit_e.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080080  00     ocr.pf_l3_data_rd.l3_hit_e.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080080  00     ocr.pf_l3_data_rd.l3_hit_e.snoop_miss cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200080080  00     ocr.pf_l3_data_rd.l3_hit_e.snoop_none cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80080080  00     ocr.pf_l3_data_rd.l3_hit_f.any_snoop cache Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200080  00     ocr.pf_l3_data_rd.l3_hit_f.hitm_other_core cache Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200080  00     ocr.pf_l3_data_rd.l3_hit_f.hit_other_core_fwd cache Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200080  00     ocr.pf_l3_data_rd.l3_hit_f.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200080  00     ocr.pf_l3_data_rd.l3_hit_f.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200080  00     ocr.pf_l3_data_rd.l3_hit_f.snoop_miss cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200200080  00     ocr.pf_l3_data_rd.l3_hit_f.snoop_none cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80200080  00     ocr.pf_l3_data_rd.l3_hit_m.any_snoop cache Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040080  00     ocr.pf_l3_data_rd.l3_hit_m.hitm_other_core cache Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040080  00     ocr.pf_l3_data_rd.l3_hit_m.hit_other_core_fwd cache Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040080  00     ocr.pf_l3_data_rd.l3_hit_m.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040080  00     ocr.pf_l3_data_rd.l3_hit_m.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040080  00     ocr.pf_l3_data_rd.l3_hit_m.snoop_miss cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200040080  00     ocr.pf_l3_data_rd.l3_hit_m.snoop_none cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80040080  00     ocr.pf_l3_data_rd.l3_hit_s.any_snoop cache Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100080  00     ocr.pf_l3_data_rd.l3_hit_s.hitm_other_core cache Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100080  00     ocr.pf_l3_data_rd.l3_hit_s.hit_other_core_fwd cache Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100080  00     ocr.pf_l3_data_rd.l3_hit_s.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100080  00     ocr.pf_l3_data_rd.l3_hit_s.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100080  00     ocr.pf_l3_data_rd.l3_hit_s.snoop_miss cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200100080  00     ocr.pf_l3_data_rd.l3_hit_s.snoop_none cache Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80100080  00     ocr.pf_l3_rfo.l3_hit.any_snoop cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0100  00     ocr.pf_l3_rfo.l3_hit.hitm_other_core cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0100  00     ocr.pf_l3_rfo.l3_hit.hit_other_core_fwd cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0100  00     ocr.pf_l3_rfo.l3_hit.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0100  00     ocr.pf_l3_rfo.l3_hit.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0100  00     ocr.pf_l3_rfo.l3_hit.snoop_hit_with_fwd cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0100  00     ocr.pf_l3_rfo.l3_hit.snoop_miss cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0100  00     ocr.pf_l3_rfo.l3_hit.snoop_none cache Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0100  00     ocr.pf_l3_rfo.l3_hit_e.any_snoop cache Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080100  00     ocr.pf_l3_rfo.l3_hit_e.hitm_other_core cache Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080100  00     ocr.pf_l3_rfo.l3_hit_e.hit_other_core_fwd cache Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080100  00     ocr.pf_l3_rfo.l3_hit_e.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080100  00     ocr.pf_l3_rfo.l3_hit_e.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080100  00     ocr.pf_l3_rfo.l3_hit_e.snoop_miss cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x200080100  00     ocr.pf_l3_rfo.l3_hit_e.snoop_none cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x80080100  00     ocr.pf_l3_rfo.l3_hit_f.any_snoop cache Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200100  00     ocr.pf_l3_rfo.l3_hit_f.hitm_other_core cache Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200100  00     ocr.pf_l3_rfo.l3_hit_f.hit_other_core_fwd cache Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200100  00     ocr.pf_l3_rfo.l3_hit_f.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200100  00     ocr.pf_l3_rfo.l3_hit_f.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200100  00     ocr.pf_l3_rfo.l3_hit_f.snoop_miss cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x200200100  00     ocr.pf_l3_rfo.l3_hit_f.snoop_none cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x80200100  00     ocr.pf_l3_rfo.l3_hit_m.any_snoop cache Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040100  00     ocr.pf_l3_rfo.l3_hit_m.hitm_other_core cache Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040100  00     ocr.pf_l3_rfo.l3_hit_m.hit_other_core_fwd cache Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040100  00     ocr.pf_l3_rfo.l3_hit_m.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040100  00     ocr.pf_l3_rfo.l3_hit_m.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040100  00     ocr.pf_l3_rfo.l3_hit_m.snoop_miss cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x200040100  00     ocr.pf_l3_rfo.l3_hit_m.snoop_none cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x80040100  00     ocr.pf_l3_rfo.l3_hit_s.any_snoop cache Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100100  00     ocr.pf_l3_rfo.l3_hit_s.hitm_other_core cache Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100100  00     ocr.pf_l3_rfo.l3_hit_s.hit_other_core_fwd cache Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100100  00     ocr.pf_l3_rfo.l3_hit_s.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100100  00     ocr.pf_l3_rfo.l3_hit_s.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100100  00     ocr.pf_l3_rfo.l3_hit_s.snoop_miss cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x200100100  00     ocr.pf_l3_rfo.l3_hit_s.snoop_none cache Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x80100100  00     offcore_requests.all_data_rd cache Demand and prefetch data reads event=0xb0,period=100003,umask=8  00    Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type offcore_requests.all_requests cache Any memory transaction that reached the SQ event=0xb0,period=100003,umask=0x80  00    Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc. offcore_requests.demand_code_rd cache Cacheable and non-cacheable code read requests event=0xb0,period=100003,umask=2  00    Counts both cacheable and non-cacheable code read requests offcore_requests.demand_data_rd cache Demand Data Read requests sent to uncore event=0xb0,period=100003,umask=1  00    Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore offcore_requests.demand_rfo cache Demand RFO requests including regular RFOs, locks, ItoM event=0xb0,period=100003,umask=4  00    Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM offcore_requests_buffer.sq_full cache Offcore requests buffer cannot take more entries for this thread core event=0xb2,period=2000003,umask=1  00    Counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.Note: Writeback pending FIFO has six entries offcore_requests_outstanding.all_data_rd cache Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore event=0x60,period=2000003,umask=8  00    Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.cycles_with_data_rd cache Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore event=0x60,cmask=1,period=2000003,umask=8  00    Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.cycles_with_demand_code_rd cache Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore event=0x60,cmask=1,period=2000003,umask=2  00    Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.cycles_with_demand_data_rd cache Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore event=0x60,cmask=1,period=2000003,umask=1  00    Counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation) offcore_requests_outstanding.cycles_with_demand_rfo cache Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore event=0x60,cmask=1,period=2000003,umask=4  00    Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.demand_code_rd cache Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle event=0x60,period=2000003,umask=2  00    Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.demand_data_rd cache Offcore outstanding Demand Data Read transactions in uncore queue event=0x60,period=2000003,umask=1  00    Counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.Note: A prefetch promoted to Demand is counted from the promotion point offcore_requests_outstanding.demand_data_rd_ge_6 cache Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue event=0x60,cmask=6,period=2000003,umask=1  00     offcore_requests_outstanding.demand_rfo cache Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle event=0x60,period=2000003,umask=4  00    Counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS offcore_response.all_data_rd.any_response cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10491  10     offcore_response.all_data_rd.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0491  10     offcore_response.all_data_rd.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0491  10     offcore_response.all_data_rd.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0491  10     offcore_response.all_data_rd.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0491  10     offcore_response.all_data_rd.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0491  10     offcore_response.all_data_rd.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0491  10     offcore_response.all_data_rd.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0491  10     offcore_response.all_data_rd.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0491  10     offcore_response.all_data_rd.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080491  10     offcore_response.all_data_rd.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080491  10     offcore_response.all_data_rd.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080491  10     offcore_response.all_data_rd.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080491  10     offcore_response.all_data_rd.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080491  10     offcore_response.all_data_rd.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200080491  10     offcore_response.all_data_rd.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80080491  10     offcore_response.all_data_rd.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200491  10     offcore_response.all_data_rd.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200491  10     offcore_response.all_data_rd.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200491  10     offcore_response.all_data_rd.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200491  10     offcore_response.all_data_rd.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200491  10     offcore_response.all_data_rd.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200200491  10     offcore_response.all_data_rd.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80200491  10     offcore_response.all_data_rd.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040491  10     offcore_response.all_data_rd.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040491  10     offcore_response.all_data_rd.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040491  10     offcore_response.all_data_rd.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040491  10     offcore_response.all_data_rd.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040491  10     offcore_response.all_data_rd.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200040491  10     offcore_response.all_data_rd.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80040491  10     offcore_response.all_data_rd.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100491  10     offcore_response.all_data_rd.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100491  10     offcore_response.all_data_rd.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100491  10     offcore_response.all_data_rd.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100491  10     offcore_response.all_data_rd.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100491  10     offcore_response.all_data_rd.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200100491  10     offcore_response.all_data_rd.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80100491  10     offcore_response.all_data_rd.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400491  10     offcore_response.all_data_rd.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400491  10     offcore_response.all_data_rd.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400491  10     offcore_response.all_data_rd.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020491  10     offcore_response.all_data_rd.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020491  10     offcore_response.all_data_rd.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020491  10     offcore_response.all_data_rd.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020491  10     offcore_response.all_data_rd.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020491  10     offcore_response.all_data_rd.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200020491  10     offcore_response.all_data_rd.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80020491  10     offcore_response.all_pf_data_rd.any_response cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10490  10     offcore_response.all_pf_data_rd.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0490  10     offcore_response.all_pf_data_rd.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0490  10     offcore_response.all_pf_data_rd.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0490  10     offcore_response.all_pf_data_rd.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0490  10     offcore_response.all_pf_data_rd.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0490  10     offcore_response.all_pf_data_rd.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0490  10     offcore_response.all_pf_data_rd.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0490  10     offcore_response.all_pf_data_rd.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0490  10     offcore_response.all_pf_data_rd.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080490  10     offcore_response.all_pf_data_rd.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080490  10     offcore_response.all_pf_data_rd.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080490  10     offcore_response.all_pf_data_rd.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080490  10     offcore_response.all_pf_data_rd.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080490  10     offcore_response.all_pf_data_rd.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200080490  10     offcore_response.all_pf_data_rd.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80080490  10     offcore_response.all_pf_data_rd.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200490  10     offcore_response.all_pf_data_rd.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200490  10     offcore_response.all_pf_data_rd.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200490  10     offcore_response.all_pf_data_rd.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200490  10     offcore_response.all_pf_data_rd.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200490  10     offcore_response.all_pf_data_rd.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200200490  10     offcore_response.all_pf_data_rd.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80200490  10     offcore_response.all_pf_data_rd.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040490  10     offcore_response.all_pf_data_rd.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040490  10     offcore_response.all_pf_data_rd.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040490  10     offcore_response.all_pf_data_rd.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040490  10     offcore_response.all_pf_data_rd.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040490  10     offcore_response.all_pf_data_rd.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200040490  10     offcore_response.all_pf_data_rd.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80040490  10     offcore_response.all_pf_data_rd.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100490  10     offcore_response.all_pf_data_rd.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100490  10     offcore_response.all_pf_data_rd.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100490  10     offcore_response.all_pf_data_rd.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100490  10     offcore_response.all_pf_data_rd.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100490  10     offcore_response.all_pf_data_rd.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200100490  10     offcore_response.all_pf_data_rd.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80100490  10     offcore_response.all_pf_data_rd.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400490  10     offcore_response.all_pf_data_rd.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400490  10     offcore_response.all_pf_data_rd.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400490  10     offcore_response.all_pf_data_rd.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020490  10     offcore_response.all_pf_data_rd.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020490  10     offcore_response.all_pf_data_rd.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020490  10     offcore_response.all_pf_data_rd.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020490  10     offcore_response.all_pf_data_rd.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020490  10     offcore_response.all_pf_data_rd.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200020490  10     offcore_response.all_pf_data_rd.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80020490  10     offcore_response.all_pf_rfo.any_response cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10120  10     offcore_response.all_pf_rfo.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0120  10     offcore_response.all_pf_rfo.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0120  10     offcore_response.all_pf_rfo.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0120  10     offcore_response.all_pf_rfo.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0120  10     offcore_response.all_pf_rfo.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0120  10     offcore_response.all_pf_rfo.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0120  10     offcore_response.all_pf_rfo.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0120  10     offcore_response.all_pf_rfo.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0120  10     offcore_response.all_pf_rfo.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080120  10     offcore_response.all_pf_rfo.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080120  10     offcore_response.all_pf_rfo.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080120  10     offcore_response.all_pf_rfo.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080120  10     offcore_response.all_pf_rfo.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080120  10     offcore_response.all_pf_rfo.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200080120  10     offcore_response.all_pf_rfo.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80080120  10     offcore_response.all_pf_rfo.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200120  10     offcore_response.all_pf_rfo.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200120  10     offcore_response.all_pf_rfo.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200120  10     offcore_response.all_pf_rfo.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200120  10     offcore_response.all_pf_rfo.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200120  10     offcore_response.all_pf_rfo.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200200120  10     offcore_response.all_pf_rfo.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80200120  10     offcore_response.all_pf_rfo.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040120  10     offcore_response.all_pf_rfo.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040120  10     offcore_response.all_pf_rfo.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040120  10     offcore_response.all_pf_rfo.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040120  10     offcore_response.all_pf_rfo.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040120  10     offcore_response.all_pf_rfo.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200040120  10     offcore_response.all_pf_rfo.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80040120  10     offcore_response.all_pf_rfo.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100120  10     offcore_response.all_pf_rfo.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100120  10     offcore_response.all_pf_rfo.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100120  10     offcore_response.all_pf_rfo.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100120  10     offcore_response.all_pf_rfo.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100120  10     offcore_response.all_pf_rfo.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200100120  10     offcore_response.all_pf_rfo.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80100120  10     offcore_response.all_pf_rfo.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400120  10     offcore_response.all_pf_rfo.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400120  10     offcore_response.all_pf_rfo.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400120  10     offcore_response.all_pf_rfo.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020120  10     offcore_response.all_pf_rfo.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020120  10     offcore_response.all_pf_rfo.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020120  10     offcore_response.all_pf_rfo.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020120  10     offcore_response.all_pf_rfo.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020120  10     offcore_response.all_pf_rfo.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200020120  10     offcore_response.all_pf_rfo.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80020120  10     offcore_response.all_reads.any_response cache This event is deprecated. Refer to new event OCR.ALL_READS.ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x107F7  10     offcore_response.all_reads.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C07F7  10     offcore_response.all_reads.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C07F7  10     offcore_response.all_reads.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C07F7  10     offcore_response.all_reads.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C07F7  10     offcore_response.all_reads.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C07F7  10     offcore_response.all_reads.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C07F7  10     offcore_response.all_reads.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C07F7  10     offcore_response.all_reads.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C07F7  10     offcore_response.all_reads.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F800807F7  10     offcore_response.all_reads.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10000807F7  10     offcore_response.all_reads.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8000807F7  10     offcore_response.all_reads.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4000807F7  10     offcore_response.all_reads.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1000807F7  10     offcore_response.all_reads.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2000807F7  10     offcore_response.all_reads.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x800807F7  10     offcore_response.all_reads.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F802007F7  10     offcore_response.all_reads.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10002007F7  10     offcore_response.all_reads.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8002007F7  10     offcore_response.all_reads.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4002007F7  10     offcore_response.all_reads.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1002007F7  10     offcore_response.all_reads.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2002007F7  10     offcore_response.all_reads.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x802007F7  10     offcore_response.all_reads.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F800407F7  10     offcore_response.all_reads.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10000407F7  10     offcore_response.all_reads.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8000407F7  10     offcore_response.all_reads.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4000407F7  10     offcore_response.all_reads.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1000407F7  10     offcore_response.all_reads.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2000407F7  10     offcore_response.all_reads.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x800407F7  10     offcore_response.all_reads.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F801007F7  10     offcore_response.all_reads.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10001007F7  10     offcore_response.all_reads.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8001007F7  10     offcore_response.all_reads.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4001007F7  10     offcore_response.all_reads.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1001007F7  10     offcore_response.all_reads.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2001007F7  10     offcore_response.all_reads.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x801007F7  10     offcore_response.all_reads.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F804007F7  10     offcore_response.all_reads.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x804007F7  10     offcore_response.all_reads.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1004007F7  10     offcore_response.all_reads.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F800207F7  10     offcore_response.all_reads.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10000207F7  10     offcore_response.all_reads.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8000207F7  10     offcore_response.all_reads.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4000207F7  10     offcore_response.all_reads.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1000207F7  10     offcore_response.all_reads.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2000207F7  10     offcore_response.all_reads.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x800207F7  10     offcore_response.all_rfo.any_response cache This event is deprecated. Refer to new event OCR.ALL_RFO.ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10122  10     offcore_response.all_rfo.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0122  10     offcore_response.all_rfo.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0122  10     offcore_response.all_rfo.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0122  10     offcore_response.all_rfo.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0122  10     offcore_response.all_rfo.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0122  10     offcore_response.all_rfo.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0122  10     offcore_response.all_rfo.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0122  10     offcore_response.all_rfo.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0122  10     offcore_response.all_rfo.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080122  10     offcore_response.all_rfo.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080122  10     offcore_response.all_rfo.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080122  10     offcore_response.all_rfo.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080122  10     offcore_response.all_rfo.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080122  10     offcore_response.all_rfo.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200080122  10     offcore_response.all_rfo.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80080122  10     offcore_response.all_rfo.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200122  10     offcore_response.all_rfo.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200122  10     offcore_response.all_rfo.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200122  10     offcore_response.all_rfo.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200122  10     offcore_response.all_rfo.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200122  10     offcore_response.all_rfo.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200200122  10     offcore_response.all_rfo.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80200122  10     offcore_response.all_rfo.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040122  10     offcore_response.all_rfo.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040122  10     offcore_response.all_rfo.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040122  10     offcore_response.all_rfo.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040122  10     offcore_response.all_rfo.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040122  10     offcore_response.all_rfo.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200040122  10     offcore_response.all_rfo.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80040122  10     offcore_response.all_rfo.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100122  10     offcore_response.all_rfo.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100122  10     offcore_response.all_rfo.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100122  10     offcore_response.all_rfo.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100122  10     offcore_response.all_rfo.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100122  10     offcore_response.all_rfo.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200100122  10     offcore_response.all_rfo.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80100122  10     offcore_response.all_rfo.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400122  10     offcore_response.all_rfo.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400122  10     offcore_response.all_rfo.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400122  10     offcore_response.all_rfo.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020122  10     offcore_response.all_rfo.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020122  10     offcore_response.all_rfo.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020122  10     offcore_response.all_rfo.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020122  10     offcore_response.all_rfo.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020122  10     offcore_response.all_rfo.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200020122  10     offcore_response.all_rfo.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80020122  10     offcore_response.demand_code_rd.any_response cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10004  10     offcore_response.demand_code_rd.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0004  10     offcore_response.demand_code_rd.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0004  10     offcore_response.demand_code_rd.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0004  10     offcore_response.demand_code_rd.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0004  10     offcore_response.demand_code_rd.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0004  10     offcore_response.demand_code_rd.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0004  10     offcore_response.demand_code_rd.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0004  10     offcore_response.demand_code_rd.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0004  10     offcore_response.demand_code_rd.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080004  10     offcore_response.demand_code_rd.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080004  10     offcore_response.demand_code_rd.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080004  10     offcore_response.demand_code_rd.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080004  10     offcore_response.demand_code_rd.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080004  10     offcore_response.demand_code_rd.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200080004  10     offcore_response.demand_code_rd.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80080004  10     offcore_response.demand_code_rd.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200004  10     offcore_response.demand_code_rd.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200004  10     offcore_response.demand_code_rd.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200004  10     offcore_response.demand_code_rd.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200004  10     offcore_response.demand_code_rd.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200004  10     offcore_response.demand_code_rd.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200200004  10     offcore_response.demand_code_rd.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80200004  10     offcore_response.demand_code_rd.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040004  10     offcore_response.demand_code_rd.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040004  10     offcore_response.demand_code_rd.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040004  10     offcore_response.demand_code_rd.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040004  10     offcore_response.demand_code_rd.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040004  10     offcore_response.demand_code_rd.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200040004  10     offcore_response.demand_code_rd.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80040004  10     offcore_response.demand_code_rd.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100004  10     offcore_response.demand_code_rd.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100004  10     offcore_response.demand_code_rd.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100004  10     offcore_response.demand_code_rd.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100004  10     offcore_response.demand_code_rd.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100004  10     offcore_response.demand_code_rd.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200100004  10     offcore_response.demand_code_rd.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80100004  10     offcore_response.demand_code_rd.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400004  10     offcore_response.demand_code_rd.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400004  10     offcore_response.demand_code_rd.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400004  10     offcore_response.demand_code_rd.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020004  10     offcore_response.demand_code_rd.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020004  10     offcore_response.demand_code_rd.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020004  10     offcore_response.demand_code_rd.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020004  10     offcore_response.demand_code_rd.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020004  10     offcore_response.demand_code_rd.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200020004  10     offcore_response.demand_code_rd.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80020004  10     offcore_response.demand_data_rd.any_response cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10001  10     offcore_response.demand_data_rd.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0001  10     offcore_response.demand_data_rd.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0001  10     offcore_response.demand_data_rd.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0001  10     offcore_response.demand_data_rd.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0001  10     offcore_response.demand_data_rd.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0001  10     offcore_response.demand_data_rd.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0001  10     offcore_response.demand_data_rd.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0001  10     offcore_response.demand_data_rd.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0001  10     offcore_response.demand_data_rd.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080001  10     offcore_response.demand_data_rd.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080001  10     offcore_response.demand_data_rd.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080001  10     offcore_response.demand_data_rd.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080001  10     offcore_response.demand_data_rd.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080001  10     offcore_response.demand_data_rd.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200080001  10     offcore_response.demand_data_rd.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80080001  10     offcore_response.demand_data_rd.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200001  10     offcore_response.demand_data_rd.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200001  10     offcore_response.demand_data_rd.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200001  10     offcore_response.demand_data_rd.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200001  10     offcore_response.demand_data_rd.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200001  10     offcore_response.demand_data_rd.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200200001  10     offcore_response.demand_data_rd.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80200001  10     offcore_response.demand_data_rd.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040001  10     offcore_response.demand_data_rd.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040001  10     offcore_response.demand_data_rd.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040001  10     offcore_response.demand_data_rd.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040001  10     offcore_response.demand_data_rd.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040001  10     offcore_response.demand_data_rd.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200040001  10     offcore_response.demand_data_rd.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80040001  10     offcore_response.demand_data_rd.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100001  10     offcore_response.demand_data_rd.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100001  10     offcore_response.demand_data_rd.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100001  10     offcore_response.demand_data_rd.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100001  10     offcore_response.demand_data_rd.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100001  10     offcore_response.demand_data_rd.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200100001  10     offcore_response.demand_data_rd.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80100001  10     offcore_response.demand_data_rd.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400001  10     offcore_response.demand_data_rd.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400001  10     offcore_response.demand_data_rd.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400001  10     offcore_response.demand_data_rd.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020001  10     offcore_response.demand_data_rd.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020001  10     offcore_response.demand_data_rd.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020001  10     offcore_response.demand_data_rd.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020001  10     offcore_response.demand_data_rd.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020001  10     offcore_response.demand_data_rd.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200020001  10     offcore_response.demand_data_rd.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80020001  10     offcore_response.demand_rfo.any_response cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10002  10     offcore_response.demand_rfo.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0002  10     offcore_response.demand_rfo.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0002  10     offcore_response.demand_rfo.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0002  10     offcore_response.demand_rfo.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0002  10     offcore_response.demand_rfo.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0002  10     offcore_response.demand_rfo.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0002  10     offcore_response.demand_rfo.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0002  10     offcore_response.demand_rfo.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0002  10     offcore_response.demand_rfo.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080002  10     offcore_response.demand_rfo.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080002  10     offcore_response.demand_rfo.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080002  10     offcore_response.demand_rfo.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080002  10     offcore_response.demand_rfo.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080002  10     offcore_response.demand_rfo.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200080002  10     offcore_response.demand_rfo.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80080002  10     offcore_response.demand_rfo.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200002  10     offcore_response.demand_rfo.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200002  10     offcore_response.demand_rfo.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200002  10     offcore_response.demand_rfo.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200002  10     offcore_response.demand_rfo.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200002  10     offcore_response.demand_rfo.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200200002  10     offcore_response.demand_rfo.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80200002  10     offcore_response.demand_rfo.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040002  10     offcore_response.demand_rfo.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040002  10     offcore_response.demand_rfo.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040002  10     offcore_response.demand_rfo.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040002  10     offcore_response.demand_rfo.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040002  10     offcore_response.demand_rfo.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200040002  10     offcore_response.demand_rfo.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80040002  10     offcore_response.demand_rfo.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100002  10     offcore_response.demand_rfo.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100002  10     offcore_response.demand_rfo.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100002  10     offcore_response.demand_rfo.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100002  10     offcore_response.demand_rfo.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100002  10     offcore_response.demand_rfo.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200100002  10     offcore_response.demand_rfo.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80100002  10     offcore_response.demand_rfo.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400002  10     offcore_response.demand_rfo.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400002  10     offcore_response.demand_rfo.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400002  10     offcore_response.demand_rfo.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020002  10     offcore_response.demand_rfo.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020002  10     offcore_response.demand_rfo.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020002  10     offcore_response.demand_rfo.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020002  10     offcore_response.demand_rfo.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020002  10     offcore_response.demand_rfo.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200020002  10     offcore_response.demand_rfo.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80020002  10     offcore_response.other.any_response cache This event is deprecated. Refer to new event OCR.OTHER.ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x18000  10     offcore_response.other.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C8000  10     offcore_response.other.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C8000  10     offcore_response.other.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C8000  10     offcore_response.other.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C8000  10     offcore_response.other.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C8000  10     offcore_response.other.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C8000  10     offcore_response.other.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C8000  10     offcore_response.other.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C8000  10     offcore_response.other.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80088000  10     offcore_response.other.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000088000  10     offcore_response.other.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800088000  10     offcore_response.other.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400088000  10     offcore_response.other.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100088000  10     offcore_response.other.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200088000  10     offcore_response.other.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80088000  10     offcore_response.other.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80208000  10     offcore_response.other.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000208000  10     offcore_response.other.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800208000  10     offcore_response.other.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400208000  10     offcore_response.other.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100208000  10     offcore_response.other.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200208000  10     offcore_response.other.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80208000  10     offcore_response.other.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80048000  10     offcore_response.other.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000048000  10     offcore_response.other.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800048000  10     offcore_response.other.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400048000  10     offcore_response.other.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100048000  10     offcore_response.other.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200048000  10     offcore_response.other.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80048000  10     offcore_response.other.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80108000  10     offcore_response.other.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000108000  10     offcore_response.other.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800108000  10     offcore_response.other.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400108000  10     offcore_response.other.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100108000  10     offcore_response.other.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200108000  10     offcore_response.other.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80108000  10     offcore_response.other.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80408000  10     offcore_response.other.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80408000  10     offcore_response.other.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100408000  10     offcore_response.other.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80028000  10     offcore_response.other.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000028000  10     offcore_response.other.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800028000  10     offcore_response.other.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400028000  10     offcore_response.other.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100028000  10     offcore_response.other.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200028000  10     offcore_response.other.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80028000  10     offcore_response.pf_l1d_and_sw.any_response cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10400  10     offcore_response.pf_l1d_and_sw.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0400  10     offcore_response.pf_l1d_and_sw.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0400  10     offcore_response.pf_l1d_and_sw.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0400  10     offcore_response.pf_l1d_and_sw.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0400  10     offcore_response.pf_l1d_and_sw.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0400  10     offcore_response.pf_l1d_and_sw.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0400  10     offcore_response.pf_l1d_and_sw.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0400  10     offcore_response.pf_l1d_and_sw.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0400  10     offcore_response.pf_l1d_and_sw.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080400  10     offcore_response.pf_l1d_and_sw.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080400  10     offcore_response.pf_l1d_and_sw.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080400  10     offcore_response.pf_l1d_and_sw.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080400  10     offcore_response.pf_l1d_and_sw.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080400  10     offcore_response.pf_l1d_and_sw.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200080400  10     offcore_response.pf_l1d_and_sw.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80080400  10     offcore_response.pf_l1d_and_sw.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200400  10     offcore_response.pf_l1d_and_sw.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200400  10     offcore_response.pf_l1d_and_sw.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200400  10     offcore_response.pf_l1d_and_sw.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200400  10     offcore_response.pf_l1d_and_sw.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200400  10     offcore_response.pf_l1d_and_sw.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200200400  10     offcore_response.pf_l1d_and_sw.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80200400  10     offcore_response.pf_l1d_and_sw.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040400  10     offcore_response.pf_l1d_and_sw.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040400  10     offcore_response.pf_l1d_and_sw.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040400  10     offcore_response.pf_l1d_and_sw.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040400  10     offcore_response.pf_l1d_and_sw.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040400  10     offcore_response.pf_l1d_and_sw.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200040400  10     offcore_response.pf_l1d_and_sw.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80040400  10     offcore_response.pf_l1d_and_sw.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100400  10     offcore_response.pf_l1d_and_sw.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100400  10     offcore_response.pf_l1d_and_sw.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100400  10     offcore_response.pf_l1d_and_sw.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100400  10     offcore_response.pf_l1d_and_sw.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100400  10     offcore_response.pf_l1d_and_sw.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200100400  10     offcore_response.pf_l1d_and_sw.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80100400  10     offcore_response.pf_l1d_and_sw.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400400  10     offcore_response.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400400  10     offcore_response.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400400  10     offcore_response.pf_l1d_and_sw.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020400  10     offcore_response.pf_l1d_and_sw.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020400  10     offcore_response.pf_l1d_and_sw.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020400  10     offcore_response.pf_l1d_and_sw.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020400  10     offcore_response.pf_l1d_and_sw.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020400  10     offcore_response.pf_l1d_and_sw.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200020400  10     offcore_response.pf_l1d_and_sw.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80020400  10     offcore_response.pf_l2_data_rd.any_response cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10010  10     offcore_response.pf_l2_data_rd.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0010  10     offcore_response.pf_l2_data_rd.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0010  10     offcore_response.pf_l2_data_rd.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0010  10     offcore_response.pf_l2_data_rd.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0010  10     offcore_response.pf_l2_data_rd.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0010  10     offcore_response.pf_l2_data_rd.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0010  10     offcore_response.pf_l2_data_rd.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0010  10     offcore_response.pf_l2_data_rd.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0010  10     offcore_response.pf_l2_data_rd.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080010  10     offcore_response.pf_l2_data_rd.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080010  10     offcore_response.pf_l2_data_rd.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080010  10     offcore_response.pf_l2_data_rd.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080010  10     offcore_response.pf_l2_data_rd.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080010  10     offcore_response.pf_l2_data_rd.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200080010  10     offcore_response.pf_l2_data_rd.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80080010  10     offcore_response.pf_l2_data_rd.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200010  10     offcore_response.pf_l2_data_rd.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200010  10     offcore_response.pf_l2_data_rd.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200010  10     offcore_response.pf_l2_data_rd.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200010  10     offcore_response.pf_l2_data_rd.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200010  10     offcore_response.pf_l2_data_rd.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200200010  10     offcore_response.pf_l2_data_rd.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80200010  10     offcore_response.pf_l2_data_rd.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040010  10     offcore_response.pf_l2_data_rd.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040010  10     offcore_response.pf_l2_data_rd.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040010  10     offcore_response.pf_l2_data_rd.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040010  10     offcore_response.pf_l2_data_rd.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040010  10     offcore_response.pf_l2_data_rd.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200040010  10     offcore_response.pf_l2_data_rd.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80040010  10     offcore_response.pf_l2_data_rd.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100010  10     offcore_response.pf_l2_data_rd.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100010  10     offcore_response.pf_l2_data_rd.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100010  10     offcore_response.pf_l2_data_rd.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100010  10     offcore_response.pf_l2_data_rd.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100010  10     offcore_response.pf_l2_data_rd.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200100010  10     offcore_response.pf_l2_data_rd.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80100010  10     offcore_response.pf_l2_data_rd.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400010  10     offcore_response.pf_l2_data_rd.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400010  10     offcore_response.pf_l2_data_rd.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400010  10     offcore_response.pf_l2_data_rd.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020010  10     offcore_response.pf_l2_data_rd.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020010  10     offcore_response.pf_l2_data_rd.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020010  10     offcore_response.pf_l2_data_rd.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020010  10     offcore_response.pf_l2_data_rd.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020010  10     offcore_response.pf_l2_data_rd.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200020010  10     offcore_response.pf_l2_data_rd.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80020010  10     offcore_response.pf_l2_rfo.any_response cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10020  10     offcore_response.pf_l2_rfo.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0020  10     offcore_response.pf_l2_rfo.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0020  10     offcore_response.pf_l2_rfo.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0020  10     offcore_response.pf_l2_rfo.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0020  10     offcore_response.pf_l2_rfo.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0020  10     offcore_response.pf_l2_rfo.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0020  10     offcore_response.pf_l2_rfo.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0020  10     offcore_response.pf_l2_rfo.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0020  10     offcore_response.pf_l2_rfo.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080020  10     offcore_response.pf_l2_rfo.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080020  10     offcore_response.pf_l2_rfo.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080020  10     offcore_response.pf_l2_rfo.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080020  10     offcore_response.pf_l2_rfo.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080020  10     offcore_response.pf_l2_rfo.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200080020  10     offcore_response.pf_l2_rfo.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80080020  10     offcore_response.pf_l2_rfo.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200020  10     offcore_response.pf_l2_rfo.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200020  10     offcore_response.pf_l2_rfo.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200020  10     offcore_response.pf_l2_rfo.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200020  10     offcore_response.pf_l2_rfo.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200020  10     offcore_response.pf_l2_rfo.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200200020  10     offcore_response.pf_l2_rfo.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80200020  10     offcore_response.pf_l2_rfo.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040020  10     offcore_response.pf_l2_rfo.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040020  10     offcore_response.pf_l2_rfo.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040020  10     offcore_response.pf_l2_rfo.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040020  10     offcore_response.pf_l2_rfo.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040020  10     offcore_response.pf_l2_rfo.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200040020  10     offcore_response.pf_l2_rfo.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80040020  10     offcore_response.pf_l2_rfo.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100020  10     offcore_response.pf_l2_rfo.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100020  10     offcore_response.pf_l2_rfo.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100020  10     offcore_response.pf_l2_rfo.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100020  10     offcore_response.pf_l2_rfo.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100020  10     offcore_response.pf_l2_rfo.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200100020  10     offcore_response.pf_l2_rfo.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80100020  10     offcore_response.pf_l2_rfo.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400020  10     offcore_response.pf_l2_rfo.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400020  10     offcore_response.pf_l2_rfo.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400020  10     offcore_response.pf_l2_rfo.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020020  10     offcore_response.pf_l2_rfo.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020020  10     offcore_response.pf_l2_rfo.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020020  10     offcore_response.pf_l2_rfo.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020020  10     offcore_response.pf_l2_rfo.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020020  10     offcore_response.pf_l2_rfo.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200020020  10     offcore_response.pf_l2_rfo.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80020020  10     offcore_response.pf_l3_data_rd.any_response cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10080  10     offcore_response.pf_l3_data_rd.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0080  10     offcore_response.pf_l3_data_rd.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0080  10     offcore_response.pf_l3_data_rd.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0080  10     offcore_response.pf_l3_data_rd.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0080  10     offcore_response.pf_l3_data_rd.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0080  10     offcore_response.pf_l3_data_rd.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0080  10     offcore_response.pf_l3_data_rd.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0080  10     offcore_response.pf_l3_data_rd.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0080  10     offcore_response.pf_l3_data_rd.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080080  10     offcore_response.pf_l3_data_rd.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080080  10     offcore_response.pf_l3_data_rd.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080080  10     offcore_response.pf_l3_data_rd.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080080  10     offcore_response.pf_l3_data_rd.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080080  10     offcore_response.pf_l3_data_rd.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200080080  10     offcore_response.pf_l3_data_rd.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80080080  10     offcore_response.pf_l3_data_rd.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200080  10     offcore_response.pf_l3_data_rd.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200080  10     offcore_response.pf_l3_data_rd.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200080  10     offcore_response.pf_l3_data_rd.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200080  10     offcore_response.pf_l3_data_rd.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200080  10     offcore_response.pf_l3_data_rd.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200200080  10     offcore_response.pf_l3_data_rd.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80200080  10     offcore_response.pf_l3_data_rd.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040080  10     offcore_response.pf_l3_data_rd.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040080  10     offcore_response.pf_l3_data_rd.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040080  10     offcore_response.pf_l3_data_rd.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040080  10     offcore_response.pf_l3_data_rd.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040080  10     offcore_response.pf_l3_data_rd.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200040080  10     offcore_response.pf_l3_data_rd.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80040080  10     offcore_response.pf_l3_data_rd.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100080  10     offcore_response.pf_l3_data_rd.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100080  10     offcore_response.pf_l3_data_rd.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100080  10     offcore_response.pf_l3_data_rd.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100080  10     offcore_response.pf_l3_data_rd.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100080  10     offcore_response.pf_l3_data_rd.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200100080  10     offcore_response.pf_l3_data_rd.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80100080  10     offcore_response.pf_l3_data_rd.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400080  10     offcore_response.pf_l3_data_rd.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400080  10     offcore_response.pf_l3_data_rd.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400080  10     offcore_response.pf_l3_data_rd.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020080  10     offcore_response.pf_l3_data_rd.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020080  10     offcore_response.pf_l3_data_rd.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020080  10     offcore_response.pf_l3_data_rd.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020080  10     offcore_response.pf_l3_data_rd.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020080  10     offcore_response.pf_l3_data_rd.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200020080  10     offcore_response.pf_l3_data_rd.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80020080  10     offcore_response.pf_l3_rfo.any_response cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10100  10     offcore_response.pf_l3_rfo.l3_hit.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0100  10     offcore_response.pf_l3_rfo.l3_hit.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0100  10     offcore_response.pf_l3_rfo.l3_hit.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0100  10     offcore_response.pf_l3_rfo.l3_hit.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0100  10     offcore_response.pf_l3_rfo.l3_hit.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0100  10     offcore_response.pf_l3_rfo.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8007C0100  10     offcore_response.pf_l3_rfo.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0100  10     offcore_response.pf_l3_rfo.l3_hit.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x803C0100  10     offcore_response.pf_l3_rfo.l3_hit_e.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80080100  10     offcore_response.pf_l3_rfo.l3_hit_e.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080100  10     offcore_response.pf_l3_rfo.l3_hit_e.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800080100  10     offcore_response.pf_l3_rfo.l3_hit_e.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400080100  10     offcore_response.pf_l3_rfo.l3_hit_e.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100080100  10     offcore_response.pf_l3_rfo.l3_hit_e.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200080100  10     offcore_response.pf_l3_rfo.l3_hit_e.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80080100  10     offcore_response.pf_l3_rfo.l3_hit_f.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80200100  10     offcore_response.pf_l3_rfo.l3_hit_f.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000200100  10     offcore_response.pf_l3_rfo.l3_hit_f.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800200100  10     offcore_response.pf_l3_rfo.l3_hit_f.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400200100  10     offcore_response.pf_l3_rfo.l3_hit_f.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100200100  10     offcore_response.pf_l3_rfo.l3_hit_f.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200200100  10     offcore_response.pf_l3_rfo.l3_hit_f.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80200100  10     offcore_response.pf_l3_rfo.l3_hit_m.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80040100  10     offcore_response.pf_l3_rfo.l3_hit_m.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040100  10     offcore_response.pf_l3_rfo.l3_hit_m.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800040100  10     offcore_response.pf_l3_rfo.l3_hit_m.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400040100  10     offcore_response.pf_l3_rfo.l3_hit_m.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100040100  10     offcore_response.pf_l3_rfo.l3_hit_m.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200040100  10     offcore_response.pf_l3_rfo.l3_hit_m.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80040100  10     offcore_response.pf_l3_rfo.l3_hit_s.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80100100  10     offcore_response.pf_l3_rfo.l3_hit_s.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100100  10     offcore_response.pf_l3_rfo.l3_hit_s.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800100100  10     offcore_response.pf_l3_rfo.l3_hit_s.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400100100  10     offcore_response.pf_l3_rfo.l3_hit_s.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100100100  10     offcore_response.pf_l3_rfo.l3_hit_s.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200100100  10     offcore_response.pf_l3_rfo.l3_hit_s.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80100100  10     offcore_response.pf_l3_rfo.pmm_hit_local_pmm.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400100  10     offcore_response.pf_l3_rfo.pmm_hit_local_pmm.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400100  10     offcore_response.pf_l3_rfo.pmm_hit_local_pmm.snoop_not_needed cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400100  10     offcore_response.pf_l3_rfo.supplier_none.any_snoop cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020100  10     offcore_response.pf_l3_rfo.supplier_none.hitm_other_core cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020100  10     offcore_response.pf_l3_rfo.supplier_none.hit_other_core_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020100  10     offcore_response.pf_l3_rfo.supplier_none.hit_other_core_no_fwd cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020100  10     offcore_response.pf_l3_rfo.supplier_none.no_snoop_needed cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020100  10     offcore_response.pf_l3_rfo.supplier_none.snoop_miss cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200020100  10     offcore_response.pf_l3_rfo.supplier_none.snoop_none cache This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80020100  10     sq_misc.split_lock cache Number of cache line split locks sent to uncore event=0xf4,period=100003,umask=0x10  00    Counts the number of cache line split locks sent to the uncore sw_prefetch_access.any cache Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed event=0x32,period=2000003,umask=0xf  00     sw_prefetch_access.nta cache Number of PREFETCHNTA instructions executed event=0x32,period=2000003,umask=1  00     sw_prefetch_access.prefetchw cache Number of PREFETCHW instructions executed event=0x32,period=2000003,umask=8  00     sw_prefetch_access.t0 cache Number of PREFETCHT0 instructions executed event=0x32,period=2000003,umask=2  00     sw_prefetch_access.t1_t2 cache Number of PREFETCHT1 or PREFETCHT2 instructions executed event=0x32,period=2000003,umask=4  00     fp_arith_inst_retired.128b_packed_double floating point Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired event=0xc7,period=2000003,umask=4  00    Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.128b_packed_single floating point Counts once for most SIMD 128-bit packed computational single precision floating-point instruction retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired event=0xc7,period=2000003,umask=8  00    Counts once for most SIMD 128-bit packed computational single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.256b_packed_double floating point Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired event=0xc7,period=2000003,umask=0x10  00    Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.256b_packed_single floating point Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired event=0xc7,period=2000003,umask=0x20  00    Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.4_flops floating point Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below.  Each count represents 2 or/and 4 computation operations, 1 for each element.  Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element event=0xc7,period=1000003,umask=0x18  00    Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision  floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 or/and 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.512b_packed_double floating point Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=2000003,umask=0x40  00    Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.  The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.512b_packed_single floating point Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=2000003,umask=0x80  00    Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.8_flops floating point Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision  FP instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, 1 for each element.  Applies to SSE* and AVX* packed single precision and double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element event=0xc7,period=1000003,umask=0x18  00    Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision  floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision and double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.scalar floating point Counts once for most SIMD scalar computational floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired event=0xc7,period=2000003,umask=3  00    Counts once for most SIMD scalar computational single precision and double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.scalar_double floating point Counts once for most SIMD scalar computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired event=0xc7,period=2000003,umask=1  00    Counts once for most SIMD scalar computational double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SIMD scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.scalar_single floating point Counts once for most SIMD scalar computational single precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired event=0xc7,period=2000003,umask=2  00    Counts once for most SIMD scalar computational single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired2.128bit_packed_bf16 floating point Intel AVX-512 computational 512-bit packed BFloat16 instructions retired event=0xcf,period=2000003,umask=0x20  00    Counts once for each Intel AVX-512 computational 128-bit packed BFloat16 floating-point instruction retired. Applies to the XMM based VDPBF16PS instruction. Each count represents 16 computation operations. This event is only supported on products formerly named Cooper Lake and is not supported on products formerly named Cascade Lake fp_arith_inst_retired2.256bit_packed_bf16 floating point Intel AVX-512 computational 128-bit packed BFloat16 instructions retired event=0xcf,period=2000003,umask=0x40  00    Counts once for each Intel AVX-512 computational 256-bit packed BFloat16 floating-point instruction retired. Applies to the YMM based VDPBF16PS instruction.  Each count represents 32 computation operations. This event is only supported on products formerly named Cooper Lake and is not supported on products formerly named Cascade Lake fp_arith_inst_retired2.512bit_packed_bf16 floating point Intel AVX-512 computational 256-bit packed BFloat16 instructions retired event=0xcf,period=2000003,umask=0x80  00    Counts once for each Intel AVX-512 computational 512-bit packed BFloat16 floating-point instruction retired. Applies to the ZMM based VDPBF16PS instruction.  Each count represents 64 computation operations. This event is only supported on products formerly named Cooper Lake and is not supported on products formerly named Cascade Lake fp_assist.any floating point Cycles with any input/output SSE or FP assist event=0xca,cmask=1,period=100003,umask=0x1e  00    Counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1 baclears.any frontend Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end event=0xe6,period=100003,umask=1  00    Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore decode.lcp frontend Stalls caused by changing prefix length of the instruction. [This event is alias to ILD_STALL.LCP] event=0x87,period=2000003,umask=1  00    Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to ILD_STALL.LCP] dsb2mite_switches.count frontend Decode Stream Buffer (DSB)-to-MITE switches event=0xab,period=2000003,umask=1  00    This event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses. Note: Invoking MITE requires two or three cycles delay dsb2mite_switches.penalty_cycles frontend Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles event=0xab,period=2000003,umask=2  00    Counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles frontend_retired.any_dsb_miss frontend Retired Instructions who experienced DSB miss (Precise event) event=0xc6,period=100007,umask=1,frontend=0x1  00    Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss (Precise event) frontend_retired.dsb_miss frontend Retired Instructions who experienced a critical DSB miss (Precise event) event=0xc6,period=100007,umask=1,frontend=0x11  00    Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss (Precise event) frontend_retired.itlb_miss frontend Retired Instructions who experienced iTLB true miss (Precise event) event=0xc6,period=100007,umask=1,frontend=0x14  00    Counts retired Instructions that experienced iTLB (Instruction TLB) true miss (Precise event) frontend_retired.l1i_miss frontend Retired Instructions who experienced Instruction L1 Cache true miss (Precise event) event=0xc6,period=100007,umask=1,frontend=0x12  00     frontend_retired.l2_miss frontend Retired Instructions who experienced Instruction L2 Cache true miss (Precise event) event=0xc6,period=100007,umask=1,frontend=0x13  00     frontend_retired.latency_ge_1 frontend Retired instructions after front-end starvation of at least 1 cycle (Must be precise) event=0xc6,period=100007,umask=1,frontend=0x400106  00    Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall (Must be precise) frontend_retired.latency_ge_128 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x408006  00     frontend_retired.latency_ge_16 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x401006  00    Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops (Precise event) frontend_retired.latency_ge_2 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x400206  00     frontend_retired.latency_ge_256 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x410006  00     frontend_retired.latency_ge_2_bubbles_ge_1 frontend Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x100206  00    Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall (Precise event) frontend_retired.latency_ge_2_bubbles_ge_2 frontend Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x200206  00     frontend_retired.latency_ge_2_bubbles_ge_3 frontend Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x300206  00     frontend_retired.latency_ge_32 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x402006  00    Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops (Precise event) frontend_retired.latency_ge_4 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x400406  00     frontend_retired.latency_ge_512 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x420006  00     frontend_retired.latency_ge_64 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x404006  00     frontend_retired.latency_ge_8 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=1,frontend=0x400806  00    Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops (Precise event) frontend_retired.stlb_miss frontend Retired Instructions who experienced STLB (2nd level TLB) true miss (Precise event) event=0xc6,period=100007,umask=1,frontend=0x15  00    Counts retired Instructions that experienced STLB (2nd level TLB) true miss (Precise event) icache_16b.ifdata_stall frontend Cycles where a code fetch is stalled due to L1 instruction cache miss event=0x80,period=2000003,umask=4  00    Cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity icache_64b.iftag_hit frontend Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity event=0x83,period=200003,umask=1  00     icache_64b.iftag_miss frontend Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity event=0x83,period=200003,umask=2  00     icache_64b.iftag_stall frontend Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS] event=0x83,period=200003,umask=4  00     icache_tag.stalls frontend Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL] event=0x83,period=200003,umask=4  00     idq.all_dsb_cycles_4_uops frontend Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is alias to IDQ.DSB_CYCLES_OK] event=0x79,cmask=4,period=2000003,umask=0x18  00    Counts the number of cycles 4 or more uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.DSB_CYCLES_OK] idq.all_dsb_cycles_any_uops frontend Cycles Decode Stream Buffer (DSB) is delivering any Uop [This event is alias to IDQ.DSB_CYCLES_ANY] event=0x79,cmask=1,period=2000003,umask=0x18  00    Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.DSB_CYCLES_ANY] idq.all_mite_cycles_4_uops frontend Cycles MITE is delivering 4 Uops event=0x79,cmask=4,period=2000003,umask=0x24  00    Counts the number of cycles 4 uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB) idq.all_mite_cycles_any_uops frontend Cycles MITE is delivering any Uop event=0x79,cmask=1,period=2000003,umask=0x24  00    Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB) idq.dsb_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path event=0x79,cmask=1,period=2000003,umask=8  00    Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ idq.dsb_cycles_any frontend Cycles Decode Stream Buffer (DSB) is delivering any Uop [This event is alias to IDQ.ALL_DSB_CYCLES_ANY_UOPS] event=0x79,cmask=1,period=2000003,umask=0x18  00    Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.ALL_DSB_CYCLES_ANY_UOPS] idq.dsb_cycles_ok frontend Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS] event=0x79,cmask=4,period=2000003,umask=0x18  00    Counts the number of cycles 4 or more uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS] idq.dsb_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path event=0x79,period=2000003,umask=8  00    Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ idq.mite_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,cmask=1,period=2000003,umask=4  00    Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ idq.mite_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,period=2000003,umask=4  00    Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) idq.ms_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,period=2000003,umask=0x30  00    Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE idq.ms_dsb_cycles frontend Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,period=2000003,umask=0x10  00    Counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ idq.ms_mite_uops frontend Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x20  00    Counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ idq.ms_uops frontend Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x30  00    Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS idq_uops_not_delivered.core frontend Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled event=0x9c,period=2000003,umask=1  00    Counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4  x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions).  c. Instruction Decode Queue (IDQ) delivers four uops idq_uops_not_delivered.cycles_0_uops_deliv.core frontend Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled event=0x9c,cmask=4,period=2000003,umask=1  00    Counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4 idq_uops_not_delivered.cycles_le_1_uop_deliv.core frontend Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled event=0x9c,cmask=3,period=2000003,umask=1  00    Counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >= 3 idq_uops_not_delivered.cycles_le_2_uop_deliv.core frontend Cycles with less than 2 uops delivered by the front end event=0x9c,cmask=2,period=2000003,umask=1  00    Cycles with less than 2 uops delivered by the front-end idq_uops_not_delivered.cycles_le_3_uop_deliv.core frontend Cycles with less than 3 uops delivered by the front end event=0x9c,cmask=1,period=2000003,umask=1  00    Cycles with less than 3 uops delivered by the front-end cycle_activity.cycles_l3_miss memory Cycles while L3 cache miss demand load is outstanding event=0xa3,cmask=2,period=2000003,umask=2  00     cycle_activity.stalls_l3_miss memory Execution stalls while L3 cache miss demand load is outstanding event=0xa3,cmask=6,period=2000003,umask=6  00     hle_retired.aborted memory Number of times an HLE execution aborted due to any reasons (multiple categories may count as one) (Precise event) event=0xc8,period=2000003,umask=4  00    Number of times HLE abort was triggered (Precise event) hle_retired.aborted_events memory Number of times an HLE execution aborted due to unfriendly events (such as interrupts) event=0xc8,period=2000003,umask=0x80  00     hle_retired.aborted_mem memory Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts) event=0xc8,period=2000003,umask=8  00     hle_retired.aborted_memtype memory Number of times an HLE execution aborted due to incompatible memory type event=0xc8,period=2000003,umask=0x40  00     hle_retired.aborted_timer memory Number of times an HLE execution aborted due to hardware timer expiration event=0xc8,period=2000003,umask=0x10  00     hle_retired.aborted_unfriendly memory Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.) event=0xc8,period=2000003,umask=0x20  00     hle_retired.commit memory Number of times an HLE execution successfully committed event=0xc8,period=2000003,umask=2  00    Number of times HLE commit succeeded hle_retired.start memory Number of times an HLE execution started event=0xc8,period=2000003,umask=1  00    Number of times we entered an HLE region. Does not count nested transactions machine_clears.memory_ordering memory Counts the number of machine clears due to memory order conflicts  Spec update: SKL089 event=0xc3,period=100003,umask=2  00    Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer  Spec update: SKL089 mem_trans_retired.load_latency_gt_128 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles  Supports address when precise (Must be precise) event=0xcd,period=1009,umask=1,ldlat=0x80  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise (Must be precise) mem_trans_retired.load_latency_gt_16 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles  Supports address when precise (Must be precise) event=0xcd,period=20011,umask=1,ldlat=0x10  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise (Must be precise) mem_trans_retired.load_latency_gt_256 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles  Supports address when precise (Must be precise) event=0xcd,period=503,umask=1,ldlat=0x100  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise (Must be precise) mem_trans_retired.load_latency_gt_32 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles  Supports address when precise (Must be precise) event=0xcd,period=100007,umask=1,ldlat=0x20  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise (Must be precise) mem_trans_retired.load_latency_gt_4 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles  Supports address when precise (Must be precise) event=0xcd,period=100003,umask=1,ldlat=0x4  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise (Must be precise) mem_trans_retired.load_latency_gt_512 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles  Supports address when precise (Must be precise) event=0xcd,period=101,umask=1,ldlat=0x200  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise (Must be precise) mem_trans_retired.load_latency_gt_64 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles  Supports address when precise (Must be precise) event=0xcd,period=2003,umask=1,ldlat=0x40  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise (Must be precise) mem_trans_retired.load_latency_gt_8 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles  Supports address when precise (Must be precise) event=0xcd,period=50021,umask=1,ldlat=0x8  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise (Must be precise) ocr.all_data_rd.l3_miss.any_snoop memory OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000491  00     ocr.all_data_rd.l3_miss.hitm_other_core memory OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000491  00     ocr.all_data_rd.l3_miss.hit_other_core_fwd memory OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000491  00     ocr.all_data_rd.l3_miss.hit_other_core_no_fwd memory OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000491  00     ocr.all_data_rd.l3_miss.no_snoop_needed memory OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000491  00     ocr.all_data_rd.l3_miss.remote_hitm memory OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00491  00     ocr.all_data_rd.l3_miss.remote_hit_forward memory OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00491  00     ocr.all_data_rd.l3_miss.snoop_miss memory OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000491  00     ocr.all_data_rd.l3_miss.snoop_none memory OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000491  00     ocr.all_data_rd.l3_miss_local_dram.any_snoop memory OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP  OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000491  00     ocr.all_data_rd.l3_miss_local_dram.hitm_other_core memory OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE  OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000491  00     ocr.all_data_rd.l3_miss_local_dram.hit_other_core_fwd memory OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000491  00     ocr.all_data_rd.l3_miss_local_dram.hit_other_core_no_fwd memory OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000491  00     ocr.all_data_rd.l3_miss_local_dram.no_snoop_needed memory OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED  OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000491  00     ocr.all_data_rd.l3_miss_local_dram.snoop_miss memory OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204000491  00     ocr.all_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000491  00     ocr.all_data_rd.l3_miss_local_dram.snoop_none memory OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84000491  00     ocr.all_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800491  00     ocr.all_data_rd.l3_miss_remote_hop1_dram.any_snoop memory OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP  OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000491  00     ocr.all_data_rd.l3_miss_remote_hop1_dram.hitm_other_core memory OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE  OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000491  00     ocr.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000491  00     ocr.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000491  00     ocr.all_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED  OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000491  00     ocr.all_data_rd.l3_miss_remote_hop1_dram.snoop_miss memory OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210000491  00     ocr.all_data_rd.l3_miss_remote_hop1_dram.snoop_none memory OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90000491  00     ocr.all_pf_data_rd.l3_miss.any_snoop memory OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000490  00     ocr.all_pf_data_rd.l3_miss.hitm_other_core memory OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000490  00     ocr.all_pf_data_rd.l3_miss.hit_other_core_fwd memory OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000490  00     ocr.all_pf_data_rd.l3_miss.hit_other_core_no_fwd memory OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000490  00     ocr.all_pf_data_rd.l3_miss.no_snoop_needed memory OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000490  00     ocr.all_pf_data_rd.l3_miss.remote_hitm memory OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00490  00     ocr.all_pf_data_rd.l3_miss.remote_hit_forward memory OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00490  00     ocr.all_pf_data_rd.l3_miss.snoop_miss memory OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000490  00     ocr.all_pf_data_rd.l3_miss.snoop_none memory OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000490  00     ocr.all_pf_data_rd.l3_miss_local_dram.any_snoop memory OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP  OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000490  00     ocr.all_pf_data_rd.l3_miss_local_dram.hitm_other_core memory OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE  OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000490  00     ocr.all_pf_data_rd.l3_miss_local_dram.hit_other_core_fwd memory OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000490  00     ocr.all_pf_data_rd.l3_miss_local_dram.hit_other_core_no_fwd memory OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000490  00     ocr.all_pf_data_rd.l3_miss_local_dram.no_snoop_needed memory OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED  OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000490  00     ocr.all_pf_data_rd.l3_miss_local_dram.snoop_miss memory OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204000490  00     ocr.all_pf_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000490  00     ocr.all_pf_data_rd.l3_miss_local_dram.snoop_none memory OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84000490  00     ocr.all_pf_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800490  00     ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.any_snoop memory OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP  OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000490  00     ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.hitm_other_core memory OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE  OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000490  00     ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000490  00     ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000490  00     ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED  OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000490  00     ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_miss memory OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210000490  00     ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_none memory OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90000490  00     ocr.all_pf_rfo.l3_miss.any_snoop memory OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000120  00     ocr.all_pf_rfo.l3_miss.hitm_other_core memory OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000120  00     ocr.all_pf_rfo.l3_miss.hit_other_core_fwd memory OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000120  00     ocr.all_pf_rfo.l3_miss.hit_other_core_no_fwd memory OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000120  00     ocr.all_pf_rfo.l3_miss.no_snoop_needed memory OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000120  00     ocr.all_pf_rfo.l3_miss.remote_hitm memory OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00120  00     ocr.all_pf_rfo.l3_miss.remote_hit_forward memory OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00120  00     ocr.all_pf_rfo.l3_miss.snoop_miss memory OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000120  00     ocr.all_pf_rfo.l3_miss.snoop_none memory OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000120  00     ocr.all_pf_rfo.l3_miss_local_dram.any_snoop memory OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP  OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000120  00     ocr.all_pf_rfo.l3_miss_local_dram.hitm_other_core memory OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE  OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000120  00     ocr.all_pf_rfo.l3_miss_local_dram.hit_other_core_fwd memory OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000120  00     ocr.all_pf_rfo.l3_miss_local_dram.hit_other_core_no_fwd memory OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000120  00     ocr.all_pf_rfo.l3_miss_local_dram.no_snoop_needed memory OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED  OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000120  00     ocr.all_pf_rfo.l3_miss_local_dram.snoop_miss memory OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204000120  00     ocr.all_pf_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000120  00     ocr.all_pf_rfo.l3_miss_local_dram.snoop_none memory OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84000120  00     ocr.all_pf_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800120  00     ocr.all_pf_rfo.l3_miss_remote_hop1_dram.any_snoop memory OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP  OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000120  00     ocr.all_pf_rfo.l3_miss_remote_hop1_dram.hitm_other_core memory OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE  OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000120  00     ocr.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd memory OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000120  00     ocr.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000120  00     ocr.all_pf_rfo.l3_miss_remote_hop1_dram.no_snoop_needed memory OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED  OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000120  00     ocr.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_miss memory OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210000120  00     ocr.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_none memory OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90000120  00     ocr.all_reads.l3_miss.any_snoop memory OCR.ALL_READS.L3_MISS.ANY_SNOOP OCR.ALL_READS.L3_MISS.ANY_SNOOP OCR.ALL_READS.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC0007F7  00     ocr.all_reads.l3_miss.hitm_other_core memory OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C0007F7  00     ocr.all_reads.l3_miss.hit_other_core_fwd memory OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C0007F7  00     ocr.all_reads.l3_miss.hit_other_core_no_fwd memory OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C0007F7  00     ocr.all_reads.l3_miss.no_snoop_needed memory OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C0007F7  00     ocr.all_reads.l3_miss.remote_hitm memory OCR.ALL_READS.L3_MISS.REMOTE_HITM OCR.ALL_READS.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC007F7  00     ocr.all_reads.l3_miss.remote_hit_forward memory OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC007F7  00     ocr.all_reads.l3_miss.snoop_miss memory OCR.ALL_READS.L3_MISS.SNOOP_MISS OCR.ALL_READS.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C0007F7  00     ocr.all_reads.l3_miss.snoop_none memory OCR.ALL_READS.L3_MISS.SNOOP_NONE OCR.ALL_READS.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC0007F7  00     ocr.all_reads.l3_miss_local_dram.any_snoop memory OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP  OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F840007F7  00     ocr.all_reads.l3_miss_local_dram.hitm_other_core memory OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE  OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10040007F7  00     ocr.all_reads.l3_miss_local_dram.hit_other_core_fwd memory OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8040007F7  00     ocr.all_reads.l3_miss_local_dram.hit_other_core_no_fwd memory OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4040007F7  00     ocr.all_reads.l3_miss_local_dram.no_snoop_needed memory OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED  OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1040007F7  00     ocr.all_reads.l3_miss_local_dram.snoop_miss memory OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2040007F7  00     ocr.all_reads.l3_miss_local_dram.snoop_miss_or_no_fwd memory OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x6040007F7  00     ocr.all_reads.l3_miss_local_dram.snoop_none memory OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x840007F7  00     ocr.all_reads.l3_miss_remote_dram.snoop_miss_or_no_fwd memory OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B8007F7  00     ocr.all_reads.l3_miss_remote_hop1_dram.any_snoop memory OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP  OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F900007F7  00     ocr.all_reads.l3_miss_remote_hop1_dram.hitm_other_core memory OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE  OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10100007F7  00     ocr.all_reads.l3_miss_remote_hop1_dram.hit_other_core_fwd memory OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8100007F7  00     ocr.all_reads.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4100007F7  00     ocr.all_reads.l3_miss_remote_hop1_dram.no_snoop_needed memory OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED  OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1100007F7  00     ocr.all_reads.l3_miss_remote_hop1_dram.snoop_miss memory OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2100007F7  00     ocr.all_reads.l3_miss_remote_hop1_dram.snoop_none memory OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x900007F7  00     ocr.all_rfo.l3_miss.any_snoop memory OCR.ALL_RFO.L3_MISS.ANY_SNOOP OCR.ALL_RFO.L3_MISS.ANY_SNOOP OCR.ALL_RFO.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000122  00     ocr.all_rfo.l3_miss.hitm_other_core memory OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000122  00     ocr.all_rfo.l3_miss.hit_other_core_fwd memory OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000122  00     ocr.all_rfo.l3_miss.hit_other_core_no_fwd memory OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000122  00     ocr.all_rfo.l3_miss.no_snoop_needed memory OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000122  00     ocr.all_rfo.l3_miss.remote_hitm memory OCR.ALL_RFO.L3_MISS.REMOTE_HITM OCR.ALL_RFO.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00122  00     ocr.all_rfo.l3_miss.remote_hit_forward memory OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00122  00     ocr.all_rfo.l3_miss.snoop_miss memory OCR.ALL_RFO.L3_MISS.SNOOP_MISS OCR.ALL_RFO.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000122  00     ocr.all_rfo.l3_miss.snoop_none memory OCR.ALL_RFO.L3_MISS.SNOOP_NONE OCR.ALL_RFO.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000122  00     ocr.all_rfo.l3_miss_local_dram.any_snoop memory OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP  OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000122  00     ocr.all_rfo.l3_miss_local_dram.hitm_other_core memory OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE  OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000122  00     ocr.all_rfo.l3_miss_local_dram.hit_other_core_fwd memory OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000122  00     ocr.all_rfo.l3_miss_local_dram.hit_other_core_no_fwd memory OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000122  00     ocr.all_rfo.l3_miss_local_dram.no_snoop_needed memory OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED  OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000122  00     ocr.all_rfo.l3_miss_local_dram.snoop_miss memory OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204000122  00     ocr.all_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000122  00     ocr.all_rfo.l3_miss_local_dram.snoop_none memory OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84000122  00     ocr.all_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800122  00     ocr.all_rfo.l3_miss_remote_hop1_dram.any_snoop memory OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP  OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000122  00     ocr.all_rfo.l3_miss_remote_hop1_dram.hitm_other_core memory OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE  OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000122  00     ocr.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd memory OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000122  00     ocr.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000122  00     ocr.all_rfo.l3_miss_remote_hop1_dram.no_snoop_needed memory OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED  OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000122  00     ocr.all_rfo.l3_miss_remote_hop1_dram.snoop_miss memory OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210000122  00     ocr.all_rfo.l3_miss_remote_hop1_dram.snoop_none memory OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90000122  00     ocr.demand_code_rd.l3_miss.any_snoop memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000004  00     ocr.demand_code_rd.l3_miss.hitm_other_core memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000004  00     ocr.demand_code_rd.l3_miss.hit_other_core_fwd memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000004  00     ocr.demand_code_rd.l3_miss.hit_other_core_no_fwd memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000004  00     ocr.demand_code_rd.l3_miss.no_snoop_needed memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000004  00     ocr.demand_code_rd.l3_miss.remote_hitm memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00004  00     ocr.demand_code_rd.l3_miss.remote_hit_forward memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00004  00     ocr.demand_code_rd.l3_miss.snoop_miss memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000004  00     ocr.demand_code_rd.l3_miss.snoop_none memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000004  00     ocr.demand_code_rd.l3_miss_local_dram.any_snoop memory Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000004  00     ocr.demand_code_rd.l3_miss_local_dram.hitm_other_core memory Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000004  00     ocr.demand_code_rd.l3_miss_local_dram.hit_other_core_fwd memory Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000004  00     ocr.demand_code_rd.l3_miss_local_dram.hit_other_core_no_fwd memory Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000004  00     ocr.demand_code_rd.l3_miss_local_dram.no_snoop_needed memory Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000004  00     ocr.demand_code_rd.l3_miss_local_dram.snoop_miss memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x204000004  00     ocr.demand_code_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000004  00     ocr.demand_code_rd.l3_miss_local_dram.snoop_none memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x84000004  00     ocr.demand_code_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800004  00     ocr.demand_code_rd.l3_miss_remote_hop1_dram.any_snoop memory Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000004  00     ocr.demand_code_rd.l3_miss_remote_hop1_dram.hitm_other_core memory Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000004  00     ocr.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000004  00     ocr.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000004  00     ocr.demand_code_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000004  00     ocr.demand_code_rd.l3_miss_remote_hop1_dram.snoop_miss memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x210000004  00     ocr.demand_code_rd.l3_miss_remote_hop1_dram.snoop_none memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x90000004  00     ocr.demand_data_rd.l3_miss.any_snoop memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000001  00     ocr.demand_data_rd.l3_miss.hitm_other_core memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000001  00     ocr.demand_data_rd.l3_miss.hit_other_core_fwd memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000001  00     ocr.demand_data_rd.l3_miss.hit_other_core_no_fwd memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000001  00     ocr.demand_data_rd.l3_miss.no_snoop_needed memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000001  00     ocr.demand_data_rd.l3_miss.remote_hitm memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00001  00     ocr.demand_data_rd.l3_miss.remote_hit_forward memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00001  00     ocr.demand_data_rd.l3_miss.snoop_miss memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000001  00     ocr.demand_data_rd.l3_miss.snoop_none memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000001  00     ocr.demand_data_rd.l3_miss_local_dram.any_snoop memory Counts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000001  00     ocr.demand_data_rd.l3_miss_local_dram.hitm_other_core memory Counts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000001  00     ocr.demand_data_rd.l3_miss_local_dram.hit_other_core_fwd memory Counts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000001  00     ocr.demand_data_rd.l3_miss_local_dram.hit_other_core_no_fwd memory Counts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000001  00     ocr.demand_data_rd.l3_miss_local_dram.no_snoop_needed memory Counts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000001  00     ocr.demand_data_rd.l3_miss_local_dram.snoop_miss memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x204000001  00     ocr.demand_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000001  00     ocr.demand_data_rd.l3_miss_local_dram.snoop_none memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x84000001  00     ocr.demand_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800001  00     ocr.demand_data_rd.l3_miss_remote_hop1_dram.any_snoop memory Counts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000001  00     ocr.demand_data_rd.l3_miss_remote_hop1_dram.hitm_other_core memory Counts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000001  00     ocr.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory Counts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000001  00     ocr.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory Counts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000001  00     ocr.demand_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory Counts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000001  00     ocr.demand_data_rd.l3_miss_remote_hop1_dram.snoop_miss memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x210000001  00     ocr.demand_data_rd.l3_miss_remote_hop1_dram.snoop_none memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x90000001  00     ocr.demand_rfo.l3_miss.any_snoop memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000002  00     ocr.demand_rfo.l3_miss.hitm_other_core memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000002  00     ocr.demand_rfo.l3_miss.hit_other_core_fwd memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000002  00     ocr.demand_rfo.l3_miss.hit_other_core_no_fwd memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000002  00     ocr.demand_rfo.l3_miss.no_snoop_needed memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000002  00     ocr.demand_rfo.l3_miss.remote_hitm memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00002  00     ocr.demand_rfo.l3_miss.remote_hit_forward memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00002  00     ocr.demand_rfo.l3_miss.snoop_miss memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000002  00     ocr.demand_rfo.l3_miss.snoop_none memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000002  00     ocr.demand_rfo.l3_miss_local_dram.any_snoop memory Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000002  00     ocr.demand_rfo.l3_miss_local_dram.hitm_other_core memory Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000002  00     ocr.demand_rfo.l3_miss_local_dram.hit_other_core_fwd memory Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000002  00     ocr.demand_rfo.l3_miss_local_dram.hit_other_core_no_fwd memory Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000002  00     ocr.demand_rfo.l3_miss_local_dram.no_snoop_needed memory Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000002  00     ocr.demand_rfo.l3_miss_local_dram.snoop_miss memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x204000002  00     ocr.demand_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000002  00     ocr.demand_rfo.l3_miss_local_dram.snoop_none memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x84000002  00     ocr.demand_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800002  00     ocr.demand_rfo.l3_miss_remote_hop1_dram.any_snoop memory Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000002  00     ocr.demand_rfo.l3_miss_remote_hop1_dram.hitm_other_core memory Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000002  00     ocr.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd memory Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000002  00     ocr.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000002  00     ocr.demand_rfo.l3_miss_remote_hop1_dram.no_snoop_needed memory Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000002  00     ocr.demand_rfo.l3_miss_remote_hop1_dram.snoop_miss memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x210000002  00     ocr.demand_rfo.l3_miss_remote_hop1_dram.snoop_none memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x90000002  00     ocr.other.l3_miss.any_snoop memory Counts any other requests OCR.OTHER.L3_MISS.ANY_SNOOP OCR.OTHER.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC008000  00     ocr.other.l3_miss.hitm_other_core memory Counts any other requests OCR.OTHER.L3_MISS.HITM_OTHER_CORE OCR.OTHER.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C008000  00     ocr.other.l3_miss.hit_other_core_fwd memory Counts any other requests OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C008000  00     ocr.other.l3_miss.hit_other_core_no_fwd memory Counts any other requests OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C008000  00     ocr.other.l3_miss.no_snoop_needed memory Counts any other requests OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C008000  00     ocr.other.l3_miss.remote_hitm memory Counts any other requests OCR.OTHER.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC08000  00     ocr.other.l3_miss.remote_hit_forward memory Counts any other requests OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC08000  00     ocr.other.l3_miss.snoop_miss memory Counts any other requests OCR.OTHER.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C008000  00     ocr.other.l3_miss.snoop_none memory Counts any other requests OCR.OTHER.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC008000  00     ocr.other.l3_miss_local_dram.any_snoop memory Counts any other requests  OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84008000  00     ocr.other.l3_miss_local_dram.hitm_other_core memory Counts any other requests  OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004008000  00     ocr.other.l3_miss_local_dram.hit_other_core_fwd memory Counts any other requests  OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804008000  00     ocr.other.l3_miss_local_dram.hit_other_core_no_fwd memory Counts any other requests  OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404008000  00     ocr.other.l3_miss_local_dram.no_snoop_needed memory Counts any other requests  OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104008000  00     ocr.other.l3_miss_local_dram.snoop_miss memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x204008000  00     ocr.other.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604008000  00     ocr.other.l3_miss_local_dram.snoop_none memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x84008000  00     ocr.other.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts any other requests OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B808000  00     ocr.other.l3_miss_remote_hop1_dram.any_snoop memory Counts any other requests  OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90008000  00     ocr.other.l3_miss_remote_hop1_dram.hitm_other_core memory Counts any other requests  OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010008000  00     ocr.other.l3_miss_remote_hop1_dram.hit_other_core_fwd memory Counts any other requests  OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810008000  00     ocr.other.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory Counts any other requests  OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410008000  00     ocr.other.l3_miss_remote_hop1_dram.no_snoop_needed memory Counts any other requests  OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110008000  00     ocr.other.l3_miss_remote_hop1_dram.snoop_miss memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x210008000  00     ocr.other.l3_miss_remote_hop1_dram.snoop_none memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x90008000  00     ocr.pf_l1d_and_sw.l3_miss.any_snoop memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000400  00     ocr.pf_l1d_and_sw.l3_miss.hitm_other_core memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000400  00     ocr.pf_l1d_and_sw.l3_miss.hit_other_core_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000400  00     ocr.pf_l1d_and_sw.l3_miss.hit_other_core_no_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000400  00     ocr.pf_l1d_and_sw.l3_miss.no_snoop_needed memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000400  00     ocr.pf_l1d_and_sw.l3_miss.remote_hitm memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00400  00     ocr.pf_l1d_and_sw.l3_miss.remote_hit_forward memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00400  00     ocr.pf_l1d_and_sw.l3_miss.snoop_miss memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000400  00     ocr.pf_l1d_and_sw.l3_miss.snoop_none memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000400  00     ocr.pf_l1d_and_sw.l3_miss_local_dram.any_snoop memory Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000400  00     ocr.pf_l1d_and_sw.l3_miss_local_dram.hitm_other_core memory Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000400  00     ocr.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000400  00     ocr.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_no_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000400  00     ocr.pf_l1d_and_sw.l3_miss_local_dram.no_snoop_needed memory Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000400  00     ocr.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss memory Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=1,offcore_rsp=0x204000400  00     ocr.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000400  00     ocr.pf_l1d_and_sw.l3_miss_local_dram.snoop_none memory Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=1,offcore_rsp=0x84000400  00     ocr.pf_l1d_and_sw.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800400  00     ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.any_snoop memory Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000400  00     ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hitm_other_core memory Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000400  00     ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000400  00     ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000400  00     ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.no_snoop_needed memory Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000400  00     ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_miss memory Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=1,offcore_rsp=0x210000400  00     ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_none memory Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=1,offcore_rsp=0x90000400  00     ocr.pf_l2_data_rd.l3_miss.any_snoop memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000010  00     ocr.pf_l2_data_rd.l3_miss.hitm_other_core memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000010  00     ocr.pf_l2_data_rd.l3_miss.hit_other_core_fwd memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000010  00     ocr.pf_l2_data_rd.l3_miss.hit_other_core_no_fwd memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000010  00     ocr.pf_l2_data_rd.l3_miss.no_snoop_needed memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000010  00     ocr.pf_l2_data_rd.l3_miss.remote_hitm memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00010  00     ocr.pf_l2_data_rd.l3_miss.remote_hit_forward memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00010  00     ocr.pf_l2_data_rd.l3_miss.snoop_miss memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000010  00     ocr.pf_l2_data_rd.l3_miss.snoop_none memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000010  00     ocr.pf_l2_data_rd.l3_miss_local_dram.any_snoop memory Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000010  00     ocr.pf_l2_data_rd.l3_miss_local_dram.hitm_other_core memory Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000010  00     ocr.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_fwd memory Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000010  00     ocr.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_no_fwd memory Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000010  00     ocr.pf_l2_data_rd.l3_miss_local_dram.no_snoop_needed memory Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000010  00     ocr.pf_l2_data_rd.l3_miss_local_dram.snoop_miss memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x204000010  00     ocr.pf_l2_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000010  00     ocr.pf_l2_data_rd.l3_miss_local_dram.snoop_none memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x84000010  00     ocr.pf_l2_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800010  00     ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.any_snoop memory Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000010  00     ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.hitm_other_core memory Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000010  00     ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000010  00     ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000010  00     ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000010  00     ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_miss memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x210000010  00     ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_none memory Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x90000010  00     ocr.pf_l2_rfo.l3_miss.any_snoop memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000020  00     ocr.pf_l2_rfo.l3_miss.hitm_other_core memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000020  00     ocr.pf_l2_rfo.l3_miss.hit_other_core_fwd memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000020  00     ocr.pf_l2_rfo.l3_miss.hit_other_core_no_fwd memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000020  00     ocr.pf_l2_rfo.l3_miss.no_snoop_needed memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000020  00     ocr.pf_l2_rfo.l3_miss.remote_hitm memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00020  00     ocr.pf_l2_rfo.l3_miss.remote_hit_forward memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00020  00     ocr.pf_l2_rfo.l3_miss.snoop_miss memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000020  00     ocr.pf_l2_rfo.l3_miss.snoop_none memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000020  00     ocr.pf_l2_rfo.l3_miss_local_dram.any_snoop memory Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000020  00     ocr.pf_l2_rfo.l3_miss_local_dram.hitm_other_core memory Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000020  00     ocr.pf_l2_rfo.l3_miss_local_dram.hit_other_core_fwd memory Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000020  00     ocr.pf_l2_rfo.l3_miss_local_dram.hit_other_core_no_fwd memory Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000020  00     ocr.pf_l2_rfo.l3_miss_local_dram.no_snoop_needed memory Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000020  00     ocr.pf_l2_rfo.l3_miss_local_dram.snoop_miss memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x204000020  00     ocr.pf_l2_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000020  00     ocr.pf_l2_rfo.l3_miss_local_dram.snoop_none memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x84000020  00     ocr.pf_l2_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800020  00     ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.any_snoop memory Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000020  00     ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.hitm_other_core memory Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000020  00     ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd memory Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000020  00     ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000020  00     ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.no_snoop_needed memory Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000020  00     ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_miss memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x210000020  00     ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_none memory Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x90000020  00     ocr.pf_l3_data_rd.l3_miss.any_snoop memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000080  00     ocr.pf_l3_data_rd.l3_miss.hitm_other_core memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000080  00     ocr.pf_l3_data_rd.l3_miss.hit_other_core_fwd memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000080  00     ocr.pf_l3_data_rd.l3_miss.hit_other_core_no_fwd memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000080  00     ocr.pf_l3_data_rd.l3_miss.no_snoop_needed memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000080  00     ocr.pf_l3_data_rd.l3_miss.remote_hitm memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00080  00     ocr.pf_l3_data_rd.l3_miss.remote_hit_forward memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00080  00     ocr.pf_l3_data_rd.l3_miss.snoop_miss memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000080  00     ocr.pf_l3_data_rd.l3_miss.snoop_none memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000080  00     ocr.pf_l3_data_rd.l3_miss_local_dram.any_snoop memory Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000080  00     ocr.pf_l3_data_rd.l3_miss_local_dram.hitm_other_core memory Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000080  00     ocr.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_fwd memory Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000080  00     ocr.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_no_fwd memory Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000080  00     ocr.pf_l3_data_rd.l3_miss_local_dram.no_snoop_needed memory Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000080  00     ocr.pf_l3_data_rd.l3_miss_local_dram.snoop_miss memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x204000080  00     ocr.pf_l3_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000080  00     ocr.pf_l3_data_rd.l3_miss_local_dram.snoop_none memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x84000080  00     ocr.pf_l3_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800080  00     ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.any_snoop memory Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000080  00     ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.hitm_other_core memory Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000080  00     ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000080  00     ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000080  00     ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000080  00     ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_miss memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x210000080  00     ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_none memory Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x90000080  00     ocr.pf_l3_rfo.l3_miss.any_snoop memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000100  00     ocr.pf_l3_rfo.l3_miss.hitm_other_core memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000100  00     ocr.pf_l3_rfo.l3_miss.hit_other_core_fwd memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000100  00     ocr.pf_l3_rfo.l3_miss.hit_other_core_no_fwd memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000100  00     ocr.pf_l3_rfo.l3_miss.no_snoop_needed memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000100  00     ocr.pf_l3_rfo.l3_miss.remote_hitm memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00100  00     ocr.pf_l3_rfo.l3_miss.remote_hit_forward memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00100  00     ocr.pf_l3_rfo.l3_miss.snoop_miss memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000100  00     ocr.pf_l3_rfo.l3_miss.snoop_none memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000100  00     ocr.pf_l3_rfo.l3_miss_local_dram.any_snoop memory Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000100  00     ocr.pf_l3_rfo.l3_miss_local_dram.hitm_other_core memory Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000100  00     ocr.pf_l3_rfo.l3_miss_local_dram.hit_other_core_fwd memory Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000100  00     ocr.pf_l3_rfo.l3_miss_local_dram.hit_other_core_no_fwd memory Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000100  00     ocr.pf_l3_rfo.l3_miss_local_dram.no_snoop_needed memory Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000100  00     ocr.pf_l3_rfo.l3_miss_local_dram.snoop_miss memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x204000100  00     ocr.pf_l3_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000100  00     ocr.pf_l3_rfo.l3_miss_local_dram.snoop_none memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x84000100  00     ocr.pf_l3_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800100  00     ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.any_snoop memory Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000100  00     ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.hitm_other_core memory Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000100  00     ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd memory Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000100  00     ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000100  00     ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.no_snoop_needed memory Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000100  00     ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_miss memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x210000100  00     ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_none memory Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x90000100  00     offcore_requests.l3_miss_demand_data_rd memory Demand Data Read requests who miss L3 cache event=0xb0,period=100003,umask=0x10  00     offcore_requests_outstanding.cycles_with_l3_miss_demand_data_rd memory Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ event=0x60,cmask=1,period=2000003,umask=0x10  00     offcore_requests_outstanding.l3_miss_demand_data_rd memory Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle event=0x60,period=2000003,umask=0x10  00     offcore_requests_outstanding.l3_miss_demand_data_rd_ge_6 memory Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ event=0x60,cmask=6,period=2000003,umask=0x10  00     offcore_response.all_data_rd.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000491  10     offcore_response.all_data_rd.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000491  10     offcore_response.all_data_rd.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000491  10     offcore_response.all_data_rd.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000491  10     offcore_response.all_data_rd.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000491  10     offcore_response.all_data_rd.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00491  10     offcore_response.all_data_rd.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00491  10     offcore_response.all_data_rd.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000491  10     offcore_response.all_data_rd.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000491  10     offcore_response.all_data_rd.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000491  10     offcore_response.all_data_rd.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000491  10     offcore_response.all_data_rd.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000491  10     offcore_response.all_data_rd.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000491  10     offcore_response.all_data_rd.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000491  10     offcore_response.all_data_rd.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204000491  10     offcore_response.all_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000491  10     offcore_response.all_data_rd.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84000491  10     offcore_response.all_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800491  10     offcore_response.all_data_rd.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000491  10     offcore_response.all_data_rd.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000491  10     offcore_response.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000491  10     offcore_response.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000491  10     offcore_response.all_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000491  10     offcore_response.all_data_rd.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210000491  10     offcore_response.all_data_rd.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90000491  10     offcore_response.all_pf_data_rd.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000490  10     offcore_response.all_pf_data_rd.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000490  10     offcore_response.all_pf_data_rd.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000490  10     offcore_response.all_pf_data_rd.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000490  10     offcore_response.all_pf_data_rd.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000490  10     offcore_response.all_pf_data_rd.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00490  10     offcore_response.all_pf_data_rd.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00490  10     offcore_response.all_pf_data_rd.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000490  10     offcore_response.all_pf_data_rd.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000490  10     offcore_response.all_pf_data_rd.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000490  10     offcore_response.all_pf_data_rd.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000490  10     offcore_response.all_pf_data_rd.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000490  10     offcore_response.all_pf_data_rd.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000490  10     offcore_response.all_pf_data_rd.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000490  10     offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204000490  10     offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000490  10     offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84000490  10     offcore_response.all_pf_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800490  10     offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000490  10     offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000490  10     offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000490  10     offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000490  10     offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000490  10     offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210000490  10     offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90000490  10     offcore_response.all_pf_rfo.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000120  10     offcore_response.all_pf_rfo.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000120  10     offcore_response.all_pf_rfo.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000120  10     offcore_response.all_pf_rfo.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000120  10     offcore_response.all_pf_rfo.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000120  10     offcore_response.all_pf_rfo.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00120  10     offcore_response.all_pf_rfo.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00120  10     offcore_response.all_pf_rfo.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000120  10     offcore_response.all_pf_rfo.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000120  10     offcore_response.all_pf_rfo.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000120  10     offcore_response.all_pf_rfo.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000120  10     offcore_response.all_pf_rfo.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000120  10     offcore_response.all_pf_rfo.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000120  10     offcore_response.all_pf_rfo.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000120  10     offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204000120  10     offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000120  10     offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84000120  10     offcore_response.all_pf_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800120  10     offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000120  10     offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000120  10     offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000120  10     offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000120  10     offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000120  10     offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210000120  10     offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90000120  10     offcore_response.all_reads.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC0007F7  10     offcore_response.all_reads.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C0007F7  10     offcore_response.all_reads.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C0007F7  10     offcore_response.all_reads.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C0007F7  10     offcore_response.all_reads.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C0007F7  10     offcore_response.all_reads.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC007F7  10     offcore_response.all_reads.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC007F7  10     offcore_response.all_reads.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C0007F7  10     offcore_response.all_reads.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC0007F7  10     offcore_response.all_reads.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F840007F7  10     offcore_response.all_reads.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10040007F7  10     offcore_response.all_reads.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8040007F7  10     offcore_response.all_reads.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4040007F7  10     offcore_response.all_reads.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1040007F7  10     offcore_response.all_reads.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2040007F7  10     offcore_response.all_reads.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x6040007F7  10     offcore_response.all_reads.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x840007F7  10     offcore_response.all_reads.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B8007F7  10     offcore_response.all_reads.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F900007F7  10     offcore_response.all_reads.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10100007F7  10     offcore_response.all_reads.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8100007F7  10     offcore_response.all_reads.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4100007F7  10     offcore_response.all_reads.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1100007F7  10     offcore_response.all_reads.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2100007F7  10     offcore_response.all_reads.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x900007F7  10     offcore_response.all_rfo.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000122  10     offcore_response.all_rfo.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000122  10     offcore_response.all_rfo.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000122  10     offcore_response.all_rfo.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000122  10     offcore_response.all_rfo.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000122  10     offcore_response.all_rfo.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00122  10     offcore_response.all_rfo.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00122  10     offcore_response.all_rfo.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000122  10     offcore_response.all_rfo.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000122  10     offcore_response.all_rfo.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000122  10     offcore_response.all_rfo.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000122  10     offcore_response.all_rfo.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000122  10     offcore_response.all_rfo.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000122  10     offcore_response.all_rfo.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000122  10     offcore_response.all_rfo.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204000122  10     offcore_response.all_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000122  10     offcore_response.all_rfo.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84000122  10     offcore_response.all_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800122  10     offcore_response.all_rfo.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000122  10     offcore_response.all_rfo.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000122  10     offcore_response.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000122  10     offcore_response.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000122  10     offcore_response.all_rfo.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000122  10     offcore_response.all_rfo.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210000122  10     offcore_response.all_rfo.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90000122  10     offcore_response.demand_code_rd.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000004  10     offcore_response.demand_code_rd.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000004  10     offcore_response.demand_code_rd.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000004  10     offcore_response.demand_code_rd.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000004  10     offcore_response.demand_code_rd.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000004  10     offcore_response.demand_code_rd.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00004  10     offcore_response.demand_code_rd.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00004  10     offcore_response.demand_code_rd.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000004  10     offcore_response.demand_code_rd.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000004  10     offcore_response.demand_code_rd.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000004  10     offcore_response.demand_code_rd.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000004  10     offcore_response.demand_code_rd.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000004  10     offcore_response.demand_code_rd.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000004  10     offcore_response.demand_code_rd.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000004  10     offcore_response.demand_code_rd.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204000004  10     offcore_response.demand_code_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000004  10     offcore_response.demand_code_rd.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84000004  10     offcore_response.demand_code_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800004  10     offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000004  10     offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000004  10     offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000004  10     offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000004  10     offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000004  10     offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210000004  10     offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90000004  10     offcore_response.demand_data_rd.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000001  10     offcore_response.demand_data_rd.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000001  10     offcore_response.demand_data_rd.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000001  10     offcore_response.demand_data_rd.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000001  10     offcore_response.demand_data_rd.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000001  10     offcore_response.demand_data_rd.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00001  10     offcore_response.demand_data_rd.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00001  10     offcore_response.demand_data_rd.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000001  10     offcore_response.demand_data_rd.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000001  10     offcore_response.demand_data_rd.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000001  10     offcore_response.demand_data_rd.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000001  10     offcore_response.demand_data_rd.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000001  10     offcore_response.demand_data_rd.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000001  10     offcore_response.demand_data_rd.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000001  10     offcore_response.demand_data_rd.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204000001  10     offcore_response.demand_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000001  10     offcore_response.demand_data_rd.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84000001  10     offcore_response.demand_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800001  10     offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000001  10     offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000001  10     offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000001  10     offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000001  10     offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000001  10     offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210000001  10     offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90000001  10     offcore_response.demand_rfo.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000002  10     offcore_response.demand_rfo.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000002  10     offcore_response.demand_rfo.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000002  10     offcore_response.demand_rfo.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000002  10     offcore_response.demand_rfo.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000002  10     offcore_response.demand_rfo.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00002  10     offcore_response.demand_rfo.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00002  10     offcore_response.demand_rfo.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000002  10     offcore_response.demand_rfo.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000002  10     offcore_response.demand_rfo.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000002  10     offcore_response.demand_rfo.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000002  10     offcore_response.demand_rfo.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000002  10     offcore_response.demand_rfo.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000002  10     offcore_response.demand_rfo.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000002  10     offcore_response.demand_rfo.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204000002  10     offcore_response.demand_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000002  10     offcore_response.demand_rfo.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84000002  10     offcore_response.demand_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800002  10     offcore_response.demand_rfo.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000002  10     offcore_response.demand_rfo.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000002  10     offcore_response.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000002  10     offcore_response.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000002  10     offcore_response.demand_rfo.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000002  10     offcore_response.demand_rfo.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210000002  10     offcore_response.demand_rfo.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90000002  10     offcore_response.other.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC008000  10     offcore_response.other.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C008000  10     offcore_response.other.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C008000  10     offcore_response.other.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C008000  10     offcore_response.other.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C008000  10     offcore_response.other.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC08000  10     offcore_response.other.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC08000  10     offcore_response.other.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C008000  10     offcore_response.other.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC008000  10     offcore_response.other.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84008000  10     offcore_response.other.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004008000  10     offcore_response.other.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804008000  10     offcore_response.other.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404008000  10     offcore_response.other.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104008000  10     offcore_response.other.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204008000  10     offcore_response.other.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604008000  10     offcore_response.other.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84008000  10     offcore_response.other.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B808000  10     offcore_response.other.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90008000  10     offcore_response.other.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010008000  10     offcore_response.other.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810008000  10     offcore_response.other.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410008000  10     offcore_response.other.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110008000  10     offcore_response.other.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210008000  10     offcore_response.other.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90008000  10     offcore_response.pf_l1d_and_sw.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000400  10     offcore_response.pf_l1d_and_sw.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000400  10     offcore_response.pf_l1d_and_sw.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000400  10     offcore_response.pf_l1d_and_sw.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000400  10     offcore_response.pf_l1d_and_sw.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000400  10     offcore_response.pf_l1d_and_sw.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00400  10     offcore_response.pf_l1d_and_sw.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00400  10     offcore_response.pf_l1d_and_sw.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000400  10     offcore_response.pf_l1d_and_sw.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000400  10     offcore_response.pf_l1d_and_sw.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000400  10     offcore_response.pf_l1d_and_sw.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000400  10     offcore_response.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000400  10     offcore_response.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000400  10     offcore_response.pf_l1d_and_sw.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000400  10     offcore_response.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204000400  10     offcore_response.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000400  10     offcore_response.pf_l1d_and_sw.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84000400  10     offcore_response.pf_l1d_and_sw.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800400  10     offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000400  10     offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000400  10     offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000400  10     offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000400  10     offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000400  10     offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210000400  10     offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90000400  10     offcore_response.pf_l2_data_rd.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000010  10     offcore_response.pf_l2_data_rd.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000010  10     offcore_response.pf_l2_data_rd.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000010  10     offcore_response.pf_l2_data_rd.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000010  10     offcore_response.pf_l2_data_rd.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000010  10     offcore_response.pf_l2_data_rd.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00010  10     offcore_response.pf_l2_data_rd.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00010  10     offcore_response.pf_l2_data_rd.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000010  10     offcore_response.pf_l2_data_rd.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000010  10     offcore_response.pf_l2_data_rd.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000010  10     offcore_response.pf_l2_data_rd.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000010  10     offcore_response.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000010  10     offcore_response.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000010  10     offcore_response.pf_l2_data_rd.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000010  10     offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204000010  10     offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000010  10     offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84000010  10     offcore_response.pf_l2_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800010  10     offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000010  10     offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000010  10     offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000010  10     offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000010  10     offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000010  10     offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210000010  10     offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90000010  10     offcore_response.pf_l2_rfo.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000020  10     offcore_response.pf_l2_rfo.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000020  10     offcore_response.pf_l2_rfo.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000020  10     offcore_response.pf_l2_rfo.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000020  10     offcore_response.pf_l2_rfo.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000020  10     offcore_response.pf_l2_rfo.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00020  10     offcore_response.pf_l2_rfo.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00020  10     offcore_response.pf_l2_rfo.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000020  10     offcore_response.pf_l2_rfo.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000020  10     offcore_response.pf_l2_rfo.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000020  10     offcore_response.pf_l2_rfo.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000020  10     offcore_response.pf_l2_rfo.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000020  10     offcore_response.pf_l2_rfo.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000020  10     offcore_response.pf_l2_rfo.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000020  10     offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204000020  10     offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000020  10     offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84000020  10     offcore_response.pf_l2_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800020  10     offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000020  10     offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000020  10     offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000020  10     offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000020  10     offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000020  10     offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210000020  10     offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90000020  10     offcore_response.pf_l3_data_rd.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000080  10     offcore_response.pf_l3_data_rd.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000080  10     offcore_response.pf_l3_data_rd.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000080  10     offcore_response.pf_l3_data_rd.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000080  10     offcore_response.pf_l3_data_rd.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000080  10     offcore_response.pf_l3_data_rd.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00080  10     offcore_response.pf_l3_data_rd.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00080  10     offcore_response.pf_l3_data_rd.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000080  10     offcore_response.pf_l3_data_rd.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000080  10     offcore_response.pf_l3_data_rd.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000080  10     offcore_response.pf_l3_data_rd.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000080  10     offcore_response.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000080  10     offcore_response.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000080  10     offcore_response.pf_l3_data_rd.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000080  10     offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204000080  10     offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000080  10     offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84000080  10     offcore_response.pf_l3_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800080  10     offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000080  10     offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000080  10     offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000080  10     offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000080  10     offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000080  10     offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210000080  10     offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90000080  10     offcore_response.pf_l3_rfo.l3_miss.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000100  10     offcore_response.pf_l3_rfo.l3_miss.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x103C000100  10     offcore_response.pf_l3_rfo.l3_miss.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x83C000100  10     offcore_response.pf_l3_rfo.l3_miss.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x43C000100  10     offcore_response.pf_l3_rfo.l3_miss.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x13C000100  10     offcore_response.pf_l3_rfo.l3_miss.remote_hitm memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00100  10     offcore_response.pf_l3_rfo.l3_miss.remote_hit_forward memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00100  10     offcore_response.pf_l3_rfo.l3_miss.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x23C000100  10     offcore_response.pf_l3_rfo.l3_miss.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0xBC000100  10     offcore_response.pf_l3_rfo.l3_miss_local_dram.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84000100  10     offcore_response.pf_l3_rfo.l3_miss_local_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000100  10     offcore_response.pf_l3_rfo.l3_miss_local_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x804000100  10     offcore_response.pf_l3_rfo.l3_miss_local_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x404000100  10     offcore_response.pf_l3_rfo.l3_miss_local_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x104000100  10     offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x204000100  10     offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x604000100  10     offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x84000100  10     offcore_response.pf_l3_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800100  10     offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.any_snoop memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F90000100  10     offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.hitm_other_core memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1010000100  10     offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x810000100  10     offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x410000100  10     offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.no_snoop_needed memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x110000100  10     offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_miss memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x210000100  10     offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_none memory This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x90000100  10     rtm_retired.aborted memory Number of times an RTM execution aborted due to any reasons (multiple categories may count as one) (Must be precise) event=0xc9,period=2000003,umask=4  00    Number of times RTM abort was triggered (Must be precise) rtm_retired.aborted_events memory Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt) event=0xc9,period=2000003,umask=0x80  00     rtm_retired.aborted_mem memory Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts) event=0xc9,period=2000003,umask=8  00     rtm_retired.aborted_memtype memory Number of times an RTM execution aborted due to incompatible memory type event=0xc9,period=2000003,umask=0x40  00     rtm_retired.aborted_timer memory Number of times an RTM execution aborted due to uncommon conditions event=0xc9,period=2000003,umask=0x10  00     rtm_retired.aborted_unfriendly memory Number of times an RTM execution aborted due to HLE-unfriendly instructions event=0xc9,period=2000003,umask=0x20  00     rtm_retired.commit memory Number of times an RTM execution successfully committed event=0xc9,period=2000003,umask=2  00    Number of times RTM commit succeeded rtm_retired.start memory Number of times an RTM execution started event=0xc9,period=2000003,umask=1  00    Number of times we entered an RTM region. Does not count nested transactions tx_exec.misc2 memory Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region event=0x5d,period=2000003,umask=2  00    Unfriendly TSX abort triggered by a vzeroupper instruction tx_mem.abort_capacity memory Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes event=0x54,period=2000003,umask=2  00     tx_mem.abort_conflict memory Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address event=0x54,period=2000003,umask=1  00    Number of times a TSX line had a cache conflict tx_mem.abort_hle_elision_buffer_mismatch memory Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer event=0x54,period=2000003,umask=0x10  00    Number of times a TSX Abort was triggered due to release/commit but data and address mismatch tx_mem.abort_hle_elision_buffer_not_empty memory Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero event=0x54,period=2000003,umask=8  00    Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty tx_mem.abort_hle_elision_buffer_unsupported_alignment memory Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer event=0x54,period=2000003,umask=0x20  00    Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer tx_mem.abort_hle_store_to_elided_lock memory Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer event=0x54,period=2000003,umask=4  00    Number of times a TSX Abort was triggered due to a non-release/commit store to lock tx_mem.hle_elision_buffer_full memory Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero event=0x54,period=2000003,umask=0x40  00    Number of times we could not allocate Lock Buffer core_power.lvl0_turbo_license other Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule event=0x28,period=200003,umask=7  00    Core cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes core_power.lvl1_turbo_license other Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule event=0x28,period=200003,umask=0x18  00    Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions core_power.lvl2_turbo_license other Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule event=0x28,period=200003,umask=0x20  00    Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchitecture).  This includes high current AVX 512-bit instructions core_power.throttle other Core cycles the core was throttled due to a pending power level request event=0x28,period=200003,umask=0x40  00    Core cycles the out-of-order engine was throttled due to a pending power level request hw_interrupts.received other Number of hardware interrupts received by the processor event=0xcb,period=203,umask=1  00    Counts the number of hardware interruptions received by the processor ocr.all_data_rd.any_response other OCR.ALL_DATA_RD.ANY_RESPONSE have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10491  00     ocr.all_data_rd.pmm_hit_local_pmm.any_snoop other OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400491  00     ocr.all_data_rd.pmm_hit_local_pmm.snoop_none other OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400491  00     ocr.all_data_rd.pmm_hit_local_pmm.snoop_not_needed other OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400491  00     ocr.all_data_rd.supplier_none.any_snoop other OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP  OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020491  00     ocr.all_data_rd.supplier_none.hitm_other_core other OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE  OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020491  00     ocr.all_data_rd.supplier_none.hit_other_core_fwd other OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD  OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020491  00     ocr.all_data_rd.supplier_none.hit_other_core_no_fwd other OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD  OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020491  00     ocr.all_data_rd.supplier_none.no_snoop_needed other OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED  OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020491  00     ocr.all_data_rd.supplier_none.snoop_miss other OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200020491  00     ocr.all_data_rd.supplier_none.snoop_none other OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80020491  00     ocr.all_pf_data_rd.any_response other OCR.ALL_PF_DATA_RD.ANY_RESPONSE have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10490  00     ocr.all_pf_data_rd.pmm_hit_local_pmm.any_snoop other OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400490  00     ocr.all_pf_data_rd.pmm_hit_local_pmm.snoop_none other OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400490  00     ocr.all_pf_data_rd.pmm_hit_local_pmm.snoop_not_needed other OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400490  00     ocr.all_pf_data_rd.supplier_none.any_snoop other OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP  OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020490  00     ocr.all_pf_data_rd.supplier_none.hitm_other_core other OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE  OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020490  00     ocr.all_pf_data_rd.supplier_none.hit_other_core_fwd other OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD  OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020490  00     ocr.all_pf_data_rd.supplier_none.hit_other_core_no_fwd other OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020490  00     ocr.all_pf_data_rd.supplier_none.no_snoop_needed other OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED  OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020490  00     ocr.all_pf_data_rd.supplier_none.snoop_miss other OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200020490  00     ocr.all_pf_data_rd.supplier_none.snoop_none other OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80020490  00     ocr.all_pf_rfo.any_response other OCR.ALL_PF_RFO.ANY_RESPONSE have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10120  00     ocr.all_pf_rfo.pmm_hit_local_pmm.any_snoop other OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400120  00     ocr.all_pf_rfo.pmm_hit_local_pmm.snoop_none other OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400120  00     ocr.all_pf_rfo.pmm_hit_local_pmm.snoop_not_needed other OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400120  00     ocr.all_pf_rfo.supplier_none.any_snoop other OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP  OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020120  00     ocr.all_pf_rfo.supplier_none.hitm_other_core other OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE  OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020120  00     ocr.all_pf_rfo.supplier_none.hit_other_core_fwd other OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD  OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020120  00     ocr.all_pf_rfo.supplier_none.hit_other_core_no_fwd other OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020120  00     ocr.all_pf_rfo.supplier_none.no_snoop_needed other OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED  OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020120  00     ocr.all_pf_rfo.supplier_none.snoop_miss other OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200020120  00     ocr.all_pf_rfo.supplier_none.snoop_none other OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80020120  00     ocr.all_reads.any_response other OCR.ALL_READS.ANY_RESPONSE have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x107F7  00     ocr.all_reads.pmm_hit_local_pmm.any_snoop other OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F804007F7  00     ocr.all_reads.pmm_hit_local_pmm.snoop_none other OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x804007F7  00     ocr.all_reads.pmm_hit_local_pmm.snoop_not_needed other OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1004007F7  00     ocr.all_reads.supplier_none.any_snoop other OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP  OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F800207F7  00     ocr.all_reads.supplier_none.hitm_other_core other OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE  OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x10000207F7  00     ocr.all_reads.supplier_none.hit_other_core_fwd other OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD  OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8000207F7  00     ocr.all_reads.supplier_none.hit_other_core_no_fwd other OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD  OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4000207F7  00     ocr.all_reads.supplier_none.no_snoop_needed other OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED  OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1000207F7  00     ocr.all_reads.supplier_none.snoop_miss other OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2000207F7  00     ocr.all_reads.supplier_none.snoop_none other OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x800207F7  00     ocr.all_rfo.any_response other OCR.ALL_RFO.ANY_RESPONSE have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10122  00     ocr.all_rfo.pmm_hit_local_pmm.any_snoop other OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400122  00     ocr.all_rfo.pmm_hit_local_pmm.snoop_none other OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400122  00     ocr.all_rfo.pmm_hit_local_pmm.snoop_not_needed other OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400122  00     ocr.all_rfo.supplier_none.any_snoop other OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP  OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020122  00     ocr.all_rfo.supplier_none.hitm_other_core other OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE  OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020122  00     ocr.all_rfo.supplier_none.hit_other_core_fwd other OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD  OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020122  00     ocr.all_rfo.supplier_none.hit_other_core_no_fwd other OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD  OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020122  00     ocr.all_rfo.supplier_none.no_snoop_needed other OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED  OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020122  00     ocr.all_rfo.supplier_none.snoop_miss other OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x200020122  00     ocr.all_rfo.supplier_none.snoop_none other OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80020122  00     ocr.other.any_response other Counts any other requests have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x18000  00     ocr.other.pmm_hit_local_pmm.any_snoop other Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80408000  00     ocr.other.pmm_hit_local_pmm.snoop_none other Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80408000  00     ocr.other.pmm_hit_local_pmm.snoop_not_needed other Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100408000  00     ocr.other.supplier_none.any_snoop other Counts any other requests  OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80028000  00     ocr.other.supplier_none.hitm_other_core other Counts any other requests  OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000028000  00     ocr.other.supplier_none.hit_other_core_fwd other Counts any other requests  OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800028000  00     ocr.other.supplier_none.hit_other_core_no_fwd other Counts any other requests  OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400028000  00     ocr.other.supplier_none.no_snoop_needed other Counts any other requests  OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100028000  00     ocr.other.supplier_none.snoop_miss other Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x200028000  00     ocr.other.supplier_none.snoop_none other Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x80028000  00     ocr.pf_l1d_and_sw.any_response other Counts L1 data cache hardware prefetch requests and software prefetch requests have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10400  00     ocr.pf_l1d_and_sw.pmm_hit_local_pmm.any_snoop other Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400400  00     ocr.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_none other Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400400  00     ocr.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_not_needed other Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400400  00     ocr.pf_l1d_and_sw.supplier_none.any_snoop other Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020400  00     ocr.pf_l1d_and_sw.supplier_none.hitm_other_core other Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020400  00     ocr.pf_l1d_and_sw.supplier_none.hit_other_core_fwd other Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020400  00     ocr.pf_l1d_and_sw.supplier_none.hit_other_core_no_fwd other Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020400  00     ocr.pf_l1d_and_sw.supplier_none.no_snoop_needed other Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020400  00     ocr.pf_l1d_and_sw.supplier_none.snoop_miss other Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=1,offcore_rsp=0x200020400  00     ocr.pf_l1d_and_sw.supplier_none.snoop_none other Counts L1 data cache hardware prefetch requests and software prefetch requests event=0xb7,period=100003,umask=1,offcore_rsp=0x80020400  00     ocr.pf_l2_data_rd.any_response other Counts prefetch (that bring data to L2) data reads have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10010  00     ocr.pf_l2_data_rd.pmm_hit_local_pmm.any_snoop other Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400010  00     ocr.pf_l2_data_rd.pmm_hit_local_pmm.snoop_none other Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400010  00     ocr.pf_l2_data_rd.pmm_hit_local_pmm.snoop_not_needed other Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400010  00     ocr.pf_l2_data_rd.supplier_none.any_snoop other Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020010  00     ocr.pf_l2_data_rd.supplier_none.hitm_other_core other Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020010  00     ocr.pf_l2_data_rd.supplier_none.hit_other_core_fwd other Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020010  00     ocr.pf_l2_data_rd.supplier_none.hit_other_core_no_fwd other Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020010  00     ocr.pf_l2_data_rd.supplier_none.no_snoop_needed other Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020010  00     ocr.pf_l2_data_rd.supplier_none.snoop_miss other Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200020010  00     ocr.pf_l2_data_rd.supplier_none.snoop_none other Counts prefetch (that bring data to L2) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80020010  00     ocr.pf_l2_rfo.any_response other Counts all prefetch (that bring data to L2) RFOs have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10020  00     ocr.pf_l2_rfo.pmm_hit_local_pmm.any_snoop other Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400020  00     ocr.pf_l2_rfo.pmm_hit_local_pmm.snoop_none other Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400020  00     ocr.pf_l2_rfo.pmm_hit_local_pmm.snoop_not_needed other Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400020  00     ocr.pf_l2_rfo.supplier_none.any_snoop other Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020020  00     ocr.pf_l2_rfo.supplier_none.hitm_other_core other Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020020  00     ocr.pf_l2_rfo.supplier_none.hit_other_core_fwd other Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020020  00     ocr.pf_l2_rfo.supplier_none.hit_other_core_no_fwd other Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020020  00     ocr.pf_l2_rfo.supplier_none.no_snoop_needed other Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020020  00     ocr.pf_l2_rfo.supplier_none.snoop_miss other Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x200020020  00     ocr.pf_l2_rfo.supplier_none.snoop_none other Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x80020020  00     ocr.pf_l3_data_rd.any_response other Counts all prefetch (that bring data to LLC only) data reads have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10080  00     ocr.pf_l3_data_rd.pmm_hit_local_pmm.any_snoop other Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400080  00     ocr.pf_l3_data_rd.pmm_hit_local_pmm.snoop_none other Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400080  00     ocr.pf_l3_data_rd.pmm_hit_local_pmm.snoop_not_needed other Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400080  00     ocr.pf_l3_data_rd.supplier_none.any_snoop other Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020080  00     ocr.pf_l3_data_rd.supplier_none.hitm_other_core other Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020080  00     ocr.pf_l3_data_rd.supplier_none.hit_other_core_fwd other Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020080  00     ocr.pf_l3_data_rd.supplier_none.hit_other_core_no_fwd other Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020080  00     ocr.pf_l3_data_rd.supplier_none.no_snoop_needed other Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020080  00     ocr.pf_l3_data_rd.supplier_none.snoop_miss other Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200020080  00     ocr.pf_l3_data_rd.supplier_none.snoop_none other Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80020080  00     ocr.pf_l3_rfo.any_response other Counts all prefetch (that bring data to LLC only) RFOs have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10100  00     ocr.pf_l3_rfo.pmm_hit_local_pmm.any_snoop other Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80400100  00     ocr.pf_l3_rfo.pmm_hit_local_pmm.snoop_none other Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=1,offcore_rsp=0x80400100  00     ocr.pf_l3_rfo.pmm_hit_local_pmm.snoop_not_needed other Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100400100  00     ocr.pf_l3_rfo.supplier_none.any_snoop other Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=1,offcore_rsp=0x3F80020100  00     ocr.pf_l3_rfo.supplier_none.hitm_other_core other Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020100  00     ocr.pf_l3_rfo.supplier_none.hit_other_core_fwd other Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x800020100  00     ocr.pf_l3_rfo.supplier_none.hit_other_core_no_fwd other Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x400020100  00     ocr.pf_l3_rfo.supplier_none.no_snoop_needed other Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x100020100  00     ocr.pf_l3_rfo.supplier_none.snoop_miss other Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x200020100  00     ocr.pf_l3_rfo.supplier_none.snoop_none other Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x80020100  00     arith.divider_active pipeline Cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations event=0x14,cmask=1,period=2000003,umask=1  00     br_inst_retired.all_branches pipeline All (macro) branch instructions retired  Spec update: SKL091 event=0xc4,period=400009  00    Counts all (macro) branch instructions retired  Spec update: SKL091 br_inst_retired.all_branches_pebs pipeline All (macro) branch instructions retired  Spec update: SKL091 (Must be precise) event=0xc4,period=400009,umask=4  00    This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired  Spec update: SKL091 (Must be precise) br_inst_retired.cond pipeline Conditional branch instructions retired. [This event is alias to BR_INST_RETIRED.CONDITIONAL]  Spec update: SKL091 event=0xc4,period=400009,umask=1  00    This event counts conditional branch instructions retired. [This event is alias to BR_INST_RETIRED.CONDITIONAL]  Spec update: SKL091 br_inst_retired.conditional pipeline Conditional branch instructions retired. [This event is alias to BR_INST_RETIRED.COND]  Spec update: SKL091 (Precise event) event=0xc4,period=400009,umask=1  00    This event counts conditional branch instructions retired. [This event is alias to BR_INST_RETIRED.COND]  Spec update: SKL091 (Precise event) br_inst_retired.cond_ntaken pipeline Not taken branch instructions retired  Spec update: SKL091 event=0xc4,period=400009,umask=0x10  00    This event counts not taken branch instructions retired  Spec update: SKL091 br_inst_retired.far_branch pipeline Far branch instructions retired  Spec update: SKL091 (Precise event) event=0xc4,period=100007,umask=0x40  00    This event counts far branch instructions retired  Spec update: SKL091 (Precise event) br_inst_retired.near_call pipeline Direct and indirect near call instructions retired  Spec update: SKL091 (Precise event) event=0xc4,period=100007,umask=2  00    This event counts both direct and indirect near call instructions retired  Spec update: SKL091 (Precise event) br_inst_retired.near_return pipeline Return instructions retired  Spec update: SKL091 (Precise event) event=0xc4,period=100007,umask=8  00    This event counts return instructions retired  Spec update: SKL091 (Precise event) br_inst_retired.near_taken pipeline Taken branch instructions retired  Spec update: SKL091 (Precise event) event=0xc4,period=400009,umask=0x20  00    This event counts taken branch instructions retired  Spec update: SKL091 (Precise event) br_inst_retired.not_taken pipeline Not taken branch instructions retired  Spec update: SKL091 event=0xc4,period=400009,umask=0x10  00    This event counts not taken branch instructions retired  Spec update: SKL091 br_misp_retired.all_branches pipeline All mispredicted macro branch instructions retired event=0xc5,period=400009  00    Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch.  When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path br_misp_retired.all_branches_pebs pipeline Mispredicted macro branch instructions retired (Must be precise) event=0xc5,period=400009,umask=4  00    This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired (Must be precise) br_misp_retired.near_call pipeline Mispredicted direct and indirect near call instructions retired (Precise event) event=0xc5,period=400009,umask=2  00    Counts both taken and not taken retired mispredicted direct and indirect near calls, including both register and memory indirect (Precise event) br_misp_retired.near_taken pipeline Number of near branch instructions retired that were mispredicted and taken (Precise event) event=0xc5,period=400009,umask=0x20  00     br_misp_retired.ret pipeline This event counts the number of mispredicted ret instructions retired. Non PEBS (Precise event) event=0xc5,period=100007,umask=8  00    This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired (Precise event) cpu_clk_thread_unhalted.one_thread_active pipeline Core crystal clock cycles when this thread is unhalted and the other thread is halted event=0x3c,period=25003,umask=2  00     cpu_clk_thread_unhalted.ref_xclk pipeline Core crystal clock cycles when the thread is unhalted event=0x3c,period=25003,umask=1  00     cpu_clk_thread_unhalted.ref_xclk_any pipeline Core crystal clock cycles when at least one thread on the physical core is unhalted event=0x3c,any=1,period=25003,umask=1  00     cpu_clk_unhalted.one_thread_active pipeline Core crystal clock cycles when this thread is unhalted and the other thread is halted event=0x3c,period=25003,umask=2  00     cpu_clk_unhalted.ref_tsc pipeline Reference cycles when the core is not in halt state event=0,period=2000003,umask=3  00    Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case cpu_clk_unhalted.ref_xclk pipeline Core crystal clock cycles when the thread is unhalted event=0x3c,period=25003,umask=1  00     cpu_clk_unhalted.ref_xclk_any pipeline Core crystal clock cycles when at least one thread on the physical core is unhalted event=0x3c,any=1,period=25003,umask=1  00     cpu_clk_unhalted.ring0_trans pipeline Counts when there is a transition from ring 1, 2 or 3 to ring 0 event=0x3c,cmask=1,edge=1,period=100007  00    Counts when the Current Privilege Level (CPL) transitions from ring 1, 2 or 3 to ring 0 (Kernel) cpu_clk_unhalted.thread pipeline Core cycles when the thread is not in halt state event=0x3c,period=2000003  00    Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events cycle_activity.cycles_mem_any pipeline Cycles while memory subsystem has an outstanding load event=0xa3,cmask=16,period=2000003,umask=0x10  00     cycle_activity.stalls_mem_any pipeline Execution stalls while memory subsystem has an outstanding load event=0xa3,cmask=20,period=2000003,umask=0x14  00     exe_activity.bound_on_stores pipeline Cycles where the Store Buffer was full and no outstanding load event=0xa6,period=2000003,umask=0x40  00     exe_activity.exe_bound_0_ports pipeline Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load event=0xa6,period=2000003,umask=1  00    Counts cycles during which no uops were executed on all ports and Reservation Station (RS) was not empty ild_stall.lcp pipeline Stalls caused by changing prefix length of the instruction. [This event is alias to DECODE.LCP] event=0x87,period=2000003,umask=1  00    Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to DECODE.LCP] inst_decoded.decoders pipeline Instruction decoders utilized in a cycle event=0x55,period=2000003,umask=1  00    Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions inst_retired.any pipeline Instructions retired from execution event=0xc0,period=2000003  00    Counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, Counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions inst_retired.any_p pipeline Number of instructions retired. General Counter - architectural event  Spec update: SKL091, SKL044 event=0xc0,period=2000003  00    Counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two)  Spec update: SKL091, SKL044 inst_retired.nop pipeline Number of all retired NOP instructions  Spec update: SKL091, SKL044 (Precise event) event=0xc0,period=2000003,umask=2  00     inst_retired.prec_dist pipeline Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution  Spec update: SKL091, SKL044 (Must be precise) event=0xc0,period=2000003,umask=1  00    A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled  Spec update: SKL091, SKL044 (Must be precise) inst_retired.total_cycles_ps pipeline Number of cycles using always true condition applied to  PEBS instructions retired event  Spec update: SKL091, SKL044 (Must be precise) event=0xc0,cmask=10,inv=1,period=2000003,umask=1  00    Number of cycles using an always true condition applied to  PEBS instructions retired event. (inst_ret< 16)  Spec update: SKL091, SKL044 (Must be precise) int_misc.clears_count pipeline Clears speculative count event=0xd,cmask=1,edge=1,period=2000003,umask=1  00    Counts the number of speculative clears due to any type of branch misprediction or machine clears int_misc.clear_resteer_cycles pipeline Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events event=0xd,period=2000003,umask=0x80  00     int_misc.recovery_cycles pipeline Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke) event=0xd,period=2000003,umask=1  00    Core cycles the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event int_misc.recovery_cycles_any pipeline Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke) event=0xd,any=1,period=2000003,umask=1  00     ld_blocks.no_sr pipeline The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use event=3,period=100003,umask=8  00     ld_blocks.store_forward pipeline Loads blocked due to overlapping with a preceding store that cannot be forwarded event=3,period=100003,umask=2  00    Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide ld_blocks_partial.address_alias pipeline False dependencies in MOB due to partial compare on address event=7,period=100003,umask=1  00    Counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased load_hit_pre.sw_pf pipeline Demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch event=0x4c,period=100003,umask=1  00    Counts all software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions lsd.cycles_4_uops pipeline Cycles 4 Uops delivered by the LSD, but didn't come from the decoder. [This event is alias to LSD.CYCLES_OK] event=0xa8,cmask=4,period=2000003,umask=1  00    Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector). [This event is alias to LSD.CYCLES_OK] lsd.cycles_ok pipeline Cycles 4 Uops delivered by the LSD, but didn't come from the decoder. [This event is alias to LSD.CYCLES_4_UOPS] event=0xa8,cmask=4,period=2000003,umask=1  00    Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector). [This event is alias to LSD.CYCLES_4_UOPS] lsd.uops pipeline Number of Uops delivered by the LSD event=0xa8,period=2000003,umask=1  00    Number of uops delivered to the back-end by the LSD(Loop Stream Detector) other_assists.any pipeline Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assists event=0xc1,period=100003,umask=0x3f  00     partial_rat_stalls.scoreboard pipeline Cycles where the pipeline is stalled due to serializing operations event=0x59,period=2000003,umask=1  00    This event counts cycles during which the microcode scoreboard stalls happen resource_stalls.any pipeline Resource-related stall cycles event=0xa2,period=2000003,umask=1  00    Counts resource-related stall cycles resource_stalls.sb pipeline Cycles stalled due to no store buffers available. (not including draining form sync) event=0xa2,period=2000003,umask=8  00    Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end rob_misc_events.lbr_inserts pipeline Increments whenever there is an update to the LBR array event=0xcc,period=2000003,umask=0x20  00    Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT rob_misc_events.pause_inst pipeline Number of retired PAUSE instructions (that do not end up with a VMExit to the VMM; TSX aborted Instructions may be counted). This event is not supported on first SKL and KBL products event=0xcc,period=2000003,umask=0x40  00     rs_events.empty_cycles pipeline Cycles when Reservation Station (RS) is empty for the thread event=0x5e,period=2000003,umask=1  00    Counts cycles during which the reservation station (RS) is empty for the thread.; Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues rs_events.empty_end pipeline Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues event=0x5e,cmask=1,edge=1,inv=1,period=2000003,umask=1  00    Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate front-end Latency Bound issues uops_dispatched_port.port_0 pipeline Cycles per thread when uops are executed in port 0 event=0xa1,period=2000003,umask=1  00    Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0 uops_dispatched_port.port_1 pipeline Cycles per thread when uops are executed in port 1 event=0xa1,period=2000003,umask=2  00    Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1 uops_dispatched_port.port_2 pipeline Cycles per thread when uops are executed in port 2 event=0xa1,period=2000003,umask=4  00    Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 2 uops_dispatched_port.port_3 pipeline Cycles per thread when uops are executed in port 3 event=0xa1,period=2000003,umask=8  00    Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 3 uops_dispatched_port.port_4 pipeline Cycles per thread when uops are executed in port 4 event=0xa1,period=2000003,umask=0x10  00    Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 4 uops_dispatched_port.port_5 pipeline Cycles per thread when uops are executed in port 5 event=0xa1,period=2000003,umask=0x20  00    Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5 uops_dispatched_port.port_6 pipeline Cycles per thread when uops are executed in port 6 event=0xa1,period=2000003,umask=0x40  00    Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6 uops_dispatched_port.port_7 pipeline Cycles per thread when uops are executed in port 7 event=0xa1,period=2000003,umask=0x80  00    Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 7 uops_executed.core_cycles_none pipeline Cycles with no micro-ops executed from any thread on physical core event=0xb1,cmask=1,inv=1,period=2000003,umask=2  00     uops_executed.stall_cycles pipeline Counts number of cycles no uops were dispatched to be executed on this thread event=0xb1,cmask=1,inv=1,period=2000003,umask=1  00    Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread uops_issued.any pipeline Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS) event=0xe,period=2000003,umask=1  00    Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS) uops_issued.stall_cycles pipeline Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread event=0xe,cmask=1,inv=1,period=2000003,umask=1  00    Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread uops_issued.vector_width_mismatch pipeline Uops inserted at issue-stage in order to preserve upper bits of vector registers event=0xe,period=2000003,umask=2  00    Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide uops_retired.macro_fused pipeline Number of macro-fused uops retired. (non precise) event=0xc2,period=2000003,umask=4  00    Counts the number of macro-fused uops retired. (non precise) uops_retired.retire_slots pipeline Retirement slots used event=0xc2,period=2000003,umask=2  00    Counts the retirement slots used uops_retired.stall_cycles pipeline Cycles without actually retired uops event=0xc2,cmask=1,inv=1,period=2000003,umask=2  00    This event counts cycles without actually retired uops uops_retired.total_cycles pipeline Cycles with less than 10 actually retired uops event=0xc2,cmask=16,inv=1,period=2000003,umask=2  00    Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event uncore_cha llc_misses.mmio_read uncore cache MMIO reads. Derived from unc_cha_tor_inserts.ia_miss event=0x35,umask=0x21,config1=0x40040e33  01    TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts llc_misses.mmio_write uncore cache MMIO writes. Derived from unc_cha_tor_inserts.ia_miss event=0x35,umask=0x21,config1=0x40041e33  01    TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts llc_misses.uncacheable uncore cache LLC misses - Uncacheable reads (from cpu). Derived from unc_cha_tor_inserts.ia_miss event=0x35,umask=0x21,config1=0x40e33  01    TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts llc_references.streaming_full uncore cache Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss event=0x35,umask=0x21,config1=0x41833  0164Bytes    TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts llc_references.streaming_partial uncore cache Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss event=0x35,umask=0x21,config1=0x41a33  0164Bytes    TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_ag0_ad_crd_acquired.tgr0 uncore cache CMS Agent0 AD Credits Acquired; For Transgress 0 event=0x80,umask=1  01    Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired.tgr1 uncore cache CMS Agent0 AD Credits Acquired; For Transgress 1 event=0x80,umask=2  01    Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired.tgr2 uncore cache CMS Agent0 AD Credits Acquired; For Transgress 2 event=0x80,umask=4  01    Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired.tgr3 uncore cache CMS Agent0 AD Credits Acquired; For Transgress 3 event=0x80,umask=8  01    Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired.tgr4 uncore cache CMS Agent0 AD Credits Acquired; For Transgress 4 event=0x80,umask=0x10  01    Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired.tgr5 uncore cache CMS Agent0 AD Credits Acquired; For Transgress 5 event=0x80,umask=0x20  01    Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy.tgr0 uncore cache CMS Agent0 AD Credits Occupancy; For Transgress 0 event=0x82,umask=1  01    Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy.tgr1 uncore cache CMS Agent0 AD Credits Occupancy; For Transgress 1 event=0x82,umask=2  01    Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy.tgr2 uncore cache CMS Agent0 AD Credits Occupancy; For Transgress 2 event=0x82,umask=4  01    Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy.tgr3 uncore cache CMS Agent0 AD Credits Occupancy; For Transgress 3 event=0x82,umask=8  01    Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy.tgr4 uncore cache CMS Agent0 AD Credits Occupancy; For Transgress 4 event=0x82,umask=0x10  01    Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy.tgr5 uncore cache CMS Agent0 AD Credits Occupancy; For Transgress 5 event=0x82,umask=0x20  01    Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired.tgr0 uncore cache CMS Agent0 BL Credits Acquired; For Transgress 0 event=0x88,umask=1  01    Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired.tgr1 uncore cache CMS Agent0 BL Credits Acquired; For Transgress 1 event=0x88,umask=2  01    Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired.tgr2 uncore cache CMS Agent0 BL Credits Acquired; For Transgress 2 event=0x88,umask=4  01    Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired.tgr3 uncore cache CMS Agent0 BL Credits Acquired; For Transgress 3 event=0x88,umask=8  01    Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired.tgr4 uncore cache CMS Agent0 BL Credits Acquired; For Transgress 4 event=0x88,umask=0x10  01    Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired.tgr5 uncore cache CMS Agent0 BL Credits Acquired; For Transgress 5 event=0x88,umask=0x20  01    Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy.tgr0 uncore cache CMS Agent0 BL Credits Occupancy; For Transgress 0 event=0x8a,umask=1  01    Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy.tgr1 uncore cache CMS Agent0 BL Credits Occupancy; For Transgress 1 event=0x8a,umask=2  01    Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy.tgr2 uncore cache CMS Agent0 BL Credits Occupancy; For Transgress 2 event=0x8a,umask=4  01    Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy.tgr3 uncore cache CMS Agent0 BL Credits Occupancy; For Transgress 3 event=0x8a,umask=8  01    Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy.tgr4 uncore cache CMS Agent0 BL Credits Occupancy; For Transgress 4 event=0x8a,umask=0x10  01    Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy.tgr5 uncore cache CMS Agent0 BL Credits Occupancy; For Transgress 5 event=0x8a,umask=0x20  01    Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired.tgr0 uncore cache CMS Agent1 AD Credits Acquired; For Transgress 0 event=0x84,umask=1  01    Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired.tgr1 uncore cache CMS Agent1 AD Credits Acquired; For Transgress 1 event=0x84,umask=2  01    Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired.tgr2 uncore cache CMS Agent1 AD Credits Acquired; For Transgress 2 event=0x84,umask=4  01    Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired.tgr3 uncore cache CMS Agent1 AD Credits Acquired; For Transgress 3 event=0x84,umask=8  01    Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired.tgr4 uncore cache CMS Agent1 AD Credits Acquired; For Transgress 4 event=0x84,umask=0x10  01    Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired.tgr5 uncore cache CMS Agent1 AD Credits Acquired; For Transgress 5 event=0x84,umask=0x20  01    Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy.tgr0 uncore cache CMS Agent1 AD Credits Occupancy; For Transgress 0 event=0x86,umask=1  01    Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy.tgr1 uncore cache CMS Agent1 AD Credits Occupancy; For Transgress 1 event=0x86,umask=2  01    Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy.tgr2 uncore cache CMS Agent1 AD Credits Occupancy; For Transgress 2 event=0x86,umask=4  01    Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy.tgr3 uncore cache CMS Agent1 AD Credits Occupancy; For Transgress 3 event=0x86,umask=8  01    Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy.tgr4 uncore cache CMS Agent1 AD Credits Occupancy; For Transgress 4 event=0x86,umask=0x10  01    Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy.tgr5 uncore cache CMS Agent1 AD Credits Occupancy; For Transgress 5 event=0x86,umask=0x20  01    Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy.tgr0 uncore cache CMS Agent1 BL Credits Occupancy; For Transgress 0 event=0x8e,umask=1  01    Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy.tgr1 uncore cache CMS Agent1 BL Credits Occupancy; For Transgress 1 event=0x8e,umask=2  01    Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy.tgr2 uncore cache CMS Agent1 BL Credits Occupancy; For Transgress 2 event=0x8e,umask=4  01    Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy.tgr3 uncore cache CMS Agent1 BL Credits Occupancy; For Transgress 3 event=0x8e,umask=8  01    Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy.tgr4 uncore cache CMS Agent1 BL Credits Occupancy; For Transgress 4 event=0x8e,umask=0x10  01    Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy.tgr5 uncore cache CMS Agent1 BL Credits Occupancy; For Transgress 5 event=0x8e,umask=0x20  01    Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_credits_acquired.tgr0 uncore cache CMS Agent1 BL Credits Acquired; For Transgress 0 event=0x8c,umask=1  01    Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_credits_acquired.tgr1 uncore cache CMS Agent1 BL Credits Acquired; For Transgress 1 event=0x8c,umask=2  01    Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_credits_acquired.tgr2 uncore cache CMS Agent1 BL Credits Acquired; For Transgress 2 event=0x8c,umask=4  01    Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_credits_acquired.tgr3 uncore cache CMS Agent1 BL Credits Acquired; For Transgress 3 event=0x8c,umask=8  01    Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_credits_acquired.tgr4 uncore cache CMS Agent1 BL Credits Acquired; For Transgress 4 event=0x8c,umask=0x10  01    Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_credits_acquired.tgr5 uncore cache CMS Agent1 BL Credits Acquired; For Transgress 5 event=0x8c,umask=0x20  01    Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_bypass_cha_imc.intermediate uncore cache CHA to iMC Bypass; Intermediate bypass Taken event=0x57,umask=2  01    Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the intermediate bypass unc_cha_bypass_cha_imc.not_taken uncore cache CHA to iMC Bypass; Not Taken event=0x57,umask=4  01    Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass, and issues a read to memory. Note that transactions that did not take the bypass but did not issue read to memory will not be counted unc_cha_bypass_cha_imc.taken uncore cache CHA to iMC Bypass; Taken event=0x57,umask=1  01    Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the full bypass unc_cha_clockticks uncore cache Uncore cache clock ticks event=0  01    Counts clockticks of the clock controlling the uncore caching and home agent (CHA) unc_cha_cms_clockticks uncore cache CMS Clockticks event=0xc0  01     unc_cha_core_pma.c1_state uncore cache Core PMA Events; C1  State event=0x17,umask=1  01     unc_cha_core_pma.c1_transition uncore cache Core PMA Events; C1 Transition event=0x17,umask=2  01     unc_cha_core_pma.c6_state uncore cache Core PMA Events; C6 State event=0x17,umask=4  01     unc_cha_core_pma.c6_transition uncore cache Core PMA Events; C6 Transition event=0x17,umask=8  01     unc_cha_core_pma.gv uncore cache Core PMA Events; GV event=0x17,umask=0x10  01     unc_cha_core_snp.any_gtone uncore cache Core Cross Snoops Issued; Any Cycle with Multiple Snoops event=0x33,umask=0xe2  01    Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.any_one uncore cache Core Cross Snoops Issued; Any Single Snoop event=0x33,umask=0xe1  01    Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.any_remote uncore cache Core Cross Snoops Issued; Any Snoop to Remote Node event=0x33,umask=0xe4  01    Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.core_gtone uncore cache Core Cross Snoops Issued; Multiple Core Requests event=0x33,umask=0x42  01    Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.core_one uncore cache Core Cross Snoops Issued; Single Core Requests event=0x33,umask=0x41  01    Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.core_remote uncore cache Core Cross Snoops Issued; Core Request to Remote Node event=0x33,umask=0x44  01    Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.evict_gtone uncore cache Core Cross Snoops Issued; Multiple Eviction event=0x33,umask=0x82  01    Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.evict_one uncore cache Core Cross Snoops Issued; Single Eviction event=0x33,umask=0x81  01    Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.evict_remote uncore cache Core Cross Snoops Issued; Eviction to Remote Node event=0x33,umask=0x84  01    Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.ext_gtone uncore cache Core Cross Snoops Issued; Multiple External Snoops event=0x33,umask=0x22  01    Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.ext_one uncore cache Core Cross Snoops Issued; Single External Snoops event=0x33,umask=0x21  01    Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.ext_remote uncore cache Core Cross Snoops Issued; External Snoop to Remote Node event=0x33,umask=0x24  01    Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s) unc_cha_counter0_occupancy uncore cache Counter 0 Occupancy event=0x1f  01    Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0.   The filtering available is found in the control register - threshold, invert and edge detect.   E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry unc_cha_dir_lookup.no_snp uncore cache Multi-socket cacheline Directory state lookups; Snoop Not Needed event=0x53,umask=2  01    Counts transactions that looked into the multi-socket cacheline Directory state, and therefore did not send a snoop because the Directory indicated it was not needed unc_cha_dir_lookup.snp uncore cache Multi-socket cacheline Directory state lookups; Snoop Needed event=0x53,umask=1  01    Counts  transactions that looked into the multi-socket cacheline Directory state, and sent one or more snoops, because the Directory indicated it was needed unc_cha_dir_update.ha uncore cache Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe event=0x54,umask=1  01    Counts only multi-socket cacheline Directory state updates memory writes issued from the HA pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines unc_cha_dir_update.tor uncore cache Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe event=0x54,umask=2  01    Counts only multi-socket cacheline Directory state updates due to memory writes issued from the TOR pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines unc_cha_egress_ordering.iv_snoopgo_dn uncore cache Egress Blocking due to Ordering requirements; Down event=0xae,umask=4  01    Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_cha_egress_ordering.iv_snoopgo_up uncore cache Egress Blocking due to Ordering requirements; Up event=0xae,umask=1  01    Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_cha_fast_asserted.horz uncore cache FaST wire asserted; Horizontal event=0xa5,umask=2  01    Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across unc_cha_fast_asserted.vert uncore cache FaST wire asserted; Vertical event=0xa5,umask=1  01    Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across unc_cha_hitme_hit.ex_rds uncore cache Read request from a remote socket which hit in the HitMe Cache to a line In the E state event=0x5f,umask=1  01    Counts read requests from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory state) to a line in the E(Exclusive) state.  This includes the following read opcodes (RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*) unc_cha_hitme_hit.shared_ownreq uncore cache Counts Number of Hits in HitMe Cache; Shared hit and op is RdInvOwn, RdInv, Inv* event=0x5f,umask=4  01     unc_cha_hitme_hit.wbmtoe uncore cache Counts Number of Hits in HitMe Cache; op is WbMtoE event=0x5f,umask=8  01     unc_cha_hitme_hit.wbmtoi_or_s uncore cache Counts Number of Hits in HitMe Cache; op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoS event=0x5f,umask=0x10  01     unc_cha_hitme_lookup.read uncore cache Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv* event=0x5e,umask=1  01     unc_cha_hitme_lookup.write uncore cache Counts Number of times HitMe Cache is accessed; op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS event=0x5e,umask=2  01     unc_cha_hitme_miss.notshared_rdinvown uncore cache Counts Number of Misses in HitMe Cache; No SF/LLC HitS/F and op is RdInvOwn event=0x60,umask=0x40  01     unc_cha_hitme_miss.read_or_inv uncore cache Counts Number of Misses in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv* event=0x60,umask=0x80  01     unc_cha_hitme_miss.shared_rdinvown uncore cache Counts Number of Misses in HitMe Cache; SF/LLC HitS/F and op is RdInvOwn event=0x60,umask=0x20  01     unc_cha_hitme_update.deallocate uncore cache Counts the number of Allocate/Update to HitMe Cache; Deallocate HitME$ on Reads without RspFwdI* event=0x61,umask=0x10  01     unc_cha_hitme_update.deallocate_rspfwdi_loc uncore cache Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a local request event=0x61,umask=1  01    Received RspFwdI* for a local request, but converted HitME$ to SF entry unc_cha_hitme_update.rdinvown uncore cache Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache on RdInvOwn even if not RspFwdI* event=0x61,umask=8  01     unc_cha_hitme_update.rspfwdi_rem uncore cache Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request event=0x61,umask=2  01    Updated HitME$ on RspFwdI* or local HitM/E received for a remote request unc_cha_hitme_update.shared uncore cache Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache to SHARed event=0x61,umask=4  01     unc_cha_horz_ring_ad_in_use.left_even uncore cache Horizontal AD Ring In Use; Left and Even event=0xa7,umask=1  01    Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ad_in_use.left_odd uncore cache Horizontal AD Ring In Use; Left and Odd event=0xa7,umask=2  01    Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ad_in_use.right_even uncore cache Horizontal AD Ring In Use; Right and Even event=0xa7,umask=4  01    Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ad_in_use.right_odd uncore cache Horizontal AD Ring In Use; Right and Odd event=0xa7,umask=8  01    Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ak_in_use.left_even uncore cache Horizontal AK Ring In Use; Left and Even event=0xa9,umask=1  01    Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ak_in_use.left_odd uncore cache Horizontal AK Ring In Use; Left and Odd event=0xa9,umask=2  01    Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ak_in_use.right_even uncore cache Horizontal AK Ring In Use; Right and Even event=0xa9,umask=4  01    Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ak_in_use.right_odd uncore cache Horizontal AK Ring In Use; Right and Odd event=0xa9,umask=8  01    Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_bl_in_use.left_even uncore cache Horizontal BL Ring in Use; Left and Even event=0xab,umask=1  01    Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_bl_in_use.left_odd uncore cache Horizontal BL Ring in Use; Left and Odd event=0xab,umask=2  01    Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_bl_in_use.right_even uncore cache Horizontal BL Ring in Use; Right and Even event=0xab,umask=4  01    Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_bl_in_use.right_odd uncore cache Horizontal BL Ring in Use; Right and Odd event=0xab,umask=8  01    Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_iv_in_use.left uncore cache Horizontal IV Ring in Use; Left event=0xad,umask=1  01    Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_cha_horz_ring_iv_in_use.right uncore cache Horizontal IV Ring in Use; Right event=0xad,umask=4  01    Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_cha_imc_reads_count.normal uncore cache Normal priority reads issued to the memory controller from the CHA event=0x59,umask=1  01    Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA unc_cha_imc_reads_count.priority uncore cache HA to iMC Reads Issued; ISOCH event=0x59,umask=2  01    Count of the number of reads issued to any of the memory controller channels.  This can be filtered by the priority of the reads unc_cha_imc_writes_count.full uncore cache CHA to iMC Full Line Writes Issued; Full Line Non-ISOCH event=0x5b,umask=1  01    Counts when a normal (Non-Isochronous) full line write is issued from the CHA to the any of the memory controller channels unc_cha_imc_writes_count.full_mig uncore cache Writes Issued to the iMC by the HA; Full Line MIG event=0x5b,umask=0x10  01    Counts the total number of writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH unc_cha_imc_writes_count.full_priority uncore cache Writes Issued to the iMC by the HA; ISOCH Full Line event=0x5b,umask=4  01    Counts the total number of writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH unc_cha_imc_writes_count.partial uncore cache Writes Issued to the iMC by the HA; Partial Non-ISOCH event=0x5b,umask=2  01    Counts the total number of writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH unc_cha_imc_writes_count.partial_mig uncore cache Writes Issued to the iMC by the HA; Partial MIG event=0x5b,umask=0x20  01    Counts the total number of writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.; Filter for memory controller 5 only unc_cha_imc_writes_count.partial_priority uncore cache Writes Issued to the iMC by the HA; ISOCH Partial event=0x5b,umask=8  01    Counts the total number of writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH unc_cha_iodc_alloc.invitom uncore cache Counts Number of times IODC entry allocation is attempted; Number of IODC allocations event=0x62,umask=1  01     unc_cha_iodc_alloc.iodcfull uncore cache Counts Number of times IODC entry allocation is attempted; Number of IODC allocations dropped due to IODC Full event=0x62,umask=2  01     unc_cha_iodc_alloc.osbgated uncore cache Counts Number of times IODC entry allocation is attempted; Number of IDOC allocation dropped due to OSB gate event=0x62,umask=4  01     unc_cha_iodc_dealloc.all uncore cache Counts number of IODC deallocations; IODC deallocated due to any reason event=0x63,umask=0x10  01     unc_cha_iodc_dealloc.snpout uncore cache Counts number of IODC deallocations; IODC deallocated due to conflicting transaction event=0x63,umask=8  01     unc_cha_iodc_dealloc.wbmtoe uncore cache Counts number of IODC deallocations; IODC deallocated due to WbMtoE event=0x63,umask=1  01     unc_cha_iodc_dealloc.wbmtoi uncore cache Counts number of IODC deallocations; IODC deallocated due to WbMtoI event=0x63,umask=2  01     unc_cha_iodc_dealloc.wbpushmtoi uncore cache Counts number of IODC deallocations; IODC deallocated due to WbPushMtoI event=0x63,umask=4  01    Moved to Cbo section unc_cha_llc_lookup.any uncore cache Cache and Snoop Filter Lookups; Any Request event=0x34,umask=0x11  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ.  This does not include lookups originating from the ISMQ unc_cha_llc_lookup.data_read uncore cache Cache and Snoop Filter Lookups; Data Read Request event=0x34,umask=3  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Read transactions unc_cha_llc_lookup.local uncore cache Cache and Snoop Filter Lookups; Local event=0x34,umask=0x31  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state unc_cha_llc_lookup.remote uncore cache Cache and Snoop Filter Lookups; Remote event=0x34,umask=0x91  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state unc_cha_llc_lookup.remote_snoop uncore cache Cache and Snoop Filter Lookups; External Snoop Request event=0x34,umask=9  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ unc_cha_llc_lookup.write uncore cache Cache and Snoop Filter Lookups; Write Requests event=0x34,umask=5  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC  This includes all write transactions -- both Cacheable and UC unc_cha_llc_victims.e_state uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E event=0x37,umask=2  11     unc_cha_llc_victims.f_state uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F event=0x37,umask=8  11     unc_cha_llc_victims.local uncore cache This event is deprecated event=0x37,umask=0x20  11     unc_cha_llc_victims.local_all uncore cache Lines Victimized; Local - All Lines event=0x37,umask=0x2f  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.local_e uncore cache Lines Victimized; Local - Lines in E State event=0x37,umask=0x22  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.local_f uncore cache Lines Victimized; Local - Lines in F State event=0x37,umask=0x28  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.local_m uncore cache Lines Victimized; Local - Lines in M State event=0x37,umask=0x21  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.local_s uncore cache Lines Victimized; Local - Lines in S State event=0x37,umask=0x24  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.m_state uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M event=0x37,umask=1  11     unc_cha_llc_victims.remote uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL event=0x37,umask=0x80  11     unc_cha_llc_victims.remote_all uncore cache Lines Victimized; Remote - All Lines event=0x37,umask=0x8f  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.remote_e uncore cache Lines Victimized; Remote - Lines in E State event=0x37,umask=0x82  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.remote_f uncore cache Lines Victimized; Remote - Lines in F State event=0x37,umask=0x88  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.remote_m uncore cache Lines Victimized; Remote - Lines in M State event=0x37,umask=0x81  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.remote_s uncore cache Lines Victimized; Remote - Lines in S State event=0x37,umask=0x84  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.s_state uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S event=0x37,umask=4  11     unc_cha_llc_victims.total_e uncore cache Lines Victimized; Lines in E state event=0x37,umask=2  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.total_f uncore cache Lines Victimized; Lines in F State event=0x37,umask=8  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.total_m uncore cache Lines Victimized; Lines in M state event=0x37,umask=1  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.total_s uncore cache Lines Victimized; Lines in S State event=0x37,umask=4  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_misc.cv0_pref_miss uncore cache Cbo Misc; CV0 Prefetch Miss event=0x39,umask=0x20  01    Miscellaneous events in the Cbo unc_cha_misc.cv0_pref_vic uncore cache Cbo Misc; CV0 Prefetch Victim event=0x39,umask=0x10  01    Miscellaneous events in the Cbo unc_cha_misc.rfo_hit_s uncore cache Number of times that an RFO hit in S state event=0x39,umask=8  01    Counts when a RFO (the Read for Ownership issued before a  write) request hit a cacheline in the S (Shared) state unc_cha_misc.rspi_was_fse uncore cache Cbo Misc; Silent Snoop Eviction event=0x39,umask=1  01    Miscellaneous events in the Cbo.; Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction.  This is useful because this information is lost in the PRE encodings unc_cha_misc.wc_aliasing uncore cache Cbo Misc; Write Combining Aliasing event=0x39,umask=2  01    Miscellaneous events in the Cbo.; Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write.  This occurs when there is WC aliasing unc_cha_osb uncore cache OSB Snoop Broadcast event=0x55  01    Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_cha_pmm_memmode_nm_setconflicts.iodc uncore cache Memory Mode related events; Counts the number of times CHA saw NM Set conflict in IODC event=0x64,umask=0x10  01    2LM related events; Counts the number of times CHA saw NM Set conflict in IODC unc_cha_pmm_memmode_nm_setconflicts.llc uncore cache Memory Mode related events; Counts the number of times CHA saw NM Set conflict in SF/LLC event=0x64,umask=2  01    NM evictions due to another read to the same near memory set in the LLC unc_cha_pmm_memmode_nm_setconflicts.sf uncore cache Memory Mode related events; Counts the number of times CHA saw NM Set conflict in SF/LLC event=0x64,umask=1  01    NM evictions due to another read to the same near memory set in the SF unc_cha_pmm_memmode_nm_setconflicts.tor uncore cache Memory Mode related events; Counts the number of times CHA saw NM Set conflict in TOR event=0x64,umask=4  01    No Reject in the CHA due to a pending read to the same near memory set in the TOR unc_cha_pmm_memmode_nm_setconflicts.tor_reject uncore cache Memory mode related events; Counts the number of times CHA saw NM Set conflict in TOR and the transaction was rejected event=0x64,umask=8  01    Rejects in the CHA due to a pending read to the same near memory set in the TOR unc_cha_read_no_credits.edc0_smi2 uncore cache CHA iMC CHNx READ Credits Empty; EDC0_SMI2 event=0x58,umask=4  01    Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 2 only unc_cha_read_no_credits.edc1_smi3 uncore cache CHA iMC CHNx READ Credits Empty; EDC1_SMI3 event=0x58,umask=8  01    Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 3 only unc_cha_read_no_credits.edc2_smi4 uncore cache CHA iMC CHNx READ Credits Empty; EDC2_SMI4 event=0x58,umask=0x10  01    Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 4 only unc_cha_read_no_credits.edc3_smi5 uncore cache CHA iMC CHNx READ Credits Empty; EDC3_SMI5 event=0x58,umask=0x20  01    Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 5 only unc_cha_read_no_credits.mc0_smi0 uncore cache CHA iMC CHNx READ Credits Empty; MC0_SMI0 event=0x58,umask=1  01    Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 0 only unc_cha_read_no_credits.mc1_smi1 uncore cache CHA iMC CHNx READ Credits Empty; MC1_SMI1 event=0x58,umask=2  01    Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 1 only unc_cha_requests.invitoe_local uncore cache Local requests for exclusive ownership of a cache line  without receiving data event=0x50,umask=0x10  01    Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA unc_cha_requests.invitoe_remote uncore cache Local requests for exclusive ownership of a cache line without receiving data event=0x50,umask=0x20  01    Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA unc_cha_requests.reads uncore cache Read requests event=0x50,umask=3  01    Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a  write)  unc_cha_requests.reads_local uncore cache Read requests from a unit on this socket event=0x50,umask=1  01    Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a  write) unc_cha_requests.reads_remote uncore cache Read requests from a remote socket event=0x50,umask=2  01    Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a  write) unc_cha_requests.writes uncore cache Write requests event=0x50,umask=0xc  01    Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc unc_cha_requests.writes_local uncore cache Write Requests from a unit on this socket event=0x50,umask=4  01    Counts  write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc unc_cha_requests.writes_remote uncore cache Read and Write Requests; Writes Remote event=0x50,umask=8  01    Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc) unc_cha_ring_bounces_horz.ad uncore cache Messages that bounced on the Horizontal Ring.; AD event=0xa1,umask=1  01    Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_cha_ring_bounces_horz.ak uncore cache Messages that bounced on the Horizontal Ring.; AK event=0xa1,umask=2  01    Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_cha_ring_bounces_horz.bl uncore cache Messages that bounced on the Horizontal Ring.; BL event=0xa1,umask=4  01    Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_cha_ring_bounces_horz.iv uncore cache Messages that bounced on the Horizontal Ring.; IV event=0xa1,umask=8  01    Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_cha_ring_bounces_vert.ad uncore cache Messages that bounced on the Vertical Ring.; AD event=0xa0,umask=1  01    Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_cha_ring_bounces_vert.ak uncore cache Messages that bounced on the Vertical Ring.; Acknowledgements to core event=0xa0,umask=2  01    Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_cha_ring_bounces_vert.bl uncore cache Messages that bounced on the Vertical Ring.; Data Responses to core event=0xa0,umask=4  01    Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_cha_ring_bounces_vert.iv uncore cache Messages that bounced on the Vertical Ring.; Snoops of processor's cache event=0xa0,umask=8  01    Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_cha_ring_sink_starved_horz.ad uncore cache Sink Starvation on Horizontal Ring; AD event=0xa3,umask=1  01     unc_cha_ring_sink_starved_horz.ak uncore cache Sink Starvation on Horizontal Ring; AK event=0xa3,umask=2  01     unc_cha_ring_sink_starved_horz.ak_ag1 uncore cache Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1 event=0xa3,umask=0x20  01     unc_cha_ring_sink_starved_horz.bl uncore cache Sink Starvation on Horizontal Ring; BL event=0xa3,umask=4  01     unc_cha_ring_sink_starved_horz.iv uncore cache Sink Starvation on Horizontal Ring; IV event=0xa3,umask=8  01     unc_cha_ring_sink_starved_vert.ad uncore cache Sink Starvation on Vertical Ring; AD event=0xa2,umask=1  01     unc_cha_ring_sink_starved_vert.ak uncore cache Sink Starvation on Vertical Ring; Acknowledgements to core event=0xa2,umask=2  01     unc_cha_ring_sink_starved_vert.bl uncore cache Sink Starvation on Vertical Ring; Data Responses to core event=0xa2,umask=4  01     unc_cha_ring_sink_starved_vert.iv uncore cache Sink Starvation on Vertical Ring; Snoops of processor's cache event=0xa2,umask=8  01     unc_cha_ring_src_thrtl uncore cache Source Throttle event=0xa4  01     unc_cha_rxc_inserts.ipq uncore cache Ingress (from CMS) Allocations; IPQ event=0x13,umask=4  01    Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.irq uncore cache Ingress (from CMS) Allocations; IRQ event=0x13,umask=1  01    Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.irq_rej uncore cache Ingress (from CMS) Allocations; IRQ Rejected event=0x13,umask=2  01    Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.prq uncore cache Ingress (from CMS) Allocations; PRQ event=0x13,umask=0x10  01    Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.prq_rej uncore cache Ingress (from CMS) Allocations; PRQ event=0x13,umask=0x20  01    Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.rrq uncore cache Ingress (from CMS) Allocations; RRQ event=0x13,umask=0x40  01    Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.wbq uncore cache Ingress (from CMS) Allocations; WBQ event=0x13,umask=0x80  01    Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_ipq0_reject.ad_req_vn0 uncore cache Ingress Probe Queue Rejects; AD REQ on VN0 event=0x22,umask=1  01     unc_cha_rxc_ipq0_reject.ad_rsp_vn0 uncore cache Ingress Probe Queue Rejects; AD RSP on VN0 event=0x22,umask=2  01     unc_cha_rxc_ipq0_reject.ak_non_upi uncore cache Ingress Probe Queue Rejects; Non UPI AK Request event=0x22,umask=0x40  01     unc_cha_rxc_ipq0_reject.bl_ncb_vn0 uncore cache Ingress Probe Queue Rejects; BL NCB on VN0 event=0x22,umask=0x10  01     unc_cha_rxc_ipq0_reject.bl_ncs_vn0 uncore cache Ingress Probe Queue Rejects; BL NCS on VN0 event=0x22,umask=0x20  01     unc_cha_rxc_ipq0_reject.bl_rsp_vn0 uncore cache Ingress Probe Queue Rejects; BL RSP on VN0 event=0x22,umask=4  01     unc_cha_rxc_ipq0_reject.bl_wb_vn0 uncore cache Ingress Probe Queue Rejects; BL WB on VN0 event=0x22,umask=8  01     unc_cha_rxc_ipq0_reject.iv_non_upi uncore cache Ingress Probe Queue Rejects; Non UPI IV Request event=0x22,umask=0x80  01     unc_cha_rxc_ipq1_reject.allow_snp uncore cache Ingress Probe Queue Rejects; Allow Snoop event=0x23,umask=0x40  01     unc_cha_rxc_ipq1_reject.any0 uncore cache Ingress Probe Queue Rejects; ANY0 event=0x23,umask=1  01     unc_cha_rxc_ipq1_reject.ha uncore cache Ingress Probe Queue Rejects; HA event=0x23,umask=2  01     unc_cha_rxc_ipq1_reject.llc_or_sf_way uncore cache Ingress Probe Queue Rejects; Merging these two together to make room for ANY_REJECT_*0 event=0x23,umask=0x20  01     unc_cha_rxc_ipq1_reject.llc_victim uncore cache Ingress Probe Queue Rejects; LLC Victim event=0x23,umask=4  01     unc_cha_rxc_ipq1_reject.pa_match uncore cache Ingress Probe Queue Rejects; PhyAddr Match event=0x23,umask=0x80  01     unc_cha_rxc_ipq1_reject.sf_victim uncore cache Ingress Probe Queue Rejects; SF Victim event=0x23,umask=8  01     unc_cha_rxc_ipq1_reject.victim uncore cache Ingress Probe Queue Rejects; Victim event=0x23,umask=0x10  01     unc_cha_rxc_irq0_reject.ad_req_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; AD REQ on VN0 event=0x18,umask=1  01     unc_cha_rxc_irq0_reject.ad_rsp_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; AD RSP on VN0 event=0x18,umask=2  01     unc_cha_rxc_irq0_reject.ak_non_upi uncore cache Ingress (from CMS) Request Queue Rejects; Non UPI AK Request event=0x18,umask=0x40  01     unc_cha_rxc_irq0_reject.bl_ncb_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; BL NCB on VN0 event=0x18,umask=0x10  01     unc_cha_rxc_irq0_reject.bl_ncs_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; BL NCS on VN0 event=0x18,umask=0x20  01     unc_cha_rxc_irq0_reject.bl_rsp_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; BL RSP on VN0 event=0x18,umask=4  01     unc_cha_rxc_irq0_reject.bl_wb_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; BL WB on VN0 event=0x18,umask=8  01     unc_cha_rxc_irq0_reject.iv_non_upi uncore cache Ingress (from CMS) Request Queue Rejects; Non UPI IV Request event=0x18,umask=0x80  01     unc_cha_rxc_irq1_reject.allow_snp uncore cache Ingress (from CMS) Request Queue Rejects; Allow Snoop event=0x19,umask=0x40  01     unc_cha_rxc_irq1_reject.any0 uncore cache Ingress (from CMS) Request Queue Rejects; ANY0 event=0x19,umask=1  01     unc_cha_rxc_irq1_reject.ha uncore cache Ingress (from CMS) Request Queue Rejects; HA event=0x19,umask=2  01     unc_cha_rxc_irq1_reject.llc_or_sf_way uncore cache Ingress (from CMS) Request Queue Rejects; Merging these two together to make room for ANY_REJECT_*0 event=0x19,umask=0x20  01     unc_cha_rxc_irq1_reject.llc_victim uncore cache Ingress (from CMS) Request Queue Rejects; LLC Victim event=0x19,umask=4  01     unc_cha_rxc_irq1_reject.pa_match uncore cache Ingress (from CMS) Request Queue Rejects; PhyAddr Match event=0x19,umask=0x80  01     unc_cha_rxc_irq1_reject.sf_victim uncore cache Ingress (from CMS) Request Queue Rejects; SF Victim event=0x19,umask=8  01     unc_cha_rxc_irq1_reject.victim uncore cache Ingress (from CMS) Request Queue Rejects; Victim event=0x19,umask=0x10  01     unc_cha_rxc_ismq0_reject.ad_req_vn0 uncore cache ISMQ Rejects; AD REQ on VN0 event=0x24,umask=1  01    Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_reject.ad_rsp_vn0 uncore cache ISMQ Rejects; AD RSP on VN0 event=0x24,umask=2  01    Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_reject.ak_non_upi uncore cache ISMQ Rejects; Non UPI AK Request event=0x24,umask=0x40  01    Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_reject.bl_ncb_vn0 uncore cache ISMQ Rejects; BL NCB on VN0 event=0x24,umask=0x10  01    Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_reject.bl_ncs_vn0 uncore cache ISMQ Rejects; BL NCS on VN0 event=0x24,umask=0x20  01    Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_reject.bl_rsp_vn0 uncore cache ISMQ Rejects; BL RSP on VN0 event=0x24,umask=4  01    Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_reject.bl_wb_vn0 uncore cache ISMQ Rejects; BL WB on VN0 event=0x24,umask=8  01    Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_reject.iv_non_upi uncore cache ISMQ Rejects; Non UPI IV Request event=0x24,umask=0x80  01    Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_retry.ad_req_vn0 uncore cache ISMQ Retries; AD REQ on VN0 event=0x2c,umask=1  01    Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_retry.ad_rsp_vn0 uncore cache ISMQ Retries; AD RSP on VN0 event=0x2c,umask=2  01    Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_retry.ak_non_upi uncore cache ISMQ Retries; Non UPI AK Request event=0x2c,umask=0x40  01    Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_retry.bl_ncb_vn0 uncore cache ISMQ Retries; BL NCB on VN0 event=0x2c,umask=0x10  01    Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_retry.bl_ncs_vn0 uncore cache ISMQ Retries; BL NCS on VN0 event=0x2c,umask=0x20  01    Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_retry.bl_rsp_vn0 uncore cache ISMQ Retries; BL RSP on VN0 event=0x2c,umask=4  01    Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_retry.bl_wb_vn0 uncore cache ISMQ Retries; BL WB on VN0 event=0x2c,umask=8  01    Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq0_retry.iv_non_upi uncore cache ISMQ Retries; Non UPI IV Request event=0x2c,umask=0x80  01    Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq1_reject.any0 uncore cache ISMQ Rejects; ANY0 event=0x25,umask=1  01    Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq1_reject.ha uncore cache ISMQ Rejects; HA event=0x25,umask=2  01    Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq1_retry.any0 uncore cache ISMQ Retries; ANY0 event=0x2d,umask=1  01    Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq1_retry.ha uncore cache ISMQ Retries; HA event=0x2d,umask=2  01    Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_occupancy.ipq uncore cache Ingress (from CMS) Occupancy; IPQ event=0x11,umask=4  01    Counts number of entries in the specified Ingress queue in each cycle unc_cha_rxc_occupancy.irq uncore cache Ingress (from CMS) Occupancy; IRQ event=0x11,umask=1  01    Counts number of entries in the specified Ingress queue in each cycle unc_cha_rxc_occupancy.rrq uncore cache Ingress (from CMS) Occupancy; RRQ event=0x11,umask=0x40  01    Counts number of entries in the specified Ingress queue in each cycle unc_cha_rxc_occupancy.wbq uncore cache Ingress (from CMS) Occupancy; WBQ event=0x11,umask=0x80  01    Counts number of entries in the specified Ingress queue in each cycle unc_cha_rxc_other0_retry.ad_req_vn0 uncore cache Other Retries; AD REQ on VN0 event=0x2e,umask=1  01    Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other0_retry.ad_rsp_vn0 uncore cache Other Retries; AD RSP on VN0 event=0x2e,umask=2  01    Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other0_retry.ak_non_upi uncore cache Other Retries; Non UPI AK Request event=0x2e,umask=0x40  01    Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other0_retry.bl_ncb_vn0 uncore cache Other Retries; BL NCB on VN0 event=0x2e,umask=0x10  01    Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other0_retry.bl_ncs_vn0 uncore cache Other Retries; BL NCS on VN0 event=0x2e,umask=0x20  01    Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other0_retry.bl_rsp_vn0 uncore cache Other Retries; BL RSP on VN0 event=0x2e,umask=4  01    Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other0_retry.bl_wb_vn0 uncore cache Other Retries; BL WB on VN0 event=0x2e,umask=8  01    Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other0_retry.iv_non_upi uncore cache Other Retries; Non UPI IV Request event=0x2e,umask=0x80  01    Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.allow_snp uncore cache Other Retries; Allow Snoop event=0x2f,umask=0x40  01    Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.any0 uncore cache Other Retries; ANY0 event=0x2f,umask=1  01    Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.ha uncore cache Other Retries; HA event=0x2f,umask=2  01    Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.llc_or_sf_way uncore cache Other Retries; Merging these two together to make room for ANY_REJECT_*0 event=0x2f,umask=0x20  01    Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.llc_victim uncore cache Other Retries; LLC Victim event=0x2f,umask=4  01    Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.pa_match uncore cache Other Retries; PhyAddr Match event=0x2f,umask=0x80  01    Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.sf_victim uncore cache Other Retries; SF Victim event=0x2f,umask=8  01    Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.victim uncore cache Other Retries; Victim event=0x2f,umask=0x10  01    Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_prq0_reject.ad_req_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; AD REQ on VN0 event=0x20,umask=1  01     unc_cha_rxc_prq0_reject.ad_rsp_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; AD RSP on VN0 event=0x20,umask=2  01     unc_cha_rxc_prq0_reject.ak_non_upi uncore cache Ingress (from CMS) Request Queue Rejects; Non UPI AK Request event=0x20,umask=0x40  01     unc_cha_rxc_prq0_reject.bl_ncb_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; BL NCB on VN0 event=0x20,umask=0x10  01     unc_cha_rxc_prq0_reject.bl_ncs_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; BL NCS on VN0 event=0x20,umask=0x20  01     unc_cha_rxc_prq0_reject.bl_rsp_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; BL RSP on VN0 event=0x20,umask=4  01     unc_cha_rxc_prq0_reject.bl_wb_vn0 uncore cache Ingress (from CMS) Request Queue Rejects; BL WB on VN0 event=0x20,umask=8  01     unc_cha_rxc_prq0_reject.iv_non_upi uncore cache Ingress (from CMS) Request Queue Rejects; Non UPI IV Request event=0x20,umask=0x80  01     unc_cha_rxc_prq1_reject.allow_snp uncore cache Ingress (from CMS) Request Queue Rejects; Allow Snoop event=0x21,umask=0x40  01     unc_cha_rxc_prq1_reject.any0 uncore cache Ingress (from CMS) Request Queue Rejects; ANY0 event=0x21,umask=1  01     unc_cha_rxc_prq1_reject.ha uncore cache Ingress (from CMS) Request Queue Rejects; HA event=0x21,umask=2  01     unc_cha_rxc_prq1_reject.llc_or_sf_way uncore cache Ingress (from CMS) Request Queue Rejects; LLC OR SF Way event=0x21,umask=0x20  01     unc_cha_rxc_prq1_reject.llc_victim uncore cache Ingress (from CMS) Request Queue Rejects; LLC Victim event=0x21,umask=4  01     unc_cha_rxc_prq1_reject.pa_match uncore cache Ingress (from CMS) Request Queue Rejects; PhyAddr Match event=0x21,umask=0x80  01     unc_cha_rxc_prq1_reject.sf_victim uncore cache Ingress (from CMS) Request Queue Rejects; SF Victim event=0x21,umask=8  01     unc_cha_rxc_prq1_reject.victim uncore cache Ingress (from CMS) Request Queue Rejects; Victim event=0x21,umask=0x10  01     unc_cha_rxc_req_q0_retry.ad_req_vn0 uncore cache Request Queue Retries; AD REQ on VN0 event=0x2a,umask=1  01    REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q0_retry.ad_rsp_vn0 uncore cache Request Queue Retries; AD RSP on VN0 event=0x2a,umask=2  01    REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q0_retry.ak_non_upi uncore cache Request Queue Retries; Non UPI AK Request event=0x2a,umask=0x40  01    REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q0_retry.bl_ncb_vn0 uncore cache Request Queue Retries; BL NCB on VN0 event=0x2a,umask=0x10  01    REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q0_retry.bl_ncs_vn0 uncore cache Request Queue Retries; BL NCS on VN0 event=0x2a,umask=0x20  01    REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q0_retry.bl_rsp_vn0 uncore cache Request Queue Retries; BL RSP on VN0 event=0x2a,umask=4  01    REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q0_retry.bl_wb_vn0 uncore cache Request Queue Retries; BL WB on VN0 event=0x2a,umask=8  01    REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q0_retry.iv_non_upi uncore cache Request Queue Retries; Non UPI IV Request event=0x2a,umask=0x80  01    REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.allow_snp uncore cache Request Queue Retries; Allow Snoop event=0x2b,umask=0x40  01    REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.any0 uncore cache Request Queue Retries; ANY0 event=0x2b,umask=1  01    REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.ha uncore cache Request Queue Retries; HA event=0x2b,umask=2  01    REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.llc_or_sf_way uncore cache Request Queue Retries; Merging these two together to make room for ANY_REJECT_*0 event=0x2b,umask=0x20  01    REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.llc_victim uncore cache Request Queue Retries; LLC Victim event=0x2b,umask=4  01    REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.pa_match uncore cache Request Queue Retries; PhyAddr Match event=0x2b,umask=0x80  01    REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.sf_victim uncore cache Request Queue Retries; SF Victim event=0x2b,umask=8  01    REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.victim uncore cache Request Queue Retries; Victim event=0x2b,umask=0x10  01    REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_rrq0_reject.ad_req_vn0 uncore cache RRQ Rejects; AD REQ on VN0 event=0x26,umask=1  01    Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq0_reject.ad_rsp_vn0 uncore cache RRQ Rejects; AD RSP on VN0 event=0x26,umask=2  01    Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq0_reject.ak_non_upi uncore cache RRQ Rejects; Non UPI AK Request event=0x26,umask=0x40  01    Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq0_reject.bl_ncb_vn0 uncore cache RRQ Rejects; BL NCB on VN0 event=0x26,umask=0x10  01    Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq0_reject.bl_ncs_vn0 uncore cache RRQ Rejects; BL NCS on VN0 event=0x26,umask=0x20  01    Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq0_reject.bl_rsp_vn0 uncore cache RRQ Rejects; BL RSP on VN0 event=0x26,umask=4  01    Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq0_reject.bl_wb_vn0 uncore cache RRQ Rejects; BL WB on VN0 event=0x26,umask=8  01    Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq0_reject.iv_non_upi uncore cache RRQ Rejects; Non UPI IV Request event=0x26,umask=0x80  01    Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.allow_snp uncore cache RRQ Rejects; Allow Snoop event=0x27,umask=0x40  01    Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.any0 uncore cache RRQ Rejects; ANY0 event=0x27,umask=1  01    Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.ha uncore cache RRQ Rejects; HA event=0x27,umask=2  01    Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.llc_or_sf_way uncore cache RRQ Rejects; Merging these two together to make room for ANY_REJECT_*0 event=0x27,umask=0x20  01    Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.llc_victim uncore cache RRQ Rejects; LLC Victim event=0x27,umask=4  01    Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.pa_match uncore cache RRQ Rejects; PhyAddr Match event=0x27,umask=0x80  01    Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.sf_victim uncore cache RRQ Rejects; SF Victim event=0x27,umask=8  01    Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.victim uncore cache RRQ Rejects; Victim event=0x27,umask=0x10  01    Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_wbq0_reject.ad_req_vn0 uncore cache WBQ Rejects; AD REQ on VN0 event=0x28,umask=1  01    Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq0_reject.ad_rsp_vn0 uncore cache WBQ Rejects; AD RSP on VN0 event=0x28,umask=2  01    Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq0_reject.ak_non_upi uncore cache WBQ Rejects; Non UPI AK Request event=0x28,umask=0x40  01    Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq0_reject.bl_ncb_vn0 uncore cache WBQ Rejects; BL NCB on VN0 event=0x28,umask=0x10  01    Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq0_reject.bl_ncs_vn0 uncore cache WBQ Rejects; BL NCS on VN0 event=0x28,umask=0x20  01    Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq0_reject.bl_rsp_vn0 uncore cache WBQ Rejects; BL RSP on VN0 event=0x28,umask=4  01    Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq0_reject.bl_wb_vn0 uncore cache WBQ Rejects; BL WB on VN0 event=0x28,umask=8  01    Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq0_reject.iv_non_upi uncore cache WBQ Rejects; Non UPI IV Request event=0x28,umask=0x80  01    Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.allow_snp uncore cache WBQ Rejects; Allow Snoop event=0x29,umask=0x40  01    Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.any0 uncore cache WBQ Rejects; ANY0 event=0x29,umask=1  01    Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.ha uncore cache WBQ Rejects; HA event=0x29,umask=2  01    Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.llc_or_sf_way uncore cache WBQ Rejects; Merging these two together to make room for ANY_REJECT_*0 event=0x29,umask=0x20  01    Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.llc_victim uncore cache WBQ Rejects; LLC Victim event=0x29,umask=4  01    Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.pa_match uncore cache WBQ Rejects; PhyAddr Match event=0x29,umask=0x80  01    Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.sf_victim uncore cache WBQ Rejects; SF Victim event=0x29,umask=8  01    Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.victim uncore cache WBQ Rejects; Victim event=0x29,umask=0x10  01    Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxr_busy_starved.ad_bnc uncore cache Transgress Injection Starvation; AD - Bounce event=0xb4,umask=1  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority unc_cha_rxr_busy_starved.ad_crd uncore cache Transgress Injection Starvation; AD - Credit event=0xb4,umask=0x10  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority unc_cha_rxr_busy_starved.bl_bnc uncore cache Transgress Injection Starvation; BL - Bounce event=0xb4,umask=4  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority unc_cha_rxr_busy_starved.bl_crd uncore cache Transgress Injection Starvation; BL - Credit event=0xb4,umask=0x40  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority unc_cha_rxr_bypass.ad_bnc uncore cache Transgress Ingress Bypass; AD - Bounce event=0xb2,umask=1  01    Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.ad_crd uncore cache Transgress Ingress Bypass; AD - Credit event=0xb2,umask=0x10  01    Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.ak_bnc uncore cache Transgress Ingress Bypass; AK - Bounce event=0xb2,umask=2  01    Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.bl_bnc uncore cache Transgress Ingress Bypass; BL - Bounce event=0xb2,umask=4  01    Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.bl_crd uncore cache Transgress Ingress Bypass; BL - Credit event=0xb2,umask=0x40  01    Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.iv_bnc uncore cache Transgress Ingress Bypass; IV - Bounce event=0xb2,umask=8  01    Number of packets bypassing the CMS Ingress unc_cha_rxr_crd_starved.ad_bnc uncore cache Transgress Injection Starvation; AD - Bounce event=0xb3,umask=1  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.ad_crd uncore cache Transgress Injection Starvation; AD - Credit event=0xb3,umask=0x10  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.ak_bnc uncore cache Transgress Injection Starvation; AK - Bounce event=0xb3,umask=2  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.bl_bnc uncore cache Transgress Injection Starvation; BL - Bounce event=0xb3,umask=4  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.bl_crd uncore cache Transgress Injection Starvation; BL - Credit event=0xb3,umask=0x40  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.ifv uncore cache Transgress Injection Starvation; IFV - Credit event=0xb3,umask=0x80  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.iv_bnc uncore cache Transgress Injection Starvation; IV - Bounce event=0xb3,umask=8  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_inserts.ad_bnc uncore cache Transgress Ingress Allocations; AD - Bounce event=0xb1,umask=1  01    Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.ad_crd uncore cache Transgress Ingress Allocations; AD - Credit event=0xb1,umask=0x10  01    Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.ak_bnc uncore cache Transgress Ingress Allocations; AK - Bounce event=0xb1,umask=2  01    Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.bl_bnc uncore cache Transgress Ingress Allocations; BL - Bounce event=0xb1,umask=4  01    Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.bl_crd uncore cache Transgress Ingress Allocations; BL - Credit event=0xb1,umask=0x40  01    Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.iv_bnc uncore cache Transgress Ingress Allocations; IV - Bounce event=0xb1,umask=8  01    Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.ad_bnc uncore cache Transgress Ingress Occupancy; AD - Bounce event=0xb0,umask=1  01    Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.ad_crd uncore cache Transgress Ingress Occupancy; AD - Credit event=0xb0,umask=0x10  01    Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.ak_bnc uncore cache Transgress Ingress Occupancy; AK - Bounce event=0xb0,umask=2  01    Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.bl_bnc uncore cache Transgress Ingress Occupancy; BL - Bounce event=0xb0,umask=4  01    Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.bl_crd uncore cache Transgress Ingress Occupancy; BL - Credit event=0xb0,umask=0x40  01    Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.iv_bnc uncore cache Transgress Ingress Occupancy; IV - Bounce event=0xb0,umask=8  01    Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_cha_sf_eviction.e_state uncore cache Snoop filter capacity evictions for E-state entries event=0x3d,umask=2  01    Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline unc_cha_sf_eviction.m_state uncore cache Snoop filter capacity evictions for M-state entries event=0x3d,umask=1  01    Counts snoop filter capacity evictions for entries tracking modified lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline unc_cha_sf_eviction.s_state uncore cache Snoop filter capacity evictions for S-state entries event=0x3d,umask=4  01    Counts snoop filter capacity evictions for entries tracking shared lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline unc_cha_snoops_sent.all uncore cache Snoops Sent; All event=0x51,umask=1  01    Counts the number of snoops issued by the HA unc_cha_snoops_sent.bcst_local uncore cache Snoops Sent; Broadcast snoop for Local Requests event=0x51,umask=0x10  01    Counts the number of snoops issued by the HA.; Counts the number of broadcast snoops issued by the HA. This filter includes only requests coming from local sockets unc_cha_snoops_sent.bcst_remote uncore cache Snoops Sent; Broadcast snoops for Remote Requests event=0x51,umask=0x20  01    Counts the number of snoops issued by the HA.; Counts the number of broadcast snoops issued by the HA.This filter includes only requests coming from remote sockets unc_cha_snoops_sent.direct_local uncore cache Snoops Sent; Directed snoops for Local Requests event=0x51,umask=0x40  01    Counts the number of snoops issued by the HA.; Counts the number of directed snoops issued by the HA. This filter includes only requests coming from local sockets unc_cha_snoops_sent.direct_remote uncore cache Snoops Sent; Directed snoops for Remote Requests event=0x51,umask=0x80  01    Counts the number of snoops issued by the HA.; Counts the number of directed snoops issued by the HA. This filter includes only requests coming from remote sockets unc_cha_snoops_sent.local uncore cache Snoops Sent; Broadcast or directed Snoops sent for Local Requests event=0x51,umask=4  01    Counts the number of snoops issued by the HA.; Counts the number of broadcast or directed snoops issued by the HA per request. This filter includes only requests coming from the local socket unc_cha_snoops_sent.remote uncore cache Snoops Sent; Broadcast or directed Snoops sent for Remote Requests event=0x51,umask=8  01    Counts the number of snoops issued by the HA.; Counts the number of broadcast or directed snoops issued by the HA per request. This filter includes only requests coming from the remote socket unc_cha_snoop_resp.rspcnflcts uncore cache RspCnflct* Snoop Responses Received event=0x5c,umask=0x40  01    Counts when a a transaction with the opcode type RspCnflct* Snoop Response was received. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent. This triggers conflict resolution hardware. This covers both the opcode RspCnflct and RspCnflctWbI unc_cha_snoop_resp.rspfwd uncore cache Snoop Responses Received; RspFwd event=0x5c,umask=0x80  01    Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspFwd to a CA request.  This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state unc_cha_snoop_resp.rspi uncore cache RspI Snoop Responses Received event=0x5c,umask=1  01    Counts when a transaction with the opcode type RspI Snoop Response was received which indicates the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO: the Read for Ownership issued before a write hits non-modified data) unc_cha_snoop_resp.rspifwd uncore cache RspIFwd Snoop Responses Received event=0x5c,umask=4  01    Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states.  This is commonly returned with RFO (the Read for Ownership issued before a write) transactions.  The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward)  states unc_cha_snoop_resp.rsps uncore cache Snoop Responses Received : RspS event=0x5c,umask=2  01    Snoop Responses Received : RspS : Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for snoop responses of RspS.  RspS is returned when a remote cache has data but is not forwarding it.  It is a way to let the requesting socket know that it cannot allocate the data in E state.  No data is sent with S RspS unc_cha_snoop_resp.rspsfwd uncore cache RspSFwd Snoop Responses Received event=0x5c,umask=8  01    Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy.  This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state unc_cha_snoop_resp.rsp_fwd_wb uncore cache Rsp*Fwd*WB Snoop Responses Received event=0x5c,umask=0x20  01    Counts when a transaction with the opcode type Rsp*Fwd*WB Snoop Response was received which indicates the data was written back to its home socket, and the cacheline was forwarded to the requestor socket.  This snoop response is only used in >= 4 socket systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to its home socket to be written back to memory unc_cha_snoop_resp.rsp_wbwb uncore cache Rsp*WB Snoop Responses Received event=0x5c,umask=0x10  01    Counts when a transaction with the opcode type Rsp*WB Snoop Response was received which indicates which indicates the data was written back to its home.  This is returned when a non-RFO request hits a cacheline in the Modified state. The Cache can either downgrade the cacheline to a S (Shared) or I (Invalid) state depending on how the system has been configured.  This response will also be sent when a cache requests E (Exclusive) ownership of a cache line without receiving data, because the cache must acquire ownership unc_cha_snoop_resp_local.rspcnflct uncore cache Snoop Responses Received Local; RspCnflct event=0x5d,umask=0x40  01    Number of snoop responses received for a Local  request; Filters for snoops responses of RspConflict to local CA requests.  This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent.  This triggers conflict resolution hardware.  This covers both RspCnflct and RspCnflctWbI unc_cha_snoop_resp_local.rspfwd uncore cache Snoop Responses Received Local; RspFwd event=0x5d,umask=0x80  01    Number of snoop responses received for a Local  request; Filters for a snoop response of RspFwd to local CA requests.  This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state unc_cha_snoop_resp_local.rspi uncore cache Snoop Responses Received Local; RspI event=0x5d,umask=1  01    Number of snoop responses received for a Local  request; Filters for snoops responses of RspI to local CA requests.  RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data) unc_cha_snoop_resp_local.rspifwd uncore cache Snoop Responses Received Local; RspIFwd event=0x5d,umask=4  01    Number of snoop responses received for a Local  request; Filters for snoop responses of RspIFwd to local CA requests.  This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states.  This is commonly returned with RFO transactions.  It can be either a HitM or a HitFE unc_cha_snoop_resp_local.rsps uncore cache Snoop Responses Received Local; RspS event=0x5d,umask=2  01    Number of snoop responses received for a Local  request; Filters for snoop responses of RspS to local CA requests.  RspS is returned when a remote cache has data but is not forwarding it.  It is a way to let the requesting socket know that it cannot allocate the data in E state.  No data is sent with S RspS unc_cha_snoop_resp_local.rspsfwd uncore cache Snoop Responses Received Local; RspSFwd event=0x5d,umask=8  01    Number of snoop responses received for a Local  request; Filters for a snoop response of RspSFwd to local CA requests.  This is returned when a remote caching agent forwards data but holds on to its current copy.  This is common for data and code reads that hit in a remote socket in E or F state unc_cha_snoop_resp_local.rsp_fwd_wb uncore cache Snoop Responses Received Local; Rsp*FWD*WB event=0x5d,umask=0x20  01    Number of snoop responses received for a Local  request; Filters for a snoop response of Rsp*Fwd*WB to local CA requests.  This snoop response is only used in 4s systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory unc_cha_snoop_resp_local.rsp_wb uncore cache Snoop Responses Received Local; Rsp*WB event=0x5d,umask=0x10  01    Number of snoop responses received for a Local  request; Filters for a snoop response of RspIWB or RspSWB to local CA requests.  This is returned when a non-RFO request hits in M state.  Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured.  InvItoE transactions will also return RspIWB because they must acquire ownership unc_cha_stall_no_txr_horz_crd_ad_ag0.tgr0 uncore cache Stall on No AD Agent0 Transgress Credits; For Transgress 0 event=0xd0,umask=1  01    Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag0.tgr1 uncore cache Stall on No AD Agent0 Transgress Credits; For Transgress 1 event=0xd0,umask=2  01    Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag0.tgr2 uncore cache Stall on No AD Agent0 Transgress Credits; For Transgress 2 event=0xd0,umask=4  01    Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag0.tgr3 uncore cache Stall on No AD Agent0 Transgress Credits; For Transgress 3 event=0xd0,umask=8  01    Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag0.tgr4 uncore cache Stall on No AD Agent0 Transgress Credits; For Transgress 4 event=0xd0,umask=0x10  01    Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag0.tgr5 uncore cache Stall on No AD Agent0 Transgress Credits; For Transgress 5 event=0xd0,umask=0x20  01    Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag1.tgr0 uncore cache Stall on No AD Agent1 Transgress Credits; For Transgress 0 event=0xd2,umask=1  01    Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag1.tgr1 uncore cache Stall on No AD Agent1 Transgress Credits; For Transgress 1 event=0xd2,umask=2  01    Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag1.tgr2 uncore cache Stall on No AD Agent1 Transgress Credits; For Transgress 2 event=0xd2,umask=4  01    Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag1.tgr3 uncore cache Stall on No AD Agent1 Transgress Credits; For Transgress 3 event=0xd2,umask=8  01    Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag1.tgr4 uncore cache Stall on No AD Agent1 Transgress Credits; For Transgress 4 event=0xd2,umask=0x10  01    Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_ad_ag1.tgr5 uncore cache Stall on No AD Agent1 Transgress Credits; For Transgress 5 event=0xd2,umask=0x20  01    Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag0.tgr0 uncore cache Stall on No BL Agent0 Transgress Credits; For Transgress 0 event=0xd4,umask=1  01    Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag0.tgr1 uncore cache Stall on No BL Agent0 Transgress Credits; For Transgress 1 event=0xd4,umask=2  01    Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag0.tgr2 uncore cache Stall on No BL Agent0 Transgress Credits; For Transgress 2 event=0xd4,umask=4  01    Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag0.tgr3 uncore cache Stall on No BL Agent0 Transgress Credits; For Transgress 3 event=0xd4,umask=8  01    Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag0.tgr4 uncore cache Stall on No BL Agent0 Transgress Credits; For Transgress 4 event=0xd4,umask=0x10  01    Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag0.tgr5 uncore cache Stall on No BL Agent0 Transgress Credits; For Transgress 5 event=0xd4,umask=0x20  01    Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag1.tgr0 uncore cache Stall on No BL Agent1 Transgress Credits; For Transgress 0 event=0xd6,umask=1  01    Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag1.tgr1 uncore cache Stall on No BL Agent1 Transgress Credits; For Transgress 1 event=0xd6,umask=2  01    Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag1.tgr2 uncore cache Stall on No BL Agent1 Transgress Credits; For Transgress 2 event=0xd6,umask=4  01    Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag1.tgr3 uncore cache Stall on No BL Agent1 Transgress Credits; For Transgress 3 event=0xd6,umask=8  01    Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag1.tgr4 uncore cache Stall on No BL Agent1 Transgress Credits; For Transgress 4 event=0xd6,umask=0x10  01    Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall_no_txr_horz_crd_bl_ag1.tgr5 uncore cache Stall on No BL Agent1 Transgress Credits; For Transgress 5 event=0xd6,umask=0x20  01    Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_tor_inserts.all uncore cache TOR Inserts; All event=0x35,umask=0xff  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.all_hit uncore cache TOR Inserts; Hits from Local event=0x35,umask=0x15  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.all_io_ia uncore cache TOR Inserts; All from Local iA and IO event=0x35,umask=0x35  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally initiated requests unc_cha_tor_inserts.all_miss uncore cache TOR Inserts; Misses from Local event=0x35,umask=0x25  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.evict uncore cache TOR Inserts; SF/LLC Evictions event=0x35,umask=2  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ) unc_cha_tor_inserts.hit uncore cache TOR Inserts; Hit (Not a Miss) event=0x35,umask=0x10  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; HITs (hit is defined to be not a miss [see below], as a result for any request allocated into the TOR, one of either HIT or MISS must be true) unc_cha_tor_inserts.ia uncore cache TOR Inserts; All from Local iA event=0x35,umask=0x31  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally initiated requests from iA Cores unc_cha_tor_inserts.ia_hit uncore cache TOR Inserts; Hits from Local iA event=0x35,umask=0x11  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.ia_hit_crd uncore cache TOR Inserts : CRds issued by iA Cores that Hit the LLC event=0x35,umask=0x11,config1=0x40233  01    TOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_drd uncore cache TOR Inserts : DRds issued by iA Cores that Hit the LLC event=0x35,umask=0x11,config1=0x40433  01    TOR Inserts : DRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_llcprefcrd uncore cache UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD event=0x35,umask=0x11,config1=0x4b233  01     unc_cha_tor_inserts.ia_hit_llcprefdrd uncore cache UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD event=0x35,umask=0x11,config1=0x4b433  01     unc_cha_tor_inserts.ia_hit_llcprefrfo uncore cache TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC event=0x35,umask=0x11,config1=0x4b033  01    TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_rfo uncore cache TOR Inserts : RFOs issued by iA Cores that Hit the LLC event=0x35,umask=0x11,config1=0x40033  01    TOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss uncore cache TOR Inserts : All requests from iA Cores that Missed the LLC event=0x35,umask=0x21  01    TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd uncore cache TOR Inserts : CRds issued by iA Cores that Missed the LLC event=0x35,umask=0x21,config1=0x40233  01    TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd uncore cache TOR Inserts : DRds issued by iA Cores that Missed the LLC event=0x35,umask=0x21,config1=0x40433  01    TOR Inserts : DRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_llcprefcrd uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD event=0x35,umask=0x21,config1=0x4b233  01     unc_cha_tor_inserts.ia_miss_llcprefdrd uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD event=0x35,umask=0x21,config1=0x4b433  01     unc_cha_tor_inserts.ia_miss_llcprefrfo uncore cache TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC event=0x35,umask=0x21,config1=0x4b033  01    TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_rfo uncore cache TOR Inserts : RFOs issued by iA Cores that Missed the LLC event=0x35,umask=0x21,config1=0x40033  01    TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io uncore cache TOR Inserts; All from Local IO event=0x35,umask=0x34  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally generated IO traffic unc_cha_tor_inserts.io_hit uncore cache TOR Inserts; Hits from Local IO event=0x35,umask=0x14  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.io_miss uncore cache TOR Inserts; Misses from Local IO event=0x35,umask=0x24  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.io_miss_itom uncore cache TOR Inserts; ItoM misses from Local IO event=0x35,umask=0x24,config1=0x49033  01    Counts the number of entries successfully inserted into the TOR that are generated from local IO ItoM requests that miss the LLC. An ItoM request is used by IIO to request a data write without first reading the data for ownership unc_cha_tor_inserts.io_miss_rdcur uncore cache TOR Inserts; RdCur misses from Local IO event=0x35,umask=0x24,config1=0x43C33  01    Counts the number of entries successfully inserted into the TOR that are generated from local IO RdCur requests and miss the LLC. A RdCur request is used by IIO to read data without changing state unc_cha_tor_inserts.io_miss_rfo uncore cache TOR Inserts; RFO misses from Local IO event=0x35,umask=0x24,config1=0x40033  01    Counts the number of entries successfully inserted into the TOR that are generated from local IO RFO requests that miss the LLC. A read for ownership (RFO) requests a cache line to be cached in E state with the intent to modify unc_cha_tor_inserts.ipq uncore cache TOR Inserts; IPQ event=0x35,umask=8  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.ipq_hit uncore cache This event is deprecated event=0x35,umask=0x18  11     unc_cha_tor_inserts.ipq_miss uncore cache This event is deprecated event=0x35,umask=0x28  11     unc_cha_tor_inserts.irq uncore cache TOR Inserts; IRQ event=0x35,umask=1  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.loc_all uncore cache This event is deprecated event=0x35,umask=0x37  11     unc_cha_tor_inserts.miss uncore cache TOR Inserts; Miss event=0x35,umask=0x20  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; Misses.  (a miss is defined to be any transaction from the IRQ, PRQ, RRQ, IPQ or (in the victim case) the ISMQ, that required the CHA to spawn a new UPI/SMI3 request on the UPI fabric (including UPI snoops and/or any RD/WR to a local memory controller, in the event that the CHA is the home node)).  Basically, if the LLC/SF/MLC complex were not able to service the request without involving another agent...it is a miss.  If only IDI snoops were required, it is not a miss (that means the SF/MLC com unc_cha_tor_inserts.prq uncore cache TOR Inserts; PRQ event=0x35,umask=4  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.rem_all uncore cache This event is deprecated event=0x35,umask=0x30  11     unc_cha_tor_inserts.rrq_hit uncore cache This event is deprecated event=0x35,umask=0x50  11     unc_cha_tor_inserts.rrq_miss uncore cache This event is deprecated event=0x35,umask=0x60  11     unc_cha_tor_inserts.wbq_hit uncore cache This event is deprecated event=0x35,umask=0x90  11     unc_cha_tor_inserts.wbq_miss uncore cache This event is deprecated event=0x35,umask=0xa0  11     unc_cha_tor_occupancy.all uncore cache TOR Occupancy : All event=0x36,umask=0xff  01    TOR Occupancy : All : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.all_from_loc uncore cache TOR Occupancy; All from Local event=0x36,umask=0x37  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All remotely generated requests unc_cha_tor_occupancy.all_hit uncore cache TOR Occupancy; Hits from Local event=0x36,umask=0x17  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T unc_cha_tor_occupancy.all_miss uncore cache TOR Occupancy; Misses from Local event=0x36,umask=0x27  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T unc_cha_tor_occupancy.evict uncore cache TOR Occupancy; SF/LLC Evictions event=0x36,umask=2  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T; TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ) unc_cha_tor_occupancy.hit uncore cache TOR Occupancy; Hit (Not a Miss) event=0x36,umask=0x10  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T; HITs (hit is defined to be not a miss [see below], as a result for any request allocated into the TOR, one of either HIT or MISS must be true) unc_cha_tor_occupancy.ia uncore cache TOR Occupancy; All from Local iA event=0x36,umask=0x31  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T; All locally initiated requests from iA Cores unc_cha_tor_occupancy.ia_hit uncore cache TOR Occupancy; Hits from Local iA event=0x36,umask=0x11  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T unc_cha_tor_occupancy.ia_hit_crd uncore cache TOR Occupancy : CRds issued by iA Cores that Hit the LLC event=0x36,umask=0x11,config1=0x40233  01    TOR Occupancy : CRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_drd uncore cache TOR Occupancy : DRds issued by iA Cores that Hit the LLC event=0x36,umask=0x11,config1=0x40433  01    TOR Occupancy : DRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_llcprefcrd uncore cache UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD event=0x36,umask=0x11,config1=0x4b233  01     unc_cha_tor_occupancy.ia_hit_llcprefdrd uncore cache UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD event=0x36,umask=0x11,config1=0x4b433  01     unc_cha_tor_occupancy.ia_hit_llcprefrfo uncore cache TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC event=0x36,umask=0x11,config1=0x4b033  01    TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_rfo uncore cache TOR Occupancy : RFOs issued by iA Cores that Hit the LLC event=0x36,umask=0x11,config1=0x40033  01    TOR Occupancy : RFOs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss uncore cache TOR Occupancy; Misses from Local iA event=0x36,umask=0x21  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T unc_cha_tor_occupancy.ia_miss_crd uncore cache TOR Occupancy : CRds issued by iA Cores that Missed the LLC event=0x36,umask=0x21,config1=0x40233  01    TOR Occupancy : CRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd uncore cache TOR Occupancy : DRds issued by iA Cores that Missed the LLC event=0x36,umask=0x21,config1=0x40433  01    TOR Occupancy : DRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_llcprefcrd uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD event=0x36,umask=0x21,config1=0x4b233  01     unc_cha_tor_occupancy.ia_miss_llcprefdrd uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD event=0x36,umask=0x21,config1=0x4b433  01     unc_cha_tor_occupancy.ia_miss_llcprefrfo uncore cache TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC event=0x36,umask=0x21,config1=0x4b033  01    TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_rfo uncore cache TOR Occupancy : RFOs issued by iA Cores that Missed the LLC event=0x36,umask=0x21,config1=0x40033  01    TOR Occupancy : RFOs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io uncore cache TOR Occupancy; All from Local IO event=0x36,umask=0x34  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T; All locally generated IO traffic unc_cha_tor_occupancy.io_hit uncore cache TOR Occupancy; Hits from Local IO event=0x36,umask=0x14  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T unc_cha_tor_occupancy.io_miss uncore cache TOR Occupancy; Misses from Local IO event=0x36,umask=0x24  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T unc_cha_tor_occupancy.io_miss_itom uncore cache TOR Occupancy;  ITOM Misses from Local IO event=0x36,umask=0x24,config1=0x49033  01    For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO ItoM requests that miss the LLC. An ItoM is used by IIO to request a data write without first reading the data for ownership unc_cha_tor_occupancy.io_miss_rdcur uncore cache TOR Occupancy;  RDCUR misses from Local IO event=0x36,umask=0x24,config1=0x43C33  01    For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO RdCur requests that miss the LLC. A RdCur request is used by IIO to read data without changing state unc_cha_tor_occupancy.io_miss_rfo uncore cache TOR Occupancy;  RFO misses from Local IO event=0x36,umask=0x24,config1=0x40033  01    For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO RFO requests that miss the LLC. A read for ownership (RFO) requests data to be cached in E state with the intent to modify unc_cha_tor_occupancy.ipq uncore cache TOR Occupancy; IPQ event=0x36,umask=8  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T unc_cha_tor_occupancy.ipq_hit uncore cache This event is deprecated event=0x36,umask=0x18  11     unc_cha_tor_occupancy.ipq_miss uncore cache This event is deprecated event=0x36,umask=0x28  11     unc_cha_tor_occupancy.irq uncore cache TOR Occupancy; IRQ event=0x36,umask=1  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T unc_cha_tor_occupancy.loc_all uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC event=0x36,umask=0x37  11     unc_cha_tor_occupancy.miss uncore cache TOR Occupancy; Miss event=0x36,umask=0x20  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T; Misses.  (a miss is defined to be any transaction from the IRQ, PRQ, RRQ, IPQ or (in the victim case) the ISMQ, that required the CHA to spawn a new UPI/SMI3 request on the UPI fabric (including UPI snoops and/or any RD/WR to a local memory controller, in the event that the CHA is the home node)).  Basically, if the LLC/SF/MLC complex were not able to service the request without involving another agent...it is a miss.  If only IDI snoops were required, it is not a miss (that means the SF/MLC com unc_cha_tor_occupancy.prq uncore cache TOR Occupancy; PRQ event=0x36,umask=4  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T unc_cha_txr_horz_ads_used.ad_bnc uncore cache CMS Horizontal ADS Used; AD - Bounce event=0x9d,umask=1  01    Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_horz_ads_used.ad_crd uncore cache CMS Horizontal ADS Used; AD - Credit event=0x9d,umask=0x10  01    Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_horz_ads_used.ak_bnc uncore cache CMS Horizontal ADS Used; AK - Bounce event=0x9d,umask=2  01    Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_horz_ads_used.bl_bnc uncore cache CMS Horizontal ADS Used; BL - Bounce event=0x9d,umask=4  01    Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_horz_ads_used.bl_crd uncore cache CMS Horizontal ADS Used; BL - Credit event=0x9d,umask=0x40  01    Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.ad_bnc uncore cache CMS Horizontal Bypass Used; AD - Bounce event=0x9f,umask=1  01    Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.ad_crd uncore cache CMS Horizontal Bypass Used; AD - Credit event=0x9f,umask=0x10  01    Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.ak_bnc uncore cache CMS Horizontal Bypass Used; AK - Bounce event=0x9f,umask=2  01    Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.bl_bnc uncore cache CMS Horizontal Bypass Used; BL - Bounce event=0x9f,umask=4  01    Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.bl_crd uncore cache CMS Horizontal Bypass Used; BL - Credit event=0x9f,umask=0x40  01    Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.iv_bnc uncore cache CMS Horizontal Bypass Used; IV - Bounce event=0x9f,umask=8  01    Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_cycles_full.ad_bnc uncore cache Cycles CMS Horizontal Egress Queue is Full; AD - Bounce event=0x96,umask=1  01    Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.ad_crd uncore cache Cycles CMS Horizontal Egress Queue is Full; AD - Credit event=0x96,umask=0x10  01    Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.ak_bnc uncore cache Cycles CMS Horizontal Egress Queue is Full; AK - Bounce event=0x96,umask=2  01    Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.bl_bnc uncore cache Cycles CMS Horizontal Egress Queue is Full; BL - Bounce event=0x96,umask=4  01    Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.bl_crd uncore cache Cycles CMS Horizontal Egress Queue is Full; BL - Credit event=0x96,umask=0x40  01    Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.iv_bnc uncore cache Cycles CMS Horizontal Egress Queue is Full; IV - Bounce event=0x96,umask=8  01    Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.ad_bnc uncore cache Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce event=0x97,umask=1  01    Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.ad_crd uncore cache Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit event=0x97,umask=0x10  01    Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.ak_bnc uncore cache Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce event=0x97,umask=2  01    Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.bl_bnc uncore cache Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce event=0x97,umask=4  01    Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.bl_crd uncore cache Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit event=0x97,umask=0x40  01    Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.iv_bnc uncore cache Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce event=0x97,umask=8  01    Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.ad_bnc uncore cache CMS Horizontal Egress Inserts; AD - Bounce event=0x95,umask=1  01    Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.ad_crd uncore cache CMS Horizontal Egress Inserts; AD - Credit event=0x95,umask=0x10  01    Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.ak_bnc uncore cache CMS Horizontal Egress Inserts; AK - Bounce event=0x95,umask=2  01    Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.bl_bnc uncore cache CMS Horizontal Egress Inserts; BL - Bounce event=0x95,umask=4  01    Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.bl_crd uncore cache CMS Horizontal Egress Inserts; BL - Credit event=0x95,umask=0x40  01    Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.iv_bnc uncore cache CMS Horizontal Egress Inserts; IV - Bounce event=0x95,umask=8  01    Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_nack.ad_bnc uncore cache CMS Horizontal Egress NACKs; AD - Bounce event=0x99,umask=1  01    Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.ad_crd uncore cache CMS Horizontal Egress NACKs; AD - Credit event=0x99,umask=0x20  01    Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.ak_bnc uncore cache CMS Horizontal Egress NACKs; AK - Bounce event=0x99,umask=2  01    Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.bl_bnc uncore cache CMS Horizontal Egress NACKs; BL - Bounce event=0x99,umask=4  01    Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.bl_crd uncore cache CMS Horizontal Egress NACKs; BL - Credit event=0x99,umask=0x40  01    Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.iv_bnc uncore cache CMS Horizontal Egress NACKs; IV - Bounce event=0x99,umask=8  01    Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_occupancy.ad_bnc uncore cache CMS Horizontal Egress Occupancy; AD - Bounce event=0x94,umask=1  01    Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.ad_crd uncore cache CMS Horizontal Egress Occupancy; AD - Credit event=0x94,umask=0x10  01    Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.ak_bnc uncore cache CMS Horizontal Egress Occupancy; AK - Bounce event=0x94,umask=2  01    Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.bl_bnc uncore cache CMS Horizontal Egress Occupancy; BL - Bounce event=0x94,umask=4  01    Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.bl_crd uncore cache CMS Horizontal Egress Occupancy; BL - Credit event=0x94,umask=0x40  01    Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.iv_bnc uncore cache CMS Horizontal Egress Occupancy; IV - Bounce event=0x94,umask=8  01    Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_starved.ad_bnc uncore cache CMS Horizontal Egress Injection Starvation; AD - Bounce event=0x9b,umask=1  01    Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_cha_txr_horz_starved.ak_bnc uncore cache CMS Horizontal Egress Injection Starvation; AK - Bounce event=0x9b,umask=2  01    Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_cha_txr_horz_starved.bl_bnc uncore cache CMS Horizontal Egress Injection Starvation; BL - Bounce event=0x9b,umask=4  01    Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_cha_txr_horz_starved.iv_bnc uncore cache CMS Horizontal Egress Injection Starvation; IV - Bounce event=0x9b,umask=8  01    Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_cha_txr_vert_ads_used.ad_ag0 uncore cache CMS Vertical ADS Used; AD - Agent 0 event=0x9c,umask=1  01    Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_vert_ads_used.ad_ag1 uncore cache CMS Vertical ADS Used; AD - Agent 1 event=0x9c,umask=0x10  01    Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_vert_ads_used.ak_ag0 uncore cache CMS Vertical ADS Used; AK - Agent 0 event=0x9c,umask=2  01    Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_vert_ads_used.ak_ag1 uncore cache CMS Vertical ADS Used; AK - Agent 1 event=0x9c,umask=0x20  01    Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_vert_ads_used.bl_ag0 uncore cache CMS Vertical ADS Used; BL - Agent 0 event=0x9c,umask=4  01    Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_vert_ads_used.bl_ag1 uncore cache CMS Vertical ADS Used; BL - Agent 1 event=0x9c,umask=0x40  01    Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.ad_ag0 uncore cache CMS Vertical ADS Used; AD - Agent 0 event=0x9e,umask=1  01    Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.ad_ag1 uncore cache CMS Vertical ADS Used; AD - Agent 1 event=0x9e,umask=0x10  01    Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.ak_ag0 uncore cache CMS Vertical ADS Used; AK - Agent 0 event=0x9e,umask=2  01    Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.ak_ag1 uncore cache CMS Vertical ADS Used; AK - Agent 1 event=0x9e,umask=0x20  01    Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.bl_ag0 uncore cache CMS Vertical ADS Used; BL - Agent 0 event=0x9e,umask=4  01    Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.bl_ag1 uncore cache CMS Vertical ADS Used; BL - Agent 1 event=0x9e,umask=0x40  01    Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.iv uncore cache CMS Vertical ADS Used; IV event=0x9e,umask=8  01    Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_cycles_full.ad_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0 event=0x92,umask=1  01    Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_cycles_full.ad_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1 event=0x92,umask=0x10  01    Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests unc_cha_txr_vert_cycles_full.ak_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0 event=0x92,umask=2  01    Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_cha_txr_vert_cycles_full.ak_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1 event=0x92,umask=0x20  01    Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_cha_txr_vert_cycles_full.bl_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0 event=0x92,umask=4  01    Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations unc_cha_txr_vert_cycles_full.bl_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1 event=0x92,umask=0x40  01    Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache unc_cha_txr_vert_cycles_full.iv uncore cache Cycles CMS Vertical Egress Queue Is Full; IV event=0x92,umask=8  01    Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores unc_cha_txr_vert_cycles_ne.ad_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0 event=0x93,umask=1  01    Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_cycles_ne.ad_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1 event=0x93,umask=0x10  01    Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests unc_cha_txr_vert_cycles_ne.ak_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0 event=0x93,umask=2  01    Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_cha_txr_vert_cycles_ne.ak_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1 event=0x93,umask=0x20  01    Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_cha_txr_vert_cycles_ne.bl_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0 event=0x93,umask=4  01    Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations unc_cha_txr_vert_cycles_ne.bl_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1 event=0x93,umask=0x40  01    Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache unc_cha_txr_vert_cycles_ne.iv uncore cache Cycles CMS Vertical Egress Queue Is Not Empty; IV event=0x93,umask=8  01    Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores unc_cha_txr_vert_inserts.ad_ag0 uncore cache CMS Vert Egress Allocations; AD - Agent 0 event=0x91,umask=1  01    Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_inserts.ad_ag1 uncore cache CMS Vert Egress Allocations; AD - Agent 1 event=0x91,umask=0x10  01    Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests unc_cha_txr_vert_inserts.ak_ag0 uncore cache CMS Vert Egress Allocations; AK - Agent 0 event=0x91,umask=2  01    Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_cha_txr_vert_inserts.ak_ag1 uncore cache CMS Vert Egress Allocations; AK - Agent 1 event=0x91,umask=0x20  01    Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_cha_txr_vert_inserts.bl_ag0 uncore cache CMS Vert Egress Allocations; BL - Agent 0 event=0x91,umask=4  01    Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations unc_cha_txr_vert_inserts.bl_ag1 uncore cache CMS Vert Egress Allocations; BL - Agent 1 event=0x91,umask=0x40  01    Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache unc_cha_txr_vert_inserts.iv uncore cache CMS Vert Egress Allocations; IV event=0x91,umask=8  01    Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores unc_cha_txr_vert_nack.ad_ag0 uncore cache CMS Vertical Egress NACKs; AD - Agent 0 event=0x98,umask=1  01    Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack.ad_ag1 uncore cache CMS Vertical Egress NACKs; AD - Agent 1 event=0x98,umask=0x10  01    Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack.ak_ag0 uncore cache CMS Vertical Egress NACKs; AK - Agent 0 event=0x98,umask=2  01    Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack.ak_ag1 uncore cache CMS Vertical Egress NACKs; AK - Agent 1 event=0x98,umask=0x20  01    Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack.bl_ag0 uncore cache CMS Vertical Egress NACKs; BL - Agent 0 event=0x98,umask=4  01    Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack.bl_ag1 uncore cache CMS Vertical Egress NACKs; BL - Agent 1 event=0x98,umask=0x40  01    Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack.iv uncore cache CMS Vertical Egress NACKs; IV event=0x98,umask=8  01    Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_occupancy.ad_ag0 uncore cache CMS Vert Egress Occupancy; AD - Agent 0 event=0x90,umask=1  01    Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_occupancy.ad_ag1 uncore cache CMS Vert Egress Occupancy; AD - Agent 1 event=0x90,umask=0x10  01    Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests unc_cha_txr_vert_occupancy.ak_ag0 uncore cache CMS Vert Egress Occupancy; AK - Agent 0 event=0x90,umask=2  01    Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_cha_txr_vert_occupancy.ak_ag1 uncore cache CMS Vert Egress Occupancy; AK - Agent 1 event=0x90,umask=0x20  01    Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_cha_txr_vert_occupancy.bl_ag0 uncore cache CMS Vert Egress Occupancy; BL - Agent 0 event=0x90,umask=4  01    Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations unc_cha_txr_vert_occupancy.bl_ag1 uncore cache CMS Vert Egress Occupancy; BL - Agent 1 event=0x90,umask=0x40  01    Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache unc_cha_txr_vert_occupancy.iv uncore cache CMS Vert Egress Occupancy; IV event=0x90,umask=8  01    Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores unc_cha_txr_vert_starved.ad_ag0 uncore cache CMS Vertical Egress Injection Starvation; AD - Agent 0 event=0x9a,umask=1  01    Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved.ad_ag1 uncore cache CMS Vertical Egress Injection Starvation; AD - Agent 1 event=0x9a,umask=0x10  01    Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved.ak_ag0 uncore cache CMS Vertical Egress Injection Starvation; AK - Agent 0 event=0x9a,umask=2  01    Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved.ak_ag1 uncore cache CMS Vertical Egress Injection Starvation; AK - Agent 1 event=0x9a,umask=0x20  01    Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved.bl_ag0 uncore cache CMS Vertical Egress Injection Starvation; BL - Agent 0 event=0x9a,umask=4  01    Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved.bl_ag1 uncore cache CMS Vertical Egress Injection Starvation; BL - Agent 1 event=0x9a,umask=0x40  01    Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved.iv uncore cache CMS Vertical Egress Injection Starvation; IV event=0x9a,umask=8  01    Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_upi_credits_acquired.ad_req uncore cache UPI Ingress Credit Allocations; AD REQ Credits event=0x38,umask=4  01    Counts the number of UPI credits acquired for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This can be used with the Credit Occupancy event in order to calculate average credit lifetime.  This event supports filtering to cover the VNA/VN0 credits and the different message classes.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credits_acquired.ad_rsp uncore cache UPI Ingress Credit Allocations; AD RSP VN0 Credits event=0x38,umask=8  01    Counts the number of UPI credits acquired for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This can be used with the Credit Occupancy event in order to calculate average credit lifetime.  This event supports filtering to cover the VNA/VN0 credits and the different message classes.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credits_acquired.bl_ncb uncore cache UPI Ingress Credit Allocations; BL NCB Credits event=0x38,umask=0x40  01    Counts the number of UPI credits acquired for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This can be used with the Credit Occupancy event in order to calculate average credit lifetime.  This event supports filtering to cover the VNA/VN0 credits and the different message classes.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credits_acquired.bl_ncs uncore cache UPI Ingress Credit Allocations; BL NCS Credits event=0x38,umask=0x80  01    Counts the number of UPI credits acquired for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This can be used with the Credit Occupancy event in order to calculate average credit lifetime.  This event supports filtering to cover the VNA/VN0 credits and the different message classes.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credits_acquired.bl_rsp uncore cache UPI Ingress Credit Allocations; BL RSP Credits event=0x38,umask=0x10  01    Counts the number of UPI credits acquired for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This can be used with the Credit Occupancy event in order to calculate average credit lifetime.  This event supports filtering to cover the VNA/VN0 credits and the different message classes.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credits_acquired.bl_wb uncore cache UPI Ingress Credit Allocations; BL DRS Credits event=0x38,umask=0x20  01    Counts the number of UPI credits acquired for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This can be used with the Credit Occupancy event in order to calculate average credit lifetime.  This event supports filtering to cover the VNA/VN0 credits and the different message classes.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credits_acquired.vn0 uncore cache UPI Ingress Credit Allocations; VN0 Credits event=0x38,umask=2  01    Counts the number of UPI credits acquired for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This can be used with the Credit Occupancy event in order to calculate average credit lifetime.  This event supports filtering to cover the VNA/VN0 credits and the different message classes.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credits_acquired.vna uncore cache UPI Ingress Credit Allocations; VNA Credits event=0x38,umask=1  01    Counts the number of UPI credits acquired for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This can be used with the Credit Occupancy event in order to calculate average credit lifetime.  This event supports filtering to cover the VNA/VN0 credits and the different message classes.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credit_occupancy.vn0_ad_req uncore cache UPI Ingress Credits In Use Cycles; AD REQ VN0 Credits event=0x3b,umask=4  01    Accumulates the number of UPI credits available in each cycle for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This stat increments by the number of credits that are available each cycle.  This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime.  This event supports filtering for the different types of credits that are available.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credit_occupancy.vn0_ad_rsp uncore cache UPI Ingress Credits In Use Cycles; AD RSP VN0 Credits event=0x3b,umask=8  01    Accumulates the number of UPI credits available in each cycle for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This stat increments by the number of credits that are available each cycle.  This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime.  This event supports filtering for the different types of credits that are available.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credit_occupancy.vn0_bl_ncb uncore cache UPI Ingress Credits In Use Cycles; BL NCB VN0 Credits event=0x3b,umask=0x40  01    Accumulates the number of UPI credits available in each cycle for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This stat increments by the number of credits that are available each cycle.  This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime.  This event supports filtering for the different types of credits that are available.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credit_occupancy.vn0_bl_ncs uncore cache UPI Ingress Credits In Use Cycles; BL NCS VN0 Credits event=0x3b,umask=0x80  01    Accumulates the number of UPI credits available in each cycle for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This stat increments by the number of credits that are available each cycle.  This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime.  This event supports filtering for the different types of credits that are available.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credit_occupancy.vn0_bl_rsp uncore cache UPI Ingress Credits In Use Cycles; BL RSP VN0 Credits event=0x3b,umask=0x10  01    Accumulates the number of UPI credits available in each cycle for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This stat increments by the number of credits that are available each cycle.  This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime.  This event supports filtering for the different types of credits that are available.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credit_occupancy.vn0_bl_wb uncore cache UPI Ingress Credits In Use Cycles; BL DRS VN0 Credits event=0x3b,umask=0x20  01    Accumulates the number of UPI credits available in each cycle for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This stat increments by the number of credits that are available each cycle.  This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime.  This event supports filtering for the different types of credits that are available.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credit_occupancy.vna_ad uncore cache UPI Ingress Credits In Use Cycles; AD VNA Credits event=0x3b,umask=1  01    Accumulates the number of UPI credits available in each cycle for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This stat increments by the number of credits that are available each cycle.  This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime.  This event supports filtering for the different types of credits that are available.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_upi_credit_occupancy.vna_bl uncore cache UPI Ingress Credits In Use Cycles; BL VNA Credits event=0x3b,umask=2  01    Accumulates the number of UPI credits available in each cycle for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This stat increments by the number of credits that are available each cycle.  This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime.  This event supports filtering for the different types of credits that are available.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time unc_cha_vert_ring_ad_in_use.dn_even uncore cache Vertical AD Ring In Use; Down and Even event=0xa6,umask=4  01    Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ad_in_use.dn_odd uncore cache Vertical AD Ring In Use; Down and Odd event=0xa6,umask=8  01    Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ad_in_use.up_even uncore cache Vertical AD Ring In Use; Up and Even event=0xa6,umask=1  01    Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ad_in_use.up_odd uncore cache Vertical AD Ring In Use; Up and Odd event=0xa6,umask=2  01    Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ak_in_use.dn_even uncore cache Vertical AK Ring In Use; Down and Even event=0xa8,umask=4  01    Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ak_in_use.dn_odd uncore cache Vertical AK Ring In Use; Down and Odd event=0xa8,umask=8  01    Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ak_in_use.up_even uncore cache Vertical AK Ring In Use; Up and Even event=0xa8,umask=1  01    Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ak_in_use.up_odd uncore cache Vertical AK Ring In Use; Up and Odd event=0xa8,umask=2  01    Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_bl_in_use.dn_even uncore cache Vertical BL Ring in Use; Down and Even event=0xaa,umask=4  01    Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_bl_in_use.dn_odd uncore cache Vertical BL Ring in Use; Down and Odd event=0xaa,umask=8  01    Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_bl_in_use.up_even uncore cache Vertical BL Ring in Use; Up and Even event=0xaa,umask=1  01    Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_bl_in_use.up_odd uncore cache Vertical BL Ring in Use; Up and Odd event=0xaa,umask=2  01    Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_iv_in_use.dn uncore cache Vertical IV Ring in Use; Down event=0xac,umask=4  01    Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_cha_vert_ring_iv_in_use.up uncore cache Vertical IV Ring in Use; Up event=0xac,umask=1  01    Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_cha_wb_push_mtoi.llc uncore cache WbPushMtoI; Pushed to LLC event=0x56,umask=1  01    Counts the number of times when the CHA was received WbPushMtoI; Counts the number of times when the CHA was able to push WbPushMToI to LLC unc_cha_wb_push_mtoi.mem uncore cache WbPushMtoI; Pushed to Memory event=0x56,umask=2  01    Counts the number of times when the CHA was received WbPushMtoI; Counts the number of times when the CHA was unable to push WbPushMToI to LLC (hence pushed it to MEM) unc_cha_write_no_credits.edc0_smi2 uncore cache CHA iMC CHNx WRITE Credits Empty; EDC0_SMI2 event=0x5a,umask=4  01    Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 2 only unc_cha_write_no_credits.edc1_smi3 uncore cache CHA iMC CHNx WRITE Credits Empty; EDC1_SMI3 event=0x5a,umask=8  01    Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 3 only unc_cha_write_no_credits.edc2_smi4 uncore cache CHA iMC CHNx WRITE Credits Empty; EDC2_SMI4 event=0x5a,umask=0x10  01    Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 4 only unc_cha_write_no_credits.edc3_smi5 uncore cache CHA iMC CHNx WRITE Credits Empty; EDC3_SMI5 event=0x5a,umask=0x20  01    Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 5 only unc_cha_write_no_credits.mc0_smi0 uncore cache CHA iMC CHNx WRITE Credits Empty; MC0_SMI0 event=0x5a,umask=1  01    Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 0 only unc_cha_write_no_credits.mc1_smi1 uncore cache CHA iMC CHNx WRITE Credits Empty; MC1_SMI1 event=0x5a,umask=2  01    Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 1 only unc_cha_xsnp_resp.any_rspi_fwdfe uncore cache Core Cross Snoop Responses; Any RspIFwdFE event=0x32,umask=0xe4  01    Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response I to Fwd F/E unc_cha_xsnp_resp.any_rspi_fwdm uncore cache Core Cross Snoop Responses event=0x32,umask=0xf0  01    Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response I to Fwd M unc_cha_xsnp_resp.any_rsps_fwdfe uncore cache Core Cross Snoop Responses; Any RspSFwdFE event=0x32,umask=0xe2  01    Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response S to Fwd F/E unc_cha_xsnp_resp.any_rsps_fwdm uncore cache Core Cross Snoop Responses; Any RspSFwdM event=0x32,umask=0xe8  01    Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response S to Fwd M unc_cha_xsnp_resp.any_rsp_hitfse uncore cache Core Cross Snoop Responses; Any RspHitFSE event=0x32,umask=0xe1  01    Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response any to Hit F/S/E unc_cha_xsnp_resp.core_rspi_fwdfe uncore cache Core Cross Snoop Responses; Core RspIFwdFE event=0x32,umask=0x44  01    Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response I to Fwd F/E unc_cha_xsnp_resp.core_rspi_fwdm uncore cache Core Cross Snoop Responses; Core RspIFwdM event=0x32,umask=0x50  01    Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response I to Fwd M unc_cha_xsnp_resp.core_rsps_fwdfe uncore cache Core Cross Snoop Responses; Core RspSFwdFE event=0x32,umask=0x42  01    Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response S to Fwd F/E unc_cha_xsnp_resp.core_rsps_fwdm uncore cache Core Cross Snoop Responses; Core RspSFwdM event=0x32,umask=0x48  01    Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response S to Fwd M unc_cha_xsnp_resp.core_rsp_hitfse uncore cache Core Cross Snoop Responses; Core RspHitFSE event=0x32,umask=0x41  01    Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response any to Hit F/S/E unc_cha_xsnp_resp.evict_rspi_fwdfe uncore cache Core Cross Snoop Responses; Evict RspIFwdFE event=0x32,umask=0x84  01    Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response I to Fwd F/E unc_cha_xsnp_resp.evict_rspi_fwdm uncore cache Core Cross Snoop Responses; Evict RspIFwdM event=0x32,umask=0x90  01    Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response I to Fwd M unc_cha_xsnp_resp.evict_rsps_fwdfe uncore cache Core Cross Snoop Responses; Evict RspSFwdFE event=0x32,umask=0x82  01    Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response S to Fwd F/E unc_cha_xsnp_resp.evict_rsps_fwdm uncore cache Core Cross Snoop Responses; Evict RspSFwdM event=0x32,umask=0x88  01    Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response S to Fwd M unc_cha_xsnp_resp.evict_rsp_hitfse uncore cache Core Cross Snoop Responses; Evict RspHitFSE event=0x32,umask=0x81  01    Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response any to Hit F/S/E unc_cha_xsnp_resp.ext_rspi_fwdfe uncore cache Core Cross Snoop Responses; External RspIFwdFE event=0x32,umask=0x24  01    Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response I to Fwd F/E unc_cha_xsnp_resp.ext_rspi_fwdm uncore cache Core Cross Snoop Responses; External RspIFwdM event=0x32,umask=0x30  01    Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response I to Fwd M unc_cha_xsnp_resp.ext_rsps_fwdfe uncore cache Core Cross Snoop Responses; External RspSFwdFE event=0x32,umask=0x22  01    Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response S to Fwd F/E unc_cha_xsnp_resp.ext_rsps_fwdm uncore cache Core Cross Snoop Responses; External RspSFwdM event=0x32,umask=0x28  01    Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response S to Fwd M unc_cha_xsnp_resp.ext_rsp_hitfse uncore cache Core Cross Snoop Responses; External RspHitFSE event=0x32,umask=0x21  01    Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response any to Hit F/S/E unc_c_clockticks uncore cache This event is deprecated. Refer to new event UNC_CHA_CLOCKTICKS event=0  11     unc_c_fast_asserted uncore cache This event is deprecated. Refer to new event UNC_CHA_FAST_ASSERTED.HORZ event=0xa5,umask=2  11     unc_c_llc_lookup.any uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.ANY event=0x34,umask=0x11  11     unc_c_llc_lookup.data_read uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ event=0x34,umask=3  11     unc_c_llc_lookup.local uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LOCAL event=0x34,umask=0x31  11     unc_c_llc_lookup.remote uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE event=0x34,umask=0x91  11     unc_c_llc_lookup.remote_snoop uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP event=0x34,umask=9  11     unc_c_llc_lookup.write uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITE event=0x34,umask=5  11     unc_c_llc_victims.e_state uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E event=0x37,umask=2  11     unc_c_llc_victims.f_state uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F event=0x37,umask=8  11     unc_c_llc_victims.local uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.LOCAL_ALL event=0x37,umask=0x2f  11     unc_c_llc_victims.m_state uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M event=0x37,umask=1  11     unc_c_llc_victims.remote uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL event=0x37,umask=0x80  11     unc_c_llc_victims.s_state uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S event=0x37,umask=4  11     unc_c_ring_src_thrtl uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_SRC_THRTL event=0xa4  11     unc_c_tor_inserts.evict uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.EVICT event=0x35,umask=2  11     unc_c_tor_inserts.hit uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.HIT event=0x35,umask=0x10  11     unc_c_tor_inserts.ipq uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IPQ event=0x35,umask=8  11     unc_c_tor_inserts.ipq_hit uncore cache This event is deprecated event=0x35,umask=0x18  11     unc_c_tor_inserts.ipq_miss uncore cache This event is deprecated event=0x35,umask=0x28  11     unc_c_tor_inserts.irq uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA event=0x35,umask=0x31  11     unc_c_tor_inserts.irq_hit uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT event=0x35,umask=0x11  11     unc_c_tor_inserts.irq_miss uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS event=0x35,umask=0x21  11     unc_c_tor_inserts.loc_all uncore cache This event is deprecated event=0x35,umask=0x37  11     unc_c_tor_inserts.loc_ia uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA event=0x35,umask=0x31  11     unc_c_tor_inserts.loc_io uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO event=0x35,umask=0x34  11     unc_c_tor_inserts.miss uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.MISS event=0x35,umask=0x20  11     unc_c_tor_inserts.prq uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.PRQ event=0x35,umask=4  11     unc_c_tor_inserts.prq_hit uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_HIT event=0x35,umask=0x14  11     unc_c_tor_inserts.prq_miss uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_MISS event=0x35,umask=0x24  11     unc_c_tor_inserts.rem_all uncore cache This event is deprecated event=0x35,umask=0x30  11     unc_c_tor_inserts.rrq_hit uncore cache This event is deprecated event=0x35,umask=0x50  11     unc_c_tor_inserts.rrq_miss uncore cache This event is deprecated event=0x35,umask=0x60  11     unc_c_tor_inserts.wbq_hit uncore cache This event is deprecated event=0x35,umask=0x90  11     unc_c_tor_inserts.wbq_miss uncore cache This event is deprecated event=0x35,umask=0xa0  11     unc_c_tor_occupancy.evict uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.EVICT event=0x36,umask=2  11     unc_c_tor_occupancy.hit uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.HIT event=0x36,umask=0x10  11     unc_c_tor_occupancy.ipq uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IPQ event=0x36,umask=8  11     unc_c_tor_occupancy.ipq_hit uncore cache This event is deprecated event=0x36,umask=0x18  11     unc_c_tor_occupancy.ipq_miss uncore cache This event is deprecated event=0x36,umask=0x28  11     unc_c_tor_occupancy.irq uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA event=0x36,umask=0x31  11     unc_c_tor_occupancy.irq_hit uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_HIT event=0x36,umask=0x11  11     unc_c_tor_occupancy.irq_miss uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_MISS event=0x36,umask=0x21  11     unc_c_tor_occupancy.loc_all uncore cache This event is deprecated event=0x36,umask=0x37  11     unc_c_tor_occupancy.loc_ia uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA event=0x36,umask=0x31  11     unc_c_tor_occupancy.loc_io uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO event=0x36,umask=0x34  11     unc_c_tor_occupancy.miss uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.MISS event=0x36,umask=0x20  11     unc_c_tor_occupancy.prq uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.PRQ event=0x36,umask=4  11     unc_c_tor_occupancy.prq_hit uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_HIT event=0x36,umask=0x14  11     unc_c_tor_occupancy.prq_miss uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_MISS event=0x36,umask=0x24  11     unc_h_ag0_ad_crd_acquired.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR0 event=0x80,umask=1  11     unc_h_ag0_ad_crd_acquired.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR1 event=0x80,umask=2  11     unc_h_ag0_ad_crd_acquired.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR2 event=0x80,umask=4  11     unc_h_ag0_ad_crd_acquired.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR3 event=0x80,umask=8  11     unc_h_ag0_ad_crd_acquired.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR4 event=0x80,umask=0x10  11     unc_h_ag0_ad_crd_acquired.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR5 event=0x80,umask=0x20  11     unc_h_ag0_ad_crd_occupancy.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR0 event=0x82,umask=1  11     unc_h_ag0_ad_crd_occupancy.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR1 event=0x82,umask=2  11     unc_h_ag0_ad_crd_occupancy.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR2 event=0x82,umask=4  11     unc_h_ag0_ad_crd_occupancy.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR3 event=0x82,umask=8  11     unc_h_ag0_ad_crd_occupancy.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR4 event=0x82,umask=0x10  11     unc_h_ag0_ad_crd_occupancy.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR5 event=0x82,umask=0x20  11     unc_h_ag0_bl_crd_acquired.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR0 event=0x88,umask=1  11     unc_h_ag0_bl_crd_acquired.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR1 event=0x88,umask=2  11     unc_h_ag0_bl_crd_acquired.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR2 event=0x88,umask=4  11     unc_h_ag0_bl_crd_acquired.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR3 event=0x88,umask=8  11     unc_h_ag0_bl_crd_acquired.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR4 event=0x88,umask=0x10  11     unc_h_ag0_bl_crd_acquired.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR5 event=0x88,umask=0x20  11     unc_h_ag0_bl_crd_occupancy.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR0 event=0x8a,umask=1  11     unc_h_ag0_bl_crd_occupancy.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR1 event=0x8a,umask=2  11     unc_h_ag0_bl_crd_occupancy.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR2 event=0x8a,umask=4  11     unc_h_ag0_bl_crd_occupancy.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR3 event=0x8a,umask=8  11     unc_h_ag0_bl_crd_occupancy.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR4 event=0x8a,umask=0x10  11     unc_h_ag0_bl_crd_occupancy.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR5 event=0x8a,umask=0x20  11     unc_h_ag1_ad_crd_acquired.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR0 event=0x84,umask=1  11     unc_h_ag1_ad_crd_acquired.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR1 event=0x84,umask=2  11     unc_h_ag1_ad_crd_acquired.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR2 event=0x84,umask=4  11     unc_h_ag1_ad_crd_acquired.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR3 event=0x84,umask=8  11     unc_h_ag1_ad_crd_acquired.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR4 event=0x84,umask=0x10  11     unc_h_ag1_ad_crd_acquired.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR5 event=0x84,umask=0x20  11     unc_h_ag1_ad_crd_occupancy.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR0 event=0x86,umask=1  11     unc_h_ag1_ad_crd_occupancy.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR1 event=0x86,umask=2  11     unc_h_ag1_ad_crd_occupancy.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR2 event=0x86,umask=4  11     unc_h_ag1_ad_crd_occupancy.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR3 event=0x86,umask=8  11     unc_h_ag1_ad_crd_occupancy.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR4 event=0x86,umask=0x10  11     unc_h_ag1_ad_crd_occupancy.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR5 event=0x86,umask=0x20  11     unc_h_ag1_bl_crd_occupancy.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR0 event=0x8e,umask=1  11     unc_h_ag1_bl_crd_occupancy.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR1 event=0x8e,umask=2  11     unc_h_ag1_bl_crd_occupancy.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR2 event=0x8e,umask=4  11     unc_h_ag1_bl_crd_occupancy.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR3 event=0x8e,umask=8  11     unc_h_ag1_bl_crd_occupancy.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR4 event=0x8e,umask=0x10  11     unc_h_ag1_bl_crd_occupancy.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR5 event=0x8e,umask=0x20  11     unc_h_ag1_bl_credits_acquired.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR0 event=0x8c,umask=1  11     unc_h_ag1_bl_credits_acquired.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR1 event=0x8c,umask=2  11     unc_h_ag1_bl_credits_acquired.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR2 event=0x8c,umask=4  11     unc_h_ag1_bl_credits_acquired.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR3 event=0x8c,umask=8  11     unc_h_ag1_bl_credits_acquired.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR4 event=0x8c,umask=0x10  11     unc_h_ag1_bl_credits_acquired.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR5 event=0x8c,umask=0x20  11     unc_h_bypass_cha_imc.intermediate uncore cache This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE event=0x57,umask=2  11     unc_h_bypass_cha_imc.not_taken uncore cache This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN event=0x57,umask=4  11     unc_h_bypass_cha_imc.taken uncore cache This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.TAKEN event=0x57,umask=1  11     unc_h_clock uncore cache This event is deprecated. Refer to new event UNC_CHA_CMS_CLOCKTICKS event=0xc0  11     unc_h_core_pma.c1_state uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C1_STATE event=0x17,umask=1  11     unc_h_core_pma.c1_transition uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C1_TRANSITION event=0x17,umask=2  11     unc_h_core_pma.c6_state uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C6_STATE event=0x17,umask=4  11     unc_h_core_pma.c6_transition uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C6_TRANSITION event=0x17,umask=8  11     unc_h_core_pma.gv uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.GV event=0x17,umask=0x10  11     unc_h_core_snp.any_gtone uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_GTONE event=0x33,umask=0xe2  11     unc_h_core_snp.any_one uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_ONE event=0x33,umask=0xe1  11     unc_h_core_snp.any_remote uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_REMOTE event=0x33,umask=0xe4  11     unc_h_core_snp.core_gtone uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_GTONE event=0x33,umask=0x42  11     unc_h_core_snp.core_one uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_ONE event=0x33,umask=0x41  11     unc_h_core_snp.core_remote uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_REMOTE event=0x33,umask=0x44  11     unc_h_core_snp.evict_gtone uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_GTONE event=0x33,umask=0x82  11     unc_h_core_snp.evict_one uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_ONE event=0x33,umask=0x81  11     unc_h_core_snp.evict_remote uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_REMOTE event=0x33,umask=0x84  11     unc_h_core_snp.ext_gtone uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_GTONE event=0x33,umask=0x22  11     unc_h_core_snp.ext_one uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_ONE event=0x33,umask=0x21  11     unc_h_core_snp.ext_remote uncore cache This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_REMOTE event=0x33,umask=0x24  11     unc_h_counter0_occupancy uncore cache This event is deprecated. Refer to new event UNC_CHA_COUNTER0_OCCUPANCY event=0x1f  11     unc_h_dir_lookup.no_snp uncore cache This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.NO_SNP event=0x53,umask=2  11     unc_h_dir_lookup.snp uncore cache This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.SNP event=0x53,umask=1  11     unc_h_dir_update.ha uncore cache This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.HA event=0x54,umask=1  11     unc_h_dir_update.tor uncore cache This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.TOR event=0x54,umask=2  11     unc_h_egress_ordering.iv_snoopgo_dn uncore cache This event is deprecated. Refer to new event UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN event=0xae,umask=4  11     unc_h_egress_ordering.iv_snoopgo_up uncore cache This event is deprecated. Refer to new event UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP event=0xae,umask=1  11     unc_h_hitme_hit.ex_rds uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.EX_RDS event=0x5f,umask=1  11     unc_h_hitme_hit.shared_ownreq uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.SHARED_OWNREQ event=0x5f,umask=4  11     unc_h_hitme_hit.wbmtoe uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.WBMTOE event=0x5f,umask=8  11     unc_h_hitme_hit.wbmtoi_or_s uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.WBMTOI_OR_S event=0x5f,umask=0x10  11     unc_h_hitme_lookup.read uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_LOOKUP.READ event=0x5e,umask=1  11     unc_h_hitme_lookup.write uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_LOOKUP.WRITE event=0x5e,umask=2  11     unc_h_hitme_miss.notshared_rdinvown uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN event=0x60,umask=0x40  11     unc_h_hitme_miss.read_or_inv uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.READ_OR_INV event=0x60,umask=0x80  11     unc_h_hitme_miss.shared_rdinvown uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.SHARED_RDINVOWN event=0x60,umask=0x20  11     unc_h_hitme_update.deallocate uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.DEALLOCATE event=0x61,umask=0x10  11     unc_h_hitme_update.deallocate_rspfwdi_loc uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC event=0x61,umask=1  11     unc_h_hitme_update.rdinvown uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.RDINVOWN event=0x61,umask=8  11     unc_h_hitme_update.rspfwdi_rem uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.RSPFWDI_REM event=0x61,umask=2  11     unc_h_hitme_update.shared uncore cache This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.SHARED event=0x61,umask=4  11     unc_h_horz_ring_ad_in_use.left_even uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN event=0xa7,umask=1  11     unc_h_horz_ring_ad_in_use.left_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD event=0xa7,umask=2  11     unc_h_horz_ring_ad_in_use.right_even uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN event=0xa7,umask=4  11     unc_h_horz_ring_ad_in_use.right_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD event=0xa7,umask=8  11     unc_h_horz_ring_ak_in_use.left_even uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN event=0xa9,umask=1  11     unc_h_horz_ring_ak_in_use.left_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD event=0xa9,umask=2  11     unc_h_horz_ring_ak_in_use.right_even uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN event=0xa9,umask=4  11     unc_h_horz_ring_ak_in_use.right_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD event=0xa9,umask=8  11     unc_h_horz_ring_bl_in_use.left_even uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN event=0xab,umask=1  11     unc_h_horz_ring_bl_in_use.left_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD event=0xab,umask=2  11     unc_h_horz_ring_bl_in_use.right_even uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN event=0xab,umask=4  11     unc_h_horz_ring_bl_in_use.right_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD event=0xab,umask=8  11     unc_h_horz_ring_iv_in_use.left uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_IV_IN_USE.LEFT event=0xad,umask=1  11     unc_h_horz_ring_iv_in_use.right uncore cache This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT event=0xad,umask=4  11     unc_h_imc_reads_count.normal uncore cache This event is deprecated. Refer to new event UNC_CHA_IMC_READS_COUNT.NORMAL event=0x59,umask=1  11     unc_h_imc_reads_count.priority uncore cache This event is deprecated. Refer to new event UNC_CHA_IMC_READS_COUNT.PRIORITY event=0x59,umask=2  11     unc_h_imc_writes_count.full uncore cache This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL event=0x5b,umask=1  11     unc_h_imc_writes_count.full_mig uncore cache This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL_MIG event=0x5b,umask=0x10  11     unc_h_imc_writes_count.full_priority uncore cache This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY event=0x5b,umask=4  11     unc_h_imc_writes_count.partial uncore cache This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL event=0x5b,umask=2  11     unc_h_imc_writes_count.partial_mig uncore cache This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL_MIG event=0x5b,umask=0x20  11     unc_h_imc_writes_count.partial_priority uncore cache This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY event=0x5b,umask=8  11     unc_h_iodc_alloc.invitom uncore cache This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.INVITOM event=0x62,umask=1  11     unc_h_iodc_alloc.iodcfull uncore cache This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.IODCFULL event=0x62,umask=2  11     unc_h_iodc_alloc.osbgated uncore cache This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.OSBGATED event=0x62,umask=4  11     unc_h_iodc_dealloc.all uncore cache This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.ALL event=0x63,umask=0x10  11     unc_h_iodc_dealloc.snpout uncore cache This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.SNPOUT event=0x63,umask=8  11     unc_h_iodc_dealloc.wbmtoe uncore cache This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBMTOE event=0x63,umask=1  11     unc_h_iodc_dealloc.wbmtoi uncore cache This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBMTOI event=0x63,umask=2  11     unc_h_iodc_dealloc.wbpushmtoi uncore cache This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBPUSHMTOI event=0x63,umask=4  11     unc_h_misc.cv0_pref_miss uncore cache This event is deprecated. Refer to new event UNC_CHA_MISC.CV0_PREF_MISS event=0x39,umask=0x20  11     unc_h_misc.cv0_pref_vic uncore cache This event is deprecated. Refer to new event UNC_CHA_MISC.CV0_PREF_VIC event=0x39,umask=0x10  11     unc_h_misc.rfo_hit_s uncore cache This event is deprecated. Refer to new event UNC_CHA_MISC.RFO_HIT_S event=0x39,umask=8  11     unc_h_misc.rspi_was_fse uncore cache This event is deprecated. Refer to new event UNC_CHA_MISC.RSPI_WAS_FSE event=0x39,umask=1  11     unc_h_misc.wc_aliasing uncore cache This event is deprecated. Refer to new event UNC_CHA_MISC.WC_ALIASING event=0x39,umask=2  11     unc_h_osb uncore cache This event is deprecated. Refer to new event UNC_CHA_OSB event=0x55  11     unc_h_read_no_credits.edc0_smi2 uncore cache This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC0_SMI2 event=0x58,umask=4  11     unc_h_read_no_credits.edc1_smi3 uncore cache This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC1_SMI3 event=0x58,umask=8  11     unc_h_read_no_credits.edc2_smi4 uncore cache This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC2_SMI4 event=0x58,umask=0x10  11     unc_h_read_no_credits.edc3_smi5 uncore cache This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC3_SMI5 event=0x58,umask=0x20  11     unc_h_read_no_credits.mc0_smi0 uncore cache This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.MC0_SMI0 event=0x58,umask=1  11     unc_h_read_no_credits.mc1_smi1 uncore cache This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.MC1_SMI1 event=0x58,umask=2  11     unc_h_requests.invitoe_local uncore cache This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_LOCAL event=0x50,umask=0x10  11     unc_h_requests.invitoe_remote uncore cache This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_REMOTE event=0x50,umask=0x20  11     unc_h_requests.reads uncore cache read requests from home agent event=0x50,umask=3  11     unc_h_requests.reads_local uncore cache read requests from local home agent event=0x50,umask=1  11     unc_h_requests.reads_remote uncore cache read requests from remote home agent event=0x50,umask=2  11     unc_h_requests.writes uncore cache write requests from home agent event=0x50,umask=0xc  11     unc_h_requests.writes_local uncore cache write requests from local home agent event=0x50,umask=4  11     unc_h_requests.writes_remote uncore cache write requests from remote home agent event=0x50,umask=8  11     unc_h_ring_bounces_horz.ad uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.AD event=0xa1,umask=1  11     unc_h_ring_bounces_horz.ak uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.AK event=0xa1,umask=2  11     unc_h_ring_bounces_horz.bl uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.BL event=0xa1,umask=4  11     unc_h_ring_bounces_horz.iv uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.IV event=0xa1,umask=8  11     unc_h_ring_bounces_vert.ad uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.AD event=0xa0,umask=1  11     unc_h_ring_bounces_vert.ak uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.AK event=0xa0,umask=2  11     unc_h_ring_bounces_vert.bl uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.BL event=0xa0,umask=4  11     unc_h_ring_bounces_vert.iv uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.IV event=0xa0,umask=8  11     unc_h_ring_sink_starved_horz.ad uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AD event=0xa3,umask=1  11     unc_h_ring_sink_starved_horz.ak uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AK event=0xa3,umask=2  11     unc_h_ring_sink_starved_horz.ak_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1 event=0xa3,umask=0x20  11     unc_h_ring_sink_starved_horz.bl uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.BL event=0xa3,umask=4  11     unc_h_ring_sink_starved_horz.iv uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.IV event=0xa3,umask=8  11     unc_h_ring_sink_starved_vert.ad uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.AD event=0xa2,umask=1  11     unc_h_ring_sink_starved_vert.ak uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.AK event=0xa2,umask=2  11     unc_h_ring_sink_starved_vert.bl uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.BL event=0xa2,umask=4  11     unc_h_ring_sink_starved_vert.iv uncore cache This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.IV event=0xa2,umask=8  11     unc_h_rxc_inserts.ipq uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IPQ event=0x13,umask=4  11     unc_h_rxc_inserts.irq uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ event=0x13,umask=1  11     unc_h_rxc_inserts.irq_rej uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ_REJ event=0x13,umask=2  11     unc_h_rxc_inserts.prq uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.PRQ event=0x13,umask=0x10  11     unc_h_rxc_inserts.prq_rej uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.PRQ_REJ event=0x13,umask=0x20  11     unc_h_rxc_inserts.rrq uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.RRQ event=0x13,umask=0x40  11     unc_h_rxc_inserts.wbq uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.WBQ event=0x13,umask=0x80  11     unc_h_rxc_ipq0_reject.ad_req_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0 event=0x22,umask=1  11     unc_h_rxc_ipq0_reject.ad_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0 event=0x22,umask=2  11     unc_h_rxc_ipq0_reject.bl_ncb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0 event=0x22,umask=0x10  11     unc_h_rxc_ipq0_reject.bl_ncs_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0 event=0x22,umask=0x20  11     unc_h_rxc_ipq0_reject.bl_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0 event=0x22,umask=4  11     unc_h_rxc_ipq0_reject.bl_wb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0 event=0x22,umask=8  11     unc_h_rxc_ipq1_reject.allow_snp uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP event=0x23,umask=0x40  11     unc_h_rxc_ipq1_reject.any_ipq0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.ANY0 event=0x23,umask=1  11     unc_h_rxc_ipq1_reject.ha uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.HA event=0x23,umask=2  11     unc_h_rxc_ipq1_reject.llc_or_sf_way uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY event=0x23,umask=0x20  11     unc_h_rxc_ipq1_reject.llc_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM event=0x23,umask=4  11     unc_h_rxc_ipq1_reject.pa_match uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH event=0x23,umask=0x80  11     unc_h_rxc_ipq1_reject.sf_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM event=0x23,umask=8  11     unc_h_rxc_ipq1_reject.victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.VICTIM event=0x23,umask=0x10  11     unc_h_rxc_irq0_reject.ad_req_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0 event=0x18,umask=1  11     unc_h_rxc_irq0_reject.ad_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0 event=0x18,umask=2  11     unc_h_rxc_irq0_reject.bl_ncb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0 event=0x18,umask=0x10  11     unc_h_rxc_irq0_reject.bl_ncs_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0 event=0x18,umask=0x20  11     unc_h_rxc_irq0_reject.bl_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0 event=0x18,umask=4  11     unc_h_rxc_irq0_reject.bl_wb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0 event=0x18,umask=8  11     unc_h_rxc_irq1_reject.allow_snp uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP event=0x19,umask=0x40  11     unc_h_rxc_irq1_reject.any_reject_irq0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.ANY0 event=0x19,umask=1  11     unc_h_rxc_irq1_reject.ha uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.HA event=0x19,umask=2  11     unc_h_rxc_irq1_reject.llc_or_sf_way uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY event=0x19,umask=0x20  11     unc_h_rxc_irq1_reject.llc_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM event=0x19,umask=4  11     unc_h_rxc_irq1_reject.pa_match uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH event=0x19,umask=0x80  11     unc_h_rxc_irq1_reject.sf_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM event=0x19,umask=8  11     unc_h_rxc_irq1_reject.victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.VICTIM event=0x19,umask=0x10  11     unc_h_rxc_ismq0_reject.ad_req_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0 event=0x24,umask=1  11     unc_h_rxc_ismq0_reject.ad_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0 event=0x24,umask=2  11     unc_h_rxc_ismq0_reject.bl_ncb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0 event=0x24,umask=0x10  11     unc_h_rxc_ismq0_reject.bl_ncs_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0 event=0x24,umask=0x20  11     unc_h_rxc_ismq0_reject.bl_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0 event=0x24,umask=4  11     unc_h_rxc_ismq0_reject.bl_wb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0 event=0x24,umask=8  11     unc_h_rxc_ismq0_retry.ad_req_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0 event=0x2c,umask=1  11     unc_h_rxc_ismq0_retry.ad_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0 event=0x2c,umask=2  11     unc_h_rxc_ismq0_retry.bl_ncb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0 event=0x2c,umask=0x10  11     unc_h_rxc_ismq0_retry.bl_ncs_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0 event=0x2c,umask=0x20  11     unc_h_rxc_ismq0_retry.bl_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0 event=0x2c,umask=4  11     unc_h_rxc_ismq0_retry.bl_wb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0 event=0x2c,umask=8  11     unc_h_rxc_ismq1_reject.any_ismq0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_REJECT.ANY0 event=0x25,umask=1  11     unc_h_rxc_ismq1_reject.ha uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_REJECT.HA event=0x25,umask=2  11     unc_h_rxc_ismq1_retry.any uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_RETRY.ANY0 event=0x2d,umask=1  11     unc_h_rxc_ismq1_retry.ha uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_RETRY.HA event=0x2d,umask=2  11     unc_h_rxc_occupancy.ipq uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IPQ event=0x11,umask=4  11     unc_h_rxc_occupancy.irq uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IRQ event=0x11,umask=1  11     unc_h_rxc_occupancy.rrq uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.RRQ event=0x11,umask=0x40  11     unc_h_rxc_occupancy.wbq uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.WBQ event=0x11,umask=0x80  11     unc_h_rxc_other0_retry.ad_req_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0 event=0x2e,umask=1  11     unc_h_rxc_other0_retry.ad_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0 event=0x2e,umask=2  11     unc_h_rxc_other0_retry.bl_ncb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0 event=0x2e,umask=0x10  11     unc_h_rxc_other0_retry.bl_ncs_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0 event=0x2e,umask=0x20  11     unc_h_rxc_other0_retry.bl_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0 event=0x2e,umask=4  11     unc_h_rxc_other0_retry.bl_wb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0 event=0x2e,umask=8  11     unc_h_rxc_other1_retry.allow_snp uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP event=0x2f,umask=0x40  11     unc_h_rxc_other1_retry.any uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.ANY0 event=0x2f,umask=1  11     unc_h_rxc_other1_retry.ha uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.HA event=0x2f,umask=2  11     unc_h_rxc_other1_retry.llc_or_sf_way uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY event=0x2f,umask=0x20  11     unc_h_rxc_other1_retry.llc_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM event=0x2f,umask=4  11     unc_h_rxc_other1_retry.pa_match uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH event=0x2f,umask=0x80  11     unc_h_rxc_other1_retry.sf_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM event=0x2f,umask=8  11     unc_h_rxc_other1_retry.victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.VICTIM event=0x2f,umask=0x10  11     unc_h_rxc_prq0_reject.ad_req_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0 event=0x20,umask=1  11     unc_h_rxc_prq0_reject.ad_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0 event=0x20,umask=2  11     unc_h_rxc_prq0_reject.bl_ncb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0 event=0x20,umask=0x10  11     unc_h_rxc_prq0_reject.bl_ncs_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0 event=0x20,umask=0x20  11     unc_h_rxc_prq0_reject.bl_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0 event=0x20,umask=4  11     unc_h_rxc_prq0_reject.bl_wb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0 event=0x20,umask=8  11     unc_h_rxc_prq1_reject.allow_snp uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP event=0x21,umask=0x40  11     unc_h_rxc_prq1_reject.any_prq0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.ANY0 event=0x21,umask=1  11     unc_h_rxc_prq1_reject.ha uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.HA event=0x21,umask=2  11     unc_h_rxc_prq1_reject.llc_or_sf_way uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY event=0x21,umask=0x20  11     unc_h_rxc_prq1_reject.llc_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM event=0x21,umask=4  11     unc_h_rxc_prq1_reject.pa_match uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH event=0x21,umask=0x80  11     unc_h_rxc_prq1_reject.sf_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM event=0x21,umask=8  11     unc_h_rxc_prq1_reject.victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.VICTIM event=0x21,umask=0x10  11     unc_h_rxc_req_q0_retry.ad_req_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0 event=0x2a,umask=1  11     unc_h_rxc_req_q0_retry.ad_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0 event=0x2a,umask=2  11     unc_h_rxc_req_q0_retry.bl_ncb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0 event=0x2a,umask=0x10  11     unc_h_rxc_req_q0_retry.bl_ncs_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0 event=0x2a,umask=0x20  11     unc_h_rxc_req_q0_retry.bl_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0 event=0x2a,umask=4  11     unc_h_rxc_req_q0_retry.bl_wb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0 event=0x2a,umask=8  11     unc_h_rxc_req_q1_retry.allow_snp uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP event=0x2b,umask=0x40  11     unc_h_rxc_req_q1_retry.any uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.ANY0 event=0x2b,umask=1  11     unc_h_rxc_req_q1_retry.ha uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.HA event=0x2b,umask=2  11     unc_h_rxc_req_q1_retry.llc_or_sf_way uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY event=0x2b,umask=0x20  11     unc_h_rxc_req_q1_retry.llc_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM event=0x2b,umask=4  11     unc_h_rxc_req_q1_retry.pa_match uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH event=0x2b,umask=0x80  11     unc_h_rxc_req_q1_retry.sf_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM event=0x2b,umask=8  11     unc_h_rxc_req_q1_retry.victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM event=0x2b,umask=0x10  11     unc_h_rxc_rrq0_reject.ad_req_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0 event=0x26,umask=1  11     unc_h_rxc_rrq0_reject.ad_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0 event=0x26,umask=2  11     unc_h_rxc_rrq0_reject.bl_ncb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0 event=0x26,umask=0x10  11     unc_h_rxc_rrq0_reject.bl_ncs_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0 event=0x26,umask=0x20  11     unc_h_rxc_rrq0_reject.bl_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0 event=0x26,umask=4  11     unc_h_rxc_rrq0_reject.bl_wb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0 event=0x26,umask=8  11     unc_h_rxc_rrq1_reject.allow_snp uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP event=0x27,umask=0x40  11     unc_h_rxc_rrq1_reject.any_rrq0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.ANY0 event=0x27,umask=1  11     unc_h_rxc_rrq1_reject.ha uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.HA event=0x27,umask=2  11     unc_h_rxc_rrq1_reject.llc_or_sf_way uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY event=0x27,umask=0x20  11     unc_h_rxc_rrq1_reject.llc_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM event=0x27,umask=4  11     unc_h_rxc_rrq1_reject.pa_match uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH event=0x27,umask=0x80  11     unc_h_rxc_rrq1_reject.sf_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM event=0x27,umask=8  11     unc_h_rxc_rrq1_reject.victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.VICTIM event=0x27,umask=0x10  11     unc_h_rxc_wbq0_reject.ad_req_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0 event=0x28,umask=1  11     unc_h_rxc_wbq0_reject.ad_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0 event=0x28,umask=2  11     unc_h_rxc_wbq0_reject.bl_ncb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0 event=0x28,umask=0x10  11     unc_h_rxc_wbq0_reject.bl_ncs_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0 event=0x28,umask=0x20  11     unc_h_rxc_wbq0_reject.bl_rsp_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0 event=0x28,umask=4  11     unc_h_rxc_wbq0_reject.bl_wb_vn0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0 event=0x28,umask=8  11     unc_h_rxc_wbq1_reject.allow_snp uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP event=0x29,umask=0x40  11     unc_h_rxc_wbq1_reject.any_wbq0 uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.ANY0 event=0x29,umask=1  11     unc_h_rxc_wbq1_reject.ha uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.HA event=0x29,umask=2  11     unc_h_rxc_wbq1_reject.llc_or_sf_way uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY event=0x29,umask=0x20  11     unc_h_rxc_wbq1_reject.llc_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM event=0x29,umask=4  11     unc_h_rxc_wbq1_reject.pa_match uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH event=0x29,umask=0x80  11     unc_h_rxc_wbq1_reject.sf_victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM event=0x29,umask=8  11     unc_h_rxc_wbq1_reject.victim uncore cache This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.VICTIM event=0x29,umask=0x10  11     unc_h_rxr_busy_starved.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.AD_BNC event=0xb4,umask=1  11     unc_h_rxr_busy_starved.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.AD_CRD event=0xb4,umask=0x10  11     unc_h_rxr_busy_starved.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.BL_BNC event=0xb4,umask=4  11     unc_h_rxr_busy_starved.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.BL_CRD event=0xb4,umask=0x40  11     unc_h_rxr_bypass.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AD_BNC event=0xb2,umask=1  11     unc_h_rxr_bypass.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AD_CRD event=0xb2,umask=0x10  11     unc_h_rxr_bypass.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AK_BNC event=0xb2,umask=2  11     unc_h_rxr_bypass.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.BL_BNC event=0xb2,umask=4  11     unc_h_rxr_bypass.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.BL_CRD event=0xb2,umask=0x40  11     unc_h_rxr_bypass.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.IV_BNC event=0xb2,umask=8  11     unc_h_rxr_crd_starved.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AD_BNC event=0xb3,umask=1  11     unc_h_rxr_crd_starved.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AD_CRD event=0xb3,umask=0x10  11     unc_h_rxr_crd_starved.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AK_BNC event=0xb3,umask=2  11     unc_h_rxr_crd_starved.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.BL_BNC event=0xb3,umask=4  11     unc_h_rxr_crd_starved.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.BL_CRD event=0xb3,umask=0x40  11     unc_h_rxr_crd_starved.ifv uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.IFV event=0xb3,umask=0x80  11     unc_h_rxr_crd_starved.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.IV_BNC event=0xb3,umask=8  11     unc_h_rxr_inserts.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AD_BNC event=0xb1,umask=1  11     unc_h_rxr_inserts.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AD_CRD event=0xb1,umask=0x10  11     unc_h_rxr_inserts.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AK_BNC event=0xb1,umask=2  11     unc_h_rxr_inserts.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.BL_BNC event=0xb1,umask=4  11     unc_h_rxr_inserts.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.BL_CRD event=0xb1,umask=0x40  11     unc_h_rxr_inserts.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.IV_BNC event=0xb1,umask=8  11     unc_h_rxr_occupancy.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AD_BNC event=0xb0,umask=1  11     unc_h_rxr_occupancy.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AD_CRD event=0xb0,umask=0x10  11     unc_h_rxr_occupancy.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AK_BNC event=0xb0,umask=2  11     unc_h_rxr_occupancy.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.BL_BNC event=0xb0,umask=4  11     unc_h_rxr_occupancy.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.BL_CRD event=0xb0,umask=0x40  11     unc_h_rxr_occupancy.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.IV_BNC event=0xb0,umask=8  11     unc_h_sf_eviction.e_state uncore cache This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.E_STATE event=0x3d,umask=2  11     unc_h_sf_eviction.m_state uncore cache This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.M_STATE event=0x3d,umask=1  11     unc_h_sf_eviction.s_state uncore cache This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.S_STATE event=0x3d,umask=4  11     unc_h_snoops_sent. uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.ALL event=0x51,umask=1  11     unc_h_snoops_sent.bcst_loc uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_LOCAL event=0x51,umask=0x10  11     unc_h_snoops_sent.bcst_rem uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_REMOTE event=0x51,umask=0x20  11     unc_h_snoops_sent.direct_loc uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL event=0x51,umask=0x40  11     unc_h_snoops_sent.direct_rem uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE event=0x51,umask=0x80  11     unc_h_snoops_sent.local uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.LOCAL event=0x51,umask=4  11     unc_h_snoops_sent.remote uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.REMOTE event=0x51,umask=8  11     unc_h_snoop_resp.rspcnflct uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPCNFLCTS event=0x5c,umask=0x40  11     unc_h_snoop_resp.rspfwd uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPFWD event=0x5c,umask=0x80  11     unc_h_snoop_resp.rspi uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPI event=0x5c,umask=1  11     unc_h_snoop_resp.rspifwd uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPIFWD event=0x5c,umask=4  11     unc_h_snoop_resp.rsps uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPS event=0x5c,umask=2  11     unc_h_snoop_resp.rspsfwd uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPSFWD event=0x5c,umask=8  11     unc_h_snoop_resp.rsp_fwd_wb uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_FWD_WB event=0x5c,umask=0x20  11     unc_h_snoop_resp.rsp_wb uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_WBWB event=0x5c,umask=0x10  11     unc_h_snp_rsp_rcv_local.rspcnflct uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT event=0x5d,umask=0x40  11     unc_h_snp_rsp_rcv_local.rspfwd uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD event=0x5d,umask=0x80  11     unc_h_snp_rsp_rcv_local.rspi uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPI event=0x5d,umask=1  11     unc_h_snp_rsp_rcv_local.rspifwd uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD event=0x5d,umask=4  11     unc_h_snp_rsp_rcv_local.rsps uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPS event=0x5d,umask=2  11     unc_h_snp_rsp_rcv_local.rspsfwd uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD event=0x5d,umask=8  11     unc_h_snp_rsp_rcv_local.rsp_fwd_wb uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB event=0x5d,umask=0x20  11     unc_h_snp_rsp_rcv_local.rsp_wb uncore cache This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB event=0x5d,umask=0x10  11     unc_h_stall_no_txr_horz_crd_ad_ag0.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0 event=0xd0,umask=1  11     unc_h_stall_no_txr_horz_crd_ad_ag0.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1 event=0xd0,umask=2  11     unc_h_stall_no_txr_horz_crd_ad_ag0.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2 event=0xd0,umask=4  11     unc_h_stall_no_txr_horz_crd_ad_ag0.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3 event=0xd0,umask=8  11     unc_h_stall_no_txr_horz_crd_ad_ag0.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4 event=0xd0,umask=0x10  11     unc_h_stall_no_txr_horz_crd_ad_ag0.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5 event=0xd0,umask=0x20  11     unc_h_stall_no_txr_horz_crd_ad_ag1.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0 event=0xd2,umask=1  11     unc_h_stall_no_txr_horz_crd_ad_ag1.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1 event=0xd2,umask=2  11     unc_h_stall_no_txr_horz_crd_ad_ag1.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2 event=0xd2,umask=4  11     unc_h_stall_no_txr_horz_crd_ad_ag1.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3 event=0xd2,umask=8  11     unc_h_stall_no_txr_horz_crd_ad_ag1.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4 event=0xd2,umask=0x10  11     unc_h_stall_no_txr_horz_crd_ad_ag1.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5 event=0xd2,umask=0x20  11     unc_h_stall_no_txr_horz_crd_bl_ag0.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0 event=0xd4,umask=1  11     unc_h_stall_no_txr_horz_crd_bl_ag0.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1 event=0xd4,umask=2  11     unc_h_stall_no_txr_horz_crd_bl_ag0.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2 event=0xd4,umask=4  11     unc_h_stall_no_txr_horz_crd_bl_ag0.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3 event=0xd4,umask=8  11     unc_h_stall_no_txr_horz_crd_bl_ag0.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4 event=0xd4,umask=0x10  11     unc_h_stall_no_txr_horz_crd_bl_ag0.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5 event=0xd4,umask=0x20  11     unc_h_stall_no_txr_horz_crd_bl_ag1.tgr0 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0 event=0xd6,umask=1  11     unc_h_stall_no_txr_horz_crd_bl_ag1.tgr1 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1 event=0xd6,umask=2  11     unc_h_stall_no_txr_horz_crd_bl_ag1.tgr2 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2 event=0xd6,umask=4  11     unc_h_stall_no_txr_horz_crd_bl_ag1.tgr3 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3 event=0xd6,umask=8  11     unc_h_stall_no_txr_horz_crd_bl_ag1.tgr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4 event=0xd6,umask=0x10  11     unc_h_stall_no_txr_horz_crd_bl_ag1.tgr5 uncore cache This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5 event=0xd6,umask=0x20  11     unc_h_txr_horz_ads_used.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AD_BNC event=0x9d,umask=1  11     unc_h_txr_horz_ads_used.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD event=0x9d,umask=0x10  11     unc_h_txr_horz_ads_used.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AK_BNC event=0x9d,umask=2  11     unc_h_txr_horz_ads_used.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.BL_BNC event=0x9d,umask=4  11     unc_h_txr_horz_ads_used.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD event=0x9d,umask=0x40  11     unc_h_txr_horz_bypass.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AD_BNC event=0x9f,umask=1  11     unc_h_txr_horz_bypass.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AD_CRD event=0x9f,umask=0x10  11     unc_h_txr_horz_bypass.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AK_BNC event=0x9f,umask=2  11     unc_h_txr_horz_bypass.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.BL_BNC event=0x9f,umask=4  11     unc_h_txr_horz_bypass.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.BL_CRD event=0x9f,umask=0x40  11     unc_h_txr_horz_bypass.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.IV_BNC event=0x9f,umask=8  11     unc_h_txr_horz_cycles_full.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_BNC event=0x96,umask=1  11     unc_h_txr_horz_cycles_full.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD event=0x96,umask=0x10  11     unc_h_txr_horz_cycles_full.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AK_BNC event=0x96,umask=2  11     unc_h_txr_horz_cycles_full.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_BNC event=0x96,umask=4  11     unc_h_txr_horz_cycles_full.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD event=0x96,umask=0x40  11     unc_h_txr_horz_cycles_full.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.IV_BNC event=0x96,umask=8  11     unc_h_txr_horz_cycles_ne.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AD_BNC event=0x97,umask=1  11     unc_h_txr_horz_cycles_ne.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD event=0x97,umask=0x10  11     unc_h_txr_horz_cycles_ne.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AK_BNC event=0x97,umask=2  11     unc_h_txr_horz_cycles_ne.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.BL_BNC event=0x97,umask=4  11     unc_h_txr_horz_cycles_ne.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD event=0x97,umask=0x40  11     unc_h_txr_horz_cycles_ne.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.IV_BNC event=0x97,umask=8  11     unc_h_txr_horz_inserts.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AD_BNC event=0x95,umask=1  11     unc_h_txr_horz_inserts.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AD_CRD event=0x95,umask=0x10  11     unc_h_txr_horz_inserts.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AK_BNC event=0x95,umask=2  11     unc_h_txr_horz_inserts.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.BL_BNC event=0x95,umask=4  11     unc_h_txr_horz_inserts.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.BL_CRD event=0x95,umask=0x40  11     unc_h_txr_horz_inserts.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.IV_BNC event=0x95,umask=8  11     unc_h_txr_horz_nack.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AD_BNC event=0x99,umask=1  11     unc_h_txr_horz_nack.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AD_CRD event=0x99,umask=0x20  11     unc_h_txr_horz_nack.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AK_BNC event=0x99,umask=2  11     unc_h_txr_horz_nack.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.BL_BNC event=0x99,umask=4  11     unc_h_txr_horz_nack.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.BL_CRD event=0x99,umask=0x40  11     unc_h_txr_horz_nack.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.IV_BNC event=0x99,umask=8  11     unc_h_txr_horz_occupancy.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AD_BNC event=0x94,umask=1  11     unc_h_txr_horz_occupancy.ad_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD event=0x94,umask=0x10  11     unc_h_txr_horz_occupancy.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AK_BNC event=0x94,umask=2  11     unc_h_txr_horz_occupancy.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.BL_BNC event=0x94,umask=4  11     unc_h_txr_horz_occupancy.bl_crd uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD event=0x94,umask=0x40  11     unc_h_txr_horz_occupancy.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.IV_BNC event=0x94,umask=8  11     unc_h_txr_horz_starved.ad_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.AD_BNC event=0x9b,umask=1  11     unc_h_txr_horz_starved.ak_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.AK_BNC event=0x9b,umask=2  11     unc_h_txr_horz_starved.bl_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.BL_BNC event=0x9b,umask=4  11     unc_h_txr_horz_starved.iv_bnc uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.IV_BNC event=0x9b,umask=8  11     unc_h_txr_vert_ads_used.ad_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AD_AG0 event=0x9c,umask=1  11     unc_h_txr_vert_ads_used.ad_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AD_AG1 event=0x9c,umask=0x10  11     unc_h_txr_vert_ads_used.ak_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AK_AG0 event=0x9c,umask=2  11     unc_h_txr_vert_ads_used.ak_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AK_AG1 event=0x9c,umask=0x20  11     unc_h_txr_vert_ads_used.bl_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.BL_AG0 event=0x9c,umask=4  11     unc_h_txr_vert_ads_used.bl_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.BL_AG1 event=0x9c,umask=0x40  11     unc_h_txr_vert_bypass.ad_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AD_AG0 event=0x9e,umask=1  11     unc_h_txr_vert_bypass.ad_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AD_AG1 event=0x9e,umask=0x10  11     unc_h_txr_vert_bypass.ak_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AK_AG0 event=0x9e,umask=2  11     unc_h_txr_vert_bypass.ak_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AK_AG1 event=0x9e,umask=0x20  11     unc_h_txr_vert_bypass.bl_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.BL_AG0 event=0x9e,umask=4  11     unc_h_txr_vert_bypass.bl_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.BL_AG1 event=0x9e,umask=0x40  11     unc_h_txr_vert_bypass.iv_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.IV event=0x9e,umask=8  11     unc_h_txr_vert_cycles_full.ad_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG0 event=0x92,umask=1  11     unc_h_txr_vert_cycles_full.ad_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG1 event=0x92,umask=0x10  11     unc_h_txr_vert_cycles_full.ak_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG0 event=0x92,umask=2  11     unc_h_txr_vert_cycles_full.ak_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG1 event=0x92,umask=0x20  11     unc_h_txr_vert_cycles_full.bl_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG0 event=0x92,umask=4  11     unc_h_txr_vert_cycles_full.bl_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG1 event=0x92,umask=0x40  11     unc_h_txr_vert_cycles_full.iv_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.IV event=0x92,umask=8  11     unc_h_txr_vert_cycles_ne.ad_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG0 event=0x93,umask=1  11     unc_h_txr_vert_cycles_ne.ad_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG1 event=0x93,umask=0x10  11     unc_h_txr_vert_cycles_ne.ak_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG0 event=0x93,umask=2  11     unc_h_txr_vert_cycles_ne.ak_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG1 event=0x93,umask=0x20  11     unc_h_txr_vert_cycles_ne.bl_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG0 event=0x93,umask=4  11     unc_h_txr_vert_cycles_ne.bl_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG1 event=0x93,umask=0x40  11     unc_h_txr_vert_cycles_ne.iv_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.IV event=0x93,umask=8  11     unc_h_txr_vert_inserts.ad_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AD_AG0 event=0x91,umask=1  11     unc_h_txr_vert_inserts.ad_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AD_AG1 event=0x91,umask=0x10  11     unc_h_txr_vert_inserts.ak_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AK_AG0 event=0x91,umask=2  11     unc_h_txr_vert_inserts.ak_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AK_AG1 event=0x91,umask=0x20  11     unc_h_txr_vert_inserts.bl_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.BL_AG0 event=0x91,umask=4  11     unc_h_txr_vert_inserts.bl_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.BL_AG1 event=0x91,umask=0x40  11     unc_h_txr_vert_inserts.iv_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.IV event=0x91,umask=8  11     unc_h_txr_vert_nack.ad_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AD_AG0 event=0x98,umask=1  11     unc_h_txr_vert_nack.ad_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AD_AG1 event=0x98,umask=0x10  11     unc_h_txr_vert_nack.ak_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AK_AG0 event=0x98,umask=2  11     unc_h_txr_vert_nack.ak_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AK_AG1 event=0x98,umask=0x20  11     unc_h_txr_vert_nack.bl_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.BL_AG0 event=0x98,umask=4  11     unc_h_txr_vert_nack.bl_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.BL_AG1 event=0x98,umask=0x40  11     unc_h_txr_vert_nack.iv uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.IV event=0x98,umask=8  11     unc_h_txr_vert_occupancy.ad_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG0 event=0x90,umask=1  11     unc_h_txr_vert_occupancy.ad_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG1 event=0x90,umask=0x10  11     unc_h_txr_vert_occupancy.ak_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG0 event=0x90,umask=2  11     unc_h_txr_vert_occupancy.ak_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG1 event=0x90,umask=0x20  11     unc_h_txr_vert_occupancy.bl_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG0 event=0x90,umask=4  11     unc_h_txr_vert_occupancy.bl_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG1 event=0x90,umask=0x40  11     unc_h_txr_vert_occupancy.iv_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.IV event=0x90,umask=8  11     unc_h_txr_vert_starved.ad_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AD_AG0 event=0x9a,umask=1  11     unc_h_txr_vert_starved.ad_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AD_AG1 event=0x9a,umask=0x10  11     unc_h_txr_vert_starved.ak_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AK_AG0 event=0x9a,umask=2  11     unc_h_txr_vert_starved.ak_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AK_AG1 event=0x9a,umask=0x20  11     unc_h_txr_vert_starved.bl_ag0 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.BL_AG0 event=0x9a,umask=4  11     unc_h_txr_vert_starved.bl_ag1 uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.BL_AG1 event=0x9a,umask=0x40  11     unc_h_txr_vert_starved.iv uncore cache This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.IV event=0x9a,umask=8  11     unc_h_vert_ring_ad_in_use.dn_even uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN event=0xa6,umask=4  11     unc_h_vert_ring_ad_in_use.dn_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD event=0xa6,umask=8  11     unc_h_vert_ring_ad_in_use.up_even uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN event=0xa6,umask=1  11     unc_h_vert_ring_ad_in_use.up_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD event=0xa6,umask=2  11     unc_h_vert_ring_ak_in_use.dn_even uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN event=0xa8,umask=4  11     unc_h_vert_ring_ak_in_use.dn_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD event=0xa8,umask=8  11     unc_h_vert_ring_ak_in_use.up_even uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN event=0xa8,umask=1  11     unc_h_vert_ring_ak_in_use.up_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD event=0xa8,umask=2  11     unc_h_vert_ring_bl_in_use.dn_even uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN event=0xaa,umask=4  11     unc_h_vert_ring_bl_in_use.dn_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD event=0xaa,umask=8  11     unc_h_vert_ring_bl_in_use.up_even uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN event=0xaa,umask=1  11     unc_h_vert_ring_bl_in_use.up_odd uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD event=0xaa,umask=2  11     unc_h_vert_ring_iv_in_use.dn uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_IV_IN_USE.DN event=0xac,umask=4  11     unc_h_vert_ring_iv_in_use.up uncore cache This event is deprecated. Refer to new event UNC_CHA_VERT_RING_IV_IN_USE.UP event=0xac,umask=1  11     unc_h_wb_push_mtoi.llc uncore cache This event is deprecated. Refer to new event UNC_CHA_WB_PUSH_MTOI.LLC event=0x56,umask=1  11     unc_h_wb_push_mtoi.mem uncore cache This event is deprecated. Refer to new event UNC_CHA_WB_PUSH_MTOI.MEM event=0x56,umask=2  11     unc_h_write_no_credits.edc0_smi2 uncore cache This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC0_SMI2 event=0x5a,umask=4  11     unc_h_write_no_credits.edc1_smi3 uncore cache This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC1_SMI3 event=0x5a,umask=8  11     unc_h_write_no_credits.edc2_smi4 uncore cache This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC2_SMI4 event=0x5a,umask=0x10  11     unc_h_write_no_credits.edc3_smi5 uncore cache This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC3_SMI5 event=0x5a,umask=0x20  11     unc_h_write_no_credits.mc0_smi0 uncore cache This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.MC0_SMI0 event=0x5a,umask=1  11     unc_h_write_no_credits.mc1_smi1 uncore cache This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.MC1_SMI1 event=0x5a,umask=2  11     unc_h_xsnp_resp.any_rspi_fwdfe uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPI_FWDFE event=0x32,umask=0xe4  11     unc_h_xsnp_resp.any_rspi_fwdm uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPI_FWDM event=0x32,umask=0xf0  11     unc_h_xsnp_resp.any_rsps_fwdfe uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPS_FWDFE event=0x32,umask=0xe2  11     unc_h_xsnp_resp.any_rsps_fwdm uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPS_FWDM event=0x32,umask=0xe8  11     unc_h_xsnp_resp.any_rsp_hitfse uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSP_HITFSE event=0x32,umask=0xe1  11     unc_h_xsnp_resp.core_rspi_fwdfe uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPI_FWDFE event=0x32,umask=0x44  11     unc_h_xsnp_resp.core_rspi_fwdm uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPI_FWDM event=0x32,umask=0x50  11     unc_h_xsnp_resp.core_rsps_fwdfe uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPS_FWDFE event=0x32,umask=0x42  11     unc_h_xsnp_resp.core_rsps_fwdm uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPS_FWDM event=0x32,umask=0x48  11     unc_h_xsnp_resp.core_rsp_hitfse uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSP_HITFSE event=0x32,umask=0x41  11     unc_h_xsnp_resp.evict_rspi_fwdfe uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDFE event=0x32,umask=0x84  11     unc_h_xsnp_resp.evict_rspi_fwdm uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDM event=0x32,umask=0x90  11     unc_h_xsnp_resp.evict_rsps_fwdfe uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDFE event=0x32,umask=0x82  11     unc_h_xsnp_resp.evict_rsps_fwdm uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDM event=0x32,umask=0x88  11     unc_h_xsnp_resp.evict_rsp_hitfse uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSP_HITFSE event=0x32,umask=0x81  11     unc_h_xsnp_resp.ext_rspi_fwdfe uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPI_FWDFE event=0x32,umask=0x24  11     unc_h_xsnp_resp.ext_rspi_fwdm uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPI_FWDM event=0x32,umask=0x30  11     unc_h_xsnp_resp.ext_rsps_fwdfe uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPS_FWDFE event=0x32,umask=0x22  11     unc_h_xsnp_resp.ext_rsps_fwdm uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPS_FWDM event=0x32,umask=0x28  11     unc_h_xsnp_resp.ext_rsp_hitfse uncore cache This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSP_HITFSE event=0x32,umask=0x21  11     unc_i_cache_total_occupancy.any uncore interconnect Total Write Cache Occupancy; Any Source event=0xf,umask=1  01    Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port unc_i_cache_total_occupancy.iv_q uncore interconnect Total Write Cache Occupancy; Snoops event=0xf,umask=2  01    Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events unc_i_cache_total_occupancy.mem uncore interconnect Total IRP occupancy of inbound read and write requests event=0xf,umask=4  01    Total IRP occupancy of inbound read and write requests.  This is effectively the sum of read occupancy and write occupancy unc_i_clockticks uncore interconnect IRP Clocks event=1  01     unc_i_coherent_ops.clflush uncore interconnect Coherent Ops; CLFlush event=0x10,umask=0x80  01    Counts the number of coherency related operations serviced by the IRP unc_i_coherent_ops.crd uncore interconnect Coherent Ops; CRd event=0x10,umask=2  01    Counts the number of coherency related operations serviced by the IRP unc_i_coherent_ops.drd uncore interconnect Coherent Ops; DRd event=0x10,umask=4  01    Counts the number of coherency related operations serviced by the IRP unc_i_coherent_ops.pcidcahint uncore interconnect Coherent Ops; PCIDCAHin5t event=0x10,umask=0x20  01    Counts the number of coherency related operations serviced by the IRP unc_i_coherent_ops.pcirdcur uncore interconnect Coherent Ops; PCIRdCur event=0x10,umask=1  01    Counts the number of coherency related operations serviced by the IRP unc_i_coherent_ops.pcitom uncore interconnect PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline event=0x10,umask=0x10  01    PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO.  PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache unc_i_coherent_ops.rfo uncore interconnect RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline event=0x10,umask=8  01    RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory.  RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cache unc_i_coherent_ops.wbmtoi uncore interconnect Coherent Ops; WbMtoI event=0x10,umask=0x40  01    Counts the number of coherency related operations serviced by the IRP unc_i_faf_full uncore interconnect FAF RF full event=0x17  01     unc_i_faf_inserts uncore interconnect Inbound read requests received by the IRP and inserted into the FAF queue event=0x18  01    Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP unc_i_faf_occupancy uncore interconnect Occupancy of the IRP FAF queue event=0x19  01    Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP unc_i_faf_transactions uncore interconnect FAF allocation -- sent to ADQ event=0x16  01     unc_i_irp_all.inbound_inserts uncore interconnect All Inserts Inbound (p2p + faf + cset) event=0x1e,umask=1  01     unc_i_irp_all.outbound_inserts uncore interconnect All Inserts Outbound (BL, AK, Snoops) event=0x1e,umask=2  01     unc_i_misc0.2nd_atomic_insert uncore interconnect Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary event=0x1c,umask=0x10  01     unc_i_misc0.2nd_rd_insert uncore interconnect Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary event=0x1c,umask=4  01     unc_i_misc0.2nd_wr_insert uncore interconnect Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary event=0x1c,umask=8  01     unc_i_misc0.fast_rej uncore interconnect Misc Events - Set 0; Fastpath Rejects event=0x1c,umask=2  01     unc_i_misc0.fast_req uncore interconnect Misc Events - Set 0; Fastpath Requests event=0x1c,umask=1  01     unc_i_misc0.fast_xfer uncore interconnect Misc Events - Set 0; Fastpath Transfers From Primary to Secondary event=0x1c,umask=0x20  01     unc_i_misc0.pf_ack_hint uncore interconnect Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary event=0x1c,umask=0x40  01     unc_i_misc0.unknown uncore interconnect Misc Events - Set 0 event=0x1c,umask=0x80  01     unc_i_misc1.lost_fwd uncore interconnect Misc Events - Set 1; Lost Forward event=0x1d,umask=0x10  01    Snoop pulled away ownership before a write was committed unc_i_misc1.sec_rcvd_invld uncore interconnect Misc Events - Set 1; Received Invalid event=0x1d,umask=0x20  01    Secondary received a transfer that did not have sufficient MESI state unc_i_misc1.sec_rcvd_vld uncore interconnect Misc Events - Set 1; Received Valid event=0x1d,umask=0x40  01    Secondary received a transfer that did have sufficient MESI state unc_i_misc1.slow_e uncore interconnect Misc Events - Set 1; Slow Transfer of E Line event=0x1d,umask=4  01    Secondary received a transfer that did have sufficient MESI state unc_i_misc1.slow_i uncore interconnect Misc Events - Set 1; Slow Transfer of I Line event=0x1d,umask=1  01    Snoop took cacheline ownership before write from data was committed unc_i_misc1.slow_m uncore interconnect Misc Events - Set 1; Slow Transfer of M Line event=0x1d,umask=8  01    Snoop took cacheline ownership before write from data was committed unc_i_misc1.slow_s uncore interconnect Misc Events - Set 1; Slow Transfer of S Line event=0x1d,umask=2  01    Secondary received a transfer that did not have sufficient MESI state unc_i_p2p_inserts uncore interconnect P2P Requests event=0x14  01    P2P requests from the ITC unc_i_p2p_occupancy uncore interconnect P2P Occupancy event=0x15  01    P2P B & S Queue Occupancy unc_i_p2p_transactions.cmpl uncore interconnect P2P Transactions; P2P completions event=0x13,umask=8  01     unc_i_p2p_transactions.loc uncore interconnect P2P Transactions; match if local only event=0x13,umask=0x40  01     unc_i_p2p_transactions.loc_and_tgt_match uncore interconnect P2P Transactions; match if local and target matches event=0x13,umask=0x80  01     unc_i_p2p_transactions.msg uncore interconnect P2P Transactions; P2P Message event=0x13,umask=4  01     unc_i_p2p_transactions.rd uncore interconnect P2P Transactions; P2P reads event=0x13,umask=1  01     unc_i_p2p_transactions.rem uncore interconnect P2P Transactions; Match if remote only event=0x13,umask=0x10  01     unc_i_p2p_transactions.rem_and_tgt_match uncore interconnect P2P Transactions; match if remote and target matches event=0x13,umask=0x20  01     unc_i_p2p_transactions.wr uncore interconnect P2P Transactions; P2P Writes event=0x13,umask=2  01     unc_i_snoop_resp.all_hit uncore interconnect Responses to snoops of any type that hit M, E, S or I line in the IIO event=0x12,umask=0x7e  01    Responses to snoops of any type (code, data, invalidate) that hit M, E, S or I line in the IIO unc_i_snoop_resp.all_hit_es uncore interconnect Responses to snoops of any type that hit E or S line in the IIO cache event=0x12,umask=0x74  01    Responses to snoops of any type (code, data, invalidate) that hit E or S line in the IIO cache unc_i_snoop_resp.all_hit_i uncore interconnect Responses to snoops of any type that hit I line in the IIO cache event=0x12,umask=0x72  01    Responses to snoops of any type (code, data, invalidate) that hit I line in the IIO cache unc_i_snoop_resp.all_hit_m uncore interconnect Responses to snoops of any type that hit M line in the IIO cache event=0x12,umask=0x78  01    Responses to snoops of any type (code, data, invalidate) that hit M line in the IIO cache unc_i_snoop_resp.all_miss uncore interconnect Responses to snoops of any type that miss the IIO cache event=0x12,umask=0x71  01    Responses to snoops of any type (code, data, invalidate) that miss the IIO cache unc_i_snoop_resp.hit_es uncore interconnect Snoop Responses; Hit E or S event=0x12,umask=4  01     unc_i_snoop_resp.hit_i uncore interconnect Snoop Responses; Hit I event=0x12,umask=2  01     unc_i_snoop_resp.hit_m uncore interconnect Snoop Responses; Hit M event=0x12,umask=8  01     unc_i_snoop_resp.miss uncore interconnect Snoop Responses; Miss event=0x12,umask=1  01     unc_i_snoop_resp.snpcode uncore interconnect Snoop Responses; SnpCode event=0x12,umask=0x10  01     unc_i_snoop_resp.snpdata uncore interconnect Snoop Responses; SnpData event=0x12,umask=0x20  01     unc_i_snoop_resp.snpinv uncore interconnect Snoop Responses; SnpInv event=0x12,umask=0x40  01     unc_i_transactions.atomic uncore interconnect Inbound Transaction Count; Atomic event=0x11,umask=0x10  01    Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of atomic transactions unc_i_transactions.other uncore interconnect Inbound Transaction Count; Other event=0x11,umask=0x20  01    Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of 'other' kinds of transactions unc_i_transactions.rd_pref uncore interconnect Inbound Transaction Count; Read Prefetches event=0x11,umask=4  01    Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches unc_i_transactions.reads uncore interconnect Inbound Transaction Count; Reads event=0x11,umask=1  01    Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches) unc_i_transactions.writes uncore interconnect Inbound Transaction Count; Writes event=0x11,umask=2  01    Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only write requests.  Each write request should have a prefetch, so there is no need to explicitly track these requests.  For writes that are tickled and have to retry, the counter will be incremented for each retry unc_i_transactions.wr_pref uncore interconnect Inbound write (fast path) requests received by the IRP event=0x11,umask=8  01    Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh unc_i_txc_ak_inserts uncore interconnect AK Egress Allocations event=0xb  01     unc_i_txc_bl_drs_cycles_full uncore interconnect BL DRS Egress Cycles Full event=5  01     unc_i_txc_bl_drs_inserts uncore interconnect BL DRS Egress Inserts event=2  01     unc_i_txc_bl_drs_occupancy uncore interconnect BL DRS Egress Occupancy event=8  01     unc_i_txc_bl_ncb_cycles_full uncore interconnect BL NCB Egress Cycles Full event=6  01     unc_i_txc_bl_ncb_inserts uncore interconnect BL NCB Egress Inserts event=3  01     unc_i_txc_bl_ncb_occupancy uncore interconnect BL NCB Egress Occupancy event=9  01     unc_i_txc_bl_ncs_cycles_full uncore interconnect BL NCS Egress Cycles Full event=7  01     unc_i_txc_bl_ncs_inserts uncore interconnect BL NCS Egress Inserts event=4  01     unc_i_txc_bl_ncs_occupancy uncore interconnect BL NCS Egress Occupancy event=0xa  01     unc_i_txr2_ad_stall_credit_cycles uncore interconnect No AD Egress Credit Stalls event=0x1a  01    Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available unc_i_txr2_bl_stall_credit_cycles uncore interconnect No BL Egress Credit Stalls event=0x1b  01    Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available unc_i_txs_data_inserts_ncb uncore interconnect Outbound Read Requests event=0xd  01    Counts the number of requests issued to the switch (towards the devices) unc_i_txs_data_inserts_ncs uncore interconnect Outbound Read Requests event=0xe  01    Counts the number of requests issued to the switch (towards the devices) unc_i_txs_request_occupancy uncore interconnect Outbound Request Queue Occupancy event=0xc  01    Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices).  This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests uncore_m2m unc_m2m_ag0_ad_crd_acquired.tgr0 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 0 event=0x80,umask=1  01    Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired.tgr1 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 1 event=0x80,umask=2  01    Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired.tgr2 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 2 event=0x80,umask=4  01    Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired.tgr3 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 3 event=0x80,umask=8  01    Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired.tgr4 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 4 event=0x80,umask=0x10  01    Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired.tgr5 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 5 event=0x80,umask=0x20  01    Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy.tgr0 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 0 event=0x82,umask=1  01    Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy.tgr1 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 1 event=0x82,umask=2  01    Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy.tgr2 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 2 event=0x82,umask=4  01    Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy.tgr3 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 3 event=0x82,umask=8  01    Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy.tgr4 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 4 event=0x82,umask=0x10  01    Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy.tgr5 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 5 event=0x82,umask=0x20  01    Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired.tgr0 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 0 event=0x88,umask=1  01    Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired.tgr1 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 1 event=0x88,umask=2  01    Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired.tgr2 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 2 event=0x88,umask=4  01    Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired.tgr3 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 3 event=0x88,umask=8  01    Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired.tgr4 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 4 event=0x88,umask=0x10  01    Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired.tgr5 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 5 event=0x88,umask=0x20  01    Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy.tgr0 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 0 event=0x8a,umask=1  01    Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy.tgr1 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 1 event=0x8a,umask=2  01    Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy.tgr2 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 2 event=0x8a,umask=4  01    Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy.tgr3 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 3 event=0x8a,umask=8  01    Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy.tgr4 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 4 event=0x8a,umask=0x10  01    Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy.tgr5 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 5 event=0x8a,umask=0x20  01    Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired.tgr0 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 0 event=0x84,umask=1  01    Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired.tgr1 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 1 event=0x84,umask=2  01    Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired.tgr2 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 2 event=0x84,umask=4  01    Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired.tgr3 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 3 event=0x84,umask=8  01    Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired.tgr4 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 4 event=0x84,umask=0x10  01    Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired.tgr5 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 5 event=0x84,umask=0x20  01    Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy.tgr0 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 0 event=0x86,umask=1  01    Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy.tgr1 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 1 event=0x86,umask=2  01    Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy.tgr2 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 2 event=0x86,umask=4  01    Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy.tgr3 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 3 event=0x86,umask=8  01    Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy.tgr4 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 4 event=0x86,umask=0x10  01    Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy.tgr5 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 5 event=0x86,umask=0x20  01    Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy.tgr0 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 0 event=0x8e,umask=1  01    Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy.tgr1 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 1 event=0x8e,umask=2  01    Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy.tgr2 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 2 event=0x8e,umask=4  01    Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy.tgr3 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 3 event=0x8e,umask=8  01    Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy.tgr4 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 4 event=0x8e,umask=0x10  01    Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy.tgr5 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 5 event=0x8e,umask=0x20  01    Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_credits_acquired.tgr0 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 0 event=0x8c,umask=1  01    Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_credits_acquired.tgr1 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 1 event=0x8c,umask=2  01    Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_credits_acquired.tgr2 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 2 event=0x8c,umask=4  01    Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_credits_acquired.tgr3 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 3 event=0x8c,umask=8  01    Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_credits_acquired.tgr4 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 4 event=0x8c,umask=0x10  01    Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_credits_acquired.tgr5 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 5 event=0x8c,umask=0x20  01    Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_bypass_m2m_egress.not_taken uncore interconnect Traffic in which the M2M to iMC Bypass was not taken event=0x22,umask=2  01    Counts traffic in which the M2M (Mesh to Memory) to iMC (Memory Controller) bypass was not taken unc_m2m_bypass_m2m_egress.taken uncore interconnect M2M to iMC Bypass; Taken event=0x22,umask=1  01     unc_m2m_bypass_m2m_ingress.not_taken uncore interconnect M2M to iMC Bypass; Not Taken event=0x21,umask=2  01     unc_m2m_bypass_m2m_ingress.taken uncore interconnect M2M to iMC Bypass; Taken event=0x21,umask=1  01     unc_m2m_clockticks uncore interconnect Cycles - at UCLK event=0  01     unc_m2m_cms_clockticks uncore interconnect CMS Clockticks event=0xc0  01     unc_m2m_direct2core_not_taken_dirstate uncore interconnect Cycles when direct to core mode (which bypasses the CHA) was disabled event=0x24  01    Counts cycles when direct to core mode (which bypasses the CHA) was disabled unc_m2m_direct2core_taken uncore interconnect Messages sent direct to core (bypassing the CHA) event=0x23  01    Counts when messages were sent direct to core (bypassing the CHA) unc_m2m_direct2core_txn_override uncore interconnect Number of reads in which direct to core transaction were overridden event=0x25  01    Counts reads in which direct to core transactions (which would have bypassed the CHA) were overridden unc_m2m_direct2upi_not_taken_credits uncore interconnect Number of reads in which direct to Intel(R) UPI transactions were overridden event=0x28  01    Counts reads in which direct to Intel(R) Ultra Path Interconnect (UPI) transactions (which would have bypassed the CHA) were overridden unc_m2m_direct2upi_not_taken_dirstate uncore interconnect Cycles when direct to Intel(R) UPI was disabled event=0x27  01    Counts cycles when the ability to send messages direct to the Intel(R) Ultra Path Interconnect (bypassing the CHA) was disabled unc_m2m_direct2upi_taken uncore interconnect Messages sent direct to the Intel(R) UPI event=0x26  01    Counts when messages were sent direct to the Intel(R) Ultra Path Interconnect (bypassing the CHA) unc_m2m_direct2upi_txn_override uncore interconnect Number of reads that a message sent direct2 Intel(R) UPI was overridden event=0x29  01    Counts when a read message that was sent direct to the Intel(R) Ultra Path Interconnect (bypassing the CHA) was overridden unc_m2m_directory_hit.clean_a uncore interconnect Directory Hit; On NonDirty Line in A State event=0x2a,umask=0x80  01     unc_m2m_directory_hit.clean_i uncore interconnect Directory Hit; On NonDirty Line in I State event=0x2a,umask=0x10  01     unc_m2m_directory_hit.clean_p uncore interconnect Directory Hit; On NonDirty Line in L State event=0x2a,umask=0x40  01     unc_m2m_directory_hit.clean_s uncore interconnect Directory Hit; On NonDirty Line in S State event=0x2a,umask=0x20  01     unc_m2m_directory_hit.dirty_a uncore interconnect Directory Hit; On Dirty Line in A State event=0x2a,umask=8  01     unc_m2m_directory_hit.dirty_i uncore interconnect Directory Hit; On Dirty Line in I State event=0x2a,umask=1  01     unc_m2m_directory_hit.dirty_p uncore interconnect Directory Hit; On Dirty Line in L State event=0x2a,umask=4  01     unc_m2m_directory_hit.dirty_s uncore interconnect Directory Hit; On Dirty Line in S State event=0x2a,umask=2  01     unc_m2m_directory_lookup.any uncore interconnect Multi-socket cacheline Directory lookups (any state found) event=0x2d,umask=1  01    Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in Any State (A, I, S or unused) unc_m2m_directory_lookup.state_a uncore interconnect Multi-socket cacheline Directory lookups (cacheline found in A state) event=0x2d,umask=8  01    Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in the A (SnoopAll) state, indicating the cacheline is stored in another socket in any state, and we must snoop the other sockets to make sure we get the latest data.  The data may be stored in any state in the local socket unc_m2m_directory_lookup.state_i uncore interconnect Multi-socket cacheline Directory lookup (cacheline found in I state) event=0x2d,umask=2  01    Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the I (Invalid) state indicating the cacheline is not stored in another socket, and so there is no need to snoop the other sockets for the latest data.  The data may be stored in any state in the local socket unc_m2m_directory_lookup.state_s uncore interconnect Multi-socket cacheline Directory lookup (cacheline found in S state) event=0x2d,umask=4  01    Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the S (Shared) state indicating the cacheline is either stored in another socket in the S(hared) state , and so there is no need to snoop the other sockets for the latest data.  The data may be stored in any state in the local socket unc_m2m_directory_miss.clean_a uncore interconnect Directory Miss; On NonDirty Line in A State event=0x2b,umask=0x80  01     unc_m2m_directory_miss.clean_i uncore interconnect Directory Miss; On NonDirty Line in I State event=0x2b,umask=0x10  01     unc_m2m_directory_miss.clean_p uncore interconnect Directory Miss; On NonDirty Line in L State event=0x2b,umask=0x40  01     unc_m2m_directory_miss.clean_s uncore interconnect Directory Miss; On NonDirty Line in S State event=0x2b,umask=0x20  01     unc_m2m_directory_miss.dirty_a uncore interconnect Directory Miss; On Dirty Line in A State event=0x2b,umask=8  01     unc_m2m_directory_miss.dirty_i uncore interconnect Directory Miss; On Dirty Line in I State event=0x2b,umask=1  01     unc_m2m_directory_miss.dirty_p uncore interconnect Directory Miss; On Dirty Line in L State event=0x2b,umask=4  01     unc_m2m_directory_miss.dirty_s uncore interconnect Directory Miss; On Dirty Line in S State event=0x2b,umask=2  01     unc_m2m_directory_update.a2i uncore interconnect Multi-socket cacheline Directory update from A to I event=0x2e,umask=0x20  01    Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from A (SnoopAll) to I (Invalid) unc_m2m_directory_update.a2s uncore interconnect Multi-socket cacheline Directory update from A to S event=0x2e,umask=0x40  01    Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from A (SnoopAll) to S (Shared) unc_m2m_directory_update.any uncore interconnect Multi-socket cacheline Directory update from/to Any state event=0x2e,umask=1  01    Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory to a new state unc_m2m_directory_update.i2a uncore interconnect Multi-socket cacheline Directory update from I to A event=0x2e,umask=4  01    Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from I (Invalid) to A (SnoopAll) unc_m2m_directory_update.i2s uncore interconnect Multi-socket cacheline Directory update from I to S event=0x2e,umask=2  01    Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from I (Invalid) to S (Shared) unc_m2m_directory_update.s2a uncore interconnect Multi-socket cacheline Directory update from S to A event=0x2e,umask=0x10  01    Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from S (Shared) to A (SnoopAll) unc_m2m_directory_update.s2i uncore interconnect Multi-socket cacheline Directory update from S to I event=0x2e,umask=8  01    Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from S (Shared) to I (Invalid) unc_m2m_egress_ordering.iv_snoopgo_dn uncore interconnect Egress Blocking due to Ordering requirements; Down event=0xae,umask=4  01    Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m2m_egress_ordering.iv_snoopgo_up uncore interconnect Egress Blocking due to Ordering requirements; Up event=0xae,umask=1  01    Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m2m_fast_asserted.horz uncore interconnect FaST wire asserted; Horizontal event=0xa5,umask=2  01    Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across unc_m2m_fast_asserted.vert uncore interconnect FaST wire asserted; Vertical event=0xa5,umask=1  01    Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across unc_m2m_horz_ring_ad_in_use.left_even uncore interconnect Horizontal AD Ring In Use; Left and Even event=0xa7,umask=1  01    Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ad_in_use.left_odd uncore interconnect Horizontal AD Ring In Use; Left and Odd event=0xa7,umask=2  01    Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ad_in_use.right_even uncore interconnect Horizontal AD Ring In Use; Right and Even event=0xa7,umask=4  01    Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ad_in_use.right_odd uncore interconnect Horizontal AD Ring In Use; Right and Odd event=0xa7,umask=8  01    Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ak_in_use.left_even uncore interconnect Horizontal AK Ring In Use; Left and Even event=0xa9,umask=1  01    Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ak_in_use.left_odd uncore interconnect Horizontal AK Ring In Use; Left and Odd event=0xa9,umask=2  01    Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ak_in_use.right_even uncore interconnect Horizontal AK Ring In Use; Right and Even event=0xa9,umask=4  01    Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ak_in_use.right_odd uncore interconnect Horizontal AK Ring In Use; Right and Odd event=0xa9,umask=8  01    Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_bl_in_use.left_even uncore interconnect Horizontal BL Ring in Use; Left and Even event=0xab,umask=1  01    Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_bl_in_use.left_odd uncore interconnect Horizontal BL Ring in Use; Left and Odd event=0xab,umask=2  01    Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_bl_in_use.right_even uncore interconnect Horizontal BL Ring in Use; Right and Even event=0xab,umask=4  01    Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_bl_in_use.right_odd uncore interconnect Horizontal BL Ring in Use; Right and Odd event=0xab,umask=8  01    Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_iv_in_use.left uncore interconnect Horizontal IV Ring in Use; Left event=0xad,umask=1  01    Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2m_horz_ring_iv_in_use.right uncore interconnect Horizontal IV Ring in Use; Right event=0xad,umask=4  01    Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2m_imc_reads.all uncore interconnect Reads to iMC issued event=0x37,umask=4  01    Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller) unc_m2m_imc_reads.from_transgress uncore interconnect M2M Reads Issued to iMC; All, regardless of priority event=0x37,umask=0x10  01     unc_m2m_imc_reads.isoch uncore interconnect M2M Reads Issued to iMC; Critical Priority event=0x37,umask=2  01     unc_m2m_imc_reads.normal uncore interconnect Reads to iMC issued at Normal Priority (Non-Isochronous) event=0x37,umask=1  01    Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller).  It only counts  normal priority non-isochronous reads unc_m2m_imc_reads.to_pmm uncore interconnect Read requests to Intel(R) Optane(TM) DC persistent memory issued to the iMC from M2M event=0x37,umask=8  01    M2M Reads Issued to iMC; All, regardless of priority unc_m2m_imc_writes.all uncore interconnect Writes to iMC issued event=0x38,umask=0x10  01    Counts when the M2M (Mesh to Memory) issues writes to the iMC (Memory Controller) unc_m2m_imc_writes.from_transgress uncore interconnect M2M Writes Issued to iMC; All, regardless of priority event=0x38,umask=0x40  01     unc_m2m_imc_writes.full uncore interconnect M2M Writes Issued to iMC; Full Line Non-ISOCH event=0x38,umask=1  01     unc_m2m_imc_writes.full_isoch uncore interconnect M2M Writes Issued to iMC; ISOCH Full Line event=0x38,umask=4  01     unc_m2m_imc_writes.ni uncore interconnect M2M Writes Issued to iMC; All, regardless of priority event=0x38,umask=0x80  01     unc_m2m_imc_writes.partial uncore interconnect Partial Non-Isochronous writes to the iMC event=0x38,umask=2  01    Counts when the M2M (Mesh to Memory) issues partial writes to the iMC (Memory Controller).  It only counts normal priority non-isochronous writes unc_m2m_imc_writes.partial_isoch uncore interconnect M2M Writes Issued to iMC; ISOCH Partial event=0x38,umask=8  01     unc_m2m_imc_writes.to_pmm uncore interconnect Write requests to Intel(R) Optane(TM) DC persistent memory issued to the iMC from M2M event=0x38,umask=0x20  01    M2M Writes Issued to iMC; All, regardless of priority unc_m2m_pkt_match.mc uncore interconnect Number Packet Header Matches; MC Match event=0x4c,umask=2  01     unc_m2m_pkt_match.mesh uncore interconnect Number Packet Header Matches; Mesh Match event=0x4c,umask=1  01     unc_m2m_pmm_rpq_cycles_reg_credits.chn0 uncore interconnect M2M->iMC RPQ Cycles w/Credits - Regular; Channel 0 event=0x4f,umask=1  01     unc_m2m_pmm_rpq_cycles_reg_credits.chn1 uncore interconnect M2M->iMC RPQ Cycles w/Credits - Regular; Channel 1 event=0x4f,umask=2  01     unc_m2m_pmm_rpq_cycles_reg_credits.chn2 uncore interconnect M2M->iMC RPQ Cycles w/Credits - Regular; Channel 2 event=0x4f,umask=4  01     unc_m2m_pmm_wpq_cycles_reg_credits.chn0 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular; Channel 0 event=0x51,umask=1  01     unc_m2m_pmm_wpq_cycles_reg_credits.chn1 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular; Channel 1 event=0x51,umask=2  01     unc_m2m_pmm_wpq_cycles_reg_credits.chn2 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular; Channel 2 event=0x51,umask=4  01     unc_m2m_prefcam_cycles_full uncore interconnect Prefetch CAM Cycles Full event=0x53  01     unc_m2m_prefcam_cycles_ne uncore interconnect Prefetch CAM Cycles Not Empty event=0x54  01     unc_m2m_prefcam_demand_promotions uncore interconnect Prefetch requests that got turn into a demand request event=0x56  01    Counts when the M2M (Mesh to Memory) promotes a outstanding request in the prefetch queue due to a subsequent demand read request that entered the M2M with the same address.  Explanatory Side Note: The Prefetch queue is made of CAM (Content Addressable Memory) unc_m2m_prefcam_inserts uncore interconnect Inserts into the Memory Controller Prefetch Queue event=0x57  01    Counts when the M2M (Mesh to Memory) receives a prefetch request and inserts it into its outstanding prefetch queue.  Explanatory Side Note: the prefect queue is made from CAM: Content Addressable Memory unc_m2m_prefcam_occupancy uncore interconnect Prefetch CAM Occupancy event=0x55  01     unc_m2m_ring_bounces_horz.ad uncore interconnect Messages that bounced on the Horizontal Ring.; AD event=0xa1,umask=1  01    Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2m_ring_bounces_horz.ak uncore interconnect Messages that bounced on the Horizontal Ring.; AK event=0xa1,umask=2  01    Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2m_ring_bounces_horz.bl uncore interconnect Messages that bounced on the Horizontal Ring.; BL event=0xa1,umask=4  01    Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2m_ring_bounces_horz.iv uncore interconnect Messages that bounced on the Horizontal Ring.; IV event=0xa1,umask=8  01    Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2m_ring_bounces_vert.ad uncore interconnect Messages that bounced on the Vertical Ring.; AD event=0xa0,umask=1  01    Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2m_ring_bounces_vert.ak uncore interconnect Messages that bounced on the Vertical Ring.; Acknowledgements to core event=0xa0,umask=2  01    Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2m_ring_bounces_vert.bl uncore interconnect Messages that bounced on the Vertical Ring.; Data Responses to core event=0xa0,umask=4  01    Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2m_ring_bounces_vert.iv uncore interconnect Messages that bounced on the Vertical Ring.; Snoops of processor's cache event=0xa0,umask=8  01    Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2m_ring_sink_starved_horz.ad uncore interconnect Sink Starvation on Horizontal Ring; AD event=0xa3,umask=1  01     unc_m2m_ring_sink_starved_horz.ak uncore interconnect Sink Starvation on Horizontal Ring; AK event=0xa3,umask=2  01     unc_m2m_ring_sink_starved_horz.ak_ag1 uncore interconnect Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1 event=0xa3,umask=0x20  01     unc_m2m_ring_sink_starved_horz.bl uncore interconnect Sink Starvation on Horizontal Ring; BL event=0xa3,umask=4  01     unc_m2m_ring_sink_starved_horz.iv uncore interconnect Sink Starvation on Horizontal Ring; IV event=0xa3,umask=8  01     unc_m2m_ring_sink_starved_vert.ad uncore interconnect Sink Starvation on Vertical Ring; AD event=0xa2,umask=1  01     unc_m2m_ring_sink_starved_vert.ak uncore interconnect Sink Starvation on Vertical Ring; Acknowledgements to core event=0xa2,umask=2  01     unc_m2m_ring_sink_starved_vert.bl uncore interconnect Sink Starvation on Vertical Ring; Data Responses to core event=0xa2,umask=4  01     unc_m2m_ring_sink_starved_vert.iv uncore interconnect Sink Starvation on Vertical Ring; Snoops of processor's cache event=0xa2,umask=8  01     unc_m2m_ring_src_thrtl uncore interconnect Source Throttle event=0xa4  01     unc_m2m_rpq_cycles_no_spec_credits.chn0 uncore interconnect This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0 event=0x44,umask=1  11     unc_m2m_rpq_cycles_no_spec_credits.chn1 uncore interconnect This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1 event=0x44,umask=2  11     unc_m2m_rpq_cycles_no_spec_credits.chn2 uncore interconnect This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2 event=0x44,umask=4  11     unc_m2m_rpq_cycles_reg_credits.chn0 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Regular; Channel 0 event=0x43,umask=1  01     unc_m2m_rpq_cycles_reg_credits.chn1 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Regular; Channel 1 event=0x43,umask=2  01     unc_m2m_rpq_cycles_reg_credits.chn2 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Regular; Channel 2 event=0x43,umask=4  01     unc_m2m_rpq_cycles_spec_credits.chn0 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Special; Channel 0 event=0x44,umask=1  01     unc_m2m_rpq_cycles_spec_credits.chn1 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Special; Channel 1 event=0x44,umask=2  01     unc_m2m_rpq_cycles_spec_credits.chn2 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Special; Channel 2 event=0x44,umask=4  01     unc_m2m_rxc_ad_cycles_full uncore interconnect AD Ingress (from CMS) Full event=4  01     unc_m2m_rxc_ad_cycles_ne uncore interconnect AD Ingress (from CMS) Not Empty event=3  01     unc_m2m_rxc_ad_inserts uncore interconnect AD Ingress (from CMS) Queue Inserts event=1  01    Counts when the a new entry is Received(RxC) and then added to the AD (Address Ring) Ingress Queue from the CMS (Common Mesh Stop).  This is generally used for reads, and unc_m2m_rxc_ad_occupancy uncore interconnect AD Ingress (from CMS) Occupancy event=2  01     unc_m2m_rxc_bl_cycles_full uncore interconnect BL Ingress (from CMS) Full event=8  01     unc_m2m_rxc_bl_cycles_ne uncore interconnect BL Ingress (from CMS) Not Empty event=7  01     unc_m2m_rxc_bl_inserts uncore interconnect BL Ingress (from CMS) Allocations event=5  01     unc_m2m_rxc_bl_occupancy uncore interconnect BL Ingress (from CMS) Occupancy event=6  01     unc_m2m_rxr_busy_starved.ad_bnc uncore interconnect Transgress Injection Starvation; AD - Bounce event=0xb4,umask=1  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority unc_m2m_rxr_busy_starved.ad_crd uncore interconnect Transgress Injection Starvation; AD - Credit event=0xb4,umask=0x10  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority unc_m2m_rxr_busy_starved.bl_bnc uncore interconnect Transgress Injection Starvation; BL - Bounce event=0xb4,umask=4  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority unc_m2m_rxr_busy_starved.bl_crd uncore interconnect Transgress Injection Starvation; BL - Credit event=0xb4,umask=0x40  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority unc_m2m_rxr_bypass.ad_bnc uncore interconnect Transgress Ingress Bypass; AD - Bounce event=0xb2,umask=1  01    Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.ad_crd uncore interconnect Transgress Ingress Bypass; AD - Credit event=0xb2,umask=0x10  01    Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.ak_bnc uncore interconnect Transgress Ingress Bypass; AK - Bounce event=0xb2,umask=2  01    Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.bl_bnc uncore interconnect Transgress Ingress Bypass; BL - Bounce event=0xb2,umask=4  01    Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.bl_crd uncore interconnect Transgress Ingress Bypass; BL - Credit event=0xb2,umask=0x40  01    Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.iv_bnc uncore interconnect Transgress Ingress Bypass; IV - Bounce event=0xb2,umask=8  01    Number of packets bypassing the CMS Ingress unc_m2m_rxr_crd_starved.ad_bnc uncore interconnect Transgress Injection Starvation; AD - Bounce event=0xb3,umask=1  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.ad_crd uncore interconnect Transgress Injection Starvation; AD - Credit event=0xb3,umask=0x10  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.ak_bnc uncore interconnect Transgress Injection Starvation; AK - Bounce event=0xb3,umask=2  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.bl_bnc uncore interconnect Transgress Injection Starvation; BL - Bounce event=0xb3,umask=4  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.bl_crd uncore interconnect Transgress Injection Starvation; BL - Credit event=0xb3,umask=0x40  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.ifv uncore interconnect Transgress Injection Starvation; IFV - Credit event=0xb3,umask=0x80  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.iv_bnc uncore interconnect Transgress Injection Starvation; IV - Bounce event=0xb3,umask=8  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_inserts.ad_bnc uncore interconnect Transgress Ingress Allocations; AD - Bounce event=0xb1,umask=1  01    Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.ad_crd uncore interconnect Transgress Ingress Allocations; AD - Credit event=0xb1,umask=0x10  01    Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.ak_bnc uncore interconnect Transgress Ingress Allocations; AK - Bounce event=0xb1,umask=2  01    Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.bl_bnc uncore interconnect Transgress Ingress Allocations; BL - Bounce event=0xb1,umask=4  01    Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.bl_crd uncore interconnect Transgress Ingress Allocations; BL - Credit event=0xb1,umask=0x40  01    Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.iv_bnc uncore interconnect Transgress Ingress Allocations; IV - Bounce event=0xb1,umask=8  01    Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.ad_bnc uncore interconnect Transgress Ingress Occupancy; AD - Bounce event=0xb0,umask=1  01    Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.ad_crd uncore interconnect Transgress Ingress Occupancy; AD - Credit event=0xb0,umask=0x10  01    Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.ak_bnc uncore interconnect Transgress Ingress Occupancy; AK - Bounce event=0xb0,umask=2  01    Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.bl_bnc uncore interconnect Transgress Ingress Occupancy; BL - Bounce event=0xb0,umask=4  01    Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.bl_crd uncore interconnect Transgress Ingress Occupancy; BL - Credit event=0xb0,umask=0x40  01    Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.iv_bnc uncore interconnect Transgress Ingress Occupancy; IV - Bounce event=0xb0,umask=8  01    Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m2m_stall_no_txr_horz_crd_ad_ag0.tgr0 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 0 event=0xd0,umask=1  01    Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag0.tgr1 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 1 event=0xd0,umask=2  01    Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag0.tgr2 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 2 event=0xd0,umask=4  01    Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag0.tgr3 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 3 event=0xd0,umask=8  01    Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag0.tgr4 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 4 event=0xd0,umask=0x10  01    Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag0.tgr5 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 5 event=0xd0,umask=0x20  01    Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag1.tgr0 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 0 event=0xd2,umask=1  01    Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag1.tgr1 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 1 event=0xd2,umask=2  01    Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag1.tgr2 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 2 event=0xd2,umask=4  01    Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag1.tgr3 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 3 event=0xd2,umask=8  01    Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag1.tgr4 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 4 event=0xd2,umask=0x10  01    Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_ad_ag1.tgr5 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 5 event=0xd2,umask=0x20  01    Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag0.tgr0 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 0 event=0xd4,umask=1  01    Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag0.tgr1 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 1 event=0xd4,umask=2  01    Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag0.tgr2 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 2 event=0xd4,umask=4  01    Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag0.tgr3 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 3 event=0xd4,umask=8  01    Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag0.tgr4 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 4 event=0xd4,umask=0x10  01    Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag0.tgr5 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 5 event=0xd4,umask=0x20  01    Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag1.tgr0 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 0 event=0xd6,umask=1  01    Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag1.tgr1 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 1 event=0xd6,umask=2  01    Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag1.tgr2 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 2 event=0xd6,umask=4  01    Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag1.tgr3 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 3 event=0xd6,umask=8  01    Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag1.tgr4 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 4 event=0xd6,umask=0x10  01    Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall_no_txr_horz_crd_bl_ag1.tgr5 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 5 event=0xd6,umask=0x20  01    Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_tag_hit.nm_rd_hit_clean uncore interconnect Clean line read hits(Regular and RFO) to Near Memory(DRAM cache) in Memory Mode and regular reads to DRAM in 1LM event=0x2c,umask=1  01    Tag Hit; Read Hit from NearMem, Clean Line unc_m2m_tag_hit.nm_rd_hit_dirty uncore interconnect Dirty line read hits(Regular and RFO) to Near Memory(DRAM cache) in Memory Mode event=0x2c,umask=2  01    Tag Hit; Read Hit from NearMem, Dirty  Line unc_m2m_tag_hit.nm_ufill_hit_clean uncore interconnect Clean line underfill read hits to Near Memory(DRAM cache) in Memory Mode event=0x2c,umask=4  01    Tag Hit; Underfill Rd Hit from NearMem, Clean Line unc_m2m_tag_hit.nm_ufill_hit_dirty uncore interconnect Dirty line underfill read hits to Near Memory(DRAM cache) in Memory Mode event=0x2c,umask=8  01    Tag Hit; Underfill Rd Hit from NearMem, Dirty  Line unc_m2m_tgr_ad_credits uncore interconnect Number AD Ingress Credits event=0x41  01     unc_m2m_tgr_bl_credits uncore interconnect Number BL Ingress Credits event=0x42  01     unc_m2m_tracker_cycles_full.ch0 uncore interconnect Tracker Cycles Full; Channel 0 event=0x45,umask=1  01     unc_m2m_tracker_cycles_full.ch1 uncore interconnect Tracker Cycles Full; Channel 1 event=0x45,umask=2  01     unc_m2m_tracker_cycles_full.ch2 uncore interconnect Tracker Cycles Full; Channel 2 event=0x45,umask=4  01     unc_m2m_tracker_cycles_ne.ch0 uncore interconnect Tracker Cycles Not Empty; Channel 0 event=0x46,umask=1  01     unc_m2m_tracker_cycles_ne.ch1 uncore interconnect Tracker Cycles Not Empty; Channel 1 event=0x46,umask=2  01     unc_m2m_tracker_cycles_ne.ch2 uncore interconnect Tracker Cycles Not Empty; Channel 2 event=0x46,umask=4  01     unc_m2m_tracker_inserts.ch0 uncore interconnect Tracker Inserts; Channel 0 event=0x49,umask=1  01     unc_m2m_tracker_inserts.ch1 uncore interconnect Tracker Inserts; Channel 1 event=0x49,umask=2  01     unc_m2m_tracker_inserts.ch2 uncore interconnect Tracker Inserts; Channel 2 event=0x49,umask=4  01     unc_m2m_tracker_occupancy.ch0 uncore interconnect Tracker Occupancy; Channel 0 event=0x47,umask=1  01     unc_m2m_tracker_occupancy.ch1 uncore interconnect Tracker Occupancy; Channel 1 event=0x47,umask=2  01     unc_m2m_tracker_occupancy.ch2 uncore interconnect Tracker Occupancy; Channel 2 event=0x47,umask=4  01     unc_m2m_tracker_pending_occupancy uncore interconnect Data Pending Occupancy event=0x48  01     unc_m2m_txc_ad_credits_acquired uncore interconnect AD Egress (to CMS) Credit Acquired event=0xd  01     unc_m2m_txc_ad_credit_occupancy uncore interconnect AD Egress (to CMS) Credits Occupancy event=0xe  01     unc_m2m_txc_ad_cycles_full uncore interconnect AD Egress (to CMS) Full event=0xc  01     unc_m2m_txc_ad_cycles_ne uncore interconnect AD Egress (to CMS) Not Empty event=0xb  01     unc_m2m_txc_ad_inserts uncore interconnect AD Egress (to CMS) Allocations event=9  01     unc_m2m_txc_ad_no_credit_cycles uncore interconnect Cycles with No AD Egress (to CMS) Credits event=0xf  01     unc_m2m_txc_ad_no_credit_stalled uncore interconnect Cycles Stalled with No AD Egress (to CMS) Credits event=0x10  01     unc_m2m_txc_ad_occupancy uncore interconnect AD Egress (to CMS) Occupancy event=0xa  01     unc_m2m_txc_ak.crd_cbo uncore interconnect Outbound Ring Transactions on AK; CRD Transactions to Cbo event=0x39,umask=2  01     unc_m2m_txc_ak.ndr uncore interconnect Outbound Ring Transactions on AK; NDR Transactions event=0x39,umask=1  01     unc_m2m_txc_ak_credits_acquired.cms0 uncore interconnect AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side event=0x1d,umask=1  01     unc_m2m_txc_ak_credits_acquired.cms1 uncore interconnect AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side event=0x1d,umask=2  01     unc_m2m_txc_ak_credit_occupancy.cms0 uncore interconnect AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side event=0x1e,umask=1  01     unc_m2m_txc_ak_credit_occupancy.cms1 uncore interconnect AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side event=0x1e,umask=2  01     unc_m2m_txc_ak_cycles_full.all uncore interconnect AK Egress (to CMS) Full; All event=0x14,umask=3  01     unc_m2m_txc_ak_cycles_full.cms0 uncore interconnect AK Egress (to CMS) Full; Common Mesh Stop - Near Side event=0x14,umask=1  01     unc_m2m_txc_ak_cycles_full.cms1 uncore interconnect AK Egress (to CMS) Full; Common Mesh Stop - Far Side event=0x14,umask=2  01     unc_m2m_txc_ak_cycles_full.rdcrd0 uncore interconnect AK Egress (to CMS) Full; Read Credit Request event=0x14,umask=8  01     unc_m2m_txc_ak_cycles_full.rdcrd1 uncore interconnect AK Egress (to CMS) Full; Read Credit Request event=0x14,umask=0x88  01     unc_m2m_txc_ak_cycles_full.wrcmp0 uncore interconnect AK Egress (to CMS) Full; Write Compare Request event=0x14,umask=0x20  01     unc_m2m_txc_ak_cycles_full.wrcmp1 uncore interconnect AK Egress (to CMS) Full; Write Compare Request event=0x14,umask=0xa0  01     unc_m2m_txc_ak_cycles_full.wrcrd0 uncore interconnect AK Egress (to CMS) Full; Write Credit Request event=0x14,umask=0x10  01     unc_m2m_txc_ak_cycles_full.wrcrd1 uncore interconnect AK Egress (to CMS) Full; Write Credit Request event=0x14,umask=0x90  01     unc_m2m_txc_ak_cycles_ne.all uncore interconnect AK Egress (to CMS) Not Empty; All event=0x13,umask=3  01     unc_m2m_txc_ak_cycles_ne.cms0 uncore interconnect AK Egress (to CMS) Not Empty; Common Mesh Stop - Near Side event=0x13,umask=1  01     unc_m2m_txc_ak_cycles_ne.cms1 uncore interconnect AK Egress (to CMS) Not Empty; Common Mesh Stop - Far Side event=0x13,umask=2  01     unc_m2m_txc_ak_cycles_ne.rdcrd uncore interconnect AK Egress (to CMS) Not Empty; Read Credit Request event=0x13,umask=8  01     unc_m2m_txc_ak_cycles_ne.wrcmp uncore interconnect AK Egress (to CMS) Not Empty; Write Compare Request event=0x13,umask=0x20  01     unc_m2m_txc_ak_cycles_ne.wrcrd uncore interconnect AK Egress (to CMS) Not Empty; Write Credit Request event=0x13,umask=0x10  01     unc_m2m_txc_ak_inserts.all uncore interconnect AK Egress (to CMS) Allocations; All event=0x11,umask=3  01     unc_m2m_txc_ak_inserts.cms0 uncore interconnect AK Egress (to CMS) Allocations; Common Mesh Stop - Near Side event=0x11,umask=1  01     unc_m2m_txc_ak_inserts.cms1 uncore interconnect AK Egress (to CMS) Allocations; Common Mesh Stop - Far Side event=0x11,umask=2  01     unc_m2m_txc_ak_inserts.pref_rd_cam_hit uncore interconnect AK Egress (to CMS) Allocations; Prefetch Read Cam Hit event=0x11,umask=0x40  01     unc_m2m_txc_ak_inserts.rdcrd uncore interconnect AK Egress (to CMS) Allocations; Read Credit Request event=0x11,umask=8  01     unc_m2m_txc_ak_inserts.wrcmp uncore interconnect AK Egress (to CMS) Allocations; Write Compare Request event=0x11,umask=0x20  01     unc_m2m_txc_ak_inserts.wrcrd uncore interconnect AK Egress (to CMS) Allocations; Write Credit Request event=0x11,umask=0x10  01     unc_m2m_txc_ak_no_credit_cycles.cms0 uncore interconnect Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side event=0x1f,umask=1  01     unc_m2m_txc_ak_no_credit_cycles.cms1 uncore interconnect Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side event=0x1f,umask=2  01     unc_m2m_txc_ak_no_credit_stalled.cms0 uncore interconnect Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side event=0x20,umask=1  01     unc_m2m_txc_ak_no_credit_stalled.cms1 uncore interconnect Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side event=0x20,umask=2  01     unc_m2m_txc_ak_occupancy.all uncore interconnect AK Egress (to CMS) Occupancy; All event=0x12,umask=3  01     unc_m2m_txc_ak_occupancy.cms0 uncore interconnect AK Egress (to CMS) Occupancy; Common Mesh Stop - Near Side event=0x12,umask=1  01     unc_m2m_txc_ak_occupancy.cms1 uncore interconnect AK Egress (to CMS) Occupancy; Common Mesh Stop - Far Side event=0x12,umask=2  01     unc_m2m_txc_ak_occupancy.rdcrd uncore interconnect AK Egress (to CMS) Occupancy; Read Credit Request event=0x12,umask=8  01     unc_m2m_txc_ak_occupancy.wrcmp uncore interconnect AK Egress (to CMS) Occupancy; Write Compare Request event=0x12,umask=0x20  01     unc_m2m_txc_ak_occupancy.wrcrd uncore interconnect AK Egress (to CMS) Occupancy; Write Credit Request event=0x12,umask=0x10  01     unc_m2m_txc_ak_sideband.rd uncore interconnect AK Egress (to CMS) Sideband event=0x6b,umask=1  01     unc_m2m_txc_ak_sideband.wr uncore interconnect AK Egress (to CMS) Sideband event=0x6b,umask=2  01     unc_m2m_txc_bl.drs_cache uncore interconnect Outbound DRS Ring Transactions to Cache; Data to Cache event=0x40,umask=1  01     unc_m2m_txc_bl.drs_core uncore interconnect Outbound DRS Ring Transactions to Cache; Data to Core event=0x40,umask=2  01     unc_m2m_txc_bl.drs_upi uncore interconnect Outbound DRS Ring Transactions to Cache; Data to QPI event=0x40,umask=4  01     unc_m2m_txc_bl_credits_acquired.cms0 uncore interconnect BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side event=0x19,umask=1  01     unc_m2m_txc_bl_credits_acquired.cms1 uncore interconnect BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side event=0x19,umask=2  01     unc_m2m_txc_bl_credit_occupancy.cms0 uncore interconnect BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side event=0x1a,umask=1  01     unc_m2m_txc_bl_credit_occupancy.cms1 uncore interconnect BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side event=0x1a,umask=2  01     unc_m2m_txc_bl_cycles_full.all uncore interconnect BL Egress (to CMS) Full; All event=0x18,umask=3  01     unc_m2m_txc_bl_cycles_full.cms0 uncore interconnect BL Egress (to CMS) Full; Common Mesh Stop - Near Side event=0x18,umask=1  01     unc_m2m_txc_bl_cycles_full.cms1 uncore interconnect BL Egress (to CMS) Full; Common Mesh Stop - Far Side event=0x18,umask=2  01     unc_m2m_txc_bl_cycles_ne.all uncore interconnect BL Egress (to CMS) Not Empty; All event=0x17,umask=3  01     unc_m2m_txc_bl_cycles_ne.cms0 uncore interconnect BL Egress (to CMS) Not Empty; Common Mesh Stop - Near Side event=0x17,umask=1  01     unc_m2m_txc_bl_cycles_ne.cms1 uncore interconnect BL Egress (to CMS) Not Empty; Common Mesh Stop - Far Side event=0x17,umask=2  01     unc_m2m_txc_bl_inserts.all uncore interconnect BL Egress (to CMS) Allocations; All event=0x15,umask=3  01     unc_m2m_txc_bl_inserts.cms0 uncore interconnect BL Egress (to CMS) Allocations; Common Mesh Stop - Near Side event=0x15,umask=1  01     unc_m2m_txc_bl_inserts.cms1 uncore interconnect BL Egress (to CMS) Allocations; Common Mesh Stop - Far Side event=0x15,umask=2  01     unc_m2m_txc_bl_no_credit_cycles.cms0 uncore interconnect Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side event=0x1b,umask=1  01     unc_m2m_txc_bl_no_credit_cycles.cms1 uncore interconnect Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side event=0x1b,umask=2  01     unc_m2m_txc_bl_no_credit_stalled.cms0 uncore interconnect Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side event=0x1c,umask=1  01     unc_m2m_txc_bl_no_credit_stalled.cms1 uncore interconnect Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side event=0x1c,umask=2  01     unc_m2m_txc_bl_occupancy.all uncore interconnect BL Egress (to CMS) Occupancy; All event=0x16,umask=3  01     unc_m2m_txc_bl_occupancy.cms0 uncore interconnect BL Egress (to CMS) Occupancy; Common Mesh Stop - Near Side event=0x16,umask=1  01     unc_m2m_txc_bl_occupancy.cms1 uncore interconnect BL Egress (to CMS) Occupancy; Common Mesh Stop - Far Side event=0x16,umask=2  01     unc_m2m_txr_horz_ads_used.ad_bnc uncore interconnect CMS Horizontal ADS Used; AD - Bounce event=0x9d,umask=1  01    Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_horz_ads_used.ad_crd uncore interconnect CMS Horizontal ADS Used; AD - Credit event=0x9d,umask=0x10  01    Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_horz_ads_used.ak_bnc uncore interconnect CMS Horizontal ADS Used; AK - Bounce event=0x9d,umask=2  01    Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_horz_ads_used.bl_bnc uncore interconnect CMS Horizontal ADS Used; BL - Bounce event=0x9d,umask=4  01    Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_horz_ads_used.bl_crd uncore interconnect CMS Horizontal ADS Used; BL - Credit event=0x9d,umask=0x40  01    Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.ad_bnc uncore interconnect CMS Horizontal Bypass Used; AD - Bounce event=0x9f,umask=1  01    Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.ad_crd uncore interconnect CMS Horizontal Bypass Used; AD - Credit event=0x9f,umask=0x10  01    Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.ak_bnc uncore interconnect CMS Horizontal Bypass Used; AK - Bounce event=0x9f,umask=2  01    Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.bl_bnc uncore interconnect CMS Horizontal Bypass Used; BL - Bounce event=0x9f,umask=4  01    Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.bl_crd uncore interconnect CMS Horizontal Bypass Used; BL - Credit event=0x9f,umask=0x40  01    Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.iv_bnc uncore interconnect CMS Horizontal Bypass Used; IV - Bounce event=0x9f,umask=8  01    Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_cycles_full.ad_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Full; AD - Bounce event=0x96,umask=1  01    Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.ad_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Full; AD - Credit event=0x96,umask=0x10  01    Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.ak_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Full; AK - Bounce event=0x96,umask=2  01    Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.bl_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Full; BL - Bounce event=0x96,umask=4  01    Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.bl_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Full; BL - Credit event=0x96,umask=0x40  01    Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.iv_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Full; IV - Bounce event=0x96,umask=8  01    Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.ad_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce event=0x97,umask=1  01    Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.ad_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit event=0x97,umask=0x10  01    Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.ak_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce event=0x97,umask=2  01    Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.bl_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce event=0x97,umask=4  01    Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.bl_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit event=0x97,umask=0x40  01    Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.iv_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce event=0x97,umask=8  01    Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.ad_bnc uncore interconnect CMS Horizontal Egress Inserts; AD - Bounce event=0x95,umask=1  01    Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.ad_crd uncore interconnect CMS Horizontal Egress Inserts; AD - Credit event=0x95,umask=0x10  01    Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.ak_bnc uncore interconnect CMS Horizontal Egress Inserts; AK - Bounce event=0x95,umask=2  01    Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.bl_bnc uncore interconnect CMS Horizontal Egress Inserts; BL - Bounce event=0x95,umask=4  01    Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.bl_crd uncore interconnect CMS Horizontal Egress Inserts; BL - Credit event=0x95,umask=0x40  01    Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.iv_bnc uncore interconnect CMS Horizontal Egress Inserts; IV - Bounce event=0x95,umask=8  01    Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_nack.ad_bnc uncore interconnect CMS Horizontal Egress NACKs; AD - Bounce event=0x99,umask=1  01    Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.ad_crd uncore interconnect CMS Horizontal Egress NACKs; AD - Credit event=0x99,umask=0x20  01    Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.ak_bnc uncore interconnect CMS Horizontal Egress NACKs; AK - Bounce event=0x99,umask=2  01    Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.bl_bnc uncore interconnect CMS Horizontal Egress NACKs; BL - Bounce event=0x99,umask=4  01    Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.bl_crd uncore interconnect CMS Horizontal Egress NACKs; BL - Credit event=0x99,umask=0x40  01    Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.iv_bnc uncore interconnect CMS Horizontal Egress NACKs; IV - Bounce event=0x99,umask=8  01    Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_occupancy.ad_bnc uncore interconnect CMS Horizontal Egress Occupancy; AD - Bounce event=0x94,umask=1  01    Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.ad_crd uncore interconnect CMS Horizontal Egress Occupancy; AD - Credit event=0x94,umask=0x10  01    Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.ak_bnc uncore interconnect CMS Horizontal Egress Occupancy; AK - Bounce event=0x94,umask=2  01    Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.bl_bnc uncore interconnect CMS Horizontal Egress Occupancy; BL - Bounce event=0x94,umask=4  01    Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.bl_crd uncore interconnect CMS Horizontal Egress Occupancy; BL - Credit event=0x94,umask=0x40  01    Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.iv_bnc uncore interconnect CMS Horizontal Egress Occupancy; IV - Bounce event=0x94,umask=8  01    Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_starved.ad_bnc uncore interconnect CMS Horizontal Egress Injection Starvation; AD - Bounce event=0x9b,umask=1  01    Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2m_txr_horz_starved.ak_bnc uncore interconnect CMS Horizontal Egress Injection Starvation; AK - Bounce event=0x9b,umask=2  01    Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2m_txr_horz_starved.bl_bnc uncore interconnect CMS Horizontal Egress Injection Starvation; BL - Bounce event=0x9b,umask=4  01    Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2m_txr_horz_starved.iv_bnc uncore interconnect CMS Horizontal Egress Injection Starvation; IV - Bounce event=0x9b,umask=8  01    Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2m_txr_vert_ads_used.ad_ag0 uncore interconnect CMS Vertical ADS Used; AD - Agent 0 event=0x9c,umask=1  01    Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_vert_ads_used.ad_ag1 uncore interconnect CMS Vertical ADS Used; AD - Agent 1 event=0x9c,umask=0x10  01    Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_vert_ads_used.ak_ag0 uncore interconnect CMS Vertical ADS Used; AK - Agent 0 event=0x9c,umask=2  01    Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_vert_ads_used.ak_ag1 uncore interconnect CMS Vertical ADS Used; AK - Agent 1 event=0x9c,umask=0x20  01    Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_vert_ads_used.bl_ag0 uncore interconnect CMS Vertical ADS Used; BL - Agent 0 event=0x9c,umask=4  01    Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_vert_ads_used.bl_ag1 uncore interconnect CMS Vertical ADS Used; BL - Agent 1 event=0x9c,umask=0x40  01    Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.ad_ag0 uncore interconnect CMS Vertical ADS Used; AD - Agent 0 event=0x9e,umask=1  01    Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.ad_ag1 uncore interconnect CMS Vertical ADS Used; AD - Agent 1 event=0x9e,umask=0x10  01    Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.ak_ag0 uncore interconnect CMS Vertical ADS Used; AK - Agent 0 event=0x9e,umask=2  01    Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.ak_ag1 uncore interconnect CMS Vertical ADS Used; AK - Agent 1 event=0x9e,umask=0x20  01    Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.bl_ag0 uncore interconnect CMS Vertical ADS Used; BL - Agent 0 event=0x9e,umask=4  01    Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.bl_ag1 uncore interconnect CMS Vertical ADS Used; BL - Agent 1 event=0x9e,umask=0x40  01    Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.iv uncore interconnect CMS Vertical ADS Used; IV event=0x9e,umask=8  01    Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_cycles_full.ad_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0 event=0x92,umask=1  01    Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_cycles_full.ad_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1 event=0x92,umask=0x10  01    Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests unc_m2m_txr_vert_cycles_full.ak_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0 event=0x92,umask=2  01    Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_m2m_txr_vert_cycles_full.ak_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1 event=0x92,umask=0x20  01    Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_m2m_txr_vert_cycles_full.bl_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0 event=0x92,umask=4  01    Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations unc_m2m_txr_vert_cycles_full.bl_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1 event=0x92,umask=0x40  01    Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache unc_m2m_txr_vert_cycles_full.iv uncore interconnect Cycles CMS Vertical Egress Queue Is Full; IV event=0x92,umask=8  01    Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores unc_m2m_txr_vert_cycles_ne.ad_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0 event=0x93,umask=1  01    Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_cycles_ne.ad_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1 event=0x93,umask=0x10  01    Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests unc_m2m_txr_vert_cycles_ne.ak_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0 event=0x93,umask=2  01    Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_m2m_txr_vert_cycles_ne.ak_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1 event=0x93,umask=0x20  01    Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_m2m_txr_vert_cycles_ne.bl_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0 event=0x93,umask=4  01    Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations unc_m2m_txr_vert_cycles_ne.bl_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1 event=0x93,umask=0x40  01    Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache unc_m2m_txr_vert_cycles_ne.iv uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; IV event=0x93,umask=8  01    Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores unc_m2m_txr_vert_inserts.ad_ag0 uncore interconnect CMS Vert Egress Allocations; AD - Agent 0 event=0x91,umask=1  01    Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_inserts.ad_ag1 uncore interconnect CMS Vert Egress Allocations; AD - Agent 1 event=0x91,umask=0x10  01    Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests unc_m2m_txr_vert_inserts.ak_ag0 uncore interconnect CMS Vert Egress Allocations; AK - Agent 0 event=0x91,umask=2  01    Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_m2m_txr_vert_inserts.ak_ag1 uncore interconnect CMS Vert Egress Allocations; AK - Agent 1 event=0x91,umask=0x20  01    Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_m2m_txr_vert_inserts.bl_ag0 uncore interconnect CMS Vert Egress Allocations; BL - Agent 0 event=0x91,umask=4  01    Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations unc_m2m_txr_vert_inserts.bl_ag1 uncore interconnect CMS Vert Egress Allocations; BL - Agent 1 event=0x91,umask=0x40  01    Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache unc_m2m_txr_vert_inserts.iv uncore interconnect CMS Vert Egress Allocations; IV event=0x91,umask=8  01    Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores unc_m2m_txr_vert_nack.ad_ag0 uncore interconnect CMS Vertical Egress NACKs; AD - Agent 0 event=0x98,umask=1  01    Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack.ad_ag1 uncore interconnect CMS Vertical Egress NACKs; AD - Agent 1 event=0x98,umask=0x10  01    Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack.ak_ag0 uncore interconnect CMS Vertical Egress NACKs; AK - Agent 0 event=0x98,umask=2  01    Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack.ak_ag1 uncore interconnect CMS Vertical Egress NACKs; AK - Agent 1 event=0x98,umask=0x20  01    Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack.bl_ag0 uncore interconnect CMS Vertical Egress NACKs; BL - Agent 0 event=0x98,umask=4  01    Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack.bl_ag1 uncore interconnect CMS Vertical Egress NACKs; BL - Agent 1 event=0x98,umask=0x40  01    Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack.iv uncore interconnect CMS Vertical Egress NACKs; IV event=0x98,umask=8  01    Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_occupancy.ad_ag0 uncore interconnect CMS Vert Egress Occupancy; AD - Agent 0 event=0x90,umask=1  01    Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_occupancy.ad_ag1 uncore interconnect CMS Vert Egress Occupancy; AD - Agent 1 event=0x90,umask=0x10  01    Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests unc_m2m_txr_vert_occupancy.ak_ag0 uncore interconnect CMS Vert Egress Occupancy; AK - Agent 0 event=0x90,umask=2  01    Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_m2m_txr_vert_occupancy.ak_ag1 uncore interconnect CMS Vert Egress Occupancy; AK - Agent 1 event=0x90,umask=0x20  01    Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_m2m_txr_vert_occupancy.bl_ag0 uncore interconnect CMS Vert Egress Occupancy; BL - Agent 0 event=0x90,umask=4  01    Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations unc_m2m_txr_vert_occupancy.bl_ag1 uncore interconnect CMS Vert Egress Occupancy; BL - Agent 1 event=0x90,umask=0x40  01    Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache unc_m2m_txr_vert_occupancy.iv uncore interconnect CMS Vert Egress Occupancy; IV event=0x90,umask=8  01    Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores unc_m2m_txr_vert_starved.ad_ag0 uncore interconnect CMS Vertical Egress Injection Starvation; AD - Agent 0 event=0x9a,umask=1  01    Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved.ad_ag1 uncore interconnect CMS Vertical Egress Injection Starvation; AD - Agent 1 event=0x9a,umask=0x10  01    Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved.ak_ag0 uncore interconnect CMS Vertical Egress Injection Starvation; AK - Agent 0 event=0x9a,umask=2  01    Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved.ak_ag1 uncore interconnect CMS Vertical Egress Injection Starvation; AK - Agent 1 event=0x9a,umask=0x20  01    Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved.bl_ag0 uncore interconnect CMS Vertical Egress Injection Starvation; BL - Agent 0 event=0x9a,umask=4  01    Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved.bl_ag1 uncore interconnect CMS Vertical Egress Injection Starvation; BL - Agent 1 event=0x9a,umask=0x40  01    Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved.iv uncore interconnect CMS Vertical Egress Injection Starvation; IV event=0x9a,umask=8  01    Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_vert_ring_ad_in_use.dn_even uncore interconnect Vertical AD Ring In Use; Down and Even event=0xa6,umask=4  01    Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ad_in_use.dn_odd uncore interconnect Vertical AD Ring In Use; Down and Odd event=0xa6,umask=8  01    Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ad_in_use.up_even uncore interconnect Vertical AD Ring In Use; Up and Even event=0xa6,umask=1  01    Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ad_in_use.up_odd uncore interconnect Vertical AD Ring In Use; Up and Odd event=0xa6,umask=2  01    Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ak_in_use.dn_even uncore interconnect Vertical AK Ring In Use; Down and Even event=0xa8,umask=4  01    Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ak_in_use.dn_odd uncore interconnect Vertical AK Ring In Use; Down and Odd event=0xa8,umask=8  01    Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ak_in_use.up_even uncore interconnect Vertical AK Ring In Use; Up and Even event=0xa8,umask=1  01    Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ak_in_use.up_odd uncore interconnect Vertical AK Ring In Use; Up and Odd event=0xa8,umask=2  01    Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_bl_in_use.dn_even uncore interconnect Vertical BL Ring in Use; Down and Even event=0xaa,umask=4  01    Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_bl_in_use.dn_odd uncore interconnect Vertical BL Ring in Use; Down and Odd event=0xaa,umask=8  01    Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_bl_in_use.up_even uncore interconnect Vertical BL Ring in Use; Up and Even event=0xaa,umask=1  01    Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_bl_in_use.up_odd uncore interconnect Vertical BL Ring in Use; Up and Odd event=0xaa,umask=2  01    Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_iv_in_use.dn uncore interconnect Vertical IV Ring in Use; Down event=0xac,umask=4  01    Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2m_vert_ring_iv_in_use.up uncore interconnect Vertical IV Ring in Use; Up event=0xac,umask=1  01    Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2m_wpq_cycles_no_reg_credits.chn0 uncore interconnect This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0 event=0x4d,umask=1  11     unc_m2m_wpq_cycles_no_reg_credits.chn1 uncore interconnect This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1 event=0x4d,umask=2  11     unc_m2m_wpq_cycles_no_reg_credits.chn2 uncore interconnect This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2 event=0x4d,umask=4  11     unc_m2m_wpq_cycles_reg_credits.chn0 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular; Channel 0 event=0x4d,umask=1  01     unc_m2m_wpq_cycles_reg_credits.chn1 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular; Channel 1 event=0x4d,umask=2  01     unc_m2m_wpq_cycles_reg_credits.chn2 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular; Channel 2 event=0x4d,umask=4  01     unc_m2m_wpq_cycles_spec_credits.chn0 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Special; Channel 0 event=0x4e,umask=1  01     unc_m2m_wpq_cycles_spec_credits.chn1 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Special; Channel 1 event=0x4e,umask=2  01     unc_m2m_wpq_cycles_spec_credits.chn2 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Special; Channel 2 event=0x4e,umask=4  01     unc_m2m_write_tracker_cycles_full.ch0 uncore interconnect Write Tracker Cycles Full; Channel 0 event=0x4a,umask=1  01     unc_m2m_write_tracker_cycles_full.ch1 uncore interconnect Write Tracker Cycles Full; Channel 1 event=0x4a,umask=2  01     unc_m2m_write_tracker_cycles_full.ch2 uncore interconnect Write Tracker Cycles Full; Channel 2 event=0x4a,umask=4  01     unc_m2m_write_tracker_cycles_ne.ch0 uncore interconnect Write Tracker Cycles Not Empty; Channel 0 event=0x4b,umask=1  01     unc_m2m_write_tracker_cycles_ne.ch1 uncore interconnect Write Tracker Cycles Not Empty; Channel 1 event=0x4b,umask=2  01     unc_m2m_write_tracker_cycles_ne.ch2 uncore interconnect Write Tracker Cycles Not Empty; Channel 2 event=0x4b,umask=4  01     unc_m2m_write_tracker_inserts.ch0 uncore interconnect Write Tracker Inserts; Channel 0 event=0x61,umask=1  01     unc_m2m_write_tracker_inserts.ch1 uncore interconnect Write Tracker Inserts; Channel 1 event=0x61,umask=2  01     unc_m2m_write_tracker_inserts.ch2 uncore interconnect Write Tracker Inserts; Channel 2 event=0x61,umask=4  01     unc_m2m_write_tracker_occupancy.ch0 uncore interconnect Write Tracker Occupancy; Channel 0 event=0x60,umask=1  01     unc_m2m_write_tracker_occupancy.ch1 uncore interconnect Write Tracker Occupancy; Channel 1 event=0x60,umask=2  01     unc_m2m_write_tracker_occupancy.ch2 uncore interconnect Write Tracker Occupancy; Channel 2 event=0x60,umask=4  01     uncore_m3upi unc_m3upi_ag0_ad_crd_acquired.tgr0 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 0 event=0x80,umask=1  01    Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired.tgr1 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 1 event=0x80,umask=2  01    Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired.tgr2 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 2 event=0x80,umask=4  01    Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired.tgr3 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 3 event=0x80,umask=8  01    Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired.tgr4 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 4 event=0x80,umask=0x10  01    Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired.tgr5 uncore interconnect CMS Agent0 AD Credits Acquired; For Transgress 5 event=0x80,umask=0x20  01    Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy.tgr0 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 0 event=0x82,umask=1  01    Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy.tgr1 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 1 event=0x82,umask=2  01    Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy.tgr2 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 2 event=0x82,umask=4  01    Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy.tgr3 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 3 event=0x82,umask=8  01    Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy.tgr4 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 4 event=0x82,umask=0x10  01    Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy.tgr5 uncore interconnect CMS Agent0 AD Credits Occupancy; For Transgress 5 event=0x82,umask=0x20  01    Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired.tgr0 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 0 event=0x88,umask=1  01    Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired.tgr1 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 1 event=0x88,umask=2  01    Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired.tgr2 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 2 event=0x88,umask=4  01    Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired.tgr3 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 3 event=0x88,umask=8  01    Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired.tgr4 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 4 event=0x88,umask=0x10  01    Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired.tgr5 uncore interconnect CMS Agent0 BL Credits Acquired; For Transgress 5 event=0x88,umask=0x20  01    Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy.tgr0 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 0 event=0x8a,umask=1  01    Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy.tgr1 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 1 event=0x8a,umask=2  01    Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy.tgr2 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 2 event=0x8a,umask=4  01    Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy.tgr3 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 3 event=0x8a,umask=8  01    Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy.tgr4 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 4 event=0x8a,umask=0x10  01    Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy.tgr5 uncore interconnect CMS Agent0 BL Credits Occupancy; For Transgress 5 event=0x8a,umask=0x20  01    Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired.tgr0 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 0 event=0x84,umask=1  01    Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired.tgr1 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 1 event=0x84,umask=2  01    Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired.tgr2 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 2 event=0x84,umask=4  01    Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired.tgr3 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 3 event=0x84,umask=8  01    Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired.tgr4 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 4 event=0x84,umask=0x10  01    Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired.tgr5 uncore interconnect CMS Agent1 AD Credits Acquired; For Transgress 5 event=0x84,umask=0x20  01    Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy.tgr0 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 0 event=0x86,umask=1  01    Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy.tgr1 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 1 event=0x86,umask=2  01    Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy.tgr2 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 2 event=0x86,umask=4  01    Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy.tgr3 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 3 event=0x86,umask=8  01    Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy.tgr4 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 4 event=0x86,umask=0x10  01    Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy.tgr5 uncore interconnect CMS Agent1 AD Credits Occupancy; For Transgress 5 event=0x86,umask=0x20  01    Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy.tgr0 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 0 event=0x8e,umask=1  01    Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy.tgr1 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 1 event=0x8e,umask=2  01    Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy.tgr2 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 2 event=0x8e,umask=4  01    Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy.tgr3 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 3 event=0x8e,umask=8  01    Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy.tgr4 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 4 event=0x8e,umask=0x10  01    Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy.tgr5 uncore interconnect CMS Agent1 BL Credits Occupancy; For Transgress 5 event=0x8e,umask=0x20  01    Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_credits_acquired.tgr0 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 0 event=0x8c,umask=1  01    Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_credits_acquired.tgr1 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 1 event=0x8c,umask=2  01    Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_credits_acquired.tgr2 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 2 event=0x8c,umask=4  01    Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_credits_acquired.tgr3 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 3 event=0x8c,umask=8  01    Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_credits_acquired.tgr4 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 4 event=0x8c,umask=0x10  01    Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_credits_acquired.tgr5 uncore interconnect CMS Agent1 BL Credits Acquired; For Transgress 5 event=0x8c,umask=0x20  01    Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_cha_ad_credits_empty.req uncore interconnect CBox AD Credits Empty; Requests event=0x22,umask=4  01    No credits available to send to Cbox on the AD Ring (covers higher CBoxes) unc_m3upi_cha_ad_credits_empty.snp uncore interconnect CBox AD Credits Empty; Snoops event=0x22,umask=8  01    No credits available to send to Cbox on the AD Ring (covers higher CBoxes) unc_m3upi_cha_ad_credits_empty.vna uncore interconnect CBox AD Credits Empty; VNA Messages event=0x22,umask=1  01    No credits available to send to Cbox on the AD Ring (covers higher CBoxes) unc_m3upi_cha_ad_credits_empty.wb uncore interconnect CBox AD Credits Empty; Writebacks event=0x22,umask=2  01    No credits available to send to Cbox on the AD Ring (covers higher CBoxes) unc_m3upi_clockticks uncore interconnect Number of uclks in domain event=1  01    Counts the number of uclks in the M3 uclk domain.  This could be slightly different than the count in the Ubox because of enable/freeze delays.  However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles unc_m3upi_cms_clockticks uncore interconnect CMS Clockticks event=0xc0  01     unc_m3upi_d2c_sent uncore interconnect D2C Sent event=0x2b  01    Count cases BL sends direct to core unc_m3upi_d2u_sent uncore interconnect D2U Sent event=0x2a  01    Cases where SMI3 sends D2U command unc_m3upi_egress_ordering.iv_snoopgo_dn uncore interconnect Egress Blocking due to Ordering requirements; Down event=0xae,umask=4  01    Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m3upi_egress_ordering.iv_snoopgo_up uncore interconnect Egress Blocking due to Ordering requirements; Up event=0xae,umask=1  01    Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m3upi_fast_asserted.horz uncore interconnect FaST wire asserted; Horizontal event=0xa5,umask=2  01    Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across unc_m3upi_fast_asserted.vert uncore interconnect FaST wire asserted; Vertical event=0xa5,umask=1  01    Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across unc_m3upi_horz_ring_ad_in_use.left_even uncore interconnect Horizontal AD Ring In Use; Left and Even event=0xa7,umask=1  01    Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ad_in_use.left_odd uncore interconnect Horizontal AD Ring In Use; Left and Odd event=0xa7,umask=2  01    Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ad_in_use.right_even uncore interconnect Horizontal AD Ring In Use; Right and Even event=0xa7,umask=4  01    Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ad_in_use.right_odd uncore interconnect Horizontal AD Ring In Use; Right and Odd event=0xa7,umask=8  01    Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ak_in_use.left_even uncore interconnect Horizontal AK Ring In Use; Left and Even event=0xa9,umask=1  01    Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ak_in_use.left_odd uncore interconnect Horizontal AK Ring In Use; Left and Odd event=0xa9,umask=2  01    Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ak_in_use.right_even uncore interconnect Horizontal AK Ring In Use; Right and Even event=0xa9,umask=4  01    Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ak_in_use.right_odd uncore interconnect Horizontal AK Ring In Use; Right and Odd event=0xa9,umask=8  01    Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_bl_in_use.left_even uncore interconnect Horizontal BL Ring in Use; Left and Even event=0xab,umask=1  01    Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_bl_in_use.left_odd uncore interconnect Horizontal BL Ring in Use; Left and Odd event=0xab,umask=2  01    Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_bl_in_use.right_even uncore interconnect Horizontal BL Ring in Use; Right and Even event=0xab,umask=4  01    Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_bl_in_use.right_odd uncore interconnect Horizontal BL Ring in Use; Right and Odd event=0xab,umask=8  01    Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_iv_in_use.left uncore interconnect Horizontal IV Ring in Use; Left event=0xad,umask=1  01    Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m3upi_horz_ring_iv_in_use.right uncore interconnect Horizontal IV Ring in Use; Right event=0xad,umask=4  01    Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m3upi_m2_bl_credits_empty.iio0_iio1_ncb uncore interconnect M2 BL Credits Empty; IIO0 and IIO1 share the same ring destination. (1 VN0 credit only) event=0x23,umask=1  01    No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.iio2_ncb uncore interconnect M2 BL Credits Empty; IIO2 event=0x23,umask=2  01    No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.iio3_ncb uncore interconnect M2 BL Credits Empty; IIO3 event=0x23,umask=4  01    No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.iio4_ncb uncore interconnect M2 BL Credits Empty; IIO4 event=0x23,umask=8  01    No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.iio5_ncb uncore interconnect M2 BL Credits Empty; IIO5 event=0x23,umask=0x10  01    No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.ncs uncore interconnect M2 BL Credits Empty; All IIO targets for NCS are in single mask. ORs them together event=0x23,umask=0x20  01    No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.ncs_sel uncore interconnect M2 BL Credits Empty; Selected M2p BL NCS credits event=0x23,umask=0x40  01    No vn0 and vna credits available to send to M2 unc_m3upi_multi_slot_rcvd.ad_slot0 uncore interconnect Multi Slot Flit Received; AD - Slot 0 event=0x3e,umask=1  01    Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_multi_slot_rcvd.ad_slot1 uncore interconnect Multi Slot Flit Received; AD - Slot 1 event=0x3e,umask=2  01    Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_multi_slot_rcvd.ad_slot2 uncore interconnect Multi Slot Flit Received; AD - Slot 2 event=0x3e,umask=4  01    Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_multi_slot_rcvd.ak_slot0 uncore interconnect Multi Slot Flit Received; AK - Slot 0 event=0x3e,umask=0x10  01    Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_multi_slot_rcvd.ak_slot2 uncore interconnect Multi Slot Flit Received; AK - Slot 2 event=0x3e,umask=0x20  01    Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_multi_slot_rcvd.bl_slot0 uncore interconnect Multi Slot Flit Received; BL - Slot 0 event=0x3e,umask=8  01    Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_ring_bounces_horz.ad uncore interconnect Messages that bounced on the Horizontal Ring.; AD event=0xa1,umask=1  01    Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m3upi_ring_bounces_horz.ak uncore interconnect Messages that bounced on the Horizontal Ring.; AK event=0xa1,umask=2  01    Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m3upi_ring_bounces_horz.bl uncore interconnect Messages that bounced on the Horizontal Ring.; BL event=0xa1,umask=4  01    Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m3upi_ring_bounces_horz.iv uncore interconnect Messages that bounced on the Horizontal Ring.; IV event=0xa1,umask=8  01    Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m3upi_ring_bounces_vert.ad uncore interconnect Messages that bounced on the Vertical Ring.; AD event=0xa0,umask=1  01    Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m3upi_ring_bounces_vert.ak uncore interconnect Messages that bounced on the Vertical Ring.; Acknowledgements to core event=0xa0,umask=2  01    Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m3upi_ring_bounces_vert.bl uncore interconnect Messages that bounced on the Vertical Ring.; Data Responses to core event=0xa0,umask=4  01    Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m3upi_ring_bounces_vert.iv uncore interconnect Messages that bounced on the Vertical Ring.; Snoops of processor's cache event=0xa0,umask=8  01    Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m3upi_ring_sink_starved_horz.ad uncore interconnect Sink Starvation on Horizontal Ring; AD event=0xa3,umask=1  01     unc_m3upi_ring_sink_starved_horz.ak uncore interconnect Sink Starvation on Horizontal Ring; AK event=0xa3,umask=2  01     unc_m3upi_ring_sink_starved_horz.ak_ag1 uncore interconnect Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1 event=0xa3,umask=0x20  01     unc_m3upi_ring_sink_starved_horz.bl uncore interconnect Sink Starvation on Horizontal Ring; BL event=0xa3,umask=4  01     unc_m3upi_ring_sink_starved_horz.iv uncore interconnect Sink Starvation on Horizontal Ring; IV event=0xa3,umask=8  01     unc_m3upi_ring_sink_starved_vert.ad uncore interconnect Sink Starvation on Vertical Ring; AD event=0xa2,umask=1  01     unc_m3upi_ring_sink_starved_vert.ak uncore interconnect Sink Starvation on Vertical Ring; Acknowledgements to core event=0xa2,umask=2  01     unc_m3upi_ring_sink_starved_vert.bl uncore interconnect Sink Starvation on Vertical Ring; Data Responses to core event=0xa2,umask=4  01     unc_m3upi_ring_sink_starved_vert.iv uncore interconnect Sink Starvation on Vertical Ring; Snoops of processor's cache event=0xa2,umask=8  01     unc_m3upi_ring_src_thrtl uncore interconnect Source Throttle event=0xa4  01     unc_m3upi_rxc_arb_lost_vn0.ad_req uncore interconnect Lost Arb for VN0; REQ on AD event=0x4b,umask=1  01    VN0 message requested but lost arbitration; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_lost_vn0.ad_rsp uncore interconnect Lost Arb for VN0; RSP on AD event=0x4b,umask=4  01    VN0 message requested but lost arbitration; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_lost_vn0.ad_snp uncore interconnect Lost Arb for VN0; SNP on AD event=0x4b,umask=2  01    VN0 message requested but lost arbitration; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_rxc_arb_lost_vn0.bl_ncb uncore interconnect Lost Arb for VN0; NCB on BL event=0x4b,umask=0x20  01    VN0 message requested but lost arbitration; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_rxc_arb_lost_vn0.bl_ncs uncore interconnect Lost Arb for VN0; NCS on BL event=0x4b,umask=0x40  01    VN0 message requested but lost arbitration; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_lost_vn0.bl_rsp uncore interconnect Lost Arb for VN0; RSP on BL event=0x4b,umask=8  01    VN0 message requested but lost arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_lost_vn0.bl_wb uncore interconnect Lost Arb for VN0; WB on BL event=0x4b,umask=0x10  01    VN0 message requested but lost arbitration; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_arb_lost_vn1.ad_req uncore interconnect Lost Arb for VN1; REQ on AD event=0x4c,umask=1  01    VN1 message requested but lost arbitration; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_lost_vn1.ad_rsp uncore interconnect Lost Arb for VN1; RSP on AD event=0x4c,umask=4  01    VN1 message requested but lost arbitration; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_lost_vn1.ad_snp uncore interconnect Lost Arb for VN1; SNP on AD event=0x4c,umask=2  01    VN1 message requested but lost arbitration; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_rxc_arb_lost_vn1.bl_ncb uncore interconnect Lost Arb for VN1; NCB on BL event=0x4c,umask=0x20  01    VN1 message requested but lost arbitration; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_rxc_arb_lost_vn1.bl_ncs uncore interconnect Lost Arb for VN1; NCS on BL event=0x4c,umask=0x40  01    VN1 message requested but lost arbitration; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_lost_vn1.bl_rsp uncore interconnect Lost Arb for VN1; RSP on BL event=0x4c,umask=8  01    VN1 message requested but lost arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_lost_vn1.bl_wb uncore interconnect Lost Arb for VN1; WB on BL event=0x4c,umask=0x10  01    VN1 message requested but lost arbitration; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_arb_misc.adbl_parallel_win uncore interconnect Arb Miscellaneous; AD, BL Parallel Win event=0x4d,umask=0x40  01    AD and BL messages won arbitration concurrently / in parallel unc_m3upi_rxc_arb_misc.no_prog_ad_vn0 uncore interconnect Arb Miscellaneous; No Progress on Pending AD VN0 event=0x4d,umask=4  01    Arbitration stage made no progress on pending ad vn0 messages because slotting stage cannot accept new message unc_m3upi_rxc_arb_misc.no_prog_ad_vn1 uncore interconnect Arb Miscellaneous; No Progress on Pending AD VN1 event=0x4d,umask=8  01    Arbitration stage made no progress on pending ad vn1 messages because slotting stage cannot accept new message unc_m3upi_rxc_arb_misc.no_prog_bl_vn0 uncore interconnect Arb Miscellaneous; No Progress on Pending BL VN0 event=0x4d,umask=0x10  01    Arbitration stage made no progress on pending bl vn0 messages because slotting stage cannot accept new message unc_m3upi_rxc_arb_misc.no_prog_bl_vn1 uncore interconnect Arb Miscellaneous; No Progress on Pending BL VN1 event=0x4d,umask=0x20  01    Arbitration stage made no progress on pending bl vn1 messages because slotting stage cannot accept new message unc_m3upi_rxc_arb_misc.par_bias_vn0 uncore interconnect Arb Miscellaneous; Parallel Bias to VN0 event=0x4d,umask=1  01    VN0/VN1 arbiter gave second, consecutive win to vn0, delaying vn1 win, because vn0 offered parallel ad/bl unc_m3upi_rxc_arb_misc.par_bias_vn1 uncore interconnect Arb Miscellaneous; Parallel Bias to VN1 event=0x4d,umask=2  01    VN0/VN1 arbiter gave second, consecutive win to vn1, delaying vn0 win, because vn1 offered parallel ad/bl unc_m3upi_rxc_arb_noad_req_vn0.ad_req uncore interconnect Can't Arb for VN0; REQ on AD event=0x49,umask=1  01    VN0 message was not able to request arbitration while some other message won arbitration; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_noad_req_vn0.ad_rsp uncore interconnect Can't Arb for VN0; RSP on AD event=0x49,umask=4  01    VN0 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_noad_req_vn0.ad_snp uncore interconnect Can't Arb for VN0; SNP on AD event=0x49,umask=2  01    VN0 message was not able to request arbitration while some other message won arbitration; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_rxc_arb_noad_req_vn0.bl_ncb uncore interconnect Can't Arb for VN0; NCB on BL event=0x49,umask=0x20  01    VN0 message was not able to request arbitration while some other message won arbitration; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_rxc_arb_noad_req_vn0.bl_ncs uncore interconnect Can't Arb for VN0; NCS on BL event=0x49,umask=0x40  01    VN0 message was not able to request arbitration while some other message won arbitration; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_noad_req_vn0.bl_rsp uncore interconnect Can't Arb for VN0; RSP on BL event=0x49,umask=8  01    VN0 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_noad_req_vn0.bl_wb uncore interconnect Can't Arb for VN0; WB on BL event=0x49,umask=0x10  01    VN0 message was not able to request arbitration while some other message won arbitration; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_arb_noad_req_vn1.ad_req uncore interconnect Can't Arb for VN1; REQ on AD event=0x4a,umask=1  01    VN1 message was not able to request arbitration while some other message won arbitration; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_noad_req_vn1.ad_rsp uncore interconnect Can't Arb for VN1; RSP on AD event=0x4a,umask=4  01    VN1 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_noad_req_vn1.ad_snp uncore interconnect Can't Arb for VN1; SNP on AD event=0x4a,umask=2  01    VN1 message was not able to request arbitration while some other message won arbitration; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_rxc_arb_noad_req_vn1.bl_ncb uncore interconnect Can't Arb for VN1; NCB on BL event=0x4a,umask=0x20  01    VN1 message was not able to request arbitration while some other message won arbitration; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_rxc_arb_noad_req_vn1.bl_ncs uncore interconnect Can't Arb for VN1; NCS on BL event=0x4a,umask=0x40  01    VN1 message was not able to request arbitration while some other message won arbitration; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_noad_req_vn1.bl_rsp uncore interconnect Can't Arb for VN1; RSP on BL event=0x4a,umask=8  01    VN1 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_noad_req_vn1.bl_wb uncore interconnect Can't Arb for VN1; WB on BL event=0x4a,umask=0x10  01    VN1 message was not able to request arbitration while some other message won arbitration; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_arb_nocred_vn0.ad_req uncore interconnect No Credits to Arb for VN0; REQ on AD event=0x47,umask=1  01    VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_nocred_vn0.ad_rsp uncore interconnect No Credits to Arb for VN0; RSP on AD event=0x47,umask=4  01    VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_nocred_vn0.ad_snp uncore interconnect No Credits to Arb for VN0; SNP on AD event=0x47,umask=2  01    VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_rxc_arb_nocred_vn0.bl_ncb uncore interconnect No Credits to Arb for VN0; NCB on BL event=0x47,umask=0x20  01    VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_rxc_arb_nocred_vn0.bl_ncs uncore interconnect No Credits to Arb for VN0; NCS on BL event=0x47,umask=0x40  01    VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_nocred_vn0.bl_rsp uncore interconnect No Credits to Arb for VN0; RSP on BL event=0x47,umask=8  01    VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_nocred_vn0.bl_wb uncore interconnect No Credits to Arb for VN0; WB on BL event=0x47,umask=0x10  01    VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_arb_nocred_vn1.ad_req uncore interconnect No Credits to Arb for VN1; REQ on AD event=0x48,umask=1  01    VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_nocred_vn1.ad_rsp uncore interconnect No Credits to Arb for VN1; RSP on AD event=0x48,umask=4  01    VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_nocred_vn1.ad_snp uncore interconnect No Credits to Arb for VN1; SNP on AD event=0x48,umask=2  01    VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_rxc_arb_nocred_vn1.bl_ncb uncore interconnect No Credits to Arb for VN1; NCB on BL event=0x48,umask=0x20  01    VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_rxc_arb_nocred_vn1.bl_ncs uncore interconnect No Credits to Arb for VN1; NCS on BL event=0x48,umask=0x40  01    VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_nocred_vn1.bl_rsp uncore interconnect No Credits to Arb for VN1; RSP on BL event=0x48,umask=8  01    VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_nocred_vn1.bl_wb uncore interconnect No Credits to Arb for VN1; WB on BL event=0x48,umask=0x10  01    VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_bypassed.ad_s0_bl_arb uncore interconnect Ingress Queue Bypasses; AD to Slot 0 on BL Arb event=0x40,umask=2  01    Number of times message is bypassed around the Ingress Queue; AD is taking bypass to slot 0 of independent flit while bl message is in arbitration unc_m3upi_rxc_bypassed.ad_s0_idle uncore interconnect Ingress Queue Bypasses; AD to Slot 0 on Idle event=0x40,umask=1  01    Number of times message is bypassed around the Ingress Queue; AD is taking bypass to slot 0 of independent flit while pipeline is idle unc_m3upi_rxc_bypassed.ad_s1_bl_slot uncore interconnect Ingress Queue Bypasses; AD + BL to Slot 1 event=0x40,umask=4  01    Number of times message is bypassed around the Ingress Queue; AD is taking bypass to flit slot 1 while merging with bl message in same flit unc_m3upi_rxc_bypassed.ad_s2_bl_slot uncore interconnect Ingress Queue Bypasses; AD + BL to Slot 2 event=0x40,umask=8  01    Number of times message is bypassed around the Ingress Queue; AD is taking bypass to flit slot 2 while merging with bl message in same flit unc_m3upi_rxc_collision_vn0.ad_req uncore interconnect VN0 message lost contest for flit; REQ on AD event=0x50,umask=1  01    Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_collision_vn0.ad_rsp uncore interconnect VN0 message lost contest for flit; RSP on AD event=0x50,umask=4  01    Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_collision_vn0.ad_snp uncore interconnect VN0 message lost contest for flit; SNP on AD event=0x50,umask=2  01    Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_rxc_collision_vn0.bl_ncb uncore interconnect VN0 message lost contest for flit; NCB on BL event=0x50,umask=0x20  01    Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_rxc_collision_vn0.bl_ncs uncore interconnect VN0 message lost contest for flit; NCS on BL event=0x50,umask=0x40  01    Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_collision_vn0.bl_rsp uncore interconnect VN0 message lost contest for flit; RSP on BL event=0x50,umask=8  01    Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_collision_vn0.bl_wb uncore interconnect VN0 message lost contest for flit; WB on BL event=0x50,umask=0x10  01    Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_collision_vn1.ad_req uncore interconnect VN1 message lost contest for flit; REQ on AD event=0x51,umask=1  01    Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_collision_vn1.ad_rsp uncore interconnect VN1 message lost contest for flit; RSP on AD event=0x51,umask=4  01    Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_collision_vn1.ad_snp uncore interconnect VN1 message lost contest for flit; SNP on AD event=0x51,umask=2  01    Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_rxc_collision_vn1.bl_ncb uncore interconnect VN1 message lost contest for flit; NCB on BL event=0x51,umask=0x20  01    Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_rxc_collision_vn1.bl_ncs uncore interconnect VN1 message lost contest for flit; NCS on BL event=0x51,umask=0x40  01    Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_collision_vn1.bl_rsp uncore interconnect VN1 message lost contest for flit; RSP on BL event=0x51,umask=8  01    Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_collision_vn1.bl_wb uncore interconnect VN1 message lost contest for flit; WB on BL event=0x51,umask=0x10  01    Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_crd_misc.any_bgf_fifo uncore interconnect Miscellaneous Credit Events; Any In BGF FIFO event=0x60,umask=1  01    Indication that at least one packet (flit) is in the bgf (fifo only) unc_m3upi_rxc_crd_misc.any_bgf_path uncore interconnect Miscellaneous Credit Events; Any in BGF Path event=0x60,umask=2  01    Indication that at least one packet (flit) is in the bgf path (i.e. pipe to fifo) unc_m3upi_rxc_crd_misc.no_d2k_for_arb uncore interconnect Miscellaneous Credit Events; No D2K For Arb event=0x60,umask=4  01    VN0 or VN1 BL RSP message was blocked from arbitration request due to lack of D2K CMP credits unc_m3upi_rxc_crd_occ.d2k_crd uncore interconnect Credit Occupancy; D2K Credits event=0x61,umask=0x10  01    D2K completion fifo credit occupancy (credits in use), accumulated across all cycles unc_m3upi_rxc_crd_occ.flits_in_fifo uncore interconnect Credit Occupancy; Packets in BGF FIFO event=0x61,umask=2  01    Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in fifo unc_m3upi_rxc_crd_occ.flits_in_path uncore interconnect Credit Occupancy; Packets in BGF Path event=0x61,umask=4  01    Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in path (i.e. pipe to fifo or fifo) unc_m3upi_rxc_crd_occ.p1p_fifo uncore interconnect Credit Occupancy event=0x61,umask=0x40  01    count of bl messages in pump-1-pending state, in completion fifo only unc_m3upi_rxc_crd_occ.p1p_total uncore interconnect Credit Occupancy event=0x61,umask=0x20  01    count of bl messages in pump-1-pending state, in marker table and in fifo unc_m3upi_rxc_crd_occ.txq_crd uncore interconnect Credit Occupancy; Transmit Credits event=0x61,umask=8  01    Link layer transmit queue credit occupancy (credits in use), accumulated across all cycles unc_m3upi_rxc_crd_occ.vna_in_use uncore interconnect Credit Occupancy; VNA In Use event=0x61,umask=1  01    Remote UPI VNA credit occupancy (number of credits in use), accumulated across all cycles unc_m3upi_rxc_cycles_ne_vn0.ad_req uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD event=0x43,umask=1  01    Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_cycles_ne_vn0.ad_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD event=0x43,umask=4  01    Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_cycles_ne_vn0.ad_snp uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD event=0x43,umask=2  01    Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_rxc_cycles_ne_vn0.bl_ncb uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL event=0x43,umask=0x20  01    Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_rxc_cycles_ne_vn0.bl_ncs uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL event=0x43,umask=0x40  01    Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_cycles_ne_vn0.bl_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL event=0x43,umask=8  01    Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_cycles_ne_vn0.bl_wb uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL event=0x43,umask=0x10  01    Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_cycles_ne_vn1.ad_req uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD event=0x44,umask=1  01    Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_cycles_ne_vn1.ad_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD event=0x44,umask=4  01    Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_cycles_ne_vn1.ad_snp uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD event=0x44,umask=2  01    Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_rxc_cycles_ne_vn1.bl_ncb uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL event=0x44,umask=0x20  01    Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_rxc_cycles_ne_vn1.bl_ncs uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL event=0x44,umask=0x40  01    Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_cycles_ne_vn1.bl_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL event=0x44,umask=8  01    Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_cycles_ne_vn1.bl_wb uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL event=0x44,umask=0x10  01    Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_flits_data_not_sent.all uncore interconnect Data Flit Not Sent; All event=0x57,umask=1  01    Data flit is ready for transmission but could not be sent unc_m3upi_rxc_flits_data_not_sent.no_bgf uncore interconnect Data Flit Not Sent; No BGF Credits event=0x57,umask=2  01    Data flit is ready for transmission but could not be sent unc_m3upi_rxc_flits_data_not_sent.no_txq uncore interconnect Data Flit Not Sent; No TxQ Credits event=0x57,umask=4  01    Data flit is ready for transmission but could not be sent unc_m3upi_rxc_flits_gen_bl.p0_wait uncore interconnect Generating BL Data Flit Sequence; Wait on Pump 0 event=0x59,umask=1  01    generating bl data flit sequence; waiting for data pump 0 unc_m3upi_rxc_flits_gen_bl.p1p_at_limit uncore interconnect Generating BL Data Flit Sequence event=0x59,umask=0x10  01    pump-1-pending logic is at capacity (pending table plus completion fifo at limit) unc_m3upi_rxc_flits_gen_bl.p1p_busy uncore interconnect Generating BL Data Flit Sequence event=0x59,umask=8  01    pump-1-pending logic is tracking at least one message unc_m3upi_rxc_flits_gen_bl.p1p_fifo_full uncore interconnect Generating BL Data Flit Sequence event=0x59,umask=0x40  01    pump-1-pending completion fifo is full unc_m3upi_rxc_flits_gen_bl.p1p_hold_p0 uncore interconnect Generating BL Data Flit Sequence event=0x59,umask=0x20  01    pump-1-pending logic is at or near capacity, such that pump-0-only bl messages are getting stalled in slotting stage unc_m3upi_rxc_flits_gen_bl.p1p_to_limbo uncore interconnect Generating BL Data Flit Sequence event=0x59,umask=4  01    a bl message finished but is in limbo and moved to pump-1-pending logic unc_m3upi_rxc_flits_gen_bl.p1_wait uncore interconnect Generating BL Data Flit Sequence; Wait on Pump 1 event=0x59,umask=2  01    generating bl data flit sequence; waiting for data pump 1 unc_m3upi_rxc_flits_misc uncore interconnect UNC_M3UPI_RxC_FLITS_MISC event=0x5a  01     unc_m3upi_rxc_flits_sent.1_msg uncore interconnect Sent Header Flit; One Message event=0x56,umask=1  01    One message in flit; VNA or non-VNA flit unc_m3upi_rxc_flits_sent.1_msg_vnx uncore interconnect Sent Header Flit; One Message in non-VNA event=0x56,umask=8  01    One message in flit; non-VNA flit unc_m3upi_rxc_flits_sent.2_msgs uncore interconnect Sent Header Flit; Two Messages event=0x56,umask=2  01    Two messages in flit; VNA flit unc_m3upi_rxc_flits_sent.3_msgs uncore interconnect Sent Header Flit; Three Messages event=0x56,umask=4  01    Three messages in flit; VNA flit unc_m3upi_rxc_flits_sent.slots_1 uncore interconnect Sent Header Flit event=0x56,umask=0x10  01     unc_m3upi_rxc_flits_sent.slots_2 uncore interconnect Sent Header Flit event=0x56,umask=0x20  01     unc_m3upi_rxc_flits_sent.slots_3 uncore interconnect Sent Header Flit event=0x56,umask=0x40  01     unc_m3upi_rxc_flits_slot_bl.all uncore interconnect Slotting BL Message Into Header Flit; All event=0x58,umask=1  01     unc_m3upi_rxc_flits_slot_bl.need_data uncore interconnect Slotting BL Message Into Header Flit; Needs Data Flit event=0x58,umask=2  01    BL message requires data flit sequence unc_m3upi_rxc_flits_slot_bl.p0_wait uncore interconnect Slotting BL Message Into Header Flit; Wait on Pump 0 event=0x58,umask=4  01    Waiting for header pump 0 unc_m3upi_rxc_flits_slot_bl.p1_not_req uncore interconnect Slotting BL Message Into Header Flit; Don't Need Pump 1 event=0x58,umask=0x10  01    Header pump 1 is not required for flit unc_m3upi_rxc_flits_slot_bl.p1_not_req_but_bubble uncore interconnect Slotting BL Message Into Header Flit; Don't Need Pump 1 - Bubble event=0x58,umask=0x20  01    Header pump 1 is not required for flit but flit transmission delayed unc_m3upi_rxc_flits_slot_bl.p1_not_req_not_avail uncore interconnect Slotting BL Message Into Header Flit; Don't Need Pump 1 - Not Avail event=0x58,umask=0x40  01    Header pump 1 is not required for flit and not available unc_m3upi_rxc_flits_slot_bl.p1_wait uncore interconnect Slotting BL Message Into Header Flit; Wait on Pump 1 event=0x58,umask=8  01    Waiting for header pump 1 unc_m3upi_rxc_flit_gen_hdr1.accum uncore interconnect Flit Gen - Header 1; Accumulate event=0x53,umask=1  01    Events related to Header Flit Generation - Set 1; Header flit slotting control state machine is in any accumulate state; multi-message flit may be assembled over multiple cycles unc_m3upi_rxc_flit_gen_hdr1.accum_read uncore interconnect Flit Gen - Header 1; Accumulate Ready event=0x53,umask=2  01    Events related to Header Flit Generation - Set 1; header flit slotting control state machine is in accum_ready state; flit is ready to send but transmission is blocked; more messages may be slotted into flit unc_m3upi_rxc_flit_gen_hdr1.accum_wasted uncore interconnect Flit Gen - Header 1; Accumulate Wasted event=0x53,umask=4  01    Events related to Header Flit Generation - Set 1; Flit is being assembled over multiple cycles, but no additional message is being slotted into flit in current cycle; accumulate cycle is wasted unc_m3upi_rxc_flit_gen_hdr1.ahead_blocked uncore interconnect Flit Gen - Header 1; Run-Ahead - Blocked event=0x53,umask=8  01    Events related to Header Flit Generation - Set 1; Header flit slotting entered run-ahead state; new header flit is started while transmission of prior, fully assembled flit is blocked unc_m3upi_rxc_flit_gen_hdr1.ahead_msg uncore interconnect Flit Gen - Header 1; Run-Ahead - Message event=0x53,umask=0x10  01    Events related to Header Flit Generation - Set 1; Header flit slotting is in run-ahead to start new flit, and message is actually slotted into new flit unc_m3upi_rxc_flit_gen_hdr1.par uncore interconnect Flit Gen - Header 1; Parallel Ok event=0x53,umask=0x20  01    Events related to Header Flit Generation - Set 1; New header flit construction may proceed in parallel with data flit sequence unc_m3upi_rxc_flit_gen_hdr1.par_flit uncore interconnect Flit Gen - Header 1; Parallel Flit Finished event=0x53,umask=0x80  01    Events related to Header Flit Generation - Set 1; Header flit finished assembly in parallel with data flit sequence unc_m3upi_rxc_flit_gen_hdr1.par_msg uncore interconnect Flit Gen - Header 1; Parallel Message event=0x53,umask=0x40  01    Events related to Header Flit Generation - Set 1; Message is slotted into header flit in parallel with data flit sequence unc_m3upi_rxc_flit_gen_hdr2.rmstall uncore interconnect Flit Gen - Header 2; Rate-matching Stall event=0x54,umask=1  01    Events related to Header Flit Generation - Set 2; Rate-matching stall injected unc_m3upi_rxc_flit_gen_hdr2.rmstall_nomsg uncore interconnect Flit Gen - Header 2; Rate-matching Stall - No Message event=0x54,umask=2  01    Events related to Header Flit Generation - Set 2; Rate matching stall injected, but no additional message slotted during stall cycle unc_m3upi_rxc_flit_not_sent.all uncore interconnect Header Not Sent; All event=0x55,umask=1  01    header flit is ready for transmission but could not be sent unc_m3upi_rxc_flit_not_sent.no_bgf_crd uncore interconnect Header Not Sent; No BGF Credits event=0x55,umask=2  01    header flit is ready for transmission but could not be sent; No BGF credits available unc_m3upi_rxc_flit_not_sent.no_bgf_no_msg uncore interconnect Header Not Sent; No BGF Credits + No Extra Message Slotted event=0x55,umask=8  01    header flit is ready for transmission but could not be sent; No BGF credits available; no additional message slotted into flit unc_m3upi_rxc_flit_not_sent.no_txq_crd uncore interconnect Header Not Sent; No TxQ Credits event=0x55,umask=4  01    header flit is ready for transmission but could not be sent; No TxQ credits available unc_m3upi_rxc_flit_not_sent.no_txq_no_msg uncore interconnect Header Not Sent; No TxQ Credits + No Extra Message Slotted event=0x55,umask=0x10  01    header flit is ready for transmission but could not be sent; No TxQ credits available; no additional message slotted into flit unc_m3upi_rxc_flit_not_sent.one_taken uncore interconnect Header Not Sent; Sent - One Slot Taken event=0x55,umask=0x20  01    header flit is ready for transmission but could not be sent; sending header flit with only one slot taken (two slots free) unc_m3upi_rxc_flit_not_sent.three_taken uncore interconnect Header Not Sent; Sent - Three Slots Taken event=0x55,umask=0x80  01    header flit is ready for transmission but could not be sent; sending header flit with three slots taken (no slots free) unc_m3upi_rxc_flit_not_sent.two_taken uncore interconnect Header Not Sent; Sent - Two Slots Taken event=0x55,umask=0x40  01    header flit is ready for transmission but could not be sent; sending header flit with only two slots taken (one slots free) unc_m3upi_rxc_held.cant_slot_ad uncore interconnect Message Held; Can't Slot AD event=0x52,umask=0x40  01    some AD message could not be slotted (logical OR of all AD events under INGR_SLOT_CANT_MC_VN{0,1}) unc_m3upi_rxc_held.cant_slot_bl uncore interconnect Message Held; Can't Slot BL event=0x52,umask=0x80  01    some BL message could not be slotted (logical OR of all BL events under INGR_SLOT_CANT_MC_VN{0,1}) unc_m3upi_rxc_held.parallel_ad_lost uncore interconnect Message Held; Parallel AD Lost event=0x52,umask=0x10  01    some AD message lost contest for slot 0 (logical OR of all AD events under INGR_SLOT_LOST_MC_VN{0,1}) unc_m3upi_rxc_held.parallel_attempt uncore interconnect Message Held; Parallel Attempt event=0x52,umask=4  01    ad and bl messages attempted to slot into the same flit in parallel unc_m3upi_rxc_held.parallel_bl_lost uncore interconnect Message Held; Parallel BL Lost event=0x52,umask=0x20  01    some BL message lost contest for slot 0 (logical OR of all BL events under INGR_SLOT_LOST_MC_VN{0,1}) unc_m3upi_rxc_held.parallel_success uncore interconnect Message Held; Parallel Success event=0x52,umask=8  01    ad and bl messages were actually slotted into the same flit in parallel unc_m3upi_rxc_held.vn0 uncore interconnect Message Held; VN0 event=0x52,umask=1  01    vn0 message(s) that couldn't be slotted into last vn0 flit are held in slotting stage while processing vn1 flit unc_m3upi_rxc_held.vn1 uncore interconnect Message Held; VN1 event=0x52,umask=2  01    vn1 message(s) that couldn't be slotted into last vn1 flit are held in slotting stage while processing vn0 flit unc_m3upi_rxc_inserts_vn0.ad_req uncore interconnect VN0 Ingress (from CMS) Queue - Inserts; REQ on AD event=0x41,umask=1  01    Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_inserts_vn0.ad_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Inserts; RSP on AD event=0x41,umask=4  01    Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_inserts_vn0.ad_snp uncore interconnect VN0 Ingress (from CMS) Queue - Inserts; SNP on AD event=0x41,umask=2  01    Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_rxc_inserts_vn0.bl_ncb uncore interconnect VN0 Ingress (from CMS) Queue - Inserts; NCB on BL event=0x41,umask=0x20  01    Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_rxc_inserts_vn0.bl_ncs uncore interconnect VN0 Ingress (from CMS) Queue - Inserts; NCS on BL event=0x41,umask=0x40  01    Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_inserts_vn0.bl_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Inserts; RSP on BL event=0x41,umask=8  01    Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_inserts_vn0.bl_wb uncore interconnect VN0 Ingress (from CMS) Queue - Inserts; WB on BL event=0x41,umask=0x10  01    Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_inserts_vn1.ad_req uncore interconnect VN1 Ingress (from CMS) Queue - Inserts; REQ on AD event=0x42,umask=1  01    Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_inserts_vn1.ad_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Inserts; RSP on AD event=0x42,umask=4  01    Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_inserts_vn1.ad_snp uncore interconnect VN1 Ingress (from CMS) Queue - Inserts; SNP on AD event=0x42,umask=2  01    Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_rxc_inserts_vn1.bl_ncb uncore interconnect VN1 Ingress (from CMS) Queue - Inserts; NCB on BL event=0x42,umask=0x20  01    Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_rxc_inserts_vn1.bl_ncs uncore interconnect VN1 Ingress (from CMS) Queue - Inserts; NCS on BL event=0x42,umask=0x40  01    Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_inserts_vn1.bl_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Inserts; RSP on BL event=0x42,umask=8  01    Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_inserts_vn1.bl_wb uncore interconnect VN1 Ingress (from CMS) Queue - Inserts; WB on BL event=0x42,umask=0x10  01    Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_occupancy_vn0.ad_req uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy; REQ on AD event=0x45,umask=1  01    Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_occupancy_vn0.ad_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy; RSP on AD event=0x45,umask=4  01    Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_occupancy_vn0.ad_snp uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy; SNP on AD event=0x45,umask=2  01    Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_rxc_occupancy_vn0.bl_ncb uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy; NCB on BL event=0x45,umask=0x20  01    Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_rxc_occupancy_vn0.bl_ncs uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy; NCS on BL event=0x45,umask=0x40  01    Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_occupancy_vn0.bl_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy; RSP on BL event=0x45,umask=8  01    Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_occupancy_vn0.bl_wb uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy; WB on BL event=0x45,umask=0x10  01    Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_occupancy_vn1.ad_req uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy; REQ on AD event=0x46,umask=1  01    Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_occupancy_vn1.ad_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy; RSP on AD event=0x46,umask=4  01    Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_occupancy_vn1.ad_snp uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy; SNP on AD event=0x46,umask=2  01    Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_rxc_occupancy_vn1.bl_ncb uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy; NCB on BL event=0x46,umask=0x20  01    Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_rxc_occupancy_vn1.bl_ncs uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy; NCS on BL event=0x46,umask=0x40  01    Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_occupancy_vn1.bl_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy; RSP on BL event=0x46,umask=8  01    Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_occupancy_vn1.bl_wb uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy; WB on BL event=0x46,umask=0x10  01    Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_packing_miss_vn0.ad_req uncore interconnect VN0 message can't slot into flit; REQ on AD event=0x4e,umask=1  01    Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_packing_miss_vn0.ad_rsp uncore interconnect VN0 message can't slot into flit; RSP on AD event=0x4e,umask=4  01    Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_packing_miss_vn0.ad_snp uncore interconnect VN0 message can't slot into flit; SNP on AD event=0x4e,umask=2  01    Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_rxc_packing_miss_vn0.bl_ncb uncore interconnect VN0 message can't slot into flit; NCB on BL event=0x4e,umask=0x20  01    Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_rxc_packing_miss_vn0.bl_ncs uncore interconnect VN0 message can't slot into flit; NCS on BL event=0x4e,umask=0x40  01    Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_packing_miss_vn0.bl_rsp uncore interconnect VN0 message can't slot into flit; RSP on BL event=0x4e,umask=8  01    Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_packing_miss_vn0.bl_wb uncore interconnect VN0 message can't slot into flit; WB on BL event=0x4e,umask=0x10  01    Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_packing_miss_vn1.ad_req uncore interconnect VN1 message can't slot into flit; REQ on AD event=0x4f,umask=1  01    Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_packing_miss_vn1.ad_rsp uncore interconnect VN1 message can't slot into flit; RSP on AD event=0x4f,umask=4  01    Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_packing_miss_vn1.ad_snp uncore interconnect VN1 message can't slot into flit; SNP on AD event=0x4f,umask=2  01    Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_rxc_packing_miss_vn1.bl_ncb uncore interconnect VN1 message can't slot into flit; NCB on BL event=0x4f,umask=0x20  01    Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_rxc_packing_miss_vn1.bl_ncs uncore interconnect VN1 message can't slot into flit; NCS on BL event=0x4f,umask=0x40  01    Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_packing_miss_vn1.bl_rsp uncore interconnect VN1 message can't slot into flit; RSP on BL event=0x4f,umask=8  01    Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_packing_miss_vn1.bl_wb uncore interconnect VN1 message can't slot into flit; WB on BL event=0x4f,umask=0x10  01    Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_smi3_pftch.arb_lost uncore interconnect SMI3 Prefetch Messages; Lost Arbitration event=0x62,umask=2  01     unc_m3upi_rxc_smi3_pftch.arrived uncore interconnect SMI3 Prefetch Messages; Arrived event=0x62,umask=1  01     unc_m3upi_rxc_smi3_pftch.drop_old uncore interconnect SMI3 Prefetch Messages; Dropped - Old event=0x62,umask=8  01     unc_m3upi_rxc_smi3_pftch.drop_wrap uncore interconnect SMI3 Prefetch Messages; Dropped - Wrap event=0x62,umask=0x10  01    Dropped because it was overwritten by new message while prefetch queue was full unc_m3upi_rxc_smi3_pftch.slotted uncore interconnect SMI3 Prefetch Messages; Slotted event=0x62,umask=4  01     unc_m3upi_rxc_vna_crd.any_in_use uncore interconnect Remote VNA Credits; Any In Use event=0x5b,umask=0x20  01    At least one remote vna credit is in use unc_m3upi_rxc_vna_crd.corrected uncore interconnect Remote VNA Credits; Corrected event=0x5b,umask=2  01    Number of remote vna credits corrected (local return) per cycle unc_m3upi_rxc_vna_crd.lt1 uncore interconnect Remote VNA Credits; Level < 1 event=0x5b,umask=4  01    Remote vna credit level is less than 1 (i.e. no vna credits available) unc_m3upi_rxc_vna_crd.lt4 uncore interconnect Remote VNA Credits; Level < 4 event=0x5b,umask=8  01    Remote vna credit level is less than 4; bl (or ad requiring 4 vna) cannot arb on vna unc_m3upi_rxc_vna_crd.lt5 uncore interconnect Remote VNA Credits; Level < 5 event=0x5b,umask=0x10  01    Remote vna credit level is less than 5; parallel ad/bl arb on vna not possible unc_m3upi_rxc_vna_crd.used uncore interconnect Remote VNA Credits; Used event=0x5b,umask=1  01    Number of remote vna credits consumed per cycle unc_m3upi_rxr_busy_starved.ad_bnc uncore interconnect Transgress Injection Starvation; AD - Bounce event=0xb4,umask=1  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority unc_m3upi_rxr_busy_starved.ad_crd uncore interconnect Transgress Injection Starvation; AD - Credit event=0xb4,umask=0x10  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority unc_m3upi_rxr_busy_starved.bl_bnc uncore interconnect Transgress Injection Starvation; BL - Bounce event=0xb4,umask=4  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority unc_m3upi_rxr_busy_starved.bl_crd uncore interconnect Transgress Injection Starvation; BL - Credit event=0xb4,umask=0x40  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority unc_m3upi_rxr_bypass.ad_bnc uncore interconnect Transgress Ingress Bypass; AD - Bounce event=0xb2,umask=1  01    Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.ad_crd uncore interconnect Transgress Ingress Bypass; AD - Credit event=0xb2,umask=0x10  01    Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.ak_bnc uncore interconnect Transgress Ingress Bypass; AK - Bounce event=0xb2,umask=2  01    Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.bl_bnc uncore interconnect Transgress Ingress Bypass; BL - Bounce event=0xb2,umask=4  01    Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.bl_crd uncore interconnect Transgress Ingress Bypass; BL - Credit event=0xb2,umask=0x40  01    Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.iv_bnc uncore interconnect Transgress Ingress Bypass; IV - Bounce event=0xb2,umask=8  01    Number of packets bypassing the CMS Ingress unc_m3upi_rxr_crd_starved.ad_bnc uncore interconnect Transgress Injection Starvation; AD - Bounce event=0xb3,umask=1  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.ad_crd uncore interconnect Transgress Injection Starvation; AD - Credit event=0xb3,umask=0x10  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.ak_bnc uncore interconnect Transgress Injection Starvation; AK - Bounce event=0xb3,umask=2  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.bl_bnc uncore interconnect Transgress Injection Starvation; BL - Bounce event=0xb3,umask=4  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.bl_crd uncore interconnect Transgress Injection Starvation; BL - Credit event=0xb3,umask=0x40  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.ifv uncore interconnect Transgress Injection Starvation; IFV - Credit event=0xb3,umask=0x80  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.iv_bnc uncore interconnect Transgress Injection Starvation; IV - Bounce event=0xb3,umask=8  01    Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_inserts.ad_bnc uncore interconnect Transgress Ingress Allocations; AD - Bounce event=0xb1,umask=1  01    Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.ad_crd uncore interconnect Transgress Ingress Allocations; AD - Credit event=0xb1,umask=0x10  01    Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.ak_bnc uncore interconnect Transgress Ingress Allocations; AK - Bounce event=0xb1,umask=2  01    Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.bl_bnc uncore interconnect Transgress Ingress Allocations; BL - Bounce event=0xb1,umask=4  01    Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.bl_crd uncore interconnect Transgress Ingress Allocations; BL - Credit event=0xb1,umask=0x40  01    Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.iv_bnc uncore interconnect Transgress Ingress Allocations; IV - Bounce event=0xb1,umask=8  01    Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.ad_bnc uncore interconnect Transgress Ingress Occupancy; AD - Bounce event=0xb0,umask=1  01    Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.ad_crd uncore interconnect Transgress Ingress Occupancy; AD - Credit event=0xb0,umask=0x10  01    Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.ak_bnc uncore interconnect Transgress Ingress Occupancy; AK - Bounce event=0xb0,umask=2  01    Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.bl_bnc uncore interconnect Transgress Ingress Occupancy; BL - Bounce event=0xb0,umask=4  01    Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.bl_crd uncore interconnect Transgress Ingress Occupancy; BL - Credit event=0xb0,umask=0x40  01    Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.iv_bnc uncore interconnect Transgress Ingress Occupancy; IV - Bounce event=0xb0,umask=8  01    Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m3upi_stall_no_txr_horz_crd_ad_ag0.tgr0 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 0 event=0xd0,umask=1  01    Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag0.tgr1 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 1 event=0xd0,umask=2  01    Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag0.tgr2 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 2 event=0xd0,umask=4  01    Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag0.tgr3 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 3 event=0xd0,umask=8  01    Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag0.tgr4 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 4 event=0xd0,umask=0x10  01    Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag0.tgr5 uncore interconnect Stall on No AD Agent0 Transgress Credits; For Transgress 5 event=0xd0,umask=0x20  01    Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag1.tgr0 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 0 event=0xd2,umask=1  01    Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag1.tgr1 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 1 event=0xd2,umask=2  01    Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag1.tgr2 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 2 event=0xd2,umask=4  01    Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag1.tgr3 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 3 event=0xd2,umask=8  01    Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag1.tgr4 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 4 event=0xd2,umask=0x10  01    Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_ad_ag1.tgr5 uncore interconnect Stall on No AD Agent1 Transgress Credits; For Transgress 5 event=0xd2,umask=0x20  01    Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag0.tgr0 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 0 event=0xd4,umask=1  01    Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag0.tgr1 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 1 event=0xd4,umask=2  01    Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag0.tgr2 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 2 event=0xd4,umask=4  01    Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag0.tgr3 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 3 event=0xd4,umask=8  01    Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag0.tgr4 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 4 event=0xd4,umask=0x10  01    Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag0.tgr5 uncore interconnect Stall on No BL Agent0 Transgress Credits; For Transgress 5 event=0xd4,umask=0x20  01    Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag1.tgr0 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 0 event=0xd6,umask=1  01    Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag1.tgr1 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 1 event=0xd6,umask=2  01    Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag1.tgr2 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 2 event=0xd6,umask=4  01    Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag1.tgr3 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 3 event=0xd6,umask=8  01    Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag1.tgr4 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 4 event=0xd6,umask=0x10  01    Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall_no_txr_horz_crd_bl_ag1.tgr5 uncore interconnect Stall on No BL Agent1 Transgress Credits; For Transgress 5 event=0xd6,umask=0x20  01    Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_txc_ad_arb_fail.vn0_req uncore interconnect Failed ARB for AD; VN0 REQ Messages event=0x30,umask=1  01    AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn0_rsp uncore interconnect Failed ARB for AD; VN0 RSP Messages event=0x30,umask=4  01    AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn0_snp uncore interconnect Failed ARB for AD; VN0 SNP Messages event=0x30,umask=2  01    AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn0_wb uncore interconnect Failed ARB for AD; VN0 WB Messages event=0x30,umask=8  01    AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn1_req uncore interconnect Failed ARB for AD; VN1 REQ Messages event=0x30,umask=0x10  01    AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn1_rsp uncore interconnect Failed ARB for AD; VN1 RSP Messages event=0x30,umask=0x40  01    AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn1_snp uncore interconnect Failed ARB for AD; VN1 SNP Messages event=0x30,umask=0x20  01    AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn1_wb uncore interconnect Failed ARB for AD; VN1 WB Messages event=0x30,umask=0x80  01    AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_flq_bypass.ad_slot0 uncore interconnect AD FlowQ Bypass event=0x2c,umask=1  01    Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least) unc_m3upi_txc_ad_flq_bypass.ad_slot1 uncore interconnect AD FlowQ Bypass event=0x2c,umask=2  01    Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least) unc_m3upi_txc_ad_flq_bypass.ad_slot2 uncore interconnect AD FlowQ Bypass event=0x2c,umask=4  01    Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least) unc_m3upi_txc_ad_flq_bypass.bl_early_rsp uncore interconnect AD FlowQ Bypass event=0x2c,umask=8  01    Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least) unc_m3upi_txc_ad_flq_cycles_ne.vn0_req uncore interconnect AD Flow Q Not Empty; VN0 REQ Messages event=0x27,umask=1  01    Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn0_rsp uncore interconnect AD Flow Q Not Empty; VN0 RSP Messages event=0x27,umask=4  01    Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn0_snp uncore interconnect AD Flow Q Not Empty; VN0 SNP Messages event=0x27,umask=2  01    Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn0_wb uncore interconnect AD Flow Q Not Empty; VN0 WB Messages event=0x27,umask=8  01    Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn1_req uncore interconnect AD Flow Q Not Empty; VN1 REQ Messages event=0x27,umask=0x10  01    Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn1_rsp uncore interconnect AD Flow Q Not Empty; VN1 RSP Messages event=0x27,umask=0x40  01    Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn1_snp uncore interconnect AD Flow Q Not Empty; VN1 SNP Messages event=0x27,umask=0x20  01    Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn1_wb uncore interconnect AD Flow Q Not Empty; VN1 WB Messages event=0x27,umask=0x80  01    Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_inserts.vn0_req uncore interconnect AD Flow Q Inserts; VN0 REQ Messages event=0x2d,umask=1  01    Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn0_rsp uncore interconnect AD Flow Q Inserts; VN0 RSP Messages event=0x2d,umask=4  01    Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn0_snp uncore interconnect AD Flow Q Inserts; VN0 SNP Messages event=0x2d,umask=2  01    Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn0_wb uncore interconnect AD Flow Q Inserts; VN0 WB Messages event=0x2d,umask=8  01    Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn1_req uncore interconnect AD Flow Q Inserts; VN1 REQ Messages event=0x2d,umask=0x10  01    Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn1_rsp uncore interconnect AD Flow Q Inserts; VN1 RSP Messages event=0x2d,umask=0x40  01    Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn1_snp uncore interconnect AD Flow Q Inserts; VN1 SNP Messages event=0x2d,umask=0x20  01    Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_occupancy.vn0_req uncore interconnect AD Flow Q Occupancy; VN0 REQ Messages event=0x1c,umask=1  01     unc_m3upi_txc_ad_flq_occupancy.vn0_rsp uncore interconnect AD Flow Q Occupancy; VN0 RSP Messages event=0x1c,umask=4  01     unc_m3upi_txc_ad_flq_occupancy.vn0_snp uncore interconnect AD Flow Q Occupancy; VN0 SNP Messages event=0x1c,umask=2  01     unc_m3upi_txc_ad_flq_occupancy.vn0_wb uncore interconnect AD Flow Q Occupancy; VN0 WB Messages event=0x1c,umask=8  01     unc_m3upi_txc_ad_flq_occupancy.vn1_req uncore interconnect AD Flow Q Occupancy; VN1 REQ Messages event=0x1c,umask=0x10  01     unc_m3upi_txc_ad_flq_occupancy.vn1_rsp uncore interconnect AD Flow Q Occupancy; VN1 RSP Messages event=0x1c,umask=0x40  01     unc_m3upi_txc_ad_flq_occupancy.vn1_snp uncore interconnect AD Flow Q Occupancy; VN1 SNP Messages event=0x1c,umask=0x20  01     unc_m3upi_txc_ad_snpf_grp1_vn1.vn0_cha uncore interconnect Number of Snoop Targets; CHA on VN0 event=0x3c,umask=4  01    Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to CHA unc_m3upi_txc_ad_snpf_grp1_vn1.vn0_non_idle uncore interconnect Number of Snoop Targets; Non Idle cycles on VN0 event=0x3c,umask=0x40  01    Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of non-idle cycles in issuing Vn0 Snpf unc_m3upi_txc_ad_snpf_grp1_vn1.vn0_peer_upi0 uncore interconnect Number of Snoop Targets; Peer UPI0 on VN0 event=0x3c,umask=1  01    Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to peer UPI0 unc_m3upi_txc_ad_snpf_grp1_vn1.vn0_peer_upi1 uncore interconnect Number of Snoop Targets; Peer UPI1 on VN0 event=0x3c,umask=2  01    Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to peer UPI1 unc_m3upi_txc_ad_snpf_grp1_vn1.vn1_cha uncore interconnect Number of Snoop Targets; CHA on VN1 event=0x3c,umask=0x20  01    Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to CHA unc_m3upi_txc_ad_snpf_grp1_vn1.vn1_non_idle uncore interconnect Number of Snoop Targets; Non Idle cycles on VN1 event=0x3c,umask=0x80  01    Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of non-idle cycles in issuing Vn1 Snpf unc_m3upi_txc_ad_snpf_grp1_vn1.vn1_peer_upi0 uncore interconnect Number of Snoop Targets; Peer UPI0 on VN1 event=0x3c,umask=8  01    Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to peer UPI0 unc_m3upi_txc_ad_snpf_grp1_vn1.vn1_peer_upi1 uncore interconnect Number of Snoop Targets; Peer UPI1 on VN1 event=0x3c,umask=0x10  01    Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to peer UPI1 unc_m3upi_txc_ad_snpf_grp2_vn1.vn0_snpfp_nonsnp uncore interconnect Snoop Arbitration; FlowQ Won event=0x3d,umask=1  01    Outcome of SnpF pending arbitration; FlowQ txn issued when SnpF pending on Vn0 unc_m3upi_txc_ad_snpf_grp2_vn1.vn0_snpfp_vn2snp uncore interconnect Snoop Arbitration; FlowQ SnpF Won event=0x3d,umask=4  01    Outcome of SnpF pending arbitration; FlowQ Vn0 SnpF issued when SnpF pending on Vn1 unc_m3upi_txc_ad_snpf_grp2_vn1.vn1_snpfp_nonsnp uncore interconnect Snoop Arbitration; FlowQ Won event=0x3d,umask=2  01    Outcome of SnpF pending arbitration; FlowQ txn issued when SnpF pending on Vn1 unc_m3upi_txc_ad_snpf_grp2_vn1.vn1_snpfp_vn0snp uncore interconnect Snoop Arbitration; FlowQ SnpF Won event=0x3d,umask=8  01    Outcome of SnpF pending arbitration; FlowQ Vn1 SnpF issued when SnpF pending on Vn0 unc_m3upi_txc_ad_spec_arb_crd_avail.vn0_req uncore interconnect Speculative ARB for AD  -  Credit Available; VN0 REQ Messages event=0x34,umask=1  01    AD speculative arb request with prior cycle credit check complete and credit avail unc_m3upi_txc_ad_spec_arb_crd_avail.vn0_snp uncore interconnect Speculative ARB for AD  -  Credit Available; VN0 SNP Messages event=0x34,umask=2  01    AD speculative arb request with prior cycle credit check complete and credit avail unc_m3upi_txc_ad_spec_arb_crd_avail.vn0_wb uncore interconnect Speculative ARB for AD  -  Credit Available; VN0 WB Messages event=0x34,umask=8  01    AD speculative arb request with prior cycle credit check complete and credit avail unc_m3upi_txc_ad_spec_arb_crd_avail.vn1_req uncore interconnect Speculative ARB for AD  -  Credit Available; VN1 REQ Messages event=0x34,umask=0x10  01    AD speculative arb request with prior cycle credit check complete and credit avail unc_m3upi_txc_ad_spec_arb_crd_avail.vn1_snp uncore interconnect Speculative ARB for AD  -  Credit Available; VN1 SNP Messages event=0x34,umask=0x20  01    AD speculative arb request with prior cycle credit check complete and credit avail unc_m3upi_txc_ad_spec_arb_crd_avail.vn1_wb uncore interconnect Speculative ARB for AD  -  Credit Available; VN1 WB Messages event=0x34,umask=0x80  01    AD speculative arb request with prior cycle credit check complete and credit avail unc_m3upi_txc_ad_spec_arb_new_msg.vn0_req uncore interconnect Speculative ARB for AD  - New Message; VN0 REQ Messages event=0x33,umask=1  01    AD speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_ad_spec_arb_new_msg.vn0_snp uncore interconnect Speculative ARB for AD  - New Message; VN0 SNP Messages event=0x33,umask=2  01    AD speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_ad_spec_arb_new_msg.vn0_wb uncore interconnect Speculative ARB for AD  - New Message; VN0 WB Messages event=0x33,umask=8  01    AD speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_ad_spec_arb_new_msg.vn1_req uncore interconnect Speculative ARB for AD  - New Message; VN1 REQ Messages event=0x33,umask=0x10  01    AD speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_ad_spec_arb_new_msg.vn1_snp uncore interconnect Speculative ARB for AD  - New Message; VN1 SNP Messages event=0x33,umask=0x20  01    AD speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_ad_spec_arb_new_msg.vn1_wb uncore interconnect Speculative ARB for AD  - New Message; VN1 WB Messages event=0x33,umask=0x80  01    AD speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_ad_spec_arb_no_other_pend.vn0_req uncore interconnect Speculative ARB for AD  - No Credit; VN0 REQ Messages event=0x32,umask=1  01    AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_ad_spec_arb_no_other_pend.vn0_rsp uncore interconnect Speculative ARB for AD  - No Credit; VN0 RSP Messages event=0x32,umask=4  01    AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_ad_spec_arb_no_other_pend.vn0_snp uncore interconnect Speculative ARB for AD  - No Credit; VN0 SNP Messages event=0x32,umask=2  01    AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_ad_spec_arb_no_other_pend.vn0_wb uncore interconnect Speculative ARB for AD  - No Credit; VN0 WB Messages event=0x32,umask=8  01    AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_ad_spec_arb_no_other_pend.vn1_req uncore interconnect Speculative ARB for AD  - No Credit; VN1 REQ Messages event=0x32,umask=0x10  01    AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_ad_spec_arb_no_other_pend.vn1_rsp uncore interconnect Speculative ARB for AD  - No Credit; VN1 RSP Messages event=0x32,umask=0x40  01    AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_ad_spec_arb_no_other_pend.vn1_snp uncore interconnect Speculative ARB for AD  - No Credit; VN1 SNP Messages event=0x32,umask=0x20  01    AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_ad_spec_arb_no_other_pend.vn1_wb uncore interconnect Speculative ARB for AD  - No Credit; VN1 WB Messages event=0x32,umask=0x80  01    AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_ak_flq_inserts uncore interconnect AK Flow Q Inserts event=0x2f  01     unc_m3upi_txc_ak_flq_occupancy uncore interconnect AK Flow Q Occupancy event=0x1e  01     unc_m3upi_txc_bl_arb_fail.vn0_ncb uncore interconnect Failed ARB for BL; VN0 NCB Messages event=0x35,umask=4  01    BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn0_ncs uncore interconnect Failed ARB for BL; VN0 NCS Messages event=0x35,umask=8  01    BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn0_rsp uncore interconnect Failed ARB for BL; VN0 RSP Messages event=0x35,umask=1  01    BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn0_wb uncore interconnect Failed ARB for BL; VN0 WB Messages event=0x35,umask=2  01    BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn1_ncb uncore interconnect Failed ARB for BL; VN1 NCS Messages event=0x35,umask=0x40  01    BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn1_ncs uncore interconnect Failed ARB for BL; VN1 NCB Messages event=0x35,umask=0x80  01    BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn1_rsp uncore interconnect Failed ARB for BL; VN1 RSP Messages event=0x35,umask=0x10  01    BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn1_wb uncore interconnect Failed ARB for BL; VN1 WB Messages event=0x35,umask=0x20  01    BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_flq_cycles_ne.vn0_req uncore interconnect BL Flow Q Not Empty; VN0 REQ Messages event=0x28,umask=1  01    Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn0_rsp uncore interconnect BL Flow Q Not Empty; VN0 RSP Messages event=0x28,umask=4  01    Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn0_snp uncore interconnect BL Flow Q Not Empty; VN0 SNP Messages event=0x28,umask=2  01    Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn0_wb uncore interconnect BL Flow Q Not Empty; VN0 WB Messages event=0x28,umask=8  01    Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn1_req uncore interconnect BL Flow Q Not Empty; VN1 REQ Messages event=0x28,umask=0x10  01    Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn1_rsp uncore interconnect BL Flow Q Not Empty; VN1 RSP Messages event=0x28,umask=0x40  01    Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn1_snp uncore interconnect BL Flow Q Not Empty; VN1 SNP Messages event=0x28,umask=0x20  01    Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn1_wb uncore interconnect BL Flow Q Not Empty; VN1 WB Messages event=0x28,umask=0x80  01    Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_inserts.vn0_ncb uncore interconnect BL Flow Q Inserts; VN0 RSP Messages event=0x2e,umask=1  01    Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn0_ncs uncore interconnect BL Flow Q Inserts; VN0 WB Messages event=0x2e,umask=2  01    Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn0_rsp uncore interconnect BL Flow Q Inserts; VN0 NCS Messages event=0x2e,umask=8  01    Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn0_wb uncore interconnect BL Flow Q Inserts; VN0 NCB Messages event=0x2e,umask=4  01    Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn1_ncb uncore interconnect BL Flow Q Inserts; VN1 RSP Messages event=0x2e,umask=0x10  01    Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn1_ncs uncore interconnect BL Flow Q Inserts; VN1 WB Messages event=0x2e,umask=0x20  01    Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn1_rsp uncore interconnect BL Flow Q Inserts; VN1_NCB Messages event=0x2e,umask=0x80  01    Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn1_wb uncore interconnect BL Flow Q Inserts; VN1_NCS Messages event=0x2e,umask=0x40  01    Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_occupancy.vn0_ncb uncore interconnect BL Flow Q Occupancy; VN0 NCB Messages event=0x1d,umask=4  01     unc_m3upi_txc_bl_flq_occupancy.vn0_ncs uncore interconnect BL Flow Q Occupancy; VN0 NCS Messages event=0x1d,umask=8  01     unc_m3upi_txc_bl_flq_occupancy.vn0_rsp uncore interconnect BL Flow Q Occupancy; VN0 RSP Messages event=0x1d,umask=1  01     unc_m3upi_txc_bl_flq_occupancy.vn0_wb uncore interconnect BL Flow Q Occupancy; VN0 WB Messages event=0x1d,umask=2  01     unc_m3upi_txc_bl_flq_occupancy.vn1_ncb uncore interconnect BL Flow Q Occupancy; VN1_NCS Messages event=0x1d,umask=0x40  01     unc_m3upi_txc_bl_flq_occupancy.vn1_ncs uncore interconnect BL Flow Q Occupancy; VN1_NCB Messages event=0x1d,umask=0x80  01     unc_m3upi_txc_bl_flq_occupancy.vn1_rsp uncore interconnect BL Flow Q Occupancy; VN1 RSP Messages event=0x1d,umask=0x10  01     unc_m3upi_txc_bl_flq_occupancy.vn1_wb uncore interconnect BL Flow Q Occupancy; VN1 WB Messages event=0x1d,umask=0x20  01     unc_m3upi_txc_bl_spec_arb_new_msg.vn0_ncb uncore interconnect Speculative ARB for BL  - New Message; VN0 WB Messages event=0x38,umask=2  01    BL speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_bl_spec_arb_new_msg.vn0_ncs uncore interconnect Speculative ARB for BL  - New Message; VN0 NCS Messages event=0x38,umask=8  01    BL speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_bl_spec_arb_new_msg.vn0_wb uncore interconnect Speculative ARB for BL  - New Message; VN0 WB Messages event=0x38,umask=1  01    BL speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_bl_spec_arb_new_msg.vn1_ncb uncore interconnect Speculative ARB for BL  - New Message; VN1 WB Messages event=0x38,umask=0x20  01    BL speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_bl_spec_arb_new_msg.vn1_ncs uncore interconnect Speculative ARB for BL  - New Message; VN1 NCB Messages event=0x38,umask=0x80  01    BL speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_bl_spec_arb_new_msg.vn1_wb uncore interconnect Speculative ARB for BL  - New Message; VN1 RSP Messages event=0x38,umask=0x10  01    BL speculative arb request due to new message arriving on a specific channel (MC/VN) unc_m3upi_txc_bl_spec_arb_no_other_pend.vn0_ncb uncore interconnect Speculative ARB for AD Failed - No Credit; VN0 NCB Messages event=0x37,umask=4  01    BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_bl_spec_arb_no_other_pend.vn0_ncs uncore interconnect Speculative ARB for AD Failed - No Credit; VN0 NCS Messages event=0x37,umask=8  01    BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_bl_spec_arb_no_other_pend.vn0_rsp uncore interconnect Speculative ARB for AD Failed - No Credit; VN0 RSP Messages event=0x37,umask=1  01    BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_bl_spec_arb_no_other_pend.vn0_wb uncore interconnect Speculative ARB for AD Failed - No Credit; VN0 WB Messages event=0x37,umask=2  01    BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_bl_spec_arb_no_other_pend.vn1_ncb uncore interconnect Speculative ARB for AD Failed - No Credit; VN1 NCS Messages event=0x37,umask=0x40  01    BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_bl_spec_arb_no_other_pend.vn1_ncs uncore interconnect Speculative ARB for AD Failed - No Credit; VN1 NCB Messages event=0x37,umask=0x80  01    BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_bl_spec_arb_no_other_pend.vn1_rsp uncore interconnect Speculative ARB for AD Failed - No Credit; VN1 RSP Messages event=0x37,umask=0x10  01    BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txc_bl_spec_arb_no_other_pend.vn1_wb uncore interconnect Speculative ARB for AD Failed - No Credit; VN1 WB Messages event=0x37,umask=0x20  01    BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send) unc_m3upi_txr_horz_ads_used.ad_bnc uncore interconnect CMS Horizontal ADS Used; AD - Bounce event=0x9d,umask=1  01    Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_horz_ads_used.ad_crd uncore interconnect CMS Horizontal ADS Used; AD - Credit event=0x9d,umask=0x10  01    Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_horz_ads_used.ak_bnc uncore interconnect CMS Horizontal ADS Used; AK - Bounce event=0x9d,umask=2  01    Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_horz_ads_used.bl_bnc uncore interconnect CMS Horizontal ADS Used; BL - Bounce event=0x9d,umask=4  01    Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_horz_ads_used.bl_crd uncore interconnect CMS Horizontal ADS Used; BL - Credit event=0x9d,umask=0x40  01    Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.ad_bnc uncore interconnect CMS Horizontal Bypass Used; AD - Bounce event=0x9f,umask=1  01    Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.ad_crd uncore interconnect CMS Horizontal Bypass Used; AD - Credit event=0x9f,umask=0x10  01    Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.ak_bnc uncore interconnect CMS Horizontal Bypass Used; AK - Bounce event=0x9f,umask=2  01    Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.bl_bnc uncore interconnect CMS Horizontal Bypass Used; BL - Bounce event=0x9f,umask=4  01    Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.bl_crd uncore interconnect CMS Horizontal Bypass Used; BL - Credit event=0x9f,umask=0x40  01    Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.iv_bnc uncore interconnect CMS Horizontal Bypass Used; IV - Bounce event=0x9f,umask=8  01    Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_cycles_full.ad_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Full; AD - Bounce event=0x96,umask=1  01    Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.ad_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Full; AD - Credit event=0x96,umask=0x10  01    Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.ak_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Full; AK - Bounce event=0x96,umask=2  01    Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.bl_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Full; BL - Bounce event=0x96,umask=4  01    Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.bl_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Full; BL - Credit event=0x96,umask=0x40  01    Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.iv_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Full; IV - Bounce event=0x96,umask=8  01    Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.ad_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce event=0x97,umask=1  01    Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.ad_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit event=0x97,umask=0x10  01    Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.ak_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce event=0x97,umask=2  01    Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.bl_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce event=0x97,umask=4  01    Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.bl_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit event=0x97,umask=0x40  01    Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.iv_bnc uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce event=0x97,umask=8  01    Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.ad_bnc uncore interconnect CMS Horizontal Egress Inserts; AD - Bounce event=0x95,umask=1  01    Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.ad_crd uncore interconnect CMS Horizontal Egress Inserts; AD - Credit event=0x95,umask=0x10  01    Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.ak_bnc uncore interconnect CMS Horizontal Egress Inserts; AK - Bounce event=0x95,umask=2  01    Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.bl_bnc uncore interconnect CMS Horizontal Egress Inserts; BL - Bounce event=0x95,umask=4  01    Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.bl_crd uncore interconnect CMS Horizontal Egress Inserts; BL - Credit event=0x95,umask=0x40  01    Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.iv_bnc uncore interconnect CMS Horizontal Egress Inserts; IV - Bounce event=0x95,umask=8  01    Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_nack.ad_bnc uncore interconnect CMS Horizontal Egress NACKs; AD - Bounce event=0x99,umask=1  01    Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.ad_crd uncore interconnect CMS Horizontal Egress NACKs; AD - Credit event=0x99,umask=0x20  01    Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.ak_bnc uncore interconnect CMS Horizontal Egress NACKs; AK - Bounce event=0x99,umask=2  01    Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.bl_bnc uncore interconnect CMS Horizontal Egress NACKs; BL - Bounce event=0x99,umask=4  01    Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.bl_crd uncore interconnect CMS Horizontal Egress NACKs; BL - Credit event=0x99,umask=0x40  01    Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.iv_bnc uncore interconnect CMS Horizontal Egress NACKs; IV - Bounce event=0x99,umask=8  01    Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_occupancy.ad_bnc uncore interconnect CMS Horizontal Egress Occupancy; AD - Bounce event=0x94,umask=1  01    Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.ad_crd uncore interconnect CMS Horizontal Egress Occupancy; AD - Credit event=0x94,umask=0x10  01    Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.ak_bnc uncore interconnect CMS Horizontal Egress Occupancy; AK - Bounce event=0x94,umask=2  01    Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.bl_bnc uncore interconnect CMS Horizontal Egress Occupancy; BL - Bounce event=0x94,umask=4  01    Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.bl_crd uncore interconnect CMS Horizontal Egress Occupancy; BL - Credit event=0x94,umask=0x40  01    Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.iv_bnc uncore interconnect CMS Horizontal Egress Occupancy; IV - Bounce event=0x94,umask=8  01    Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_starved.ad_bnc uncore interconnect CMS Horizontal Egress Injection Starvation; AD - Bounce event=0x9b,umask=1  01    Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m3upi_txr_horz_starved.ak_bnc uncore interconnect CMS Horizontal Egress Injection Starvation; AK - Bounce event=0x9b,umask=2  01    Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m3upi_txr_horz_starved.bl_bnc uncore interconnect CMS Horizontal Egress Injection Starvation; BL - Bounce event=0x9b,umask=4  01    Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m3upi_txr_horz_starved.iv_bnc uncore interconnect CMS Horizontal Egress Injection Starvation; IV - Bounce event=0x9b,umask=8  01    Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m3upi_txr_vert_ads_used.ad_ag0 uncore interconnect CMS Vertical ADS Used; AD - Agent 0 event=0x9c,umask=1  01    Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_vert_ads_used.ad_ag1 uncore interconnect CMS Vertical ADS Used; AD - Agent 1 event=0x9c,umask=0x10  01    Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_vert_ads_used.ak_ag0 uncore interconnect CMS Vertical ADS Used; AK - Agent 0 event=0x9c,umask=2  01    Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_vert_ads_used.ak_ag1 uncore interconnect CMS Vertical ADS Used; AK - Agent 1 event=0x9c,umask=0x20  01    Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_vert_ads_used.bl_ag0 uncore interconnect CMS Vertical ADS Used; BL - Agent 0 event=0x9c,umask=4  01    Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_vert_ads_used.bl_ag1 uncore interconnect CMS Vertical ADS Used; BL - Agent 1 event=0x9c,umask=0x40  01    Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.ad_ag0 uncore interconnect CMS Vertical ADS Used; AD - Agent 0 event=0x9e,umask=1  01    Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.ad_ag1 uncore interconnect CMS Vertical ADS Used; AD - Agent 1 event=0x9e,umask=0x10  01    Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.ak_ag0 uncore interconnect CMS Vertical ADS Used; AK - Agent 0 event=0x9e,umask=2  01    Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.ak_ag1 uncore interconnect CMS Vertical ADS Used; AK - Agent 1 event=0x9e,umask=0x20  01    Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.bl_ag0 uncore interconnect CMS Vertical ADS Used; BL - Agent 0 event=0x9e,umask=4  01    Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.bl_ag1 uncore interconnect CMS Vertical ADS Used; BL - Agent 1 event=0x9e,umask=0x40  01    Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.iv uncore interconnect CMS Vertical ADS Used; IV event=0x9e,umask=8  01    Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_cycles_full.ad_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0 event=0x92,umask=1  01    Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_cycles_full.ad_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1 event=0x92,umask=0x10  01    Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests unc_m3upi_txr_vert_cycles_full.ak_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0 event=0x92,umask=2  01    Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_cycles_full.ak_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1 event=0x92,umask=0x20  01    Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_m3upi_txr_vert_cycles_full.bl_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0 event=0x92,umask=4  01    Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations unc_m3upi_txr_vert_cycles_full.bl_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1 event=0x92,umask=0x40  01    Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache unc_m3upi_txr_vert_cycles_full.iv uncore interconnect Cycles CMS Vertical Egress Queue Is Full; IV event=0x92,umask=8  01    Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores unc_m3upi_txr_vert_cycles_ne.ad_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0 event=0x93,umask=1  01    Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_cycles_ne.ad_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1 event=0x93,umask=0x10  01    Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests unc_m3upi_txr_vert_cycles_ne.ak_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0 event=0x93,umask=2  01    Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_cycles_ne.ak_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1 event=0x93,umask=0x20  01    Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_m3upi_txr_vert_cycles_ne.bl_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0 event=0x93,umask=4  01    Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations unc_m3upi_txr_vert_cycles_ne.bl_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1 event=0x93,umask=0x40  01    Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache unc_m3upi_txr_vert_cycles_ne.iv uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty; IV event=0x93,umask=8  01    Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores unc_m3upi_txr_vert_inserts.ad_ag0 uncore interconnect CMS Vert Egress Allocations; AD - Agent 0 event=0x91,umask=1  01    Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_inserts.ad_ag1 uncore interconnect CMS Vert Egress Allocations; AD - Agent 1 event=0x91,umask=0x10  01    Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests unc_m3upi_txr_vert_inserts.ak_ag0 uncore interconnect CMS Vert Egress Allocations; AK - Agent 0 event=0x91,umask=2  01    Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_inserts.ak_ag1 uncore interconnect CMS Vert Egress Allocations; AK - Agent 1 event=0x91,umask=0x20  01    Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_m3upi_txr_vert_inserts.bl_ag0 uncore interconnect CMS Vert Egress Allocations; BL - Agent 0 event=0x91,umask=4  01    Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations unc_m3upi_txr_vert_inserts.bl_ag1 uncore interconnect CMS Vert Egress Allocations; BL - Agent 1 event=0x91,umask=0x40  01    Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache unc_m3upi_txr_vert_inserts.iv uncore interconnect CMS Vert Egress Allocations; IV event=0x91,umask=8  01    Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores unc_m3upi_txr_vert_nack.ad_ag0 uncore interconnect CMS Vertical Egress NACKs; AD - Agent 0 event=0x98,umask=1  01    Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack.ad_ag1 uncore interconnect CMS Vertical Egress NACKs; AD - Agent 1 event=0x98,umask=0x10  01    Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack.ak_ag0 uncore interconnect CMS Vertical Egress NACKs; AK - Agent 0 event=0x98,umask=2  01    Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack.ak_ag1 uncore interconnect CMS Vertical Egress NACKs; AK - Agent 1 event=0x98,umask=0x20  01    Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack.bl_ag0 uncore interconnect CMS Vertical Egress NACKs; BL - Agent 0 event=0x98,umask=4  01    Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack.bl_ag1 uncore interconnect CMS Vertical Egress NACKs; BL - Agent 1 event=0x98,umask=0x40  01    Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack.iv uncore interconnect CMS Vertical Egress NACKs; IV event=0x98,umask=8  01    Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_occupancy.ad_ag0 uncore interconnect CMS Vert Egress Occupancy; AD - Agent 0 event=0x90,umask=1  01    Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_occupancy.ad_ag1 uncore interconnect CMS Vert Egress Occupancy; AD - Agent 1 event=0x90,umask=0x10  01    Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests unc_m3upi_txr_vert_occupancy.ak_ag0 uncore interconnect CMS Vert Egress Occupancy; AK - Agent 0 event=0x90,umask=2  01    Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_occupancy.ak_ag1 uncore interconnect CMS Vert Egress Occupancy; AK - Agent 1 event=0x90,umask=0x20  01    Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring unc_m3upi_txr_vert_occupancy.bl_ag0 uncore interconnect CMS Vert Egress Occupancy; BL - Agent 0 event=0x90,umask=4  01    Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations unc_m3upi_txr_vert_occupancy.bl_ag1 uncore interconnect CMS Vert Egress Occupancy; BL - Agent 1 event=0x90,umask=0x40  01    Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache unc_m3upi_txr_vert_occupancy.iv uncore interconnect CMS Vert Egress Occupancy; IV event=0x90,umask=8  01    Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores unc_m3upi_txr_vert_starved.ad_ag0 uncore interconnect CMS Vertical Egress Injection Starvation; AD - Agent 0 event=0x9a,umask=1  01    Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved.ad_ag1 uncore interconnect CMS Vertical Egress Injection Starvation; AD - Agent 1 event=0x9a,umask=0x10  01    Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved.ak_ag0 uncore interconnect CMS Vertical Egress Injection Starvation; AK - Agent 0 event=0x9a,umask=2  01    Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved.ak_ag1 uncore interconnect CMS Vertical Egress Injection Starvation; AK - Agent 1 event=0x9a,umask=0x20  01    Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved.bl_ag0 uncore interconnect CMS Vertical Egress Injection Starvation; BL - Agent 0 event=0x9a,umask=4  01    Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved.bl_ag1 uncore interconnect CMS Vertical Egress Injection Starvation; BL - Agent 1 event=0x9a,umask=0x40  01    Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved.iv uncore interconnect CMS Vertical Egress Injection Starvation; IV event=0x9a,umask=8  01    Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_upi_peer_ad_credits_empty.vn0_req uncore interconnect UPI0 AD Credits Empty; VN0 REQ Messages event=0x20,umask=2  01    No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vn0_rsp uncore interconnect UPI0 AD Credits Empty; VN0 RSP Messages event=0x20,umask=8  01    No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vn0_snp uncore interconnect UPI0 AD Credits Empty; VN0 SNP Messages event=0x20,umask=4  01    No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vn1_req uncore interconnect UPI0 AD Credits Empty; VN1 REQ Messages event=0x20,umask=0x10  01    No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vn1_rsp uncore interconnect UPI0 AD Credits Empty; VN1 RSP Messages event=0x20,umask=0x40  01    No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vn1_snp uncore interconnect UPI0 AD Credits Empty; VN1 SNP Messages event=0x20,umask=0x20  01    No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vna uncore interconnect UPI0 AD Credits Empty; VNA event=0x20,umask=1  01    No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_bl_credits_empty.vn0_ncs_ncb uncore interconnect UPI0 BL Credits Empty; VN0 RSP Messages event=0x21,umask=4  01    No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vn0_rsp uncore interconnect UPI0 BL Credits Empty; VN0 REQ Messages event=0x21,umask=2  01    No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vn0_wb uncore interconnect UPI0 BL Credits Empty; VN0 SNP Messages event=0x21,umask=8  01    No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vn1_ncs_ncb uncore interconnect UPI0 BL Credits Empty; VN1 RSP Messages event=0x21,umask=0x20  01    No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vn1_rsp uncore interconnect UPI0 BL Credits Empty; VN1 REQ Messages event=0x21,umask=0x10  01    No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vn1_wb uncore interconnect UPI0 BL Credits Empty; VN1 SNP Messages event=0x21,umask=0x40  01    No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vna uncore interconnect UPI0 BL Credits Empty; VNA event=0x21,umask=1  01    No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_prefetch_spawn uncore interconnect Prefetches generated by the flow control queue of the M3UPI unit event=0x29  01    Count cases where flow control queue that sits between the Intel(R) Ultra Path Interconnect (UPI) and the mesh spawns a prefetch to the iMC (Memory Controller) unc_m3upi_vert_ring_ad_in_use.dn_even uncore interconnect Vertical AD Ring In Use; Down and Even event=0xa6,umask=4  01    Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ad_in_use.dn_odd uncore interconnect Vertical AD Ring In Use; Down and Odd event=0xa6,umask=8  01    Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ad_in_use.up_even uncore interconnect Vertical AD Ring In Use; Up and Even event=0xa6,umask=1  01    Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ad_in_use.up_odd uncore interconnect Vertical AD Ring In Use; Up and Odd event=0xa6,umask=2  01    Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ak_in_use.dn_even uncore interconnect Vertical AK Ring In Use; Down and Even event=0xa8,umask=4  01    Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ak_in_use.dn_odd uncore interconnect Vertical AK Ring In Use; Down and Odd event=0xa8,umask=8  01    Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ak_in_use.up_even uncore interconnect Vertical AK Ring In Use; Up and Even event=0xa8,umask=1  01    Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ak_in_use.up_odd uncore interconnect Vertical AK Ring In Use; Up and Odd event=0xa8,umask=2  01    Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_bl_in_use.dn_even uncore interconnect Vertical BL Ring in Use; Down and Even event=0xaa,umask=4  01    Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_bl_in_use.dn_odd uncore interconnect Vertical BL Ring in Use; Down and Odd event=0xaa,umask=8  01    Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_bl_in_use.up_even uncore interconnect Vertical BL Ring in Use; Up and Even event=0xaa,umask=1  01    Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_bl_in_use.up_odd uncore interconnect Vertical BL Ring in Use; Up and Odd event=0xaa,umask=2  01    Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_iv_in_use.dn uncore interconnect Vertical IV Ring in Use; Down event=0xac,umask=4  01    Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m3upi_vert_ring_iv_in_use.up uncore interconnect Vertical IV Ring in Use; Up event=0xac,umask=1  01    Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m3upi_vn0_credits_used.ncb uncore interconnect VN0 Credit Used; WB on BL event=0x5c,umask=0x10  01    Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_vn0_credits_used.ncs uncore interconnect VN0 Credit Used; NCB on BL event=0x5c,umask=0x20  01    Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_vn0_credits_used.req uncore interconnect VN0 Credit Used; REQ on AD event=0x5c,umask=1  01    Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_vn0_credits_used.rsp uncore interconnect VN0 Credit Used; RSP on AD event=0x5c,umask=4  01    Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn0_credits_used.snp uncore interconnect VN0 Credit Used; SNP on AD event=0x5c,umask=2  01    Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_vn0_credits_used.wb uncore interconnect VN0 Credit Used; RSP on BL event=0x5c,umask=8  01    Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn0_no_credits.ncb uncore interconnect VN0 No Credits; WB on BL event=0x5e,umask=0x10  01    Number of Cycles there were no VN0 Credits; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_vn0_no_credits.ncs uncore interconnect VN0 No Credits; NCB on BL event=0x5e,umask=0x20  01    Number of Cycles there were no VN0 Credits; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_vn0_no_credits.req uncore interconnect VN0 No Credits; REQ on AD event=0x5e,umask=1  01    Number of Cycles there were no VN0 Credits; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_vn0_no_credits.rsp uncore interconnect VN0 No Credits; RSP on AD event=0x5e,umask=4  01    Number of Cycles there were no VN0 Credits; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn0_no_credits.snp uncore interconnect VN0 No Credits; SNP on AD event=0x5e,umask=2  01    Number of Cycles there were no VN0 Credits; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_vn0_no_credits.wb uncore interconnect VN0 No Credits; RSP on BL event=0x5e,umask=8  01    Number of Cycles there were no VN0 Credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn1_credits_used.ncb uncore interconnect VN1 Credit Used; WB on BL event=0x5d,umask=0x10  01    Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_vn1_credits_used.ncs uncore interconnect VN1 Credit Used; NCB on BL event=0x5d,umask=0x20  01    Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_vn1_credits_used.req uncore interconnect VN1 Credit Used; REQ on AD event=0x5d,umask=1  01    Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_vn1_credits_used.rsp uncore interconnect VN1 Credit Used; RSP on AD event=0x5d,umask=4  01    Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn1_credits_used.snp uncore interconnect VN1 Credit Used; SNP on AD event=0x5d,umask=2  01    Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_vn1_credits_used.wb uncore interconnect VN1 Credit Used; RSP on BL event=0x5d,umask=8  01    Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn1_no_credits.ncb uncore interconnect VN1 No Credits; WB on BL event=0x5f,umask=0x10  01    Number of Cycles there were no VN1 Credits; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_vn1_no_credits.ncs uncore interconnect VN1 No Credits; NCB on BL event=0x5f,umask=0x20  01    Number of Cycles there were no VN1 Credits; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_vn1_no_credits.req uncore interconnect VN1 No Credits; REQ on AD event=0x5f,umask=1  01    Number of Cycles there were no VN1 Credits; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_vn1_no_credits.rsp uncore interconnect VN1 No Credits; RSP on AD event=0x5f,umask=4  01    Number of Cycles there were no VN1 Credits; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn1_no_credits.snp uncore interconnect VN1 No Credits; SNP on AD event=0x5f,umask=2  01    Number of Cycles there were no VN1 Credits; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_vn1_no_credits.wb uncore interconnect VN1 No Credits; RSP on BL event=0x5f,umask=8  01    Number of Cycles there were no VN1 Credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_nounit_txc_bl.drs_upi uncore interconnect This event is deprecated. Refer to new event UNC_M2M_TxC_BL.DRS_UPI event=0x40,umask=4  11     uncore_upi unc_upi_clockticks uncore interconnect Clocks of the Intel(R) Ultra Path Interconnect (UPI) event=1  01    Counts clockticks of the fixed frequency clock controlling the Intel(R) Ultra Path Interconnect (UPI).  This clock runs at1/8th the 'GT/s' speed of the UPI link.  For example, a  9.6GT/s  link will have a fixed Frequency of 1.2 Ghz unc_upi_direct_attempts.d2c uncore interconnect Data Response packets that go direct to core event=0x12,umask=1  01    Counts Data Response (DRS) packets that attempted to go direct to core bypassing the CHA unc_upi_direct_attempts.d2k uncore interconnect This event is deprecated. Refer to new event UNC_UPI_DIRECT_ATTEMPTS.D2U event=0x12,umask=2  11     unc_upi_direct_attempts.d2u uncore interconnect Data Response packets that go direct to Intel(R) UPI event=0x12,umask=2  01    Counts Data Response (DRS) packets that attempted to go direct to Intel(R) Ultra Path Interconnect (UPI) bypassing the CHA  unc_upi_flowq_no_vna_crd.ad_vna_eq0 uncore interconnect UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0 event=0x18,umask=1  01     unc_upi_flowq_no_vna_crd.ad_vna_eq1 uncore interconnect UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1 event=0x18,umask=2  01     unc_upi_flowq_no_vna_crd.ad_vna_eq2 uncore interconnect UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2 event=0x18,umask=4  01     unc_upi_flowq_no_vna_crd.ak_vna_eq0 uncore interconnect UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0 event=0x18,umask=0x10  01     unc_upi_flowq_no_vna_crd.ak_vna_eq1 uncore interconnect UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1 event=0x18,umask=0x20  01     unc_upi_flowq_no_vna_crd.ak_vna_eq2 uncore interconnect UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2 event=0x18,umask=0x40  01     unc_upi_flowq_no_vna_crd.ak_vna_eq3 uncore interconnect UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3 event=0x18,umask=0x80  01     unc_upi_flowq_no_vna_crd.bl_vna_eq0 uncore interconnect UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0 event=0x18,umask=8  01     unc_upi_l1_power_cycles uncore interconnect Cycles Intel(R) UPI is in L1 power mode (shutdown) event=0x21  01    Counts cycles when the Intel(R) Ultra Path Interconnect (UPI) is in L1 power mode.  L1 is a mode that totally shuts down the UPI link.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another, this event only coutns when both links are shutdown unc_upi_m3_byp_blocked.bgf_crd uncore interconnect UNC_UPI_M3_BYP_BLOCKED.BGF_CRD event=0x14,umask=8  01     unc_upi_m3_byp_blocked.flowq_ad_vna_le2 uncore interconnect UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2 event=0x14,umask=1  01     unc_upi_m3_byp_blocked.flowq_ak_vna_le3 uncore interconnect UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3 event=0x14,umask=4  01     unc_upi_m3_byp_blocked.flowq_bl_vna_eq0 uncore interconnect UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0 event=0x14,umask=2  01     unc_upi_m3_byp_blocked.gv_block uncore interconnect UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK event=0x14,umask=0x10  01     unc_upi_m3_crd_return_blocked uncore interconnect UNC_UPI_M3_CRD_RETURN_BLOCKED event=0x16  01     unc_upi_m3_rxq_blocked.bgf_crd uncore interconnect UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD event=0x15,umask=0x20  01     unc_upi_m3_rxq_blocked.flowq_ad_vna_btw_2_thresh uncore interconnect UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH event=0x15,umask=2  01     unc_upi_m3_rxq_blocked.flowq_ad_vna_le2 uncore interconnect UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2 event=0x15,umask=1  01     unc_upi_m3_rxq_blocked.flowq_ak_vna_le3 uncore interconnect UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3 event=0x15,umask=0x10  01     unc_upi_m3_rxq_blocked.flowq_bl_vna_btw_0_thresh uncore interconnect UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH event=0x15,umask=8  01     unc_upi_m3_rxq_blocked.flowq_bl_vna_eq0 uncore interconnect UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0 event=0x15,umask=4  01     unc_upi_m3_rxq_blocked.gv_block uncore interconnect UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK event=0x15,umask=0x40  01     unc_upi_phy_init_cycles uncore interconnect Cycles where phy is not in L0, L0c, L0p, L1 event=0x20  01     unc_upi_power_l1_nack uncore interconnect L1 Req Nack event=0x23  01    Counts the number of times a link sends/receives a LinkReqNAck.  When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states.  This requests can either be accepted or denied.  If the Rx side replies with an Ack, the power mode will change.  If it replies with NAck, no change will take place.  This can be filtered based on Rx and Tx.  An Rx LinkReqNAck refers to receiving an NAck (meaning this agent's Tx originally requested the power change).  A Tx LinkReqNAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it) unc_upi_power_l1_req uncore interconnect L1 Req (same as L1 Ack) event=0x22  01    Counts the number of times a link sends/receives a LinkReqAck.  When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states.  This requests can either be accepted or denied.  If the Rx side replies with an Ack, the power mode will change.  If it replies with NAck, no change will take place.  This can be filtered based on Rx and Tx.  An Rx LinkReqAck refers to receiving an Ack (meaning this agent's Tx originally requested the power change).  A Tx LinkReqAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it) unc_upi_req_slot2_from_m3.ack uncore interconnect UNC_UPI_REQ_SLOT2_FROM_M3.ACK event=0x46,umask=8  01     unc_upi_req_slot2_from_m3.vn0 uncore interconnect UNC_UPI_REQ_SLOT2_FROM_M3.VN0 event=0x46,umask=2  01     unc_upi_req_slot2_from_m3.vn1 uncore interconnect UNC_UPI_REQ_SLOT2_FROM_M3.VN1 event=0x46,umask=4  01     unc_upi_req_slot2_from_m3.vna uncore interconnect UNC_UPI_REQ_SLOT2_FROM_M3.VNA event=0x46,umask=1  01     unc_upi_rxl0p_power_cycles uncore interconnect Cycles the Rx of the Intel(R) UPI is in L0p power mode event=0x25  01    Counts cycles when the receive side (Rx) of the Intel(R) Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power unc_upi_rxl0_power_cycles uncore interconnect Cycles in L0. Receive side event=0x24  01    Number of UPI qfclk cycles spent in L0 power mode in the Link Layer.  L0 is the default mode which provides the highest performance with the most power.  Use edge detect to count the number of instances that the link entered L0.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.  The phy layer  sometimes leaves L0 for training, which will not be captured by this event unc_upi_rxl_basic_hdr_match.ncb uncore interconnect Matches on Receive path of a UPI Port; Non-Coherent Bypass event=5,umask=0xe  01    Match Message Class - NCB unc_upi_rxl_basic_hdr_match.ncb_opc uncore interconnect Matches on Receive path of a UPI Port; Non-Coherent Bypass event=5,umask=0x10e  01    Match Message Class - NCB unc_upi_rxl_basic_hdr_match.ncs uncore interconnect Matches on Receive path of a UPI Port; Non-Coherent Standard event=5,umask=0xf  01    Match Message Class - NCS unc_upi_rxl_basic_hdr_match.ncs_opc uncore interconnect Matches on Receive path of a UPI Port; Non-Coherent Standard event=5,umask=0x10f  01    Match Message Class - NCS unc_upi_rxl_basic_hdr_match.req uncore interconnect Matches on Receive path of a UPI Port; Request event=5,umask=8  01    REQ Message Class unc_upi_rxl_basic_hdr_match.req_opc uncore interconnect Matches on Receive path of a UPI Port; Request Opcode event=5,umask=0x108  01    Match REQ Opcodes - Specified in Umask[7:4] unc_upi_rxl_basic_hdr_match.rspcnflt uncore interconnect Matches on Receive path of a UPI Port; Response - Conflict event=5,umask=0x1aa  01     unc_upi_rxl_basic_hdr_match.rspi uncore interconnect Matches on Receive path of a UPI Port; Response - Invalid event=5,umask=0x12a  01     unc_upi_rxl_basic_hdr_match.rsp_data uncore interconnect Matches on Receive path of a UPI Port; Response - Data event=5,umask=0xc  01    Match Message Class -WB unc_upi_rxl_basic_hdr_match.rsp_data_opc uncore interconnect Matches on Receive path of a UPI Port; Response - Data event=5,umask=0x10c  01    Match Message Class -WB unc_upi_rxl_basic_hdr_match.rsp_nodata uncore interconnect Matches on Receive path of a UPI Port; Response - No Data event=5,umask=0xa  01    Match Message Class - RSP unc_upi_rxl_basic_hdr_match.rsp_nodata_opc uncore interconnect Matches on Receive path of a UPI Port; Response - No Data event=5,umask=0x10a  01    Match Message Class - RSP unc_upi_rxl_basic_hdr_match.snp uncore interconnect Matches on Receive path of a UPI Port; Snoop event=5,umask=9  01    SNP Message Class unc_upi_rxl_basic_hdr_match.snp_opc uncore interconnect Matches on Receive path of a UPI Port; Snoop Opcode event=5,umask=0x109  01    Match SNP Opcodes - Specified in Umask[7:4] unc_upi_rxl_basic_hdr_match.wb uncore interconnect Matches on Receive path of a UPI Port; Writeback event=5,umask=0xd  01    Match Message Class -WB unc_upi_rxl_basic_hdr_match.wb_opc uncore interconnect Matches on Receive path of a UPI Port; Writeback event=5,umask=0x10d  01    Match Message Class -WB unc_upi_rxl_bypassed.slot0 uncore interconnect FLITs received which bypassed the Slot0 Receive Buffer event=0x31,umask=1  01    Counts incoming FLITs (FLow control unITs) which bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency unc_upi_rxl_bypassed.slot1 uncore interconnect FLITs received which bypassed the Slot0 Receive Buffer event=0x31,umask=2  01    Counts incoming FLITs (FLow control unITs) which bypassed the slot1 RxQ buffer  (Receive Queue) and passed directly across the BGF and into the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency unc_upi_rxl_bypassed.slot2 uncore interconnect FLITs received which bypassed the Slot0 Receive Buffer event=0x31,umask=4  01    Counts incoming FLITs (FLow control unITs) which bypassed the slot2 RxQ buffer (Receive Queue)  and passed directly to the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency unc_upi_rxl_credits_consumed_vn0 uncore interconnect VN0 Credit Consumed event=0x39  01    Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed unc_upi_rxl_credits_consumed_vn1 uncore interconnect VN1 Credit Consumed event=0x3a  01    Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed unc_upi_rxl_credits_consumed_vna uncore interconnect VNA Credit Consumed event=0x38  01    Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed unc_upi_rxl_flits.all_data uncore interconnect Valid data FLITs received from any slot event=3,umask=0xf  01    Counts valid data FLITs  (80 bit FLow control unITs: 64bits of data) received from any of the 3 Intel(R) Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit unc_upi_rxl_flits.all_null uncore interconnect Null FLITs received from any slot event=3,umask=0x27  01    Counts null FLITs (80 bit FLow control unITs) received from any of the 3 Intel(R) Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit unc_upi_rxl_flits.data uncore interconnect Valid Flits Received; Data event=3,umask=8  01    Shows legal flit time (hides impact of L0p and L0c).; Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting. unc_upi_rxl_flits.idle uncore interconnect Valid Flits Received; Idle event=3,umask=0x47  01    Shows legal flit time (hides impact of L0p and L0c) unc_upi_rxl_flits.llcrd uncore interconnect Valid Flits Received; LLCRD Not Empty event=3,umask=0x10  01    Shows legal flit time (hides impact of L0p and L0c).; Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2 unc_upi_rxl_flits.llctrl uncore interconnect Valid Flits Received; LLCTRL event=3,umask=0x40  01    Shows legal flit time (hides impact of L0p and L0c).; Equivalent to an idle packet.  Enables counting of slot 0 LLCTRL messages unc_upi_rxl_flits.non_data uncore interconnect Protocol header and credit FLITs received from any slot event=3,umask=0x97  01    Counts protocol header and credit FLITs  (80 bit FLow control unITs) received from any of the 3 UPI slots on this UPI unit unc_upi_rxl_flits.null uncore interconnect This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.ALL_NULL event=3,umask=0x20  11     unc_upi_rxl_flits.prothdr uncore interconnect Valid Flits Received; Protocol Header event=3,umask=0x80  01    Shows legal flit time (hides impact of L0p and L0c).; Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits) unc_upi_rxl_flits.prot_hdr uncore interconnect This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.PROTHDR event=3,umask=0x80  11     unc_upi_rxl_flits.slot0 uncore interconnect Valid Flits Received; Slot 0 event=3,umask=1  01    Shows legal flit time (hides impact of L0p and L0c).; Count Slot 0 - Other mask bits determine types of headers to count unc_upi_rxl_flits.slot1 uncore interconnect Valid Flits Received; Slot 1 event=3,umask=2  01    Shows legal flit time (hides impact of L0p and L0c).; Count Slot 1 - Other mask bits determine types of headers to count unc_upi_rxl_flits.slot2 uncore interconnect Valid Flits Received; Slot 2 event=3,umask=4  01    Shows legal flit time (hides impact of L0p and L0c).; Count Slot 2 - Other mask bits determine types of headers to count unc_upi_rxl_hdr_match.ncb uncore interconnect This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCB event=5,umask=0xc  11     unc_upi_rxl_hdr_match.ncs uncore interconnect This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCS event=5,umask=0xd  11     unc_upi_rxl_hdr_match.req uncore interconnect This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.REQ event=5,umask=8  11     unc_upi_rxl_hdr_match.rsp uncore interconnect This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA event=5,umask=0xa  11     unc_upi_rxl_hdr_match.snp uncore interconnect This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.SNP event=5,umask=9  11     unc_upi_rxl_hdr_match.wb uncore interconnect This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.WB event=5,umask=0xb  11     unc_upi_rxl_inserts.slot0 uncore interconnect RxQ Flit Buffer Allocations; Slot 0 event=0x30,umask=1  01    Number of allocations into the UPI Rx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime unc_upi_rxl_inserts.slot1 uncore interconnect RxQ Flit Buffer Allocations; Slot 1 event=0x30,umask=2  01    Number of allocations into the UPI Rx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime unc_upi_rxl_inserts.slot2 uncore interconnect RxQ Flit Buffer Allocations; Slot 2 event=0x30,umask=4  01    Number of allocations into the UPI Rx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime unc_upi_rxl_occupancy.slot0 uncore interconnect RxQ Occupancy - All Packets; Slot 0 event=0x32,umask=1  01    Accumulates the number of elements in the UPI RxQ in each cycle.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime unc_upi_rxl_occupancy.slot1 uncore interconnect RxQ Occupancy - All Packets; Slot 1 event=0x32,umask=2  01    Accumulates the number of elements in the UPI RxQ in each cycle.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime unc_upi_rxl_occupancy.slot2 uncore interconnect RxQ Occupancy - All Packets; Slot 2 event=0x32,umask=4  01    Accumulates the number of elements in the UPI RxQ in each cycle.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime unc_upi_rxl_slot_bypass.s0_rxq1 uncore interconnect UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1 event=0x33,umask=1  01     unc_upi_rxl_slot_bypass.s0_rxq2 uncore interconnect UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2 event=0x33,umask=2  01     unc_upi_rxl_slot_bypass.s1_rxq0 uncore interconnect UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0 event=0x33,umask=4  01     unc_upi_rxl_slot_bypass.s1_rxq2 uncore interconnect UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2 event=0x33,umask=8  01     unc_upi_rxl_slot_bypass.s2_rxq0 uncore interconnect UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0 event=0x33,umask=0x10  01     unc_upi_rxl_slot_bypass.s2_rxq1 uncore interconnect UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1 event=0x33,umask=0x20  01     unc_upi_txl0p_clk_active.cfg_ctl uncore interconnect UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL event=0x2a,umask=1  01     unc_upi_txl0p_clk_active.dfx uncore interconnect UNC_UPI_TxL0P_CLK_ACTIVE.DFX event=0x2a,umask=0x40  01     unc_upi_txl0p_clk_active.retry uncore interconnect UNC_UPI_TxL0P_CLK_ACTIVE.RETRY event=0x2a,umask=0x20  01     unc_upi_txl0p_clk_active.rxq uncore interconnect UNC_UPI_TxL0P_CLK_ACTIVE.RXQ event=0x2a,umask=2  01     unc_upi_txl0p_clk_active.rxq_bypass uncore interconnect UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS event=0x2a,umask=4  01     unc_upi_txl0p_clk_active.rxq_cred uncore interconnect UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED event=0x2a,umask=8  01     unc_upi_txl0p_clk_active.spare uncore interconnect UNC_UPI_TxL0P_CLK_ACTIVE.SPARE event=0x2a,umask=0x80  01     unc_upi_txl0p_clk_active.txq uncore interconnect UNC_UPI_TxL0P_CLK_ACTIVE.TXQ event=0x2a,umask=0x10  01     unc_upi_txl0p_power_cycles uncore interconnect Cycles in which the Tx of the Intel(R) Ultra Path Interconnect (UPI) is in L0p power mode event=0x27  01    Counts cycles when the transmit side (Tx) of the Intel(R) Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power unc_upi_txl0p_power_cycles_ll_enter uncore interconnect UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER event=0x28  01     unc_upi_txl0p_power_cycles_m3_exit uncore interconnect UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT event=0x29  01     unc_upi_txl0_power_cycles uncore interconnect Cycles in L0. Transmit side event=0x26  01    Number of UPI qfclk cycles spent in L0 power mode in the Link Layer.  L0 is the default mode which provides the highest performance with the most power.  Use edge detect to count the number of instances that the link entered L0.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.  The phy layer  sometimes leaves L0 for training, which will not be captured by this event unc_upi_txl_basic_hdr_match.ncb uncore interconnect Matches on Transmit path of a UPI Port; Non-Coherent Bypass event=4,umask=0xe  01    Match Message Class - NCB unc_upi_txl_basic_hdr_match.ncb_opc uncore interconnect Matches on Transmit path of a UPI Port; Non-Coherent Bypass event=4,umask=0x10e  01    Match Message Class - NCB unc_upi_txl_basic_hdr_match.ncs uncore interconnect Matches on Transmit path of a UPI Port; Non-Coherent Standard event=4,umask=0xf  01    Match Message Class - NCS unc_upi_txl_basic_hdr_match.ncs_opc uncore interconnect Matches on Transmit path of a UPI Port; Non-Coherent Standard event=4,umask=0x10f  01    Match Message Class - NCS unc_upi_txl_basic_hdr_match.req uncore interconnect Matches on Transmit path of a UPI Port; Request event=4,umask=8  01    REQ Message Class unc_upi_txl_basic_hdr_match.req_opc uncore interconnect Matches on Transmit path of a UPI Port; Request Opcode event=4,umask=0x108  01    Match REQ Opcodes - Specified in Umask[7:4] unc_upi_txl_basic_hdr_match.rspcnflt uncore interconnect Matches on Transmit path of a UPI Port; Response - Conflict event=4,umask=0x1aa  01     unc_upi_txl_basic_hdr_match.rspi uncore interconnect Matches on Transmit path of a UPI Port; Response - Invalid event=4,umask=0x12a  01     unc_upi_txl_basic_hdr_match.rsp_data uncore interconnect Matches on Transmit path of a UPI Port; Response - Data event=4,umask=0xc  01    Match Message Class -WB unc_upi_txl_basic_hdr_match.rsp_data_opc uncore interconnect Matches on Transmit path of a UPI Port; Response - Data event=4,umask=0x10c  01    Match Message Class -WB unc_upi_txl_basic_hdr_match.rsp_nodata uncore interconnect Matches on Transmit path of a UPI Port; Response - No Data event=4,umask=0xa  01    Match Message Class - RSP unc_upi_txl_basic_hdr_match.rsp_nodata_opc uncore interconnect Matches on Transmit path of a UPI Port; Response - No Data event=4,umask=0x10a  01    Match Message Class - RSP unc_upi_txl_basic_hdr_match.snp uncore interconnect Matches on Transmit path of a UPI Port; Snoop event=4,umask=9  01    SNP Message Class unc_upi_txl_basic_hdr_match.snp_opc uncore interconnect Matches on Transmit path of a UPI Port; Snoop Opcode event=4,umask=0x109  01    Match SNP Opcodes - Specified in Umask[7:4] unc_upi_txl_basic_hdr_match.wb uncore interconnect Matches on Transmit path of a UPI Port; Writeback event=4,umask=0xd  01    Match Message Class -WB unc_upi_txl_basic_hdr_match.wb_opc uncore interconnect Matches on Transmit path of a UPI Port; Writeback event=4,umask=0x10d  01    Match Message Class -WB unc_upi_txl_bypassed uncore interconnect FLITs that bypassed the TxL Buffer event=0x41  01    Counts incoming FLITs (FLow control unITs) which bypassed the TxL(transmit) FLIT buffer and pass directly out the UPI Link. Generally, when data is transmitted across the Intel(R) Ultra Path Interconnect (UPI), it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used in L0p (Low Power) mode and (Link Layer Retry) LLR  mode, increasing latency to transfer out to the link unc_upi_txl_flits.all_data uncore interconnect Valid data FLITs transmitted via any slot event=2,umask=0xf  01    Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) transmitted (TxL) via any of the 3 Intel(R) Ultra Path Interconnect (UPI) slots on this UPI unit unc_upi_txl_flits.all_null uncore interconnect Null FLITs transmitted from any slot event=2,umask=0x27  01    Counts null FLITs (80 bit FLow control unITs) transmitted via any of the 3 Intel(R) Ulra Path Interconnect (UPI) slots on this UPI unit unc_upi_txl_flits.data uncore interconnect Valid Flits Sent; Data event=2,umask=8  01    Shows legal flit time (hides impact of L0p and L0c).; Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting. unc_upi_txl_flits.idle uncore interconnect Idle FLITs transmitted event=2,umask=0x47  01    Counts when the Intel Ultra Path Interconnect(UPI) transmits an idle FLIT(80 bit FLow control unITs).  Every UPI cycle must be sending either data FLITs, protocol/credit FLITs or idle FLITs unc_upi_txl_flits.llcrd uncore interconnect Valid Flits Sent; LLCRD Not Empty event=2,umask=0x10  01    Shows legal flit time (hides impact of L0p and L0c).; Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2 unc_upi_txl_flits.llctrl uncore interconnect Valid Flits Sent; LLCTRL event=2,umask=0x40  01    Shows legal flit time (hides impact of L0p and L0c).; Equivalent to an idle packet.  Enables counting of slot 0 LLCTRL messages unc_upi_txl_flits.non_data uncore interconnect Protocol header and credit FLITs transmitted across any slot event=2,umask=0x97  01    Counts protocol header and credit FLITs (80 bit FLow control unITs) transmitted across any of the 3 UPI (Ultra Path Interconnect) slots on this UPI unit unc_upi_txl_flits.null uncore interconnect This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.ALL_NULL event=2,umask=0x20  11     unc_upi_txl_flits.prothdr uncore interconnect Valid Flits Sent; Protocol Header event=2,umask=0x80  01    Shows legal flit time (hides impact of L0p and L0c).; Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits) unc_upi_txl_flits.prot_hdr uncore interconnect This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.PROTHDR event=2,umask=0x80  11     unc_upi_txl_flits.slot0 uncore interconnect Valid Flits Sent; Slot 0 event=2,umask=1  01    Shows legal flit time (hides impact of L0p and L0c).; Count Slot 0 - Other mask bits determine types of headers to count unc_upi_txl_flits.slot1 uncore interconnect Valid Flits Sent; Slot 1 event=2,umask=2  01    Shows legal flit time (hides impact of L0p and L0c).; Count Slot 1 - Other mask bits determine types of headers to count unc_upi_txl_flits.slot2 uncore interconnect Valid Flits Sent; Slot 2 event=2,umask=4  01    Shows legal flit time (hides impact of L0p and L0c).; Count Slot 2 - Other mask bits determine types of headers to count unc_upi_txl_hdr_match.data_hdr uncore interconnect This event is deprecated event=4  11     unc_upi_txl_hdr_match.dual_slot_hdr uncore interconnect This event is deprecated event=4  11     unc_upi_txl_hdr_match.loc uncore interconnect This event is deprecated event=4  11     unc_upi_txl_hdr_match.ncb uncore interconnect This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCB event=4,umask=0xe  11     unc_upi_txl_hdr_match.ncs uncore interconnect This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCS event=4,umask=0xf  11     unc_upi_txl_hdr_match.non_data_hdr uncore interconnect This event is deprecated event=4  11     unc_upi_txl_hdr_match.rem uncore interconnect This event is deprecated event=4  11     unc_upi_txl_hdr_match.req uncore interconnect This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.REQ event=4,umask=8  11     unc_upi_txl_hdr_match.rsp_data uncore interconnect This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA event=4,umask=0xc  11     unc_upi_txl_hdr_match.rsp_nodata uncore interconnect This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA event=4,umask=0xa  11     unc_upi_txl_hdr_match.sgl_slot_hdr uncore interconnect This event is deprecated event=4  11     unc_upi_txl_hdr_match.snp uncore interconnect This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.SNP event=4,umask=9  11     unc_upi_txl_hdr_match.wb uncore interconnect This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.WB event=4,umask=0xc  11     unc_upi_txl_inserts uncore interconnect Tx Flit Buffer Allocations event=0x40  01    Number of allocations into the UPI Tx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime unc_upi_txl_occupancy uncore interconnect Tx Flit Buffer Occupancy event=0x42  01    Accumulates the number of flits in the TxQ.  Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ unc_upi_vna_credit_return_blocked_vn01 uncore interconnect UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01 event=0x45  01     unc_upi_vna_credit_return_occupancy uncore interconnect VNA Credits Pending Return - Occupancy event=0x44  01    Number of VNA credits in the Rx side that are waitng to be returned back across the link unc_u_event_msg.doorbell_rcvd uncore interconnect Message Received event=0x42,umask=8  01    Virtual Logical Wire (legacy) message were received from Uncore unc_u_event_msg.int_prio uncore interconnect Message Received event=0x42,umask=0x10  01    Virtual Logical Wire (legacy) message were received from Uncore unc_u_event_msg.ipi_rcvd uncore interconnect Message Received; IPI event=0x42,umask=4  01    Virtual Logical Wire (legacy) message were received from Uncore.; Inter Processor Interrupts unc_u_event_msg.msi_rcvd uncore interconnect Message Received; MSI event=0x42,umask=2  01    Virtual Logical Wire (legacy) message were received from Uncore.; Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only) unc_u_event_msg.vlw_rcvd uncore interconnect Message Received; VLW event=0x42,umask=1  01    Virtual Logical Wire (legacy) message were received from Uncore unc_u_lock_cycles uncore interconnect IDI Lock/SplitLock Cycles event=0x44  01    Number of times an IDI Lock/SplitLock sequence was started unc_u_phold_cycles.assert_to_ack uncore interconnect Cycles PHOLD Assert to Ack; Assert to ACK event=0x45,umask=1  01    PHOLD cycles unc_u_racu_drng.pftch_buf_empty uncore interconnect UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY event=0x4c,umask=4  01     unc_u_racu_drng.rdrand uncore interconnect UNC_U_RACU_DRNG.RDRAND event=0x4c,umask=1  01     unc_u_racu_drng.rdseed uncore interconnect UNC_U_RACU_DRNG.RDSEED event=0x4c,umask=2  01     uncore_iio llc_misses.pcie_read uncore io PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0 event=0x83,ch_mask=1,fc_mask=7,umask=4,ch_mask=0x1f  014Bytes    Counts every read request for 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus llc_misses.pcie_write uncore io PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0 event=0x83,ch_mask=1,fc_mask=7,umask=1,ch_mask=0x1f  014Bytes    Counts every write request of 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_clockticks uncore io Clockticks of the IIO Traffic Controller event=1  01    Counts clockticks of the 1GHz traffic controller clock in the IIO unit unc_iio_comp_buf_inserts.cmpd.all_parts uncore io PCIe Completion Buffer Inserts of completions with data: Part 0-3 event=0xc2,ch_mask=0xf,fc_mask=4,umask=3  01     unc_iio_comp_buf_inserts.cmpd.part0 uncore io PCIe Completion Buffer Inserts of completions with data: Part 0 event=0xc2,ch_mask=1,fc_mask=4,umask=3  01     unc_iio_comp_buf_inserts.cmpd.part1 uncore io PCIe Completion Buffer Inserts of completions with data: Part 1 event=0xc2,ch_mask=2,fc_mask=4,umask=3  01     unc_iio_comp_buf_inserts.cmpd.part2 uncore io PCIe Completion Buffer Inserts of completions with data: Part 2 event=0xc2,ch_mask=4,fc_mask=4,umask=3  01     unc_iio_comp_buf_inserts.cmpd.part3 uncore io PCIe Completion Buffer Inserts of completions with data: Part 3 event=0xc2,ch_mask=8,fc_mask=4,umask=3  01     unc_iio_comp_buf_inserts.port0 uncore io PCIe Completion Buffer Inserts; Port 0 event=0xc2,ch_mask=1,fc_mask=7,umask=4  01     unc_iio_comp_buf_inserts.port1 uncore io PCIe Completion Buffer Inserts; Port 1 event=0xc2,ch_mask=2,fc_mask=7,umask=4  01     unc_iio_comp_buf_inserts.port2 uncore io PCIe Completion Buffer Inserts; Port 2 event=0xc2,ch_mask=4,fc_mask=7,umask=4  01     unc_iio_comp_buf_inserts.port3 uncore io PCIe Completion Buffer Inserts; Port 3 event=0xc2,ch_mask=8,fc_mask=7,umask=4  01     unc_iio_comp_buf_occupancy.cmpd.all_parts uncore io PCIe Completion Buffer occupancy of completions with data: Part 0-3 event=0xd5,fc_mask=4,umask=0xf  01     unc_iio_comp_buf_occupancy.cmpd.part0 uncore io PCIe Completion Buffer occupancy of completions with data: Part 0 event=0xd5,fc_mask=4,umask=1  01     unc_iio_comp_buf_occupancy.cmpd.part1 uncore io PCIe Completion Buffer occupancy of completions with data: Part 1 event=0xd5,fc_mask=4,umask=2  01     unc_iio_comp_buf_occupancy.cmpd.part2 uncore io PCIe Completion Buffer occupancy of completions with data: Part 2 event=0xd5,fc_mask=4,umask=4  01     unc_iio_comp_buf_occupancy.cmpd.part3 uncore io PCIe Completion Buffer occupancy of completions with data: Part 3 event=0xd5,fc_mask=4,umask=8  01     unc_iio_data_req_by_cpu.cfg_read.part0 uncore io Data requested by the CPU; Core reading from Card's PCICFG space event=0xc0,ch_mask=1,fc_mask=7,umask=0x40  01    Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.cfg_read.part1 uncore io Data requested by the CPU; Core reading from Card's PCICFG space event=0xc0,ch_mask=2,fc_mask=7,umask=0x40  01    Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.cfg_read.part2 uncore io Data requested by the CPU; Core reading from Card's PCICFG space event=0xc0,ch_mask=4,fc_mask=7,umask=0x40  01    Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.cfg_read.part3 uncore io Data requested by the CPU; Core reading from Card's PCICFG space event=0xc0,ch_mask=8,fc_mask=7,umask=0x40  01    Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.cfg_read.vtd0 uncore io Data requested by the CPU; Core reading from Card's PCICFG space event=0xc0,ch_mask=0x10,fc_mask=7,umask=0x40  01    Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0 unc_iio_data_req_by_cpu.cfg_read.vtd1 uncore io Data requested by the CPU; Core reading from Card's PCICFG space event=0xc0,ch_mask=0x20,fc_mask=7,umask=0x40  01    Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1 unc_iio_data_req_by_cpu.cfg_write.part0 uncore io Data requested by the CPU; Core writing to Card's PCICFG space event=0xc0,ch_mask=1,fc_mask=7,umask=0x10  01    Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.cfg_write.part1 uncore io Data requested by the CPU; Core writing to Card's PCICFG space event=0xc0,ch_mask=2,fc_mask=7,umask=0x10  01    Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.cfg_write.part2 uncore io Data requested by the CPU; Core writing to Card's PCICFG space event=0xc0,ch_mask=4,fc_mask=7,umask=0x10  01    Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.cfg_write.part3 uncore io Data requested by the CPU; Core writing to Card's PCICFG space event=0xc0,ch_mask=8,fc_mask=7,umask=0x10  01    Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.cfg_write.vtd0 uncore io Data requested by the CPU; Core writing to Card's PCICFG space event=0xc0,ch_mask=0x10,fc_mask=7,umask=0x10  01    Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0 unc_iio_data_req_by_cpu.cfg_write.vtd1 uncore io Data requested by the CPU; Core writing to Card's PCICFG space event=0xc0,ch_mask=0x20,fc_mask=7,umask=0x10  01    Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1 unc_iio_data_req_by_cpu.io_read.part0 uncore io Data requested by the CPU; Core reading from Card's IO space event=0xc0,ch_mask=1,fc_mask=7,umask=0x80  01    Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.io_read.part1 uncore io Data requested by the CPU; Core reading from Card's IO space event=0xc0,ch_mask=2,fc_mask=7,umask=0x80  01    Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.io_read.part2 uncore io Data requested by the CPU; Core reading from Card's IO space event=0xc0,ch_mask=4,fc_mask=7,umask=0x80  01    Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.io_read.part3 uncore io Data requested by the CPU; Core reading from Card's IO space event=0xc0,ch_mask=8,fc_mask=7,umask=0x80  01    Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.io_read.vtd0 uncore io Data requested by the CPU; Core reading from Card's IO space event=0xc0,ch_mask=0x10,fc_mask=7,umask=0x80  01    Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0 unc_iio_data_req_by_cpu.io_read.vtd1 uncore io Data requested by the CPU; Core reading from Card's IO space event=0xc0,ch_mask=0x20,fc_mask=7,umask=0x80  01    Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1 unc_iio_data_req_by_cpu.io_write.part0 uncore io Data requested by the CPU; Core writing to Card's IO space event=0xc0,ch_mask=1,fc_mask=7,umask=0x20  01    Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.io_write.part1 uncore io Data requested by the CPU; Core writing to Card's IO space event=0xc0,ch_mask=2,fc_mask=7,umask=0x20  01    Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.io_write.part2 uncore io Data requested by the CPU; Core writing to Card's IO space event=0xc0,ch_mask=4,fc_mask=7,umask=0x20  01    Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.io_write.part3 uncore io Data requested by the CPU; Core writing to Card's IO space event=0xc0,ch_mask=8,fc_mask=7,umask=0x20  01    Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.io_write.vtd0 uncore io Data requested by the CPU; Core writing to Card's IO space event=0xc0,ch_mask=0x10,fc_mask=7,umask=0x20  01    Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0 unc_iio_data_req_by_cpu.io_write.vtd1 uncore io Data requested by the CPU; Core writing to Card's IO space event=0xc0,ch_mask=0x20,fc_mask=7,umask=0x20  01    Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1 unc_iio_data_req_by_cpu.mem_read.part0 uncore io Read request for 4 bytes made by the CPU to IIO Part0 event=0xc0,ch_mask=1,fc_mask=7,umask=4  01    Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.mem_read.part1 uncore io Read request for 4 bytes made by the CPU to IIO Part1 event=0xc0,ch_mask=2,fc_mask=7,umask=4  01    Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.mem_read.part2 uncore io Read request for 4 bytes made by the CPU to IIO Part2 event=0xc0,ch_mask=4,fc_mask=7,umask=4  01    Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.mem_read.part3 uncore io Read request for 4 bytes made by the CPU to IIO Part3 event=0xc0,ch_mask=8,fc_mask=7,umask=4  01    Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.mem_read.vtd0 uncore io Data requested by the CPU; Core reading from Card's MMIO space event=0xc0,ch_mask=0x10,fc_mask=7,umask=4  01    Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0 unc_iio_data_req_by_cpu.mem_read.vtd1 uncore io Data requested by the CPU; Core reading from Card's MMIO space event=0xc0,ch_mask=0x20,fc_mask=7,umask=4  01    Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1 unc_iio_data_req_by_cpu.mem_write.part0 uncore io Write request of 4 bytes made to IIO Part0 by the CPU event=0xc0,ch_mask=1,fc_mask=7,umask=1  01    Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.mem_write.part1 uncore io Write request of 4 bytes made to IIO Part1 by the CPU event=0xc0,ch_mask=2,fc_mask=7,umask=1  01    Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.mem_write.part2 uncore io Write request of 4 bytes made to IIO Part2 by the CPU event=0xc0,ch_mask=4,fc_mask=7,umask=1  01    Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by  a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.mem_write.part3 uncore io Write request of 4 bytes made to IIO Part3 by the CPU event=0xc0,ch_mask=8,fc_mask=7,umask=1  01    Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by  a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.mem_write.vtd0 uncore io Data requested by the CPU; Core writing to Card's MMIO space event=0xc0,ch_mask=0x10,fc_mask=7,umask=1  01    Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0 unc_iio_data_req_by_cpu.mem_write.vtd1 uncore io Data requested by the CPU; Core writing to Card's MMIO space event=0xc0,ch_mask=0x20,fc_mask=7,umask=1  01    Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1 unc_iio_data_req_by_cpu.peer_read.part0 uncore io Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0 event=0xc0,ch_mask=1,fc_mask=7,umask=8  01    Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_read.part1 uncore io Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part1 event=0xc0,ch_mask=2,fc_mask=7,umask=8  01    Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_read.part2 uncore io Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part2 event=0xc0,ch_mask=4,fc_mask=7,umask=8  01    Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_read.part3 uncore io Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part3 event=0xc0,ch_mask=8,fc_mask=7,umask=8  01    Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_read.vtd0 uncore io Data requested by the CPU; Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x10,fc_mask=7,umask=8  01    Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0 unc_iio_data_req_by_cpu.peer_read.vtd1 uncore io Data requested by the CPU; Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x20,fc_mask=7,umask=8  01    Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1 unc_iio_data_req_by_cpu.peer_write.part0 uncore io Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit event=0xc0,ch_mask=1,fc_mask=7,umask=2  01    Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit.  In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_write.part1 uncore io Peer to peer write request of 4 bytes made to IIO Part1 by a different IIO unit event=0xc0,ch_mask=2,fc_mask=7,umask=2  01    Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_write.part2 uncore io Peer to peer write request of 4 bytes made to IIO Part2 by a different IIO unit event=0xc0,ch_mask=4,fc_mask=7,umask=2  01    Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_write.part3 uncore io Peer to peer write request of 4 bytes made to IIO Part3 by a different IIO unit event=0xc0,ch_mask=8,fc_mask=7,umask=2  01    Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_write.vtd0 uncore io Data requested by the CPU; Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x10,fc_mask=7,umask=2  01    Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0 unc_iio_data_req_by_cpu.peer_write.vtd1 uncore io Data requested by the CPU; Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x20,fc_mask=7,umask=2  01    Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1 unc_iio_data_req_of_cpu.atomic.part0 uncore io Data requested of the CPU; Atomic requests targeting DRAM event=0x83,ch_mask=1,fc_mask=7,umask=0x10  01    Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.atomic.part1 uncore io Data requested of the CPU; Atomic requests targeting DRAM event=0x83,ch_mask=2,fc_mask=7,umask=0x10  01    Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.atomic.part2 uncore io Data requested of the CPU; Atomic requests targeting DRAM event=0x83,ch_mask=4,fc_mask=7,umask=0x10  01    Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.atomic.part3 uncore io Data requested of the CPU; Atomic requests targeting DRAM event=0x83,ch_mask=8,fc_mask=7,umask=0x10  01    Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.atomic.vtd0 uncore io Data requested of the CPU; Atomic requests targeting DRAM event=0x83,ch_mask=0x10,fc_mask=7,umask=0x10  01    Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0 unc_iio_data_req_of_cpu.atomic.vtd1 uncore io Data requested of the CPU; Atomic requests targeting DRAM event=0x83,ch_mask=0x20,fc_mask=7,umask=0x10  01    Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1 unc_iio_data_req_of_cpu.atomiccmp.part0 uncore io Data requested of the CPU; Completion of atomic requests targeting DRAM event=0x83,ch_mask=1,fc_mask=7,umask=0x20  01    Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.atomiccmp.part1 uncore io Data requested of the CPU; Completion of atomic requests targeting DRAM event=0x83,ch_mask=2,fc_mask=7,umask=0x20  01    Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.atomiccmp.part2 uncore io Data requested of the CPU; Completion of atomic requests targeting DRAM event=0x83,ch_mask=4,fc_mask=7,umask=0x20  01    Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.atomiccmp.part3 uncore io Data requested of the CPU; Completion of atomic requests targeting DRAM event=0x83,ch_mask=8,fc_mask=7,umask=0x20  01    Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.mem_read.part0 uncore io PCI Express bandwidth reading at IIO, part 0 event=0x83,ch_mask=1,fc_mask=7,umask=4  01    Counts every read request for 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.mem_read.part1 uncore io PCI Express bandwidth reading at IIO, part 1 event=0x83,ch_mask=2,fc_mask=7,umask=4  01    Counts every read request for 4 bytes of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.mem_read.part2 uncore io PCI Express bandwidth reading at IIO, part 2 event=0x83,ch_mask=4,fc_mask=7,umask=4  01    Counts every read request for 4 bytes of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.mem_read.part3 uncore io PCI Express bandwidth reading at IIO, part 3 event=0x83,ch_mask=8,fc_mask=7,umask=4  01    Counts every read request for 4 bytes of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.mem_read.vtd0 uncore io Data requested of the CPU; Card reading from DRAM event=0x83,ch_mask=0x10,fc_mask=7,umask=4  01    Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0 unc_iio_data_req_of_cpu.mem_read.vtd1 uncore io Data requested of the CPU; Card reading from DRAM event=0x83,ch_mask=0x20,fc_mask=7,umask=4  01    Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1 unc_iio_data_req_of_cpu.mem_write.part0 uncore io PCI Express bandwidth writing at IIO, part 0 event=0x83,ch_mask=1,fc_mask=7,umask=1  01    Counts every write request of 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.mem_write.part1 uncore io PCI Express bandwidth writing at IIO, part 1 event=0x83,ch_mask=2,fc_mask=7,umask=1  01    Counts every write request of 4 bytes of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.mem_write.part2 uncore io PCI Express bandwidth writing at IIO, part 2 event=0x83,ch_mask=4,fc_mask=7,umask=1  01    Counts every write request of 4 bytes of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.mem_write.part3 uncore io PCI Express bandwidth writing at IIO, part 3 event=0x83,ch_mask=8,fc_mask=7,umask=1  01    Counts every write request of 4 bytes of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.mem_write.vtd0 uncore io Data requested of the CPU; Card writing to DRAM event=0x83,ch_mask=0x10,fc_mask=7,umask=1  01    Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0 unc_iio_data_req_of_cpu.mem_write.vtd1 uncore io Data requested of the CPU; Card writing to DRAM event=0x83,ch_mask=0x20,fc_mask=7,umask=1  01    Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1 unc_iio_data_req_of_cpu.msg.part0 uncore io Data requested of the CPU; Messages event=0x83,ch_mask=1,fc_mask=7,umask=0x40  01    Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.msg.part1 uncore io Data requested of the CPU; Messages event=0x83,ch_mask=2,fc_mask=7,umask=0x40  01    Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.msg.part2 uncore io Data requested of the CPU; Messages event=0x83,ch_mask=4,fc_mask=7,umask=0x40  01    Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.msg.part3 uncore io Data requested of the CPU; Messages event=0x83,ch_mask=8,fc_mask=7,umask=0x40  01    Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.msg.vtd0 uncore io Data requested of the CPU; Messages event=0x83,ch_mask=0x10,fc_mask=7,umask=0x40  01    Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0 unc_iio_data_req_of_cpu.msg.vtd1 uncore io Data requested of the CPU; Messages event=0x83,ch_mask=0x20,fc_mask=7,umask=0x40  01    Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1 unc_iio_data_req_of_cpu.peer_read.part0 uncore io Peer to peer read request for 4 bytes made by IIO Part0 to an IIO target event=0x83,ch_mask=1,fc_mask=7,umask=8  01    Counts every peer to peer read request for 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_read.part1 uncore io Peer to peer read request for 4 bytes made by IIO Part1 to an IIO target event=0x83,ch_mask=2,fc_mask=7,umask=8  01    Counts every peer to peer read request for 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_read.part2 uncore io Peer to peer read request for 4 bytes made by IIO Part2 to an IIO target event=0x83,ch_mask=4,fc_mask=7,umask=8  01    Counts every peer to peer read request for 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_read.part3 uncore io Peer to peer read request for 4 bytes made by IIO Part3 to an IIO target event=0x83,ch_mask=8,fc_mask=7,umask=8  01    Counts every peer to peer read request for 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_read.vtd0 uncore io Data requested of the CPU; Card reading from another Card (same or different stack) event=0x83,ch_mask=0x10,fc_mask=7,umask=8  01    Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0 unc_iio_data_req_of_cpu.peer_read.vtd1 uncore io Data requested of the CPU; Card reading from another Card (same or different stack) event=0x83,ch_mask=0x20,fc_mask=7,umask=8  01    Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1 unc_iio_data_req_of_cpu.peer_write.part0 uncore io Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target event=0x83,ch_mask=1,fc_mask=7,umask=2  01    Counts every peer to peer write request of 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_write.part1 uncore io Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target event=0x83,ch_mask=2,fc_mask=7,umask=2  01    Counts every peer to peer write request of 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_write.part2 uncore io Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target event=0x83,ch_mask=4,fc_mask=7,umask=2  01    Counts every peer to peer write request of 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_write.part3 uncore io Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target event=0x83,ch_mask=8,fc_mask=7,umask=2  01    Counts every peer to peer write request of 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_write.vtd0 uncore io Data requested of the CPU; Card writing to another Card (same or different stack) event=0x83,ch_mask=0x10,fc_mask=7,umask=2  01    Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0 unc_iio_data_req_of_cpu.peer_write.vtd1 uncore io Data requested of the CPU; Card writing to another Card (same or different stack) event=0x83,ch_mask=0x20,fc_mask=7,umask=2  01    Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1 unc_iio_link_num_corr_err uncore io Num Link  Correctable Errors event=0xf  01     unc_iio_link_num_retries uncore io Num Link Retries event=0xe  01     unc_iio_mask_match uncore io Number packets that passed the Mask/Match Filter event=0x21  01     unc_iio_mask_match_and.bus0 uncore io AND Mask/match for debug bus; Non-PCIE bus event=2,umask=1  01    Asserted if all bits specified by mask match unc_iio_mask_match_and.bus0_bus1 uncore io AND Mask/match for debug bus; Non-PCIE bus and PCIE bus event=2,umask=8  01    Asserted if all bits specified by mask match unc_iio_mask_match_and.bus0_not_bus1 uncore io AND Mask/match for debug bus; Non-PCIE bus and !(PCIE bus) event=2,umask=4  01    Asserted if all bits specified by mask match unc_iio_mask_match_and.bus1 uncore io AND Mask/match for debug bus; PCIE bus event=2,umask=2  01    Asserted if all bits specified by mask match unc_iio_mask_match_and.not_bus0_bus1 uncore io AND Mask/match for debug bus; !(Non-PCIE bus) and PCIE bus event=2,umask=0x10  01    Asserted if all bits specified by mask match unc_iio_mask_match_and.not_bus0_not_bus1 uncore io AND Mask/match for debug bus event=2,umask=0x20  01    Asserted if all bits specified by mask match unc_iio_mask_match_or.bus0 uncore io OR Mask/match for debug bus; Non-PCIE bus event=3,umask=1  01    Asserted if any bits specified by mask match unc_iio_mask_match_or.bus0_bus1 uncore io OR Mask/match for debug bus; Non-PCIE bus and PCIE bus event=3,umask=8  01    Asserted if any bits specified by mask match unc_iio_mask_match_or.bus0_not_bus1 uncore io OR Mask/match for debug bus; Non-PCIE bus and !(PCIE bus) event=3,umask=4  01    Asserted if any bits specified by mask match unc_iio_mask_match_or.bus1 uncore io OR Mask/match for debug bus; PCIE bus event=3,umask=2  01    Asserted if any bits specified by mask match unc_iio_mask_match_or.not_bus0_bus1 uncore io OR Mask/match for debug bus; !(Non-PCIE bus) and PCIE bus event=3,umask=0x10  01    Asserted if any bits specified by mask match unc_iio_mask_match_or.not_bus0_not_bus1 uncore io OR Mask/match for debug bus; !(Non-PCIE bus) and !(PCIE bus) event=3,umask=0x20  01    Asserted if any bits specified by mask match unc_iio_nothing uncore io Counting disabled event=0  01     unc_iio_payload_bytes_in.atomic.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0 event=0x83,ch_mask=1,fc_mask=7,umask=0x10  11     unc_iio_payload_bytes_in.atomic.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1 event=0x83,ch_mask=2,fc_mask=7,umask=0x10  11     unc_iio_payload_bytes_in.atomic.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2 event=0x83,ch_mask=4,fc_mask=7,umask=0x10  11     unc_iio_payload_bytes_in.atomic.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3 event=0x83,ch_mask=8,fc_mask=7,umask=0x10  11     unc_iio_payload_bytes_in.atomic.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0 event=0x83,ch_mask=0x10,fc_mask=7,umask=0x10  11     unc_iio_payload_bytes_in.atomic.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1 event=0x83,ch_mask=0x20,fc_mask=7,umask=0x10  11     unc_iio_payload_bytes_in.atomiccmp.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0 event=0x83,ch_mask=1,fc_mask=7,umask=0x20  11     unc_iio_payload_bytes_in.atomiccmp.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1 event=0x83,ch_mask=2,fc_mask=7,umask=0x20  11     unc_iio_payload_bytes_in.atomiccmp.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2 event=0x83,ch_mask=4,fc_mask=7,umask=0x20  11     unc_iio_payload_bytes_in.atomiccmp.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3 event=0x83,ch_mask=8,fc_mask=7,umask=0x20  11     unc_iio_payload_bytes_in.mem_read.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 event=0x83,ch_mask=1,fc_mask=7,umask=4  11     unc_iio_payload_bytes_in.mem_read.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 event=0x83,ch_mask=2,fc_mask=7,umask=4  11     unc_iio_payload_bytes_in.mem_read.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 event=0x83,ch_mask=4,fc_mask=7,umask=4  11     unc_iio_payload_bytes_in.mem_read.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 event=0x83,ch_mask=8,fc_mask=7,umask=4  11     unc_iio_payload_bytes_in.mem_read.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0 event=0x83,ch_mask=0x10,fc_mask=7,umask=4  11     unc_iio_payload_bytes_in.mem_read.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1 event=0x83,ch_mask=0x20,fc_mask=7,umask=4  11     unc_iio_payload_bytes_in.mem_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 event=0x83,ch_mask=1,fc_mask=7,umask=1  11     unc_iio_payload_bytes_in.mem_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 event=0x83,ch_mask=2,fc_mask=7,umask=1  11     unc_iio_payload_bytes_in.mem_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 event=0x83,ch_mask=4,fc_mask=7,umask=1  11     unc_iio_payload_bytes_in.mem_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3 event=0x83,ch_mask=8,fc_mask=7,umask=1  11     unc_iio_payload_bytes_in.mem_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0 event=0x83,ch_mask=0x10,fc_mask=7,umask=1  11     unc_iio_payload_bytes_in.mem_write.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1 event=0x83,ch_mask=0x20,fc_mask=7,umask=1  11     unc_iio_payload_bytes_in.msg.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0 event=0x83,ch_mask=1,fc_mask=7,umask=0x40  11     unc_iio_payload_bytes_in.msg.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1 event=0x83,ch_mask=2,fc_mask=7,umask=0x40  11     unc_iio_payload_bytes_in.msg.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2 event=0x83,ch_mask=4,fc_mask=7,umask=0x40  11     unc_iio_payload_bytes_in.msg.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3 event=0x83,ch_mask=8,fc_mask=7,umask=0x40  11     unc_iio_payload_bytes_in.msg.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0 event=0x83,ch_mask=0x10,fc_mask=7,umask=0x40  11     unc_iio_payload_bytes_in.msg.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1 event=0x83,ch_mask=0x20,fc_mask=7,umask=0x40  11     unc_iio_payload_bytes_in.peer_read.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0 event=0x83,ch_mask=1,fc_mask=7,umask=8  11     unc_iio_payload_bytes_in.peer_read.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1 event=0x83,ch_mask=2,fc_mask=7,umask=8  11     unc_iio_payload_bytes_in.peer_read.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2 event=0x83,ch_mask=4,fc_mask=7,umask=8  11     unc_iio_payload_bytes_in.peer_read.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3 event=0x83,ch_mask=8,fc_mask=7,umask=8  11     unc_iio_payload_bytes_in.peer_read.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0 event=0x83,ch_mask=0x10,fc_mask=7,umask=8  11     unc_iio_payload_bytes_in.peer_read.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1 event=0x83,ch_mask=0x20,fc_mask=7,umask=8  11     unc_iio_payload_bytes_in.peer_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0 event=0x83,ch_mask=1,fc_mask=7,umask=2  11     unc_iio_payload_bytes_in.peer_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1 event=0x83,ch_mask=2,fc_mask=7,umask=2  11     unc_iio_payload_bytes_in.peer_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2 event=0x83,ch_mask=4,fc_mask=7,umask=2  11     unc_iio_payload_bytes_in.peer_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3 event=0x83,ch_mask=8,fc_mask=7,umask=2  11     unc_iio_payload_bytes_in.peer_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0 event=0x83,ch_mask=0x10,fc_mask=7,umask=2  11     unc_iio_payload_bytes_in.peer_write.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1 event=0x83,ch_mask=0x20,fc_mask=7,umask=2  11     unc_iio_payload_bytes_out.cfg_read.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0 event=0xc0,ch_mask=1,fc_mask=7,umask=0x40  11     unc_iio_payload_bytes_out.cfg_read.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1 event=0xc0,ch_mask=2,fc_mask=7,umask=0x40  11     unc_iio_payload_bytes_out.cfg_read.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2 event=0xc0,ch_mask=4,fc_mask=7,umask=0x40  11     unc_iio_payload_bytes_out.cfg_read.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3 event=0xc0,ch_mask=8,fc_mask=7,umask=0x40  11     unc_iio_payload_bytes_out.cfg_read.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0 event=0xc0,ch_mask=0x10,fc_mask=7,umask=0x40  11     unc_iio_payload_bytes_out.cfg_read.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1 event=0xc0,ch_mask=0x20,fc_mask=7,umask=0x40  11     unc_iio_payload_bytes_out.cfg_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0 event=0xc0,ch_mask=1,fc_mask=7,umask=0x10  11     unc_iio_payload_bytes_out.cfg_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1 event=0xc0,ch_mask=2,fc_mask=7,umask=0x10  11     unc_iio_payload_bytes_out.cfg_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2 event=0xc0,ch_mask=4,fc_mask=7,umask=0x10  11     unc_iio_payload_bytes_out.cfg_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3 event=0xc0,ch_mask=8,fc_mask=7,umask=0x10  11     unc_iio_payload_bytes_out.cfg_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0 event=0xc0,ch_mask=0x10,fc_mask=7,umask=0x10  11     unc_iio_payload_bytes_out.cfg_write.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1 event=0xc0,ch_mask=0x20,fc_mask=7,umask=0x10  11     unc_iio_payload_bytes_out.io_read.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0 event=0xc0,ch_mask=1,fc_mask=7,umask=0x80  11     unc_iio_payload_bytes_out.io_read.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1 event=0xc0,ch_mask=2,fc_mask=7,umask=0x80  11     unc_iio_payload_bytes_out.io_read.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2 event=0xc0,ch_mask=4,fc_mask=7,umask=0x80  11     unc_iio_payload_bytes_out.io_read.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3 event=0xc0,ch_mask=8,fc_mask=7,umask=0x80  11     unc_iio_payload_bytes_out.io_read.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0 event=0xc0,ch_mask=0x10,fc_mask=7,umask=0x80  11     unc_iio_payload_bytes_out.io_read.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1 event=0xc0,ch_mask=0x20,fc_mask=7,umask=0x80  11     unc_iio_payload_bytes_out.io_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0 event=0xc0,ch_mask=1,fc_mask=7,umask=0x20  11     unc_iio_payload_bytes_out.io_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1 event=0xc0,ch_mask=2,fc_mask=7,umask=0x20  11     unc_iio_payload_bytes_out.io_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2 event=0xc0,ch_mask=4,fc_mask=7,umask=0x20  11     unc_iio_payload_bytes_out.io_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3 event=0xc0,ch_mask=8,fc_mask=7,umask=0x20  11     unc_iio_payload_bytes_out.io_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0 event=0xc0,ch_mask=0x10,fc_mask=7,umask=0x20  11     unc_iio_payload_bytes_out.io_write.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1 event=0xc0,ch_mask=0x20,fc_mask=7,umask=0x20  11     unc_iio_payload_bytes_out.mem_read.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0 event=0xc0,ch_mask=1,fc_mask=7,umask=4  11     unc_iio_payload_bytes_out.mem_read.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1 event=0xc0,ch_mask=2,fc_mask=7,umask=4  11     unc_iio_payload_bytes_out.mem_read.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2 event=0xc0,ch_mask=4,fc_mask=7,umask=4  11     unc_iio_payload_bytes_out.mem_read.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3 event=0xc0,ch_mask=8,fc_mask=7,umask=4  11     unc_iio_payload_bytes_out.mem_read.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0 event=0xc0,ch_mask=0x10,fc_mask=7,umask=4  11     unc_iio_payload_bytes_out.mem_read.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1 event=0xc0,ch_mask=0x20,fc_mask=7,umask=4  11     unc_iio_payload_bytes_out.mem_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0 event=0xc0,ch_mask=1,fc_mask=7,umask=1  11     unc_iio_payload_bytes_out.mem_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1 event=0xc0,ch_mask=2,fc_mask=7,umask=1  11     unc_iio_payload_bytes_out.mem_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2 event=0xc0,ch_mask=4,fc_mask=7,umask=1  11     unc_iio_payload_bytes_out.mem_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3 event=0xc0,ch_mask=8,fc_mask=7,umask=1  11     unc_iio_payload_bytes_out.mem_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0 event=0xc0,ch_mask=0x10,fc_mask=7,umask=1  11     unc_iio_payload_bytes_out.mem_write.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1 event=0xc0,ch_mask=0x20,fc_mask=7,umask=1  11     unc_iio_payload_bytes_out.peer_read.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0 event=0xc0,ch_mask=1,fc_mask=7,umask=8  11     unc_iio_payload_bytes_out.peer_read.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1 event=0xc0,ch_mask=2,fc_mask=7,umask=8  11     unc_iio_payload_bytes_out.peer_read.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2 event=0xc0,ch_mask=4,fc_mask=7,umask=8  11     unc_iio_payload_bytes_out.peer_read.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3 event=0xc0,ch_mask=8,fc_mask=7,umask=8  11     unc_iio_payload_bytes_out.peer_read.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0 event=0xc0,ch_mask=0x10,fc_mask=7,umask=8  11     unc_iio_payload_bytes_out.peer_read.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1 event=0xc0,ch_mask=0x20,fc_mask=7,umask=8  11     unc_iio_payload_bytes_out.peer_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0 event=0xc0,ch_mask=1,fc_mask=7,umask=2  11     unc_iio_payload_bytes_out.peer_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1 event=0xc0,ch_mask=2,fc_mask=7,umask=2  11     unc_iio_payload_bytes_out.peer_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2 event=0xc0,ch_mask=4,fc_mask=7,umask=2  11     unc_iio_payload_bytes_out.peer_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3 event=0xc0,ch_mask=8,fc_mask=7,umask=2  11     unc_iio_payload_bytes_out.peer_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0 event=0xc0,ch_mask=0x10,fc_mask=7,umask=2  11     unc_iio_payload_bytes_out.peer_write.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1 event=0xc0,ch_mask=0x20,fc_mask=7,umask=2  11     unc_iio_symbol_times uncore io Symbol Times on Link event=0x82  01    Gen1 - increment once every 4nS, Gen2 - increment once every 2nS, Gen3 - increment once every 1nS unc_iio_txn_in.atomic.part0 uncore io This event is deprecated event=0x84,ch_mask=1,fc_mask=7,umask=0x10  11     unc_iio_txn_in.atomic.part1 uncore io This event is deprecated event=0x84,ch_mask=2,fc_mask=7,umask=0x10  11     unc_iio_txn_in.atomic.part2 uncore io This event is deprecated event=0x84,ch_mask=4,fc_mask=7,umask=0x10  11     unc_iio_txn_in.atomic.part3 uncore io This event is deprecated event=0x84,ch_mask=8,fc_mask=7,umask=0x10  11     unc_iio_txn_in.atomic.vtd0 uncore io This event is deprecated event=0x84,ch_mask=0x10,fc_mask=7,umask=0x10  11     unc_iio_txn_in.atomic.vtd1 uncore io This event is deprecated event=0x84,ch_mask=0x20,fc_mask=7,umask=0x10  11     unc_iio_txn_in.atomiccmp.part0 uncore io This event is deprecated event=0x84,ch_mask=1,fc_mask=7,umask=0x20  11     unc_iio_txn_in.atomiccmp.part1 uncore io This event is deprecated event=0x84,ch_mask=2,fc_mask=7,umask=0x20  11     unc_iio_txn_in.atomiccmp.part2 uncore io This event is deprecated event=0x84,ch_mask=4,fc_mask=7,umask=0x20  11     unc_iio_txn_in.atomiccmp.part3 uncore io This event is deprecated event=0x84,ch_mask=8,fc_mask=7,umask=0x20  11     unc_iio_txn_in.mem_read.part0 uncore io This event is deprecated event=0x84,ch_mask=1,fc_mask=7,umask=4  11     unc_iio_txn_in.mem_read.part1 uncore io This event is deprecated event=0x84,ch_mask=2,fc_mask=7,umask=4  11     unc_iio_txn_in.mem_read.part2 uncore io This event is deprecated event=0x84,ch_mask=4,fc_mask=7,umask=4  11     unc_iio_txn_in.mem_read.part3 uncore io This event is deprecated event=0x84,ch_mask=8,fc_mask=7,umask=4  11     unc_iio_txn_in.mem_read.vtd0 uncore io This event is deprecated event=0x84,ch_mask=0x10,fc_mask=7,umask=4  11     unc_iio_txn_in.mem_read.vtd1 uncore io This event is deprecated event=0x84,ch_mask=0x20,fc_mask=7,umask=4  11     unc_iio_txn_in.mem_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0 event=0x84,ch_mask=1,fc_mask=7,umask=1  11     unc_iio_txn_in.mem_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1 event=0x84,ch_mask=2,fc_mask=7,umask=1  11     unc_iio_txn_in.mem_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2 event=0x84,ch_mask=4,fc_mask=7,umask=1  11     unc_iio_txn_in.mem_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3 event=0x84,ch_mask=8,fc_mask=7,umask=1  11     unc_iio_txn_in.mem_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0 event=0x84,ch_mask=0x10,fc_mask=7,umask=1  11     unc_iio_txn_in.mem_write.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1 event=0x84,ch_mask=0x20,fc_mask=7,umask=1  11     unc_iio_txn_in.msg.part0 uncore io This event is deprecated event=0x84,ch_mask=1,fc_mask=7,umask=0x40  11     unc_iio_txn_in.msg.part1 uncore io This event is deprecated event=0x84,ch_mask=2,fc_mask=7,umask=0x40  11     unc_iio_txn_in.msg.part2 uncore io This event is deprecated event=0x84,ch_mask=4,fc_mask=7,umask=0x40  11     unc_iio_txn_in.msg.part3 uncore io This event is deprecated event=0x84,ch_mask=8,fc_mask=7,umask=0x40  11     unc_iio_txn_in.msg.vtd0 uncore io This event is deprecated event=0x84,ch_mask=0x10,fc_mask=7,umask=0x40  11     unc_iio_txn_in.msg.vtd1 uncore io This event is deprecated event=0x84,ch_mask=0x20,fc_mask=7,umask=0x40  11     unc_iio_txn_in.peer_read.part0 uncore io This event is deprecated event=0x84,ch_mask=1,fc_mask=7,umask=8  11     unc_iio_txn_in.peer_read.part1 uncore io This event is deprecated event=0x84,ch_mask=2,fc_mask=7,umask=8  11     unc_iio_txn_in.peer_read.part2 uncore io This event is deprecated event=0x84,ch_mask=4,fc_mask=7,umask=8  11     unc_iio_txn_in.peer_read.part3 uncore io This event is deprecated event=0x84,ch_mask=8,fc_mask=7,umask=8  11     unc_iio_txn_in.peer_read.vtd0 uncore io This event is deprecated event=0x84,ch_mask=0x10,fc_mask=7,umask=8  11     unc_iio_txn_in.peer_read.vtd1 uncore io This event is deprecated event=0x84,ch_mask=0x20,fc_mask=7,umask=8  11     unc_iio_txn_in.peer_write.part0 uncore io This event is deprecated event=0x84,ch_mask=1,fc_mask=7,umask=2  11     unc_iio_txn_in.peer_write.part1 uncore io This event is deprecated event=0x84,ch_mask=2,fc_mask=7,umask=2  11     unc_iio_txn_in.peer_write.part2 uncore io This event is deprecated event=0x84,ch_mask=4,fc_mask=7,umask=2  11     unc_iio_txn_in.peer_write.part3 uncore io This event is deprecated event=0x84,ch_mask=8,fc_mask=7,umask=2  11     unc_iio_txn_in.peer_write.vtd0 uncore io This event is deprecated event=0x84,ch_mask=0x10,fc_mask=7,umask=2  11     unc_iio_txn_in.peer_write.vtd1 uncore io This event is deprecated event=0x84,ch_mask=0x20,fc_mask=7,umask=2  11     unc_iio_txn_out.cfg_read.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0 event=0xc1,ch_mask=1,fc_mask=7,umask=0x40  11     unc_iio_txn_out.cfg_read.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1 event=0xc1,ch_mask=2,fc_mask=7,umask=0x40  11     unc_iio_txn_out.cfg_read.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2 event=0xc1,ch_mask=4,fc_mask=7,umask=0x40  11     unc_iio_txn_out.cfg_read.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3 event=0xc1,ch_mask=8,fc_mask=7,umask=0x40  11     unc_iio_txn_out.cfg_read.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0 event=0xc1,ch_mask=0x10,fc_mask=7,umask=0x40  11     unc_iio_txn_out.cfg_read.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1 event=0xc1,ch_mask=0x20,fc_mask=7,umask=0x40  11     unc_iio_txn_out.cfg_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0 event=0xc1,ch_mask=1,fc_mask=7,umask=0x10  11     unc_iio_txn_out.cfg_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1 event=0xc1,ch_mask=2,fc_mask=7,umask=0x10  11     unc_iio_txn_out.cfg_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2 event=0xc1,ch_mask=4,fc_mask=7,umask=0x10  11     unc_iio_txn_out.cfg_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3 event=0xc1,ch_mask=8,fc_mask=7,umask=0x10  11     unc_iio_txn_out.cfg_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0 event=0xc1,ch_mask=0x10,fc_mask=7,umask=0x10  11     unc_iio_txn_out.io_read.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0 event=0xc1,ch_mask=1,fc_mask=7,umask=0x80  11     unc_iio_txn_out.io_read.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1 event=0xc1,ch_mask=2,fc_mask=7,umask=0x80  11     unc_iio_txn_out.io_read.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2 event=0xc1,ch_mask=4,fc_mask=7,umask=0x80  11     unc_iio_txn_out.io_read.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3 event=0xc1,ch_mask=8,fc_mask=7,umask=0x80  11     unc_iio_txn_out.io_read.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0 event=0xc1,ch_mask=0x10,fc_mask=7,umask=0x80  11     unc_iio_txn_out.io_read.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1 event=0xc1,ch_mask=0x20,fc_mask=7,umask=0x80  11     unc_iio_txn_out.io_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0 event=0xc1,ch_mask=1,fc_mask=7,umask=0x20  11     unc_iio_txn_out.io_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1 event=0xc1,ch_mask=2,fc_mask=7,umask=0x20  11     unc_iio_txn_out.io_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2 event=0xc1,ch_mask=4,fc_mask=7,umask=0x20  11     unc_iio_txn_out.io_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3 event=0xc1,ch_mask=8,fc_mask=7,umask=0x20  11     unc_iio_txn_out.io_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0 event=0xc1,ch_mask=0x10,fc_mask=7,umask=0x20  11     unc_iio_txn_out.io_write.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1 event=0xc1,ch_mask=0x20,fc_mask=7,umask=0x20  11     unc_iio_txn_out.mem_read.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0 event=0xc1,ch_mask=1,fc_mask=7,umask=4  11     unc_iio_txn_out.mem_read.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1 event=0xc1,ch_mask=2,fc_mask=7,umask=4  11     unc_iio_txn_out.mem_read.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2 event=0xc1,ch_mask=4,fc_mask=7,umask=4  11     unc_iio_txn_out.mem_read.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3 event=0xc1,ch_mask=8,fc_mask=7,umask=4  11     unc_iio_txn_out.mem_read.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0 event=0xc1,ch_mask=0x10,fc_mask=7,umask=4  11     unc_iio_txn_out.mem_read.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1 event=0xc1,ch_mask=0x20,fc_mask=7,umask=4  11     unc_iio_txn_out.mem_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0 event=0xc1,ch_mask=1,fc_mask=7,umask=1  11     unc_iio_txn_out.mem_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1 event=0xc1,ch_mask=2,fc_mask=7,umask=1  11     unc_iio_txn_out.mem_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2 event=0xc1,ch_mask=4,fc_mask=7,umask=1  11     unc_iio_txn_out.mem_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3 event=0xc1,ch_mask=8,fc_mask=7,umask=1  11     unc_iio_txn_out.mem_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0 event=0xc1,ch_mask=0x10,fc_mask=7,umask=1  11     unc_iio_txn_out.mem_write.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1 event=0xc1,ch_mask=0x20,fc_mask=7,umask=1  11     unc_iio_txn_out.peer_read.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0 event=0xc1,ch_mask=1,fc_mask=7,umask=8  11     unc_iio_txn_out.peer_read.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1 event=0xc1,ch_mask=2,fc_mask=7,umask=8  11     unc_iio_txn_out.peer_read.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2 event=0xc1,ch_mask=4,fc_mask=7,umask=8  11     unc_iio_txn_out.peer_read.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3 event=0xc1,ch_mask=8,fc_mask=7,umask=8  11     unc_iio_txn_out.peer_read.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0 event=0xc1,ch_mask=0x10,fc_mask=7,umask=8  11     unc_iio_txn_out.peer_read.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1 event=0xc1,ch_mask=0x20,fc_mask=7,umask=8  11     unc_iio_txn_out.peer_write.part0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0 event=0xc1,ch_mask=1,fc_mask=7,umask=2  11     unc_iio_txn_out.peer_write.part1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1 event=0xc1,ch_mask=2,fc_mask=7,umask=2  11     unc_iio_txn_out.peer_write.part2 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2 event=0xc1,ch_mask=4,fc_mask=7,umask=2  11     unc_iio_txn_out.peer_write.part3 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3 event=0xc1,ch_mask=8,fc_mask=7,umask=2  11     unc_iio_txn_out.peer_write.vtd0 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0 event=0xc1,ch_mask=0x10,fc_mask=7,umask=2  11     unc_iio_txn_out.peer_write.vtd1 uncore io This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1 event=0xc1,ch_mask=0x20,fc_mask=7,umask=2  11     unc_iio_txn_req_by_cpu.cfg_read.part0 uncore io Number Transactions requested by the CPU; Core reading from Card's PCICFG space event=0xc1,ch_mask=1,fc_mask=7,umask=0x40  01    Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.cfg_read.part1 uncore io Number Transactions requested by the CPU; Core reading from Card's PCICFG space event=0xc1,ch_mask=2,fc_mask=7,umask=0x40  01    Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.cfg_read.part2 uncore io Number Transactions requested by the CPU; Core reading from Card's PCICFG space event=0xc1,ch_mask=4,fc_mask=7,umask=0x40  01    Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.cfg_read.part3 uncore io Number Transactions requested by the CPU; Core reading from Card's PCICFG space event=0xc1,ch_mask=8,fc_mask=7,umask=0x40  01    Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.cfg_read.vtd0 uncore io Number Transactions requested by the CPU; Core reading from Card's PCICFG space event=0xc1,ch_mask=0x10,fc_mask=7,umask=0x40  01    Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 0 unc_iio_txn_req_by_cpu.cfg_read.vtd1 uncore io Number Transactions requested by the CPU; Core reading from Card's PCICFG space event=0xc1,ch_mask=0x20,fc_mask=7,umask=0x40  01    Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 1 unc_iio_txn_req_by_cpu.cfg_write.part0 uncore io Number Transactions requested by the CPU; Core writing to Card's PCICFG space event=0xc1,ch_mask=1,fc_mask=7,umask=0x10  01    Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.cfg_write.part1 uncore io Number Transactions requested by the CPU; Core writing to Card's PCICFG space event=0xc1,ch_mask=2,fc_mask=7,umask=0x10  01    Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.cfg_write.part2 uncore io Number Transactions requested by the CPU; Core writing to Card's PCICFG space event=0xc1,ch_mask=4,fc_mask=7,umask=0x10  01    Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.cfg_write.part3 uncore io Number Transactions requested by the CPU; Core writing to Card's PCICFG space event=0xc1,ch_mask=8,fc_mask=7,umask=0x10  01    Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.cfg_write.vtd0 uncore io Number Transactions requested by the CPU; Core writing to Card's PCICFG space event=0xc1,ch_mask=0x10,fc_mask=7,umask=0x10  01    Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 0 unc_iio_txn_req_by_cpu.cfg_write.vtd1 uncore io Number Transactions requested by the CPU; Core writing to Card's PCICFG space event=0xc1,ch_mask=0x20,fc_mask=7,umask=0x10  01    Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 1 unc_iio_txn_req_by_cpu.io_read.part0 uncore io Number Transactions requested by the CPU; Core reading from Card's IO space event=0xc1,ch_mask=1,fc_mask=7,umask=0x80  01    Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.io_read.part1 uncore io Number Transactions requested by the CPU; Core reading from Card's IO space event=0xc1,ch_mask=2,fc_mask=7,umask=0x80  01    Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.io_read.part2 uncore io Number Transactions requested by the CPU; Core reading from Card's IO space event=0xc1,ch_mask=4,fc_mask=7,umask=0x80  01    Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.io_read.part3 uncore io Number Transactions requested by the CPU; Core reading from Card's IO space event=0xc1,ch_mask=8,fc_mask=7,umask=0x80  01    Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.io_read.vtd0 uncore io Number Transactions requested by the CPU; Core reading from Card's IO space event=0xc1,ch_mask=0x10,fc_mask=7,umask=0x80  01    Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 0 unc_iio_txn_req_by_cpu.io_read.vtd1 uncore io Number Transactions requested by the CPU; Core reading from Card's IO space event=0xc1,ch_mask=0x20,fc_mask=7,umask=0x80  01    Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 1 unc_iio_txn_req_by_cpu.io_write.part0 uncore io Number Transactions requested by the CPU; Core writing to Card's IO space event=0xc1,ch_mask=1,fc_mask=7,umask=0x20  01    Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.io_write.part1 uncore io Number Transactions requested by the CPU; Core writing to Card's IO space event=0xc1,ch_mask=2,fc_mask=7,umask=0x20  01    Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.io_write.part2 uncore io Number Transactions requested by the CPU; Core writing to Card's IO space event=0xc1,ch_mask=4,fc_mask=7,umask=0x20  01    Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.io_write.part3 uncore io Number Transactions requested by the CPU; Core writing to Card's IO space event=0xc1,ch_mask=8,fc_mask=7,umask=0x20  01    Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.io_write.vtd0 uncore io Number Transactions requested by the CPU; Core writing to Card's IO space event=0xc1,ch_mask=0x10,fc_mask=7,umask=0x20  01    Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 0 unc_iio_txn_req_by_cpu.io_write.vtd1 uncore io Number Transactions requested by the CPU; Core writing to Card's IO space event=0xc1,ch_mask=0x20,fc_mask=7,umask=0x20  01    Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 1 unc_iio_txn_req_by_cpu.mem_read.part0 uncore io Read request for up to a 64 byte transaction is made by the CPU to IIO Part0 event=0xc1,ch_mask=1,fc_mask=7,umask=4  01    Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_read.part1 uncore io Read request for up to a 64 byte transaction is made by the CPU to IIO Part1 event=0xc1,ch_mask=2,fc_mask=7,umask=4  01    Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_read.part2 uncore io Read request for up to a 64 byte transaction is made by the CPU to IIO Part2 event=0xc1,ch_mask=4,fc_mask=7,umask=4  01    Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_read.part3 uncore io Read request for up to a 64 byte transaction is made by the CPU to IIO Part3 event=0xc1,ch_mask=8,fc_mask=7,umask=4  01    Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_read.vtd0 uncore io Number Transactions requested by the CPU; Core reading from Card's MMIO space event=0xc1,ch_mask=0x10,fc_mask=7,umask=4  01    Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 0 unc_iio_txn_req_by_cpu.mem_read.vtd1 uncore io Number Transactions requested by the CPU; Core reading from Card's MMIO space event=0xc1,ch_mask=0x20,fc_mask=7,umask=4  01    Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 1 unc_iio_txn_req_by_cpu.mem_write.part0 uncore io Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU event=0xc1,ch_mask=1,fc_mask=7,umask=1  01    Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_write.part1 uncore io Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU event=0xc1,ch_mask=2,fc_mask=7,umask=1  01    Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_write.part2 uncore io Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU event=0xc1,ch_mask=4,fc_mask=7,umask=1  01    Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_write.part3 uncore io Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU event=0xc1,ch_mask=8,fc_mask=7,umask=1  01    Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_write.vtd0 uncore io Number Transactions requested by the CPU; Core writing to Card's MMIO space event=0xc1,ch_mask=0x10,fc_mask=7,umask=1  01    Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 0 unc_iio_txn_req_by_cpu.mem_write.vtd1 uncore io Number Transactions requested by the CPU; Core writing to Card's MMIO space event=0xc1,ch_mask=0x20,fc_mask=7,umask=1  01    Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 1 unc_iio_txn_req_by_cpu.peer_read.part0 uncore io Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part0 event=0xc1,ch_mask=1,fc_mask=7,umask=8  01    Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_read.part1 uncore io Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part1 event=0xc1,ch_mask=2,fc_mask=7,umask=8  01    Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_read.part2 uncore io Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part2 event=0xc1,ch_mask=4,fc_mask=7,umask=8  01    Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_read.part3 uncore io Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part3 event=0xc1,ch_mask=8,fc_mask=7,umask=8  01    Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_read.vtd0 uncore io Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card event=0xc1,ch_mask=0x10,fc_mask=7,umask=8  01    Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 0 unc_iio_txn_req_by_cpu.peer_read.vtd1 uncore io Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card event=0xc1,ch_mask=0x20,fc_mask=7,umask=8  01    Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 1 unc_iio_txn_req_by_cpu.peer_write.part0 uncore io Peer to peer write request of up to a 64 byte transaction is made to IIO Part0 by a different IIO unit event=0xc1,ch_mask=1,fc_mask=7,umask=2  01    Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_write.part1 uncore io Peer to peer write request of up to a 64 byte transaction is made to IIO Part1 by a different IIO unit event=0xc1,ch_mask=2,fc_mask=7,umask=2  01    Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_write.part2 uncore io Peer to peer write request of up to a 64 byte transaction is made to IIO Part2 by a different IIO unit event=0xc1,ch_mask=4,fc_mask=7,umask=2  01    Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_write.part3 uncore io Peer to peer write request of up to a 64 byte transaction is made to IIO Part3 by a different IIO unit event=0xc1,ch_mask=8,fc_mask=7,umask=2  01    Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_write.vtd0 uncore io Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x10,fc_mask=7,umask=2  01    Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 0 unc_iio_txn_req_by_cpu.peer_write.vtd1 uncore io Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x20,fc_mask=7,umask=2  01    Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 1 unc_iio_txn_req_of_cpu.atomic.part0 uncore io Number Transactions requested of the CPU; Atomic requests targeting DRAM event=0x84,ch_mask=1,fc_mask=7,umask=0x10  01    Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.atomic.part1 uncore io Number Transactions requested of the CPU; Atomic requests targeting DRAM event=0x84,ch_mask=2,fc_mask=7,umask=0x10  01    Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.atomic.part2 uncore io Number Transactions requested of the CPU; Atomic requests targeting DRAM event=0x84,ch_mask=4,fc_mask=7,umask=0x10  01    Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_of_cpu.atomic.part3 uncore io Number Transactions requested of the CPU; Atomic requests targeting DRAM event=0x84,ch_mask=8,fc_mask=7,umask=0x10  01    Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.atomic.vtd0 uncore io Number Transactions requested of the CPU; Atomic requests targeting DRAM event=0x84,ch_mask=0x10,fc_mask=7,umask=0x10  01    Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0 unc_iio_txn_req_of_cpu.atomic.vtd1 uncore io Number Transactions requested of the CPU; Atomic requests targeting DRAM event=0x84,ch_mask=0x20,fc_mask=7,umask=0x10  01    Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1 unc_iio_txn_req_of_cpu.atomiccmp.part0 uncore io Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM event=0x84,ch_mask=1,fc_mask=7,umask=0x20  01    Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.atomiccmp.part1 uncore io Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM event=0x84,ch_mask=2,fc_mask=7,umask=0x20  01    Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.atomiccmp.part2 uncore io Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM event=0x84,ch_mask=4,fc_mask=7,umask=0x20  01    Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_of_cpu.atomiccmp.part3 uncore io Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM event=0x84,ch_mask=8,fc_mask=7,umask=0x20  01    Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.mem_read.part0 uncore io Read request for up to a 64 byte transaction is made by IIO Part0 to Memory event=0x84,ch_mask=1,fc_mask=7,umask=4  01    Counts every read request for up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_read.part1 uncore io Read request for up to a 64 byte transaction is  made by IIO Part1 to Memory event=0x84,ch_mask=2,fc_mask=7,umask=4  01    Counts every read request for up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_read.part2 uncore io Read request for up to a 64 byte transaction is made by IIO Part2 to Memory event=0x84,ch_mask=4,fc_mask=7,umask=4  01    Counts every read request for up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_read.part3 uncore io Read request for up to a 64 byte transaction is made by IIO Part3 to Memory event=0x84,ch_mask=8,fc_mask=7,umask=4  01    Counts every read request for up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_read.vtd0 uncore io Number Transactions requested of the CPU; Card reading from DRAM event=0x84,ch_mask=0x10,fc_mask=7,umask=4  01    Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0 unc_iio_txn_req_of_cpu.mem_read.vtd1 uncore io Number Transactions requested of the CPU; Card reading from DRAM event=0x84,ch_mask=0x20,fc_mask=7,umask=4  01    Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1 unc_iio_txn_req_of_cpu.mem_write.part0 uncore io Write request of up to a 64 byte transaction is made by IIO Part0 to Memory event=0x84,ch_mask=1,fc_mask=7,umask=1  01    Counts every write request of up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_write.part1 uncore io Write request of up to a 64 byte transaction is made by IIO Part1 to Memory event=0x84,ch_mask=2,fc_mask=7,umask=1  01    Counts every write request of up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_write.part2 uncore io Write request of up to a 64 byte transaction is made by IIO Part2 to Memory event=0x84,ch_mask=4,fc_mask=7,umask=1  01    Counts every write request of up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_write.part3 uncore io Write request of up to a 64 byte transaction is made by IIO Part3 to Memory event=0x84,ch_mask=8,fc_mask=7,umask=1  01    Counts every write request of up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_write.vtd0 uncore io Number Transactions requested of the CPU; Card writing to DRAM event=0x84,ch_mask=0x10,fc_mask=7,umask=1  01    Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0 unc_iio_txn_req_of_cpu.mem_write.vtd1 uncore io Number Transactions requested of the CPU; Card writing to DRAM event=0x84,ch_mask=0x20,fc_mask=7,umask=1  01    Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1 unc_iio_txn_req_of_cpu.msg.part0 uncore io Number Transactions requested of the CPU; Messages event=0x84,ch_mask=1,fc_mask=7,umask=0x40  01    Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.msg.part1 uncore io Number Transactions requested of the CPU; Messages event=0x84,ch_mask=2,fc_mask=7,umask=0x40  01    Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.msg.part2 uncore io Number Transactions requested of the CPU; Messages event=0x84,ch_mask=4,fc_mask=7,umask=0x40  01    Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_of_cpu.msg.part3 uncore io Number Transactions requested of the CPU; Messages event=0x84,ch_mask=8,fc_mask=7,umask=0x40  01    Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.msg.vtd0 uncore io Number Transactions requested of the CPU; Messages event=0x84,ch_mask=0x10,fc_mask=7,umask=0x40  01    Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0 unc_iio_txn_req_of_cpu.msg.vtd1 uncore io Number Transactions requested of the CPU; Messages event=0x84,ch_mask=0x20,fc_mask=7,umask=0x40  01    Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1 unc_iio_txn_req_of_cpu.peer_read.part0 uncore io Peer to peer read request of up to a 64 byte transaction is made by IIO Part0 to an IIO target event=0x84,ch_mask=1,fc_mask=7,umask=8  01    Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_read.part1 uncore io Peer to peer read request of up to a 64 byte transaction is made by IIO Part1 to an IIO target event=0x84,ch_mask=2,fc_mask=7,umask=8  01    Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_read.part2 uncore io Peer to peer read request of up to a 64 byte transaction is made by IIO Part2 to an IIO target event=0x84,ch_mask=4,fc_mask=7,umask=8  01    Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_read.part3 uncore io Peer to peer read request of up to a 64 byte transaction is made by IIO Part3 to an IIO target event=0x84,ch_mask=8,fc_mask=7,umask=8  01    Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_read.vtd0 uncore io Number Transactions requested of the CPU; Card reading from another Card (same or different stack) event=0x84,ch_mask=0x10,fc_mask=7,umask=8  01    Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0 unc_iio_txn_req_of_cpu.peer_read.vtd1 uncore io Number Transactions requested of the CPU; Card reading from another Card (same or different stack) event=0x84,ch_mask=0x20,fc_mask=7,umask=8  01    Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1 unc_iio_txn_req_of_cpu.peer_write.part0 uncore io Peer to peer write request of up to a 64 byte transaction is made by IIO Part0 to an IIO target event=0x84,ch_mask=1,fc_mask=7,umask=2  01    Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_write.part1 uncore io Peer to peer write request of up to a 64 byte transaction is made by IIO Part1 to an IIO target event=0x84,ch_mask=2,fc_mask=7,umask=2  01    Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part1 to the MMIO space of an IIO target.In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_write.part2 uncore io Peer to peer write request of up to a 64 byte transaction is made by IIO Part2 to an IIO target event=0x84,ch_mask=4,fc_mask=7,umask=2  01    Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_write.part3 uncore io Peer to peer write request of up to a 64 byte transaction is made by IIO Part3 to an IIO target event=0x84,ch_mask=8,fc_mask=7,umask=2  01    Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_write.vtd0 uncore io Number Transactions requested of the CPU; Card writing to another Card (same or different stack) event=0x84,ch_mask=0x10,fc_mask=7,umask=2  01    Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0 unc_iio_txn_req_of_cpu.peer_write.vtd1 uncore io Number Transactions requested of the CPU; Card writing to another Card (same or different stack) event=0x84,ch_mask=0x20,fc_mask=7,umask=2  01    Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1 unc_iio_vtd_access.ctxt_miss uncore io VTd Access; context cache miss event=0x41,umask=2  01     unc_iio_vtd_access.l1_miss uncore io VTd Access; L1 miss event=0x41,umask=4  01     unc_iio_vtd_access.l2_miss uncore io VTd Access; L2 miss event=0x41,umask=8  01     unc_iio_vtd_access.l3_miss uncore io VTd Access; L3 miss event=0x41,umask=0x10  01     unc_iio_vtd_access.l4_page_hit uncore io VTd Access; Vtd hit event=0x41,umask=1  01     unc_iio_vtd_access.tlb1_miss uncore io VTd Access; TLB miss event=0x41,umask=0x80  01     unc_iio_vtd_access.tlb_full uncore io VTd Access; TLB is full event=0x41,umask=0x40  01     unc_iio_vtd_access.tlb_miss uncore io VTd Access; TLB miss event=0x41,umask=0x20  01     unc_iio_vtd_occupancy uncore io VTd Occupancy event=0x40  01     llc_misses.mem_read uncore memory read requests to memory controller. Derived from unc_m_cas_count.rd event=4,umask=3  0164Bytes    Counts all CAS (Column Access Select) read commands issued to DRAM on a per channel basis.  CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every read.  This event includes underfill reads due to partial write requests.  This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write)  is enabled or not llc_misses.mem_write uncore memory write requests to memory controller. Derived from unc_m_cas_count.wr event=4,umask=0xc  0164Bytes    Counts all CAS (Column Address Select) commands issued to DRAM per memory channel.  CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not unc_m_act_count.byp uncore memory DRAM Activate Count; Activate due to Bypass event=1,umask=8  01    Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_m_act_count.wr uncore memory DRAM Page Activate commands sent due to a write request event=1,umask=2  01    Counts DRAM Page Activate commands sent on this channel due to a write request to the iMC (Memory Controller).  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS (Column Access Select) command unc_m_cas_count.all uncore memory All DRAM CAS Commands issued event=4,umask=0xf  01    Counts all CAS (Column Address Select) commands issued to DRAM per memory channel.  CAS commands are issued to specify the address to read or write on DRAM, so this event increments for every read and write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not unc_m_cas_count.rd uncore memory All DRAM Read CAS Commands issued (including underfills) event=4,umask=3  01    Counts all CAS (Column Access Select) read commands issued to DRAM on a per channel basis.  CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every read.  This event includes underfill reads due to partial write requests.  This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write)  is enabled or not unc_m_cas_count.rd_isoch uncore memory DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Read ISOCH Mode event=4,umask=0x40  01     unc_m_cas_count.rd_reg uncore memory All DRAM Read CAS Commands issued (does not include underfills) event=4,umask=1  01    Counts CAS (Column Access Select) regular read commands issued to DRAM on a per channel basis.  CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every regular read.  This event only counts regular reads and does not includes underfill reads due to partial write requests.  This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write)  is enabled or not unc_m_cas_count.rd_rmm uncore memory DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in RMM event=4,umask=0x20  01     unc_m_cas_count.rd_underfill uncore memory DRAM Underfill Read CAS Commands issued event=4,umask=2  01    Counts CAS (Column Access Select) underfill read commands issued to DRAM due to a partial write, on a per channel basis.  CAS commands are issued to specify the address to read or write on DRAM, and this command counts underfill reads.  Partial writes must be completed by first reading in the underfill from DRAM and then merging in the partial write data before writing the full line back to DRAM. This event will generally count about the same as the number of partial writes, but may be slightly less because of partials hitting in the WPQ (due to a previous write request) unc_m_cas_count.rd_wmm uncore memory DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in WMM event=4,umask=0x10  01     unc_m_cas_count.wr uncore memory All DRAM Write CAS commands issued event=4,umask=0xc  01    Counts all CAS (Column Address Select) commands issued to DRAM per memory channel.  CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not unc_m_cas_count.wr_isoch uncore memory DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Write ISOCH Mode event=4,umask=0x80  01     unc_m_cas_count.wr_rmm uncore memory DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode event=4,umask=8  01    Counts the total number of Opportunistic DRAM Write CAS commands issued on this channel while in Read-Major-Mode unc_m_cas_count.wr_wmm uncore memory DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode event=4,umask=4  01    Counts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Mode unc_m_clockticks uncore memory Memory controller clock ticks event=0  01    Counts clockticks of the fixed frequency clock of the memory controller using one of the programmable counters unc_m_clockticks_f uncore memory Clockticks in the Memory Controller using a dedicated 48-bit Fixed Counter event=0xff  01     unc_m_majmode2.dram_cyc uncore memory UNC_M_MAJMODE2.DRAM_CYC event=0xed,umask=2  01     unc_m_majmode2.dram_enter uncore memory UNC_M_MAJMODE2.DRAM_ENTER event=0xed,umask=8  01     unc_m_majmode2.pmm_cyc uncore memory Major Mode 2 : Cycles in PMM major mode event=0xed,umask=1  01     unc_m_majmode2.pmm_enter uncore memory Major Mode 2 : Entered PMM major mode event=0xed,umask=4  01     unc_m_pmm_bandwidth.read uncore memory Intel Optane DC persistent memory bandwidth read (MiB/sec). Derived from unc_m_pmm_rpq_inserts event=0xe3  016.103515625E-5MiB/sec     unc_m_pmm_bandwidth.total uncore memory Intel Optane DC persistent memory bandwidth total (MiB/sec). Derived from unc_m_pmm_rpq_inserts event=0xe3  016.103515625E-5MiB/sec     unc_m_pmm_bandwidth.write uncore memory Intel Optane DC persistent memory bandwidth write (MiB/sec). Derived from unc_m_pmm_wpq_inserts event=0xe7  016.103515625E-5MiB/sec     unc_m_pmm_cmd1.all uncore memory All commands for Intel(R) Optane(TM) DC persistent memory event=0xea,umask=1  01     unc_m_pmm_cmd1.misc uncore memory Misc Commands (error, flow ACKs) event=0xea,umask=0x80  01     unc_m_pmm_cmd1.misc_gnt uncore memory Misc GNTs event=0xea,umask=0x40  01     unc_m_pmm_cmd1.rd uncore memory Regular reads(RPQ) commands for Intel(R) Optane(TM) DC persistent memory event=0xea,umask=2  01    All Reads - RPQ or Ufill unc_m_pmm_cmd1.rpq_gnts uncore memory RPQ GNTs event=0xea,umask=0x10  01     unc_m_pmm_cmd1.ufill_rd uncore memory Underfill read commands for Intel(R) Optane(TM) DC persistent memory event=0xea,umask=8  01    Underfill reads unc_m_pmm_cmd1.wpq_gnts uncore memory Underfill GNTs event=0xea,umask=0x20  01     unc_m_pmm_cmd1.wr uncore memory Write commands for Intel(R) Optane(TM) DC persistent memory event=0xea,umask=4  01    Writes unc_m_pmm_cmd2.nodata_exp uncore memory Expected No data packet (ERID matched NDP encoding) event=0xeb,umask=2  01     unc_m_pmm_cmd2.nodata_unexp uncore memory Unexpected No data packet (ERID matched a Read, but data was a NDP) event=0xeb,umask=4  01     unc_m_pmm_cmd2.opp_rd uncore memory Opportunistic Reads event=0xeb,umask=1  01     unc_m_pmm_cmd2.pmm_ecc_error uncore memory PMM ECC Errors event=0xeb,umask=0x20  01     unc_m_pmm_cmd2.pmm_erid_error uncore memory PMM ERID detectable parity error event=0xeb,umask=0x40  01     unc_m_pmm_cmd2.reqs_slot0 uncore memory Read Requests - Slot 0 event=0xeb,umask=8  01     unc_m_pmm_cmd2.reqs_slot1 uncore memory Read Requests - Slot 1 event=0xeb,umask=0x10  01     unc_m_pmm_majmode1.partial_wr_cyc uncore memory PMM Major Mode; Cycles PMM is in Partial Write Major Mode event=0xec,umask=4  01     unc_m_pmm_majmode1.partial_wr_enter uncore memory PMM Major Mode event=0xec,umask=0x20  01     unc_m_pmm_majmode1.partial_wr_exit uncore memory PMM Major Mode event=0xec,umask=0x40  01     unc_m_pmm_majmode1.rd_cyc uncore memory PMM Major Mode; Cycles PMM is in Read Major Mode event=0xec,umask=1  01     unc_m_pmm_majmode1.wr_cyc uncore memory PMM Major Mode; Cycles PMM is in Write Major Mode event=0xec,umask=2  01     unc_m_pmm_read_latency uncore memory Intel Optane DC persistent memory read latency (ns). Derived from unc_m_pmm_rpq_occupancy.all event=0xe0,umask=1  016000000000ns     unc_m_pmm_rpq_cycles_full uncore memory PMM Read Queue Cycles Full event=0xe2  01     unc_m_pmm_rpq_cycles_ne uncore memory PMM Read Queue Cycles Not Empty event=0xe1  01     unc_m_pmm_rpq_inserts uncore memory Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory event=0xe3  01     unc_m_pmm_rpq_occupancy.all uncore memory Read Pending Queue Occupancy of all read requests for Intel Optane DC persistent memory event=0xe0,umask=1  01     unc_m_pmm_rpq_occupancy.gnt_wait uncore memory PMM Occupancy event=0xe0,umask=4  01     unc_m_pmm_wpq_cycles_full uncore memory PMM Write Queue Cycles Full event=0xe6  01     unc_m_pmm_wpq_cycles_ne uncore memory PMM Write Queue Cycles Not Empty event=0xe5  01     unc_m_pmm_wpq_inserts uncore memory Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory event=0xe7  01     unc_m_pmm_wpq_occupancy.all uncore memory Write Pending Queue Occupancy of all write requests for Intel(R) Optane(TM) DC persistent memory event=0xe4,umask=1  01     unc_m_pmm_wpq_occupancy.cas uncore memory PMM Occupancy event=0xe4,umask=2  01     unc_m_pmm_wpq_occupancy.pwr uncore memory PMM Occupancy event=0xe4,umask=4  01     unc_m_pmm_wpq_pcommit uncore memory UNC_M_PMM_WPQ_PCOMMIT event=0xe8  01     unc_m_pmm_wpq_pcommit_cyc uncore memory UNC_M_PMM_WPQ_PCOMMIT_CYC event=0xe9  01     unc_m_power_channel_ppd uncore memory Cycles where DRAM ranks are in power down (CKE) mode+C37 event=0x85  01    Counts cycles when all the ranks in the channel are in PPD (PreCharge Power Down) mode. If IBT (Input Buffer Terminators)=off is enabled, then this event counts the cycles in PPD mode. If IBT=off is not enabled, then this event counts the number of cycles when being in PPD mode could have been taken advantage of unc_m_power_self_refresh uncore memory Cycles Memory is in self refresh power mode event=0x43  01    Counts the number of cycles when the iMC (memory controller) is in self-refresh and has a clock. This happens in some ACPI CPU package C-states for the sleep levels. For example, the PCU (Power Control Unit) may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Intel? Dynamic Power Technology.  Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases unc_m_pre_count.page_miss uncore memory Pre-charges due to page misses event=2,umask=1  01    Counts the number of explicit DRAM Precharge commands sent on this channel as a result of a DRAM page miss. This does not include the implicit precharge commands sent with CAS commands in Auto-Precharge mode. This does not include Precharge commands sent as a result of a page close counter expiration unc_m_pre_count.rd uncore memory Pre-charge for reads event=2,umask=4  01    Counts the number of explicit DRAM Precharge commands issued on a per channel basis due to a read, so as to close the previous DRAM page, before opening the requested page unc_m_pre_count.wr uncore memory Pre-charge for writes event=2,umask=8  01    Counts the number of DRAM Precharge commands sent on this channel unc_m_rd_cas_rank0.allbanks uncore memory RD_CAS Access to Rank 0; All Banks event=0xb0,umask=0x10  01     unc_m_rd_cas_rank0.bank0 uncore memory RD_CAS Access to Rank 0; Bank 0 event=0xb0  01     unc_m_rd_cas_rank0.bank1 uncore memory RD_CAS Access to Rank 0; Bank 1 event=0xb0,umask=1  01     unc_m_rd_cas_rank0.bank10 uncore memory RD_CAS Access to Rank 0; Bank 10 event=0xb0,umask=0xa  01     unc_m_rd_cas_rank0.bank11 uncore memory RD_CAS Access to Rank 0; Bank 11 event=0xb0,umask=0xb  01     unc_m_rd_cas_rank0.bank12 uncore memory RD_CAS Access to Rank 0; Bank 12 event=0xb0,umask=0xc  01     unc_m_rd_cas_rank0.bank13 uncore memory RD_CAS Access to Rank 0; Bank 13 event=0xb0,umask=0xd  01     unc_m_rd_cas_rank0.bank14 uncore memory RD_CAS Access to Rank 0; Bank 14 event=0xb0,umask=0xe  01     unc_m_rd_cas_rank0.bank15 uncore memory RD_CAS Access to Rank 0; Bank 15 event=0xb0,umask=0xf  01     unc_m_rd_cas_rank0.bank2 uncore memory RD_CAS Access to Rank 0; Bank 2 event=0xb0,umask=2  01     unc_m_rd_cas_rank0.bank3 uncore memory RD_CAS Access to Rank 0; Bank 3 event=0xb0,umask=3  01     unc_m_rd_cas_rank0.bank4 uncore memory RD_CAS Access to Rank 0; Bank 4 event=0xb0,umask=4  01     unc_m_rd_cas_rank0.bank5 uncore memory RD_CAS Access to Rank 0; Bank 5 event=0xb0,umask=5  01     unc_m_rd_cas_rank0.bank6 uncore memory RD_CAS Access to Rank 0; Bank 6 event=0xb0,umask=6  01     unc_m_rd_cas_rank0.bank7 uncore memory RD_CAS Access to Rank 0; Bank 7 event=0xb0,umask=7  01     unc_m_rd_cas_rank0.bank8 uncore memory RD_CAS Access to Rank 0; Bank 8 event=0xb0,umask=8  01     unc_m_rd_cas_rank0.bank9 uncore memory RD_CAS Access to Rank 0; Bank 9 event=0xb0,umask=9  01     unc_m_rd_cas_rank0.bankg0 uncore memory RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3) event=0xb0,umask=0x11  01     unc_m_rd_cas_rank0.bankg1 uncore memory RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7) event=0xb0,umask=0x12  01     unc_m_rd_cas_rank0.bankg2 uncore memory RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11) event=0xb0,umask=0x13  01     unc_m_rd_cas_rank0.bankg3 uncore memory RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15) event=0xb0,umask=0x14  01     unc_m_rd_cas_rank1.allbanks uncore memory RD_CAS Access to Rank 1; All Banks event=0xb1,umask=0x10  01     unc_m_rd_cas_rank1.bank0 uncore memory RD_CAS Access to Rank 1; Bank 0 event=0xb1  01     unc_m_rd_cas_rank1.bank1 uncore memory RD_CAS Access to Rank 1; Bank 1 event=0xb1,umask=1  01     unc_m_rd_cas_rank1.bank10 uncore memory RD_CAS Access to Rank 1; Bank 10 event=0xb1,umask=0xa  01     unc_m_rd_cas_rank1.bank11 uncore memory RD_CAS Access to Rank 1; Bank 11 event=0xb1,umask=0xb  01     unc_m_rd_cas_rank1.bank12 uncore memory RD_CAS Access to Rank 1; Bank 12 event=0xb1,umask=0xc  01     unc_m_rd_cas_rank1.bank13 uncore memory RD_CAS Access to Rank 1; Bank 13 event=0xb1,umask=0xd  01     unc_m_rd_cas_rank1.bank14 uncore memory RD_CAS Access to Rank 1; Bank 14 event=0xb1,umask=0xe  01     unc_m_rd_cas_rank1.bank15 uncore memory RD_CAS Access to Rank 1; Bank 15 event=0xb1,umask=0xf  01     unc_m_rd_cas_rank1.bank2 uncore memory RD_CAS Access to Rank 1; Bank 2 event=0xb1,umask=2  01     unc_m_rd_cas_rank1.bank3 uncore memory RD_CAS Access to Rank 1; Bank 3 event=0xb1,umask=3  01     unc_m_rd_cas_rank1.bank4 uncore memory RD_CAS Access to Rank 1; Bank 4 event=0xb1,umask=4  01     unc_m_rd_cas_rank1.bank5 uncore memory RD_CAS Access to Rank 1; Bank 5 event=0xb1,umask=5  01     unc_m_rd_cas_rank1.bank6 uncore memory RD_CAS Access to Rank 1; Bank 6 event=0xb1,umask=6  01     unc_m_rd_cas_rank1.bank7 uncore memory RD_CAS Access to Rank 1; Bank 7 event=0xb1,umask=7  01     unc_m_rd_cas_rank1.bank8 uncore memory RD_CAS Access to Rank 1; Bank 8 event=0xb1,umask=8  01     unc_m_rd_cas_rank1.bank9 uncore memory RD_CAS Access to Rank 1; Bank 9 event=0xb1,umask=9  01     unc_m_rd_cas_rank1.bankg0 uncore memory RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3) event=0xb1,umask=0x11  01     unc_m_rd_cas_rank1.bankg1 uncore memory RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7) event=0xb1,umask=0x12  01     unc_m_rd_cas_rank1.bankg2 uncore memory RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11) event=0xb1,umask=0x13  01     unc_m_rd_cas_rank1.bankg3 uncore memory RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15) event=0xb1,umask=0x14  01     unc_m_rd_cas_rank2.allbanks uncore memory RD_CAS Access to Rank 2; All Banks event=0xb2,umask=0x10  01     unc_m_rd_cas_rank2.bank0 uncore memory RD_CAS Access to Rank 2; Bank 0 event=0xb2  01     unc_m_rd_cas_rank2.bank1 uncore memory RD_CAS Access to Rank 2; Bank 1 event=0xb2,umask=1  01     unc_m_rd_cas_rank2.bank10 uncore memory RD_CAS Access to Rank 2; Bank 10 event=0xb2,umask=0xa  01     unc_m_rd_cas_rank2.bank11 uncore memory RD_CAS Access to Rank 2; Bank 11 event=0xb2,umask=0xb  01     unc_m_rd_cas_rank2.bank12 uncore memory RD_CAS Access to Rank 2; Bank 12 event=0xb2,umask=0xc  01     unc_m_rd_cas_rank2.bank13 uncore memory RD_CAS Access to Rank 2; Bank 13 event=0xb2,umask=0xd  01     unc_m_rd_cas_rank2.bank14 uncore memory RD_CAS Access to Rank 2; Bank 14 event=0xb2,umask=0xe  01     unc_m_rd_cas_rank2.bank15 uncore memory RD_CAS Access to Rank 2; Bank 15 event=0xb2,umask=0xf  01     unc_m_rd_cas_rank2.bank2 uncore memory RD_CAS Access to Rank 2; Bank 2 event=0xb2,umask=2  01     unc_m_rd_cas_rank2.bank3 uncore memory RD_CAS Access to Rank 2; Bank 3 event=0xb2,umask=3  01     unc_m_rd_cas_rank2.bank4 uncore memory RD_CAS Access to Rank 2; Bank 4 event=0xb2,umask=4  01     unc_m_rd_cas_rank2.bank5 uncore memory RD_CAS Access to Rank 2; Bank 5 event=0xb2,umask=5  01     unc_m_rd_cas_rank2.bank6 uncore memory RD_CAS Access to Rank 2; Bank 6 event=0xb2,umask=6  01     unc_m_rd_cas_rank2.bank7 uncore memory RD_CAS Access to Rank 2; Bank 7 event=0xb2,umask=7  01     unc_m_rd_cas_rank2.bank8 uncore memory RD_CAS Access to Rank 2; Bank 8 event=0xb2,umask=8  01     unc_m_rd_cas_rank2.bank9 uncore memory RD_CAS Access to Rank 2; Bank 9 event=0xb2,umask=9  01     unc_m_rd_cas_rank2.bankg0 uncore memory RD_CAS Access to Rank 2; Bank Group 0 (Banks 0-3) event=0xb2,umask=0x11  01     unc_m_rd_cas_rank2.bankg1 uncore memory RD_CAS Access to Rank 2; Bank Group 1 (Banks 4-7) event=0xb2,umask=0x12  01     unc_m_rd_cas_rank2.bankg2 uncore memory RD_CAS Access to Rank 2; Bank Group 2 (Banks 8-11) event=0xb2,umask=0x13  01     unc_m_rd_cas_rank2.bankg3 uncore memory RD_CAS Access to Rank 2; Bank Group 3 (Banks 12-15) event=0xb2,umask=0x14  01     unc_m_rd_cas_rank3.allbanks uncore memory RD_CAS Access to Rank 3; All Banks event=0xb3,umask=0x10  01     unc_m_rd_cas_rank3.bank0 uncore memory RD_CAS Access to Rank 3; Bank 0 event=0xb3  01     unc_m_rd_cas_rank3.bank1 uncore memory RD_CAS Access to Rank 3; Bank 1 event=0xb3,umask=1  01     unc_m_rd_cas_rank3.bank10 uncore memory RD_CAS Access to Rank 3; Bank 10 event=0xb3,umask=0xa  01     unc_m_rd_cas_rank3.bank11 uncore memory RD_CAS Access to Rank 3; Bank 11 event=0xb3,umask=0xb  01     unc_m_rd_cas_rank3.bank12 uncore memory RD_CAS Access to Rank 3; Bank 12 event=0xb3,umask=0xc  01     unc_m_rd_cas_rank3.bank13 uncore memory RD_CAS Access to Rank 3; Bank 13 event=0xb3,umask=0xd  01     unc_m_rd_cas_rank3.bank14 uncore memory RD_CAS Access to Rank 3; Bank 14 event=0xb3,umask=0xe  01     unc_m_rd_cas_rank3.bank15 uncore memory RD_CAS Access to Rank 3; Bank 15 event=0xb3,umask=0xf  01     unc_m_rd_cas_rank3.bank2 uncore memory RD_CAS Access to Rank 3; Bank 2 event=0xb3,umask=2  01     unc_m_rd_cas_rank3.bank3 uncore memory RD_CAS Access to Rank 3; Bank 3 event=0xb3,umask=3  01     unc_m_rd_cas_rank3.bank4 uncore memory RD_CAS Access to Rank 3; Bank 4 event=0xb3,umask=4  01     unc_m_rd_cas_rank3.bank5 uncore memory RD_CAS Access to Rank 3; Bank 5 event=0xb3,umask=5  01     unc_m_rd_cas_rank3.bank6 uncore memory RD_CAS Access to Rank 3; Bank 6 event=0xb3,umask=6  01     unc_m_rd_cas_rank3.bank7 uncore memory RD_CAS Access to Rank 3; Bank 7 event=0xb3,umask=7  01     unc_m_rd_cas_rank3.bank8 uncore memory RD_CAS Access to Rank 3; Bank 8 event=0xb3,umask=8  01     unc_m_rd_cas_rank3.bank9 uncore memory RD_CAS Access to Rank 3; Bank 9 event=0xb3,umask=9  01     unc_m_rd_cas_rank3.bankg0 uncore memory RD_CAS Access to Rank 3; Bank Group 0 (Banks 0-3) event=0xb3,umask=0x11  01     unc_m_rd_cas_rank3.bankg1 uncore memory RD_CAS Access to Rank 3; Bank Group 1 (Banks 4-7) event=0xb3,umask=0x12  01     unc_m_rd_cas_rank3.bankg2 uncore memory RD_CAS Access to Rank 3; Bank Group 2 (Banks 8-11) event=0xb3,umask=0x13  01     unc_m_rd_cas_rank3.bankg3 uncore memory RD_CAS Access to Rank 3; Bank Group 3 (Banks 12-15) event=0xb3,umask=0x14  01     unc_m_rd_cas_rank4.allbanks uncore memory RD_CAS Access to Rank 4; All Banks event=0xb4,umask=0x10  01     unc_m_rd_cas_rank4.bank0 uncore memory RD_CAS Access to Rank 4; Bank 0 event=0xb4  01     unc_m_rd_cas_rank4.bank1 uncore memory RD_CAS Access to Rank 4; Bank 1 event=0xb4,umask=1  01     unc_m_rd_cas_rank4.bank10 uncore memory RD_CAS Access to Rank 4; Bank 10 event=0xb4,umask=0xa  01     unc_m_rd_cas_rank4.bank11 uncore memory RD_CAS Access to Rank 4; Bank 11 event=0xb4,umask=0xb  01     unc_m_rd_cas_rank4.bank12 uncore memory RD_CAS Access to Rank 4; Bank 12 event=0xb4,umask=0xc  01     unc_m_rd_cas_rank4.bank13 uncore memory RD_CAS Access to Rank 4; Bank 13 event=0xb4,umask=0xd  01     unc_m_rd_cas_rank4.bank14 uncore memory RD_CAS Access to Rank 4; Bank 14 event=0xb4,umask=0xe  01     unc_m_rd_cas_rank4.bank15 uncore memory RD_CAS Access to Rank 4; Bank 15 event=0xb4,umask=0xf  01     unc_m_rd_cas_rank4.bank2 uncore memory RD_CAS Access to Rank 4; Bank 2 event=0xb4,umask=2  01     unc_m_rd_cas_rank4.bank3 uncore memory RD_CAS Access to Rank 4; Bank 3 event=0xb4,umask=3  01     unc_m_rd_cas_rank4.bank4 uncore memory RD_CAS Access to Rank 4; Bank 4 event=0xb4,umask=4  01     unc_m_rd_cas_rank4.bank5 uncore memory RD_CAS Access to Rank 4; Bank 5 event=0xb4,umask=5  01     unc_m_rd_cas_rank4.bank6 uncore memory RD_CAS Access to Rank 4; Bank 6 event=0xb4,umask=6  01     unc_m_rd_cas_rank4.bank7 uncore memory RD_CAS Access to Rank 4; Bank 7 event=0xb4,umask=7  01     unc_m_rd_cas_rank4.bank8 uncore memory RD_CAS Access to Rank 4; Bank 8 event=0xb4,umask=8  01     unc_m_rd_cas_rank4.bank9 uncore memory RD_CAS Access to Rank 4; Bank 9 event=0xb4,umask=9  01     unc_m_rd_cas_rank4.bankg0 uncore memory RD_CAS Access to Rank 4; Bank Group 0 (Banks 0-3) event=0xb4,umask=0x11  01     unc_m_rd_cas_rank4.bankg1 uncore memory RD_CAS Access to Rank 4; Bank Group 1 (Banks 4-7) event=0xb4,umask=0x12  01     unc_m_rd_cas_rank4.bankg2 uncore memory RD_CAS Access to Rank 4; Bank Group 2 (Banks 8-11) event=0xb4,umask=0x13  01     unc_m_rd_cas_rank4.bankg3 uncore memory RD_CAS Access to Rank 4; Bank Group 3 (Banks 12-15) event=0xb4,umask=0x14  01     unc_m_rd_cas_rank5.allbanks uncore memory RD_CAS Access to Rank 5; All Banks event=0xb5,umask=0x10  01     unc_m_rd_cas_rank5.bank0 uncore memory RD_CAS Access to Rank 5; Bank 0 event=0xb5  01     unc_m_rd_cas_rank5.bank1 uncore memory RD_CAS Access to Rank 5; Bank 1 event=0xb5,umask=1  01     unc_m_rd_cas_rank5.bank10 uncore memory RD_CAS Access to Rank 5; Bank 10 event=0xb5,umask=0xa  01     unc_m_rd_cas_rank5.bank11 uncore memory RD_CAS Access to Rank 5; Bank 11 event=0xb5,umask=0xb  01     unc_m_rd_cas_rank5.bank12 uncore memory RD_CAS Access to Rank 5; Bank 12 event=0xb5,umask=0xc  01     unc_m_rd_cas_rank5.bank13 uncore memory RD_CAS Access to Rank 5; Bank 13 event=0xb5,umask=0xd  01     unc_m_rd_cas_rank5.bank14 uncore memory RD_CAS Access to Rank 5; Bank 14 event=0xb5,umask=0xe  01     unc_m_rd_cas_rank5.bank15 uncore memory RD_CAS Access to Rank 5; Bank 15 event=0xb5,umask=0xf  01     unc_m_rd_cas_rank5.bank2 uncore memory RD_CAS Access to Rank 5; Bank 2 event=0xb5,umask=2  01     unc_m_rd_cas_rank5.bank3 uncore memory RD_CAS Access to Rank 5; Bank 3 event=0xb5,umask=3  01     unc_m_rd_cas_rank5.bank4 uncore memory RD_CAS Access to Rank 5; Bank 4 event=0xb5,umask=4  01     unc_m_rd_cas_rank5.bank5 uncore memory RD_CAS Access to Rank 5; Bank 5 event=0xb5,umask=5  01     unc_m_rd_cas_rank5.bank6 uncore memory RD_CAS Access to Rank 5; Bank 6 event=0xb5,umask=6  01     unc_m_rd_cas_rank5.bank7 uncore memory RD_CAS Access to Rank 5; Bank 7 event=0xb5,umask=7  01     unc_m_rd_cas_rank5.bank8 uncore memory RD_CAS Access to Rank 5; Bank 8 event=0xb5,umask=8  01     unc_m_rd_cas_rank5.bank9 uncore memory RD_CAS Access to Rank 5; Bank 9 event=0xb5,umask=9  01     unc_m_rd_cas_rank5.bankg0 uncore memory RD_CAS Access to Rank 5; Bank Group 0 (Banks 0-3) event=0xb5,umask=0x11  01     unc_m_rd_cas_rank5.bankg1 uncore memory RD_CAS Access to Rank 5; Bank Group 1 (Banks 4-7) event=0xb5,umask=0x12  01     unc_m_rd_cas_rank5.bankg2 uncore memory RD_CAS Access to Rank 5; Bank Group 2 (Banks 8-11) event=0xb5,umask=0x13  01     unc_m_rd_cas_rank5.bankg3 uncore memory RD_CAS Access to Rank 5; Bank Group 3 (Banks 12-15) event=0xb5,umask=0x14  01     unc_m_rd_cas_rank6.allbanks uncore memory RD_CAS Access to Rank 6; All Banks event=0xb6,umask=0x10  01     unc_m_rd_cas_rank6.bank0 uncore memory RD_CAS Access to Rank 6; Bank 0 event=0xb6  01     unc_m_rd_cas_rank6.bank1 uncore memory RD_CAS Access to Rank 6; Bank 1 event=0xb6,umask=1  01     unc_m_rd_cas_rank6.bank10 uncore memory RD_CAS Access to Rank 6; Bank 10 event=0xb6,umask=0xa  01     unc_m_rd_cas_rank6.bank11 uncore memory RD_CAS Access to Rank 6; Bank 11 event=0xb6,umask=0xb  01     unc_m_rd_cas_rank6.bank12 uncore memory RD_CAS Access to Rank 6; Bank 12 event=0xb6,umask=0xc  01     unc_m_rd_cas_rank6.bank13 uncore memory RD_CAS Access to Rank 6; Bank 13 event=0xb6,umask=0xd  01     unc_m_rd_cas_rank6.bank14 uncore memory RD_CAS Access to Rank 6; Bank 14 event=0xb6,umask=0xe  01     unc_m_rd_cas_rank6.bank15 uncore memory RD_CAS Access to Rank 6; Bank 15 event=0xb6,umask=0xf  01     unc_m_rd_cas_rank6.bank2 uncore memory RD_CAS Access to Rank 6; Bank 2 event=0xb6,umask=2  01     unc_m_rd_cas_rank6.bank3 uncore memory RD_CAS Access to Rank 6; Bank 3 event=0xb6,umask=3  01     unc_m_rd_cas_rank6.bank4 uncore memory RD_CAS Access to Rank 6; Bank 4 event=0xb6,umask=4  01     unc_m_rd_cas_rank6.bank5 uncore memory RD_CAS Access to Rank 6; Bank 5 event=0xb6,umask=5  01     unc_m_rd_cas_rank6.bank6 uncore memory RD_CAS Access to Rank 6; Bank 6 event=0xb6,umask=6  01     unc_m_rd_cas_rank6.bank7 uncore memory RD_CAS Access to Rank 6; Bank 7 event=0xb6,umask=7  01     unc_m_rd_cas_rank6.bank8 uncore memory RD_CAS Access to Rank 6; Bank 8 event=0xb6,umask=8  01     unc_m_rd_cas_rank6.bank9 uncore memory RD_CAS Access to Rank 6; Bank 9 event=0xb6,umask=9  01     unc_m_rd_cas_rank6.bankg0 uncore memory RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3) event=0xb6,umask=0x11  01     unc_m_rd_cas_rank6.bankg1 uncore memory RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7) event=0xb6,umask=0x12  01     unc_m_rd_cas_rank6.bankg2 uncore memory RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11) event=0xb6,umask=0x13  01     unc_m_rd_cas_rank6.bankg3 uncore memory RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15) event=0xb6,umask=0x14  01     unc_m_rd_cas_rank7.allbanks uncore memory RD_CAS Access to Rank 7; All Banks event=0xb7,umask=0x10  01     unc_m_rd_cas_rank7.bank0 uncore memory RD_CAS Access to Rank 7; Bank 0 event=0xb7  01     unc_m_rd_cas_rank7.bank1 uncore memory RD_CAS Access to Rank 7; Bank 1 event=0xb7,umask=1  01     unc_m_rd_cas_rank7.bank10 uncore memory RD_CAS Access to Rank 7; Bank 10 event=0xb7,umask=0xa  01     unc_m_rd_cas_rank7.bank11 uncore memory RD_CAS Access to Rank 7; Bank 11 event=0xb7,umask=0xb  01     unc_m_rd_cas_rank7.bank12 uncore memory RD_CAS Access to Rank 7; Bank 12 event=0xb7,umask=0xc  01     unc_m_rd_cas_rank7.bank13 uncore memory RD_CAS Access to Rank 7; Bank 13 event=0xb7,umask=0xd  01     unc_m_rd_cas_rank7.bank14 uncore memory RD_CAS Access to Rank 7; Bank 14 event=0xb7,umask=0xe  01     unc_m_rd_cas_rank7.bank15 uncore memory RD_CAS Access to Rank 7; Bank 15 event=0xb7,umask=0xf  01     unc_m_rd_cas_rank7.bank2 uncore memory RD_CAS Access to Rank 7; Bank 2 event=0xb7,umask=2  01     unc_m_rd_cas_rank7.bank3 uncore memory RD_CAS Access to Rank 7; Bank 3 event=0xb7,umask=3  01     unc_m_rd_cas_rank7.bank4 uncore memory RD_CAS Access to Rank 7; Bank 4 event=0xb7,umask=4  01     unc_m_rd_cas_rank7.bank5 uncore memory RD_CAS Access to Rank 7; Bank 5 event=0xb7,umask=5  01     unc_m_rd_cas_rank7.bank6 uncore memory RD_CAS Access to Rank 7; Bank 6 event=0xb7,umask=6  01     unc_m_rd_cas_rank7.bank7 uncore memory RD_CAS Access to Rank 7; Bank 7 event=0xb7,umask=7  01     unc_m_rd_cas_rank7.bank8 uncore memory RD_CAS Access to Rank 7; Bank 8 event=0xb7,umask=8  01     unc_m_rd_cas_rank7.bank9 uncore memory RD_CAS Access to Rank 7; Bank 9 event=0xb7,umask=9  01     unc_m_rd_cas_rank7.bankg0 uncore memory RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3) event=0xb7,umask=0x11  01     unc_m_rd_cas_rank7.bankg1 uncore memory RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7) event=0xb7,umask=0x12  01     unc_m_rd_cas_rank7.bankg2 uncore memory RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11) event=0xb7,umask=0x13  01     unc_m_rd_cas_rank7.bankg3 uncore memory RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15) event=0xb7,umask=0x14  01     unc_m_rpq_cycles_full uncore memory Read Pending Queue Full Cycles event=0x12  01    Counts the number of cycles when the Read Pending Queue is full.  When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC.  This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead.  We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM.  This event only tracks non-ISOC queue entries unc_m_rpq_inserts uncore memory Read Pending Queue Allocations event=0x10  01    Counts the number of read requests allocated into the Read Pending Queue (RPQ).  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  The requests deallocate after the read CAS command has been issued to DRAM.  This event counts both Isochronous and non-Isochronous requests which were issued to the RPQ unc_m_rpq_occupancy uncore memory Read Pending Queue Occupancy event=0x80  01    Counts the number of entries in the Read Pending Queue (RPQ) at each cycle.  This can then be used to calculate both the average occupancy of the queue (in conjunction with the number of cycles not empty) and the average latency in the queue (in conjunction with the number of allocations).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate from the RPQ after the CAS command has been issued to memory unc_m_sb_accesses.fm_rd_cmps uncore memory Scoreboard Accesses; Write Accepts event=0xd2,umask=0x40  01     unc_m_sb_accesses.fm_wr_cmps uncore memory Scoreboard Accesses; Write Rejects event=0xd2,umask=0x80  01     unc_m_sb_accesses.nm_rd_cmps uncore memory Scoreboard Accesses; FM read completions event=0xd2,umask=0x10  01     unc_m_sb_accesses.nm_wr_cmps uncore memory Scoreboard Accesses; FM write completions event=0xd2,umask=0x20  01     unc_m_sb_accesses.rd_accepts uncore memory Scoreboard Accesses; Read Accepts event=0xd2,umask=1  01     unc_m_sb_accesses.rd_rejects uncore memory Scoreboard Accesses; Read Rejects event=0xd2,umask=2  01     unc_m_sb_accesses.wr_accepts uncore memory Scoreboard Accesses; NM read completions event=0xd2,umask=4  01     unc_m_sb_accesses.wr_rejects uncore memory Scoreboard Accesses; NM write completions event=0xd2,umask=8  01     unc_m_sb_canary.alloc uncore memory Alloc event=0xd9,umask=1  01     unc_m_sb_canary.dealloc uncore memory Dealloc event=0xd9,umask=2  01     unc_m_sb_canary.fmrd_starved uncore memory Far Mem Read Starved event=0xd9,umask=0x40  01     unc_m_sb_canary.fmwr_starved uncore memory Far Mem Write Starved event=0xd9,umask=0x80  01     unc_m_sb_canary.nmrd_starved uncore memory Near Mem Read Starved event=0xd9,umask=0x10  01     unc_m_sb_canary.nmwr_starved uncore memory Near Mem Write Starved event=0xd9,umask=0x20  01     unc_m_sb_canary.rej uncore memory Reject event=0xd9,umask=4  01     unc_m_sb_canary.vld uncore memory Valid event=0xd9,umask=8  01     unc_m_sb_cycles_full uncore memory Scoreboard Cycles Full event=0xd1  01     unc_m_sb_cycles_ne uncore memory Scoreboard Cycles Not-Empty event=0xd0  01     unc_m_sb_inserts.block_rds uncore memory Scoreboard Inserts; Block region reads event=0xd6,umask=0x10  01     unc_m_sb_inserts.block_wrs uncore memory Scoreboard Inserts; Block region writes event=0xd6,umask=0x20  01     unc_m_sb_inserts.dealloc uncore memory Scoreboard Inserts; Dealloc all commands (for error flows) event=0xd6,umask=0x40  01     unc_m_sb_inserts.patrol uncore memory Scoreboard Inserts; Patrol inserts event=0xd6,umask=0x80  01     unc_m_sb_inserts.pmm_rds uncore memory Scoreboard Inserts; Persistent Mem reads event=0xd6,umask=4  01     unc_m_sb_inserts.pmm_wrs uncore memory Scoreboard Inserts; Persistent Mem writes event=0xd6,umask=8  01     unc_m_sb_inserts.rds uncore memory Scoreboard Inserts; Reads event=0xd6,umask=1  01     unc_m_sb_inserts.wrs uncore memory Scoreboard Inserts; Writes event=0xd6,umask=2  01     unc_m_sb_occupancy.block_rds uncore memory Scoreboard Occupancy; Block region reads event=0xd5,umask=0x20  01     unc_m_sb_occupancy.block_wrs uncore memory Scoreboard Occupancy; Block region writes event=0xd5,umask=0x40  01     unc_m_sb_occupancy.patrol uncore memory Scoreboard Occupancy; Patrol event=0xd5,umask=0x80  01     unc_m_sb_occupancy.pmm_rds uncore memory Scoreboard Occupancy; Persistent Mem reads event=0xd5,umask=4  01     unc_m_sb_occupancy.pmm_wrs uncore memory Scoreboard Occupancy; Persistent Mem writes event=0xd5,umask=8  01     unc_m_sb_occupancy.rds uncore memory Scoreboard Occupancy; Reads event=0xd5,umask=1  01     unc_m_sb_occupancy.wrs uncore memory Scoreboard Occupancy; Writes event=0xd5,umask=2  01     unc_m_sb_reject.fm_addr_cnflt uncore memory Number of Scoreboard Requests Rejected; FM requests rejected due to full address conflict event=0xd4,umask=2  01     unc_m_sb_reject.nm_set_cnflt uncore memory Number of Scoreboard Requests Rejected; NM requests rejected due to set conflict event=0xd4,umask=1  01     unc_m_sb_reject.patrol_set_cnflt uncore memory Number of Scoreboard Requests Rejected; Patrol requests rejected due to set conflict event=0xd4,umask=4  01     unc_m_sb_strv_alloc.fmrd_clr uncore memory Far Mem Read - Clear event=0xd7,umask=0x20  01     unc_m_sb_strv_alloc.fmrd_set uncore memory Far Mem Read - Set event=0xd7,umask=2  01     unc_m_sb_strv_alloc.fmwr_clr uncore memory Far Mem Write - Clear event=0xd7,umask=0x80  01     unc_m_sb_strv_alloc.fmwr_set uncore memory Far Mem Write - Set event=0xd7,umask=8  01     unc_m_sb_strv_alloc.nmrd_clr uncore memory Near Mem Read - Clear event=0xd7,umask=0x10  01     unc_m_sb_strv_alloc.nmrd_set uncore memory Near Mem Read - Set event=0xd7,umask=1  01     unc_m_sb_strv_alloc.nmwr_clr uncore memory Near Mem Write - Clear event=0xd7,umask=0x40  01     unc_m_sb_strv_alloc.nmwr_set uncore memory Near Mem Write - Set event=0xd7,umask=4  01     unc_m_sb_strv_occ.fmrd uncore memory Far Mem Read event=0xd8,umask=2  01     unc_m_sb_strv_occ.fmwr uncore memory Far Mem Write event=0xd8,umask=8  01     unc_m_sb_strv_occ.nmrd uncore memory Near Mem Read event=0xd8,umask=1  01     unc_m_sb_strv_occ.nmwr uncore memory Near Mem Write event=0xd8,umask=4  01     unc_m_sb_tagged.ddr4_cmp uncore memory UNC_M_SB_TAGGED.DDR4_CMP event=0xdd,umask=8  01     unc_m_sb_tagged.new uncore memory UNC_M_SB_TAGGED.NEW event=0xdd,umask=1  01     unc_m_sb_tagged.occ uncore memory UNC_M_SB_TAGGED.OCC event=0xdd,umask=0x80  01     unc_m_sb_tagged.pmm0_cmp uncore memory UNC_M_SB_TAGGED.PMM0_CMP event=0xdd,umask=0x10  01     unc_m_sb_tagged.pmm1_cmp uncore memory UNC_M_SB_TAGGED.PMM1_CMP event=0xdd,umask=0x20  01     unc_m_sb_tagged.pmm2_cmp uncore memory UNC_M_SB_TAGGED.PMM2_CMP event=0xdd,umask=0x40  01     unc_m_sb_tagged.rd_hit uncore memory UNC_M_SB_TAGGED.RD_HIT event=0xdd,umask=2  01     unc_m_sb_tagged.rd_miss uncore memory UNC_M_SB_TAGGED.RD_MISS event=0xdd,umask=4  01     unc_m_tagchk.hit uncore memory All hits to Near Memory(DRAM cache) in Memory Mode event=0xd3,umask=1  01    Tag Check; Hit unc_m_tagchk.miss_clean uncore memory All Clean line misses to Near Memory(DRAM cache) in Memory Mode event=0xd3,umask=2  01    Tag Check; Clean unc_m_tagchk.miss_dirty uncore memory All dirty line misses to Near Memory(DRAM cache) in Memory Mode event=0xd3,umask=4  01    Tag Check; Dirty unc_m_wpq_cycles_full uncore memory Write Pending Queue Full Cycles event=0x22  01    Counts the number of cycles when the Write Pending Queue is full.  When the WPQ is full, the HA will not be able to issue any additional write requests into the iMC.  This count should be similar count in the CHA which tracks the number of cycles that the CHA has no WPQ credits, just somewhat smaller to account for the credit return overhead unc_m_wpq_cycles_ne uncore memory Write Pending Queue Not Empty event=0x21  01    Counts the number of cycles that the Write Pending Queue is not empty.  This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies unc_m_wpq_inserts uncore memory Write Pending Queue Allocations event=0x20  01    Counts the number of writes requests allocated into the Write Pending Queue (WPQ).  The WPQ is used to schedule writes out to the memory controller and to track the requests.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (Memory Controller).  The write requests deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC unc_m_wpq_occupancy uncore memory Write Pending Queue Occupancy event=0x81  01    Counts the number of entries in the Write Pending Queue (WPQ) at each cycle.  This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The WPQ is used to schedule writes out to the memory controller and to track the requests.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (memory controller).  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.  So, we provide filtering based on if the request has posted or not.  By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA.  The 'posted' filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory.  High average occupancies will generally coincide with high write major mode counts unc_m_wr_cas_rank0.allbanks uncore memory WR_CAS Access to Rank 0; All Banks event=0xb8,umask=0x10  01     unc_m_wr_cas_rank0.bank0 uncore memory WR_CAS Access to Rank 0; Bank 0 event=0xb8  01     unc_m_wr_cas_rank0.bank1 uncore memory WR_CAS Access to Rank 0; Bank 1 event=0xb8,umask=1  01     unc_m_wr_cas_rank0.bank10 uncore memory WR_CAS Access to Rank 0; Bank 10 event=0xb8,umask=0xa  01     unc_m_wr_cas_rank0.bank11 uncore memory WR_CAS Access to Rank 0; Bank 11 event=0xb8,umask=0xb  01     unc_m_wr_cas_rank0.bank12 uncore memory WR_CAS Access to Rank 0; Bank 12 event=0xb8,umask=0xc  01     unc_m_wr_cas_rank0.bank13 uncore memory WR_CAS Access to Rank 0; Bank 13 event=0xb8,umask=0xd  01     unc_m_wr_cas_rank0.bank14 uncore memory WR_CAS Access to Rank 0; Bank 14 event=0xb8,umask=0xe  01     unc_m_wr_cas_rank0.bank15 uncore memory WR_CAS Access to Rank 0; Bank 15 event=0xb8,umask=0xf  01     unc_m_wr_cas_rank0.bank2 uncore memory WR_CAS Access to Rank 0; Bank 2 event=0xb8,umask=2  01     unc_m_wr_cas_rank0.bank3 uncore memory WR_CAS Access to Rank 0; Bank 3 event=0xb8,umask=3  01     unc_m_wr_cas_rank0.bank4 uncore memory WR_CAS Access to Rank 0; Bank 4 event=0xb8,umask=4  01     unc_m_wr_cas_rank0.bank5 uncore memory WR_CAS Access to Rank 0; Bank 5 event=0xb8,umask=5  01     unc_m_wr_cas_rank0.bank6 uncore memory WR_CAS Access to Rank 0; Bank 6 event=0xb8,umask=6  01     unc_m_wr_cas_rank0.bank7 uncore memory WR_CAS Access to Rank 0; Bank 7 event=0xb8,umask=7  01     unc_m_wr_cas_rank0.bank8 uncore memory WR_CAS Access to Rank 0; Bank 8 event=0xb8,umask=8  01     unc_m_wr_cas_rank0.bank9 uncore memory WR_CAS Access to Rank 0; Bank 9 event=0xb8,umask=9  01     unc_m_wr_cas_rank0.bankg0 uncore memory WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3) event=0xb8,umask=0x11  01     unc_m_wr_cas_rank0.bankg1 uncore memory WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7) event=0xb8,umask=0x12  01     unc_m_wr_cas_rank0.bankg2 uncore memory WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11) event=0xb8,umask=0x13  01     unc_m_wr_cas_rank0.bankg3 uncore memory WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15) event=0xb8,umask=0x14  01     unc_m_wr_cas_rank1.allbanks uncore memory WR_CAS Access to Rank 1; All Banks event=0xb9,umask=0x10  01     unc_m_wr_cas_rank1.bank0 uncore memory WR_CAS Access to Rank 1; Bank 0 event=0xb9  01     unc_m_wr_cas_rank1.bank1 uncore memory WR_CAS Access to Rank 1; Bank 1 event=0xb9,umask=1  01     unc_m_wr_cas_rank1.bank10 uncore memory WR_CAS Access to Rank 1; Bank 10 event=0xb9,umask=0xa  01     unc_m_wr_cas_rank1.bank11 uncore memory WR_CAS Access to Rank 1; Bank 11 event=0xb9,umask=0xb  01     unc_m_wr_cas_rank1.bank12 uncore memory WR_CAS Access to Rank 1; Bank 12 event=0xb9,umask=0xc  01     unc_m_wr_cas_rank1.bank13 uncore memory WR_CAS Access to Rank 1; Bank 13 event=0xb9,umask=0xd  01     unc_m_wr_cas_rank1.bank14 uncore memory WR_CAS Access to Rank 1; Bank 14 event=0xb9,umask=0xe  01     unc_m_wr_cas_rank1.bank15 uncore memory WR_CAS Access to Rank 1; Bank 15 event=0xb9,umask=0xf  01     unc_m_wr_cas_rank1.bank2 uncore memory WR_CAS Access to Rank 1; Bank 2 event=0xb9,umask=2  01     unc_m_wr_cas_rank1.bank3 uncore memory WR_CAS Access to Rank 1; Bank 3 event=0xb9,umask=3  01     unc_m_wr_cas_rank1.bank4 uncore memory WR_CAS Access to Rank 1; Bank 4 event=0xb9,umask=4  01     unc_m_wr_cas_rank1.bank5 uncore memory WR_CAS Access to Rank 1; Bank 5 event=0xb9,umask=5  01     unc_m_wr_cas_rank1.bank6 uncore memory WR_CAS Access to Rank 1; Bank 6 event=0xb9,umask=6  01     unc_m_wr_cas_rank1.bank7 uncore memory WR_CAS Access to Rank 1; Bank 7 event=0xb9,umask=7  01     unc_m_wr_cas_rank1.bank8 uncore memory WR_CAS Access to Rank 1; Bank 8 event=0xb9,umask=8  01     unc_m_wr_cas_rank1.bank9 uncore memory WR_CAS Access to Rank 1; Bank 9 event=0xb9,umask=9  01     unc_m_wr_cas_rank1.bankg0 uncore memory WR_CAS Access to Rank 1; Bank Group 0 (Banks 0-3) event=0xb9,umask=0x11  01     unc_m_wr_cas_rank1.bankg1 uncore memory WR_CAS Access to Rank 1; Bank Group 1 (Banks 4-7) event=0xb9,umask=0x12  01     unc_m_wr_cas_rank1.bankg2 uncore memory WR_CAS Access to Rank 1; Bank Group 2 (Banks 8-11) event=0xb9,umask=0x13  01     unc_m_wr_cas_rank1.bankg3 uncore memory WR_CAS Access to Rank 1; Bank Group 3 (Banks 12-15) event=0xb9,umask=0x14  01     unc_m_wr_cas_rank2.allbanks uncore memory WR_CAS Access to Rank 2; All Banks event=0xba,umask=0x10  01     unc_m_wr_cas_rank2.bank0 uncore memory WR_CAS Access to Rank 2; Bank 0 event=0xba  01     unc_m_wr_cas_rank2.bank1 uncore memory WR_CAS Access to Rank 2; Bank 1 event=0xba,umask=1  01     unc_m_wr_cas_rank2.bank10 uncore memory WR_CAS Access to Rank 2; Bank 10 event=0xba,umask=0xa  01     unc_m_wr_cas_rank2.bank11 uncore memory WR_CAS Access to Rank 2; Bank 11 event=0xba,umask=0xb  01     unc_m_wr_cas_rank2.bank12 uncore memory WR_CAS Access to Rank 2; Bank 12 event=0xba,umask=0xc  01     unc_m_wr_cas_rank2.bank13 uncore memory WR_CAS Access to Rank 2; Bank 13 event=0xba,umask=0xd  01     unc_m_wr_cas_rank2.bank14 uncore memory WR_CAS Access to Rank 2; Bank 14 event=0xba,umask=0xe  01     unc_m_wr_cas_rank2.bank15 uncore memory WR_CAS Access to Rank 2; Bank 15 event=0xba,umask=0xf  01     unc_m_wr_cas_rank2.bank2 uncore memory WR_CAS Access to Rank 2; Bank 2 event=0xba,umask=2  01     unc_m_wr_cas_rank2.bank3 uncore memory WR_CAS Access to Rank 2; Bank 3 event=0xba,umask=3  01     unc_m_wr_cas_rank2.bank4 uncore memory WR_CAS Access to Rank 2; Bank 4 event=0xba,umask=4  01     unc_m_wr_cas_rank2.bank5 uncore memory WR_CAS Access to Rank 2; Bank 5 event=0xba,umask=5  01     unc_m_wr_cas_rank2.bank6 uncore memory WR_CAS Access to Rank 2; Bank 6 event=0xba,umask=6  01     unc_m_wr_cas_rank2.bank7 uncore memory WR_CAS Access to Rank 2; Bank 7 event=0xba,umask=7  01     unc_m_wr_cas_rank2.bank8 uncore memory WR_CAS Access to Rank 2; Bank 8 event=0xba,umask=8  01     unc_m_wr_cas_rank2.bank9 uncore memory WR_CAS Access to Rank 2; Bank 9 event=0xba,umask=9  01     unc_m_wr_cas_rank2.bankg0 uncore memory WR_CAS Access to Rank 2; Bank Group 0 (Banks 0-3) event=0xba,umask=0x11  01     unc_m_wr_cas_rank2.bankg1 uncore memory WR_CAS Access to Rank 2; Bank Group 1 (Banks 4-7) event=0xba,umask=0x12  01     unc_m_wr_cas_rank2.bankg2 uncore memory WR_CAS Access to Rank 2; Bank Group 2 (Banks 8-11) event=0xba,umask=0x13  01     unc_m_wr_cas_rank2.bankg3 uncore memory WR_CAS Access to Rank 2; Bank Group 3 (Banks 12-15) event=0xba,umask=0x14  01     unc_m_wr_cas_rank3.allbanks uncore memory WR_CAS Access to Rank 3; All Banks event=0xbb,umask=0x10  01     unc_m_wr_cas_rank3.bank0 uncore memory WR_CAS Access to Rank 3; Bank 0 event=0xbb  01     unc_m_wr_cas_rank3.bank1 uncore memory WR_CAS Access to Rank 3; Bank 1 event=0xbb,umask=1  01     unc_m_wr_cas_rank3.bank10 uncore memory WR_CAS Access to Rank 3; Bank 10 event=0xbb,umask=0xa  01     unc_m_wr_cas_rank3.bank11 uncore memory WR_CAS Access to Rank 3; Bank 11 event=0xbb,umask=0xb  01     unc_m_wr_cas_rank3.bank12 uncore memory WR_CAS Access to Rank 3; Bank 12 event=0xbb,umask=0xc  01     unc_m_wr_cas_rank3.bank13 uncore memory WR_CAS Access to Rank 3; Bank 13 event=0xbb,umask=0xd  01     unc_m_wr_cas_rank3.bank14 uncore memory WR_CAS Access to Rank 3; Bank 14 event=0xbb,umask=0xe  01     unc_m_wr_cas_rank3.bank15 uncore memory WR_CAS Access to Rank 3; Bank 15 event=0xbb,umask=0xf  01     unc_m_wr_cas_rank3.bank2 uncore memory WR_CAS Access to Rank 3; Bank 2 event=0xbb,umask=2  01     unc_m_wr_cas_rank3.bank3 uncore memory WR_CAS Access to Rank 3; Bank 3 event=0xbb,umask=3  01     unc_m_wr_cas_rank3.bank4 uncore memory WR_CAS Access to Rank 3; Bank 4 event=0xbb,umask=4  01     unc_m_wr_cas_rank3.bank5 uncore memory WR_CAS Access to Rank 3; Bank 5 event=0xbb,umask=5  01     unc_m_wr_cas_rank3.bank6 uncore memory WR_CAS Access to Rank 3; Bank 6 event=0xbb,umask=6  01     unc_m_wr_cas_rank3.bank7 uncore memory WR_CAS Access to Rank 3; Bank 7 event=0xbb,umask=7  01     unc_m_wr_cas_rank3.bank8 uncore memory WR_CAS Access to Rank 3; Bank 8 event=0xbb,umask=8  01     unc_m_wr_cas_rank3.bank9 uncore memory WR_CAS Access to Rank 3; Bank 9 event=0xbb,umask=9  01     unc_m_wr_cas_rank3.bankg0 uncore memory WR_CAS Access to Rank 3; Bank Group 0 (Banks 0-3) event=0xbb,umask=0x11  01     unc_m_wr_cas_rank3.bankg1 uncore memory WR_CAS Access to Rank 3; Bank Group 1 (Banks 4-7) event=0xbb,umask=0x12  01     unc_m_wr_cas_rank3.bankg2 uncore memory WR_CAS Access to Rank 3; Bank Group 2 (Banks 8-11) event=0xbb,umask=0x13  01     unc_m_wr_cas_rank3.bankg3 uncore memory WR_CAS Access to Rank 3; Bank Group 3 (Banks 12-15) event=0xbb,umask=0x14  01     unc_m_wr_cas_rank4.allbanks uncore memory WR_CAS Access to Rank 4; All Banks event=0xbc,umask=0x10  01     unc_m_wr_cas_rank4.bank0 uncore memory WR_CAS Access to Rank 4; Bank 0 event=0xbc  01     unc_m_wr_cas_rank4.bank1 uncore memory WR_CAS Access to Rank 4; Bank 1 event=0xbc,umask=1  01     unc_m_wr_cas_rank4.bank10 uncore memory WR_CAS Access to Rank 4; Bank 10 event=0xbc,umask=0xa  01     unc_m_wr_cas_rank4.bank11 uncore memory WR_CAS Access to Rank 4; Bank 11 event=0xbc,umask=0xb  01     unc_m_wr_cas_rank4.bank12 uncore memory WR_CAS Access to Rank 4; Bank 12 event=0xbc,umask=0xc  01     unc_m_wr_cas_rank4.bank13 uncore memory WR_CAS Access to Rank 4; Bank 13 event=0xbc,umask=0xd  01     unc_m_wr_cas_rank4.bank14 uncore memory WR_CAS Access to Rank 4; Bank 14 event=0xbc,umask=0xe  01     unc_m_wr_cas_rank4.bank15 uncore memory WR_CAS Access to Rank 4; Bank 15 event=0xbc,umask=0xf  01     unc_m_wr_cas_rank4.bank2 uncore memory WR_CAS Access to Rank 4; Bank 2 event=0xbc,umask=2  01     unc_m_wr_cas_rank4.bank3 uncore memory WR_CAS Access to Rank 4; Bank 3 event=0xbc,umask=3  01     unc_m_wr_cas_rank4.bank4 uncore memory WR_CAS Access to Rank 4; Bank 4 event=0xbc,umask=4  01     unc_m_wr_cas_rank4.bank5 uncore memory WR_CAS Access to Rank 4; Bank 5 event=0xbc,umask=5  01     unc_m_wr_cas_rank4.bank6 uncore memory WR_CAS Access to Rank 4; Bank 6 event=0xbc,umask=6  01     unc_m_wr_cas_rank4.bank7 uncore memory WR_CAS Access to Rank 4; Bank 7 event=0xbc,umask=7  01     unc_m_wr_cas_rank4.bank8 uncore memory WR_CAS Access to Rank 4; Bank 8 event=0xbc,umask=8  01     unc_m_wr_cas_rank4.bank9 uncore memory WR_CAS Access to Rank 4; Bank 9 event=0xbc,umask=9  01     unc_m_wr_cas_rank4.bankg0 uncore memory WR_CAS Access to Rank 4; Bank Group 0 (Banks 0-3) event=0xbc,umask=0x11  01     unc_m_wr_cas_rank4.bankg1 uncore memory WR_CAS Access to Rank 4; Bank Group 1 (Banks 4-7) event=0xbc,umask=0x12  01     unc_m_wr_cas_rank4.bankg2 uncore memory WR_CAS Access to Rank 4; Bank Group 2 (Banks 8-11) event=0xbc,umask=0x13  01     unc_m_wr_cas_rank4.bankg3 uncore memory WR_CAS Access to Rank 4; Bank Group 3 (Banks 12-15) event=0xbc,umask=0x14  01     unc_m_wr_cas_rank5.allbanks uncore memory WR_CAS Access to Rank 5; All Banks event=0xbd,umask=0x10  01     unc_m_wr_cas_rank5.bank0 uncore memory WR_CAS Access to Rank 5; Bank 0 event=0xbd  01     unc_m_wr_cas_rank5.bank1 uncore memory WR_CAS Access to Rank 5; Bank 1 event=0xbd,umask=1  01     unc_m_wr_cas_rank5.bank10 uncore memory WR_CAS Access to Rank 5; Bank 10 event=0xbd,umask=0xa  01     unc_m_wr_cas_rank5.bank11 uncore memory WR_CAS Access to Rank 5; Bank 11 event=0xbd,umask=0xb  01     unc_m_wr_cas_rank5.bank12 uncore memory WR_CAS Access to Rank 5; Bank 12 event=0xbd,umask=0xc  01     unc_m_wr_cas_rank5.bank13 uncore memory WR_CAS Access to Rank 5; Bank 13 event=0xbd,umask=0xd  01     unc_m_wr_cas_rank5.bank14 uncore memory WR_CAS Access to Rank 5; Bank 14 event=0xbd,umask=0xe  01     unc_m_wr_cas_rank5.bank15 uncore memory WR_CAS Access to Rank 5; Bank 15 event=0xbd,umask=0xf  01     unc_m_wr_cas_rank5.bank2 uncore memory WR_CAS Access to Rank 5; Bank 2 event=0xbd,umask=2  01     unc_m_wr_cas_rank5.bank3 uncore memory WR_CAS Access to Rank 5; Bank 3 event=0xbd,umask=3  01     unc_m_wr_cas_rank5.bank4 uncore memory WR_CAS Access to Rank 5; Bank 4 event=0xbd,umask=4  01     unc_m_wr_cas_rank5.bank5 uncore memory WR_CAS Access to Rank 5; Bank 5 event=0xbd,umask=5  01     unc_m_wr_cas_rank5.bank6 uncore memory WR_CAS Access to Rank 5; Bank 6 event=0xbd,umask=6  01     unc_m_wr_cas_rank5.bank7 uncore memory WR_CAS Access to Rank 5; Bank 7 event=0xbd,umask=7  01     unc_m_wr_cas_rank5.bank8 uncore memory WR_CAS Access to Rank 5; Bank 8 event=0xbd,umask=8  01     unc_m_wr_cas_rank5.bank9 uncore memory WR_CAS Access to Rank 5; Bank 9 event=0xbd,umask=9  01     unc_m_wr_cas_rank5.bankg0 uncore memory WR_CAS Access to Rank 5; Bank Group 0 (Banks 0-3) event=0xbd,umask=0x11  01     unc_m_wr_cas_rank5.bankg1 uncore memory WR_CAS Access to Rank 5; Bank Group 1 (Banks 4-7) event=0xbd,umask=0x12  01     unc_m_wr_cas_rank5.bankg2 uncore memory WR_CAS Access to Rank 5; Bank Group 2 (Banks 8-11) event=0xbd,umask=0x13  01     unc_m_wr_cas_rank5.bankg3 uncore memory WR_CAS Access to Rank 5; Bank Group 3 (Banks 12-15) event=0xbd,umask=0x14  01     unc_m_wr_cas_rank6.allbanks uncore memory WR_CAS Access to Rank 6; All Banks event=0xbe,umask=0x10  01     unc_m_wr_cas_rank6.bank0 uncore memory WR_CAS Access to Rank 6; Bank 0 event=0xbe  01     unc_m_wr_cas_rank6.bank1 uncore memory WR_CAS Access to Rank 6; Bank 1 event=0xbe,umask=1  01     unc_m_wr_cas_rank6.bank10 uncore memory WR_CAS Access to Rank 6; Bank 10 event=0xbe,umask=0xa  01     unc_m_wr_cas_rank6.bank11 uncore memory WR_CAS Access to Rank 6; Bank 11 event=0xbe,umask=0xb  01     unc_m_wr_cas_rank6.bank12 uncore memory WR_CAS Access to Rank 6; Bank 12 event=0xbe,umask=0xc  01     unc_m_wr_cas_rank6.bank13 uncore memory WR_CAS Access to Rank 6; Bank 13 event=0xbe,umask=0xd  01     unc_m_wr_cas_rank6.bank14 uncore memory WR_CAS Access to Rank 6; Bank 14 event=0xbe,umask=0xe  01     unc_m_wr_cas_rank6.bank15 uncore memory WR_CAS Access to Rank 6; Bank 15 event=0xbe,umask=0xf  01     unc_m_wr_cas_rank6.bank2 uncore memory WR_CAS Access to Rank 6; Bank 2 event=0xbe,umask=2  01     unc_m_wr_cas_rank6.bank3 uncore memory WR_CAS Access to Rank 6; Bank 3 event=0xbe,umask=3  01     unc_m_wr_cas_rank6.bank4 uncore memory WR_CAS Access to Rank 6; Bank 4 event=0xbe,umask=4  01     unc_m_wr_cas_rank6.bank5 uncore memory WR_CAS Access to Rank 6; Bank 5 event=0xbe,umask=5  01     unc_m_wr_cas_rank6.bank6 uncore memory WR_CAS Access to Rank 6; Bank 6 event=0xbe,umask=6  01     unc_m_wr_cas_rank6.bank7 uncore memory WR_CAS Access to Rank 6; Bank 7 event=0xbe,umask=7  01     unc_m_wr_cas_rank6.bank8 uncore memory WR_CAS Access to Rank 6; Bank 8 event=0xbe,umask=8  01     unc_m_wr_cas_rank6.bank9 uncore memory WR_CAS Access to Rank 6; Bank 9 event=0xbe,umask=9  01     unc_m_wr_cas_rank6.bankg0 uncore memory WR_CAS Access to Rank 6; Bank Group 0 (Banks 0-3) event=0xbe,umask=0x11  01     unc_m_wr_cas_rank6.bankg1 uncore memory WR_CAS Access to Rank 6; Bank Group 1 (Banks 4-7) event=0xbe,umask=0x12  01     unc_m_wr_cas_rank6.bankg2 uncore memory WR_CAS Access to Rank 6; Bank Group 2 (Banks 8-11) event=0xbe,umask=0x13  01     unc_m_wr_cas_rank6.bankg3 uncore memory WR_CAS Access to Rank 6; Bank Group 3 (Banks 12-15) event=0xbe,umask=0x14  01     unc_m_wr_cas_rank7.allbanks uncore memory WR_CAS Access to Rank 7; All Banks event=0xbf,umask=0x10  01     unc_m_wr_cas_rank7.bank0 uncore memory WR_CAS Access to Rank 7; Bank 0 event=0xbf  01     unc_m_wr_cas_rank7.bank1 uncore memory WR_CAS Access to Rank 7; Bank 1 event=0xbf,umask=1  01     unc_m_wr_cas_rank7.bank10 uncore memory WR_CAS Access to Rank 7; Bank 10 event=0xbf,umask=0xa  01     unc_m_wr_cas_rank7.bank11 uncore memory WR_CAS Access to Rank 7; Bank 11 event=0xbf,umask=0xb  01     unc_m_wr_cas_rank7.bank12 uncore memory WR_CAS Access to Rank 7; Bank 12 event=0xbf,umask=0xc  01     unc_m_wr_cas_rank7.bank13 uncore memory WR_CAS Access to Rank 7; Bank 13 event=0xbf,umask=0xd  01     unc_m_wr_cas_rank7.bank14 uncore memory WR_CAS Access to Rank 7; Bank 14 event=0xbf,umask=0xe  01     unc_m_wr_cas_rank7.bank15 uncore memory WR_CAS Access to Rank 7; Bank 15 event=0xbf,umask=0xf  01     unc_m_wr_cas_rank7.bank2 uncore memory WR_CAS Access to Rank 7; Bank 2 event=0xbf,umask=2  01     unc_m_wr_cas_rank7.bank3 uncore memory WR_CAS Access to Rank 7; Bank 3 event=0xbf,umask=3  01     unc_m_wr_cas_rank7.bank4 uncore memory WR_CAS Access to Rank 7; Bank 4 event=0xbf,umask=4  01     unc_m_wr_cas_rank7.bank5 uncore memory WR_CAS Access to Rank 7; Bank 5 event=0xbf,umask=5  01     unc_m_wr_cas_rank7.bank6 uncore memory WR_CAS Access to Rank 7; Bank 6 event=0xbf,umask=6  01     unc_m_wr_cas_rank7.bank7 uncore memory WR_CAS Access to Rank 7; Bank 7 event=0xbf,umask=7  01     unc_m_wr_cas_rank7.bank8 uncore memory WR_CAS Access to Rank 7; Bank 8 event=0xbf,umask=8  01     unc_m_wr_cas_rank7.bank9 uncore memory WR_CAS Access to Rank 7; Bank 9 event=0xbf,umask=9  01     unc_m_wr_cas_rank7.bankg0 uncore memory WR_CAS Access to Rank 7; Bank Group 0 (Banks 0-3) event=0xbf,umask=0x11  01     unc_m_wr_cas_rank7.bankg1 uncore memory WR_CAS Access to Rank 7; Bank Group 1 (Banks 4-7) event=0xbf,umask=0x12  01     unc_m_wr_cas_rank7.bankg2 uncore memory WR_CAS Access to Rank 7; Bank Group 2 (Banks 8-11) event=0xbf,umask=0x13  01     unc_m_wr_cas_rank7.bankg3 uncore memory WR_CAS Access to Rank 7; Bank Group 3 (Banks 12-15) event=0xbf,umask=0x14  01     unc_p_core_transition_cycles uncore power UNC_P_CORE_TRANSITION_CYCLES event=0x60  01     unc_p_demotions uncore power UNC_P_DEMOTIONS event=0x30  01     unc_p_fivr_ps_ps0_cycles uncore power Phase Shed 0 Cycles event=0x75  01    Cycles spent in phase-shedding power state 0 unc_p_fivr_ps_ps1_cycles uncore power Phase Shed 1 Cycles event=0x76  01    Cycles spent in phase-shedding power state 1 unc_p_fivr_ps_ps2_cycles uncore power Phase Shed 2 Cycles event=0x77  01    Cycles spent in phase-shedding power state 2 unc_p_fivr_ps_ps3_cycles uncore power Phase Shed 3 Cycles event=0x78  01    Cycles spent in phase-shedding power state 3 unc_p_mcp_prochot_cycles uncore power UNC_P_MCP_PROCHOT_CYCLES event=6  01     unc_p_pmax_throttled_cycles uncore power UNC_P_PMAX_THROTTLED_CYCLES event=7  01     unc_p_power_state_occupancy.cores_c0 uncore power Number of cores in C-State; C0 and C1 event=0x80,umask=0x40  01    This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_power_state_occupancy.cores_c3 uncore power Number of cores in C-State; C3 event=0x80,umask=0x80  01    This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_power_state_occupancy.cores_c6 uncore power Number of cores in C-State; C6 and C7 event=0x80,umask=0xc0  01    This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_vr_hot_cycles uncore power VR Hot event=0x42  01     dtlb_load_misses.miss_causes_a_walk virtual memory Load misses in all DTLB levels that cause page walks event=8,period=100003,umask=1  00    Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed dtlb_load_misses.stlb_hit virtual memory Loads that miss the DTLB and hit the STLB event=8,period=2000003,umask=0x20  00    Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB) dtlb_load_misses.walk_active virtual memory Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake event=8,cmask=1,period=100003,umask=0x10  00    Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load dtlb_load_misses.walk_completed virtual memory Load miss in all TLB levels causes a page walk that completes. (All page sizes) event=8,period=100003,umask=0xe  00    Counts completed page walks  (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_load_misses.walk_completed_1g virtual memory Page walk completed due to a demand data load to a 1G page event=8,period=2000003,umask=8  00    Counts completed page walks  (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_load_misses.walk_completed_2m_4m virtual memory Page walk completed due to a demand data load to a 2M/4M page event=8,period=2000003,umask=4  00    Counts completed page walks  (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_load_misses.walk_completed_4k virtual memory Page walk completed due to a demand data load to a 4K page event=8,period=2000003,umask=2  00    Counts completed page walks  (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_load_misses.walk_pending virtual memory Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake event=8,period=2000003,umask=0x10  00    Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake microarchitecture dtlb_store_misses.miss_causes_a_walk virtual memory Store misses in all DTLB levels that cause page walks event=0x49,period=100003,umask=1  00    Counts demand data stores that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed dtlb_store_misses.stlb_hit virtual memory Stores that miss the DTLB and hit the STLB event=0x49,period=100003,umask=0x20  00    Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB) dtlb_store_misses.walk_active virtual memory Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake event=0x49,cmask=1,period=100003,umask=0x10  00    Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store dtlb_store_misses.walk_completed virtual memory Store misses in all TLB levels causes a page walk that completes. (All page sizes) event=0x49,period=100003,umask=0xe  00    Counts completed page walks  (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_completed_1g virtual memory Page walk completed due to a demand data store to a 1G page event=0x49,period=100003,umask=8  00    Counts completed page walks  (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_completed_2m_4m virtual memory Page walk completed due to a demand data store to a 2M/4M page event=0x49,period=100003,umask=4  00    Counts completed page walks  (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_completed_4k virtual memory Page walk completed due to a demand data store to a 4K page event=0x49,period=100003,umask=2  00    Counts completed page walks  (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_pending virtual memory Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake event=0x49,period=2000003,umask=0x10  00    Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitecture ept.walk_pending virtual memory Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type event=0x4f,period=2000003,umask=0x10  00    Counts cycles for each PMH (Page Miss Handler) that is busy with an EPT (Extended Page Table) walk for any request type itlb.itlb_flush virtual memory Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages event=0xae,period=100007,umask=1  00    Counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific) itlb_misses.miss_causes_a_walk virtual memory Misses at all ITLB levels that cause page walks event=0x85,period=100003,umask=1  00    Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB, but the walk need not have completed itlb_misses.stlb_hit virtual memory Instruction fetch requests that miss the ITLB and hit the STLB event=0x85,period=100003,umask=0x20  00     itlb_misses.walk_active virtual memory Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake event=0x85,cmask=1,period=100003,umask=0x10  00    Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake microarchitecture itlb_misses.walk_completed virtual memory Code miss in all TLB levels causes a page walk that completes. (All page sizes) event=0x85,period=100003,umask=0xe  00    Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault itlb_misses.walk_completed_1g virtual memory Code miss in all TLB levels causes a page walk that completes. (1G) event=0x85,period=100003,umask=8  00    Counts completed page walks (1G page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault itlb_misses.walk_completed_2m_4m virtual memory Code miss in all TLB levels causes a page walk that completes. (2M/4M) event=0x85,period=100003,umask=4  00    Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault itlb_misses.walk_completed_4k virtual memory Code miss in all TLB levels causes a page walk that completes. (4K) event=0x85,period=100003,umask=2  00    Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault itlb_misses.walk_pending virtual memory Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake event=0x85,period=100003,umask=0x10  00    Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake microarchitecture tlb_flush.dtlb_thread virtual memory DTLB flush attempts of the thread-specific entries event=0xbd,period=100007,umask=1  00    Counts the number of DTLB flush attempts of the thread-specific entries tlb_flush.stlb_any virtual memory STLB flush attempts event=0xbd,period=100007,umask=0x20  00    Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.) longest_lat_cache.miss cache Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis event=0x2e,period=1000003,umask=0x41  00    Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis longest_lat_cache.reference cache Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis event=0x2e,period=1000003,umask=0x4f  00    Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis mem_uops_retired.all_loads cache Counts the number of load ops retired event=0xd0,period=1000003,umask=0x81  00    Counts the number of load ops retired. Available PDIST counters: 0,1 mem_uops_retired.all_stores cache Counts the number of store ops retired event=0xd0,period=1000003,umask=0x82  00    Counts the number of store ops retired. Available PDIST counters: 0,1 mem_uops_retired.load_latency_gt_1024 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled event=0xd0,period=1000003,umask=5,ldlat=0x400  00    Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: 0,1 mem_uops_retired.load_latency_gt_128 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled event=0xd0,period=1000003,umask=5,ldlat=0x80  00    Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: 0,1 mem_uops_retired.load_latency_gt_16 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled event=0xd0,period=1000003,umask=5,ldlat=0x10  00    Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: 0,1 mem_uops_retired.load_latency_gt_2048 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled event=0xd0,period=1000003,umask=5,ldlat=0x800  00    Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: 0,1 mem_uops_retired.load_latency_gt_256 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled event=0xd0,period=1000003,umask=5,ldlat=0x100  00    Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: 0,1 mem_uops_retired.load_latency_gt_32 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled event=0xd0,period=1000003,umask=5,ldlat=0x20  00    Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: 0,1 mem_uops_retired.load_latency_gt_4 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled event=0xd0,period=1000003,umask=5,ldlat=0x4  00    Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: 0,1 mem_uops_retired.load_latency_gt_512 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled event=0xd0,period=1000003,umask=5,ldlat=0x200  00    Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: 0,1 mem_uops_retired.load_latency_gt_64 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled event=0xd0,period=1000003,umask=5,ldlat=0x40  00    Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: 0,1 mem_uops_retired.load_latency_gt_8 cache Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled event=0xd0,period=1000003,umask=5,ldlat=0x8  00    Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: 0,1 mem_uops_retired.store_latency cache Counts the number of  stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES event=0xd0,period=1000003,umask=6  00    Counts the number of  stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES Available PDIST counters: 0,1 ocr.demand_rfo.any_response cache Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10002  00    Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response. Available PDIST counters: 0 icache.accesses frontend Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump event=0x80,period=1000003,umask=3  00     icache.misses frontend Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. - event=0x80,period=1000003,umask=2  00     ocr.demand_data_rd.l3_miss memory Counts demand data reads that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x33FBFC00001  00    Counts demand data reads that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.demand_rfo.l3_miss memory Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x33FBFC00002  00    Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. Available PDIST counters: 0 br_inst_retired.all_branches pipeline Counts the total number of branch instructions retired for all branch types event=0xc4,period=1000003  00    Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires.  All branch type instructions are accounted for. Available PDIST counters: 0,1 br_misp_retired.all_branches pipeline Counts the total number of mispredicted branch instructions retired for all branch types event=0xc5,period=1000003  00    Counts the total number of mispredicted branch instructions retired.  All branch type instructions are accounted for.  Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP.    A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path. Available PDIST counters: 0,1 cpu_clk_unhalted.core_p pipeline Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD_P] event=0x3c,period=1000003  00     cpu_clk_unhalted.ref_tsc pipeline Fixed Counter: Counts the number of unhalted reference clock cycles event=0,period=1000003,umask=3  00     cpu_clk_unhalted.ref_tsc_p pipeline Counts the number of unhalted reference clock cycles at TSC frequency event=0x3c,period=1000003,umask=1  00    Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter cpu_clk_unhalted.thread_p pipeline Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE_P] event=0x3c,period=1000003  00     inst_retired.any_p pipeline Counts the number of instructions retired event=0xc0,period=2000003  00    Counts the number of instructions retired. Available PDIST counters: 0,1 topdown_bad_speculation.all pipeline Fixed Counter: Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear event=0,period=1000003,umask=5  00     topdown_be_bound.all pipeline Counts the number of retirement slots not consumed due to backend stalls. [This event is alias to TOPDOWN_BE_BOUND.ALL_P] event=0xa4,period=1000003,umask=2  00     topdown_be_bound.all_p pipeline Counts the number of retirement slots not consumed due to backend stalls. [This event is alias to TOPDOWN_BE_BOUND.ALL] event=0xa4,period=1000003,umask=2  00     dtlb_load_misses.walk_completed virtual memory Counts the number of page walks completed due to load DTLB misses to any page size event=8,period=1000003,umask=0xe  00    Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault dtlb_store_misses.walk_completed virtual memory Counts the number of page walks completed due to store DTLB misses to any page size event=0x49,period=1000003,umask=0xe  00    Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size.  Includes page walks that page fault itlb_misses.walk_completed virtual memory Counts the number of page walks completed due to instruction fetch misses to any page size event=0x85,period=1000003,umask=0xe  00    Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size.  Includes page walks that page fault core_reject_l2q.any cache Counts the number of core requests (demand and L1 prefetchers) rejected by the L2 queue (L2Q) due to a full condition event=0x31,period=200003  00    Counts the number of (demand and L1 prefetchers) core requests rejected by the L2 queue (L2Q) due to a full or nearly full condition, which likely indicates back pressure from L2Q.  It also counts requests that would have gone directly to the External Queue (XQ), but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link.  The L2Q may also reject transactions  from a core to ensure fairness between cores, or to delay a cores dirty eviction when the address conflicts incoming external snoops.  (Note that L2 prefetcher requests that are dropped are not counted by this event).  Counts on a per core basis l2_reject_xq.any cache Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition event=0x30,period=200003  00    Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition which likely indicates back pressure from the IDI link.  The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 write-back victims) l2_request.rejects cache Counts the number of L2 Cache accesses that miss the L2 and get rejected. Counts on a per core basis event=0x24,period=200003,umask=4  00    Counts the number of L2 Cache accesses that miss the L2 and get BBL reject  short and long rejects (includes those counted in L2_reject_XQ.any). Counts on a per core basis longest_lat_cache.miss cache Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis event=0x2e,period=200003,umask=0x41  00    Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis longest_lat_cache.reference cache Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis event=0x2e,period=200003,umask=0x4f  00    Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis mem_bound_stalls.store_buffer_full cache Counts the number of cycles the core is stalled due to a store buffer being full event=0x34,period=200003,umask=0x40  00     mem_load_uops_retired.dram_hit cache Counts the number of load uops retired that hit in DRAM  Supports address when precise (Precise event) event=0xd1,period=200003,umask=0x80  00    Counts the number of load uops retired that hit in DRAM. Available PDIST counters: 0  Supports address when precise (Precise event) mem_load_uops_retired.hitm cache Counts the number of load uops retired that hit in the L3 cache, in which a snoop was required and modified data was forwarded from another core or module  Supports address when precise (Precise event) event=0xd1,period=200003,umask=0x20  00    Counts the number of load uops retired that hit in the L3 cache, in which a snoop was required and modified data was forwarded from another core or module. Available PDIST counters: 0  Supports address when precise (Precise event) mem_load_uops_retired.l1_hit cache Counts the number of load uops retired that hit in the L1 data cache  Supports address when precise (Precise event) event=0xd1,period=200003,umask=1  00    Counts the number of load uops retired that hit in the L1 data cache. Available PDIST counters: 0  Supports address when precise (Precise event) mem_load_uops_retired.l1_miss cache Counts the number of load uops retired that miss in the L1 data cache  Supports address when precise (Precise event) event=0xd1,period=200003,umask=8  00    Counts the number of load uops retired that miss in the L1 data cache. Available PDIST counters: 0  Supports address when precise (Precise event) mem_load_uops_retired.l2_hit cache Counts the number of load uops retired that hit in the L2 cache  Supports address when precise (Precise event) event=0xd1,period=200003,umask=2  00    Counts the number of load uops retired that hit in the L2 cache. Available PDIST counters: 0  Supports address when precise (Precise event) mem_load_uops_retired.l2_miss cache Counts the number of load uops retired that miss in the L2 cache  Supports address when precise (Precise event) event=0xd1,period=200003,umask=0x10  00    Counts the number of load uops retired that miss in the L2 cache. Available PDIST counters: 0  Supports address when precise (Precise event) mem_load_uops_retired.l3_hit cache Counts the number of load uops retired that hit in the L3 cache  Supports address when precise (Precise event) event=0xd1,period=200003,umask=4  00    Counts the number of load uops retired that hit in the L3 cache. Available PDIST counters: 0  Supports address when precise (Precise event) mem_uops_retired.all cache Counts the number of memory uops retired  Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x83  00    Counts the number of memory uops retired.  A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST) Available PDIST counters: 0  Supports address when precise (Precise event) mem_uops_retired.all_loads cache Counts the number of load uops retired  Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x81  00    Counts the total number of load uops retired. Available PDIST counters: 0  Supports address when precise (Precise event) mem_uops_retired.all_stores cache Counts the number of store uops retired  Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x82  00    Counts the total number of store uops retired. Available PDIST counters: 0  Supports address when precise (Precise event) mem_uops_retired.lock_loads cache Counts the number of load uops retired that performed one or more locks  Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x21  00    Counts the number of load uops retired that performed one or more locks. Available PDIST counters: 0  Supports address when precise (Precise event) mem_uops_retired.split cache Counts the number of memory uops retired that were splits  Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x43  00    Counts the number of memory uops retired that were splits. Available PDIST counters: 0  Supports address when precise (Precise event) mem_uops_retired.split_loads cache Counts the number of retired split load uops  Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x41  00    Counts the number of retired split load uops. Available PDIST counters: 0  Supports address when precise (Precise event) mem_uops_retired.split_stores cache Counts the number of retired split store uops  Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x42  00    Counts the number of retired split store uops. Available PDIST counters: 0  Supports address when precise (Precise event) ocr.all_code_rd.l3_hit cache Counts all code reads that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x1F803C0044  00    Counts all code reads that were supplied by the L3 cache. Available PDIST counters: 0 ocr.all_code_rd.l3_hit.snoop_hitm cache Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0044  00    Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. Available PDIST counters: 0 ocr.all_code_rd.l3_hit.snoop_hit_no_fwd cache Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0044  00    Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. Available PDIST counters: 0 ocr.all_code_rd.l3_hit.snoop_hit_with_fwd cache Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0044  00    Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. Available PDIST counters: 0 ocr.all_code_rd.l3_hit.snoop_miss cache Counts all code reads that were supplied by the L3 cache where a snoop was sent but the snoop missed event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0044  00    Counts all code reads that were supplied by the L3 cache where a snoop was sent but the snoop missed. Available PDIST counters: 0 ocr.all_code_rd.l3_hit.snoop_not_needed cache Counts all code reads that were supplied by the L3 cache where no snoop was needed to satisfy the request event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0044  00    Counts all code reads that were supplied by the L3 cache where no snoop was needed to satisfy the request. Available PDIST counters: 0 ocr.corewb_m.any_response cache Counts modified writebacks from L1 cache and L2 cache that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x3000000010000  00    Counts modified writebacks from L1 cache and L2 cache that have any type of response. Available PDIST counters: 0 ocr.corewb_m.l3_hit cache Counts modified writebacks from L1 cache and L2 cache that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3001F803C0000  00    Counts modified writebacks from L1 cache and L2 cache that were supplied by the L3 cache. Available PDIST counters: 0 ocr.corewb_m.outstanding cache Counts modified writebacks from L1 cache and L2 cache that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency) event=0xb7,period=100003,umask=1,offcore_rsp=0x8003000000000000  00    Counts modified writebacks from L1 cache and L2 cache that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency). Available PDIST counters: 0 ocr.demand_code_rd.l3_hit.snoop_miss cache Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent but the snoop missed event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0004  00    Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent but the snoop missed. Available PDIST counters: 0 ocr.demand_code_rd.l3_hit.snoop_not_needed cache Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where no snoop was needed to satisfy the request event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0004  00    Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where no snoop was needed to satisfy the request. Available PDIST counters: 0 ocr.demand_data_and_l1pf_rd.any_response cache Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10001  00    Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have any type of response. Available PDIST counters: 0 ocr.demand_data_and_l1pf_rd.l3_hit cache Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x1F803C0001  00    Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache. Available PDIST counters: 0 ocr.demand_data_and_l1pf_rd.l3_hit.snoop_hitm cache Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0001  00    Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. Available PDIST counters: 0 ocr.demand_data_and_l1pf_rd.l3_hit.snoop_hit_no_fwd cache Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0001  00    Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. Available PDIST counters: 0 ocr.demand_data_and_l1pf_rd.l3_hit.snoop_hit_with_fwd cache Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0001  00    Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. Available PDIST counters: 0 ocr.demand_data_and_l1pf_rd.l3_hit.snoop_miss cache Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0001  00    Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed. Available PDIST counters: 0 ocr.demand_data_and_l1pf_rd.l3_hit.snoop_not_needed cache Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0001  00    Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request. Available PDIST counters: 0 ocr.demand_data_and_l1pf_rd.outstanding cache Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency) event=0xb7,period=100003,umask=1,offcore_rsp=0x8000000000000001  00    Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency). Available PDIST counters: 0 ocr.demand_data_rd.any_response cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10001  10    This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE Available PDIST counters: 0 ocr.demand_data_rd.l3_hit cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT event=0xb7,period=100003,umask=1,offcore_rsp=0x1F803C0001  10    This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT Available PDIST counters: 0 ocr.demand_data_rd.l3_hit.snoop_hitm cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0001  10    This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM Available PDIST counters: 0 ocr.demand_data_rd.l3_hit.snoop_hit_no_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0001  10    This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD Available PDIST counters: 0 ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0001  10    This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD Available PDIST counters: 0 ocr.demand_data_rd.l3_hit.snoop_miss cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0001  10    This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS Available PDIST counters: 0 ocr.demand_data_rd.l3_hit.snoop_not_needed cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0001  10    This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED Available PDIST counters: 0 ocr.demand_data_rd.outstanding cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING event=0xb7,period=100003,umask=1,offcore_rsp=0x8000000000000001  10    This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING Available PDIST counters: 0 ocr.demand_rfo.l3_hit.snoop_miss cache Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0002  00    Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed. Available PDIST counters: 0 ocr.demand_rfo.l3_hit.snoop_not_needed cache Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0002  00    Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request. Available PDIST counters: 0 ocr.demand_rfo.outstanding cache Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency) event=0xb7,period=100003,umask=1,offcore_rsp=0x8000000000000002  00    Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency). Available PDIST counters: 0 ocr.full_streaming_wr.l3_hit cache Counts streaming stores which modify a full 64 byte cacheline that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x801F803C0000  00    Counts streaming stores which modify a full 64 byte cacheline that were supplied by the L3 cache. Available PDIST counters: 0 ocr.hwpf_l1d_and_swpf.any_response cache Counts L1 data cache hardware prefetches and software prefetches (except PREFETCHW and PFRFO) that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10400  00    Counts L1 data cache hardware prefetches and software prefetches (except PREFETCHW and PFRFO) that have any type of response. Available PDIST counters: 0 ocr.hwpf_l1d_and_swpf.l3_hit.snoop_hitm cache Counts L1 data cache hardware prefetches and software prefetches (except PREFETCHW and PFRFO) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0400  00    Counts L1 data cache hardware prefetches and software prefetches (except PREFETCHW and PFRFO) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. Available PDIST counters: 0 ocr.hwpf_l2_code_rd.any_response cache Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10040  00    Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have any type of response. Available PDIST counters: 0 ocr.hwpf_l2_code_rd.l3_hit cache Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x1F803C0040  00    Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache. Available PDIST counters: 0 ocr.hwpf_l2_code_rd.l3_hit.snoop_hitm cache Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0040  00    Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. Available PDIST counters: 0 ocr.hwpf_l2_code_rd.l3_hit.snoop_hit_no_fwd cache Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0040  00    Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. Available PDIST counters: 0 ocr.hwpf_l2_code_rd.l3_hit.snoop_hit_with_fwd cache Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0040  00    Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. Available PDIST counters: 0 ocr.hwpf_l2_code_rd.l3_hit.snoop_miss cache Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0040  00    Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed. Available PDIST counters: 0 ocr.hwpf_l2_code_rd.l3_hit.snoop_not_needed cache Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0040  00    Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request. Available PDIST counters: 0 ocr.hwpf_l2_code_rd.outstanding cache Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency) event=0xb7,period=100003,umask=1,offcore_rsp=0x8000000000000040  00    Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency). Available PDIST counters: 0 ocr.hwpf_l2_data_rd.any_response cache Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10010  00    Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that have any type of response. Available PDIST counters: 0 ocr.hwpf_l2_data_rd.l3_hit cache Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x1F803C0010  00    Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache. Available PDIST counters: 0 ocr.hwpf_l2_data_rd.l3_hit.snoop_hitm cache Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0010  00    Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. Available PDIST counters: 0 ocr.hwpf_l2_data_rd.l3_hit.snoop_hit_no_fwd cache Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0010  00    Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. Available PDIST counters: 0 ocr.hwpf_l2_data_rd.l3_hit.snoop_hit_with_fwd cache Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0010  00    Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. Available PDIST counters: 0 ocr.hwpf_l2_data_rd.l3_hit.snoop_miss cache Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0010  00    Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed. Available PDIST counters: 0 ocr.hwpf_l2_data_rd.l3_hit.snoop_not_needed cache Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0010  00    Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request. Available PDIST counters: 0 ocr.hwpf_l2_rfo.any_response cache Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10020  00    Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have any type of response. Available PDIST counters: 0 ocr.hwpf_l2_rfo.l3_hit cache Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x1F803C0020  00    Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache. Available PDIST counters: 0 ocr.hwpf_l2_rfo.l3_hit.snoop_hitm cache Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0020  00    Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. Available PDIST counters: 0 ocr.hwpf_l2_rfo.l3_hit.snoop_hit_no_fwd cache Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0020  00    Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. Available PDIST counters: 0 ocr.hwpf_l2_rfo.l3_hit.snoop_hit_with_fwd cache Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0020  00    Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. Available PDIST counters: 0 ocr.hwpf_l2_rfo.l3_hit.snoop_miss cache Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0020  00    Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed. Available PDIST counters: 0 ocr.hwpf_l2_rfo.l3_hit.snoop_not_needed cache Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0020  00    Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request. Available PDIST counters: 0 ocr.hwpf_l2_rfo.outstanding cache Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency) event=0xb7,period=100003,umask=1,offcore_rsp=0x8000000000000020  00    Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency). Available PDIST counters: 0 ocr.l1wb_m.any_response cache Counts modified writebacks from L1 cache that miss the L2 cache that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x1000000010000  00    Counts modified writebacks from L1 cache that miss the L2 cache that have any type of response. Available PDIST counters: 0 ocr.l1wb_m.l3_hit cache Counts modified writebacks from L1 cache that miss the L2 cache that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x1001F803C0000  00    Counts modified writebacks from L1 cache that miss the L2 cache that were supplied by the L3 cache. Available PDIST counters: 0 ocr.l2wb_m.any_response cache Counts modified writeBacks from L2 cache that miss the L3 cache that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x2000000010000  00    Counts modified writeBacks from L2 cache that miss the L3 cache that have any type of response. Available PDIST counters: 0 ocr.l2wb_m.l3_hit cache Counts modified writeBacks from L2 cache that miss the L3 cache that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2001F803C0000  00    Counts modified writeBacks from L2 cache that miss the L3 cache that were supplied by the L3 cache. Available PDIST counters: 0 ocr.partial_streaming_wr.l3_hit cache Counts streaming stores which modify only part of a 64 byte cacheline that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x401F803C0000  00    Counts streaming stores which modify only part of a 64 byte cacheline that were supplied by the L3 cache. Available PDIST counters: 0 ocr.reads_to_core.any_response cache Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10477  00    Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response. Available PDIST counters: 0 ocr.reads_to_core.l3_hit cache Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x1F803C0477  00    Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache. Available PDIST counters: 0 ocr.reads_to_core.l3_hit.snoop_hitm cache Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0477  00    Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. Available PDIST counters: 0 ocr.reads_to_core.l3_hit.snoop_hit_no_fwd cache Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0477  00    Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. Available PDIST counters: 0 ocr.reads_to_core.l3_hit.snoop_hit_with_fwd cache Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0477  00    Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. Available PDIST counters: 0 ocr.reads_to_core.l3_hit.snoop_miss cache Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent but the snoop missed event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0477  00    Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent but the snoop missed. Available PDIST counters: 0 ocr.reads_to_core.l3_hit.snoop_not_needed cache Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where no snoop was needed to satisfy the request event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0477  00    Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where no snoop was needed to satisfy the request. Available PDIST counters: 0 ocr.reads_to_core.outstanding cache Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency) event=0xb7,period=100003,umask=1,offcore_rsp=0x8000000000000477  00    Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency). Available PDIST counters: 0 ocr.streaming_wr.l3_hit cache Counts streaming stores that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x1F803C0800  00    Counts streaming stores that were supplied by the L3 cache. Available PDIST counters: 0 ocr.uc_rd.l3_hit cache Counts uncached memory reads that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x101F803C0000  00    Counts uncached memory reads that were supplied by the L3 cache. Available PDIST counters: 0 ocr.uc_rd.l3_hit.snoop_hitm cache Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x1010003C0000  00    Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. Available PDIST counters: 0 ocr.uc_rd.l3_hit.snoop_hit_no_fwd cache Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x1004003C0000  00    Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. Available PDIST counters: 0 ocr.uc_rd.l3_hit.snoop_hit_with_fwd cache Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x1008003C0000  00    Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. Available PDIST counters: 0 ocr.uc_rd.l3_hit.snoop_miss cache Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent but the snoop missed event=0xb7,period=100003,umask=1,offcore_rsp=0x1002003C0000  00    Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent but the snoop missed. Available PDIST counters: 0 ocr.uc_rd.l3_hit.snoop_not_needed cache Counts uncached memory reads that were supplied by the L3 cache where no snoop was needed to satisfy the request event=0xb7,period=100003,umask=1,offcore_rsp=0x1001003C0000  00    Counts uncached memory reads that were supplied by the L3 cache where no snoop was needed to satisfy the request. Available PDIST counters: 0 ocr.uc_wr.l3_hit cache Counts uncached memory writes that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x201F803C0000  00    Counts uncached memory writes that were supplied by the L3 cache. Available PDIST counters: 0 cycles_div_busy.fpdiv floating point Counts the number of cycles the floating point divider is busy event=0xcd,period=200003,umask=2  00    Counts the number of cycles the floating point divider is busy.  Does not imply a stall waiting for the divider uops_retired.fpdiv floating point Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt) (Precise event) event=0xc2,period=2000003,umask=8  00    Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt). Available PDIST counters: 0 (Precise event) icache.hit frontend Counts the number of instruction cache hits event=0x80,period=200003,umask=1  00    Counts the number of requests that hit in the instruction cache.  The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one.  Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line misalign_mem_ref.load_page_split memory Counts the number of misaligned load uops that are 4K page splits (Precise event) event=0x13,period=200003,umask=2  00    Counts the number of misaligned load uops that are 4K page splits. Available PDIST counters: 0 (Precise event) misalign_mem_ref.store_page_split memory Counts the number of misaligned store uops that are 4K page splits (Precise event) event=0x13,period=200003,umask=4  00    Counts the number of misaligned store uops that are 4K page splits. Available PDIST counters: 0 (Precise event) ocr.all_code_rd.dram memory Counts all code reads that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000044  00    Counts all code reads that were supplied by DRAM. Available PDIST counters: 0 ocr.all_code_rd.l3_miss memory Counts all code reads that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000044  00    Counts all code reads that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.all_code_rd.l3_miss_local memory Counts all code reads that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000044  00    Counts all code reads that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.all_code_rd.local_dram memory Counts all code reads that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000044  00    Counts all code reads that were supplied by DRAM. Available PDIST counters: 0 ocr.corewb_m.l3_miss memory Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3002184000000  00    Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.corewb_m.l3_miss_local memory Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3002184000000  00    Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.demand_code_rd.dram memory Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000004  00    Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM. Available PDIST counters: 0 ocr.demand_code_rd.l3_miss memory Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000004  00    Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.demand_code_rd.l3_miss_local memory Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000004  00    Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.demand_code_rd.local_dram memory Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000004  00    Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM. Available PDIST counters: 0 ocr.demand_data_and_l1pf_rd.dram memory Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000001  00    Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM. Available PDIST counters: 0 ocr.demand_data_and_l1pf_rd.l3_miss memory Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000001  00    Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.demand_data_and_l1pf_rd.l3_miss_local memory Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000001  00    Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.demand_data_and_l1pf_rd.local_dram memory Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000001  00    Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM. Available PDIST counters: 0 ocr.demand_data_rd.dram memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000001  10    This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.DRAM Available PDIST counters: 0 ocr.demand_data_rd.l3_miss memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000001  10    This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS Available PDIST counters: 0 ocr.demand_data_rd.l3_miss_local memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000001  10    This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL Available PDIST counters: 0 ocr.demand_data_rd.local_dram memory This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000001  10    This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM Available PDIST counters: 0 ocr.demand_rfo.dram memory Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000002  00    Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM. Available PDIST counters: 0 ocr.demand_rfo.l3_miss memory Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000002  00    Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.demand_rfo.l3_miss_local memory Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000002  00    Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.demand_rfo.local_dram memory Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000002  00    Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM. Available PDIST counters: 0 ocr.full_streaming_wr.l3_miss memory Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x802184000000  00    Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.full_streaming_wr.l3_miss_local memory Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x802184000000  00    Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.hwpf_l2_code_rd.dram memory Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000040  00    Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM. Available PDIST counters: 0 ocr.hwpf_l2_code_rd.l3_miss memory Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000040  00    Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.hwpf_l2_code_rd.l3_miss_local memory Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000040  00    Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.hwpf_l2_code_rd.local_dram memory Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000040  00    Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM. Available PDIST counters: 0 ocr.hwpf_l2_data_rd.dram memory Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000010  00    Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM. Available PDIST counters: 0 ocr.hwpf_l2_data_rd.l3_miss memory Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000010  00    Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.hwpf_l2_data_rd.l3_miss_local memory Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000010  00    Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.hwpf_l2_data_rd.local_dram memory Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000010  00    Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM. Available PDIST counters: 0 ocr.hwpf_l2_rfo.dram memory Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000020  00    Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM. Available PDIST counters: 0 ocr.hwpf_l2_rfo.l3_miss memory Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000020  00    Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.hwpf_l2_rfo.l3_miss_local memory Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000020  00    Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.hwpf_l2_rfo.local_dram memory Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000020  00    Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM. Available PDIST counters: 0 ocr.l1wb_m.l3_miss memory Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x1002184000000  00    Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.l1wb_m.l3_miss_local memory Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x1002184000000  00    Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.l2wb_m.l3_miss memory Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2002184000000  00    Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.l2wb_m.l3_miss_local memory Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2002184000000  00    Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.other.l3_miss memory Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184008000  00    Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.other.l3_miss_local memory Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184008000  00    Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.partial_streaming_wr.l3_miss memory Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x402184000000  00    Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.partial_streaming_wr.l3_miss_local memory Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x402184000000  00    Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.prefetches.l3_miss memory Counts all hardware and software prefetches that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000470  00    Counts all hardware and software prefetches that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.reads_to_core.dram memory Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000477  00    Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM. Available PDIST counters: 0 ocr.reads_to_core.l3_miss memory Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000477  00    Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.reads_to_core.l3_miss_local memory Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000477  00    Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.reads_to_core.local_dram memory Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000477  00    Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM. Available PDIST counters: 0 ocr.streaming_wr.l3_miss memory Counts streaming stores that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000800  00    Counts streaming stores that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.streaming_wr.l3_miss_local memory Counts streaming stores that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x2184000800  00    Counts streaming stores that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.uc_rd.dram memory Counts uncached memory reads that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x100184000000  00    Counts uncached memory reads that were supplied by DRAM. Available PDIST counters: 0 ocr.uc_rd.l3_miss memory Counts uncached memory reads that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x102184000000  00    Counts uncached memory reads that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.uc_rd.l3_miss_local memory Counts uncached memory reads that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x102184000000  00    Counts uncached memory reads that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.uc_rd.local_dram memory Counts uncached memory reads that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x100184000000  00    Counts uncached memory reads that were supplied by DRAM. Available PDIST counters: 0 ocr.uc_wr.l3_miss memory Counts uncached memory writes that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x202184000000  00    Counts uncached memory writes that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.uc_wr.l3_miss_local memory Counts uncached memory writes that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x202184000000  00    Counts uncached memory writes that were not supplied by the L3 cache. Available PDIST counters: 0 bus_lock.all other This event is deprecated. Refer to new event BUS_LOCK.SELF_LOCKS event=0x63,edge=1,period=200003  10     bus_lock.block_cycles other Counts the number of unhalted cycles a core is blocked due to an accepted lock issued by other cores event=0x63,period=200003,umask=2  00    Counts the number of unhalted cycles a core is blocked due to an accepted lock issued by other cores. Counts on a per core basis bus_lock.cycles_other_block other This event is deprecated. Refer to new event BUS_LOCK.BLOCK_CYCLES event=0x63,period=200003,umask=2  10     bus_lock.cycles_self_block other This event is deprecated. Refer to new event BUS_LOCK.LOCK_CYCLES event=0x63,period=200003,umask=1  10     bus_lock.lock_cycles other Counts the number of unhalted cycles a core is blocked due to an accepted lock it issued event=0x63,period=200003,umask=1  00    Counts the number of unhalted cycles a core is blocked due to an accepted lock it issued. Counts on a per core basis bus_lock.self_locks other Counts the number of bus locks a core issued its self (e.g. lock to UC or Split Lock) and does not include cache locks event=0x63,edge=1,period=200003  00    Counts the number of bus locks a core issued its self (e.g. lock to UC or Split Lock) and does not include cache locks. Counts on a per core basis c0_stalls.load_dram_hit other This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_DRAM_HIT event=0x34,period=200003,umask=4  10     c0_stalls.load_l2_hit other This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_L2_HIT event=0x34,period=200003,umask=1  10     c0_stalls.load_llc_hit other This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_LLC_HIT event=0x34,period=200003,umask=2  10     hw_interrupts.masked other Counts the number of core cycles during which interrupts are masked (disabled) event=0xcb,period=200003,umask=2  00    Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not hw_interrupts.pending_and_masked other Counts the number of core cycles during which there are pending interrupts while interrupts are masked (disabled) event=0xcb,period=200003,umask=4  00    Counts the number of core cycles during which there are pending interrupts while interrupts are masked (disabled). Increments by 1 each core cycle that both EFLAGS.IF is 0 and an INTR is pending (which means the APIC is telling the ROB to cause an INTR). This event does not increment if EFLAGS.IF is 0 but all interrupt in the APICs Interrupt Request Register (IRR) are inhibited by the PPR (thus either by ISRV or TPR)  because in these cases the interrupts would be held up in the APIC and would not be pended to the ROB. This event does count when an interrupt is only inhibited by MOV/POP SS state machines or the STI state machine. These extra inhibits only last for a single instructions and would not be important hw_interrupts.received other Counts the number of hardware interrupts received by the processor event=0xcb,period=203,umask=1  00     ocr.all_code_rd.any_response other Counts all code reads that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10044  00    Counts all code reads that have any type of response. Available PDIST counters: 0 ocr.all_code_rd.outstanding other Counts all code reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency) event=0xb7,period=100003,umask=1,offcore_rsp=0x8000000000000044  00    Counts all code reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency). Available PDIST counters: 0 ocr.other.any_response other Counts miscellaneous requests, such as I/O accesses, that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x18000  00    Counts miscellaneous requests, such as I/O accesses, that have any type of response. Available PDIST counters: 0 ocr.prefetches.any_response other Counts all hardware and software prefetches that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10470  00    Counts all hardware and software prefetches that have any type of response. Available PDIST counters: 0 ocr.uc_rd.any_response other Counts uncached memory reads that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x100000010000  00    Counts uncached memory reads that have any type of response. Available PDIST counters: 0 ocr.uc_rd.outstanding other Counts uncached memory reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency) event=0xb7,period=100003,umask=1,offcore_rsp=0x8000100000000000  00    Counts uncached memory reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency). Available PDIST counters: 0 ocr.uc_wr.any_response other Counts uncached memory writes that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x200000010000  00    Counts uncached memory writes that have any type of response. Available PDIST counters: 0 br_inst_retired.all_branches pipeline Counts the total number of branch instructions retired for all branch types (Precise event) event=0xc4,period=200003  00    Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires.  All branch type instructions are accounted for. Available PDIST counters: 0 (Precise event) br_inst_retired.call pipeline Counts the number of near CALL branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xf9  00    Counts the number of near CALL branch instructions retired. Available PDIST counters: 0 (Precise event) br_inst_retired.far_branch pipeline Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return (Precise event) event=0xc4,period=200003,umask=0xbf  00    Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return. Available PDIST counters: 0 (Precise event) br_inst_retired.ind_call pipeline Counts the number of near indirect CALL branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xfb  00    Counts the number of near indirect CALL branch instructions retired. Available PDIST counters: 0 (Precise event) br_inst_retired.jcc pipeline Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches (Precise event) event=0xc4,period=200003,umask=0x7e  00    Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches. Available PDIST counters: 0 (Precise event) br_inst_retired.non_return_ind pipeline Counts the number of near indirect JMP and near indirect CALL branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xeb  00    Counts the number of near indirect JMP and near indirect CALL branch instructions retired. Available PDIST counters: 0 (Precise event) br_inst_retired.rel_call pipeline Counts the number of near relative CALL branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xfd  00    Counts the number of near relative CALL branch instructions retired. Available PDIST counters: 0 (Precise event) br_inst_retired.return pipeline Counts the number of near RET branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xf7  00    Counts the number of near RET branch instructions retired. Available PDIST counters: 0 (Precise event) br_inst_retired.taken_jcc pipeline Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xfe  00    Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired. Available PDIST counters: 0 (Precise event) br_misp_retired.all_branches pipeline Counts the total number of mispredicted branch instructions retired for all branch types (Precise event) event=0xc5,period=200003  00    Counts the total number of mispredicted branch instructions retired.  All branch type instructions are accounted for.  Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP.    A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path. Available PDIST counters: 0 (Precise event) br_misp_retired.ind_call pipeline Counts the number of mispredicted near indirect CALL branch instructions retired (Precise event) event=0xc5,period=200003,umask=0xfb  00    Counts the number of mispredicted near indirect CALL branch instructions retired. Available PDIST counters: 0 (Precise event) br_misp_retired.jcc pipeline Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired (Precise event) event=0xc5,period=200003,umask=0x7e  00    Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired. Available PDIST counters: 0 (Precise event) br_misp_retired.non_return_ind pipeline Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired (Precise event) event=0xc5,period=200003,umask=0xeb  00    Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired. Available PDIST counters: 0 (Precise event) br_misp_retired.return pipeline Counts the number of mispredicted near RET branch instructions retired (Precise event) event=0xc5,period=200003,umask=0xf7  00    Counts the number of mispredicted near RET branch instructions retired. Available PDIST counters: 0 (Precise event) br_misp_retired.taken_jcc pipeline Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired (Precise event) event=0xc5,period=200003,umask=0xfe  00    Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired. Available PDIST counters: 0 (Precise event) btclear.any pipeline Counts the total number of BTCLEARS event=0xe8,period=200003  00    Counts the total number of BTCLEARS which occurs when the Branch Target Buffer (BTB) predicts a taken branch cpu_clk_unhalted.ref pipeline Counts the number of unhalted reference clock cycles at TSC frequency event=0x0,umask=0x03,period=2000003  00    Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2 cycles_div_busy.any pipeline This event is deprecated event=0xcd,period=2000003  10     cycles_div_busy.idiv pipeline Counts the number of cycles the integer divider is busy event=0xcd,period=200003,umask=1  00    Counts the number of cycles the integer divider is busy.  Does not imply a stall waiting for the divider inst_retired.any pipeline Counts the total number of instructions retired. (Fixed event) (Precise event) event=0xc0,period=2000003  00    Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. Available PDIST counters: 0 (Precise event) inst_retired.any_p pipeline Counts the total number of instructions retired (Precise event) event=0xc0,period=2000003  00    Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses a programmable general purpose performance counter. Available PDIST counters: 0 (Precise event) ld_blocks.4k_alias pipeline Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check (Precise event) event=3,period=1000003,umask=4  00    Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check. Available PDIST counters: 0 (Precise event) ld_blocks.all pipeline Counts the number of retired loads that are blocked for any of the following reasons:  DTLB miss, address alias, store forward or data unknown (includes memory disambiguation blocks and ESP consuming load blocks) (Precise event) event=3,period=1000003,umask=0x10  00    Counts the number of retired loads that are blocked for any of the following reasons:  DTLB miss, address alias, store forward or data unknown (includes memory disambiguation blocks and ESP consuming load blocks). Available PDIST counters: 0 (Precise event) ld_blocks.data_unknown pipeline Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready (Precise event) event=3,period=1000003,umask=1  00    Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready. Available PDIST counters: 0 (Precise event) ld_blocks.store_forward pipeline Counts the number of retired loads that are blocked because its address partially overlapped with an older store (Precise event) event=3,period=1000003,umask=2  00    Counts the number of retired loads that are blocked because its address partially overlapped with an older store. Available PDIST counters: 0 (Precise event) machine_clears.any pipeline Counts the total number of machine clears for any reason including, but not limited to, memory ordering, memory disambiguation, SMC, and FP assist event=0xc3,period=20003  00     topdown_bad_speculation.all pipeline Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear event=0x73,period=1000003,umask=6  00    Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ) even if an FE_bound event occurs during this period. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear topdown_bad_speculation.machine_clears pipeline Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation event=0x73,period=1000003,umask=2  00     topdown_bad_speculation.monuke pipeline This event is deprecated. Refer to new event TOPDOWN_BAD_SPECULATION.FASTNUKE event=0x73,period=1000003,umask=2  10     topdown_be_bound.store_buffer pipeline This event is deprecated event=0x74,period=1000003,umask=4  10     topdown_retiring.all pipeline Counts the total number of consumed retirement slots (Precise event) event=0xc2,period=1000003  00    Counts the total number of consumed retirement slots. Available PDIST counters: 0 (Precise event) uops_retired.all pipeline Counts the total number of uops retired (Precise event) event=0xc2,period=2000003  00    Counts the total number of uops retired. Available PDIST counters: 0 (Precise event) uops_retired.idiv pipeline Counts the number of integer divide uops retired (Precise event) event=0xc2,period=2000003,umask=0x10  00    Counts the number of integer divide uops retired. Available PDIST counters: 0 (Precise event) uops_retired.ms pipeline Counts the number of uops that are from complex flows issued by the micro-sequencer (MS) (Precise event) event=0xc2,period=2000003,umask=1  00    Counts the number of uops that are from complex flows issued by the Microcode Sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows. Available PDIST counters: 0 (Precise event) uops_retired.x87 pipeline Counts the number of x87 uops retired, includes those in MS flows (Precise event) event=0xc2,period=2000003,umask=2  00    Counts the number of x87 uops retired, includes those in MS flows. Available PDIST counters: 0 (Precise event) dtlb_load_misses.pde_cache_miss virtual memory Counts the number of page walks due to loads that miss the PDE (Page Directory Entry) cache event=8,period=200003,umask=0x80  00     dtlb_load_misses.stlb_hit virtual memory Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Account for all page sizes. Will result in a DTLB write from STLB event=8,period=200003,umask=0x20  00     dtlb_load_misses.walk_completed_1g virtual memory Counts the number of page walks completed due to load DTLB misses to a 1G page event=8,period=200003,umask=8  00    Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1GB pages. Includes page walks that page fault dtlb_load_misses.walk_pending virtual memory Counts the number of page walks outstanding in the page miss handler (PMH) for demand loads every cycle event=8,period=200003,umask=0x10  00    Counts the number of page walks outstanding in the page miss handler (PMH) for demand loads every cycle.  A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals dtlb_store_misses.pde_cache_miss virtual memory Counts the number of page walks due to stores that miss the PDE (Page Directory Entry) cache event=0x49,period=2000003,umask=0x80  00     dtlb_store_misses.stlb_hit virtual memory Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Account for all pages sizes. Will result in a DTLB write from STLB event=0x49,period=2000003,umask=0x20  00     dtlb_store_misses.walk_completed virtual memory Counts the number of page walks completed due to store DTLB misses to any page size event=0x49,period=200003,umask=0xe  00    Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size.  Includes page walks that page fault dtlb_store_misses.walk_completed_1g virtual memory Counts the number of page walks completed due to store DTLB misses to a 1G page event=0x49,period=200003,umask=8  00    Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1G pages.  Includes page walks that page fault dtlb_store_misses.walk_pending virtual memory Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle event=0x49,period=200003,umask=0x10  00    Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle.  A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals ept.epde_hit virtual memory Counts the number of Extended Page Directory Entry hits event=0x4f,period=2000003,umask=1  00    Counts the number of Extended Page Directory Entry hits.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches ept.epde_miss virtual memory Counts the number of Extended Page Directory Entry misses event=0x4f,period=2000003,umask=2  00    Counts the number Extended Page Directory Entry misses.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches ept.epdpe_hit virtual memory Counts the number of Extended Page Directory Pointer Entry hits event=0x4f,period=2000003,umask=4  00    Counts the number Extended Page Directory Pointer Entry hits.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches ept.epdpe_miss virtual memory Counts the number of Extended Page Directory Pointer Entry misses event=0x4f,period=2000003,umask=8  00    Counts the number Extended Page Directory Pointer Entry misses.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches ept.walk_pending virtual memory Counts the number of page walks outstanding for an Extended Page table walk including GTLB hits per cycle event=0x4f,period=200003,umask=0x10  00    Counts the number of page walks outstanding for an Extended Page table walk including GTLB hits per cycle.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches itlb_misses.walk_completed_1g virtual memory Counts the number of page walks completed due to instruction fetch misses to a 1G page event=0x85,period=200003,umask=8  00    Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1G pages.  Includes page walks that page fault itlb_misses.walk_pending virtual memory Counts the number of page walks outstanding in the page miss handler (PMH) for instruction fetches every cycle event=0x85,period=200003,umask=0x10  00    Counts the number of page walks outstanding in the page miss handler (PMH) for instruction fetches every cycle.  A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk) ld_blocks.dtlb_miss virtual memory Counts the number of retired loads that are blocked due to a first level TLB miss (Precise event) event=3,period=1000003,umask=8  00    Counts the number of retired loads that are blocked due to a first level TLB miss. Available PDIST counters: 0 (Precise event) mem_uops_retired.dtlb_miss virtual memory Counts the number of memory uops retired that missed in the second level TLB  Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x13  00    Counts the number of memory uops retired that missed in the second level TLB. Available PDIST counters: 0  Supports address when precise (Precise event) mem_uops_retired.dtlb_miss_loads virtual memory Counts the number of load uops retired that miss in the second Level TLB  Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x11  00    Counts the number of load uops retired that miss in the second Level TLB. Available PDIST counters: 0  Supports address when precise (Precise event) mem_uops_retired.dtlb_miss_stores virtual memory Counts the number of store uops retired that miss in the second level TLB  Supports address when precise (Precise event) event=0xd0,period=200003,umask=0x12  00    Counts the number of store uops retired that miss in the second level TLB. Available PDIST counters: 0  Supports address when precise (Precise event) core_snoop_response.i_fwd_fe cache Hit snoop reply with data, line invalidated event=0x27,period=1000003,umask=0x20  00    Counts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's cache, after the data is forwarded back to the requestor and indicating the data was found unmodified in the (FE) Forward or Exclusive State in this cores caches cache.  A single snoop response from the core counts on all hyperthreads of the core core_snoop_response.i_fwd_m cache HitM snoop reply with data, line invalidated event=0x27,period=1000003,umask=0x10  00    Counts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's caches, after the data is forwarded back to the requestor, and indicating the data was found modified(M) in this cores caches cache (aka HitM response).  A single snoop response from the core counts on all hyperthreads of the core core_snoop_response.i_hit_fse cache Hit snoop reply without sending the data, line invalidated event=0x27,period=1000003,umask=2  00    Counts responses to snoops indicating the line will now be (I)nvalidated in this core's caches without forwarded back to the requestor. The line was in Forward, Shared or Exclusive (FSE) state in this cores caches.  A single snoop response from the core counts on all hyperthreads of the core core_snoop_response.miss cache Line not found snoop reply event=0x27,period=1000003,umask=1  00    Counts responses to snoops indicating that the data was not found (IHitI) in this core's caches. A single snoop response from the core counts on all hyperthreads of the Core core_snoop_response.s_fwd_fe cache Hit snoop reply with data, line kept in Shared state event=0x27,period=1000003,umask=0x40  00    Counts responses to snoops indicating the line may be kept on this core in the (S)hared state, after the data is forwarded back to the requestor, initially the data was found in the cache in the (FS) Forward or Shared state.  A single snoop response from the core counts on all hyperthreads of the core core_snoop_response.s_fwd_m cache HitM snoop reply with data, line kept in Shared state event=0x27,period=1000003,umask=8  00    Counts responses to snoops indicating the line may be kept on this core in the (S)hared state, after the data is forwarded back to the requestor, initially the data was found in the cache in the (M)odified state.  A single snoop response from the core counts on all hyperthreads of the core core_snoop_response.s_hit_fse cache Hit snoop reply without sending the data, line kept in Shared state event=0x27,period=1000003,umask=4  00    Counts responses to snoops indicating the line was kept on this core in the (S)hared state, and that the data was found unmodified but not forwarded back to the requestor, initially the data was found in the cache in the (FSE) Forward, Shared state or Exclusive state.  A single snoop response from the core counts on all hyperthreads of the core l2_rqsts.all_demand_references cache Demand requests to L2 cache event=0x24,period=200003,umask=0xe7  00    Counts demand requests to L2 cache mem_load_l3_miss_retired.remote_dram cache MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM  Supports address when precise event=0xd3,period=1000003,umask=2  00    MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM Available PDIST counters: 0  Supports address when precise mem_load_l3_miss_retired.remote_fwd cache Retired load instructions whose data sources was forwarded from a remote cache  Supports address when precise event=0xd3,period=100007,umask=8  00    Retired load instructions whose data sources was forwarded from a remote cache. Available PDIST counters: 0  Supports address when precise mem_load_l3_miss_retired.remote_hitm cache MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM  Supports address when precise event=0xd3,period=1000003,umask=4  00    MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM Available PDIST counters: 0  Supports address when precise ocr.demand_code_rd.any_response cache Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response event=0x2a,period=100003,umask=1,offcore_rsp=0x10004  00    Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response. Available PDIST counters: 0 ocr.demand_code_rd.l3_hit cache Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket event=0x2a,period=100003,umask=1,offcore_rsp=0x3F803C0004  00    Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket. Available PDIST counters: 0 ocr.demand_code_rd.l3_hit.snoop_hitm cache Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data event=0x2a,period=100003,umask=1,offcore_rsp=0x10003C0004  00    Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data. Available PDIST counters: 0 ocr.demand_code_rd.snc_cache.hitm cache Counts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=1,offcore_rsp=0x1008000004  00    Counts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode. Available PDIST counters: 0 ocr.demand_code_rd.snc_cache.hit_with_fwd cache Counts demand instruction fetches and L1 instruction cache prefetches that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=1,offcore_rsp=0x808000004  00    Counts demand instruction fetches and L1 instruction cache prefetches that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode. Available PDIST counters: 0 ocr.demand_data_rd.l3_hit cache Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket event=0x2a,period=100003,umask=1,offcore_rsp=0x3F803C0001  00    Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket. Available PDIST counters: 0 ocr.demand_data_rd.l3_hit.snoop_hitm cache Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data event=0x2a,period=100003,umask=1,offcore_rsp=0x10003C0001  00    Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data. Available PDIST counters: 0 ocr.demand_data_rd.l3_hit.snoop_hit_no_fwd cache Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data event=0x2a,period=100003,umask=1,offcore_rsp=0x4003C0001  00    Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data. Available PDIST counters: 0 ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd cache Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core event=0x2a,period=100003,umask=1,offcore_rsp=0x8003C0001  00    Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core. Available PDIST counters: 0 ocr.demand_data_rd.remote_cache.snoop_hitm cache Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data event=0x2a,period=100003,umask=1,offcore_rsp=0x1030000001  00    Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data. Available PDIST counters: 0 ocr.demand_data_rd.remote_cache.snoop_hit_with_fwd cache Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core event=0x2a,period=100003,umask=1,offcore_rsp=0x830000001  00    Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core. Available PDIST counters: 0 ocr.demand_data_rd.snc_cache.hitm cache Counts demand data reads that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=1,offcore_rsp=0x1008000001  00    Counts demand data reads that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode. Available PDIST counters: 0 ocr.demand_data_rd.snc_cache.hit_with_fwd cache Counts demand data reads that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=1,offcore_rsp=0x808000001  00    Counts demand data reads that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode. Available PDIST counters: 0 ocr.demand_rfo.any_response cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response event=0x2a,period=100003,umask=1,offcore_rsp=0x3F3FFC0002  00    Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response. Available PDIST counters: 0 ocr.demand_rfo.l3_hit cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket event=0x2a,period=100003,umask=1,offcore_rsp=0x3F803C0002  00    Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket. Available PDIST counters: 0 ocr.demand_rfo.l3_hit.snoop_hitm cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data event=0x2a,period=100003,umask=1,offcore_rsp=0x10003C0002  00    Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data. Available PDIST counters: 0 ocr.demand_rfo.snc_cache.hitm cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=1,offcore_rsp=0x1008000002  00    Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode. Available PDIST counters: 0 ocr.demand_rfo.snc_cache.hit_with_fwd cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=1,offcore_rsp=0x808000002  00    Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode. Available PDIST counters: 0 ocr.hwpf_l1d.any_response cache Counts data load hardware prefetch requests to the L1 data cache that have any type of response event=0x2a,period=100003,umask=1,offcore_rsp=0x10400  00    Counts data load hardware prefetch requests to the L1 data cache that have any type of response. Available PDIST counters: 0 ocr.hwpf_l2.any_response cache Counts hardware prefetches (which bring data to L2) that have any type of response event=0x2a,period=100003,umask=1,offcore_rsp=0x10070  00    Counts hardware prefetches (which bring data to L2) that have any type of response. Available PDIST counters: 0 ocr.hwpf_l3.any_response cache Counts hardware prefetches to the L3 only that have any type of response event=0x2a,period=100003,umask=1,offcore_rsp=0x12380  00    Counts hardware prefetches to the L3 only that have any type of response. Available PDIST counters: 0 ocr.hwpf_l3.l3_hit cache Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket event=0x2a,period=100003,umask=1,offcore_rsp=0x80082380  00    Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket. Available PDIST counters: 0 ocr.hwpf_l3.remote cache Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket event=0x2a,period=100003,umask=1,offcore_rsp=0x90002380  00    Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket. Available PDIST counters: 0 ocr.modified_write.any_response cache Counts writebacks of modified cachelines and streaming stores that have any type of response event=0x2a,period=100003,umask=1,offcore_rsp=0x10808  00    Counts writebacks of modified cachelines and streaming stores that have any type of response. Available PDIST counters: 0 ocr.reads_to_core.any_response cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response event=0x2a,period=100003,umask=1,offcore_rsp=0x3F3FFC4477  00    Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response. Available PDIST counters: 0 ocr.reads_to_core.l3_hit cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket event=0x2a,period=100003,umask=1,offcore_rsp=0x3F003C4477  00    Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket. Available PDIST counters: 0 ocr.reads_to_core.l3_hit.snoop_hitm cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data event=0x2a,period=100003,umask=1,offcore_rsp=0x10003C4477  00    Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data. Available PDIST counters: 0 ocr.reads_to_core.l3_hit.snoop_hit_no_fwd cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data event=0x2a,period=100003,umask=1,offcore_rsp=0x4003C4477  00    Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data. Available PDIST counters: 0 ocr.reads_to_core.l3_hit.snoop_hit_with_fwd cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core event=0x2a,period=100003,umask=1,offcore_rsp=0x8003C4477  00    Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core. Available PDIST counters: 0 ocr.reads_to_core.remote cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socket event=0x2a,period=100003,umask=1,offcore_rsp=0x3F33004477  00    Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socket. Available PDIST counters: 0 ocr.reads_to_core.remote_cache.snoop_fwd cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified) event=0x2a,period=100003,umask=1,offcore_rsp=0x1830004477  00    Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified). Available PDIST counters: 0 ocr.reads_to_core.remote_cache.snoop_hitm cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data event=0x2a,period=100003,umask=1,offcore_rsp=0x1030004477  00    Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data. Available PDIST counters: 0 ocr.reads_to_core.remote_cache.snoop_hit_with_fwd cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core event=0x2a,period=100003,umask=1,offcore_rsp=0x830004477  00    Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core. Available PDIST counters: 0 ocr.reads_to_core.snc_cache.hitm cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=1,offcore_rsp=0x1008004477  00    Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode. Available PDIST counters: 0 ocr.reads_to_core.snc_cache.hit_with_fwd cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=1,offcore_rsp=0x808004477  00    Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode. Available PDIST counters: 0 ocr.rfo_to_core.l3_hit_m cache Counts demand reads for ownership (RFO), hardware prefetch RFOs (which bring data to L2), and software prefetches for exclusive ownership (PREFETCHW) that hit to a (M)odified cacheline in the L3 or snoop filter event=0x2a,period=100003,umask=1,offcore_rsp=0x1F80040022  00    Counts demand reads for ownership (RFO), hardware prefetch RFOs (which bring data to L2), and software prefetches for exclusive ownership (PREFETCHW) that hit to a (M)odified cacheline in the L3 or snoop filter. Available PDIST counters: 0 ocr.streaming_wr.l3_hit cache Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket event=0x2a,period=100003,umask=1,offcore_rsp=0x80080800  00    Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket. Available PDIST counters: 0 offcore_requests_outstanding.all_data_rd cache This event is deprecated. Refer to new event OFFCORE_REQUESTS_OUTSTANDING.DATA_RD event=0x20,period=1000003,umask=8  10     offcore_requests_outstanding.cycles_with_data_rd cache OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD event=0x20,cmask=1,period=1000003,umask=8  00     offcore_requests_outstanding.cycles_with_demand_rfo cache OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO event=0x20,cmask=1,period=1000003,umask=4  00     offcore_requests_outstanding.data_rd cache OFFCORE_REQUESTS_OUTSTANDING.DATA_RD event=0x20,period=1000003,umask=8  00     fp_arith_inst_retired.512b_packed_double floating point Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=0x40  00    Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.512b_packed_single floating point Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=0x80  00    Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.8_flops floating point Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision  FP instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, 1 for each element.  Applies to SSE* and AVX* packed single precision and double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element event=0xc7,period=100003,umask=0x60  00    Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision  floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision and double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired2.128b_packed_half floating point FP_ARITH_INST_RETIRED2.128B_PACKED_HALF event=0xcf,period=100003,umask=4  00     fp_arith_inst_retired2.256b_packed_half floating point FP_ARITH_INST_RETIRED2.256B_PACKED_HALF event=0xcf,period=100003,umask=8  00     fp_arith_inst_retired2.512b_packed_half floating point FP_ARITH_INST_RETIRED2.512B_PACKED_HALF event=0xcf,period=100003,umask=0x10  00     fp_arith_inst_retired2.complex_scalar_half floating point FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF event=0xcf,period=100003,umask=2  00     fp_arith_inst_retired2.scalar floating point Number of all Scalar Half-Precision FP arithmetic instructions(1) retired - regular and complex event=0xcf,period=100003,umask=3  00    FP_ARITH_INST_RETIRED2.SCALAR fp_arith_inst_retired2.scalar_half floating point FP_ARITH_INST_RETIRED2.SCALAR_HALF event=0xcf,period=100003,umask=1  00     fp_arith_inst_retired2.vector floating point Number of all Vector (also called packed) Half-Precision FP arithmetic instructions(1) retired event=0xcf,period=100003,umask=0x1c  00    FP_ARITH_INST_RETIRED2.VECTOR ocr.demand_code_rd.dram memory Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM event=0x2a,period=100003,umask=1,offcore_rsp=0x73C000004  00    Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM. Available PDIST counters: 0 ocr.demand_code_rd.l3_miss memory Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches event=0x2a,period=100003,umask=1,offcore_rsp=0x3FBFC00004  00    Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches. Available PDIST counters: 0 ocr.demand_code_rd.local_dram memory Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster event=0x2a,period=100003,umask=1,offcore_rsp=0x104000004  00    Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster. Available PDIST counters: 0 ocr.demand_code_rd.snc_dram memory Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=1,offcore_rsp=0x708000004  00    Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode. Available PDIST counters: 0 ocr.demand_data_rd.dram memory Counts demand data reads that were supplied by DRAM event=0x2a,period=100003,umask=1,offcore_rsp=0x73C000001  00    Counts demand data reads that were supplied by DRAM. Available PDIST counters: 0 ocr.demand_data_rd.l3_miss memory Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches event=0x2a,period=100003,umask=1,offcore_rsp=0x3FBFC00001  00    Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches. Available PDIST counters: 0 ocr.demand_data_rd.local_dram memory Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster event=0x2a,period=100003,umask=1,offcore_rsp=0x104000001  00    Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster. Available PDIST counters: 0 ocr.demand_data_rd.remote_dram memory Counts demand data reads that were supplied by DRAM attached to another socket event=0x2a,period=100003,umask=1,offcore_rsp=0x730000001  00    Counts demand data reads that were supplied by DRAM attached to another socket. Available PDIST counters: 0 ocr.demand_data_rd.snc_dram memory Counts demand data reads that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=1,offcore_rsp=0x708000001  00    Counts demand data reads that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode. Available PDIST counters: 0 ocr.demand_rfo.dram memory Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM event=0x2a,period=100003,umask=1,offcore_rsp=0x73C000002  00    Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM. Available PDIST counters: 0 ocr.demand_rfo.l3_miss memory Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches event=0x2a,period=100003,umask=1,offcore_rsp=0x3F3FC00002  00    Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches. Available PDIST counters: 0 ocr.demand_rfo.local_dram memory Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster event=0x2a,period=100003,umask=1,offcore_rsp=0x104000002  00    Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster. Available PDIST counters: 0 ocr.demand_rfo.snc_dram memory Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=1,offcore_rsp=0x708000002  00    Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode. Available PDIST counters: 0 ocr.hwpf_l3.l3_miss memory Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches event=0x2a,period=100003,umask=1,offcore_rsp=0x94002380  00    Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches. Available PDIST counters: 0 ocr.hwpf_l3.l3_miss_local memory Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0x2a,period=100003,umask=1,offcore_rsp=0x84002380  00    Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally. Available PDIST counters: 0 ocr.reads_to_core.dram memory Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM event=0x2a,period=100003,umask=1,offcore_rsp=0x73C004477  00    Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM. Available PDIST counters: 0 ocr.reads_to_core.l3_miss memory Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches event=0x2a,period=100003,umask=1,offcore_rsp=0x3F3FC04477  00    Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches. Available PDIST counters: 0 ocr.reads_to_core.l3_miss_local memory Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0x2a,period=100003,umask=1,offcore_rsp=0x3F04C04477  00    Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally. Available PDIST counters: 0 ocr.reads_to_core.l3_miss_local_socket memory Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster.  It does not count misses to the L3 which go to Local CXL Type 2 Memory or Local Non DRAM event=0x2a,period=100003,umask=1,offcore_rsp=0x70CC04477  00    Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster.  It does not count misses to the L3 which go to Local CXL Type 2 Memory or Local Non DRAM. Available PDIST counters: 0 ocr.reads_to_core.local_dram memory Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster event=0x2a,period=100003,umask=1,offcore_rsp=0x104004477  00    Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster. Available PDIST counters: 0 ocr.reads_to_core.local_socket_dram memory Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster event=0x2a,period=100003,umask=1,offcore_rsp=0x70C004477  00    Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster. Available PDIST counters: 0 ocr.reads_to_core.remote_dram memory Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket event=0x2a,period=100003,umask=1,offcore_rsp=0x730004477  00    Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket. Available PDIST counters: 0 ocr.reads_to_core.remote_memory memory Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or PMM attached to another socket event=0x2a,period=100003,umask=1,offcore_rsp=0x733004477  00    Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or PMM attached to another socket. Available PDIST counters: 0 ocr.reads_to_core.snc_dram memory Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=1,offcore_rsp=0x708004477  00    Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode. Available PDIST counters: 0 ocr.streaming_wr.l3_miss memory Counts streaming stores that missed the local socket's L1, L2, and L3 caches event=0x2a,period=100003,umask=1,offcore_rsp=0x94000800  00    Counts streaming stores that missed the local socket's L1, L2, and L3 caches. Available PDIST counters: 0 ocr.streaming_wr.l3_miss_local memory Counts streaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0x2a,period=100003,umask=1,offcore_rsp=0x84000800  00    Counts streaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally. Available PDIST counters: 0 ocr.write_estimate.memory memory Counts Demand RFOs, ItoM's, PREFECTHW's, Hardware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted in a store to Memory (DRAM or PMM) event=0x2a,period=100003,umask=1,offcore_rsp=0xFBFF80822  00    Counts Demand RFOs, ItoM's, PREFECTHW's, Hardware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted in a store to Memory (DRAM or PMM) Available PDIST counters: 0 rtm_retired.aborted memory Number of times an RTM execution aborted event=0xc9,period=100003,umask=4  00    Counts the number of times RTM abort was triggered. Available PDIST counters: 0 rtm_retired.aborted_events memory Number of times an RTM execution aborted due to none of the previous 3 categories (e.g. interrupt) event=0xc9,period=100003,umask=0x80  00    Counts the number of times an RTM execution aborted due to none of the previous 3 categories (e.g. interrupt) rtm_retired.aborted_mem memory Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts) event=0xc9,period=100003,umask=8  00    Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts) rtm_retired.aborted_memtype memory Number of times an RTM execution aborted due to incompatible memory type event=0xc9,period=100003,umask=0x40  00    Counts the number of times an RTM execution aborted due to incompatible memory type rtm_retired.aborted_unfriendly memory Number of times an RTM execution aborted due to HLE-unfriendly instructions event=0xc9,period=100003,umask=0x20  00    Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions rtm_retired.commit memory Number of times an RTM execution successfully committed event=0xc9,period=100003,umask=2  00    Counts the number of times RTM commit succeeded rtm_retired.start memory Number of times an RTM execution started event=0xc9,period=100003,umask=1  00    Counts the number of times we entered an RTM region. Does not count nested transactions tx_mem.abort_capacity_read memory Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads event=0x54,period=100003,umask=0x80  00    Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads tx_mem.abort_capacity_write memory Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes event=0x54,period=100003,umask=2  00    Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes tx_mem.abort_conflict memory Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address event=0x54,period=100003,umask=1  00    Counts the number of times a TSX line had a cache conflict hw_interrupts.masked other HW_INTERRUPTS.MASKED event=0xcb,period=100003,umask=2  00     hw_interrupts.pending_and_masked other HW_INTERRUPTS.PENDING_AND_MASKED event=0xcb,period=100003,umask=4  00     exe.amx_busy pipeline Counts the cycles where the AMX (Advance Matrix Extension) unit is busy performing an operation event=0xb7,period=2000003,umask=2  00     int_misc.mba_stalls pipeline INT_MISC.MBA_STALLS event=0xad,period=1000003,umask=0x20  00     uops_executed.core pipeline Number of uops executed on the core event=0xb1,period=2000003,umask=2  00    Counts the number of uops executed from any thread unc_cha_bypass_cha_imc.intermediate uncore cache CHA to iMC Bypass : Intermediate bypass Taken event=0x57,umask=2  01    CHA to iMC Bypass : Intermediate bypass Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that succeeded in taking the intermediate bypass unc_cha_bypass_cha_imc.not_taken uncore cache CHA to iMC Bypass : Not Taken event=0x57,umask=4  01    CHA to iMC Bypass : Not Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that could not take the bypass, and issues a read to memory. Note that transactions that did not take the bypass but did not issue read to memory will not be counted unc_cha_bypass_cha_imc.taken uncore cache CHA to iMC Bypass : Taken event=0x57,umask=1  01    CHA to iMC Bypass : Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that succeeded in taking the full bypass unc_cha_clockticks uncore cache CHA Clockticks event=1  01    Number of CHA clock cycles while the event is enabled unc_cha_core_snp.any_gtone uncore cache Core Cross Snoops Issued : Any Cycle with Multiple Snoops event=0x33,umask=0xf2  01    Core Cross Snoops Issued : Any Cycle with Multiple Snoops : Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.any_one uncore cache Core Cross Snoops Issued : Any Single Snoop event=0x33,umask=0xf1  01    Core Cross Snoops Issued : Any Single Snoop : Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.core_gtone uncore cache Core Cross Snoops Issued : Multiple Core Requests event=0x33,umask=0x42  01    Core Cross Snoops Issued : Multiple Core Requests : Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.core_one uncore cache Core Cross Snoops Issued : Single Core Requests event=0x33,umask=0x41  01    Core Cross Snoops Issued : Single Core Requests : Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.evict_gtone uncore cache Core Cross Snoops Issued : Multiple Eviction event=0x33,umask=0x82  01    Core Cross Snoops Issued : Multiple Eviction : Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.evict_one uncore cache Core Cross Snoops Issued : Single Eviction event=0x33,umask=0x81  01    Core Cross Snoops Issued : Single Eviction : Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.ext_gtone uncore cache Core Cross Snoops Issued : Multiple External Snoops event=0x33,umask=0x22  01    Core Cross Snoops Issued : Multiple External Snoops : Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.ext_one uncore cache Core Cross Snoops Issued : Single External Snoops event=0x33,umask=0x21  01    Core Cross Snoops Issued : Single External Snoops : Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.remote_gtone uncore cache Core Cross Snoops Issued : Multiple Snoop Targets from Remote event=0x33,umask=0x12  01    Core Cross Snoops Issued : Multiple Snoop Targets from Remote : Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.remote_one uncore cache Core Cross Snoops Issued : Single Snoop Target from Remote event=0x33,umask=0x11  01    Core Cross Snoops Issued : Single Snoop Target from Remote : Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s) unc_cha_direct_go.ha_suppress_drd uncore cache Direct GO event=0x6e,umask=4  01     unc_cha_direct_go.ha_suppress_no_d2c uncore cache Direct GO event=0x6e,umask=2  01     unc_cha_direct_go.ha_tor_dealloc uncore cache Direct GO event=0x6e,umask=1  01     unc_cha_direct_go_opc.extcmp uncore cache Direct GO event=0x6d,umask=1  01     unc_cha_direct_go_opc.fast_go uncore cache Direct GO event=0x6d,umask=0x10  01     unc_cha_direct_go_opc.fast_go_pull uncore cache Direct GO event=0x6d,umask=0x20  01     unc_cha_direct_go_opc.go uncore cache Direct GO event=0x6d,umask=4  01     unc_cha_direct_go_opc.go_pull uncore cache Direct GO event=0x6d,umask=8  01     unc_cha_direct_go_opc.idle_due_suppress uncore cache Direct GO event=0x6d,umask=0x80  01     unc_cha_direct_go_opc.nop uncore cache Direct GO event=0x6d,umask=0x40  01     unc_cha_direct_go_opc.pull uncore cache Direct GO event=0x6d,umask=2  01     unc_cha_distress_asserted.dpt_nonlocal uncore cache Distress signal asserted : DPT Remote event=0xaf,umask=8  01    Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile unc_cha_egress_ordering.iv_snoopgo_dn uncore cache Egress Blocking due to Ordering requirements : Down event=0xba,umask=4  01    Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_cha_egress_ordering.iv_snoopgo_up uncore cache Egress Blocking due to Ordering requirements : Up event=0xba,umask=1  01    Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_cha_hitme_hit.shared_ownreq uncore cache Counts Number of Hits in HitMe Cache : Shared hit and op is RdInvOwn, RdInv, Inv* event=0x5f,umask=4  01     unc_cha_hitme_hit.wbmtoe uncore cache Counts Number of Hits in HitMe Cache : op is WbMtoE event=0x5f,umask=8  01     unc_cha_hitme_hit.wbmtoi_or_s uncore cache Counts Number of Hits in HitMe Cache : op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoS event=0x5f,umask=0x10  01     unc_cha_hitme_lookup.read uncore cache Counts Number of times HitMe Cache is accessed : op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv* event=0x5e,umask=1  01     unc_cha_hitme_lookup.write uncore cache Counts Number of times HitMe Cache is accessed : op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS event=0x5e,umask=2  01     unc_cha_hitme_miss.notshared_rdinvown uncore cache Counts Number of Misses in HitMe Cache : No SF/LLC HitS/F and op is RdInvOwn event=0x60,umask=0x40  01     unc_cha_hitme_miss.read_or_inv uncore cache Counts Number of Misses in HitMe Cache : op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv* event=0x60,umask=0x80  01     unc_cha_hitme_miss.shared_rdinvown uncore cache Counts Number of Misses in HitMe Cache : SF/LLC HitS/F and op is RdInvOwn event=0x60,umask=0x20  01     unc_cha_hitme_update.deallocate uncore cache Counts the number of Allocate/Update to HitMe Cache : Deallocate HitME$ on Reads without RspFwdI* event=0x61,umask=0x10  01     unc_cha_hitme_update.deallocate_rspfwdi_loc uncore cache Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a local request event=0x61,umask=1  01    Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a local request : Received RspFwdI* for a local request, but converted HitME$ to SF entry unc_cha_hitme_update.rdinvown uncore cache Counts the number of Allocate/Update to HitMe Cache : Update HitMe Cache on RdInvOwn even if not RspFwdI* event=0x61,umask=8  01     unc_cha_hitme_update.rspfwdi_rem uncore cache Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a remote request event=0x61,umask=2  01    Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a remote request : Updated HitME$ on RspFwdI* or local HitM/E received for a remote request unc_cha_hitme_update.shared uncore cache Counts the number of Allocate/Update to HitMe Cache : Update HitMe Cache to SHARed event=0x61,umask=4  01     unc_cha_imc_reads_count.priority uncore cache HA to iMC Reads Issued : ISOCH event=0x59,umask=2  01    HA to iMC Reads Issued : ISOCH : Count of the number of reads issued to any of the memory controller channels.  This can be filtered by the priority of the reads unc_cha_imc_writes_count.full_priority uncore cache CHA to iMC Full Line Writes Issued : ISOCH Full Line event=0x5b,umask=4  01    CHA to iMC Full Line Writes Issued : ISOCH Full Line : Counts the total number of full line writes issued from the HA into the memory controller unc_cha_imc_writes_count.partial uncore cache CHA to iMC Full Line Writes Issued : Partial Non-ISOCH event=0x5b,umask=2  01    CHA to iMC Full Line Writes Issued : Partial Non-ISOCH : Counts the total number of full line writes issued from the HA into the memory controller unc_cha_imc_writes_count.partial_priority uncore cache CHA to iMC Full Line Writes Issued : ISOCH Partial event=0x5b,umask=8  01    CHA to iMC Full Line Writes Issued : ISOCH Partial : Counts the total number of full line writes issued from the HA into the memory controller unc_cha_llc_lookup.all uncore cache Cache and Snoop Filter Lookups; Any Request event=0x34,umask=0x1fffff  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ.  This does not include lookups originating from the ISMQ unc_cha_llc_lookup.all_remote uncore cache Cache Lookups : All transactions from Remote Agents event=0x34,umask=0x17e0ff  01    Cache Lookups : All transactions from Remote Agents : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing unc_cha_llc_lookup.any_f uncore cache Cache Lookups : All Requests event=0x34  01    Cache Lookups : All Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Any local or remote transaction to the LLC, including prefetch unc_cha_llc_lookup.code uncore cache Cache Lookups : CRd Requests event=0x34,umask=0x1bd0ff  01    Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC.  This includes CRd prefetch unc_cha_llc_lookup.code_read_f uncore cache Cache Lookups : CRd Requests event=0x34  01    Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC.  This includes CRd prefetch unc_cha_llc_lookup.corepref_or_dmnd_local_f uncore cache Cache Lookups : Local non-prefetch requests event=0x34  01    Cache Lookups : Local non-prefetch requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Any local transaction to the LLC, not including prefetch unc_cha_llc_lookup.data_rd uncore cache Cache and Snoop Filter Lookups; Data Read Request event=0x34,umask=0x1bc1ff  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.data_read_all uncore cache Cache Lookups : Data Reads event=0x34,umask=0x1fc1ff  01    Cache Lookups : Data Reads : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing unc_cha_llc_lookup.data_read_f uncore cache Cache Lookups : Data Read Request event=0x34  01    Cache Lookups : Data Read Request : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Read transactions unc_cha_llc_lookup.data_read_local uncore cache Cache Lookups : Demand Data Reads, Core and LLC prefetches event=0x34,umask=0x841ff  01    Cache Lookups : Demand Data Reads, Core and LLC prefetches : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing unc_cha_llc_lookup.data_read_miss uncore cache Cache Lookups : Data Read Misses event=0x34,umask=0x1fc101  01    Cache Lookups : Data Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing unc_cha_llc_lookup.e uncore cache Cache Lookups : E State event=0x34,umask=0x20  01    Cache Lookups : E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Hit Exclusive State unc_cha_llc_lookup.f uncore cache Cache Lookups : F State event=0x34,umask=0x80  01    Cache Lookups : F State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Hit Forward State unc_cha_llc_lookup.flush_inv uncore cache Cache Lookups : Flush or Invalidate Requests event=0x34,umask=0x1a44ff  01    Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing unc_cha_llc_lookup.flush_or_inv_f uncore cache Cache Lookups : Flush event=0x34  01    Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing unc_cha_llc_lookup.i uncore cache Cache Lookups : I State event=0x34,umask=1  01    Cache Lookups : I State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Miss unc_cha_llc_lookup.llcpref_local_f uncore cache Cache Lookups : Local LLC prefetch requests (from LLC) event=0x34  01    Cache Lookups : Local LLC prefetch requests (from LLC) : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Any local LLC prefetch to the LLC unc_cha_llc_lookup.locally_homed_address uncore cache Cache Lookups : Transactions homed locally event=0x34,umask=0xbdfff  01    Cache Lookups : Transactions homed locally : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Transaction whose address resides in the local MC unc_cha_llc_lookup.local_code uncore cache Cache Lookups : CRd Requests that come from the local socket (usually the core) event=0x34,umask=0x19d0ff  01    Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC.  This includes CRd prefetch unc_cha_llc_lookup.local_data_rd uncore cache Cache and Snoop Filter Lookups; Data Read Request that come from the local socket (usually the core) event=0x34,umask=0x19c1ff  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.local_dmnd_code uncore cache Cache Lookups : Demand CRd Requests that come from the local socket (usually the core) event=0x34,umask=0x1850ff  01    Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC.  This includes CRd prefetch unc_cha_llc_lookup.local_dmnd_data_rd uncore cache Cache and Snoop Filter Lookups; Demand Data Reads that come from the local socket (usually the core) event=0x34,umask=0x1841ff  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.local_dmnd_rfo uncore cache Cache Lookups : Demand RFO Requests that come from the local socket (usually the core) event=0x34,umask=0x1848ff  01    Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC.  This includes RFO prefetch unc_cha_llc_lookup.local_f uncore cache Cache Lookups : Transactions homed locally event=0x34  01    Cache Lookups : Transactions homed locally : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Transaction whose address resides in the local MC unc_cha_llc_lookup.local_flush_inv uncore cache Cache Lookups : Flush or Invalidate Requests that come from the local socket (usually the core) event=0x34,umask=0x1844ff  01    Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing unc_cha_llc_lookup.local_llc_pf uncore cache Cache and Snoop Filter Lookups; Prefetch requests to the LLC that come from the local socket (usually the core) event=0x34,umask=0x189dff  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.local_pf uncore cache Cache and Snoop Filter Lookups; Data Read Prefetches that come from the local socket (usually the core) event=0x34,umask=0x199dff  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.local_pf_code uncore cache Cache Lookups : CRd Prefetches that come from the local socket (usually the core) event=0x34,umask=0x1910ff  01    Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC.  This includes CRd prefetch unc_cha_llc_lookup.local_pf_data_rd uncore cache Cache and Snoop Filter Lookups; Data Read Prefetches that come from the local socket (usually the core) event=0x34,umask=0x1981ff  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.local_pf_rfo uncore cache Cache Lookups : RFO Prefetches that come from the local socket (usually the core) event=0x34,umask=0x1908ff  01    Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC.  This includes RFO prefetch unc_cha_llc_lookup.local_rfo uncore cache Cache Lookups : RFO Requests that come from the local socket (usually the core) event=0x34,umask=0x19c8ff  01    Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC.  This includes RFO prefetch unc_cha_llc_lookup.m uncore cache Cache Lookups : M State event=0x34,umask=0x40  01    Cache Lookups : M State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Hit Modified State unc_cha_llc_lookup.miss_all uncore cache Cache Lookups : All Misses event=0x34,umask=0x1fe001  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing unc_cha_llc_lookup.other_req_f uncore cache Cache Lookups : Write Requests event=0x34  01    Cache Lookups : Write Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Writeback transactions from L2 to the LLC  This includes all write transactions -- both Cacheable and UC unc_cha_llc_lookup.pref_or_dmnd_remote_f uncore cache Cache Lookups : Remote non-snoop requests event=0x34  01    Cache Lookups : Remote non-snoop requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Remote non-snoop transactions to the LLC unc_cha_llc_lookup.remotely_homed_address uncore cache Cache Lookups : Transactions homed remotely event=0x34,umask=0x15dfff  01    Cache Lookups : Transactions homed remotely : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Transaction whose address resides in a remote MC unc_cha_llc_lookup.remote_code uncore cache Cache Lookups : CRd Requests that come from a Remote socket event=0x34,umask=0x1a10ff  01    Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC.  This includes CRd prefetch unc_cha_llc_lookup.remote_data_rd uncore cache Cache and Snoop Filter Lookups; Data Read Requests that come from a Remote socket event=0x34,umask=0x1a01ff  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.remote_f uncore cache Cache Lookups : Transactions homed remotely event=0x34  01    Cache Lookups : Transactions homed remotely : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Transaction whose address resides in a remote MC unc_cha_llc_lookup.remote_flush_inv uncore cache Cache Lookups : Flush or Invalidate requests that come from a Remote socket event=0x34,umask=0x1a04ff  01    Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing unc_cha_llc_lookup.remote_other uncore cache Cache Lookups : Filters Requests for those that write info into the cache that come from a remote socket event=0x34,umask=0x1a02ff  01    Cache Lookups : Write Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Writeback transactions from L2 to the LLC  This includes all write transactions -- both Cacheable and UC unc_cha_llc_lookup.remote_rfo uncore cache Cache Lookups : RFO Requests that come from a Remote socket event=0x34,umask=0x1a08ff  01    Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC.  This includes RFO prefetch unc_cha_llc_lookup.remote_snoop_f uncore cache Cache Lookups : Remote snoop requests event=0x34  01    Cache Lookups : Remote snoop requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Remote snoop transactions to the LLC unc_cha_llc_lookup.remote_snp uncore cache Cache and Snoop Filter Lookups; Snoop Requests from a Remote Socket event=0x34,umask=0x1c19ff  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ.  This does not include lookups originating from the ISMQ unc_cha_llc_lookup.rfo uncore cache Cache Lookups : RFO Requests event=0x34,umask=0x1bc8ff  01    Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC.  This includes RFO prefetch unc_cha_llc_lookup.rfo_f uncore cache Cache Lookups : RFO Request Filter event=0x34  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC.  This includes RFO prefetch unc_cha_llc_lookup.rfo_local uncore cache Cache Lookups : Locally HOMed RFOs - Demand and Prefetches event=0x34,umask=0x9c8ff  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing unc_cha_llc_lookup.s uncore cache Cache Lookups : S State event=0x34,umask=0x10  01    Cache Lookups : S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Hit Shared State unc_cha_llc_lookup.sf_e uncore cache Cache Lookups : SnoopFilter - E State event=0x34,umask=4  01    Cache Lookups : SnoopFilter - E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : SF Hit Exclusive State unc_cha_llc_lookup.sf_h uncore cache Cache Lookups : SnoopFilter - H State event=0x34,umask=8  01    Cache Lookups : SnoopFilter - H State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : SF Hit HitMe State unc_cha_llc_lookup.sf_s uncore cache Cache Lookups : SnoopFilter - S State event=0x34,umask=2  01    Cache Lookups : SnoopFilter - S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : SF Hit Shared State unc_cha_llc_lookup.write_local uncore cache Cache Lookups : Writes event=0x34,umask=0x842ff  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Requests that install or change a line in the LLC.    Examples:  Writebacks from Core L2's and UPI.  Prefetches into the LLC unc_cha_llc_lookup.write_remote uncore cache Cache Lookups : Remote Writes event=0x34,umask=0x17c2ff  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing unc_cha_llc_victims.e_state uncore cache Lines Victimized : Lines in E state event=0x37,umask=2  01    Lines Victimized : Lines in E state : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.ia uncore cache Lines Victimized : IA traffic event=0x37,umask=0x20  01    Lines Victimized : IA traffic : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.io uncore cache Lines Victimized : IO traffic event=0x37,umask=0x10  01    Lines Victimized : IO traffic : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.io_e uncore cache All LLC lines in E state that are victimized on a fill from an IO device event=0x37,umask=0x12  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.io_fs uncore cache All LLC lines in F or S state that are victimized on a fill from an IO device event=0x37,umask=0x1c  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.io_m uncore cache All LLC lines in M state that are victimized on a fill from an IO device event=0x37,umask=0x11  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.io_mesf uncore cache All LLC lines in any state that are victimized on a fill from an IO device event=0x37,umask=0x1f  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.local_all uncore cache Lines Victimized; Local - All Lines event=0x37,umask=0x200f  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.local_e uncore cache Lines Victimized event=0x37,umask=0x2002  01    Lines Victimized : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.local_m uncore cache Lines Victimized event=0x37,umask=0x2001  01    Lines Victimized : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.local_only uncore cache Lines Victimized : Local Only event=0x37  01    Lines Victimized : Local Only : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.local_s uncore cache Lines Victimized event=0x37,umask=0x2004  01    Lines Victimized : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.m_state uncore cache Lines Victimized : Lines in M state event=0x37,umask=1  01    Lines Victimized : Lines in M state : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.remote_all uncore cache Lines Victimized; Remote - All Lines event=0x37,umask=0x800f  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.remote_e uncore cache Lines Victimized event=0x37,umask=0x8002  01    Lines Victimized : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.remote_m uncore cache Lines Victimized event=0x37,umask=0x8001  01    Lines Victimized : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.remote_only uncore cache Lines Victimized : Remote Only event=0x37  01    Lines Victimized : Remote Only : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.remote_s uncore cache Lines Victimized event=0x37,umask=0x8004  01    Lines Victimized : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.s_state uncore cache Lines Victimized : Lines in S State event=0x37,umask=4  01    Lines Victimized : Lines in S State : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.total_e uncore cache All LLC lines in E state that are victimized on a fill event=0x37,umask=2  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.total_m uncore cache All LLC lines in M state that are victimized on a fill event=0x37,umask=1  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.total_s uncore cache All LLC lines in S state that are victimized on a fill event=0x37,umask=4  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_misc.cv0_pref_miss uncore cache Cbo Misc : CV0 Prefetch Miss event=0x39,umask=0x20  01    Cbo Misc : CV0 Prefetch Miss : Miscellaneous events in the Cbo unc_cha_misc.cv0_pref_vic uncore cache Cbo Misc : CV0 Prefetch Victim event=0x39,umask=0x10  01    Cbo Misc : CV0 Prefetch Victim : Miscellaneous events in the Cbo unc_cha_misc.rspi_was_fse uncore cache Cbo Misc : Silent Snoop Eviction event=0x39,umask=1  01    Cbo Misc : Silent Snoop Eviction : Miscellaneous events in the Cbo. : Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction.  This is useful because this information is lost in the PRE encodings unc_cha_misc.wc_aliasing uncore cache Cbo Misc : Write Combining Aliasing event=0x39,umask=2  01    Cbo Misc : Write Combining Aliasing : Miscellaneous events in the Cbo. : Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write.  This occurs when there is WC aliasing unc_cha_osb.local_invitoe uncore cache OSB Snoop Broadcast : Local InvItoE event=0x55,umask=1  01    OSB Snoop Broadcast : Local InvItoE : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_cha_osb.local_read uncore cache OSB Snoop Broadcast : Local Rd event=0x55,umask=2  01    OSB Snoop Broadcast : Local Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_cha_osb.off_pwrheuristic uncore cache OSB Snoop Broadcast : Off event=0x55,umask=0x20  01    OSB Snoop Broadcast : Off : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_cha_osb.remote_read uncore cache OSB Snoop Broadcast : Remote Rd event=0x55,umask=4  01    OSB Snoop Broadcast : Remote Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_cha_osb.remote_readinvitoe uncore cache OSB Snoop Broadcast : Remote Rd InvItoE event=0x55,umask=8  01    OSB Snoop Broadcast : Remote Rd InvItoE : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_cha_osb.rfo_hits_snp_bcast uncore cache OSB Snoop Broadcast : RFO HitS Snoop Broadcast event=0x55,umask=0x10  01    OSB Snoop Broadcast : RFO HitS Snoop Broadcast : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB unc_cha_pmm_memmode_nm_invitox.local uncore cache UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL event=0x65,umask=1  01     unc_cha_pmm_memmode_nm_invitox.remote uncore cache UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE event=0x65,umask=2  01     unc_cha_pmm_memmode_nm_invitox.setconflict uncore cache UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT event=0x65,umask=4  01     unc_cha_pmm_memmode_nm_setconflicts.llc uncore cache Memory Mode related events; Counts the number of times CHA saw a Near Memory set conflict in SF/LLC event=0x64,umask=2  01    Near Memory evictions due to another read to the same Near Memory set in the LLC unc_cha_pmm_memmode_nm_setconflicts.sf uncore cache Memory Mode related events; Counts the number of times CHA saw a Near memory set conflict in SF/LLC event=0x64,umask=1  01    Near Memory evictions due to another read to the same Near Memory set in the SF unc_cha_pmm_memmode_nm_setconflicts.tor uncore cache Memory Mode related events; Counts the number of times CHA saw a Near Memory set conflict in TOR event=0x64,umask=4  01    No Reject in the CHA due to a pending read to the same Near Memory set in the TOR unc_cha_pmm_memmode_nm_setconflicts2.iodc uncore cache UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC event=0x70,umask=1  01     unc_cha_pmm_memmode_nm_setconflicts2.memwr uncore cache UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR event=0x70,umask=2  01     unc_cha_pmm_memmode_nm_setconflicts2.memwrni uncore cache UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI event=0x70,umask=4  01     unc_cha_pmm_qos.ddr4_fast_insert uncore cache UNC_CHA_PMM_QOS.DDR4_FAST_INSERT event=0x66,umask=2  01     unc_cha_pmm_qos.rej_irq uncore cache UNC_CHA_PMM_QOS.REJ_IRQ event=0x66,umask=8  01     unc_cha_pmm_qos.slowtorq_skip uncore cache UNC_CHA_PMM_QOS.SLOWTORQ_SKIP event=0x66,umask=0x40  01     unc_cha_pmm_qos.slow_insert uncore cache UNC_CHA_PMM_QOS.SLOW_INSERT event=0x66,umask=1  01     unc_cha_pmm_qos.throttle uncore cache UNC_CHA_PMM_QOS.THROTTLE event=0x66,umask=4  01     unc_cha_pmm_qos.throttle_irq uncore cache UNC_CHA_PMM_QOS.THROTTLE_IRQ event=0x66,umask=0x20  01     unc_cha_pmm_qos.throttle_prq uncore cache UNC_CHA_PMM_QOS.THROTTLE_PRQ event=0x66,umask=0x10  01     unc_cha_pmm_qos_occupancy.ddr_fast_fifo uncore cache UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO event=0x67,umask=2  01    : count # of FAST TOR Request inserted to ha_tor_req_fifo unc_cha_pmm_qos_occupancy.ddr_slow_fifo uncore cache Number of SLOW TOR Request inserted to ha_pmm_tor_req_fifo event=0x67,umask=1  01     unc_cha_read_no_credits.mc0 uncore cache CHA iMC CHNx READ Credits Empty : MC0 event=0x58,umask=1  01    CHA iMC CHNx READ Credits Empty : MC0 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 0 only unc_cha_read_no_credits.mc1 uncore cache CHA iMC CHNx READ Credits Empty : MC1 event=0x58,umask=2  01    CHA iMC CHNx READ Credits Empty : MC1 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 1 only unc_cha_read_no_credits.mc2 uncore cache CHA iMC CHNx READ Credits Empty : MC2 event=0x58,umask=4  01    CHA iMC CHNx READ Credits Empty : MC2 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 2 only unc_cha_read_no_credits.mc3 uncore cache CHA iMC CHNx READ Credits Empty : MC3 event=0x58,umask=8  01    CHA iMC CHNx READ Credits Empty : MC3 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 3 only unc_cha_read_no_credits.mc4 uncore cache CHA iMC CHNx READ Credits Empty : MC4 event=0x58,umask=0x10  01    CHA iMC CHNx READ Credits Empty : MC4 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 4 only unc_cha_read_no_credits.mc5 uncore cache CHA iMC CHNx READ Credits Empty : MC5 event=0x58,umask=0x20  01    CHA iMC CHNx READ Credits Empty : MC5 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 5 only unc_cha_requests.invitoe uncore cache Requests for exclusive ownership of a cache line without receiving data event=0x50,umask=0x30  01    Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA unc_cha_requests.invitoe_remote uncore cache Remote requests for exclusive ownership of a cache line  without receiving data event=0x50,umask=0x20  01    Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA unc_cha_requests.reads uncore cache Read requests made into the CHA event=0x50,umask=3  01    Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a  write)  unc_cha_requests.writes uncore cache Write requests made into the CHA event=0x50,umask=0xc  01    Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc unc_cha_rxc_inserts.ipq uncore cache Ingress (from CMS) Allocations : IPQ event=0x13,umask=4  01    Ingress (from CMS) Allocations : IPQ : Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.irq uncore cache Ingress (from CMS) Allocations : IRQ event=0x13,umask=1  01    Ingress (from CMS) Allocations : IRQ : Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.irq_rej uncore cache Ingress (from CMS) Allocations : IRQ Rejected event=0x13,umask=2  01    Ingress (from CMS) Allocations : IRQ Rejected : Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.prq uncore cache Ingress (from CMS) Allocations : PRQ event=0x13,umask=0x10  01    Ingress (from CMS) Allocations : PRQ : Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.prq_rej uncore cache Ingress (from CMS) Allocations : PRQ event=0x13,umask=0x20  01    Ingress (from CMS) Allocations : PRQ : Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.rrq uncore cache Ingress (from CMS) Allocations : RRQ event=0x13,umask=0x40  01    Ingress (from CMS) Allocations : RRQ : Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_inserts.wbq uncore cache Ingress (from CMS) Allocations : WBQ event=0x13,umask=0x80  01    Ingress (from CMS) Allocations : WBQ : Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_ipq0_reject.ad_req_vn0 uncore cache IPQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 event=0x22,umask=1  01    IPQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request unc_cha_rxc_ipq0_reject.ad_rsp_vn0 uncore cache IPQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 event=0x22,umask=2  01    IPQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response unc_cha_rxc_ipq0_reject.ak_non_upi uncore cache IPQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request event=0x22,umask=0x40  01    IPQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message unc_cha_rxc_ipq0_reject.bl_ncb_vn0 uncore cache IPQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 event=0x22,umask=0x10  01    IPQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB unc_cha_rxc_ipq0_reject.bl_ncs_vn0 uncore cache IPQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 event=0x22,umask=0x20  01    IPQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS unc_cha_rxc_ipq0_reject.bl_rsp_vn0 uncore cache IPQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 event=0x22,umask=4  01    IPQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response unc_cha_rxc_ipq0_reject.bl_wb_vn0 uncore cache IPQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 event=0x22,umask=8  01    IPQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback unc_cha_rxc_ipq0_reject.iv_non_upi uncore cache IPQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request event=0x22,umask=0x80  01    IPQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message unc_cha_rxc_ipq1_reject.allow_snp uncore cache IPQ Requests (from CMS) Rejected - Set 1 : Allow Snoop event=0x23,umask=0x40  01     unc_cha_rxc_ipq1_reject.any0 uncore cache IPQ Requests (from CMS) Rejected - Set 1 : ANY0 event=0x23,umask=1  01    IPQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the IPQ0 Reject counter was true unc_cha_rxc_ipq1_reject.ha uncore cache IPQ Requests (from CMS) Rejected - Set 1 : HA event=0x23,umask=2  01     unc_cha_rxc_ipq1_reject.llc_or_sf_way uncore cache IPQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way event=0x23,umask=0x20  01    IPQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way : Way conflict with another request that caused the reject unc_cha_rxc_ipq1_reject.llc_victim uncore cache IPQ Requests (from CMS) Rejected - Set 1 : LLC Victim event=0x23,umask=4  01     unc_cha_rxc_ipq1_reject.pa_match uncore cache IPQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match event=0x23,umask=0x80  01    IPQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match : Address match with an outstanding request that was rejected unc_cha_rxc_ipq1_reject.sf_victim uncore cache IPQ Requests (from CMS) Rejected - Set 1 : SF Victim event=0x23,umask=8  01    IPQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim unc_cha_rxc_ipq1_reject.victim uncore cache IPQ Requests (from CMS) Rejected - Set 1 : Victim event=0x23,umask=0x10  01     unc_cha_rxc_irq0_reject.ad_req_vn0 uncore cache IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 event=0x18,umask=1  01    IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request unc_cha_rxc_irq0_reject.ad_rsp_vn0 uncore cache IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 event=0x18,umask=2  01    IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response unc_cha_rxc_irq0_reject.ak_non_upi uncore cache IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request event=0x18,umask=0x40  01    IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message unc_cha_rxc_irq0_reject.bl_ncb_vn0 uncore cache IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 event=0x18,umask=0x10  01    IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB unc_cha_rxc_irq0_reject.bl_ncs_vn0 uncore cache IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 event=0x18,umask=0x20  01    IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS unc_cha_rxc_irq0_reject.bl_rsp_vn0 uncore cache IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 event=0x18,umask=4  01    IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response unc_cha_rxc_irq0_reject.bl_wb_vn0 uncore cache IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 event=0x18,umask=8  01    IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback unc_cha_rxc_irq0_reject.iv_non_upi uncore cache IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request event=0x18,umask=0x80  01    IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message unc_cha_rxc_irq1_reject.allow_snp uncore cache IRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop event=0x19,umask=0x40  01     unc_cha_rxc_irq1_reject.any0 uncore cache IRQ Requests (from CMS) Rejected - Set 1 : ANY0 event=0x19,umask=1  01    IRQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the IRQ0 Reject counter was true unc_cha_rxc_irq1_reject.ha uncore cache IRQ Requests (from CMS) Rejected - Set 1 : HA event=0x19,umask=2  01     unc_cha_rxc_irq1_reject.llc_or_sf_way uncore cache IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way event=0x19,umask=0x20  01    IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way : Way conflict with another request that caused the reject unc_cha_rxc_irq1_reject.llc_victim uncore cache IRQ Requests (from CMS) Rejected - Set 1 : LLC Victim event=0x19,umask=4  01     unc_cha_rxc_irq1_reject.sf_victim uncore cache IRQ Requests (from CMS) Rejected - Set 1 : SF Victim event=0x19,umask=8  01    IRQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim unc_cha_rxc_irq1_reject.victim uncore cache IRQ Requests (from CMS) Rejected - Set 1 : Victim event=0x19,umask=0x10  01     unc_cha_rxc_ismq0_reject.ad_req_vn0 uncore cache ISMQ Rejects - Set 0 : AD REQ on VN0 event=0x24,umask=1  01    ISMQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a request unc_cha_rxc_ismq0_reject.ad_rsp_vn0 uncore cache ISMQ Rejects - Set 0 : AD RSP on VN0 event=0x24,umask=2  01    ISMQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a response unc_cha_rxc_ismq0_reject.ak_non_upi uncore cache ISMQ Rejects - Set 0 : Non UPI AK Request event=0x24,umask=0x40  01    ISMQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject AK ring message unc_cha_rxc_ismq0_reject.bl_ncb_vn0 uncore cache ISMQ Rejects - Set 0 : BL NCB on VN0 event=0x24,umask=0x10  01    ISMQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCB unc_cha_rxc_ismq0_reject.bl_ncs_vn0 uncore cache ISMQ Rejects - Set 0 : BL NCS on VN0 event=0x24,umask=0x20  01    ISMQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCS unc_cha_rxc_ismq0_reject.bl_rsp_vn0 uncore cache ISMQ Rejects - Set 0 : BL RSP on VN0 event=0x24,umask=4  01    ISMQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a response unc_cha_rxc_ismq0_reject.bl_wb_vn0 uncore cache ISMQ Rejects - Set 0 : BL WB on VN0 event=0x24,umask=8  01    ISMQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a writeback unc_cha_rxc_ismq0_reject.iv_non_upi uncore cache ISMQ Rejects - Set 0 : Non UPI IV Request event=0x24,umask=0x80  01    ISMQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject IV ring message unc_cha_rxc_ismq0_retry.ad_req_vn0 uncore cache ISMQ Retries - Set 0 : AD REQ on VN0 event=0x2c,umask=1  01    ISMQ Retries - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a request unc_cha_rxc_ismq0_retry.ad_rsp_vn0 uncore cache ISMQ Retries - Set 0 : AD RSP on VN0 event=0x2c,umask=2  01    ISMQ Retries - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a response unc_cha_rxc_ismq0_retry.ak_non_upi uncore cache ISMQ Retries - Set 0 : Non UPI AK Request event=0x2c,umask=0x40  01    ISMQ Retries - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject AK ring message unc_cha_rxc_ismq0_retry.bl_ncb_vn0 uncore cache ISMQ Retries - Set 0 : BL NCB on VN0 event=0x2c,umask=0x10  01    ISMQ Retries - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCB unc_cha_rxc_ismq0_retry.bl_ncs_vn0 uncore cache ISMQ Retries - Set 0 : BL NCS on VN0 event=0x2c,umask=0x20  01    ISMQ Retries - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCS unc_cha_rxc_ismq0_retry.bl_rsp_vn0 uncore cache ISMQ Retries - Set 0 : BL RSP on VN0 event=0x2c,umask=4  01    ISMQ Retries - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a response unc_cha_rxc_ismq0_retry.bl_wb_vn0 uncore cache ISMQ Retries - Set 0 : BL WB on VN0 event=0x2c,umask=8  01    ISMQ Retries - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a writeback unc_cha_rxc_ismq0_retry.iv_non_upi uncore cache ISMQ Retries - Set 0 : Non UPI IV Request event=0x2c,umask=0x80  01    ISMQ Retries - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject IV ring message unc_cha_rxc_ismq1_reject.any0 uncore cache ISMQ Rejects - Set 1 : ANY0 event=0x25,umask=1  01    ISMQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : Any condition listed in the ISMQ0 Reject counter was true unc_cha_rxc_ismq1_reject.ha uncore cache ISMQ Rejects - Set 1 : HA event=0x25,umask=2  01    ISMQ Rejects - Set 1 : HA : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_ismq1_retry.any0 uncore cache ISMQ Retries - Set 1 : ANY0 event=0x2d,umask=1  01    ISMQ Retries - Set 1 : ANY0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : Any condition listed in the ISMQ0 Reject counter was true unc_cha_rxc_ismq1_retry.ha uncore cache ISMQ Retries - Set 1 : HA event=0x2d,umask=2  01    ISMQ Retries - Set 1 : HA : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores unc_cha_rxc_occupancy.ipq uncore cache Ingress (from CMS) Occupancy : IPQ event=0x11,umask=4  01    Ingress (from CMS) Occupancy : IPQ : Counts number of entries in the specified Ingress queue in each cycle unc_cha_rxc_occupancy.rrq uncore cache Ingress (from CMS) Occupancy : RRQ event=0x11,umask=0x40  01    Ingress (from CMS) Occupancy : RRQ : Counts number of entries in the specified Ingress queue in each cycle unc_cha_rxc_occupancy.wbq uncore cache Ingress (from CMS) Occupancy : WBQ event=0x11,umask=0x80  01    Ingress (from CMS) Occupancy : WBQ : Counts number of entries in the specified Ingress queue in each cycle unc_cha_rxc_other0_retry.ad_req_vn0 uncore cache Other Retries - Set 0 : AD REQ on VN0 event=0x2e,umask=1  01    Other Retries - Set 0 : AD REQ on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No AD VN0 credit for generating a request unc_cha_rxc_other0_retry.ad_rsp_vn0 uncore cache Other Retries - Set 0 : AD RSP on VN0 event=0x2e,umask=2  01    Other Retries - Set 0 : AD RSP on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No AD VN0 credit for generating a response unc_cha_rxc_other0_retry.ak_non_upi uncore cache Other Retries - Set 0 : Non UPI AK Request event=0x2e,umask=0x40  01    Other Retries - Set 0 : Non UPI AK Request : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Can't inject AK ring message unc_cha_rxc_other0_retry.bl_ncb_vn0 uncore cache Other Retries - Set 0 : BL NCB on VN0 event=0x2e,umask=0x10  01    Other Retries - Set 0 : BL NCB on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for NCB unc_cha_rxc_other0_retry.bl_ncs_vn0 uncore cache Other Retries - Set 0 : BL NCS on VN0 event=0x2e,umask=0x20  01    Other Retries - Set 0 : BL NCS on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for NCS unc_cha_rxc_other0_retry.bl_rsp_vn0 uncore cache Other Retries - Set 0 : BL RSP on VN0 event=0x2e,umask=4  01    Other Retries - Set 0 : BL RSP on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for generating a response unc_cha_rxc_other0_retry.bl_wb_vn0 uncore cache Other Retries - Set 0 : BL WB on VN0 event=0x2e,umask=8  01    Other Retries - Set 0 : BL WB on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for generating a writeback unc_cha_rxc_other0_retry.iv_non_upi uncore cache Other Retries - Set 0 : Non UPI IV Request event=0x2e,umask=0x80  01    Other Retries - Set 0 : Non UPI IV Request : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Can't inject IV ring message unc_cha_rxc_other1_retry.allow_snp uncore cache Other Retries - Set 1 : Allow Snoop event=0x2f,umask=0x40  01    Other Retries - Set 1 : Allow Snoop : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.any0 uncore cache Other Retries - Set 1 : ANY0 event=0x2f,umask=1  01    Other Retries - Set 1 : ANY0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Any condition listed in the Other0 Reject counter was true unc_cha_rxc_other1_retry.ha uncore cache Other Retries - Set 1 : HA event=0x2f,umask=2  01    Other Retries - Set 1 : HA : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.llc_or_sf_way uncore cache Other Retries - Set 1 : LLC OR SF Way event=0x2f,umask=0x20  01    Other Retries - Set 1 : LLC OR SF Way : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Way conflict with another request that caused the reject unc_cha_rxc_other1_retry.llc_victim uncore cache Other Retries - Set 1 : LLC Victim event=0x2f,umask=4  01    Other Retries - Set 1 : LLC Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_other1_retry.pa_match uncore cache Other Retries - Set 1 : PhyAddr Match event=0x2f,umask=0x80  01    Other Retries - Set 1 : PhyAddr Match : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Address match with an outstanding request that was rejected unc_cha_rxc_other1_retry.sf_victim uncore cache Other Retries - Set 1 : SF Victim event=0x2f,umask=8  01    Other Retries - Set 1 : SF Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Requests did not generate Snoop filter victim unc_cha_rxc_other1_retry.victim uncore cache Other Retries - Set 1 : Victim event=0x2f,umask=0x10  01    Other Retries - Set 1 : Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) unc_cha_rxc_prq0_reject.ad_req_vn0 uncore cache PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 event=0x20,umask=1  01    PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request unc_cha_rxc_prq0_reject.ad_rsp_vn0 uncore cache PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 event=0x20,umask=2  01    PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response unc_cha_rxc_prq0_reject.ak_non_upi uncore cache PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request event=0x20,umask=0x40  01    PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message unc_cha_rxc_prq0_reject.bl_ncb_vn0 uncore cache PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 event=0x20,umask=0x10  01    PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB unc_cha_rxc_prq0_reject.bl_ncs_vn0 uncore cache PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 event=0x20,umask=0x20  01    PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS unc_cha_rxc_prq0_reject.bl_rsp_vn0 uncore cache PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 event=0x20,umask=4  01    PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response unc_cha_rxc_prq0_reject.bl_wb_vn0 uncore cache PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 event=0x20,umask=8  01    PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback unc_cha_rxc_prq0_reject.iv_non_upi uncore cache PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request event=0x20,umask=0x80  01    PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message unc_cha_rxc_prq1_reject.allow_snp uncore cache PRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop event=0x21,umask=0x40  01     unc_cha_rxc_prq1_reject.any0 uncore cache PRQ Requests (from CMS) Rejected - Set 1 : ANY0 event=0x21,umask=1  01    PRQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the PRQ0 Reject counter was true unc_cha_rxc_prq1_reject.ha uncore cache PRQ Requests (from CMS) Rejected - Set 1 : HA event=0x21,umask=2  01     unc_cha_rxc_prq1_reject.llc_or_sf_way uncore cache PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way event=0x21,umask=0x20  01    PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way : Way conflict with another request that caused the reject unc_cha_rxc_prq1_reject.llc_victim uncore cache PRQ Requests (from CMS) Rejected - Set 1 : LLC Victim event=0x21,umask=4  01     unc_cha_rxc_prq1_reject.pa_match uncore cache PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match event=0x21,umask=0x80  01    PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match : Address match with an outstanding request that was rejected unc_cha_rxc_prq1_reject.sf_victim uncore cache PRQ Requests (from CMS) Rejected - Set 1 : SF Victim event=0x21,umask=8  01    PRQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim unc_cha_rxc_prq1_reject.victim uncore cache PRQ Requests (from CMS) Rejected - Set 1 : Victim event=0x21,umask=0x10  01     unc_cha_rxc_req_q0_retry.ad_req_vn0 uncore cache Request Queue Retries - Set 0 : AD REQ on VN0 event=0x2a,umask=1  01    Request Queue Retries - Set 0 : AD REQ on VN0 : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No AD VN0 credit for generating a request unc_cha_rxc_req_q0_retry.ad_rsp_vn0 uncore cache Request Queue Retries - Set 0 : AD RSP on VN0 event=0x2a,umask=2  01    Request Queue Retries - Set 0 : AD RSP on VN0 : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No AD VN0 credit for generating a response unc_cha_rxc_req_q0_retry.ak_non_upi uncore cache Request Queue Retries - Set 0 : Non UPI AK Request event=0x2a,umask=0x40  01    Request Queue Retries - Set 0 : Non UPI AK Request : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Can't inject AK ring message unc_cha_rxc_req_q0_retry.bl_ncb_vn0 uncore cache Request Queue Retries - Set 0 : BL NCB on VN0 event=0x2a,umask=0x10  01    Request Queue Retries - Set 0 : BL NCB on VN0 : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for NCB unc_cha_rxc_req_q0_retry.bl_ncs_vn0 uncore cache Request Queue Retries - Set 0 : BL NCS on VN0 event=0x2a,umask=0x20  01    Request Queue Retries - Set 0 : BL NCS on VN0 : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for NCS unc_cha_rxc_req_q0_retry.bl_rsp_vn0 uncore cache Request Queue Retries - Set 0 : BL RSP on VN0 event=0x2a,umask=4  01    Request Queue Retries - Set 0 : BL RSP on VN0 : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for generating a response unc_cha_rxc_req_q0_retry.bl_wb_vn0 uncore cache Request Queue Retries - Set 0 : BL WB on VN0 event=0x2a,umask=8  01    Request Queue Retries - Set 0 : BL WB on VN0 : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for generating a writeback unc_cha_rxc_req_q0_retry.iv_non_upi uncore cache Request Queue Retries - Set 0 : Non UPI IV Request event=0x2a,umask=0x80  01    Request Queue Retries - Set 0 : Non UPI IV Request : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Can't inject IV ring message unc_cha_rxc_req_q1_retry.allow_snp uncore cache Request Queue Retries - Set 1 : Allow Snoop event=0x2b,umask=0x40  01    Request Queue Retries - Set 1 : Allow Snoop : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.any0 uncore cache Request Queue Retries - Set 1 : ANY0 event=0x2b,umask=1  01    Request Queue Retries - Set 1 : ANY0 : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Any condition listed in the WBQ0 Reject counter was true unc_cha_rxc_req_q1_retry.ha uncore cache Request Queue Retries - Set 1 : HA event=0x2b,umask=2  01    Request Queue Retries - Set 1 : HA : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.llc_or_sf_way uncore cache Request Queue Retries - Set 1 : LLC OR SF Way event=0x2b,umask=0x20  01    Request Queue Retries - Set 1 : LLC OR SF Way : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Way conflict with another request that caused the reject unc_cha_rxc_req_q1_retry.llc_victim uncore cache Request Queue Retries - Set 1 : LLC Victim event=0x2b,umask=4  01    Request Queue Retries - Set 1 : LLC Victim : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_req_q1_retry.pa_match uncore cache Request Queue Retries - Set 1 : PhyAddr Match event=0x2b,umask=0x80  01    Request Queue Retries - Set 1 : PhyAddr Match : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Address match with an outstanding request that was rejected unc_cha_rxc_req_q1_retry.sf_victim uncore cache Request Queue Retries - Set 1 : SF Victim event=0x2b,umask=8  01    Request Queue Retries - Set 1 : SF Victim : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Requests did not generate Snoop filter victim unc_cha_rxc_req_q1_retry.victim uncore cache Request Queue Retries - Set 1 : Victim event=0x2b,umask=0x10  01    Request Queue Retries - Set 1 : Victim : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) unc_cha_rxc_rrq0_reject.ad_req_vn0 uncore cache RRQ Rejects - Set 0 : AD REQ on VN0 event=0x26,umask=1  01    RRQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No AD VN0 credit for generating a request unc_cha_rxc_rrq0_reject.ad_rsp_vn0 uncore cache RRQ Rejects - Set 0 : AD RSP on VN0 event=0x26,umask=2  01    RRQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No AD VN0 credit for generating a response unc_cha_rxc_rrq0_reject.ak_non_upi uncore cache RRQ Rejects - Set 0 : Non UPI AK Request event=0x26,umask=0x40  01    RRQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Can't inject AK ring message unc_cha_rxc_rrq0_reject.bl_ncb_vn0 uncore cache RRQ Rejects - Set 0 : BL NCB on VN0 event=0x26,umask=0x10  01    RRQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for NCB unc_cha_rxc_rrq0_reject.bl_ncs_vn0 uncore cache RRQ Rejects - Set 0 : BL NCS on VN0 event=0x26,umask=0x20  01    RRQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for NCS unc_cha_rxc_rrq0_reject.bl_rsp_vn0 uncore cache RRQ Rejects - Set 0 : BL RSP on VN0 event=0x26,umask=4  01    RRQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for generating a response unc_cha_rxc_rrq0_reject.bl_wb_vn0 uncore cache RRQ Rejects - Set 0 : BL WB on VN0 event=0x26,umask=8  01    RRQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for generating a writeback unc_cha_rxc_rrq0_reject.iv_non_upi uncore cache RRQ Rejects - Set 0 : Non UPI IV Request event=0x26,umask=0x80  01    RRQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Can't inject IV ring message unc_cha_rxc_rrq1_reject.allow_snp uncore cache RRQ Rejects - Set 1 : Allow Snoop event=0x27,umask=0x40  01    RRQ Rejects - Set 1 : Allow Snoop : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.any0 uncore cache RRQ Rejects - Set 1 : ANY0 event=0x27,umask=1  01    RRQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Any condition listed in the RRQ0 Reject counter was true unc_cha_rxc_rrq1_reject.ha uncore cache RRQ Rejects - Set 1 : HA event=0x27,umask=2  01    RRQ Rejects - Set 1 : HA : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.llc_or_sf_way uncore cache RRQ Rejects - Set 1 : LLC OR SF Way event=0x27,umask=0x20  01    RRQ Rejects - Set 1 : LLC OR SF Way : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Way conflict with another request that caused the reject unc_cha_rxc_rrq1_reject.llc_victim uncore cache RRQ Rejects - Set 1 : LLC Victim event=0x27,umask=4  01    RRQ Rejects - Set 1 : LLC Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_rrq1_reject.pa_match uncore cache RRQ Rejects - Set 1 : PhyAddr Match event=0x27,umask=0x80  01    RRQ Rejects - Set 1 : PhyAddr Match : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Address match with an outstanding request that was rejected unc_cha_rxc_rrq1_reject.sf_victim uncore cache RRQ Rejects - Set 1 : SF Victim event=0x27,umask=8  01    RRQ Rejects - Set 1 : SF Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Requests did not generate Snoop filter victim unc_cha_rxc_rrq1_reject.victim uncore cache RRQ Rejects - Set 1 : Victim event=0x27,umask=0x10  01    RRQ Rejects - Set 1 : Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry unc_cha_rxc_wbq0_reject.ad_req_vn0 uncore cache WBQ Rejects - Set 0 : AD REQ on VN0 event=0x28,umask=1  01    WBQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No AD VN0 credit for generating a request unc_cha_rxc_wbq0_reject.ad_rsp_vn0 uncore cache WBQ Rejects - Set 0 : AD RSP on VN0 event=0x28,umask=2  01    WBQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No AD VN0 credit for generating a response unc_cha_rxc_wbq0_reject.ak_non_upi uncore cache WBQ Rejects - Set 0 : Non UPI AK Request event=0x28,umask=0x40  01    WBQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Can't inject AK ring message unc_cha_rxc_wbq0_reject.bl_ncb_vn0 uncore cache WBQ Rejects - Set 0 : BL NCB on VN0 event=0x28,umask=0x10  01    WBQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for NCB unc_cha_rxc_wbq0_reject.bl_ncs_vn0 uncore cache WBQ Rejects - Set 0 : BL NCS on VN0 event=0x28,umask=0x20  01    WBQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for NCS unc_cha_rxc_wbq0_reject.bl_rsp_vn0 uncore cache WBQ Rejects - Set 0 : BL RSP on VN0 event=0x28,umask=4  01    WBQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for generating a response unc_cha_rxc_wbq0_reject.bl_wb_vn0 uncore cache WBQ Rejects - Set 0 : BL WB on VN0 event=0x28,umask=8  01    WBQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for generating a writeback unc_cha_rxc_wbq0_reject.iv_non_upi uncore cache WBQ Rejects - Set 0 : Non UPI IV Request event=0x28,umask=0x80  01    WBQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Can't inject IV ring message unc_cha_rxc_wbq1_reject.allow_snp uncore cache WBQ Rejects - Set 1 : Allow Snoop event=0x29,umask=0x40  01    WBQ Rejects - Set 1 : Allow Snoop : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.any0 uncore cache WBQ Rejects - Set 1 : ANY0 event=0x29,umask=1  01    WBQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Any condition listed in the WBQ0 Reject counter was true unc_cha_rxc_wbq1_reject.ha uncore cache WBQ Rejects - Set 1 : HA event=0x29,umask=2  01    WBQ Rejects - Set 1 : HA : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.llc_or_sf_way uncore cache WBQ Rejects - Set 1 : LLC OR SF Way event=0x29,umask=0x20  01    WBQ Rejects - Set 1 : LLC OR SF Way : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Way conflict with another request that caused the reject unc_cha_rxc_wbq1_reject.llc_victim uncore cache WBQ Rejects - Set 1 : LLC Victim event=0x29,umask=4  01    WBQ Rejects - Set 1 : LLC Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_rxc_wbq1_reject.pa_match uncore cache WBQ Rejects - Set 1 : PhyAddr Match event=0x29,umask=0x80  01    WBQ Rejects - Set 1 : PhyAddr Match : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Address match with an outstanding request that was rejected unc_cha_rxc_wbq1_reject.sf_victim uncore cache WBQ Rejects - Set 1 : SF Victim event=0x29,umask=8  01    WBQ Rejects - Set 1 : SF Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Requests did not generate Snoop filter victim unc_cha_rxc_wbq1_reject.victim uncore cache WBQ Rejects - Set 1 : Victim event=0x29,umask=0x10  01    WBQ Rejects - Set 1 : Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry unc_cha_snoops_sent.all uncore cache Snoops Sent : All event=0x51,umask=1  01    Snoops Sent : All : Counts the number of snoops issued by the HA unc_cha_snoops_sent.bcst_local uncore cache Snoops Sent : Broadcast snoop for Local Requests event=0x51,umask=0x10  01    Snoops Sent : Broadcast snoop for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast snoops issued by the HA. This filter includes only requests coming from local sockets unc_cha_snoops_sent.bcst_remote uncore cache Snoops Sent : Broadcast snoops for Remote Requests event=0x51,umask=0x20  01    Snoops Sent : Broadcast snoops for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast snoops issued by the HA.This filter includes only requests coming from remote sockets unc_cha_snoops_sent.direct_local uncore cache Snoops Sent : Directed snoops for Local Requests event=0x51,umask=0x40  01    Snoops Sent : Directed snoops for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of directed snoops issued by the HA. This filter includes only requests coming from local sockets unc_cha_snoops_sent.direct_remote uncore cache Snoops Sent : Directed snoops for Remote Requests event=0x51,umask=0x80  01    Snoops Sent : Directed snoops for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of directed snoops issued by the HA. This filter includes only requests coming from remote sockets unc_cha_snoops_sent.local uncore cache Snoops Sent : Broadcast or directed Snoops sent for Local Requests event=0x51,umask=4  01    Snoops Sent : Broadcast or directed Snoops sent for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast or directed snoops issued by the HA per request. This filter includes only requests coming from the local socket unc_cha_snoops_sent.remote uncore cache Snoops Sent : Broadcast or directed Snoops sent for Remote Requests event=0x51,umask=8  01    Snoops Sent : Broadcast or directed Snoops sent for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast or directed snoops issued by the HA per request. This filter includes only requests coming from the remote socket unc_cha_snoop_resp.rspcnflct uncore cache Snoop Responses Received : RSPCNFLCT* event=0x5c,umask=0x40  01    Snoop Responses Received : RSPCNFLCT* : Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for snoops responses of RspConflict.  This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent.  This triggers conflict resolution hardware.  This covers both RspCnflct and RspCnflctWbI unc_cha_snoop_resp.rspfwd uncore cache Snoop Responses Received : RspFwd event=0x5c,umask=0x80  01    Snoop Responses Received : RspFwd : Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of RspFwd to a CA request.  This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state unc_cha_snoop_resp.rspfwdwb uncore cache Snoop Responses Received : Rsp*Fwd*WB event=0x5c,umask=0x20  01    Snoop Responses Received : Rsp*Fwd*WB : Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of Rsp*Fwd*WB.  This snoop response is only used in 4s systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory unc_cha_snoop_resp.rsps uncore cache RspS Snoop Responses Received event=0x5c,umask=2  01    Counts when a transaction with the opcode type RspS Snoop Response was received which indicates when a remote cache has data but is not forwarding it.  It is a way to let the requesting socket know that it cannot allocate the data in E state.  No data is sent with S RspS unc_cha_snoop_resp.rspwb uncore cache Snoop Responses Received : Rsp*WB event=0x5c,umask=0x10  01    Snoop Responses Received : Rsp*WB : Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of RspIWB or RspSWB.  This is returned when a non-RFO request hits in M state.  Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured.  InvItoE transactions will also return RspIWB because they must acquire ownership unc_cha_snoop_resp_local.rspcnflct uncore cache Snoop Responses Received Local : RspCnflct event=0x5d,umask=0x40  01    Snoop Responses Received Local : RspCnflct : Number of snoop responses received for a Local  request : Filters for snoops responses of RspConflict to local CA requests.  This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent.  This triggers conflict resolution hardware.  This covers both RspCnflct and RspCnflctWbI unc_cha_snoop_resp_local.rspfwd uncore cache Snoop Responses Received Local : RspFwd event=0x5d,umask=0x80  01    Snoop Responses Received Local : RspFwd : Number of snoop responses received for a Local  request : Filters for a snoop response of RspFwd to local CA requests.  This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state unc_cha_snoop_resp_local.rspfwdwb uncore cache Snoop Responses Received Local : Rsp*FWD*WB event=0x5d,umask=0x20  01    Snoop Responses Received Local : Rsp*FWD*WB : Number of snoop responses received for a Local  request : Filters for a snoop response of Rsp*Fwd*WB to local CA requests.  This snoop response is only used in 4s systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory unc_cha_snoop_resp_local.rspi uncore cache Snoop Responses Received Local : RspI event=0x5d,umask=1  01    Snoop Responses Received Local : RspI : Number of snoop responses received for a Local  request : Filters for snoops responses of RspI to local CA requests.  RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data) unc_cha_snoop_resp_local.rspifwd uncore cache Snoop Responses Received Local : RspIFwd event=0x5d,umask=4  01    Snoop Responses Received Local : RspIFwd : Number of snoop responses received for a Local  request : Filters for snoop responses of RspIFwd to local CA requests.  This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states.  This is commonly returned with RFO transactions.  It can be either a HitM or a HitFE unc_cha_snoop_resp_local.rsps uncore cache Snoop Responses Received Local : RspS event=0x5d,umask=2  01    Snoop Responses Received Local : RspS : Number of snoop responses received for a Local  request : Filters for snoop responses of RspS to local CA requests.  RspS is returned when a remote cache has data but is not forwarding it.  It is a way to let the requesting socket know that it cannot allocate the data in E state.  No data is sent with S RspS unc_cha_snoop_resp_local.rspsfwd uncore cache Snoop Responses Received Local : RspSFwd event=0x5d,umask=8  01    Snoop Responses Received Local : RspSFwd : Number of snoop responses received for a Local  request : Filters for a snoop response of RspSFwd to local CA requests.  This is returned when a remote caching agent forwards data but holds on to its current copy.  This is common for data and code reads that hit in a remote socket in E or F state unc_cha_snoop_resp_local.rspwb uncore cache Snoop Responses Received Local : Rsp*WB event=0x5d,umask=0x10  01    Snoop Responses Received Local : Rsp*WB : Number of snoop responses received for a Local  request : Filters for a snoop response of RspIWB or RspSWB to local CA requests.  This is returned when a non-RFO request hits in M state.  Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured.  InvItoE transactions will also return RspIWB because they must acquire ownership unc_cha_snoop_rsp_misc.mtoi_rspdatam uncore cache Misc Snoop Responses Received : MtoI RspIDataM event=0x6b,umask=2  01     unc_cha_snoop_rsp_misc.mtoi_rspifwdm uncore cache Misc Snoop Responses Received : MtoI RspIFwdM event=0x6b,umask=1  01     unc_cha_snoop_rsp_misc.pulldataptl_hitllc uncore cache Misc Snoop Responses Received : Pull Data Partial - Hit LLC event=0x6b,umask=0x20  01     unc_cha_snoop_rsp_misc.pulldataptl_hitsf uncore cache Misc Snoop Responses Received : Pull Data Partial - Hit SF event=0x6b,umask=0x10  01     unc_cha_snoop_rsp_misc.rspifwdmptl_hitllc uncore cache Misc Snoop Responses Received : RspIFwdPtl Hit LLC event=0x6b,umask=8  01     unc_cha_snoop_rsp_misc.rspifwdmptl_hitsf uncore cache Misc Snoop Responses Received : RspIFwdPtl Hit SF event=0x6b,umask=4  01     unc_cha_tor_inserts.all uncore cache TOR Inserts : All event=0x35,umask=0xc001ffff  01    TOR Inserts : All : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.ddr uncore cache TOR Inserts : DDR Access event=0x35  01    TOR Inserts : DDR Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.evict uncore cache TOR Inserts : SF/LLC Evictions event=0x35,umask=2  01    TOR Inserts : SF/LLC Evictions : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ) unc_cha_tor_inserts.hit uncore cache TOR Inserts : Just Hits event=0x35  01    TOR Inserts : Just Hits : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.ia uncore cache TOR Inserts; All from Local IA event=0x35,umask=0xc001ff01  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally initiated requests from IA Cores unc_cha_tor_inserts.ia_clflush uncore cache TOR Inserts;CLFlush from Local IA event=0x35,umask=0xc8c7ff01  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; CLFlush events that are initiated from the Core unc_cha_tor_inserts.ia_clflushopt uncore cache TOR Inserts;CLFlushOpt from Local IA event=0x35,umask=0xc8d7ff01  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; CLFlushOpt events that are initiated from the Core unc_cha_tor_inserts.ia_crd uncore cache TOR Inserts; CRd from local IA event=0x35,umask=0xc80fff01  01    TOR Inserts; Code read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_crd_pref uncore cache TOR Inserts; CRd Pref from local IA event=0x35,umask=0xc88fff01  01    TOR Inserts; Code read prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_drd uncore cache TOR Inserts; DRd from local IA event=0x35,umask=0xc817ff01  01    TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_drdpte uncore cache TOR Inserts : DRd PTEs issued by iA Cores event=0x35,umask=0xc837ff01  01    TOR Inserts : DRd PTEs issued by iA Cores due to a page walk : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_drd_opt uncore cache TOR Inserts; DRd Opt from local IA event=0x35,umask=0xc827ff01  01    TOR Inserts; Data read opt from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_drd_opt_pref uncore cache TOR Inserts; DRd Opt Pref from local IA event=0x35,umask=0xc8a7ff01  01    TOR Inserts; Data read opt prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_drd_pref uncore cache TOR Inserts; DRd Pref from local IA event=0x35,umask=0xc897ff01  01    TOR Inserts; Data read prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_hit uncore cache TOR Inserts; Hits from Local IA event=0x35,umask=0xc001fd01  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.ia_hit_crd uncore cache TOR Inserts; CRd hits from local IA event=0x35,umask=0xc80ffd01  01    TOR Inserts; Code read from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_hit_crd_pref uncore cache TOR Inserts; CRd Pref hits from local IA event=0x35,umask=0xc88ffd01  01    TOR Inserts; Code read prefetch from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_hit_cxl_acc uncore cache All requests issued from IA cores to CXL accelerator memory regions that hit the LLC event=0x35,umask=0x10c0018101  01     unc_cha_tor_inserts.ia_hit_cxl_acc_local uncore cache UNC_CHA_TOR_INSERTS.IA_HIT_CXL_ACC_LOCAL event=0x35,umask=0x10c0008101  01     unc_cha_tor_inserts.ia_hit_drd uncore cache TOR Inserts; DRd hits from local IA event=0x35,umask=0xc817fd01  01    TOR Inserts; Data read from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_hit_drdpte uncore cache TOR Inserts : DRd PTEs issued by iA Cores that Hit the LLC event=0x35,umask=0xc837fd01  01    TOR Inserts : DRd PTEs issued by iA Cores due to page walks that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_drd_opt uncore cache TOR Inserts; DRd Opt hits from local IA event=0x35,umask=0xc827fd01  01    TOR Inserts; Data read opt from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_hit_drd_opt_pref uncore cache TOR Inserts; DRd Opt Pref hits from local IA event=0x35,umask=0xc8a7fd01  01    TOR Inserts; Data read opt prefetch from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_hit_drd_pref uncore cache TOR Inserts; DRd Pref hits from local IA event=0x35,umask=0xc897fd01  01    TOR Inserts; Data read prefetch from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_hit_itom uncore cache TOR Inserts : ItoMs issued by iA Cores that Hit LLC event=0x35,umask=0xcc47fd01  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_llcprefcode uncore cache TOR Inserts; LLCPrefCode hits from local IA event=0x35,umask=0xcccffd01  01    TOR Inserts; Last level cache prefetch code read from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_hit_llcprefdata uncore cache TOR Inserts; LLCPrefData hits from local IA event=0x35,umask=0xccd7fd01  01    TOR Inserts; Last level cache prefetch data read from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_hit_llcprefrfo uncore cache TOR Inserts; LLCPrefRFO hits from local IA event=0x35,umask=0xccc7fd01  01    TOR Inserts; Last level cache prefetch read for ownership from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_hit_rfo uncore cache TOR Inserts; RFO hits from local IA event=0x35,umask=0xc807fd01  01    TOR Inserts; Read for ownership from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_hit_rfo_pref uncore cache TOR Inserts; RFO Pref hits from local IA event=0x35,umask=0xc887fd01  01    TOR Inserts; Read for ownership prefetch from local IA that hits in the snoop filter unc_cha_tor_inserts.ia_itom uncore cache TOR Inserts;ItoM from Local IA event=0x35,umask=0xcc47ff01  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; ItoM events that are initiated from the Core unc_cha_tor_inserts.ia_itomcachenear uncore cache TOR Inserts : ItoMCacheNears issued by iA Cores event=0x35,umask=0xcd47ff01  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_llcprefcode uncore cache TOR Inserts; LLCPrefCode from local IA event=0x35,umask=0xcccfff01  01    TOR Inserts; Last level cache prefetch code read from local IA unc_cha_tor_inserts.ia_llcprefdata uncore cache TOR Inserts; LLCPrefData from local IA event=0x35,umask=0xccd7ff01  01    TOR Inserts; Last level cache prefetch data read from local IA unc_cha_tor_inserts.ia_llcprefrfo uncore cache TOR Inserts; LLCPrefRFO from local IA event=0x35,umask=0xccc7ff01  01    TOR Inserts; Last level cache prefetch read for ownership from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss uncore cache TOR Inserts; misses from Local IA event=0x35,umask=0xc001fe01  01    TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd uncore cache TOR Inserts for CRd misses from local IA event=0x35,umask=0xc80ffe01  01    Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode CRd unc_cha_tor_inserts.ia_miss_crdmorph_cxl_acc uncore cache CRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x35,umask=0x10c80b8201  01     unc_cha_tor_inserts.ia_miss_crd_local uncore cache TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally event=0x35,umask=0xc80efe01  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd_pref uncore cache TOR Inserts; CRd Pref misses from local IA event=0x35,umask=0xc88ffe01  01    TOR Inserts; Code read prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_crd_pref_local uncore cache TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally event=0x35,umask=0xc88efe01  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd_pref_remote uncore cache TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely event=0x35,umask=0xc88f7e01  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd_remote uncore cache TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely event=0x35,umask=0xc80f7e01  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_cxl_acc uncore cache All requests issued from IA cores to CXL accelerator memory regions that miss the LLC event=0x35,umask=0x10c0018201  01     unc_cha_tor_inserts.ia_miss_cxl_acc_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_CXL_ACC_LOCAL event=0x35,umask=0x10c0008201  01     unc_cha_tor_inserts.ia_miss_drd uncore cache TOR Inserts for DRd misses from local IA event=0x35,umask=0xc817fe01  01    Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd unc_cha_tor_inserts.ia_miss_drdmorph_cxl_acc uncore cache DRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x35,umask=0x10c8138201  01     unc_cha_tor_inserts.ia_miss_drdpte uncore cache TOR Inserts : DRd PTEs issued by iA Cores that Missed the LLC event=0x35,umask=0xc837fe01  01    TOR Inserts : DRd PTEs issued by iA Cores due to a page walk that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_cxl_acc uncore cache DRds issued from an IA core which miss the L3 and target memory in a CXL type 2 memory expander card event=0x35,umask=0x10c8178201  01     unc_cha_tor_inserts.ia_miss_drd_cxl_acc_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_DRD_CXL_ACC_LOCAL event=0x35,umask=0x10c8168201  01     unc_cha_tor_inserts.ia_miss_drd_cxl_exp_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_DRD_CXL_EXP_LOCAL event=0x35,umask=0x20c8168201  01     unc_cha_tor_inserts.ia_miss_drd_ddr uncore cache TOR Inserts for DRds issued by IA Cores targeting DDR Mem that Missed the LLC event=0x35,umask=0xc8178601  01    Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target DDR memory unc_cha_tor_inserts.ia_miss_drd_local uncore cache TOR Inserts for DRd misses from local IA targeting local memory event=0x35,umask=0xc816fe01  01    Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target local memory unc_cha_tor_inserts.ia_miss_drd_local_ddr uncore cache TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally event=0x35,umask=0xc8168601  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_local_pmm uncore cache TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally event=0x35,umask=0xc8168a01  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_opt uncore cache TOR Inserts; DRd Opt misses from local IA event=0x35,umask=0xc827fe01  01    TOR Inserts; Data read opt from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_drd_opt_cxl_acc_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_CXL_ACC_LOCAL event=0x35,umask=0x10c8268201  01     unc_cha_tor_inserts.ia_miss_drd_opt_pref uncore cache TOR Inserts; DRd Opt Pref misses from local IA event=0x35,umask=0xc8a7fe01  01    TOR Inserts; Data read opt prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_drd_opt_pref_cxl_acc_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_CXL_ACC_LOCAL event=0x35,umask=0x10c8a68201  01     unc_cha_tor_inserts.ia_miss_drd_pmm uncore cache TOR Inserts for DRds issued by iA Cores targeting PMM Mem that Missed the LLC event=0x35,umask=0xc8178a01  01    Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target PMM memory unc_cha_tor_inserts.ia_miss_drd_pref uncore cache TOR Inserts for DRd Pref misses from local IA event=0x35,umask=0xc897fe01  01    Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF unc_cha_tor_inserts.ia_miss_drd_pref_cxl_acc uncore cache L2 data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x35,umask=0x10c8978201  01     unc_cha_tor_inserts.ia_miss_drd_pref_cxl_acc_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_CXL_ACC_LOCAL event=0x35,umask=0x10c8968201  01     unc_cha_tor_inserts.ia_miss_drd_pref_cxl_exp_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_CXL_EXP_LOCAL event=0x35,umask=0x20c8968201  01     unc_cha_tor_inserts.ia_miss_drd_pref_ddr uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC event=0x35,umask=0xc8978601  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_local uncore cache TOR Inserts for DRd Pref misses from local IA targeting local memory event=0x35,umask=0xc896fe01  01    Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF, and target local memory unc_cha_tor_inserts.ia_miss_drd_pref_local_ddr uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally event=0x35,umask=0xc8968601  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_local_pmm uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally event=0x35,umask=0xc8968a01  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_pmm uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC event=0x35,umask=0xc8978a01  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_remote uncore cache TOR Inserts for DRd Pref misses from local IA targeting remote memory event=0x35,umask=0xc8977e01  01    Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF, and target remote memory unc_cha_tor_inserts.ia_miss_drd_pref_remote_ddr uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely event=0x35,umask=0xc8970601  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_remote_pmm uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely event=0x35,umask=0xc8970a01  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_remote uncore cache TOR Inserts for DRd misses from local IA targeting remote memory event=0x35,umask=0xc8177e01  01    Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and target remote memory unc_cha_tor_inserts.ia_miss_drd_remote_ddr uncore cache TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely event=0x35,umask=0xc8170601  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_remote_pmm uncore cache TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely event=0x35,umask=0xc8170a01  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_itom uncore cache TOR Inserts : ItoMs issued by iA Cores that Missed LLC event=0x35,umask=0xcc47fe01  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_llcprefcode uncore cache TOR Inserts; LLCPrefCode misses from local IA event=0x35,umask=0xcccffe01  01    TOR Inserts; Last level cache prefetch code read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_llcprefcode_cxl_acc uncore cache LLC Prefetch Code transactions issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x35,umask=0x10cccf8201  01     unc_cha_tor_inserts.ia_miss_llcprefdata uncore cache TOR Inserts; LLCPrefData misses from local IA event=0x35,umask=0xccd7fe01  01    TOR Inserts; Last level cache prefetch data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_llcprefdata_cxl_acc uncore cache LLC data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x35,umask=0x10ccd78201  01     unc_cha_tor_inserts.ia_miss_llcprefdata_cxl_acc_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA_CXL_ACC_LOCAL event=0x35,umask=0x10ccd68201  01     unc_cha_tor_inserts.ia_miss_llcprefdata_cxl_exp_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA_CXL_EXP_LOCAL event=0x35,umask=0x20ccd68201  01     unc_cha_tor_inserts.ia_miss_llcprefrfo uncore cache TOR Inserts; LLCPrefRFO misses from local IA event=0x35,umask=0xccc7fe01  01    TOR Inserts; Last level cache prefetch read for ownership from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_llcprefrfo_cxl_acc uncore cache L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x35,umask=0x10c8878201  01     unc_cha_tor_inserts.ia_miss_llcprefrfo_cxl_acc_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO_CXL_ACC_LOCAL event=0x35,umask=0x10c8868201  01     unc_cha_tor_inserts.ia_miss_llcprefrfo_cxl_exp_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO_CXL_EXP_LOCAL event=0x35,umask=0x20c8868201  01     unc_cha_tor_inserts.ia_miss_local_wcilf_ddr uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally event=0x35,umask=0xc8668601  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_local_wcilf_pmm uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally event=0x35,umask=0xc8668a01  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_local_wcil_ddr uncore cache TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally event=0x35,umask=0xc86e8601  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_local_wcil_pmm uncore cache TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally event=0x35,umask=0xc86e8a01  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_remote_wcilf_ddr uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely event=0x35,umask=0xc8670601  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_remote_wcilf_pmm uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely event=0x35,umask=0xc8670a01  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_remote_wcil_ddr uncore cache TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely event=0x35,umask=0xc86f0601  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_remote_wcil_pmm uncore cache TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely event=0x35,umask=0xc86f0a01  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_rfo uncore cache TOR Inserts; RFO misses from local IA event=0x35,umask=0xc807fe01  01    TOR Inserts; Read for ownership from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_rfomorph_cxl_acc uncore cache RFO and L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x35,umask=0x10c8038201  01     unc_cha_tor_inserts.ia_miss_rfo_cxl_acc uncore cache RFOs issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x35,umask=0x10c8078201  01     unc_cha_tor_inserts.ia_miss_rfo_cxl_acc_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_RFO_CXL_ACC_LOCAL event=0x35,umask=0x10c8068201  01     unc_cha_tor_inserts.ia_miss_rfo_cxl_exp_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_RFO_CXL_EXP_LOCAL event=0x35,umask=0x20c8068201  01     unc_cha_tor_inserts.ia_miss_rfo_local uncore cache TOR Inserts RFO misses from local IA event=0x35,umask=0xc806fe01  01    TOR Inserts; Read for ownership from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_rfo_pref uncore cache TOR Inserts; RFO pref misses from local IA event=0x35,umask=0xc887fe01  01    TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_rfo_pref_cxl_acc uncore cache LLC RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x35,umask=0x10ccc78201  01     unc_cha_tor_inserts.ia_miss_rfo_pref_cxl_acc_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_CXL_ACC_LOCAL event=0x35,umask=0x10ccc68201  01     unc_cha_tor_inserts.ia_miss_rfo_pref_cxl_exp_local uncore cache UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_CXL_EXP_LOCAL event=0x35,umask=0x20ccc68201  01     unc_cha_tor_inserts.ia_miss_rfo_pref_local uncore cache TOR Inserts; RFO prefetch misses from local IA event=0x35,umask=0xc886fe01  01    TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_rfo_pref_remote uncore cache TOR Inserts; RFO prefetch misses from local IA event=0x35,umask=0xc8877e01  01    TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_rfo_remote uncore cache TOR Inserts; RFO misses from local IA event=0x35,umask=0xc8077e01  01    TOR Inserts Read for ownership from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_ucrdf uncore cache TOR Inserts : UCRdFs issued by iA Cores that Missed LLC event=0x35,umask=0xc877de01  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcil uncore cache TOR Inserts : WCiLs issued by iA Cores that Missed the LLC event=0x35,umask=0xc86ffe01  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcilf uncore cache TOR Inserts : WCiLF issued by iA Cores that Missed the LLC event=0x35,umask=0xc867fe01  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcilf_ddr uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC event=0x35,umask=0xc8678601  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcilf_pmm uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC event=0x35,umask=0xc8678a01  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcil_ddr uncore cache TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC event=0x35,umask=0xc86f8601  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcil_pmm uncore cache TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC event=0x35,umask=0xc86f8a01  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wil uncore cache TOR Inserts : WiLs issued by iA Cores that Missed LLC event=0x35,umask=0xc87fde01  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_rfo uncore cache TOR Inserts; RFO from local IA event=0x35,umask=0xc807ff01  01    TOR Inserts; Read for ownership from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_rfo_pref uncore cache TOR Inserts; RFO pref from local IA event=0x35,umask=0xc887ff01  01    TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_specitom uncore cache TOR Inserts;SpecItoM from Local IA event=0x35,umask=0xcc57ff01  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; SpecItoM events that are initiated from the Core unc_cha_tor_inserts.ia_wbeftoe uncore cache TOR Inserts : WBEFtoEs issued by an IA Core.  Non Modified Write Backs event=0x35,umask=0xcc3fff01  01    WbEFtoEs issued by iA Cores .  (Non Modified Write Backs)  :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.  Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wbeftoi uncore cache TOR Inserts : WBEFtoEs issued by an IA Core.  Non Modified Write Backs event=0x35,umask=0xcc37ff01  01    WbEFtoEs issued by iA Cores .  (Non Modified Write Backs)  :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.  Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wbmtoe uncore cache TOR Inserts : WBEFtoEs issued by an IA Core.  Non Modified Write Backs event=0x35,umask=0xcc2fff01  01    WbEFtoEs issued by iA Cores .  (Non Modified Write Backs)  :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.  Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wbmtoi uncore cache TOR Inserts : WbMtoIs issued by an iA Cores. Modified Write Backs event=0x35,umask=0xcc27ff01  01    WbMtoIs issued by iA Cores .  (Modified Write Backs)  :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.  Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wbstoi uncore cache TOR Inserts : WBEFtoEs issued by an IA Core.  Non Modified Write Backs event=0x35,umask=0xcc67ff01  01    WbEFtoEs issued by iA Cores .  (Non Modified Write Backs)  :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.  Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wcil uncore cache TOR Inserts : WCiLs issued by iA Cores event=0x35,umask=0xc86fff01  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wcilf uncore cache TOR Inserts : WCiLF issued by iA Cores event=0x35,umask=0xc867ff01  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io uncore cache TOR Inserts; All from local IO event=0x35,umask=0xc001ff04  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_clflush uncore cache TOR Inserts : CLFlushes issued by IO Devices event=0x35,umask=0xc8c3ff04  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_hit uncore cache TOR Inserts; Hits from local IO event=0x35,umask=0xc001fd04  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_hit_itom uncore cache TOR Inserts; ItoM hits from local IO event=0x35,umask=0xcc43fd04  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_hit_itomcachenear uncore cache TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC event=0x35,umask=0xcd43fd04  01    TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_hit_pcirdcur uncore cache TOR Inserts; RdCur and FsRdCur hits from local IO event=0x35,umask=0xc8f3fd04  01    TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_hit_rfo uncore cache TOR Inserts; RFO hits from local IO event=0x35,umask=0xc803fd04  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_itom uncore cache TOR Inserts for ItoM from local IO event=0x35,umask=0xcc43ff04  01    Inserts into the TOR from local IO with the opcode ItoM unc_cha_tor_inserts.io_itomcachenear uncore cache TOR Inserts for ItoMCacheNears from IO devices event=0x35,umask=0xcd43ff04  01    Inserts into the TOR from local IO devices with the opcode ItoMCacheNears.  This event indicates a partial write request unc_cha_tor_inserts.io_itomcachenear_local uncore cache ItoMCacheNear (partial write) transactions from an IO device that addresses memory on the local socket event=0x35,umask=0xcd42ff04  01    TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_itomcachenear_remote uncore cache ItoMCacheNear (partial write) transactions from an IO device that addresses memory on a remote socket event=0x35,umask=0xcd437f04  01    TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_itom_local uncore cache ItoM (write) transactions from an IO device that addresses memory on the local socket event=0x35,umask=0xcc42ff04  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_itom_remote uncore cache ItoM (write) transactions from an IO device that addresses memory on a remote socket event=0x35,umask=0xcc437f04  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_miss uncore cache TOR Inserts; Misses from local IO event=0x35,umask=0xc001fe04  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_miss_itom uncore cache TOR Inserts : ItoM, indicating a full cacheline write request, from IO Devices that missed the LLC event=0x35,umask=0xcc43fe04  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_miss_itomcachenear uncore cache TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC event=0x35,umask=0xcd43fe04  01    TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_miss_pcirdcur uncore cache TOR Inserts; RdCur and FsRdCur requests from local IO that miss LLC event=0x35,umask=0xc8f3fe04  01    TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_miss_rfo uncore cache TOR Inserts; RFO misses from local IO event=0x35,umask=0xc803fe04  01    TOR Inserts : RFOs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_pcirdcur uncore cache TOR Inserts for RdCur from local IO event=0x35,umask=0xc8f3ff04  01    Inserts into the TOR from local IO with the opcode RdCur unc_cha_tor_inserts.io_pcirdcur_local uncore cache PCIRDCUR (read) transactions from an IO device that addresses memory on a remote socket event=0x35,umask=0xc8f2ff04  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_pcirdcur_remote uncore cache PCIRDCUR (read) transactions from an IO device that addresses memory on the local socket event=0x35,umask=0xc8f37f04  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_rfo uncore cache TOR Inserts; RFO from local IO event=0x35,umask=0xc803ff04  01    TOR Inserts : RFOs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_wbmtoi uncore cache TOR Inserts : WbMtoIs issued by IO Devices event=0x35,umask=0xcc23ff04  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ipq uncore cache TOR Inserts : IPQ event=0x35,umask=8  01    TOR Inserts : IPQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.irq_ia uncore cache TOR Inserts : IRQ - iA event=0x35,umask=1  01    TOR Inserts : IRQ - iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : From an iA Core unc_cha_tor_inserts.irq_non_ia uncore cache TOR Inserts : IRQ - Non iA event=0x35,umask=0x10  01    TOR Inserts : IRQ - Non iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.isoc uncore cache TOR Inserts : Just ISOC event=0x35  01    TOR Inserts : Just ISOC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.local_tgt uncore cache TOR Inserts : Just Local Targets event=0x35  01    TOR Inserts : Just Local Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.loc_all uncore cache TOR Inserts : All from Local iA and IO event=0x35,umask=0xc000ff05  01    TOR Inserts : All from Local iA and IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All locally initiated requests unc_cha_tor_inserts.loc_ia uncore cache TOR Inserts : All from Local iA event=0x35,umask=0xc000ff01  01    TOR Inserts : All from Local iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All locally initiated requests from iA Cores unc_cha_tor_inserts.loc_io uncore cache TOR Inserts : All from Local IO event=0x35,umask=0xc000ff04  01    TOR Inserts : All from Local IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All locally generated IO traffic unc_cha_tor_inserts.match_opc uncore cache TOR Inserts : Match the Opcode in b[29:19] of the extended umask field event=0x35  01    TOR Inserts : Match the Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.miss uncore cache TOR Inserts : Just Misses event=0x35  01    TOR Inserts : Just Misses : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.mmcfg uncore cache TOR Inserts : MMCFG Access event=0x35  01    TOR Inserts : MMCFG Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.mmio uncore cache TOR Inserts : MMIO Access event=0x35  01    TOR Inserts : MMIO Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.nearmem uncore cache TOR Inserts : Just NearMem event=0x35  01    TOR Inserts : Just NearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.noncoh uncore cache TOR Inserts : Just NonCoherent event=0x35  01    TOR Inserts : Just NonCoherent : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.not_nearmem uncore cache TOR Inserts : Just NotNearMem event=0x35  01    TOR Inserts : Just NotNearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.pmm uncore cache TOR Inserts : PMM Access event=0x35  01    TOR Inserts : PM Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.premorph_opc uncore cache TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field event=0x35  01    TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.prq_iosf uncore cache TOR Inserts : PRQ - IOSF event=0x35,umask=4  01    TOR Inserts : PRQ - IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : From a PCIe Device unc_cha_tor_inserts.prq_non_iosf uncore cache TOR Inserts : PRQ - Non IOSF event=0x35,umask=0x20  01    TOR Inserts : PRQ - Non IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.remote_tgt uncore cache TOR Inserts : Just Remote Targets event=0x35  01    TOR Inserts : Just Remote Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.rem_all uncore cache TOR Inserts : All from Remote event=0x35,umask=0xc001ffc8  01    TOR Inserts : All from Remote : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All remote requests (e.g. snoops, writebacks) that came from remote sockets unc_cha_tor_inserts.rem_snps uncore cache TOR Inserts : All Snoops from Remote event=0x35,umask=0xc001ff08  01    TOR Inserts : All Snoops from Remote : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All snoops to this LLC that came from remote sockets unc_cha_tor_inserts.rrq uncore cache TOR Inserts : RRQ event=0x35,umask=0x40  01    TOR Inserts : RRQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_inserts.rrq_miss_invxtom_cxl_exp_local uncore cache TOR Inserts for INVXTOM opcodes received from a remote socket which miss the L3 and target memory in a CXL type 3 memory expander local to this socket event=0x35,umask=0x20e87e8240  01     unc_cha_tor_inserts.rrq_miss_rdcode_cxl_exp_local uncore cache TOR Inserts for RDCODE opcodes received from a remote socket which miss the L3 and target memory in a CXL type 3 memory expander local to this socket event=0x35,umask=0x20e80e8240  01     unc_cha_tor_inserts.rrq_miss_rdcur_cxl_exp_local uncore cache TOR Inserts for RDCUR opcodes received from a remote socket which miss the L3 and target memory in a CXL type 3 memory expander local to this socket event=0x35,umask=0x20e8068240  01     unc_cha_tor_inserts.rrq_miss_rddata_cxl_exp_local uncore cache TOR Inserts for RDDATA opcodes received from a remote socket which miss the L3 and target memory in a CXL type 3 memory expander local to this socket event=0x35,umask=0x20e8168240  01     unc_cha_tor_inserts.rrq_miss_rdinvown_opt_cxl_exp_local uncore cache TOR Inserts for RDINVOWN_OPT opcodes received from a remote socket which miss the L3 and target memory in a CXL type 3 memory expander local to this socket event=0x35,umask=0x20e8268240  01     unc_cha_tor_inserts.snps_from_rem uncore cache TOR Inserts; All Snoops from Remote event=0x35,umask=0xc001ff08  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. All snoops to this LLC that came from remote sockets unc_cha_tor_inserts.wbq uncore cache TOR Inserts : WBQ event=0x35,umask=0x80  01    TOR Inserts : WBQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent unc_cha_tor_occupancy.all uncore cache TOR Occupancy : All event=0x36,umask=0xc001ffff  01    TOR Occupancy : All : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T unc_cha_tor_occupancy.ddr uncore cache TOR Occupancy : DDR Access event=0x36  01    TOR Occupancy : DDR Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent unc_cha_tor_occupancy.evict uncore cache TOR Occupancy : SF/LLC Evictions event=0x36,umask=2  01    TOR Occupancy : SF/LLC Evictions : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ) unc_cha_tor_occupancy.hit uncore cache TOR Occupancy : Just Hits event=0x36  01    TOR Occupancy : Just Hits : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T unc_cha_tor_occupancy.ia uncore cache TOR Occupancy; All from local IA event=0x36,umask=0xc001ff01  01    TOR Occupancy : All requests from iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_clflush uncore cache TOR Occupancy : CLFlushes issued by iA Cores event=0x36,umask=0xc8c7ff01  01    TOR Occupancy : CLFlushes issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_clflushopt uncore cache TOR Occupancy : CLFlushOpts issued by iA Cores event=0x36,umask=0xc8d7ff01  01    TOR Occupancy : CLFlushOpts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_crd uncore cache TOR Occupancy; CRd from local IA event=0x36,umask=0xc80fff01  01    TOR Occupancy; Code read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_crd_pref uncore cache TOR Occupancy; CRd Pref from local IA event=0x36,umask=0xc88fff01  01    TOR Occupancy; Code read prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_drd uncore cache TOR Occupancy; DRd from local IA event=0x36,umask=0xc817ff01  01    TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_drdpte uncore cache TOR Occupancy : DRdPte issued by iA Cores due to a page walk event=0x36,umask=0xc837ff01  01    TOR Occupancy : DRdPte issued by iA Cores due to a page walk : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_drd_opt uncore cache TOR Occupancy; DRd Opt from local IA event=0x36,umask=0xc827ff01  01    TOR Occupancy; Data read opt from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_drd_opt_pref uncore cache TOR Occupancy; DRd Opt Pref from local IA event=0x36,umask=0xc8a7ff01  01    TOR Occupancy; Data read opt prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_drd_pref uncore cache TOR Occupancy; DRd Pref from local IA event=0x36,umask=0xc897ff01  01    TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_hit uncore cache TOR Occupancy; Hits from local IA event=0x36,umask=0xc001fd01  01    TOR Occupancy : All requests from iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_crd uncore cache TOR Occupancy; CRd hits from local IA event=0x36,umask=0xc80ffd01  01    TOR Occupancy; Code read from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_hit_crd_pref uncore cache TOR Occupancy; CRd Pref hits from local IA event=0x36,umask=0xc88ffd01  01    TOR Occupancy; Code read prefetch from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_hit_cxl_acc uncore cache TOR Occupancy for All requests issued from IA cores to CXL accelerator memory regions that hit the LLC event=0x36,umask=0x10c0018101  01     unc_cha_tor_occupancy.ia_hit_cxl_acc_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_HIT_CXL_ACC_LOCAL event=0x36,umask=0x10c0008101  01     unc_cha_tor_occupancy.ia_hit_drd uncore cache TOR Occupancy; DRd hits from local IA event=0x36,umask=0xc817fd01  01    TOR Occupancy; Data read from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_hit_drdpte uncore cache TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC event=0x36,umask=0xc837fd01  01    TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_drd_opt uncore cache TOR Occupancy; DRd Opt hits from local IA event=0x36,umask=0xc827fd01  01    TOR Occupancy; Data read opt from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_hit_drd_opt_pref uncore cache TOR Occupancy; DRd Opt Pref hits from local IA event=0x36,umask=0xc8a7fd01  01    TOR Occupancy; Data read opt prefetch from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_hit_drd_pref uncore cache TOR Occupancy; DRd Pref hits from local IA event=0x36,umask=0xc897fd01  01    TOR Occupancy; Data read prefetch from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_hit_itom uncore cache TOR Occupancy : ItoMs issued by iA Cores that Hit LLC event=0x36,umask=0xcc47fd01  01    TOR Occupancy : ItoMs issued by iA Cores that Hit LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_llcprefcode uncore cache TOR Occupancy; LLCPrefCode hits from local IA event=0x36,umask=0xcccffd01  01    TOR Occupancy; Last level cache prefetch code read from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_hit_llcprefdata uncore cache TOR Occupancy; LLCPrefData hits from local IA event=0x36,umask=0xccd7fd01  01    TOR Occupancy; Last level cache prefetch data read from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_hit_llcprefrfo uncore cache TOR Occupancy; LLCPrefRFO hits from local IA event=0x36,umask=0xccc7fd01  01    TOR Occupancy; Last level cache prefetch read for ownership from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_hit_rfo uncore cache TOR Occupancy; RFO hits from local IA event=0x36,umask=0xc807fd01  01    TOR Occupancy; Read for ownership from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_hit_rfo_pref uncore cache TOR Occupancy; RFO Pref hits from local IA event=0x36,umask=0xc887fd01  01    TOR Occupancy; Read for ownership prefetch from local IA that hits in the snoop filter unc_cha_tor_occupancy.ia_itom uncore cache TOR Occupancy : ItoMs issued by iA Cores event=0x36,umask=0xcc47ff01  01    TOR Occupancy : ItoMs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_itomcachenear uncore cache TOR Occupancy : ItoMCacheNears issued by iA Cores event=0x36,umask=0xcd47ff01  01    TOR Occupancy : ItoMCacheNears issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_llcprefcode uncore cache TOR Occupancy; LLCPrefCode from local IA event=0x36,umask=0xcccfff01  01    TOR Occupancy; Last level cache prefetch data read from local IA unc_cha_tor_occupancy.ia_llcprefdata uncore cache TOR Occupancy; LLCPrefData from local IA event=0x36,umask=0xccd7ff01  01    TOR Occupancy; Last level cache prefetch data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_llcprefrfo uncore cache TOR Occupancy; LLCPrefRFO from local IA event=0x36,umask=0xccc7ff01  01    TOR Occupancy; Last level cache prefetch read for ownership from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss uncore cache TOR Occupancy; Misses from Local IA event=0x36,umask=0xc001fe01  01    TOR Occupancy : All requests from iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_crd uncore cache TOR Occupancy; CRd misses from local IA event=0x36,umask=0xc80ffe01  01    TOR Occupancy; Code read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_crdmorph_cxl_acc uncore cache TOR Occupancy for CRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x36,umask=0x10c80b8201  01     unc_cha_tor_occupancy.ia_miss_crd_local uncore cache TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally event=0x36,umask=0xc80efe01  01    TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_crd_pref uncore cache TOR Occupancy; CRd Pref misses from local IA event=0x36,umask=0xc88ffe01  01    TOR Occupancy; Code read prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_crd_pref_local uncore cache TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally event=0x36,umask=0xc88efe01  01    TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_crd_pref_remote uncore cache TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely event=0x36,umask=0xc88f7e01  01    TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_crd_remote uncore cache TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely event=0x36,umask=0xc80f7e01  01    TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_cxl_acc uncore cache TOR Occupancy for All requests issued from IA cores to CXL accelerator memory regions that miss the LLC event=0x36,umask=0x10c0018201  01     unc_cha_tor_occupancy.ia_miss_cxl_acc_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_CXL_ACC_LOCAL event=0x36,umask=0x10c0008201  01     unc_cha_tor_occupancy.ia_miss_drd uncore cache TOR Occupancy for DRd misses from local IA event=0x36,umask=0xc817fe01  01    Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd unc_cha_tor_occupancy.ia_miss_drdmorph_cxl_acc uncore cache TOR Occupancy for DRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x36,umask=0x10c8138201  01     unc_cha_tor_occupancy.ia_miss_drdpte uncore cache TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC event=0x36,umask=0xc837fe01  01    TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_cxl_acc uncore cache TOR Occupancy for DRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 memory expander card event=0x36,umask=0x10c8178201  01     unc_cha_tor_occupancy.ia_miss_drd_cxl_acc_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_CXL_ACC_LOCAL event=0x36,umask=0x10c8168201  01     unc_cha_tor_occupancy.ia_miss_drd_cxl_exp_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_CXL_EXP_LOCAL event=0x36,umask=0x20c8168201  01     unc_cha_tor_occupancy.ia_miss_drd_ddr uncore cache TOR Occupancy for DRds issued by iA Cores targeting DDR Mem that Missed the LLC event=0x36,umask=0xc8178601  01    Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target DDR memory unc_cha_tor_occupancy.ia_miss_drd_local uncore cache TOR Occupancy for DRd misses from local IA targeting local memory event=0x36,umask=0xc816fe01  01    Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target local memory unc_cha_tor_occupancy.ia_miss_drd_local_ddr uncore cache TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally event=0x36,umask=0xc8168601  01    TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_local_pmm uncore cache TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally event=0x36,umask=0xc8168a01  01    TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_opt uncore cache TOR Occupancy; DRd Opt misses from local IA event=0x36,umask=0xc827fe01  01    TOR Occupancy; Data read opt from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_drd_opt_cxl_acc_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_CXL_ACC_LOCAL event=0x36,umask=0x10c8268201  01     unc_cha_tor_occupancy.ia_miss_drd_opt_pref uncore cache TOR Occupancy; DRd Opt Pref misses from local IA event=0x36,umask=0xc8a7fe01  01    TOR Occupancy; Data read opt prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_drd_opt_pref_cxl_acc_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF_CXL_ACC_LOCAL event=0x36,umask=0x10c8a68201  01     unc_cha_tor_occupancy.ia_miss_drd_pmm uncore cache TOR Occupancy for DRds issued by iA Cores targeting PMM Mem that Missed the LLC event=0x36,umask=0xc8178a01  01    Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target PMM memory unc_cha_tor_occupancy.ia_miss_drd_pref uncore cache TOR Occupancy; DRd Pref misses from local IA event=0x36,umask=0xc897fe01  01    TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_drd_pref_cxl_acc uncore cache TOR Occupancy for L2 data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x36,umask=0x10c8978201  01     unc_cha_tor_occupancy.ia_miss_drd_pref_cxl_acc_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_CXL_ACC_LOCAL event=0x36,umask=0x10c8968201  01     unc_cha_tor_occupancy.ia_miss_drd_pref_cxl_exp_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_CXL_EXP_LOCAL event=0x36,umask=0x20c8968201  01     unc_cha_tor_occupancy.ia_miss_drd_pref_ddr uncore cache TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC event=0x36,umask=0xc8978601  01    TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_pref_local uncore cache TOR Occupancy; DRd Pref misses from local IA event=0x36,umask=0xc896fe01  01    TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_drd_pref_local_ddr uncore cache TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally event=0x36,umask=0xc8968601  01    TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_pref_local_pmm uncore cache TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally event=0x36,umask=0xc8968a01  01    TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_pref_pmm uncore cache TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC event=0x36,umask=0xc8978a01  01    TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_pref_remote uncore cache TOR Occupancy; DRd Pref misses from local IA event=0x36,umask=0xc8977e01  01    TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_drd_pref_remote_ddr uncore cache TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely event=0x36,umask=0xc8970601  01    TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_pref_remote_pmm uncore cache TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely event=0x36,umask=0xc8970a01  01    TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_remote uncore cache TOR Occupancy for DRd misses from local IA targeting remote memory event=0x36,umask=0xc8177e01  01    Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target remote memory unc_cha_tor_occupancy.ia_miss_drd_remote_ddr uncore cache TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely event=0x36,umask=0xc8170601  01    TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_remote_pmm uncore cache TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely event=0x36,umask=0xc8170a01  01    TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_itom uncore cache TOR Occupancy : ItoMs issued by iA Cores that Missed LLC event=0x36,umask=0xcc47fe01  01    TOR Occupancy : ItoMs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_llcprefcode uncore cache TOR Occupancy; LLCPrefCode misses from local IA event=0x36,umask=0xcccffe01  01    TOR Occupancy; Last level cache prefetch code read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_llcprefcode_cxl_acc uncore cache TOR Occupancy for LLC Prefetch Code transactions issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x36,umask=0x10cccf8201  01     unc_cha_tor_occupancy.ia_miss_llcprefdata uncore cache TOR Occupancy; LLCPrefData misses from local IA event=0x36,umask=0xccd7fe01  01    TOR Occupancy; Last level cache prefetch data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_llcprefdata_cxl_acc uncore cache TOR Occupancy for LLC data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x36,umask=0x10ccd78201  01     unc_cha_tor_occupancy.ia_miss_llcprefdata_cxl_acc_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA_CXL_ACC_LOCAL event=0x36,umask=0x10ccd68201  01     unc_cha_tor_occupancy.ia_miss_llcprefdata_cxl_exp_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA_CXL_EXP_LOCAL event=0x36,umask=0x20ccd68201  01     unc_cha_tor_occupancy.ia_miss_llcprefrfo uncore cache TOR Occupancy; LLCPrefRFO misses from local IA event=0x36,umask=0xccc7fe01  01    TOR Occupancy; Last level cache prefetch read for ownership from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_llcprefrfo_cxl_acc uncore cache TOR Occupancy for L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x36,umask=0x10c8878201  01     unc_cha_tor_occupancy.ia_miss_llcprefrfo_cxl_acc_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO_CXL_ACC_LOCAL event=0x36,umask=0x10c8868201  01     unc_cha_tor_occupancy.ia_miss_llcprefrfo_cxl_exp_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO_CXL_EXP_LOCAL event=0x36,umask=0x20c8868201  01     unc_cha_tor_occupancy.ia_miss_local_wcilf_ddr uncore cache TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally event=0x36,umask=0xc8668601  01    TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_local_wcilf_pmm uncore cache TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally event=0x36,umask=0xc8668a01  01    TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_local_wcil_ddr uncore cache TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally event=0x36,umask=0xc86e8601  01    TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_local_wcil_pmm uncore cache TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally event=0x36,umask=0xc86e8a01  01    TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_remote_wcilf_ddr uncore cache TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely event=0x36,umask=0xc8670601  01    TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_remote_wcilf_pmm uncore cache TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely event=0x36,umask=0xc8670a01  01    TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_remote_wcil_ddr uncore cache TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely event=0x36,umask=0xc86f0601  01    TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_remote_wcil_pmm uncore cache TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely event=0x36,umask=0xc86f0a01  01    TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_rfo uncore cache TOR Occupancy; RFO misses from local IA event=0x36,umask=0xc807fe01  01    TOR Occupancy; Read for ownership from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_rfomorph_cxl_acc uncore cache TOR Occupancy for RFO and L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x36,umask=0x10c8038201  01     unc_cha_tor_occupancy.ia_miss_rfo_cxl_acc uncore cache TOR Occupancy for RFOs issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x36,umask=0x10c8078201  01     unc_cha_tor_occupancy.ia_miss_rfo_cxl_acc_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_CXL_ACC_LOCAL event=0x36,umask=0x10c8068201  01     unc_cha_tor_occupancy.ia_miss_rfo_cxl_exp_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_CXL_EXP_LOCAL event=0x36,umask=0x20c8068201  01     unc_cha_tor_occupancy.ia_miss_rfo_local uncore cache TOR Occupancy; RFO misses from local IA event=0x36,umask=0xc806fe01  01    TOR Occupancy; Read for ownership from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_rfo_pref uncore cache TOR Occupancy; RFO prefetch misses from local IA event=0x36,umask=0xc887fe01  01    TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_rfo_pref_cxl_acc uncore cache TOR Occupancy for LLC RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator event=0x36,umask=0x10ccc78201  01     unc_cha_tor_occupancy.ia_miss_rfo_pref_cxl_acc_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_CXL_ACC_LOCAL event=0x36,umask=0x10ccc68201  01     unc_cha_tor_occupancy.ia_miss_rfo_pref_cxl_exp_local uncore cache UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_CXL_EXP_LOCAL event=0x36,umask=0x20ccc68201  01     unc_cha_tor_occupancy.ia_miss_rfo_pref_local uncore cache TOR Occupancy; RFO prefetch misses from local IA event=0x36,umask=0xc886fe01  01    TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_rfo_pref_remote uncore cache TOR Occupancy; RFO prefetch misses from local IA event=0x36,umask=0xc8877e01  01    TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_rfo_remote uncore cache TOR Occupancy; RFO misses from local IA event=0x36,umask=0xc8077e01  01    TOR Occupancy; Read for ownership from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_ucrdf uncore cache TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC event=0x36,umask=0xc877de01  01    TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_wcil uncore cache TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC event=0x36,umask=0xc86ffe01  01    TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_wcilf uncore cache TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC event=0x36,umask=0xc867fe01  01    TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_wcilf_ddr uncore cache TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC event=0x36,umask=0xc8678601  01    TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_wcilf_pmm uncore cache TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC event=0x36,umask=0xc8678a01  01    TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_wcil_ddr uncore cache TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC event=0x36,umask=0xc86f8601  01    TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_wcil_pmm uncore cache TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC event=0x36,umask=0xc86f8a01  01    TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_wil uncore cache TOR Occupancy : WiLs issued by iA Cores that Missed LLC event=0x36,umask=0xc87fde01  01    TOR Occupancy : WiLs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_rfo uncore cache TOR Occupancy; RFO from local IA event=0x36,umask=0xc807ff01  01    TOR Occupancy; Read for ownership from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_rfo_pref uncore cache TOR Occupancy; RFO prefetch from local IA event=0x36,umask=0xc887ff01  01    TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_specitom uncore cache TOR Occupancy : SpecItoMs issued by iA Cores event=0x36,umask=0xcc57ff01  01    TOR Occupancy : SpecItoMs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_wbmtoi uncore cache TOR Occupancy : WbMtoIs issued by iA Cores event=0x36,umask=0xcc27ff01  01    TOR Occupancy : WbMtoIs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_wcil uncore cache TOR Occupancy : WCiLs issued by iA Cores event=0x36,umask=0xc86fff01  01    TOR Occupancy : WCiLs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_wcilf uncore cache TOR Occupancy : WCiLF issued by iA Cores event=0x36,umask=0xc867ff01  01    TOR Occupancy : WCiLF issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io uncore cache TOR Occupancy; All from local IO event=0x36,umask=0xc001ff04  01    TOR Occupancy : All requests from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_clflush uncore cache TOR Occupancy : CLFlushes issued by IO Devices event=0x36,umask=0xc8c3ff04  01    TOR Occupancy : CLFlushes issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_hit uncore cache TOR Occupancy; Hits from local IO event=0x36,umask=0xc001fd04  01    TOR Occupancy : All requests from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_hit_itom uncore cache TOR Occupancy; ITOM hits from local IO event=0x36,umask=0xcc43fd04  01    TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_hit_itomcachenear uncore cache TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC event=0x36,umask=0xcd43fd04  01    TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_hit_pcirdcur uncore cache TOR Occupancy; RdCur and FsRdCur hits from local IO event=0x36,umask=0xc8f3fd04  01    TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_hit_rfo uncore cache TOR Occupancy; RFO hits from local IO event=0x36,umask=0xc803fd04  01    TOR Occupancy : RFOs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_itom uncore cache TOR Occupancy; ITOM from local IO event=0x36,umask=0xcc43ff04  01    TOR Occupancy : ItoMs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_itomcachenear uncore cache TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices event=0x36,umask=0xcd43ff04  01    TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss uncore cache TOR Occupancy; Misses from local IO event=0x36,umask=0xc001fe04  01    TOR Occupancy : All requests from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_itom uncore cache TOR Occupancy; ITOM misses from local IO event=0x36,umask=0xcc43fe04  01    TOR Occupancy : ItoMs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_itomcachenear uncore cache TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC event=0x36,umask=0xcd43fe04  01    TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_itomcachenear_local uncore cache TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC and targets local memory event=0x36,umask=0xcd42fe04  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_itomcachenear_remote uncore cache TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC and targets remote memory event=0x36,umask=0xcd437e04  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_itom_local uncore cache TOR Occupancy; ITOM misses from local IO and targets local memory event=0x36,umask=0xcc42fe04  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_itom_remote uncore cache TOR Occupancy; ITOM misses from local IO and targets remote memory event=0x36,umask=0xcc437e04  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_pcirdcur uncore cache TOR Occupancy; RdCur and FsRdCur misses from local IO event=0x36,umask=0xc8f3fe04  01    TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_pcirdcur_local uncore cache TOR Occupancy; RdCur and FsRdCur misses from local IO and targets local memory event=0x36,umask=0xc8f2fe04  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_pcirdcur_remote uncore cache TOR Occupancy; RdCur and FsRdCur misses from local IO and targets remote memory event=0x36,umask=0xc8f37e04  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_rfo uncore cache TOR Occupancy; RFO misses from local IO event=0x36,umask=0xc803fe04  01    TOR Occupancy : RFOs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_pcirdcur uncore cache TOR Occupancy; RdCur and FsRdCur from local IO event=0x36,umask=0xc8f3ff04  01    TOR Occupancy : PCIRdCurs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_rfo uncore cache TOR Occupancy; ItoM from local IO event=0x36,umask=0xc803ff04  01    TOR Occupancy : RFOs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_wbmtoi uncore cache TOR Occupancy : WbMtoIs issued by IO Devices event=0x36,umask=0xcc23ff04  01    TOR Occupancy : WbMtoIs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ipq uncore cache TOR Occupancy : IPQ event=0x36,umask=8  01    TOR Occupancy : IPQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T unc_cha_tor_occupancy.irq_ia uncore cache TOR Occupancy : IRQ - iA event=0x36,umask=1  01    TOR Occupancy : IRQ - iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T : From an iA Core unc_cha_tor_occupancy.irq_non_ia uncore cache TOR Occupancy : IRQ - Non iA event=0x36,umask=0x10  01    TOR Occupancy : IRQ - Non iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T unc_cha_tor_occupancy.isoc uncore cache TOR Occupancy : Just ISOC event=0x36  01    TOR Occupancy : Just ISOC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T unc_cha_tor_occupancy.local_tgt uncore cache TOR Occupancy : Just Local Targets event=0x36  01    TOR Occupancy : Just Local Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T unc_cha_tor_occupancy.loc_all uncore cache TOR Occupancy : All from Local iA and IO event=0x36,umask=0xc000ff05  01    TOR Occupancy : All from Local iA and IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T : All locally initiated requests unc_cha_tor_occupancy.loc_ia uncore cache TOR Occupancy : All from Local iA event=0x36,umask=0xc000ff01  01    TOR Occupancy : All from Local iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T : All locally initiated requests from iA Cores unc_cha_tor_occupancy.loc_io uncore cache TOR Occupancy : All from Local IO event=0x36,umask=0xc000ff04  01    TOR Occupancy : All from Local IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T : All locally generated IO traffic unc_cha_tor_occupancy.match_opc uncore cache TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field event=0x36  01    TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T unc_cha_tor_occupancy.miss uncore cache TOR Occupancy : Just Misses event=0x36  01    TOR Occupancy : Just Misses : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T unc_cha_tor_occupancy.mmcfg uncore cache TOR Occupancy : MMCFG Access event=0x36  01    TOR Occupancy : MMCFG Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T unc_cha_tor_occupancy.mmio uncore cache TOR Occupancy : MMIO Access event=0x36  01    TOR Occupancy : MMIO Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T unc_cha_tor_occupancy.nearmem uncore cache TOR Occupancy : Just NearMem event=0x36  01    TOR Occupancy : Just NearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T unc_cha_tor_occupancy.noncoh uncore cache TOR Occupancy : Just NonCoherent event=0x36  01    TOR Occupancy : Just NonCoherent : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T unc_cha_tor_occupancy.not_nearmem uncore cache TOR Occupancy : Just NotNearMem event=0x36  01    TOR Occupancy : Just NotNearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T unc_cha_tor_occupancy.pmm uncore cache TOR Occupancy : PMM Access event=0x36  01    TOR Occupancy : PMM Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent unc_cha_tor_occupancy.premorph_opc uncore cache TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field event=0x36  01    TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T unc_cha_tor_occupancy.prq uncore cache TOR Occupancy : PRQ - IOSF event=0x36,umask=4  01    TOR Occupancy : PRQ - IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T : From a PCIe Device unc_cha_tor_occupancy.prq_non_iosf uncore cache TOR Occupancy : PRQ - Non IOSF event=0x36,umask=0x20  01    TOR Occupancy : PRQ - Non IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T unc_cha_tor_occupancy.remote_tgt uncore cache TOR Occupancy : Just Remote Targets event=0x36  01    TOR Occupancy : Just Remote Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T unc_cha_tor_occupancy.rem_all uncore cache TOR Occupancy : All from Remote event=0x36,umask=0xc001ffc8  01    TOR Occupancy : All from Remote : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T : All remote requests (e.g. snoops, writebacks) that came from remote sockets unc_cha_tor_occupancy.rem_snps uncore cache TOR Occupancy : All Snoops from Remote event=0x36,umask=0xc001ff08  01    TOR Occupancy : All Snoops from Remote : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T : All snoops to this LLC that came from remote sockets unc_cha_tor_occupancy.rrq uncore cache TOR Occupancy : RRQ event=0x36,umask=0x40  01    TOR Occupancy : RRQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T unc_cha_tor_occupancy.rrq_miss_invxtom_cxl_exp_local uncore cache TOR Occupancy for INVXTOM opcodes received from a remote socket which miss the L3 and target memory in a CXL type 3 memory expander local to this socket event=0x36,umask=0x20e87e8240  01     unc_cha_tor_occupancy.rrq_miss_rdcode_cxl_exp_local uncore cache TOR Occupancy for RDCODE opcodes received from a remote socket which miss the L3 and target memory in a CXL type 3 memory expander local to this socket event=0x36,umask=0x20e80e8240  01     unc_cha_tor_occupancy.rrq_miss_rdcur_cxl_exp_local uncore cache TOR Occupancy for RDCUR opcodes received from a remote socket which miss the L3 and target memory in a CXL type 3 memory expander local to this socket event=0x36,umask=0x20e8068240  01     unc_cha_tor_occupancy.rrq_miss_rddata_cxl_exp_local uncore cache TOR Occupancy for RDDATA opcodes received from a remote socket which miss the L3 and target memory in a CXL type 3 memory expander local to this socket event=0x36,umask=0x20e8168240  01     unc_cha_tor_occupancy.rrq_miss_rdinvown_opt_cxl_exp_local uncore cache TOR Occupancy for RDINVOWN_OPT opcodes received from a remote socket which miss the L3 and target memory in a CXL type 3 memory expander local to this socket event=0x36,umask=0x20e8268240  01     unc_cha_tor_occupancy.snps_from_rem uncore cache TOR Occupancy; All Snoops from Remote event=0x36,umask=0xc001ff08  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   All snoops to this LLC that came from remote sockets unc_cha_tor_occupancy.wbq uncore cache TOR Occupancy : WBQ event=0x36,umask=0x80  01    TOR Occupancy : WBQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T unc_cha_wb_push_mtoi.llc uncore cache WbPushMtoI : Pushed to LLC event=0x56,umask=1  01    WbPushMtoI : Pushed to LLC : Counts the number of times when the CHA was received WbPushMtoI : Counts the number of times when the CHA was able to push WbPushMToI to LLC unc_cha_wb_push_mtoi.mem uncore cache WbPushMtoI : Pushed to Memory event=0x56,umask=2  01    WbPushMtoI : Pushed to Memory : Counts the number of times when the CHA was received WbPushMtoI : Counts the number of times when the CHA was unable to push WbPushMToI to LLC (hence pushed it to MEM) unc_cha_write_no_credits.mc0 uncore cache CHA iMC CHNx WRITE Credits Empty : MC0 event=0x5a,umask=1  01    CHA iMC CHNx WRITE Credits Empty : MC0 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 0 only unc_cha_write_no_credits.mc1 uncore cache CHA iMC CHNx WRITE Credits Empty : MC1 event=0x5a,umask=2  01    CHA iMC CHNx WRITE Credits Empty : MC1 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 1 only unc_cha_write_no_credits.mc2 uncore cache CHA iMC CHNx WRITE Credits Empty : MC2 event=0x5a,umask=4  01    CHA iMC CHNx WRITE Credits Empty : MC2 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 2 only unc_cha_write_no_credits.mc3 uncore cache CHA iMC CHNx WRITE Credits Empty : MC3 event=0x5a,umask=8  01    CHA iMC CHNx WRITE Credits Empty : MC3 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 3 only unc_cha_write_no_credits.mc4 uncore cache CHA iMC CHNx WRITE Credits Empty : MC4 event=0x5a,umask=0x10  01    CHA iMC CHNx WRITE Credits Empty : MC4 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 4 only unc_cha_write_no_credits.mc5 uncore cache CHA iMC CHNx WRITE Credits Empty : MC5 event=0x5a,umask=0x20  01    CHA iMC CHNx WRITE Credits Empty : MC5 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 5 only unc_cha_xpt_pref.drop0_conflict uncore cache XPT Prefetches : Dropped (on 0?) - Conflict event=0x6f,umask=8  01    XPT Prefetches : Dropped (on 0?) - Conflict : Number of XPT prefetches dropped due to AD CMS write port contention unc_cha_xpt_pref.drop0_nocrd uncore cache XPT Prefetches : Dropped (on 0?) - No Credits event=0x6f,umask=4  01    XPT Prefetches : Dropped (on 0?) - No Credits : Number of XPT prefetches dropped due to lack of XPT AD egress credits unc_cha_xpt_pref.drop1_conflict uncore cache XPT Prefetches : Dropped (on 1?) - Conflict event=0x6f,umask=0x80  01    XPT Prefetches : Dropped (on 1?) - Conflict : Number of XPT prefetches dropped due to AD CMS write port contention unc_cha_xpt_pref.drop1_nocrd uncore cache XPT Prefetches : Dropped (on 1?) - No Credits event=0x6f,umask=0x40  01    XPT Prefetches : Dropped (on 1?) - No Credits : Number of XPT prefetches dropped due to lack of XPT AD egress credits unc_cha_xpt_pref.sent0 uncore cache XPT Prefetches : Sent (on 0?) event=0x6f,umask=1  01    XPT Prefetches : Sent (on 0?) : Number of XPT prefetches sent unc_cha_xpt_pref.sent1 uncore cache XPT Prefetches : Sent (on 1?) event=0x6f,umask=0x10  01    XPT Prefetches : Sent (on 1?) : Number of XPT prefetches sent uncore_cxlcm unc_cxlcm_clockticks uncore cxl Counts the number of lfclk ticks event=1,umask=2  01     unc_cxlcm_rxc_agf_inserts.cache_data uncore cxl Number of Allocation to Mem Rxx AGF 0 event=0x43,umask=8  01     unc_cxlcm_rxc_agf_inserts.cache_req0 uncore cxl Number of Allocation to Cache Req AGF0 event=0x43,umask=1  01     unc_cxlcm_rxc_agf_inserts.cache_req1 uncore cxl Number of Allocation to Cache Rsp AGF event=0x43,umask=2  01     unc_cxlcm_rxc_agf_inserts.cache_rsp0 uncore cxl Number of Allocation to Cache Data AGF event=0x43,umask=4  01     unc_cxlcm_rxc_agf_inserts.cache_rsp1 uncore cxl Number of Allocation to Cache Rsp AGF event=0x43,umask=0x40  01     unc_cxlcm_rxc_agf_inserts.mem_data uncore cxl Number of Allocation to Cache Req AGF 1 event=0x43,umask=0x20  01     unc_cxlcm_rxc_agf_inserts.mem_req uncore cxl Number of Allocation to Mem Data AGF event=0x43,umask=0x10  01     unc_cxlcm_rxc_flits.ak_hdr uncore cxl Count the number of Flits with AK set event=0x4b,umask=0x10  01     unc_cxlcm_rxc_flits.be_hdr uncore cxl Count the number of Flits with BE set event=0x4b,umask=0x20  01     unc_cxlcm_rxc_flits.ctrl uncore cxl Count the number of control flits received event=0x4b,umask=4  01     unc_cxlcm_rxc_flits.no_hdr uncore cxl Count the number of Headerless flits received event=0x4b,umask=8  01     unc_cxlcm_rxc_flits.prot uncore cxl Count the number of protocol flits received event=0x4b,umask=2  01     unc_cxlcm_rxc_flits.sz_hdr uncore cxl Count the number of Flits with SZ set event=0x4b,umask=0x40  01     unc_cxlcm_rxc_flits.valid uncore cxl Count the number of flits received event=0x4b,umask=1  01     unc_cxlcm_rxc_flits.valid_msg uncore cxl Count the number of valid messages in the flit event=0x4b,umask=0x80  01     unc_cxlcm_rxc_misc.crc_errors uncore cxl Count the number of CRC errors detected event=0x40,umask=8  01     unc_cxlcm_rxc_misc.init uncore cxl Count the number of Init flits sent event=0x40,umask=4  01     unc_cxlcm_rxc_misc.llcrd uncore cxl Count the number of LLCRD flits sent event=0x40,umask=1  01     unc_cxlcm_rxc_misc.retry uncore cxl Count the number of Retry flits sent event=0x40,umask=2  01     unc_cxlcm_rxc_pack_buf_full.cache_data uncore cxl Number of cycles the Packing Buffer is Full event=0x52,umask=4  01     unc_cxlcm_rxc_pack_buf_full.cache_req uncore cxl Number of cycles the Packing Buffer is Full event=0x52,umask=1  01     unc_cxlcm_rxc_pack_buf_full.cache_rsp uncore cxl Number of cycles the Packing Buffer is Full event=0x52,umask=2  01     unc_cxlcm_rxc_pack_buf_full.mem_data uncore cxl Number of cycles the Packing Buffer is Full event=0x52,umask=0x10  01     unc_cxlcm_rxc_pack_buf_full.mem_req uncore cxl Number of cycles the Packing Buffer is Full event=0x52,umask=8  01     unc_cxlcm_rxc_pack_buf_inserts.cache_data uncore cxl Number of Allocation to Cache Data Packing buffer event=0x41,umask=4  01     unc_cxlcm_rxc_pack_buf_inserts.cache_req uncore cxl Number of Allocation to Cache Req Packing buffer event=0x41,umask=1  01     unc_cxlcm_rxc_pack_buf_inserts.cache_rsp uncore cxl Number of Allocation to Cache Rsp Packing buffer event=0x41,umask=2  01     unc_cxlcm_rxc_pack_buf_inserts.mem_data uncore cxl Number of Allocation to Mem Data Packing buffer event=0x41,umask=0x10  01     unc_cxlcm_rxc_pack_buf_inserts.mem_req uncore cxl Number of Allocation to Mem Rxx Packing buffer event=0x41,umask=8  01     unc_cxlcm_rxc_pack_buf_ne.cache_data uncore cxl Number of cycles of Not Empty for Cache Data Packing buffer event=0x42,umask=4  01     unc_cxlcm_rxc_pack_buf_ne.cache_req uncore cxl Number of cycles of Not Empty for Cache Req Packing buffer event=0x42,umask=1  01     unc_cxlcm_rxc_pack_buf_ne.cache_rsp uncore cxl Number of cycles of Not Empty for Cache Rsp Packing buffer event=0x42,umask=2  01     unc_cxlcm_rxc_pack_buf_ne.mem_data uncore cxl Number of cycles of Not Empty for Mem Data Packing buffer event=0x42,umask=0x10  01     unc_cxlcm_rxc_pack_buf_ne.mem_req uncore cxl Number of cycles of Not Empty for Mem Rxx Packing buffer event=0x42,umask=8  01     unc_cxlcm_txc_flits.ak_hdr uncore cxl Count the number of Flits with AK set event=5,umask=0x10  01     unc_cxlcm_txc_flits.be_hdr uncore cxl Count the number of Flits with BE set event=5,umask=0x20  01     unc_cxlcm_txc_flits.ctrl uncore cxl Count the number of control flits packed event=5,umask=4  01     unc_cxlcm_txc_flits.no_hdr uncore cxl Count the number of Headerless flits packed event=5,umask=8  01     unc_cxlcm_txc_flits.prot uncore cxl Count the number of protocol flits packed event=5,umask=2  01     unc_cxlcm_txc_flits.sz_hdr uncore cxl Count the number of Flits with SZ set event=5,umask=0x40  01     unc_cxlcm_txc_flits.valid uncore cxl Count the number of flits packed event=5,umask=1  01     unc_cxlcm_txc_pack_buf_inserts.cache_data uncore cxl Number of Allocation to Cache Data Packing buffer event=2,umask=4  01     unc_cxlcm_txc_pack_buf_inserts.cache_req0 uncore cxl Number of Allocation to Cache Req Packing buffer event=2,umask=1  01     unc_cxlcm_txc_pack_buf_inserts.cache_req1 uncore cxl Number of Allocation to Cache Rsp1 Packing buffer event=2,umask=0x40  01     unc_cxlcm_txc_pack_buf_inserts.cache_rsp0 uncore cxl Number of Allocation to Cache Rsp0 Packing buffer event=2,umask=2  01     unc_cxlcm_txc_pack_buf_inserts.cache_rsp1 uncore cxl Number of Allocation to Cache Req Packing buffer event=2,umask=0x20  01     unc_cxlcm_txc_pack_buf_inserts.mem_data uncore cxl Number of Allocation to Mem Data Packing buffer event=2,umask=0x10  01     unc_cxlcm_txc_pack_buf_inserts.mem_req uncore cxl Number of Allocation to Mem Rxx Packing buffer event=2,umask=8  01     uncore_cxldp unc_cxldp_clockticks uncore cxl Counts the number of uclk ticks event=1,umask=1  01     unc_cxldp_txc_agf_inserts.m2s_data uncore cxl Number of Allocation to M2S Data AGF event=2,umask=0x20  01     unc_cxldp_txc_agf_inserts.m2s_req uncore cxl Number of Allocation to M2S Req AGF event=2,umask=0x10  01     unc_cxldp_txc_agf_inserts.u2c_data uncore cxl Number of Allocation to U2C Data AGF event=2,umask=8  01     unc_cxldp_txc_agf_inserts.u2c_req uncore cxl Number of Allocation to U2C Req AGF event=2,umask=1  01     unc_cxldp_txc_agf_inserts.u2c_rsp0 uncore cxl Number of Allocation to U2C Rsp AGF 0 event=2,umask=2  01     unc_cxldp_txc_agf_inserts.u2c_rsp1 uncore cxl Number of Allocation to U2C Rsp AGF 1 event=2,umask=4  01     unc_i_cache_total_occupancy.mem uncore interconnect Total IRP occupancy of inbound read and write requests to coherent memory event=0xf,umask=4  01    Total IRP occupancy of inbound read and write requests to coherent memory.  This is effectively the sum of read occupancy and write occupancy unc_i_clockticks uncore interconnect IRP Clockticks event=1  01    Number of IRP clock cycles while the event is enabled unc_i_faf_inserts uncore interconnect FAF - request insert from TC event=0x18  01     unc_i_faf_occupancy uncore interconnect FAF occupancy event=0x19  01     unc_i_irp_all.evicts uncore interconnect : All Inserts Outbound (BL, AK, Snoops) event=0x20,umask=4  01     unc_i_irp_all.inbound_inserts uncore interconnect : All Inserts Inbound (p2p + faf + cset) event=0x20,umask=1  01     unc_i_irp_all.outbound_inserts uncore interconnect : All Inserts Outbound (BL, AK, Snoops) event=0x20,umask=2  01     unc_i_misc0.2nd_atomic_insert uncore interconnect Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary event=0x1e,umask=0x10  01     unc_i_misc0.2nd_rd_insert uncore interconnect Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary event=0x1e,umask=4  01     unc_i_misc0.2nd_wr_insert uncore interconnect Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary event=0x1e,umask=8  01     unc_i_misc0.fast_rej uncore interconnect Counts Timeouts - Set 0 : Fastpath Rejects event=0x1e,umask=2  01     unc_i_misc0.fast_req uncore interconnect Counts Timeouts - Set 0 : Fastpath Requests event=0x1e,umask=1  01     unc_i_misc0.fast_xfer uncore interconnect Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary event=0x1e,umask=0x20  01     unc_i_misc0.pf_ack_hint uncore interconnect Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary event=0x1e,umask=0x40  01     unc_i_misc0.slowpath_fwpf_no_prf uncore interconnect Counts Timeouts - Set 0 : Slow path fwpf didn't find prefetch event=0x1e,umask=0x80  01     unc_i_misc1.lost_fwd uncore interconnect Misc Events - Set 1 : Lost Forward event=0x1f,umask=0x10  01    Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed unc_i_misc1.sec_rcvd_invld uncore interconnect Misc Events - Set 1 : Received Invalid event=0x1f,umask=0x20  01    Misc Events - Set 1 : Received Invalid : Secondary received a transfer that did not have sufficient MESI state unc_i_misc1.sec_rcvd_vld uncore interconnect Misc Events - Set 1 : Received Valid event=0x1f,umask=0x40  01    Misc Events - Set 1 : Received Valid : Secondary received a transfer that did have sufficient MESI state unc_i_misc1.slow_e uncore interconnect Misc Events - Set 1 : Slow Transfer of E Line event=0x1f,umask=4  01    Misc Events - Set 1 : Slow Transfer of E Line : Secondary received a transfer that did have sufficient MESI state unc_i_misc1.slow_i uncore interconnect Misc Events - Set 1 : Slow Transfer of I Line event=0x1f,umask=1  01    Misc Events - Set 1 : Slow Transfer of I Line : Snoop took cacheline ownership before write from data was committed unc_i_misc1.slow_m uncore interconnect Misc Events - Set 1 : Slow Transfer of M Line event=0x1f,umask=8  01    Misc Events - Set 1 : Slow Transfer of M Line : Snoop took cacheline ownership before write from data was committed unc_i_misc1.slow_s uncore interconnect Misc Events - Set 1 : Slow Transfer of S Line event=0x1f,umask=2  01    Misc Events - Set 1 : Slow Transfer of S Line : Secondary received a transfer that did not have sufficient MESI state unc_i_snoop_resp.hit_es uncore interconnect Snoop Responses : Hit E or S event=0x12,umask=4  01     unc_i_snoop_resp.hit_i uncore interconnect Snoop Responses : Hit I event=0x12,umask=2  01     unc_i_snoop_resp.hit_m uncore interconnect Snoop Responses : Hit M event=0x12,umask=8  01     unc_i_snoop_resp.miss uncore interconnect Snoop Responses : Miss event=0x12,umask=1  01     unc_i_snoop_resp.snpcode uncore interconnect Snoop Responses : SnpCode event=0x12,umask=0x10  01     unc_i_snoop_resp.snpdata uncore interconnect Snoop Responses : SnpData event=0x12,umask=0x20  01     unc_i_snoop_resp.snpinv uncore interconnect Snoop Responses : SnpInv event=0x12,umask=0x40  01     unc_i_txr2_ad01_stall_credit_cycles uncore interconnect UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES event=0x1c  01    : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no Egress Credits available on AD0, A1 or AD0AD1 both. Stalls on both AD0 and AD1 will count as 2 unc_i_txr2_ad0_stall_credit_cycles uncore interconnect No AD0 Egress Credits Stalls event=0x1a  01    No AD0 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD0 Egress Credits available unc_i_txr2_ad1_stall_credit_cycles uncore interconnect No AD1 Egress Credits Stalls event=0x1b  01    No AD1 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD1 Egress Credits available unc_i_txr2_bl_stall_credit_cycles uncore interconnect No BL Egress Credit Stalls event=0x1d  01    No BL Egress Credit Stalls : Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available unc_i_txs_data_inserts_ncb uncore interconnect Outbound Read Requests event=0xd  01    Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices) unc_i_txs_data_inserts_ncs uncore interconnect Outbound Read Requests event=0xe  01    Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices) unc_i_txs_request_occupancy uncore interconnect Outbound Request Queue Occupancy event=0xc  01    Outbound Request Queue Occupancy : Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices).  This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests unc_m2m_clockticks uncore interconnect M2M Clockticks event=1  01    Clockticks of the mesh to memory (M2M) unc_m2m_direct2core_not_taken_dirstate uncore interconnect Cycles when direct to core mode (which bypasses the CHA) was disabled event=0x17,umask=7  01     unc_m2m_direct2core_not_taken_dirstate.non_cisgress uncore interconnect Cycles when direct to core mode, which bypasses the CHA, was disabled : Non Cisgress event=0x17,umask=2  01    Cycles when direct to core mode, which bypasses the CHA, was disabled : Non Cisgress : Counts the number of time non cisgress D2C was not honoured by egress due to directory state constraints unc_m2m_direct2core_not_taken_notforked uncore interconnect Counts the time when FM didn't do d2c for fill reads (cross tile case) event=0x4a  01     unc_m2m_direct2core_txn_override uncore interconnect Number of reads in which direct to core transaction were overridden event=0x18,umask=3  01     unc_m2m_direct2core_txn_override.cisgress uncore interconnect Number of reads in which direct to core transaction was overridden : Cisgress event=0x18,umask=2  01     unc_m2m_direct2core_txn_override.pmm_hit uncore interconnect Number of reads in which direct to core transaction was overridden : 2LM Hit? event=0x18,umask=1  01     unc_m2m_direct2upitxn_override.pmm_hit uncore interconnect Number of times a direct to UPI transaction was overridden event=0x1c,umask=1  01    Number of times a direct to UPI transaction was overridden. : Counts the number of times D2K wasn't honored even though the incoming request had d2k set unc_m2m_direct2upi_not_taken_credits uncore interconnect Number of reads in which direct to Intel UPI transactions were overridden event=0x1b,umask=7  01     unc_m2m_direct2upi_not_taken_dirstate uncore interconnect Cycles when direct to Intel UPI was disabled event=0x1a,umask=7  01     unc_m2m_direct2upi_not_taken_dirstate.cisgress uncore interconnect Cycles when Direct2UPI was Disabled : Cisgress D2U Ignored event=0x1a,umask=4  01    Cycles when Direct2UPI was Disabled : Cisgress D2U Ignored : Counts cisgress d2K that was not honored due to directory constraints unc_m2m_direct2upi_not_taken_dirstate.egress uncore interconnect Cycles when Direct2UPI was Disabled : Egress Ignored D2U event=0x1a,umask=1  01    Cycles when Direct2UPI was Disabled : Egress Ignored D2U : Counts the number of time D2K was not honoured by egress due to directory state constraints unc_m2m_direct2upi_not_taken_dirstate.non_cisgress uncore interconnect Cycles when Direct2UPI was Disabled : Non Cisgress D2U Ignored event=0x1a,umask=2  01    Cycles when Direct2UPI was Disabled : Non Cisgress D2U Ignored : Counts non cisgress d2K that was not honored due to directory constraints unc_m2m_direct2upi_taken uncore interconnect Messages sent direct to the Intel UPI event=0x19,umask=7  01    Counts the number of times egress did D2K (Direct to KTI) unc_m2m_direct2upi_txn_override uncore interconnect Number of reads that a message sent direct2 Intel UPI was overridden event=0x1c,umask=3  01     unc_m2m_direct2upi_txn_override.cisgress uncore interconnect Number of times a direct to UPI transaction was overridden event=0x1c,umask=2  01     unc_m2m_directory_hit.clean_a uncore interconnect Directory Hit : On NonDirty Line in A State event=0x1d,umask=0x80  01     unc_m2m_directory_hit.clean_i uncore interconnect Directory Hit : On NonDirty Line in I State event=0x1d,umask=0x10  01     unc_m2m_directory_hit.clean_p uncore interconnect Directory Hit : On NonDirty Line in L State event=0x1d,umask=0x40  01     unc_m2m_directory_hit.clean_s uncore interconnect Directory Hit : On NonDirty Line in S State event=0x1d,umask=0x20  01     unc_m2m_directory_hit.dirty_a uncore interconnect Directory Hit : On Dirty Line in A State event=0x1d,umask=8  01     unc_m2m_directory_hit.dirty_i uncore interconnect Directory Hit : On Dirty Line in I State event=0x1d,umask=1  01     unc_m2m_directory_hit.dirty_p uncore interconnect Directory Hit : On Dirty Line in L State event=0x1d,umask=4  01     unc_m2m_directory_hit.dirty_s uncore interconnect Directory Hit : On Dirty Line in S State event=0x1d,umask=2  01     unc_m2m_directory_lookup.any uncore interconnect Multi-socket cacheline Directory lookups (any state found) event=0x20,umask=1  01    Counts the number of hit data returns to egress with any directory to non persistent memory unc_m2m_directory_lookup.state_a uncore interconnect Multi-socket cacheline Directory lookups (cacheline found in A state) event=0x20,umask=8  01    Counts the number of hit data returns to egress with directory A to non persistent memory unc_m2m_directory_lookup.state_i uncore interconnect Multi-socket cacheline Directory lookup (cacheline found in I state) event=0x20,umask=2  01    Counts the number of hit data returns to egress with directory I to non persistent memory unc_m2m_directory_lookup.state_s uncore interconnect Multi-socket cacheline Directory lookup (cacheline found in S state) event=0x20,umask=4  01    Counts the number of hit data returns to egress with directory S to non persistent memory unc_m2m_directory_miss.clean_a uncore interconnect Directory Miss : On NonDirty Line in A State event=0x1e,umask=0x80  01     unc_m2m_directory_miss.clean_i uncore interconnect Directory Miss : On NonDirty Line in I State event=0x1e,umask=0x10  01     unc_m2m_directory_miss.clean_p uncore interconnect Directory Miss : On NonDirty Line in L State event=0x1e,umask=0x40  01     unc_m2m_directory_miss.clean_s uncore interconnect Directory Miss : On NonDirty Line in S State event=0x1e,umask=0x20  01     unc_m2m_directory_miss.dirty_a uncore interconnect Directory Miss : On Dirty Line in A State event=0x1e,umask=8  01     unc_m2m_directory_miss.dirty_i uncore interconnect Directory Miss : On Dirty Line in I State event=0x1e,umask=1  01     unc_m2m_directory_miss.dirty_p uncore interconnect Directory Miss : On Dirty Line in L State event=0x1e,umask=4  01     unc_m2m_directory_miss.dirty_s uncore interconnect Directory Miss : On Dirty Line in S State event=0x1e,umask=2  01     unc_m2m_directory_update.a2i uncore interconnect Multi-socket cacheline Directory update from A to I event=0x21,umask=0x320  01     unc_m2m_directory_update.a2s uncore interconnect Multi-socket cacheline Directory update from A to S event=0x21,umask=0x340  01     unc_m2m_directory_update.any uncore interconnect Multi-socket cacheline Directory update from/to Any state event=0x21,umask=0x301  01     unc_m2m_directory_update.a_to_i_hit_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x120  01    Counts 1lm or 2lm hit  data returns that would result in directory update from A to I to non persistent memory (DRAM or HBM) unc_m2m_directory_update.a_to_i_miss_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x220  01    Counts 2lm miss  data returns that would result in directory update from A to I to non persistent memory (DRAM or HBM) unc_m2m_directory_update.a_to_s_hit_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x140  01    Counts 1lm or 2lm hit  data returns that would result in directory update from A to S to non persistent memory (DRAM or HBM) unc_m2m_directory_update.a_to_s_miss_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x240  01    Counts 2lm miss  data returns that would result in directory update from A to S to non persistent memory (DRAM or HBM) unc_m2m_directory_update.hit_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x101  01    Counts any 1lm or 2lm hit data return that would result in directory update to non persistent memory (DRAM or HBM) unc_m2m_directory_update.i2a uncore interconnect Multi-socket cacheline Directory update from I to A event=0x21,umask=0x304  01     unc_m2m_directory_update.i2s uncore interconnect Multi-socket cacheline Directory update from I to S event=0x21,umask=0x302  01     unc_m2m_directory_update.i_to_a_hit_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x104  01    Counts 1lm or 2lm hit  data returns that would result in directory update from I to A to non persistent memory (DRAM or HBM) unc_m2m_directory_update.i_to_a_miss_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x204  01    Counts 2lm miss  data returns that would result in directory update from I to A to non persistent memory (DRAM or HBM) unc_m2m_directory_update.i_to_s_hit_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x102  01    Counts 1lm or 2lm hit  data returns that would result in directory update from I to S to non persistent memory (DRAM or HBM) unc_m2m_directory_update.i_to_s_miss_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x202  01    Counts  2lm miss  data returns that would result in directory update from I to S to non persistent memory (DRAM or HBM) unc_m2m_directory_update.miss_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x201  01    Counts any 2lm miss data return that would result in directory update to non persistent memory (DRAM or HBM) unc_m2m_directory_update.s2a uncore interconnect Multi-socket cacheline Directory update from S to A event=0x21,umask=0x310  01     unc_m2m_directory_update.s2i uncore interconnect Multi-socket cacheline Directory update from S to I event=0x21,umask=0x308  01     unc_m2m_directory_update.s_to_a_hit_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x110  01    Counts 1lm or 2lm hit  data returns that would result in directory update from S to A to non persistent memory (DRAM or HBM) unc_m2m_directory_update.s_to_a_miss_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x210  01    Counts 2lm miss  data returns that would result in directory update from S to A to non persistent memory (DRAM or HBM) unc_m2m_directory_update.s_to_i_hit_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x108  01    Counts 1lm or 2lm hit  data returns that would result in directory update from S to I to non persistent memory (DRAM or HBM) unc_m2m_directory_update.s_to_i_miss_non_pmm uncore interconnect Multi-socket cacheline Directory Updates event=0x21,umask=0x208  01    Counts 2lm miss  data returns that would result in directory update from S to I to non persistent memory (DRAM or HBM) unc_m2m_egress_ordering.iv_snoopgo_dn uncore interconnect Egress Blocking due to Ordering requirements : Down event=0xba,umask=0x80000004  01    Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m2m_egress_ordering.iv_snoopgo_up uncore interconnect Egress Blocking due to Ordering requirements : Up event=0xba,umask=0x80000001  01    Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m2m_igr_starve_winner.mask7 uncore interconnect Count when Starve Glocab counter is at 7 event=0x44,umask=0x80  01     unc_m2m_imc_reads.all uncore interconnect Reads to iMC issued event=0x24,umask=0x304  01     unc_m2m_imc_reads.ch0.to_nm1lm uncore interconnect UNC_M2M_IMC_READS.CH0.TO_NM1LM event=0x24,umask=0x108  01     unc_m2m_imc_reads.ch0.to_nmcache uncore interconnect UNC_M2M_IMC_READS.CH0.TO_NMCache event=0x24,umask=0x110  01     unc_m2m_imc_reads.ch0_all uncore interconnect UNC_M2M_IMC_READS.CH0_ALL event=0x24,umask=0x104  01     unc_m2m_imc_reads.ch0_from_tgr uncore interconnect UNC_M2M_IMC_READS.CH0_FROM_TGR event=0x24,umask=0x140  01     unc_m2m_imc_reads.ch0_isoch uncore interconnect UNC_M2M_IMC_READS.CH0_ISOCH event=0x24,umask=0x102  01     unc_m2m_imc_reads.ch0_normal uncore interconnect UNC_M2M_IMC_READS.CH0_NORMAL event=0x24,umask=0x101  01     unc_m2m_imc_reads.ch0_to_ddr_as_cache uncore interconnect UNC_M2M_IMC_READS.CH0_TO_DDR_AS_CACHE event=0x24,umask=0x110  01     unc_m2m_imc_reads.ch0_to_ddr_as_mem uncore interconnect UNC_M2M_IMC_READS.CH0_TO_DDR_AS_MEM event=0x24,umask=0x108  01     unc_m2m_imc_reads.ch0_to_pmm uncore interconnect UNC_M2M_IMC_READS.CH0_TO_PMM event=0x24,umask=0x120  01     unc_m2m_imc_reads.ch1.to_nm1lm uncore interconnect UNC_M2M_IMC_READS.CH1.TO_NM1LM event=0x24,umask=0x208  01     unc_m2m_imc_reads.ch1.to_nmcache uncore interconnect UNC_M2M_IMC_READS.CH1.TO_NMCache event=0x24,umask=0x210  01     unc_m2m_imc_reads.ch1_all uncore interconnect UNC_M2M_IMC_READS.CH1_ALL event=0x24,umask=0x204  01     unc_m2m_imc_reads.ch1_from_tgr uncore interconnect UNC_M2M_IMC_READS.CH1_FROM_TGR event=0x24,umask=0x240  01     unc_m2m_imc_reads.ch1_isoch uncore interconnect UNC_M2M_IMC_READS.CH1_ISOCH event=0x24,umask=0x202  01     unc_m2m_imc_reads.ch1_normal uncore interconnect UNC_M2M_IMC_READS.CH1_NORMAL event=0x24,umask=0x201  01     unc_m2m_imc_reads.ch1_to_ddr_as_cache uncore interconnect UNC_M2M_IMC_READS.CH1_TO_DDR_AS_CACHE event=0x24,umask=0x210  01     unc_m2m_imc_reads.ch1_to_ddr_as_mem uncore interconnect UNC_M2M_IMC_READS.CH1_TO_DDR_AS_MEM event=0x24,umask=0x208  01     unc_m2m_imc_reads.ch1_to_pmm uncore interconnect UNC_M2M_IMC_READS.CH1_TO_PMM event=0x24,umask=0x220  01     unc_m2m_imc_reads.from_tgr uncore interconnect UNC_M2M_IMC_READS.FROM_TGR event=0x24,umask=0x340  01     unc_m2m_imc_reads.isoch uncore interconnect UNC_M2M_IMC_READS.ISOCH event=0x24,umask=0x302  01     unc_m2m_imc_reads.normal uncore interconnect UNC_M2M_IMC_READS.NORMAL event=0x24,umask=0x301  01     unc_m2m_imc_reads.to_ddr_as_cache uncore interconnect UNC_M2M_IMC_READS.TO_DDR_AS_CACHE event=0x24,umask=0x310  01     unc_m2m_imc_reads.to_ddr_as_mem uncore interconnect UNC_M2M_IMC_READS.TO_DDR_AS_MEM event=0x24,umask=0x308  01     unc_m2m_imc_reads.to_nm1lm uncore interconnect UNC_M2M_IMC_READS.TO_NM1LM event=0x24,umask=0x308  01     unc_m2m_imc_reads.to_nmcache uncore interconnect UNC_M2M_IMC_READS.TO_NMCACHE event=0x24,umask=0x310  01     unc_m2m_imc_reads.to_pmm uncore interconnect UNC_M2M_IMC_READS.TO_PMM event=0x24,umask=0x320  01     unc_m2m_imc_writes.all uncore interconnect All Writes - All Channels event=0x25,umask=0x1810  01     unc_m2m_imc_writes.ch0.ni uncore interconnect Non-Inclusive - Ch0 event=0x25  01     unc_m2m_imc_writes.ch0_all uncore interconnect UNC_M2M_IMC_WRITES.CH0_ALL event=0x25,umask=0x810  01     unc_m2m_imc_writes.ch0_from_tgr uncore interconnect From TGR - Ch0 event=0x25  01     unc_m2m_imc_writes.ch0_full uncore interconnect UNC_M2M_IMC_WRITES.CH0_FULL event=0x25,umask=0x801  01     unc_m2m_imc_writes.ch0_full_isoch uncore interconnect UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH event=0x25,umask=0x804  01     unc_m2m_imc_writes.ch0_ni uncore interconnect Non-Inclusive - Ch0 event=0x25  01     unc_m2m_imc_writes.ch0_ni_miss uncore interconnect Non-Inclusive Miss - Ch0 event=0x25  01     unc_m2m_imc_writes.ch0_partial uncore interconnect UNC_M2M_IMC_WRITES.CH0_PARTIAL event=0x25,umask=0x802  01     unc_m2m_imc_writes.ch0_partial_isoch uncore interconnect UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH event=0x25,umask=0x808  01     unc_m2m_imc_writes.ch0_to_ddr_as_cache uncore interconnect DDR, acting as Cache - Ch0 event=0x25,umask=0x840  01     unc_m2m_imc_writes.ch0_to_ddr_as_mem uncore interconnect UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_MEM event=0x25,umask=0x820  01     unc_m2m_imc_writes.ch0_to_pmm uncore interconnect PMM - Ch0 event=0x25,umask=0x880  01    PMM - Ch0 : Counts all PMM dimm writes requests(full line and partial) sent from M2M to iMC unc_m2m_imc_writes.ch1.ni uncore interconnect Non-Inclusive - Ch1 event=0x25  01     unc_m2m_imc_writes.ch1_all uncore interconnect All Writes - Ch1 event=0x25,umask=0x1010  01     unc_m2m_imc_writes.ch1_from_tgr uncore interconnect From TGR - Ch1 event=0x25  01     unc_m2m_imc_writes.ch1_full uncore interconnect Full Line Non-ISOCH - Ch1 event=0x25,umask=0x1001  01     unc_m2m_imc_writes.ch1_full_isoch uncore interconnect ISOCH Full Line - Ch1 event=0x25,umask=0x1004  01     unc_m2m_imc_writes.ch1_ni uncore interconnect Non-Inclusive - Ch1 event=0x25  01     unc_m2m_imc_writes.ch1_ni_miss uncore interconnect Non-Inclusive Miss - Ch1 event=0x25  01     unc_m2m_imc_writes.ch1_partial uncore interconnect Partial Non-ISOCH - Ch1 event=0x25,umask=0x1002  01     unc_m2m_imc_writes.ch1_partial_isoch uncore interconnect ISOCH Partial - Ch1 event=0x25,umask=0x1008  01     unc_m2m_imc_writes.ch1_to_ddr_as_cache uncore interconnect DDR, acting as Cache - Ch1 event=0x25,umask=0x1040  01     unc_m2m_imc_writes.ch1_to_ddr_as_mem uncore interconnect DDR - Ch1 event=0x25,umask=0x1020  01     unc_m2m_imc_writes.ch1_to_pmm uncore interconnect PMM - Ch1 event=0x25,umask=0x1080  01    PMM - Ch1 : Counts all PMM dimm writes requests(full line and partial) sent from M2M to iMC unc_m2m_imc_writes.from_tgr uncore interconnect From TGR - All Channels event=0x25  01     unc_m2m_imc_writes.full uncore interconnect Full Non-ISOCH - All Channels event=0x25,umask=0x1801  01     unc_m2m_imc_writes.full_isoch uncore interconnect ISOCH Full Line - All Channels event=0x25,umask=0x1804  01     unc_m2m_imc_writes.ni uncore interconnect Non-Inclusive - All Channels event=0x25  01     unc_m2m_imc_writes.ni_miss uncore interconnect Non-Inclusive Miss - All Channels event=0x25  01     unc_m2m_imc_writes.partial uncore interconnect Partial Non-ISOCH - All Channels event=0x25,umask=0x1802  01     unc_m2m_imc_writes.partial_isoch uncore interconnect ISOCH Partial - All Channels event=0x25,umask=0x1808  01     unc_m2m_imc_writes.to_ddr_as_cache uncore interconnect DDR, acting as Cache - All Channels event=0x25,umask=0x1840  01     unc_m2m_imc_writes.to_ddr_as_mem uncore interconnect DDR - All Channels event=0x25,umask=0x1820  01     unc_m2m_imc_writes.to_pmm uncore interconnect PMM - All Channels event=0x25,umask=0x1880  01     unc_m2m_prefcam_cis_drops uncore interconnect UNC_M2M_PREFCAM_CIS_DROPS event=0x5c  01     unc_m2m_prefcam_demand_drops.ch0_upi uncore interconnect Data Prefetches Dropped event=0x58,umask=2  01     unc_m2m_prefcam_demand_drops.ch0_xpt uncore interconnect Data Prefetches Dropped event=0x58,umask=1  01     unc_m2m_prefcam_demand_drops.ch1_upi uncore interconnect Data Prefetches Dropped event=0x58,umask=8  01     unc_m2m_prefcam_demand_drops.ch1_xpt uncore interconnect Data Prefetches Dropped event=0x58,umask=4  01     unc_m2m_prefcam_demand_drops.upi_allch uncore interconnect Data Prefetches Dropped : UPI - All Channels event=0x58,umask=0xa  01     unc_m2m_prefcam_demand_drops.xpt_allch uncore interconnect Data Prefetches Dropped event=0x58,umask=5  01     unc_m2m_prefcam_demand_merge.upi_allch uncore interconnect : UPI - All Channels event=0x5d,umask=0xa  01     unc_m2m_prefcam_demand_merge.xpt_allch uncore interconnect : XPT - All Channels event=0x5d,umask=5  01     unc_m2m_prefcam_demand_no_merge.rd_merged uncore interconnect Demands Not Merged with CAMed Prefetches event=0x5e,umask=0x40  01     unc_m2m_prefcam_demand_no_merge.wr_merged uncore interconnect Demands Not Merged with CAMed Prefetches event=0x5e,umask=0x20  01     unc_m2m_prefcam_demand_no_merge.wr_squashed uncore interconnect Demands Not Merged with CAMed Prefetches event=0x5e,umask=0x10  01     unc_m2m_prefcam_inserts.ch0_upi uncore interconnect Prefetch CAM Inserts : UPI - Ch 0 event=0x56,umask=2  01     unc_m2m_prefcam_inserts.ch0_xpt uncore interconnect Prefetch CAM Inserts : XPT - Ch 0 event=0x56,umask=1  01     unc_m2m_prefcam_inserts.ch1_upi uncore interconnect Prefetch CAM Inserts : UPI - Ch 1 event=0x56,umask=8  01     unc_m2m_prefcam_inserts.ch1_xpt uncore interconnect Prefetch CAM Inserts : XPT - Ch 1 event=0x56,umask=4  01     unc_m2m_prefcam_inserts.upi_allch uncore interconnect Prefetch CAM Inserts : UPI - All Channels event=0x56,umask=0xa  01     unc_m2m_prefcam_inserts.xpt_allch uncore interconnect Prefetch CAM Inserts : XPT - All Channels event=0x56,umask=5  01    Prefetch CAM Inserts : XPT -All Channels unc_m2m_prefcam_occupancy.allch uncore interconnect Prefetch CAM Occupancy : All Channels event=0x54,umask=3  01     unc_m2m_prefcam_occupancy.ch0 uncore interconnect Prefetch CAM Occupancy : Channel 0 event=0x54,umask=1  01     unc_m2m_prefcam_occupancy.ch1 uncore interconnect Prefetch CAM Occupancy : Channel 1 event=0x54,umask=2  01     unc_m2m_prefcam_resp_miss.allch uncore interconnect All Channels event=0x5f,umask=3  01     unc_m2m_prefcam_resp_miss.ch0 uncore interconnect : Channel 0 event=0x5f,umask=1  01     unc_m2m_prefcam_resp_miss.ch1 uncore interconnect : Channel 1 event=0x5f,umask=2  01     unc_m2m_prefcam_rxc_deallocs.1lm_posted uncore interconnect UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED event=0x62,umask=2  01     unc_m2m_prefcam_rxc_deallocs.cis uncore interconnect UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS event=0x62,umask=8  01     unc_m2m_prefcam_rxc_deallocs.pmm_memmode_accept uncore interconnect UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT event=0x62,umask=4  01     unc_m2m_prefcam_rxc_deallocs.squashed uncore interconnect UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED event=0x62,umask=1  01     unc_m2m_prefcam_rxc_occupancy uncore interconnect AD Ingress (from CMS) Occupancy - Prefetches event=0x60  01     unc_m2m_rxc_ad_inserts uncore interconnect AD Ingress (from CMS) : AD Ingress (from CMS) Allocations event=2,umask=1  01     unc_m2m_rxc_ad_occupancy uncore interconnect AD Ingress (from CMS) Occupancy event=3  01     unc_m2m_tag_hit.nm_rd_hit_clean uncore interconnect Clean NearMem Read Hit event=0x1f,umask=1  01    Counts clean full line read hits (reads and RFOs) unc_m2m_tag_hit.nm_rd_hit_dirty uncore interconnect Dirty NearMem Read Hit event=0x1f,umask=2  01    Counts dirty full line read hits (reads and RFOs) unc_m2m_tag_hit.nm_ufill_hit_clean uncore interconnect Tag Hit : Clean NearMem Underfill Hit event=0x1f,umask=4  01    Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts clean underfill hits due to a partial write unc_m2m_tag_hit.nm_ufill_hit_dirty uncore interconnect Tag Hit : Dirty NearMem Underfill Hit event=0x1f,umask=8  01    Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts dirty underfill read hits due to a partial write unc_m2m_tag_miss uncore interconnect UNC_M2M_TAG_MISS event=0x4b,umask=3  01     unc_m2m_tgr_ad_credits uncore interconnect Number AD Ingress Credits event=0x2e  01     unc_m2m_tgr_bl_credits uncore interconnect Number BL Ingress Credits event=0x2f  01     unc_m2m_tracker_inserts.ch0 uncore interconnect Tracker Inserts : Channel 0 event=0x32,umask=0x104  01     unc_m2m_tracker_inserts.ch1 uncore interconnect Tracker Inserts : Channel 1 event=0x32,umask=0x204  01     unc_m2m_tracker_occupancy.ch0 uncore interconnect Tracker Occupancy : Channel 0 event=0x33,umask=1  01     unc_m2m_tracker_occupancy.ch1 uncore interconnect Tracker Occupancy : Channel 1 event=0x33,umask=2  01     unc_m2m_wpq_flush.ch0 uncore interconnect WPQ Flush : Channel 0 event=0x42,umask=1  01     unc_m2m_wpq_flush.ch1 uncore interconnect WPQ Flush : Channel 1 event=0x42,umask=2  01     unc_m2m_wpq_no_reg_crd.chn0 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular : Channel 0 event=0x37,umask=1  01     unc_m2m_wpq_no_reg_crd.chn1 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular : Channel 1 event=0x37,umask=2  01     unc_m2m_wpq_no_spec_crd.chn0 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Special : Channel 0 event=0x38,umask=1  01     unc_m2m_wpq_no_spec_crd.chn1 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Special : Channel 1 event=0x38,umask=2  01     unc_m2m_wr_tracker_inserts.ch0 uncore interconnect Write Tracker Inserts : Channel 0 event=0x40,umask=1  01     unc_m2m_wr_tracker_inserts.ch1 uncore interconnect Write Tracker Inserts : Channel 1 event=0x40,umask=2  01     unc_m2m_wr_tracker_ne.ch0 uncore interconnect Write Tracker Cycles Not Empty : Channel 0 event=0x35,umask=1  01     unc_m2m_wr_tracker_ne.ch1 uncore interconnect Write Tracker Cycles Not Empty : Channel 1 event=0x35,umask=2  01     unc_m2m_wr_tracker_ne.mirr uncore interconnect Write Tracker Cycles Not Empty : Mirror event=0x35,umask=4  01     unc_m2m_wr_tracker_ne.mirr_nontgr uncore interconnect Write Tracker Cycles Not Empty event=0x35,umask=8  01     unc_m2m_wr_tracker_ne.mirr_pwr uncore interconnect Write Tracker Cycles Not Empty event=0x35,umask=0x10  01     unc_m2m_wr_tracker_nonposted_inserts.ch0 uncore interconnect Write Tracker Non-Posted Inserts : Channel 0 event=0x4d,umask=1  01     unc_m2m_wr_tracker_nonposted_inserts.ch1 uncore interconnect Write Tracker Non-Posted Inserts : Channel 1 event=0x4d,umask=2  01     unc_m2m_wr_tracker_nonposted_occupancy.ch0 uncore interconnect Write Tracker Non-Posted Occupancy : Channel 0 event=0x4c,umask=1  01     unc_m2m_wr_tracker_nonposted_occupancy.ch1 uncore interconnect Write Tracker Non-Posted Occupancy : Channel 1 event=0x4c,umask=2  01     unc_m2m_wr_tracker_posted_inserts.ch0 uncore interconnect Write Tracker Posted Inserts : Channel 0 event=0x48,umask=1  01     unc_m2m_wr_tracker_posted_inserts.ch1 uncore interconnect Write Tracker Posted Inserts : Channel 1 event=0x48,umask=2  01     unc_m2m_wr_tracker_posted_occupancy.ch0 uncore interconnect Write Tracker Posted Occupancy : Channel 0 event=0x47,umask=1  01     unc_m2m_wr_tracker_posted_occupancy.ch1 uncore interconnect Write Tracker Posted Occupancy : Channel 1 event=0x47,umask=2  01     unc_m3upi_cha_ad_credits_empty.req uncore interconnect CBox AD Credits Empty : Requests event=0x22,umask=4  01    CBox AD Credits Empty : Requests : No credits available to send to Cbox on the AD Ring (covers higher CBoxes) unc_m3upi_cha_ad_credits_empty.snp uncore interconnect CBox AD Credits Empty : Snoops event=0x22,umask=8  01    CBox AD Credits Empty : Snoops : No credits available to send to Cbox on the AD Ring (covers higher CBoxes) unc_m3upi_cha_ad_credits_empty.vna uncore interconnect CBox AD Credits Empty : VNA Messages event=0x22,umask=1  01    CBox AD Credits Empty : VNA Messages : No credits available to send to Cbox on the AD Ring (covers higher CBoxes) unc_m3upi_cha_ad_credits_empty.wb uncore interconnect CBox AD Credits Empty : Writebacks event=0x22,umask=2  01    CBox AD Credits Empty : Writebacks : No credits available to send to Cbox on the AD Ring (covers higher CBoxes) unc_m3upi_clockticks uncore interconnect M3UPI Clockticks event=1  01    Number of M2UPI clock cycles while the event is enabled unc_m3upi_cms_clockticks uncore interconnect M3UPI CMS Clockticks event=0xc0  01     unc_m3upi_d2c_sent uncore interconnect D2C Sent event=0x2b  01    D2C Sent : Count cases BL sends direct to core unc_m3upi_d2u_sent uncore interconnect D2U Sent event=0x2a  01    D2U Sent : Cases where SMI3 sends D2U command unc_m3upi_egress_ordering.iv_snoopgo_dn uncore interconnect Egress Blocking due to Ordering requirements : Down event=0xba,umask=4  01    Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m3upi_egress_ordering.iv_snoopgo_up uncore interconnect Egress Blocking due to Ordering requirements : Up event=0xba,umask=1  01    Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m3upi_m2_bl_credits_empty.iio1_ncb uncore interconnect M2 BL Credits Empty : IIO0 and IIO1 share the same ring destination. (1 VN0 credit only) event=0x23,umask=1  01    M2 BL Credits Empty : IIO0 and IIO1 share the same ring destination. (1 VN0 credit only) : No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.iio2_ncb uncore interconnect M2 BL Credits Empty : IIO2 event=0x23,umask=2  01    M2 BL Credits Empty : IIO2 : No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.iio3_ncb uncore interconnect M2 BL Credits Empty : IIO3 event=0x23,umask=4  01    M2 BL Credits Empty : IIO3 : No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.iio4_ncb uncore interconnect M2 BL Credits Empty : IIO4 event=0x23,umask=8  01    M2 BL Credits Empty : IIO4 : No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.iio5_ncb uncore interconnect M2 BL Credits Empty : IIO5 event=0x23,umask=0x10  01    M2 BL Credits Empty : IIO5 : No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.ncs uncore interconnect M2 BL Credits Empty : All IIO targets for NCS are in single mask. ORs them together event=0x23,umask=0x40  01    M2 BL Credits Empty : All IIO targets for NCS are in single mask. ORs them together : No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.ncs_sel uncore interconnect M2 BL Credits Empty : Selected M2p BL NCS credits event=0x23,umask=0x80  01    M2 BL Credits Empty : Selected M2p BL NCS credits : No vn0 and vna credits available to send to M2 unc_m3upi_m2_bl_credits_empty.ubox_ncb uncore interconnect M2 BL Credits Empty : IIO5 event=0x23,umask=0x20  01    M2 BL Credits Empty : IIO5 : No vn0 and vna credits available to send to M2 unc_m3upi_multi_slot_rcvd.ad_slot0 uncore interconnect Multi Slot Flit Received : AD - Slot 0 event=0x3e,umask=1  01    Multi Slot Flit Received : AD - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_multi_slot_rcvd.ad_slot1 uncore interconnect Multi Slot Flit Received : AD - Slot 1 event=0x3e,umask=2  01    Multi Slot Flit Received : AD - Slot 1 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_multi_slot_rcvd.ad_slot2 uncore interconnect Multi Slot Flit Received : AD - Slot 2 event=0x3e,umask=4  01    Multi Slot Flit Received : AD - Slot 2 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_multi_slot_rcvd.ak_slot0 uncore interconnect Multi Slot Flit Received : AK - Slot 0 event=0x3e,umask=0x10  01    Multi Slot Flit Received : AK - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_multi_slot_rcvd.ak_slot2 uncore interconnect Multi Slot Flit Received : AK - Slot 2 event=0x3e,umask=0x20  01    Multi Slot Flit Received : AK - Slot 2 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_multi_slot_rcvd.bl_slot0 uncore interconnect Multi Slot Flit Received : BL - Slot 0 event=0x3e,umask=8  01    Multi Slot Flit Received : BL - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations) unc_m3upi_rxc_arb_lost_vn0.ad_req uncore interconnect Lost Arb for VN0 : REQ on AD event=0x4b,umask=1  01    Lost Arb for VN0 : REQ on AD : VN0 message requested but lost arbitration : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_lost_vn0.ad_rsp uncore interconnect Lost Arb for VN0 : RSP on AD event=0x4b,umask=4  01    Lost Arb for VN0 : RSP on AD : VN0 message requested but lost arbitration : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_lost_vn0.ad_snp uncore interconnect Lost Arb for VN0 : SNP on AD event=0x4b,umask=2  01    Lost Arb for VN0 : SNP on AD : VN0 message requested but lost arbitration : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_rxc_arb_lost_vn0.bl_ncb uncore interconnect Lost Arb for VN0 : NCB on BL event=0x4b,umask=0x20  01    Lost Arb for VN0 : NCB on BL : VN0 message requested but lost arbitration : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_rxc_arb_lost_vn0.bl_ncs uncore interconnect Lost Arb for VN0 : NCS on BL event=0x4b,umask=0x40  01    Lost Arb for VN0 : NCS on BL : VN0 message requested but lost arbitration : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_lost_vn0.bl_rsp uncore interconnect Lost Arb for VN0 : RSP on BL event=0x4b,umask=8  01    Lost Arb for VN0 : RSP on BL : VN0 message requested but lost arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_lost_vn0.bl_wb uncore interconnect Lost Arb for VN0 : WB on BL event=0x4b,umask=0x10  01    Lost Arb for VN0 : WB on BL : VN0 message requested but lost arbitration : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_arb_lost_vn1.ad_req uncore interconnect Lost Arb for VN1 : REQ on AD event=0x4c,umask=1  01    Lost Arb for VN1 : REQ on AD : VN1 message requested but lost arbitration : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_lost_vn1.ad_rsp uncore interconnect Lost Arb for VN1 : RSP on AD event=0x4c,umask=4  01    Lost Arb for VN1 : RSP on AD : VN1 message requested but lost arbitration : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_lost_vn1.ad_snp uncore interconnect Lost Arb for VN1 : SNP on AD event=0x4c,umask=2  01    Lost Arb for VN1 : SNP on AD : VN1 message requested but lost arbitration : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_rxc_arb_lost_vn1.bl_ncb uncore interconnect Lost Arb for VN1 : NCB on BL event=0x4c,umask=0x20  01    Lost Arb for VN1 : NCB on BL : VN1 message requested but lost arbitration : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_rxc_arb_lost_vn1.bl_ncs uncore interconnect Lost Arb for VN1 : NCS on BL event=0x4c,umask=0x40  01    Lost Arb for VN1 : NCS on BL : VN1 message requested but lost arbitration : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_lost_vn1.bl_rsp uncore interconnect Lost Arb for VN1 : RSP on BL event=0x4c,umask=8  01    Lost Arb for VN1 : RSP on BL : VN1 message requested but lost arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_lost_vn1.bl_wb uncore interconnect Lost Arb for VN1 : WB on BL event=0x4c,umask=0x10  01    Lost Arb for VN1 : WB on BL : VN1 message requested but lost arbitration : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_arb_misc.adbl_parallel_win_vn0 uncore interconnect Arb Miscellaneous : AD, BL Parallel Win VN0 event=0x4d,umask=0x10  01    Arb Miscellaneous : AD, BL Parallel Win VN0 : AD and BL messages won arbitration concurrently / in parallel unc_m3upi_rxc_arb_misc.adbl_parallel_win_vn1 uncore interconnect Arb Miscellaneous : AD, BL Parallel Win VN1 event=0x4d,umask=0x20  01    Arb Miscellaneous : AD, BL Parallel Win VN1 : AD and BL messages won arbitration concurrently / in parallel unc_m3upi_rxc_arb_misc.all_parallel_win uncore interconnect Arb Miscellaneous : Max Parallel Win event=0x4d,umask=0x80  01    Arb Miscellaneous : Max Parallel Win : VN0 and VN1 arbitration sub-pipelines both produced AD and BL winners (maximum possible parallel winners) unc_m3upi_rxc_arb_misc.no_prog_ad_vn0 uncore interconnect Arb Miscellaneous : No Progress on Pending AD VN0 event=0x4d,umask=1  01    Arb Miscellaneous : No Progress on Pending AD VN0 : Arbitration stage made no progress on pending ad vn0 messages because slotting stage cannot accept new message unc_m3upi_rxc_arb_misc.no_prog_ad_vn1 uncore interconnect Arb Miscellaneous : No Progress on Pending AD VN1 event=0x4d,umask=2  01    Arb Miscellaneous : No Progress on Pending AD VN1 : Arbitration stage made no progress on pending ad vn1 messages because slotting stage cannot accept new message unc_m3upi_rxc_arb_misc.no_prog_bl_vn0 uncore interconnect Arb Miscellaneous : No Progress on Pending BL VN0 event=0x4d,umask=4  01    Arb Miscellaneous : No Progress on Pending BL VN0 : Arbitration stage made no progress on pending bl vn0 messages because slotting stage cannot accept new message unc_m3upi_rxc_arb_misc.no_prog_bl_vn1 uncore interconnect Arb Miscellaneous : No Progress on Pending BL VN1 event=0x4d,umask=8  01    Arb Miscellaneous : No Progress on Pending BL VN1 : Arbitration stage made no progress on pending bl vn1 messages because slotting stage cannot accept new message unc_m3upi_rxc_arb_misc.vn01_parallel_win uncore interconnect Arb Miscellaneous : VN0, VN1 Parallel Win event=0x4d,umask=0x40  01    Arb Miscellaneous : VN0, VN1 Parallel Win : VN0 and VN1 arbitration sub-pipelines had parallel winners (at least one AD or BL on each side) unc_m3upi_rxc_arb_nocrd_vn0.ad_req uncore interconnect No Credits to Arb for VN0 : REQ on AD event=0x47,umask=1  01    No Credits to Arb for VN0 : REQ on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_nocrd_vn0.ad_rsp uncore interconnect No Credits to Arb for VN0 : RSP on AD event=0x47,umask=4  01    No Credits to Arb for VN0 : RSP on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_nocrd_vn0.ad_snp uncore interconnect No Credits to Arb for VN0 : SNP on AD event=0x47,umask=2  01    No Credits to Arb for VN0 : SNP on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_rxc_arb_nocrd_vn0.bl_ncb uncore interconnect No Credits to Arb for VN0 : NCB on BL event=0x47,umask=0x20  01    No Credits to Arb for VN0 : NCB on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_rxc_arb_nocrd_vn0.bl_ncs uncore interconnect No Credits to Arb for VN0 : NCS on BL event=0x47,umask=0x40  01    No Credits to Arb for VN0 : NCS on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_nocrd_vn0.bl_rsp uncore interconnect No Credits to Arb for VN0 : RSP on BL event=0x47,umask=8  01    No Credits to Arb for VN0 : RSP on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_nocrd_vn0.bl_wb uncore interconnect No Credits to Arb for VN0 : WB on BL event=0x47,umask=0x10  01    No Credits to Arb for VN0 : WB on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_arb_nocrd_vn1.ad_req uncore interconnect No Credits to Arb for VN1 : REQ on AD event=0x48,umask=1  01    No Credits to Arb for VN1 : REQ on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_nocrd_vn1.ad_rsp uncore interconnect No Credits to Arb for VN1 : RSP on AD event=0x48,umask=4  01    No Credits to Arb for VN1 : RSP on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_nocrd_vn1.ad_snp uncore interconnect No Credits to Arb for VN1 : SNP on AD event=0x48,umask=2  01    No Credits to Arb for VN1 : SNP on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_rxc_arb_nocrd_vn1.bl_ncb uncore interconnect No Credits to Arb for VN1 : NCB on BL event=0x48,umask=0x20  01    No Credits to Arb for VN1 : NCB on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_rxc_arb_nocrd_vn1.bl_ncs uncore interconnect No Credits to Arb for VN1 : NCS on BL event=0x48,umask=0x40  01    No Credits to Arb for VN1 : NCS on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_nocrd_vn1.bl_rsp uncore interconnect No Credits to Arb for VN1 : RSP on BL event=0x48,umask=8  01    No Credits to Arb for VN1 : RSP on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_nocrd_vn1.bl_wb uncore interconnect No Credits to Arb for VN1 : WB on BL event=0x48,umask=0x10  01    No Credits to Arb for VN1 : WB on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_arb_noreq_vn0.ad_req uncore interconnect Can't Arb for VN0 : REQ on AD event=0x49,umask=1  01    Can't Arb for VN0 : REQ on AD : VN0 message was not able to request arbitration while some other message won arbitration : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_noreq_vn0.ad_rsp uncore interconnect Can't Arb for VN0 : RSP on AD event=0x49,umask=4  01    Can't Arb for VN0 : RSP on AD : VN0 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_noreq_vn0.ad_snp uncore interconnect Can't Arb for VN0 : SNP on AD event=0x49,umask=2  01    Can't Arb for VN0 : SNP on AD : VN0 message was not able to request arbitration while some other message won arbitration : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_rxc_arb_noreq_vn0.bl_ncb uncore interconnect Can't Arb for VN0 : NCB on BL event=0x49,umask=0x20  01    Can't Arb for VN0 : NCB on BL : VN0 message was not able to request arbitration while some other message won arbitration : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_rxc_arb_noreq_vn0.bl_ncs uncore interconnect Can't Arb for VN0 : NCS on BL event=0x49,umask=0x40  01    Can't Arb for VN0 : NCS on BL : VN0 message was not able to request arbitration while some other message won arbitration : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_noreq_vn0.bl_rsp uncore interconnect Can't Arb for VN0 : RSP on BL event=0x49,umask=8  01    Can't Arb for VN0 : RSP on BL : VN0 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_noreq_vn0.bl_wb uncore interconnect Can't Arb for VN0 : WB on BL event=0x49,umask=0x10  01    Can't Arb for VN0 : WB on BL : VN0 message was not able to request arbitration while some other message won arbitration : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_arb_noreq_vn1.ad_req uncore interconnect Can't Arb for VN1 : REQ on AD event=0x4a,umask=1  01    Can't Arb for VN1 : REQ on AD : VN1 message was not able to request arbitration while some other message won arbitration : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_arb_noreq_vn1.ad_rsp uncore interconnect Can't Arb for VN1 : RSP on AD event=0x4a,umask=4  01    Can't Arb for VN1 : RSP on AD : VN1 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_noreq_vn1.ad_snp uncore interconnect Can't Arb for VN1 : SNP on AD event=0x4a,umask=2  01    Can't Arb for VN1 : SNP on AD : VN1 message was not able to request arbitration while some other message won arbitration : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_rxc_arb_noreq_vn1.bl_ncb uncore interconnect Can't Arb for VN1 : NCB on BL event=0x4a,umask=0x20  01    Can't Arb for VN1 : NCB on BL : VN1 message was not able to request arbitration while some other message won arbitration : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_rxc_arb_noreq_vn1.bl_ncs uncore interconnect Can't Arb for VN1 : NCS on BL event=0x4a,umask=0x40  01    Can't Arb for VN1 : NCS on BL : VN1 message was not able to request arbitration while some other message won arbitration : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_arb_noreq_vn1.bl_rsp uncore interconnect Can't Arb for VN1 : RSP on BL event=0x4a,umask=8  01    Can't Arb for VN1 : RSP on BL : VN1 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_arb_noreq_vn1.bl_wb uncore interconnect Can't Arb for VN1 : WB on BL event=0x4a,umask=0x10  01    Can't Arb for VN1 : WB on BL : VN1 message was not able to request arbitration while some other message won arbitration : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_bypassed.ad_s0_bl_arb uncore interconnect Ingress Queue Bypasses : AD to Slot 0 on BL Arb event=0x40,umask=2  01    Ingress Queue Bypasses : AD to Slot 0 on BL Arb : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to slot 0 of independent flit while bl message is in arbitration unc_m3upi_rxc_bypassed.ad_s0_idle uncore interconnect Ingress Queue Bypasses : AD to Slot 0 on Idle event=0x40,umask=1  01    Ingress Queue Bypasses : AD to Slot 0 on Idle : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to slot 0 of independent flit while pipeline is idle unc_m3upi_rxc_bypassed.ad_s1_bl_slot uncore interconnect Ingress Queue Bypasses : AD + BL to Slot 1 event=0x40,umask=4  01    Ingress Queue Bypasses : AD + BL to Slot 1 : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to flit slot 1 while merging with bl message in same flit unc_m3upi_rxc_bypassed.ad_s2_bl_slot uncore interconnect Ingress Queue Bypasses : AD + BL to Slot 2 event=0x40,umask=8  01    Ingress Queue Bypasses : AD + BL to Slot 2 : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to flit slot 2 while merging with bl message in same flit unc_m3upi_rxc_crd_misc.any_bgf_fifo uncore interconnect Miscellaneous Credit Events : Any In BGF FIFO event=0x5f,umask=1  01    Miscellaneous Credit Events : Any In BGF FIFO : Indication that at least one packet (flit) is in the bgf (fifo only) unc_m3upi_rxc_crd_misc.any_bgf_path uncore interconnect Miscellaneous Credit Events : Any in BGF Path event=0x5f,umask=2  01    Miscellaneous Credit Events : Any in BGF Path : Indication that at least one packet (flit) is in the bgf path (i.e. pipe to fifo) unc_m3upi_rxc_crd_misc.lt1_for_d2k uncore interconnect Miscellaneous Credit Events event=0x5f,umask=0x10  01    Miscellaneous Credit Events : d2k credit count is less than 1 unc_m3upi_rxc_crd_misc.lt2_for_d2k uncore interconnect Miscellaneous Credit Events event=0x5f,umask=0x20  01    Miscellaneous Credit Events : d2k credit count is less than 2 unc_m3upi_rxc_crd_misc.vn0_no_d2k_for_arb uncore interconnect Miscellaneous Credit Events : No D2K For Arb event=0x5f,umask=4  01    Miscellaneous Credit Events : No D2K For Arb : VN0 BL RSP message was blocked from arbitration request due to lack of D2K CMP credit unc_m3upi_rxc_crd_misc.vn1_no_d2k_for_arb uncore interconnect Miscellaneous Credit Events event=0x5f,umask=8  01    Miscellaneous Credit Events : VN1 BL RSP message was blocked from arbitration request due to lack of D2K CMP credits unc_m3upi_rxc_crd_occ.consumed uncore interconnect Credit Occupancy : Credits Consumed event=0x60,umask=0x80  01    Credit Occupancy : Credits Consumed : number of remote vna credits consumed per cycle unc_m3upi_rxc_crd_occ.d2k_crd uncore interconnect Credit Occupancy : D2K Credits event=0x60,umask=0x10  01    Credit Occupancy : D2K Credits : D2K completion fifo credit occupancy (credits in use), accumulated across all cycles unc_m3upi_rxc_crd_occ.flits_in_fifo uncore interconnect Credit Occupancy : Packets in BGF FIFO event=0x60,umask=2  01    Credit Occupancy : Packets in BGF FIFO : Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in fifo unc_m3upi_rxc_crd_occ.flits_in_path uncore interconnect Credit Occupancy : Packets in BGF Path event=0x60,umask=4  01    Credit Occupancy : Packets in BGF Path : Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in path (i.e. pipe to fifo or fifo) unc_m3upi_rxc_crd_occ.p1p_fifo uncore interconnect Credit Occupancy event=0x60,umask=0x40  01    Credit Occupancy : count of bl messages in pump-1-pending state, in completion fifo only unc_m3upi_rxc_crd_occ.p1p_total uncore interconnect Credit Occupancy event=0x60,umask=0x20  01    Credit Occupancy : count of bl messages in pump-1-pending state, in marker table and in fifo unc_m3upi_rxc_crd_occ.txq_crd uncore interconnect Credit Occupancy : Transmit Credits event=0x60,umask=8  01    Credit Occupancy : Transmit Credits : Link layer transmit queue credit occupancy (credits in use), accumulated across all cycles unc_m3upi_rxc_crd_occ.vna_in_use uncore interconnect Credit Occupancy : VNA In Use event=0x60,umask=1  01    Credit Occupancy : VNA In Use : Remote UPI VNA credit occupancy (number of credits in use), accumulated across all cycles unc_m3upi_rxc_cycles_ne_vn0.ad_req uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD event=0x43,umask=1  01    VN0 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD : Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_cycles_ne_vn0.ad_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD event=0x43,umask=4  01    VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD : Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_cycles_ne_vn0.ad_snp uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD event=0x43,umask=2  01    VN0 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD : Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_rxc_cycles_ne_vn0.bl_ncb uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL event=0x43,umask=0x20  01    VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL : Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_rxc_cycles_ne_vn0.bl_ncs uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL event=0x43,umask=0x40  01    VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL : Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_cycles_ne_vn0.bl_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL event=0x43,umask=8  01    VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL : Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_cycles_ne_vn0.bl_wb uncore interconnect VN0 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL event=0x43,umask=0x10  01    VN0 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL : Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_data_flits_not_sent.all uncore interconnect Data Flit Not Sent : All event=0x55,umask=1  01    Data Flit Not Sent : All : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but could not be sent for any reason, e.g. low credits, low tsv, stall injection unc_m3upi_rxc_data_flits_not_sent.no_bgf uncore interconnect Data Flit Not Sent : No BGF Credits event=0x55,umask=8  01    Data Flit Not Sent : No BGF Credits : Data flit is ready for transmission but could not be sent unc_m3upi_rxc_data_flits_not_sent.no_txq uncore interconnect Data Flit Not Sent : No TxQ Credits event=0x55,umask=0x10  01    Data Flit Not Sent : No TxQ Credits : Data flit is ready for transmission but could not be sent unc_m3upi_rxc_data_flits_not_sent.tsv_hi uncore interconnect Data Flit Not Sent : TSV High event=0x55,umask=2  01    Data Flit Not Sent : TSV High : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but was not sent while tsv high unc_m3upi_rxc_data_flits_not_sent.valid_for_flit uncore interconnect Data Flit Not Sent : Cycle valid for Flit event=0x55,umask=4  01    Data Flit Not Sent : Cycle valid for Flit : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but was not sent while cycle is valid for flit transmission unc_m3upi_rxc_flits_gen_bl.p0_wait uncore interconnect Generating BL Data Flit Sequence : Wait on Pump 0 event=0x57,umask=1  01    Generating BL Data Flit Sequence : Wait on Pump 0 : generating bl data flit sequence; waiting for data pump 0 unc_m3upi_rxc_flits_gen_bl.p1p_at_limit uncore interconnect Generating BL Data Flit Sequence event=0x57,umask=0x10  01    Generating BL Data Flit Sequence : pump-1-pending logic is at capacity (pending table plus completion fifo at limit) unc_m3upi_rxc_flits_gen_bl.p1p_busy uncore interconnect Generating BL Data Flit Sequence event=0x57,umask=8  01    Generating BL Data Flit Sequence : pump-1-pending logic is tracking at least one message unc_m3upi_rxc_flits_gen_bl.p1p_fifo_full uncore interconnect Generating BL Data Flit Sequence event=0x57,umask=0x40  01    Generating BL Data Flit Sequence : pump-1-pending completion fifo is full unc_m3upi_rxc_flits_gen_bl.p1p_hold_p0 uncore interconnect Generating BL Data Flit Sequence event=0x57,umask=0x20  01    Generating BL Data Flit Sequence : pump-1-pending logic is at or near capacity, such that pump-0-only bl messages are getting stalled in slotting stage unc_m3upi_rxc_flits_gen_bl.p1p_to_limbo uncore interconnect Generating BL Data Flit Sequence event=0x57,umask=4  01    Generating BL Data Flit Sequence : a bl message finished but is in limbo and moved to pump-1-pending logic unc_m3upi_rxc_flits_gen_bl.p1_wait uncore interconnect Generating BL Data Flit Sequence : Wait on Pump 1 event=0x57,umask=2  01    Generating BL Data Flit Sequence : Wait on Pump 1 : generating bl data flit sequence; waiting for data pump 1 unc_m3upi_rxc_flits_misc.s2req_in_holdoff uncore interconnect UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF event=0x58,umask=4  01    : slot 2 request naturally serviced during hold-off period unc_m3upi_rxc_flits_misc.s2req_in_service uncore interconnect UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE event=0x58,umask=8  01    : slot 2 request forcibly serviced during service window unc_m3upi_rxc_flits_misc.s2req_received uncore interconnect UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED event=0x58,umask=1  01    : slot 2 request received from link layer while idle (with no slot 2 request active immediately prior) unc_m3upi_rxc_flits_misc.s2req_withdrawn uncore interconnect UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN event=0x58,umask=2  01    : slot 2 request withdrawn during hold-off period or service window unc_m3upi_rxc_flits_slot_bl.all uncore interconnect Slotting BL Message Into Header Flit : All event=0x56,umask=1  01     unc_m3upi_rxc_flits_slot_bl.need_data uncore interconnect Slotting BL Message Into Header Flit : Needs Data Flit event=0x56,umask=2  01    Slotting BL Message Into Header Flit : Needs Data Flit : BL message requires data flit sequence unc_m3upi_rxc_flits_slot_bl.p0_wait uncore interconnect Slotting BL Message Into Header Flit : Wait on Pump 0 event=0x56,umask=4  01    Slotting BL Message Into Header Flit : Wait on Pump 0 : Waiting for header pump 0 unc_m3upi_rxc_flits_slot_bl.p1_not_req uncore interconnect Slotting BL Message Into Header Flit : Don't Need Pump 1 event=0x56,umask=0x10  01    Slotting BL Message Into Header Flit : Don't Need Pump 1 : Header pump 1 is not required for flit unc_m3upi_rxc_flits_slot_bl.p1_not_req_but_bubble uncore interconnect Slotting BL Message Into Header Flit : Don't Need Pump 1 - Bubble event=0x56,umask=0x20  01    Slotting BL Message Into Header Flit : Don't Need Pump 1 - Bubble : Header pump 1 is not required for flit but flit transmission delayed unc_m3upi_rxc_flits_slot_bl.p1_not_req_not_avail uncore interconnect Slotting BL Message Into Header Flit : Don't Need Pump 1 - Not Avail event=0x56,umask=0x40  01    Slotting BL Message Into Header Flit : Don't Need Pump 1 - Not Avail : Header pump 1 is not required for flit and not available unc_m3upi_rxc_flits_slot_bl.p1_wait uncore interconnect Slotting BL Message Into Header Flit : Wait on Pump 1 event=0x56,umask=8  01    Slotting BL Message Into Header Flit : Wait on Pump 1 : Waiting for header pump 1 unc_m3upi_rxc_flit_gen_hdr1.accum uncore interconnect Flit Gen - Header 1 : Accumulate event=0x51,umask=1  01    Flit Gen - Header 1 : Accumulate : Events related to Header Flit Generation - Set 1 : Header flit slotting control state machine is in any accumulate state; multi-message flit may be assembled over multiple cycles unc_m3upi_rxc_flit_gen_hdr1.accum_read uncore interconnect Flit Gen - Header 1 : Accumulate Ready event=0x51,umask=2  01    Flit Gen - Header 1 : Accumulate Ready : Events related to Header Flit Generation - Set 1 : header flit slotting control state machine is in accum_ready state; flit is ready to send but transmission is blocked; more messages may be slotted into flit unc_m3upi_rxc_flit_gen_hdr1.accum_wasted uncore interconnect Flit Gen - Header 1 : Accumulate Wasted event=0x51,umask=4  01    Flit Gen - Header 1 : Accumulate Wasted : Events related to Header Flit Generation - Set 1 : Flit is being assembled over multiple cycles, but no additional message is being slotted into flit in current cycle; accumulate cycle is wasted unc_m3upi_rxc_flit_gen_hdr1.ahead_blocked uncore interconnect Flit Gen - Header 1 : Run-Ahead - Blocked event=0x51,umask=8  01    Flit Gen - Header 1 : Run-Ahead - Blocked : Events related to Header Flit Generation - Set 1 : Header flit slotting entered run-ahead state; new header flit is started while transmission of prior, fully assembled flit is blocked unc_m3upi_rxc_flit_gen_hdr1.ahead_msg1_after uncore interconnect Flit Gen - Header 1 event=0x51,umask=0x80  01    Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: message was slotted only after run-ahead was over; run-ahead mode definitely wasted unc_m3upi_rxc_flit_gen_hdr1.ahead_msg1_during uncore interconnect Flit Gen - Header 1 : Run-Ahead - Message event=0x51,umask=0x10  01    Flit Gen - Header 1 : Run-Ahead - Message : Events related to Header Flit Generation - Set 1 : run-ahead mode: one message slotted during run-ahead unc_m3upi_rxc_flit_gen_hdr1.ahead_msg2_after uncore interconnect Flit Gen - Header 1 event=0x51,umask=0x20  01    Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: second message slotted immediately after run-ahead; potential run-ahead success unc_m3upi_rxc_flit_gen_hdr1.ahead_msg2_sent uncore interconnect Flit Gen - Header 1 event=0x51,umask=0x40  01    Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: two (or three) message flit sent immediately after run-ahead; complete run-ahead success unc_m3upi_rxc_flit_gen_hdr2.par uncore interconnect Flit Gen - Header 2 : Parallel Ok event=0x52,umask=4  01    Flit Gen - Header 2 : Parallel Ok : Events related to Header Flit Generation - Set 2 : new header flit construction may proceed in parallel with data flit sequence unc_m3upi_rxc_flit_gen_hdr2.par_flit uncore interconnect Flit Gen - Header 2 : Parallel Flit Finished event=0x52,umask=0x10  01    Flit Gen - Header 2 : Parallel Flit Finished : Events related to Header Flit Generation - Set 2 : header flit finished assembly in parallel with data flit sequence unc_m3upi_rxc_flit_gen_hdr2.par_msg uncore interconnect Flit Gen - Header 2 : Parallel Message event=0x52,umask=8  01    Flit Gen - Header 2 : Parallel Message : Events related to Header Flit Generation - Set 2 : message is slotted into header flit in parallel with data flit sequence unc_m3upi_rxc_flit_gen_hdr2.rmstall uncore interconnect Flit Gen - Header 2 : Rate-matching Stall event=0x52,umask=1  01    Flit Gen - Header 2 : Rate-matching Stall : Events related to Header Flit Generation - Set 2 : Rate-matching stall injected unc_m3upi_rxc_flit_gen_hdr2.rmstall_nomsg uncore interconnect Flit Gen - Header 2 : Rate-matching Stall - No Message event=0x52,umask=2  01    Flit Gen - Header 2 : Rate-matching Stall - No Message : Events related to Header Flit Generation - Set 2 : Rate matching stall injected, but no additional message slotted during stall cycle unc_m3upi_rxc_hdr_flits_sent.1_msg uncore interconnect Sent Header Flit : One Message event=0x54,umask=1  01    Sent Header Flit : One Message : One message in flit; VNA or non-VNA flit unc_m3upi_rxc_hdr_flits_sent.1_msg_vnx uncore interconnect Sent Header Flit : One Message in non-VNA event=0x54,umask=8  01    Sent Header Flit : One Message in non-VNA : One message in flit; non-VNA flit unc_m3upi_rxc_hdr_flits_sent.2_msgs uncore interconnect Sent Header Flit : Two Messages event=0x54,umask=2  01    Sent Header Flit : Two Messages : Two messages in flit; VNA flit unc_m3upi_rxc_hdr_flits_sent.3_msgs uncore interconnect Sent Header Flit : Three Messages event=0x54,umask=4  01    Sent Header Flit : Three Messages : Three messages in flit; VNA flit unc_m3upi_rxc_hdr_flits_sent.slots_1 uncore interconnect Sent Header Flit : One Slot Taken event=0x54,umask=0x10  01     unc_m3upi_rxc_hdr_flits_sent.slots_2 uncore interconnect Sent Header Flit : Two Slots Taken event=0x54,umask=0x20  01     unc_m3upi_rxc_hdr_flits_sent.slots_3 uncore interconnect Sent Header Flit : All Slots Taken event=0x54,umask=0x40  01     unc_m3upi_rxc_hdr_flit_not_sent.all uncore interconnect Header Not Sent : All event=0x53,umask=1  01    Header Not Sent : All : header flit is ready for transmission but could not be sent : header flit is ready for transmission but could not be sent for any reason, e.g. no credits, low tsv, stall injection unc_m3upi_rxc_hdr_flit_not_sent.no_bgf_crd uncore interconnect Header Not Sent : No BGF Credits event=0x53,umask=8  01    Header Not Sent : No BGF Credits : header flit is ready for transmission but could not be sent : No BGF credits available unc_m3upi_rxc_hdr_flit_not_sent.no_bgf_no_msg uncore interconnect Header Not Sent : No BGF Credits + No Extra Message Slotted event=0x53,umask=0x20  01    Header Not Sent : No BGF Credits + No Extra Message Slotted : header flit is ready for transmission but could not be sent : No BGF credits available; no additional message slotted into flit unc_m3upi_rxc_hdr_flit_not_sent.no_txq_crd uncore interconnect Header Not Sent : No TxQ Credits event=0x53,umask=0x10  01    Header Not Sent : No TxQ Credits : header flit is ready for transmission but could not be sent : No TxQ credits available unc_m3upi_rxc_hdr_flit_not_sent.no_txq_no_msg uncore interconnect Header Not Sent : No TxQ Credits + No Extra Message Slotted event=0x53,umask=0x40  01    Header Not Sent : No TxQ Credits + No Extra Message Slotted : header flit is ready for transmission but could not be sent : No TxQ credits available; no additional message slotted into flit unc_m3upi_rxc_hdr_flit_not_sent.tsv_hi uncore interconnect Header Not Sent : TSV High event=0x53,umask=2  01    Header Not Sent : TSV High : header flit is ready for transmission but could not be sent : header flit is ready for transmission but was not sent while tsv high unc_m3upi_rxc_hdr_flit_not_sent.valid_for_flit uncore interconnect Header Not Sent : Cycle valid for Flit event=0x53,umask=4  01    Header Not Sent : Cycle valid for Flit : header flit is ready for transmission but could not be sent : header flit is ready for transmission but was not sent while cycle is valid for flit transmission unc_m3upi_rxc_held.cant_slot_ad uncore interconnect Message Held : Can't Slot AD event=0x50,umask=0x10  01    Message Held : Can't Slot AD : some AD message could not be slotted (logical OR of all AD events under INGR_SLOT_CANT_MC_VN{0,1}) unc_m3upi_rxc_held.cant_slot_bl uncore interconnect Message Held : Can't Slot BL event=0x50,umask=0x20  01    Message Held : Can't Slot BL : some BL message could not be slotted (logical OR of all BL events under INGR_SLOT_CANT_MC_VN{0,1}) unc_m3upi_rxc_held.parallel_attempt uncore interconnect Message Held : Parallel Attempt event=0x50,umask=4  01    Message Held : Parallel Attempt : ad and bl messages attempted to slot into the same flit in parallel unc_m3upi_rxc_held.parallel_success uncore interconnect Message Held : Parallel Success event=0x50,umask=8  01    Message Held : Parallel Success : ad and bl messages were actually slotted into the same flit in parallel unc_m3upi_rxc_held.vn0 uncore interconnect Message Held : VN0 event=0x50,umask=1  01    Message Held : VN0 : vn0 message(s) that couldn't be slotted into last vn0 flit are held in slotting stage while processing vn1 flit unc_m3upi_rxc_held.vn1 uncore interconnect Message Held : VN1 event=0x50,umask=2  01    Message Held : VN1 : vn1 message(s) that couldn't be slotted into last vn1 flit are held in slotting stage while processing vn0 flit unc_m3upi_rxc_packing_miss_vn0.ad_req uncore interconnect VN0 message can't slot into flit : REQ on AD event=0x4e,umask=1  01    VN0 message can't slot into flit : REQ on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_packing_miss_vn0.ad_rsp uncore interconnect VN0 message can't slot into flit : RSP on AD event=0x4e,umask=4  01    VN0 message can't slot into flit : RSP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_packing_miss_vn0.ad_snp uncore interconnect VN0 message can't slot into flit : SNP on AD event=0x4e,umask=2  01    VN0 message can't slot into flit : SNP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_rxc_packing_miss_vn0.bl_ncb uncore interconnect VN0 message can't slot into flit : NCB on BL event=0x4e,umask=0x20  01    VN0 message can't slot into flit : NCB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_rxc_packing_miss_vn0.bl_ncs uncore interconnect VN0 message can't slot into flit : NCS on BL event=0x4e,umask=0x40  01    VN0 message can't slot into flit : NCS on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_packing_miss_vn0.bl_rsp uncore interconnect VN0 message can't slot into flit : RSP on BL event=0x4e,umask=8  01    VN0 message can't slot into flit : RSP on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_packing_miss_vn0.bl_wb uncore interconnect VN0 message can't slot into flit : WB on BL event=0x4e,umask=0x10  01    VN0 message can't slot into flit : WB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_packing_miss_vn1.ad_req uncore interconnect VN1 message can't slot into flit : REQ on AD event=0x4f,umask=1  01    VN1 message can't slot into flit : REQ on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_packing_miss_vn1.ad_rsp uncore interconnect VN1 message can't slot into flit : RSP on AD event=0x4f,umask=4  01    VN1 message can't slot into flit : RSP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_packing_miss_vn1.ad_snp uncore interconnect VN1 message can't slot into flit : SNP on AD event=0x4f,umask=2  01    VN1 message can't slot into flit : SNP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_rxc_packing_miss_vn1.bl_ncb uncore interconnect VN1 message can't slot into flit : NCB on BL event=0x4f,umask=0x20  01    VN1 message can't slot into flit : NCB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_rxc_packing_miss_vn1.bl_ncs uncore interconnect VN1 message can't slot into flit : NCS on BL event=0x4f,umask=0x40  01    VN1 message can't slot into flit : NCS on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_packing_miss_vn1.bl_rsp uncore interconnect VN1 message can't slot into flit : RSP on BL event=0x4f,umask=8  01    VN1 message can't slot into flit : RSP on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_packing_miss_vn1.bl_wb uncore interconnect VN1 message can't slot into flit : WB on BL event=0x4f,umask=0x10  01    VN1 message can't slot into flit : WB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_vna_crd.any_in_use uncore interconnect Remote VNA Credits : Any In Use event=0x5a,umask=0x20  01    Remote VNA Credits : Any In Use : At least one remote vna credit is in use unc_m3upi_rxc_vna_crd.corrected uncore interconnect Remote VNA Credits : Corrected event=0x5a,umask=1  01    Remote VNA Credits : Corrected : Number of remote vna credits corrected (local return) per cycle unc_m3upi_rxc_vna_crd.lt1 uncore interconnect Remote VNA Credits : Level < 1 event=0x5a,umask=2  01    Remote VNA Credits : Level < 1 : Remote vna credit level is less than 1 (i.e. no vna credits available) unc_m3upi_rxc_vna_crd.lt10 uncore interconnect Remote VNA Credits : Level < 10 event=0x5a,umask=0x10  01    Remote VNA Credits : Level < 10 : remote vna credit level is less than 10; parallel vn0/vn1 arb not possible unc_m3upi_rxc_vna_crd.lt4 uncore interconnect Remote VNA Credits : Level < 4 event=0x5a,umask=4  01    Remote VNA Credits : Level < 4 : Remote vna credit level is less than 4; bl (or ad requiring 4 vna) cannot arb on vna unc_m3upi_rxc_vna_crd.lt5 uncore interconnect Remote VNA Credits : Level < 5 event=0x5a,umask=8  01    Remote VNA Credits : Level < 5 : Remote vna credit level is less than 5; parallel ad/bl arb on vna not possible unc_m3upi_rxc_vna_crd_misc.req_adbl_alloc_l5 uncore interconnect UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5 event=0x59,umask=2  01    : remote vna credit count was less than 5 and allocation to ad or bl messages was required unc_m3upi_rxc_vna_crd_misc.req_vn01_alloc_lt10 uncore interconnect UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10 event=0x59,umask=1  01    : remote vna credit count was less than 10 and allocation to vn0 or vn1 was required unc_m3upi_rxc_vna_crd_misc.vn0_just_ad uncore interconnect UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD event=0x59,umask=0x10  01    : on vn0, remote vna credits were allocated only to ad messages, not to bl unc_m3upi_rxc_vna_crd_misc.vn0_just_bl uncore interconnect UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL event=0x59,umask=0x20  01    : on vn0, remote vna credits were allocated only to bl messages, not to ad unc_m3upi_rxc_vna_crd_misc.vn0_only uncore interconnect UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY event=0x59,umask=4  01    : remote vna credits were allocated only to vn0, not to vn1 unc_m3upi_rxc_vna_crd_misc.vn1_just_ad uncore interconnect UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD event=0x59,umask=0x40  01    : on vn1, remote vna credits were allocated only to ad messages, not to bl unc_m3upi_rxc_vna_crd_misc.vn1_just_bl uncore interconnect UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL event=0x59,umask=0x80  01    : on vn1, remote vna credits were allocated only to bl messages, not to ad unc_m3upi_rxc_vna_crd_misc.vn1_only uncore interconnect UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY event=0x59,umask=8  01    : remote vna credits were allocated only to vn1, not to vn0 unc_m3upi_txc_ad_arb_fail.vn0_req uncore interconnect Failed ARB for AD : VN0 REQ Messages event=0x30,umask=1  01    Failed ARB for AD : VN0 REQ Messages : AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn0_rsp uncore interconnect Failed ARB for AD : VN0 RSP Messages event=0x30,umask=4  01    Failed ARB for AD : VN0 RSP Messages : AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn0_snp uncore interconnect Failed ARB for AD : VN0 SNP Messages event=0x30,umask=2  01    Failed ARB for AD : VN0 SNP Messages : AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn0_wb uncore interconnect Failed ARB for AD : VN0 WB Messages event=0x30,umask=8  01    Failed ARB for AD : VN0 WB Messages : AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn1_req uncore interconnect Failed ARB for AD : VN1 REQ Messages event=0x30,umask=0x10  01    Failed ARB for AD : VN1 REQ Messages : AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn1_rsp uncore interconnect Failed ARB for AD : VN1 RSP Messages event=0x30,umask=0x40  01    Failed ARB for AD : VN1 RSP Messages : AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn1_snp uncore interconnect Failed ARB for AD : VN1 SNP Messages event=0x30,umask=0x20  01    Failed ARB for AD : VN1 SNP Messages : AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_arb_fail.vn1_wb uncore interconnect Failed ARB for AD : VN1 WB Messages event=0x30,umask=0x80  01    Failed ARB for AD : VN1 WB Messages : AD arb but no win; arb request asserted but not won unc_m3upi_txc_ad_flq_bypass uncore interconnect AD FlowQ Bypass event=0x2c  01    Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least) unc_m3upi_txc_ad_flq_bypass.ad_slot0 uncore interconnect AD FlowQ Bypass event=0x2c,umask=1  01    AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least) unc_m3upi_txc_ad_flq_bypass.ad_slot1 uncore interconnect AD FlowQ Bypass event=0x2c,umask=2  01    AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least) unc_m3upi_txc_ad_flq_bypass.ad_slot2 uncore interconnect AD FlowQ Bypass event=0x2c,umask=4  01    AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least) unc_m3upi_txc_ad_flq_bypass.bl_early_rsp uncore interconnect AD FlowQ Bypass event=0x2c,umask=8  01    AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least) unc_m3upi_txc_ad_flq_cycles_ne.vn0_req uncore interconnect AD Flow Q Not Empty : VN0 REQ Messages event=0x27,umask=1  01    AD Flow Q Not Empty : VN0 REQ Messages : Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn0_rsp uncore interconnect AD Flow Q Not Empty : VN0 RSP Messages event=0x27,umask=4  01    AD Flow Q Not Empty : VN0 RSP Messages : Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn0_snp uncore interconnect AD Flow Q Not Empty : VN0 SNP Messages event=0x27,umask=2  01    AD Flow Q Not Empty : VN0 SNP Messages : Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn0_wb uncore interconnect AD Flow Q Not Empty : VN0 WB Messages event=0x27,umask=8  01    AD Flow Q Not Empty : VN0 WB Messages : Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn1_req uncore interconnect AD Flow Q Not Empty : VN1 REQ Messages event=0x27,umask=0x10  01    AD Flow Q Not Empty : VN1 REQ Messages : Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn1_rsp uncore interconnect AD Flow Q Not Empty : VN1 RSP Messages event=0x27,umask=0x40  01    AD Flow Q Not Empty : VN1 RSP Messages : Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn1_snp uncore interconnect AD Flow Q Not Empty : VN1 SNP Messages event=0x27,umask=0x20  01    AD Flow Q Not Empty : VN1 SNP Messages : Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_cycles_ne.vn1_wb uncore interconnect AD Flow Q Not Empty : VN1 WB Messages event=0x27,umask=0x80  01    AD Flow Q Not Empty : VN1 WB Messages : Number of cycles the AD Egress queue is Not Empty unc_m3upi_txc_ad_flq_inserts.vn0_req uncore interconnect AD Flow Q Inserts : VN0 REQ Messages event=0x2d,umask=1  01    AD Flow Q Inserts : VN0 REQ Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn0_rsp uncore interconnect AD Flow Q Inserts : VN0 RSP Messages event=0x2d,umask=4  01    AD Flow Q Inserts : VN0 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn0_snp uncore interconnect AD Flow Q Inserts : VN0 SNP Messages event=0x2d,umask=2  01    AD Flow Q Inserts : VN0 SNP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn0_wb uncore interconnect AD Flow Q Inserts : VN0 WB Messages event=0x2d,umask=8  01    AD Flow Q Inserts : VN0 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn1_req uncore interconnect AD Flow Q Inserts : VN1 REQ Messages event=0x2d,umask=0x10  01    AD Flow Q Inserts : VN1 REQ Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn1_rsp uncore interconnect AD Flow Q Inserts : VN1 RSP Messages event=0x2d,umask=0x40  01    AD Flow Q Inserts : VN1 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_inserts.vn1_snp uncore interconnect AD Flow Q Inserts : VN1 SNP Messages event=0x2d,umask=0x20  01    AD Flow Q Inserts : VN1 SNP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_m3upi_txc_ad_flq_occupancy.vn0_req uncore interconnect AD Flow Q Occupancy : VN0 REQ Messages event=0x1c,umask=1  01     unc_m3upi_txc_ad_flq_occupancy.vn0_rsp uncore interconnect AD Flow Q Occupancy : VN0 RSP Messages event=0x1c,umask=4  01     unc_m3upi_txc_ad_flq_occupancy.vn0_snp uncore interconnect AD Flow Q Occupancy : VN0 SNP Messages event=0x1c,umask=2  01     unc_m3upi_txc_ad_flq_occupancy.vn0_wb uncore interconnect AD Flow Q Occupancy : VN0 WB Messages event=0x1c,umask=8  01     unc_m3upi_txc_ad_flq_occupancy.vn1_req uncore interconnect AD Flow Q Occupancy : VN1 REQ Messages event=0x1c,umask=0x10  01     unc_m3upi_txc_ad_flq_occupancy.vn1_rsp uncore interconnect AD Flow Q Occupancy : VN1 RSP Messages event=0x1c,umask=0x40  01     unc_m3upi_txc_ad_flq_occupancy.vn1_snp uncore interconnect AD Flow Q Occupancy : VN1 SNP Messages event=0x1c,umask=0x20  01     unc_m3upi_txc_bl_arb_fail.vn0_ncb uncore interconnect Failed ARB for BL : VN0 NCB Messages event=0x35,umask=4  01    Failed ARB for BL : VN0 NCB Messages : BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn0_ncs uncore interconnect Failed ARB for BL : VN0 NCS Messages event=0x35,umask=8  01    Failed ARB for BL : VN0 NCS Messages : BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn0_rsp uncore interconnect Failed ARB for BL : VN0 RSP Messages event=0x35,umask=1  01    Failed ARB for BL : VN0 RSP Messages : BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn0_wb uncore interconnect Failed ARB for BL : VN0 WB Messages event=0x35,umask=2  01    Failed ARB for BL : VN0 WB Messages : BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn1_ncb uncore interconnect Failed ARB for BL : VN1 NCS Messages event=0x35,umask=0x40  01    Failed ARB for BL : VN1 NCS Messages : BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn1_ncs uncore interconnect Failed ARB for BL : VN1 NCB Messages event=0x35,umask=0x80  01    Failed ARB for BL : VN1 NCB Messages : BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn1_rsp uncore interconnect Failed ARB for BL : VN1 RSP Messages event=0x35,umask=0x10  01    Failed ARB for BL : VN1 RSP Messages : BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_arb_fail.vn1_wb uncore interconnect Failed ARB for BL : VN1 WB Messages event=0x35,umask=0x20  01    Failed ARB for BL : VN1 WB Messages : BL arb but no win; arb request asserted but not won unc_m3upi_txc_bl_flq_cycles_ne.vn0_req uncore interconnect BL Flow Q Not Empty : VN0 REQ Messages event=0x28,umask=1  01    BL Flow Q Not Empty : VN0 REQ Messages : Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn0_rsp uncore interconnect BL Flow Q Not Empty : VN0 RSP Messages event=0x28,umask=4  01    BL Flow Q Not Empty : VN0 RSP Messages : Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn0_snp uncore interconnect BL Flow Q Not Empty : VN0 SNP Messages event=0x28,umask=2  01    BL Flow Q Not Empty : VN0 SNP Messages : Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn0_wb uncore interconnect BL Flow Q Not Empty : VN0 WB Messages event=0x28,umask=8  01    BL Flow Q Not Empty : VN0 WB Messages : Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn1_req uncore interconnect BL Flow Q Not Empty : VN1 REQ Messages event=0x28,umask=0x10  01    BL Flow Q Not Empty : VN1 REQ Messages : Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn1_rsp uncore interconnect BL Flow Q Not Empty : VN1 RSP Messages event=0x28,umask=0x40  01    BL Flow Q Not Empty : VN1 RSP Messages : Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn1_snp uncore interconnect BL Flow Q Not Empty : VN1 SNP Messages event=0x28,umask=0x20  01    BL Flow Q Not Empty : VN1 SNP Messages : Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_cycles_ne.vn1_wb uncore interconnect BL Flow Q Not Empty : VN1 WB Messages event=0x28,umask=0x80  01    BL Flow Q Not Empty : VN1 WB Messages : Number of cycles the BL Egress queue is Not Empty unc_m3upi_txc_bl_flq_inserts.vn0_ncb uncore interconnect BL Flow Q Inserts : VN0 RSP Messages event=0x2e,umask=1  01    BL Flow Q Inserts : VN0 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn0_ncs uncore interconnect BL Flow Q Inserts : VN0 WB Messages event=0x2e,umask=2  01    BL Flow Q Inserts : VN0 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn0_rsp uncore interconnect BL Flow Q Inserts : VN0 NCS Messages event=0x2e,umask=8  01    BL Flow Q Inserts : VN0 NCS Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn0_wb uncore interconnect BL Flow Q Inserts : VN0 NCB Messages event=0x2e,umask=4  01    BL Flow Q Inserts : VN0 NCB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn1_ncb uncore interconnect BL Flow Q Inserts : VN1 RSP Messages event=0x2e,umask=0x10  01    BL Flow Q Inserts : VN1 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn1_ncs uncore interconnect BL Flow Q Inserts : VN1 WB Messages event=0x2e,umask=0x20  01    BL Flow Q Inserts : VN1 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn1_rsp uncore interconnect BL Flow Q Inserts : VN1_NCB Messages event=0x2e,umask=0x80  01    BL Flow Q Inserts : VN1_NCB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_inserts.vn1_wb uncore interconnect BL Flow Q Inserts : VN1_NCS Messages event=0x2e,umask=0x40  01    BL Flow Q Inserts : VN1_NCS Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_m3upi_txc_bl_flq_occupancy.vn0_ncb uncore interconnect BL Flow Q Occupancy : VN0 NCB Messages event=0x1d,umask=4  01     unc_m3upi_txc_bl_flq_occupancy.vn0_ncs uncore interconnect BL Flow Q Occupancy : VN0 NCS Messages event=0x1d,umask=8  01     unc_m3upi_txc_bl_flq_occupancy.vn0_rsp uncore interconnect BL Flow Q Occupancy : VN0 RSP Messages event=0x1d,umask=1  01     unc_m3upi_txc_bl_flq_occupancy.vn0_wb uncore interconnect BL Flow Q Occupancy : VN0 WB Messages event=0x1d,umask=2  01     unc_m3upi_txc_bl_flq_occupancy.vn1_ncb uncore interconnect BL Flow Q Occupancy : VN1_NCS Messages event=0x1d,umask=0x40  01     unc_m3upi_txc_bl_flq_occupancy.vn1_ncs uncore interconnect BL Flow Q Occupancy : VN1_NCB Messages event=0x1d,umask=0x80  01     unc_m3upi_txc_bl_flq_occupancy.vn1_rsp uncore interconnect BL Flow Q Occupancy : VN1 RSP Messages event=0x1d,umask=0x10  01     unc_m3upi_txc_bl_flq_occupancy.vn1_wb uncore interconnect BL Flow Q Occupancy : VN1 WB Messages event=0x1d,umask=0x20  01     unc_m3upi_txc_bl_wb_flq_occupancy.vn0_local uncore interconnect BL Flow Q Occupancy : VN0 RSP Messages event=0x1f,umask=1  01     unc_m3upi_txc_bl_wb_flq_occupancy.vn0_through uncore interconnect BL Flow Q Occupancy : VN0 WB Messages event=0x1f,umask=2  01     unc_m3upi_txc_bl_wb_flq_occupancy.vn0_wrpull uncore interconnect BL Flow Q Occupancy : VN0 NCB Messages event=0x1f,umask=4  01     unc_m3upi_txc_bl_wb_flq_occupancy.vn1_local uncore interconnect BL Flow Q Occupancy : VN1 RSP Messages event=0x1f,umask=0x10  01     unc_m3upi_txc_bl_wb_flq_occupancy.vn1_through uncore interconnect BL Flow Q Occupancy : VN1 WB Messages event=0x1f,umask=0x20  01     unc_m3upi_txc_bl_wb_flq_occupancy.vn1_wrpull uncore interconnect BL Flow Q Occupancy : VN1_NCS Messages event=0x1f,umask=0x40  01     unc_m3upi_upi_peer_ad_credits_empty.vn0_req uncore interconnect UPI0 AD Credits Empty : VN0 REQ Messages event=0x20,umask=2  01    UPI0 AD Credits Empty : VN0 REQ Messages : No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vn0_rsp uncore interconnect UPI0 AD Credits Empty : VN0 RSP Messages event=0x20,umask=8  01    UPI0 AD Credits Empty : VN0 RSP Messages : No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vn0_snp uncore interconnect UPI0 AD Credits Empty : VN0 SNP Messages event=0x20,umask=4  01    UPI0 AD Credits Empty : VN0 SNP Messages : No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vn1_req uncore interconnect UPI0 AD Credits Empty : VN1 REQ Messages event=0x20,umask=0x10  01    UPI0 AD Credits Empty : VN1 REQ Messages : No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vn1_rsp uncore interconnect UPI0 AD Credits Empty : VN1 RSP Messages event=0x20,umask=0x40  01    UPI0 AD Credits Empty : VN1 RSP Messages : No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vn1_snp uncore interconnect UPI0 AD Credits Empty : VN1 SNP Messages event=0x20,umask=0x20  01    UPI0 AD Credits Empty : VN1 SNP Messages : No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_ad_credits_empty.vna uncore interconnect UPI0 AD Credits Empty : VNA event=0x20,umask=1  01    UPI0 AD Credits Empty : VNA : No credits available to send to UPIs on the AD Ring unc_m3upi_upi_peer_bl_credits_empty.vn0_ncs_ncb uncore interconnect UPI0 BL Credits Empty : VN0 RSP Messages event=0x21,umask=4  01    UPI0 BL Credits Empty : VN0 RSP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vn0_rsp uncore interconnect UPI0 BL Credits Empty : VN0 REQ Messages event=0x21,umask=2  01    UPI0 BL Credits Empty : VN0 REQ Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vn0_wb uncore interconnect UPI0 BL Credits Empty : VN0 SNP Messages event=0x21,umask=8  01    UPI0 BL Credits Empty : VN0 SNP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vn1_ncs_ncb uncore interconnect UPI0 BL Credits Empty : VN1 RSP Messages event=0x21,umask=0x20  01    UPI0 BL Credits Empty : VN1 RSP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vn1_rsp uncore interconnect UPI0 BL Credits Empty : VN1 REQ Messages event=0x21,umask=0x10  01    UPI0 BL Credits Empty : VN1 REQ Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vn1_wb uncore interconnect UPI0 BL Credits Empty : VN1 SNP Messages event=0x21,umask=0x40  01    UPI0 BL Credits Empty : VN1 SNP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_peer_bl_credits_empty.vna uncore interconnect UPI0 BL Credits Empty : VNA event=0x21,umask=1  01    UPI0 BL Credits Empty : VNA : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode) unc_m3upi_upi_prefetch_spawn uncore interconnect FlowQ Generated Prefetch event=0x29  01    FlowQ Generated Prefetch : Count cases where FlowQ causes spawn of Prefetch to iMC/SMI3 target unc_m3upi_vn0_credits_used.ncb uncore interconnect VN0 Credit Used : WB on BL event=0x5b,umask=0x10  01    VN0 Credit Used : WB on BL : Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_vn0_credits_used.ncs uncore interconnect VN0 Credit Used : NCB on BL event=0x5b,umask=0x20  01    VN0 Credit Used : NCB on BL : Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_vn0_credits_used.req uncore interconnect VN0 Credit Used : REQ on AD event=0x5b,umask=1  01    VN0 Credit Used : REQ on AD : Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_vn0_credits_used.rsp uncore interconnect VN0 Credit Used : RSP on AD event=0x5b,umask=4  01    VN0 Credit Used : RSP on AD : Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn0_credits_used.snp uncore interconnect VN0 Credit Used : SNP on AD event=0x5b,umask=2  01    VN0 Credit Used : SNP on AD : Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_vn0_credits_used.wb uncore interconnect VN0 Credit Used : RSP on BL event=0x5b,umask=8  01    VN0 Credit Used : RSP on BL : Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn0_no_credits.ncb uncore interconnect VN0 No Credits : WB on BL event=0x5d,umask=0x10  01    VN0 No Credits : WB on BL : Number of Cycles there were no VN0 Credits : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_vn0_no_credits.ncs uncore interconnect VN0 No Credits : NCB on BL event=0x5d,umask=0x20  01    VN0 No Credits : NCB on BL : Number of Cycles there were no VN0 Credits : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_vn0_no_credits.req uncore interconnect VN0 No Credits : REQ on AD event=0x5d,umask=1  01    VN0 No Credits : REQ on AD : Number of Cycles there were no VN0 Credits : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_vn0_no_credits.rsp uncore interconnect VN0 No Credits : RSP on AD event=0x5d,umask=4  01    VN0 No Credits : RSP on AD : Number of Cycles there were no VN0 Credits : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn0_no_credits.snp uncore interconnect VN0 No Credits : SNP on AD event=0x5d,umask=2  01    VN0 No Credits : SNP on AD : Number of Cycles there were no VN0 Credits : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_vn0_no_credits.wb uncore interconnect VN0 No Credits : RSP on BL event=0x5d,umask=8  01    VN0 No Credits : RSP on BL : Number of Cycles there were no VN0 Credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn1_credits_used.ncb uncore interconnect VN1 Credit Used : WB on BL event=0x5c,umask=0x10  01    VN1 Credit Used : WB on BL : Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_vn1_credits_used.ncs uncore interconnect VN1 Credit Used : NCB on BL event=0x5c,umask=0x20  01    VN1 Credit Used : NCB on BL : Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_vn1_credits_used.req uncore interconnect VN1 Credit Used : REQ on AD event=0x5c,umask=1  01    VN1 Credit Used : REQ on AD : Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_vn1_credits_used.rsp uncore interconnect VN1 Credit Used : RSP on AD event=0x5c,umask=4  01    VN1 Credit Used : RSP on AD : Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn1_credits_used.snp uncore interconnect VN1 Credit Used : SNP on AD event=0x5c,umask=2  01    VN1 Credit Used : SNP on AD : Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_vn1_credits_used.wb uncore interconnect VN1 Credit Used : RSP on BL event=0x5c,umask=8  01    VN1 Credit Used : RSP on BL : Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn1_no_credits.ncb uncore interconnect VN1 No Credits : WB on BL event=0x5e,umask=0x10  01    VN1 No Credits : WB on BL : Number of Cycles there were no VN1 Credits : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_vn1_no_credits.ncs uncore interconnect VN1 No Credits : NCB on BL event=0x5e,umask=0x20  01    VN1 No Credits : NCB on BL : Number of Cycles there were no VN1 Credits : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_vn1_no_credits.req uncore interconnect VN1 No Credits : REQ on AD event=0x5e,umask=1  01    VN1 No Credits : REQ on AD : Number of Cycles there were no VN1 Credits : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_vn1_no_credits.rsp uncore interconnect VN1 No Credits : RSP on AD event=0x5e,umask=4  01    VN1 No Credits : RSP on AD : Number of Cycles there were no VN1 Credits : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_vn1_no_credits.snp uncore interconnect VN1 No Credits : SNP on AD event=0x5e,umask=2  01    VN1 No Credits : SNP on AD : Number of Cycles there were no VN1 Credits : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_vn1_no_credits.wb uncore interconnect VN1 No Credits : RSP on BL event=0x5e,umask=8  01    VN1 No Credits : RSP on BL : Number of Cycles there were no VN1 Credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_wb_occ_compare.bothnonzero_rt_eq_localdest_vn0 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN0 event=0x7e,umask=0x82  01     unc_m3upi_wb_occ_compare.bothnonzero_rt_eq_localdest_vn1 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN1 event=0x7e,umask=0xa0  01     unc_m3upi_wb_occ_compare.bothnonzero_rt_gt_localdest_vn0 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN0 event=0x7e,umask=0x81  01     unc_m3upi_wb_occ_compare.bothnonzero_rt_gt_localdest_vn1 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN1 event=0x7e,umask=0x90  01     unc_m3upi_wb_occ_compare.bothnonzero_rt_lt_localdest_vn0 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN0 event=0x7e,umask=0x84  01     unc_m3upi_wb_occ_compare.bothnonzero_rt_lt_localdest_vn1 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN1 event=0x7e,umask=0xc0  01     unc_m3upi_wb_occ_compare.rt_eq_localdest_vn0 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0 event=0x7e,umask=2  01     unc_m3upi_wb_occ_compare.rt_eq_localdest_vn1 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1 event=0x7e,umask=0x20  01     unc_m3upi_wb_occ_compare.rt_gt_localdest_vn0 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0 event=0x7e,umask=1  01     unc_m3upi_wb_occ_compare.rt_gt_localdest_vn1 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1 event=0x7e,umask=0x10  01     unc_m3upi_wb_occ_compare.rt_lt_localdest_vn0 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0 event=0x7e,umask=4  01     unc_m3upi_wb_occ_compare.rt_lt_localdest_vn1 uncore interconnect UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1 event=0x7e,umask=0x40  01     unc_m3upi_wb_pending.localdest_vn0 uncore interconnect UNC_M3UPI_WB_PENDING.LOCALDEST_VN0 event=0x7d,umask=1  01     unc_m3upi_wb_pending.localdest_vn1 uncore interconnect UNC_M3UPI_WB_PENDING.LOCALDEST_VN1 event=0x7d,umask=0x10  01     unc_m3upi_wb_pending.local_and_rt_vn0 uncore interconnect UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0 event=0x7d,umask=4  01     unc_m3upi_wb_pending.local_and_rt_vn1 uncore interconnect UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1 event=0x7d,umask=0x40  01     unc_m3upi_wb_pending.routethru_vn0 uncore interconnect UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0 event=0x7d,umask=2  01     unc_m3upi_wb_pending.routethru_vn1 uncore interconnect UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1 event=0x7d,umask=0x20  01     unc_m3upi_wb_pending.waiting4pull_vn0 uncore interconnect UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0 event=0x7d,umask=8  01     unc_m3upi_wb_pending.waiting4pull_vn1 uncore interconnect UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1 event=0x7d,umask=0x80  01     unc_m3upi_xpt_pftch.arb uncore interconnect UNC_M3UPI_XPT_PFTCH.ARB event=0x61,umask=4  01    : xpt prefetch message is making arbitration request unc_m3upi_xpt_pftch.arrived uncore interconnect UNC_M3UPI_XPT_PFTCH.ARRIVED event=0x61,umask=1  01    : xpt prefetch message arrived in ingress pipeline unc_m3upi_xpt_pftch.bypass uncore interconnect UNC_M3UPI_XPT_PFTCH.BYPASS event=0x61,umask=2  01    : xpt prefetch message took bypass path unc_m3upi_xpt_pftch.flitted uncore interconnect UNC_M3UPI_XPT_PFTCH.FLITTED event=0x61,umask=0x10  01    : xpt prefetch message was slotted into flit (non bypass) unc_m3upi_xpt_pftch.lost_arb uncore interconnect UNC_M3UPI_XPT_PFTCH.LOST_ARB event=0x61,umask=8  01    : xpt prefetch message lost arbitration unc_m3upi_xpt_pftch.lost_old uncore interconnect UNC_M3UPI_XPT_PFTCH.LOST_OLD event=0x61,umask=0x20  01    : xpt prefetch message was dropped because it became too old unc_m3upi_xpt_pftch.lost_qfull uncore interconnect UNC_M3UPI_XPT_PFTCH.LOST_QFULL event=0x61,umask=0x40  01    : xpt prefetch message was dropped because it was overwritten by new message while prefetch queue was full uncore_mdf unc_mdf_crs_txr_inserts.ad_bnc uncore interconnect Number of allocations into the CRS Egress  used to queue up requests destined to the mesh (AD Bounceable) event=0x47,umask=1  01    AD Bounceable : Number of allocations into the CRS Egress unc_mdf_crs_txr_inserts.ad_crd uncore interconnect Number of allocations into the CRS Egress  used to queue up requests destined to the mesh (AD credited) event=0x47,umask=2  01    AD credited : Number of allocations into the CRS Egress unc_mdf_crs_txr_inserts.ak uncore interconnect Number of allocations into the CRS Egress  used to queue up requests destined to the mesh (AK) event=0x47,umask=0x10  01    AK : Number of allocations into the CRS Egress unc_mdf_crs_txr_inserts.akc uncore interconnect Number of allocations into the CRS Egress  used to queue up requests destined to the mesh (AKC) event=0x47,umask=0x40  01    AKC : Number of allocations into the CRS Egress unc_mdf_crs_txr_inserts.bl_bnc uncore interconnect Number of allocations into the CRS Egress  used to queue up requests destined to the mesh (BL Bounceable) event=0x47,umask=4  01    BL Bounceable : Number of allocations into the CRS Egress unc_mdf_crs_txr_inserts.bl_crd uncore interconnect Number of allocations into the CRS Egress  used to queue up requests destined to the mesh (BL credited) event=0x47,umask=8  01    BL credited : Number of allocations into the CRS Egress unc_mdf_crs_txr_inserts.iv uncore interconnect Number of allocations into the CRS Egress  used to queue up requests destined to the mesh (IV) event=0x47,umask=0x20  01    IV : Number of allocations into the CRS Egress unc_mdf_crs_txr_v_bounces.ad uncore interconnect Number of cycles incoming messages from the vertical ring that are bounced at the SBO Ingress (V-EMIB) (AD) event=0x4b,umask=1  01    AD : Number of cycles incoming messages from the vertical ring that are bounced at the SBO unc_mdf_crs_txr_v_bounces.ak uncore interconnect Number of cycles incoming messages from the vertical ring that are bounced at the SBO Ingress (V-EMIB) (AK) event=0x4b,umask=4  01    AK : Number of cycles incoming messages from the vertical ring that are bounced at the SBO unc_mdf_crs_txr_v_bounces.akc uncore interconnect Number of cycles incoming messages from the vertical ring that are bounced at the SBO Ingress (V-EMIB) (AKC) event=0x4b,umask=0x10  01    AKC : Number of cycles incoming messages from the vertical ring that are bounced at the SBO unc_mdf_crs_txr_v_bounces.bl uncore interconnect Number of cycles incoming messages from the vertical ring that are bounced at the SBO Ingress (V-EMIB) (BL) event=0x4b,umask=2  01    BL : Number of cycles incoming messages from the vertical ring that are bounced at the SBO unc_mdf_crs_txr_v_bounces.iv uncore interconnect Number of cycles incoming messages from the vertical ring that are bounced at the SBO Ingress (V-EMIB) (IV) event=0x4b,umask=8  01    IV : Number of cycles incoming messages from the vertical ring that are bounced at the SBO unc_mdf_fast_asserted.ad_bnc uncore interconnect Counts the number of cycles when the distress signals are asserted based on SBO Ingress threshold event=0x15,umask=1  01    AD bnc : Counts the number of cycles when the  distress signals are asserted based on SBO Ingress threshold unc_mdf_fast_asserted.bl_crd uncore interconnect Counts the number of cycles when the distress signals are asserted based on SBO Ingress threshold event=0x15,umask=2  01    BL bnc : Counts the number of cycles when the  distress signals are asserted based on SBO Ingress threshold unc_upi_clockticks uncore interconnect UPI Clockticks event=1  01    Number of UPI LL clock cycles while the event is enabled unc_upi_direct_attempts.d2c uncore interconnect Direct packet attempts : D2C event=0x12,umask=1  01    Direct packet attempts : D2C : Counts the number of DRS packets that we attempted to do direct2core/direct2UPI on.  There are 4 mutually exclusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos unc_upi_direct_attempts.d2k uncore interconnect Direct packet attempts : D2K event=0x12,umask=2  01    Direct packet attempts : D2K : Counts the number of DRS packets that we attempted to do direct2core/direct2UPI on.  There are 4 mutually exclusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos unc_upi_l1_power_cycles uncore interconnect Cycles in L1 event=0x21  01    Cycles in L1 : Number of UPI qfclk cycles spent in L1 power mode.  L1 is a mode that totally shuts down a UPI link.  Use edge detect to count the number of instances when the UPI link entered L1.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode unc_upi_power_l1_nack uncore interconnect L1 Req Nack event=0x23  01    L1 Req Nack : Counts the number of times a link sends/receives a LinkReqNAck.  When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states.  This requests can either be accepted or denied.  If the Rx side replies with an Ack, the power mode will change.  If it replies with NAck, no change will take place.  This can be filtered based on Rx and Tx.  An Rx LinkReqNAck refers to receiving an NAck (meaning this agent's Tx originally requested the power change).  A Tx LinkReqNAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it) unc_upi_power_l1_req uncore interconnect L1 Req (same as L1 Ack) event=0x22  01    L1 Req (same as L1 Ack). : Counts the number of times a link sends/receives a LinkReqAck.  When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states.  This requests can either be accepted or denied.  If the Rx side replies with an Ack, the power mode will change.  If it replies with NAck, no change will take place.  This can be filtered based on Rx and Tx.  An Rx LinkReqAck refers to receiving an Ack (meaning this agent's Tx originally requested the power change).  A Tx LinkReqAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it) unc_upi_rxl0p_power_cycles uncore interconnect Cycles in L0p event=0x25  01    Cycles in L0p : Number of UPI qfclk cycles spent in L0p power mode.  L0p is a mode where we disable 1/2 of the UPI lanes, decreasing our bandwidth in order to save power.  It increases snoop and data transfer latencies and decreases overall bandwidth.  This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses.  Use edge detect to count the number of instances when the UPI link entered L0p.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another unc_upi_rxl0_power_cycles uncore interconnect Cycles in L0 event=0x24  01    Cycles in L0 : Number of UPI qfclk cycles spent in L0 power mode in the Link Layer.  L0 is the default mode which provides the highest performance with the most power.  Use edge detect to count the number of instances that the link entered L0.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.  The phy layer  sometimes leaves L0 for training, which will not be captured by this event unc_upi_rxl_any_flits.data uncore interconnect UNC_UPI_RxL_ANY_FLITS.DATA event=0x4b,umask=8  01     unc_upi_rxl_any_flits.llcrd uncore interconnect UNC_UPI_RxL_ANY_FLITS.LLCRD event=0x4b,umask=0x10  01     unc_upi_rxl_any_flits.llctrl uncore interconnect UNC_UPI_RxL_ANY_FLITS.LLCTRL event=0x4b,umask=0x40  01     unc_upi_rxl_any_flits.null uncore interconnect UNC_UPI_RxL_ANY_FLITS.NULL event=0x4b,umask=0x20  01     unc_upi_rxl_any_flits.prothdr uncore interconnect UNC_UPI_RxL_ANY_FLITS.PROTHDR event=0x4b,umask=0x80  01     unc_upi_rxl_any_flits.slot0 uncore interconnect UNC_UPI_RxL_ANY_FLITS.SLOT0 event=0x4b,umask=1  01     unc_upi_rxl_any_flits.slot1 uncore interconnect UNC_UPI_RxL_ANY_FLITS.SLOT1 event=0x4b,umask=2  01     unc_upi_rxl_any_flits.slot2 uncore interconnect UNC_UPI_RxL_ANY_FLITS.SLOT2 event=0x4b,umask=4  01     unc_upi_rxl_basic_hdr_match.ncb uncore interconnect Matches on Receive path of a UPI Port : Non-Coherent Bypass event=5,umask=0xe  01    Matches on Receive path of a UPI Port : Non-Coherent Bypass : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.ncb_opc uncore interconnect Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode event=5,umask=0x10e  01    Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.ncs uncore interconnect Matches on Receive path of a UPI Port : Non-Coherent Standard event=5,umask=0xf  01    Matches on Receive path of a UPI Port : Non-Coherent Standard : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.ncs_opc uncore interconnect Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode event=5,umask=0x10f  01    Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_bypassed.slot0 uncore interconnect RxQ Flit Buffer Bypassed : Slot 0 event=0x31,umask=1  01    RxQ Flit Buffer Bypassed : Slot 0 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency unc_upi_rxl_bypassed.slot1 uncore interconnect RxQ Flit Buffer Bypassed : Slot 1 event=0x31,umask=2  01    RxQ Flit Buffer Bypassed : Slot 1 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency unc_upi_rxl_bypassed.slot2 uncore interconnect RxQ Flit Buffer Bypassed : Slot 2 event=0x31,umask=4  01    RxQ Flit Buffer Bypassed : Slot 2 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency unc_upi_rxl_crc_errors uncore interconnect CRC Errors Detected event=0xb  01    CRC Errors Detected : Number of CRC errors detected in the UPI Agent.  Each UPI flit incorporates 8 bits of CRC for error detection.  This counts the number of flits where the CRC was able to detect an error.  After an error has been detected, the UPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it) unc_upi_rxl_crc_llr_req_transmit uncore interconnect LLR Requests Sent event=8  01    LLR Requests Sent : Number of LLR Requests were transmitted.  This should generally be <= the number of CRC errors detected.  If multiple errors are detected before the Rx side receives a LLC_REQ_ACK from the Tx side, there is no need to send more LLR_REQ_NACKs. unc_upi_rxl_credits_consumed_vn0 uncore interconnect VN0 Credit Consumed event=0x39  01    VN0 Credit Consumed : Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed unc_upi_rxl_credits_consumed_vn1 uncore interconnect VN1 Credit Consumed event=0x3a  01    VN1 Credit Consumed : Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed unc_upi_rxl_flits.all_data uncore interconnect Valid Flits Received : All Data event=3,umask=0xf  01    Valid Flits Received : All Data : Shows legal flit time (hides impact of L0p and L0c) unc_upi_rxl_flits.all_null uncore interconnect Null FLITs received from any slot event=3,umask=0x27  01     unc_upi_rxl_flits.data uncore interconnect Valid Flits Received : Data event=3,umask=8  01    Valid Flits Received : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting. unc_upi_rxl_flits.idle uncore interconnect Valid Flits Received : Idle event=3,umask=0x47  01    Valid Flits Received : Idle : Shows legal flit time (hides impact of L0p and L0c) unc_upi_rxl_flits.llcrd uncore interconnect Valid Flits Received : LLCRD Not Empty event=3,umask=0x10  01    Valid Flits Received : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2 unc_upi_rxl_flits.llctrl uncore interconnect Valid Flits Received : LLCTRL event=3,umask=0x40  01    Valid Flits Received : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet.  Enables counting of slot 0 LLCTRL messages unc_upi_rxl_flits.non_data uncore interconnect Valid Flits Received : All Non Data event=3,umask=0x97  01    Valid Flits Received : All Non Data : Shows legal flit time (hides impact of L0p and L0c) unc_upi_rxl_flits.null uncore interconnect Valid Flits Received : Slot NULL or LLCRD Empty event=3,umask=0x20  01    Valid Flits Received : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2 unc_upi_rxl_flits.prothdr uncore interconnect Valid Flits Received : Protocol Header event=3,umask=0x80  01    Valid Flits Received : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits) unc_upi_rxl_flits.slot0 uncore interconnect Valid Flits Received : Slot 0 event=3,umask=1  01    Valid Flits Received : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count unc_upi_rxl_flits.slot1 uncore interconnect Valid Flits Received : Slot 1 event=3,umask=2  01    Valid Flits Received : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count unc_upi_rxl_flits.slot2 uncore interconnect Valid Flits Received : Slot 2 event=3,umask=4  01    Valid Flits Received : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count unc_upi_rxl_inserts.slot0 uncore interconnect RxQ Flit Buffer Allocations : Slot 0 event=0x30,umask=1  01    RxQ Flit Buffer Allocations : Slot 0 : Number of allocations into the UPI Rx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime unc_upi_rxl_inserts.slot1 uncore interconnect RxQ Flit Buffer Allocations : Slot 1 event=0x30,umask=2  01    RxQ Flit Buffer Allocations : Slot 1 : Number of allocations into the UPI Rx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime unc_upi_rxl_inserts.slot2 uncore interconnect RxQ Flit Buffer Allocations : Slot 2 event=0x30,umask=4  01    RxQ Flit Buffer Allocations : Slot 2 : Number of allocations into the UPI Rx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime unc_upi_rxl_occupancy.slot0 uncore interconnect RxQ Occupancy - All Packets : Slot 0 event=0x32,umask=1  01    RxQ Occupancy - All Packets : Slot 0 : Accumulates the number of elements in the UPI RxQ in each cycle.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime unc_upi_rxl_occupancy.slot1 uncore interconnect RxQ Occupancy - All Packets : Slot 1 event=0x32,umask=2  01    RxQ Occupancy - All Packets : Slot 1 : Accumulates the number of elements in the UPI RxQ in each cycle.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime unc_upi_rxl_occupancy.slot2 uncore interconnect RxQ Occupancy - All Packets : Slot 2 event=0x32,umask=4  01    RxQ Occupancy - All Packets : Slot 2 : Accumulates the number of elements in the UPI RxQ in each cycle.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime unc_upi_txl0p_power_cycles uncore interconnect Cycles in L0p event=0x27  01    Cycles in L0p : Number of UPI qfclk cycles spent in L0p power mode.  L0p is a mode where we disable 1/2 of the UPI lanes, decreasing our bandwidth in order to save power.  It increases snoop and data transfer latencies and decreases overall bandwidth.  This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses.  Use edge detect to count the number of instances when the UPI link entered L0p.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another unc_upi_txl0_power_cycles uncore interconnect Cycles in L0 event=0x26  01    Cycles in L0 : Number of UPI qfclk cycles spent in L0 power mode in the Link Layer.  L0 is the default mode which provides the highest performance with the most power.  Use edge detect to count the number of instances that the link entered L0.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.  The phy layer  sometimes leaves L0 for training, which will not be captured by this event unc_upi_txl_any_flits.data uncore interconnect UNC_UPI_TxL_ANY_FLITS.DATA event=0x4a,umask=8  01     unc_upi_txl_any_flits.llcrd uncore interconnect UNC_UPI_TxL_ANY_FLITS.LLCRD event=0x4a,umask=0x10  01     unc_upi_txl_any_flits.llctrl uncore interconnect UNC_UPI_TxL_ANY_FLITS.LLCTRL event=0x4a,umask=0x40  01     unc_upi_txl_any_flits.null uncore interconnect UNC_UPI_TxL_ANY_FLITS.NULL event=0x4a,umask=0x20  01     unc_upi_txl_any_flits.prothdr uncore interconnect UNC_UPI_TxL_ANY_FLITS.PROTHDR event=0x4a,umask=0x80  01     unc_upi_txl_any_flits.slot0 uncore interconnect UNC_UPI_TxL_ANY_FLITS.SLOT0 event=0x4a,umask=1  01     unc_upi_txl_any_flits.slot1 uncore interconnect UNC_UPI_TxL_ANY_FLITS.SLOT1 event=0x4a,umask=2  01     unc_upi_txl_any_flits.slot2 uncore interconnect UNC_UPI_TxL_ANY_FLITS.SLOT2 event=0x4a,umask=4  01     unc_upi_txl_basic_hdr_match.ncb uncore interconnect Matches on Transmit path of a UPI Port : Non-Coherent Bypass event=4,umask=0xe  01    Matches on Transmit path of a UPI Port : Non-Coherent Bypass : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.ncb_opc uncore interconnect Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode event=4,umask=0x10e  01    Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.ncs uncore interconnect Matches on Transmit path of a UPI Port : Non-Coherent Standard event=4,umask=0xf  01    Matches on Transmit path of a UPI Port : Non-Coherent Standard : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.ncs_opc uncore interconnect Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode event=4,umask=0x10f  01    Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_bypassed uncore interconnect Tx Flit Buffer Bypassed event=0x41  01    Tx Flit Buffer Bypassed : Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the UPI Link. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link unc_upi_txl_flits.all_data uncore interconnect Valid Flits Sent : All Data event=2,umask=0xf  01    Valid Flits Sent : All Data : Counts number of data flits across this UPI link unc_upi_txl_flits.all_llcrd uncore interconnect Valid Flits Sent : All LLCRD Not Empty event=2,umask=0x17  01    Valid Flits Sent : All Data : Shows legal flit time (hides impact of L0p and L0c) unc_upi_txl_flits.all_llctrl uncore interconnect Valid Flits Sent : All LLCTRL event=2,umask=0x47  01    Valid Flits Sent : All LLCTRL : Shows legal flit time (hides impact of L0p and L0c) unc_upi_txl_flits.all_null uncore interconnect All Null Flits event=2,umask=0x27  01     unc_upi_txl_flits.all_prothdr uncore interconnect Valid Flits Sent : All Protocol Header event=2,umask=0x87  01    Valid Flits Sent : All ProtDDR : Shows legal flit time (hides impact of L0p and L0c) unc_upi_txl_flits.data uncore interconnect Valid Flits Sent : Data event=2,umask=8  01    Valid Flits Sent : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting. unc_upi_txl_flits.idle uncore interconnect Valid Flits Sent : Idle event=2,umask=0x47  01    Valid Flits Sent : Idle : Shows legal flit time (hides impact of L0p and L0c) unc_upi_txl_flits.llcrd uncore interconnect Valid Flits Sent : LLCRD Not Empty event=2,umask=0x10  01    Valid Flits Sent : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2 unc_upi_txl_flits.llctrl uncore interconnect Valid Flits Sent : LLCTRL event=2,umask=0x40  01    Valid Flits Sent : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet.  Enables counting of slot 0 LLCTRL messages unc_upi_txl_flits.non_data uncore interconnect Valid Flits Sent : All Non Data event=2,umask=0x97  01    Valid Flits Sent : All Non Data : Shows legal flit time (hides impact of L0p and L0c) unc_upi_txl_flits.null uncore interconnect Valid Flits Sent : Slot NULL or LLCRD Empty event=2,umask=0x20  01    Valid Flits Sent : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2 unc_upi_txl_flits.prothdr uncore interconnect Valid Flits Sent : Protocol Header event=2,umask=0x80  01    Valid Flits Sent : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits) unc_upi_txl_flits.slot0 uncore interconnect Valid Flits Sent : Slot 0 event=2,umask=1  01    Valid Flits Sent : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count unc_upi_txl_flits.slot1 uncore interconnect Valid Flits Sent : Slot 1 event=2,umask=2  01    Valid Flits Sent : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count unc_upi_txl_flits.slot2 uncore interconnect Valid Flits Sent : Slot 2 event=2,umask=4  01    Valid Flits Sent : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count unc_upi_txl_inserts uncore interconnect Tx Flit Buffer Allocations event=0x40  01    Tx Flit Buffer Allocations : Number of allocations into the UPI Tx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime unc_upi_txl_occupancy uncore interconnect Tx Flit Buffer Occupancy event=0x42  01    Tx Flit Buffer Occupancy : Accumulates the number of flits in the TxQ.  Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ unc_upi_vna_credit_return_occupancy uncore interconnect VNA Credits Pending Return - Occupancy event=0x44  01    VNA Credits Pending Return - Occupancy : Number of VNA credits in the Rx side that are waitng to be returned back across the link unc_u_event_msg.doorbell_rcvd uncore interconnect Message Received : Doorbell event=0x42,umask=8  01     unc_u_event_msg.int_prio uncore interconnect Message Received : Interrupt event=0x42,umask=0x10  01    Message Received : Interrupt : Interrupts unc_u_event_msg.ipi_rcvd uncore interconnect Message Received : IPI event=0x42,umask=4  01    Message Received : IPI : Inter Processor Interrupts unc_u_event_msg.msi_rcvd uncore interconnect Message Received : MSI event=0x42,umask=2  01    Message Received : MSI : Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only) unc_u_event_msg.vlw_rcvd uncore interconnect Message Received : VLW event=0x42,umask=1  01    Message Received : VLW : Virtual Logical Wire (legacy) message were received from Uncore unc_u_m2u_misc1.rxc_cycles_ne_cbo_ncb uncore interconnect UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB event=0x4d,umask=1  01     unc_u_m2u_misc1.rxc_cycles_ne_cbo_ncs uncore interconnect UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS event=0x4d,umask=2  01     unc_u_m2u_misc1.rxc_cycles_ne_upi_ncb uncore interconnect UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB event=0x4d,umask=4  01     unc_u_m2u_misc1.rxc_cycles_ne_upi_ncs uncore interconnect UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS event=0x4d,umask=8  01     unc_u_m2u_misc1.txc_cycles_crd_ovf_cbo_ncb uncore interconnect UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB event=0x4d,umask=0x10  01     unc_u_m2u_misc1.txc_cycles_crd_ovf_cbo_ncs uncore interconnect UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS event=0x4d,umask=0x20  01     unc_u_m2u_misc1.txc_cycles_crd_ovf_upi_ncb uncore interconnect UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB event=0x4d,umask=0x40  01     unc_u_m2u_misc1.txc_cycles_crd_ovf_upi_ncs uncore interconnect UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS event=0x4d,umask=0x80  01     unc_u_m2u_misc2.rxc_cycles_empty_bl uncore interconnect UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL event=0x4e,umask=2  01     unc_u_m2u_misc2.rxc_cycles_full_bl uncore interconnect UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL event=0x4e,umask=1  01     unc_u_m2u_misc2.txc_cycles_crd_ovf_vn0_ncb uncore interconnect UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB event=0x4e,umask=4  01     unc_u_m2u_misc2.txc_cycles_crd_ovf_vn0_ncs uncore interconnect UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS event=0x4e,umask=8  01     unc_u_m2u_misc2.txc_cycles_empty_ak uncore interconnect UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK event=0x4e,umask=0x20  01     unc_u_m2u_misc2.txc_cycles_empty_akc uncore interconnect UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC event=0x4e,umask=0x40  01     unc_u_m2u_misc2.txc_cycles_empty_bl uncore interconnect UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL event=0x4e,umask=0x10  01     unc_u_m2u_misc2.txc_cycles_full_bl uncore interconnect UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL event=0x4e,umask=0x80  01     unc_u_m2u_misc3.txc_cycles_full_ak uncore interconnect UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK event=0x4f,umask=1  01     unc_u_m2u_misc3.txc_cycles_full_akc uncore interconnect UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC event=0x4f,umask=2  01     unc_u_phold_cycles.assert_to_ack uncore interconnect Cycles PHOLD Assert to Ack : Assert to ACK event=0x45,umask=1  01    Cycles PHOLD Assert to Ack : Assert to ACK : PHOLD cycles unc_u_racu_requests uncore interconnect RACU Request event=0x46  01    RACU Request : Number outstanding register requests within message channel tracker uncore_iio_free_running unc_iio_bandwidth_in.part0_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x20  01     unc_iio_bandwidth_in.part1_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x21  01     unc_iio_bandwidth_in.part2_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x22  01     unc_iio_bandwidth_in.part3_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x23  01     unc_iio_bandwidth_in.part4_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x24  01     unc_iio_bandwidth_in.part5_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x25  01     unc_iio_bandwidth_in.part6_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x26  01     unc_iio_bandwidth_in.part7_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x27  01     unc_iio_clockticks uncore io IIO Clockticks event=1  01    Number of IIO clock cycles while the event is enabled unc_iio_clockticks_freerun uncore io Free running counter that increments for IIO clocktick event=0xff,umask=0x10  01     unc_iio_comp_buf_inserts.cmpd.all_parts uncore io PCIe Completion Buffer Inserts of completions with data: Part 0-7 event=0xc2,ch_mask=0xff,fc_mask=7,umask=4  01    PCIe Completion Buffer Inserts of completions with data : Part 0-7 unc_iio_comp_buf_inserts.cmpd.part0 uncore io PCIe Completion Buffer Inserts of completions with data: Part 0 event=0xc2,ch_mask=1,fc_mask=7,umask=4  01    PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_comp_buf_inserts.cmpd.part1 uncore io PCIe Completion Buffer Inserts of completions with data: Part 1 event=0xc2,ch_mask=2,fc_mask=7,umask=4  01    PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1 unc_iio_comp_buf_inserts.cmpd.part2 uncore io PCIe Completion Buffer Inserts of completions with data: Part 2 event=0xc2,ch_mask=4,fc_mask=7,umask=4  01    PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2 unc_iio_comp_buf_inserts.cmpd.part3 uncore io PCIe Completion Buffer Inserts of completions with data: Part 3 event=0xc2,ch_mask=8,fc_mask=7,umask=4  01    PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3 unc_iio_comp_buf_inserts.cmpd.part4 uncore io PCIe Completion Buffer Inserts of completions with data: Part 4 event=0xc2,ch_mask=0x10,fc_mask=7,umask=4  01    PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4 unc_iio_comp_buf_inserts.cmpd.part5 uncore io PCIe Completion Buffer Inserts of completions with data: Part 5 event=0xc2,ch_mask=0x20,fc_mask=7,umask=4  01    PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5 unc_iio_comp_buf_inserts.cmpd.part6 uncore io PCIe Completion Buffer Inserts of completions with data: Part 6 event=0xc2,ch_mask=0x40,fc_mask=7,umask=4  01    PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6 unc_iio_comp_buf_inserts.cmpd.part7 uncore io PCIe Completion Buffer Inserts of completions with data: Part 7 event=0xc2,ch_mask=0x80,fc_mask=7,umask=4  01    PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7 unc_iio_comp_buf_occupancy.cmpd.all_parts uncore io UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS event=0xd5,fc_mask=7,umask=0xff  01     unc_iio_comp_buf_occupancy.cmpd.part0 uncore io PCIe Completion Buffer Occupancy : Part 0 event=0xd5,fc_mask=7,umask=1  01    x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_comp_buf_occupancy.cmpd.part1 uncore io PCIe Completion Buffer Occupancy : Part 1 event=0xd5,fc_mask=7,umask=2  01    x4 card is plugged in to slot 1 unc_iio_comp_buf_occupancy.cmpd.part2 uncore io PCIe Completion Buffer Occupancy : Part 2 event=0xd5,fc_mask=7,umask=4  01    x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_comp_buf_occupancy.cmpd.part3 uncore io PCIe Completion Buffer Occupancy : Part 3 event=0xd5,fc_mask=7,umask=8  01    x4 card is plugged in to slot 3 unc_iio_comp_buf_occupancy.cmpd.part4 uncore io PCIe Completion Buffer Occupancy : Part 4 event=0xd5,fc_mask=7,umask=0x10  01    x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_comp_buf_occupancy.cmpd.part5 uncore io PCIe Completion Buffer Occupancy : Part 5 event=0xd5,fc_mask=7,umask=0x20  01    x4 card is plugged in to slot 1 unc_iio_comp_buf_occupancy.cmpd.part6 uncore io PCIe Completion Buffer Occupancy : Part 6 event=0xd5,fc_mask=7,umask=0x40  01    x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_comp_buf_occupancy.cmpd.part7 uncore io PCIe Completion Buffer Occupancy : Part 7 event=0xd5,fc_mask=7,umask=0x80  01    x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.mem_read.all_parts uncore io Read request for 4 bytes made by the CPU to IIO Part0-7 event=0xc0,ch_mask=0xff,fc_mask=7,umask=4  01     unc_iio_data_req_by_cpu.mem_read.part0 uncore io Read request for 4 bytes made by the CPU to IIO Part0 event=0xc0,ch_mask=1,fc_mask=7,umask=4  01    Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.mem_read.part1 uncore io Read request for 4 bytes made by the CPU to IIO Part1 event=0xc0,ch_mask=2,fc_mask=7,umask=4  01    Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.mem_read.part2 uncore io Read request for 4 bytes made by the CPU to IIO Part2 event=0xc0,ch_mask=4,fc_mask=7,umask=4  01    Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.mem_read.part3 uncore io Read request for 4 bytes made by the CPU to IIO Part3 event=0xc0,ch_mask=8,fc_mask=7,umask=4  01    Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.mem_read.part4 uncore io Data requested by the CPU : Core reading from Cards MMIO space event=0xc0,ch_mask=0x10,fc_mask=7,umask=4  01    Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.mem_read.part5 uncore io Data requested by the CPU : Core reading from Cards MMIO space event=0xc0,ch_mask=0x20,fc_mask=7,umask=4  01    Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.mem_read.part6 uncore io Data requested by the CPU : Core reading from Cards MMIO space event=0xc0,ch_mask=0x40,fc_mask=7,umask=4  01    Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.mem_read.part7 uncore io Data requested by the CPU : Core reading from Cards MMIO space event=0xc0,ch_mask=0x80,fc_mask=7,umask=4  01    Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.mem_write.all_parts uncore io Write request of 4 bytes made to IIO Part0-7 by the CPU event=0xc0,ch_mask=0xff,fc_mask=7,umask=1  01     unc_iio_data_req_by_cpu.mem_write.iommu0 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=0x100,fc_mask=7,umask=1  01    Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_by_cpu.mem_write.iommu1 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=0x200,fc_mask=7,umask=1  01    Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_by_cpu.mem_write.part0 uncore io Write request of 4 bytes made to IIO Part0 by the CPU event=0xc0,ch_mask=1,fc_mask=7,umask=1  01    Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.mem_write.part1 uncore io Write request of 4 bytes made to IIO Part1 by the CPU event=0xc0,ch_mask=2,fc_mask=7,umask=1  01    Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.mem_write.part2 uncore io Write request of 4 bytes made to IIO Part2 by the CPU event=0xc0,ch_mask=4,fc_mask=7,umask=1  01    Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.mem_write.part3 uncore io Write request of 4 bytes made to IIO Part3 by the CPU event=0xc0,ch_mask=8,fc_mask=7,umask=1  01    Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.mem_write.part4 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=0x10,fc_mask=7,umask=1  01    Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.mem_write.part5 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=0x20,fc_mask=7,umask=1  01    Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.mem_write.part6 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=0x40,fc_mask=7,umask=1  01    Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.mem_write.part7 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=0x80,fc_mask=7,umask=1  01    Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.peer_read.part0 uncore io Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0 event=0xc0,ch_mask=1,fc_mask=7,umask=8  01    Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.peer_read.part1 uncore io Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0 event=0xc0,ch_mask=2,fc_mask=7,umask=8  01    Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.peer_read.part2 uncore io Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0 event=0xc0,ch_mask=4,fc_mask=7,umask=8  01    Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.peer_read.part3 uncore io Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0 event=0xc0,ch_mask=8,fc_mask=7,umask=8  01    Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.peer_read.part4 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x10,fc_mask=7,umask=8  01    Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.peer_read.part5 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x20,fc_mask=7,umask=8  01    Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.peer_read.part6 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x40,fc_mask=7,umask=8  01    Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.peer_read.part7 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x80,fc_mask=7,umask=8  01    Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.peer_write.part0 uncore io Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit event=0xc0,ch_mask=1,fc_mask=7,umask=2  01    Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.peer_write.part1 uncore io Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit event=0xc0,ch_mask=2,fc_mask=7,umask=2  01    Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.peer_write.part2 uncore io Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit event=0xc0,ch_mask=4,fc_mask=7,umask=2  01    Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.peer_write.part3 uncore io Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit event=0xc0,ch_mask=8,fc_mask=7,umask=2  01    Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.peer_write.part4 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x10,fc_mask=7,umask=2  01    Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.peer_write.part5 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x20,fc_mask=7,umask=2  01    Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.peer_write.part6 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x40,fc_mask=7,umask=2  01    Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.peer_write.part7 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x80,fc_mask=7,umask=2  01    Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.cmpd.all_parts uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0xff,fc_mask=7,umask=0x80  01    Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.cmpd.part0 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=1,fc_mask=7,umask=0x80  01    Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.cmpd.part1 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=2,fc_mask=7,umask=0x80  01    Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.cmpd.part2 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=4,fc_mask=7,umask=0x80  01    Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.cmpd.part3 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=8,fc_mask=7,umask=0x80  01    Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.cmpd.part4 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0x10,fc_mask=7,umask=0x80  01    Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_of_cpu.cmpd.part5 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0x20,fc_mask=7,umask=0x80  01    Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_of_cpu.cmpd.part6 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0x40,fc_mask=7,umask=0x80  01    Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_of_cpu.cmpd.part7 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0x80,fc_mask=7,umask=0x80  01    Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_of_cpu.mem_read.all_parts uncore io Read request for 4 bytes made by IIO Part0-7 to Memory event=0x83,ch_mask=0xff,fc_mask=7,umask=4  01     unc_iio_data_req_of_cpu.mem_read.part0 uncore io Read request for 4 bytes made by IIO Part0 to Memory event=0x83,ch_mask=1,fc_mask=7,umask=4  01    Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.mem_read.part1 uncore io Read request for 4 bytes made by IIO Part1 to Memory event=0x83,ch_mask=2,fc_mask=7,umask=4  01    Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_read.part2 uncore io Read request for 4 bytes made by IIO Part2 to Memory event=0x83,ch_mask=4,fc_mask=7,umask=4  01    Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_read.part3 uncore io Read request for 4 bytes made by IIO Part3 to Memory event=0x83,ch_mask=8,fc_mask=7,umask=4  01    Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.mem_read.part4 uncore io Data requested of the CPU : Card reading from DRAM event=0x83,ch_mask=0x10,fc_mask=7,umask=4  01    Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.mem_read.part5 uncore io Data requested of the CPU : Card reading from DRAM event=0x83,ch_mask=0x20,fc_mask=7,umask=4  01    Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_read.part6 uncore io Data requested of the CPU : Card reading from DRAM event=0x83,ch_mask=0x40,fc_mask=7,umask=4  01    Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_read.part7 uncore io Data requested of the CPU : Card reading from DRAM event=0x83,ch_mask=0x80,fc_mask=7,umask=4  01    Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.mem_write.all_parts uncore io Write request of 4 bytes made by IIO Part0-7 to Memory event=0x83,ch_mask=0xff,fc_mask=7,umask=1  01     unc_iio_data_req_of_cpu.mem_write.part0 uncore io Write request of 4 bytes made by IIO Part0 to Memory event=0x83,ch_mask=1,fc_mask=7,umask=1  01    Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.mem_write.part1 uncore io Write request of 4 bytes made by IIO Part1 to Memory event=0x83,ch_mask=2,fc_mask=7,umask=1  01    Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_write.part2 uncore io Write request of 4 bytes made by IIO Part2 to Memory event=0x83,ch_mask=4,fc_mask=7,umask=1  01    Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_write.part3 uncore io Write request of 4 bytes made by IIO Part3 to Memory event=0x83,ch_mask=8,fc_mask=7,umask=1  01    Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.mem_write.part4 uncore io Data requested of the CPU : Card writing to DRAM event=0x83,ch_mask=0x10,fc_mask=7,umask=1  01    Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.mem_write.part5 uncore io Data requested of the CPU : Card writing to DRAM event=0x83,ch_mask=0x20,fc_mask=7,umask=1  01    Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_write.part6 uncore io Data requested of the CPU : Card writing to DRAM event=0x83,ch_mask=0x40,fc_mask=7,umask=1  01    Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_write.part7 uncore io Data requested of the CPU : Card writing to DRAM event=0x83,ch_mask=0x80,fc_mask=7,umask=1  01    Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.peer_write.part0 uncore io Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target event=0x83,ch_mask=1,fc_mask=7,umask=2  01    Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.peer_write.part1 uncore io Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target event=0x83,ch_mask=2,fc_mask=7,umask=2  01    Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.peer_write.part2 uncore io Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target event=0x83,ch_mask=4,fc_mask=7,umask=2  01    Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.peer_write.part3 uncore io Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target event=0x83,ch_mask=8,fc_mask=7,umask=2  01    Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.peer_write.part4 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x10,fc_mask=7,umask=2  01    Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.peer_write.part5 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x20,fc_mask=7,umask=2  01    Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.peer_write.part6 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x40,fc_mask=7,umask=2  01    Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.peer_write.part7 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x80,fc_mask=7,umask=2  01    Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_inbound_arb_req.data uncore io Incoming arbitration requests : Passing data to be written event=0x86,ch_mask=0xff,fc_mask=7,umask=0x20  01    Incoming arbitration requests : Passing data to be written : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests unc_iio_inbound_arb_req.final_rd_wr uncore io Incoming arbitration requests : Issuing final read or write of line event=0x86,ch_mask=0xff,fc_mask=7,umask=8  01    Incoming arbitration requests : Issuing final read or write of line : How often different queues (e.g. channel / fc) ask to send request into pipeline unc_iio_inbound_arb_req.iommu_hit uncore io Incoming arbitration requests : Processing response from IOMMU event=0x86,ch_mask=0xff,fc_mask=7,umask=2  01    Incoming arbitration requests : Processing response from IOMMU : How often different queues (e.g. channel / fc) ask to send request into pipeline unc_iio_inbound_arb_req.iommu_req uncore io Incoming arbitration requests : Issuing to IOMMU event=0x86,ch_mask=0xff,fc_mask=7,umask=1  01    Incoming arbitration requests : Issuing to IOMMU : How often different queues (e.g. channel / fc) ask to send request into pipeline unc_iio_inbound_arb_req.req_own uncore io Incoming arbitration requests : Request Ownership event=0x86,ch_mask=0xff,fc_mask=7,umask=4  01    Incoming arbitration requests : Request Ownership : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests unc_iio_inbound_arb_req.wr uncore io Incoming arbitration requests : Writing line event=0x86,ch_mask=0xff,fc_mask=7,umask=0x10  01    Incoming arbitration requests : Writing line : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests unc_iio_inbound_arb_won.data uncore io Incoming arbitration requests granted : Passing data to be written event=0x87,ch_mask=0xff,fc_mask=7,umask=0x20  01    Incoming arbitration requests granted : Passing data to be written : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests unc_iio_inbound_arb_won.final_rd_wr uncore io Incoming arbitration requests granted : Issuing final read or write of line event=0x87,ch_mask=0xff,fc_mask=7,umask=8  01    Incoming arbitration requests granted : Issuing final read or write of line : How often different queues (e.g. channel / fc) are allowed to send request into pipeline unc_iio_inbound_arb_won.iommu_hit uncore io Incoming arbitration requests granted : Processing response from IOMMU event=0x87,ch_mask=0xff,fc_mask=7,umask=2  01    Incoming arbitration requests granted : Processing response from IOMMU : How often different queues (e.g. channel / fc) are allowed to send request into pipeline unc_iio_inbound_arb_won.iommu_req uncore io Incoming arbitration requests granted : Issuing to IOMMU event=0x87,ch_mask=0xff,fc_mask=7,umask=1  01    Incoming arbitration requests granted : Issuing to IOMMU : How often different queues (e.g. channel / fc) are allowed to send request into pipeline unc_iio_inbound_arb_won.req_own uncore io Incoming arbitration requests granted : Request Ownership event=0x87,ch_mask=0xff,fc_mask=7,umask=4  01    Incoming arbitration requests granted : Request Ownership : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests unc_iio_inbound_arb_won.wr uncore io Incoming arbitration requests granted : Writing line event=0x87,ch_mask=0xff,fc_mask=7,umask=0x10  01    Incoming arbitration requests granted : Writing line : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests unc_iio_iommu0.1g_hits uncore io : IOTLB Hits to a 1G Page event=0x40,umask=0x10  01    : IOTLB Hits to a 1G Page : Counts if a transaction to a 1G page, on its first lookup, hits the IOTLB unc_iio_iommu0.2m_hits uncore io : IOTLB Hits to a 2M Page event=0x40,umask=8  01    : IOTLB Hits to a 2M Page : Counts if a transaction to a 2M page, on its first lookup, hits the IOTLB unc_iio_iommu0.4k_hits uncore io : IOTLB Hits to a 4K Page event=0x40,umask=4  01    : IOTLB Hits to a 4K Page : Counts if a transaction to a 4K page, on its first lookup, hits the IOTLB unc_iio_iommu0.ctxt_cache_hits uncore io : Context cache hits event=0x40,umask=0x80  01    : Context cache hits : Counts each time a first look up of the transaction hits the RCC unc_iio_iommu0.ctxt_cache_lookups uncore io : Context cache lookups event=0x40,umask=0x40  01    : Context cache lookups : Counts each time a transaction looks up root context cache unc_iio_iommu0.first_lookups uncore io : IOTLB lookups first event=0x40,umask=1  01    : IOTLB lookups first : Some transactions have to look up IOTLB multiple times.  Counts the first time a request looks up IOTLB unc_iio_iommu0.misses uncore io IOTLB Fills (same as IOTLB miss) event=0x40,umask=0x20  01    IOTLB Fills (same as IOTLB miss) : When a transaction misses IOTLB, it does a page walk to look up memory and bring in the relevant page translation. Counts when this page translation is written to IOTLB unc_iio_iommu1.num_mem_accesses uncore io : IOMMU memory access event=0x41,umask=0xc0  01    : IOMMU memory access : IOMMU sends out memory fetches when it misses the cache look up which is indicated by this signal.  M2IOSF only uses low priority channel unc_iio_iommu1.pwc_1g_hits uncore io : PWC Hit to a 2M page event=0x41,umask=4  01    : PWC Hit to a 2M page : Counts each time a transaction's first look up hits the SLPWC at the 2M level unc_iio_iommu1.pwc_256t_hits uncore io : PWT Hit to a 256T page event=0x41,umask=0x10  01    : PWT Hit to a 256T page : Counts each time a transaction's first look up hits the SLPWC at the 512G level unc_iio_iommu1.pwc_2m_hits uncore io : PWC Hit to a 4K page event=0x41,umask=2  01    : PWC Hit to a 4K page : Counts each time a transaction's first look up hits the SLPWC at the 4K level unc_iio_iommu1.pwc_512g_hits uncore io : PWC Hit to a 1G page event=0x41,umask=8  01    : PWC Hit to a 1G page : Counts each time a transaction's first look up hits the SLPWC at the 1G level unc_iio_iommu1.pwc_cache_fills uncore io : PageWalk cache fill event=0x41,umask=0x20  01    : PageWalk cache fill : When a transaction misses SLPWC, it does a page walk to look up memory and bring in the relevant page translation. When this page translation is written to SLPWC, ObsPwcFillValid_nnnH is asserted unc_iio_iommu1.pwt_cache_lookups uncore io : PageWalk cache lookup event=0x41,umask=1  01    : PageWalk cache lookup : Counts each time a transaction looks up second level page walk cache unc_iio_iommu1.slpwc_1g_hits uncore io : PWC Hit to a 2M page event=0x41,umask=4  01    : PWC Hit to a 2M page : Counts each time a transaction's first look up hits the SLPWC at the 2M level unc_iio_iommu1.slpwc_256t_hits uncore io : PWC Hit to a 2M page event=0x41,umask=0x10  01    : PWC Hit to a 2M page : Counts each time a transaction's first look up hits the SLPWC at the 2M level unc_iio_iommu1.slpwc_512g_hits uncore io : PWC Hit to a 1G page event=0x41,umask=8  01    : PWC Hit to a 1G page : Counts each time a transaction's first look up hits the SLPWC at the 1G level unc_iio_iommu3.pwt_occupancy_msb uncore io : Global IOTLB invalidation cycles event=0x43,umask=1  01    : Global IOTLB invalidation cycles : Indicates that IOMMU is doing global invalidation unc_iio_mask_match_and.bus0 uncore io AND Mask/match for debug bus : Non-PCIE bus event=2,umask=1  01    AND Mask/match for debug bus : Non-PCIE bus : Asserted if all bits specified by mask match unc_iio_mask_match_and.bus0_bus1 uncore io AND Mask/match for debug bus : Non-PCIE bus and PCIE bus event=2,umask=8  01    AND Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if all bits specified by mask match unc_iio_mask_match_and.bus0_not_bus1 uncore io AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) event=2,umask=4  01    AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if all bits specified by mask match unc_iio_mask_match_and.bus1 uncore io AND Mask/match for debug bus : PCIE bus event=2,umask=2  01    AND Mask/match for debug bus : PCIE bus : Asserted if all bits specified by mask match unc_iio_mask_match_and.not_bus0_bus1 uncore io AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus event=2,umask=0x10  01    AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if all bits specified by mask match unc_iio_mask_match_and.not_bus0_not_bus1 uncore io AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) event=2,umask=0x20  01    AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if all bits specified by mask match unc_iio_mask_match_or.bus0 uncore io OR Mask/match for debug bus : Non-PCIE bus event=3,umask=1  01    OR Mask/match for debug bus : Non-PCIE bus : Asserted if any bits specified by mask match unc_iio_mask_match_or.bus0_bus1 uncore io OR Mask/match for debug bus : Non-PCIE bus and PCIE bus event=3,umask=8  01    OR Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if any bits specified by mask match unc_iio_mask_match_or.bus0_not_bus1 uncore io OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) event=3,umask=4  01    OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if any bits specified by mask match unc_iio_mask_match_or.bus1 uncore io OR Mask/match for debug bus : PCIE bus event=3,umask=2  01    OR Mask/match for debug bus : PCIE bus : Asserted if any bits specified by mask match unc_iio_mask_match_or.not_bus0_bus1 uncore io OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus event=3,umask=0x10  01    OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if any bits specified by mask match unc_iio_mask_match_or.not_bus0_not_bus1 uncore io OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) event=3,umask=0x20  01    OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if any bits specified by mask match unc_iio_num_req_of_cpu.commit.all uncore io Number requests PCIe makes of the main die : All event=0x85,ch_mask=0xfff,fc_mask=7,umask=1  01    Number requests PCIe makes of the main die : All : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU unc_iio_num_req_of_cpu_by_tgt.abort uncore io Num requests sent by PCIe - by target : Abort event=0x8e,ch_mask=0xff,fc_mask=7,umask=0x80  01     unc_iio_num_req_of_cpu_by_tgt.confined_p2p uncore io Num requests sent by PCIe - by target : Confined P2P event=0x8e,ch_mask=0xff,fc_mask=7,umask=0x40  01     unc_iio_num_req_of_cpu_by_tgt.loc_p2p uncore io Num requests sent by PCIe - by target : Local P2P event=0x8e,ch_mask=0xff,fc_mask=7,umask=0x20  01     unc_iio_num_req_of_cpu_by_tgt.mcast uncore io Num requests sent by PCIe - by target : Multi-cast event=0x8e,ch_mask=0xff,fc_mask=7,umask=2  01     unc_iio_num_req_of_cpu_by_tgt.mem uncore io Num requests sent by PCIe - by target : Memory event=0x8e,ch_mask=0xff,fc_mask=7,umask=8  01     unc_iio_num_req_of_cpu_by_tgt.msgb uncore io Num requests sent by PCIe - by target : MsgB event=0x8e,ch_mask=0xff,fc_mask=7,umask=1  01     unc_iio_num_req_of_cpu_by_tgt.rem_p2p uncore io Num requests sent by PCIe - by target : Remote P2P event=0x8e,ch_mask=0xff,fc_mask=7,umask=0x10  01     unc_iio_num_req_of_cpu_by_tgt.ubox uncore io Num requests sent by PCIe - by target : Ubox event=0x8e,ch_mask=0xff,fc_mask=7,umask=4  01     unc_iio_num_req_of_cpu_by_tgt.ubox_posted uncore io Posted requests sent by the integrated IO (IIO) controller to the Ubox, useful for counting message signaled interrupts (MSI) event=0x8e,ch_mask=0xff,fc_mask=1,umask=4  01     unc_iio_num_tgt_matched_req_of_cpu uncore io ITC address map 1 event=0x8f  01    UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU unc_iio_outbound_cl_reqs_issued.to_io uncore io Outbound cacheline requests issued : 64B requests issued to device event=0xd0,ch_mask=0xff,fc_mask=7,umask=8  01    Outbound cacheline requests issued : 64B requests issued to device : Each outbound cacheline granular request may need to make multiple passes through the pipeline.  Each time a cacheline completes all its passes it advances line unc_iio_outbound_tlp_reqs_issued.to_io uncore io Outbound TLP (transaction layer packet) requests issued : To device event=0xd1,ch_mask=0xff,fc_mask=7,umask=8  01    Outbound TLP (transaction layer packet) requests issued : To device : Each time an outbound completes all its passes it advances the pointer unc_iio_pwt_occupancy uncore io PWT occupancy.  Does not include 9th bit of occupancy (will undercount if PWT is greater than 255 per cycle) event=0x42,umask=0xff  01    PWT occupancy : Indicates how many page walks are outstanding at any point in time unc_iio_req_from_pcie_cl_cmpl.data uncore io Request Ownership : PCIe Request complete event=0x91,ch_mask=0xff,fc_mask=7,umask=0x20  01    Request Ownership : PCIe Request complete : Only for posted requests : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a single PCIe request completes all its cacheline granular requests, it advances pointer unc_iio_req_from_pcie_cl_cmpl.final_rd_wr uncore io Request Ownership : Writing line event=0x91,ch_mask=0xff,fc_mask=7,umask=8  01    Request Ownership : Writing line : Only for posted requests : Only for posted requests unc_iio_req_from_pcie_cl_cmpl.req_own uncore io Request Ownership : Issuing final read or write of line event=0x91,ch_mask=0xff,fc_mask=7,umask=4  01    Request Ownership : Issuing final read or write of line : Only for posted requests unc_iio_req_from_pcie_cl_cmpl.wr uncore io Request Ownership : Passing data to be written event=0x91,ch_mask=0xff,fc_mask=7,umask=0x10  01    Request Ownership : Passing data to be written : Only for posted requests : Only for posted requests unc_iio_req_from_pcie_cmpl.final_rd_wr uncore io Processing response from IOMMU : Passing data to be written event=0x92,ch_mask=0xff,fc_mask=7,umask=8  01    Processing response from IOMMU : Passing data to be written : Only for posted requests unc_iio_req_from_pcie_cmpl.iommu_hit uncore io Processing response from IOMMU : Issuing final read or write of line event=0x92,ch_mask=0xff,fc_mask=7,umask=2  01     unc_iio_req_from_pcie_cmpl.iommu_req uncore io Processing response from IOMMU : Request Ownership event=0x92,ch_mask=0xff,fc_mask=7,umask=1  01    Processing response from IOMMU : Request Ownership : Only for posted requests unc_iio_req_from_pcie_cmpl.req_own uncore io Processing response from IOMMU : Writing line event=0x92,ch_mask=0xff,fc_mask=7,umask=4  01    Processing response from IOMMU : Writing line : Only for posted requests unc_iio_req_from_pcie_pass_cmpl.data uncore io PCIe Request - pass complete : Passing data to be written event=0x90,ch_mask=0xff,fc_mask=7,umask=0x20  01    PCIe Request - pass complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests unc_iio_req_from_pcie_pass_cmpl.final_rd_wr uncore io PCIe Request - pass complete : Issuing final read or write of line event=0x90,ch_mask=0xff,fc_mask=7,umask=8  01    PCIe Request - pass complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state unc_iio_req_from_pcie_pass_cmpl.req_own uncore io PCIe Request - pass complete : Request Ownership event=0x90,ch_mask=0xff,fc_mask=7,umask=4  01    PCIe Request - pass complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests unc_iio_req_from_pcie_pass_cmpl.wr uncore io PCIe Request - pass complete : Writing line event=0x90,ch_mask=0xff,fc_mask=7,umask=0x10  01    PCIe Request - pass complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests unc_iio_txn_req_by_cpu.mem_read.part0 uncore io Read request for up to a 64 byte transaction is made by the CPU to IIO Part0 event=0xc1,ch_mask=1,fc_mask=7,umask=4  01    Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.mem_read.part1 uncore io Read request for up to a 64 byte transaction is made by the CPU to IIO Part1 event=0xc1,ch_mask=2,fc_mask=7,umask=4  01    Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.mem_read.part2 uncore io Read request for up to a 64 byte transaction is made by the CPU to IIO Part2 event=0xc1,ch_mask=4,fc_mask=7,umask=4  01    Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.mem_read.part3 uncore io Read request for up to a 64 byte transaction is made by the CPU to IIO Part3 event=0xc1,ch_mask=8,fc_mask=7,umask=4  01    Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.mem_read.part4 uncore io Number Transactions requested by the CPU : Core reading from Cards MMIO space event=0xc1,ch_mask=0x10,fc_mask=7,umask=4  01    Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.mem_read.part5 uncore io Number Transactions requested by the CPU : Core reading from Cards MMIO space event=0xc1,ch_mask=0x20,fc_mask=7,umask=4  01    Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.mem_read.part6 uncore io Number Transactions requested by the CPU : Core reading from Cards MMIO space event=0xc1,ch_mask=0x40,fc_mask=7,umask=4  01    Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.mem_read.part7 uncore io Number Transactions requested by the CPU : Core reading from Cards MMIO space event=0xc1,ch_mask=0x80,fc_mask=7,umask=4  01    Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.mem_write.part0 uncore io Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU event=0xc1,ch_mask=1,fc_mask=7,umask=1  01    Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.mem_write.part1 uncore io Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU event=0xc1,ch_mask=2,fc_mask=7,umask=1  01    Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.mem_write.part2 uncore io Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU event=0xc1,ch_mask=4,fc_mask=7,umask=1  01    Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.mem_write.part3 uncore io Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU event=0xc1,ch_mask=8,fc_mask=7,umask=1  01    Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.mem_write.part4 uncore io Number Transactions requested by the CPU : Core writing to Cards MMIO space event=0xc1,ch_mask=0x10,fc_mask=7,umask=1  01    Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.mem_write.part5 uncore io Number Transactions requested by the CPU : Core writing to Cards MMIO space event=0xc1,ch_mask=0x20,fc_mask=7,umask=1  01    Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.mem_write.part6 uncore io Number Transactions requested by the CPU : Core writing to Cards MMIO space event=0xc1,ch_mask=0x40,fc_mask=7,umask=1  01    Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.mem_write.part7 uncore io Number Transactions requested by the CPU : Core writing to Cards MMIO space event=0xc1,ch_mask=0x80,fc_mask=7,umask=1  01    Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.peer_write.part0 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=1,fc_mask=7,umask=2  01    Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.peer_write.part1 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=2,fc_mask=7,umask=2  01    Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.peer_write.part2 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=4,fc_mask=7,umask=2  01    Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.peer_write.part3 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=8,fc_mask=7,umask=2  01    Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.peer_write.part4 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x10,fc_mask=7,umask=2  01    Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_by_cpu.peer_write.part5 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x20,fc_mask=7,umask=2  01    Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_by_cpu.peer_write.part6 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x40,fc_mask=7,umask=2  01    Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_by_cpu.peer_write.part7 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x80,fc_mask=7,umask=2  01    Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_of_cpu.cmpd.part0 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=1,fc_mask=7,umask=0x80  01    Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.cmpd.part1 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=2,fc_mask=7,umask=0x80  01    Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.cmpd.part2 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=4,fc_mask=7,umask=0x80  01    Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_of_cpu.cmpd.part3 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=8,fc_mask=7,umask=0x80  01    Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.cmpd.part4 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=0x10,fc_mask=7,umask=0x80  01    Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_of_cpu.cmpd.part5 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=0x20,fc_mask=7,umask=0x80  01    Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_of_cpu.cmpd.part6 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=0x40,fc_mask=7,umask=0x80  01    Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_of_cpu.cmpd.part7 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=0x80,fc_mask=7,umask=0x80  01    Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_of_cpu.mem_read.part0 uncore io Read request for up to a 64 byte transaction is made by IIO Part0 to Memory event=0x84,ch_mask=1,fc_mask=7,umask=4  01    Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.mem_read.part1 uncore io Read request for up to a 64 byte transaction is  made by IIO Part1 to Memory event=0x84,ch_mask=2,fc_mask=7,umask=4  01    Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.mem_read.part2 uncore io Read request for up to a 64 byte transaction is made by IIO Part2 to Memory event=0x84,ch_mask=4,fc_mask=7,umask=4  01    Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.mem_read.part3 uncore io Read request for up to a 64 byte transaction is made by IIO Part3 to Memory event=0x84,ch_mask=8,fc_mask=7,umask=4  01    Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.mem_read.part4 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x10,fc_mask=7,umask=4  01    Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.mem_read.part5 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x20,fc_mask=7,umask=4  01    Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.mem_read.part6 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x40,fc_mask=7,umask=4  01    Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.mem_read.part7 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x80,fc_mask=7,umask=4  01    Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.mem_write.part0 uncore io Write request of up to a 64 byte transaction is made by IIO Part0 to Memory event=0x84,ch_mask=1,fc_mask=7,umask=1  01    Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.mem_write.part1 uncore io Write request of up to a 64 byte transaction is made by IIO Part1 to Memory event=0x84,ch_mask=2,fc_mask=7,umask=1  01    Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.mem_write.part2 uncore io Write request of up to a 64 byte transaction is made by IIO Part2 to Memory event=0x84,ch_mask=4,fc_mask=7,umask=1  01    Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.mem_write.part3 uncore io Write request of up to a 64 byte transaction is made by IIO Part3 to Memory event=0x84,ch_mask=8,fc_mask=7,umask=1  01    Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.mem_write.part4 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x10,fc_mask=7,umask=1  01    Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.mem_write.part5 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x20,fc_mask=7,umask=1  01    Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.mem_write.part6 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x40,fc_mask=7,umask=1  01    Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.mem_write.part7 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x80,fc_mask=7,umask=1  01    Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.peer_write.part0 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=1,fc_mask=7,umask=2  01    Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.peer_write.part1 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=2,fc_mask=7,umask=2  01    Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.peer_write.part2 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=4,fc_mask=7,umask=2  01    Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_of_cpu.peer_write.part3 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=8,fc_mask=7,umask=2  01    Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.peer_write.part4 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x10,fc_mask=7,umask=2  01    Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_of_cpu.peer_write.part5 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x20,fc_mask=7,umask=2  01    Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_of_cpu.peer_write.part6 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x40,fc_mask=7,umask=2  01    Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_of_cpu.peer_write.part7 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x80,fc_mask=7,umask=2  01    Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 uncore_m2pcie unc_m2p_clockticks uncore io M2P Clockticks event=1  01    Number of M2P clock cycles while the event is enabled unc_m2p_cms_clockticks uncore io CMS Clockticks event=0xc0  01     unc_m2p_egress_ordering.iv_snoopgo_dn uncore io Egress Blocking due to Ordering requirements : Down event=0xba,umask=4  01    Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m2p_egress_ordering.iv_snoopgo_up uncore io Egress Blocking due to Ordering requirements : Up event=0xba,umask=1  01    Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m2p_iio_credits_acquired.drs_0 uncore io M2PCIe IIO Credit Acquired : DRS event=0x33,umask=1  01    M2PCIe IIO Credit Acquired : DRS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class unc_m2p_iio_credits_acquired.drs_1 uncore io M2PCIe IIO Credit Acquired : DRS event=0x33,umask=2  01    M2PCIe IIO Credit Acquired : DRS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class unc_m2p_iio_credits_acquired.ncb_0 uncore io M2PCIe IIO Credit Acquired : NCB event=0x33,umask=4  01    M2PCIe IIO Credit Acquired : NCB : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class unc_m2p_iio_credits_acquired.ncb_1 uncore io M2PCIe IIO Credit Acquired : NCB event=0x33,umask=8  01    M2PCIe IIO Credit Acquired : NCB : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class unc_m2p_iio_credits_acquired.ncs_0 uncore io M2PCIe IIO Credit Acquired : NCS event=0x33,umask=0x10  01    M2PCIe IIO Credit Acquired : NCS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS message class unc_m2p_iio_credits_acquired.ncs_1 uncore io M2PCIe IIO Credit Acquired : NCS event=0x33,umask=0x20  01    M2PCIe IIO Credit Acquired : NCS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS message class unc_m2p_iio_credits_reject.drs uncore io M2PCIe IIO Failed to Acquire a Credit : DRS event=0x34,umask=8  01    M2PCIe IIO Failed to Acquire a Credit : DRS : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the DRS message class unc_m2p_iio_credits_reject.ncb uncore io M2PCIe IIO Failed to Acquire a Credit : NCB event=0x34,umask=0x10  01    M2PCIe IIO Failed to Acquire a Credit : NCB : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the NCB message class unc_m2p_iio_credits_reject.ncs uncore io M2PCIe IIO Failed to Acquire a Credit : NCS event=0x34,umask=0x20  01    M2PCIe IIO Failed to Acquire a Credit : NCS : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the NCS message class unc_m2p_iio_credits_used.drs_0 uncore io M2PCIe IIO Credits in Use : DRS to CMS Port 0 event=0x32,umask=1  01    M2PCIe IIO Credits in Use : DRS to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class unc_m2p_iio_credits_used.drs_1 uncore io M2PCIe IIO Credits in Use : DRS to CMS Port 1 event=0x32,umask=2  01    M2PCIe IIO Credits in Use : DRS to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class unc_m2p_iio_credits_used.ncb_0 uncore io M2PCIe IIO Credits in Use : NCB to CMS Port 0 event=0x32,umask=4  01    M2PCIe IIO Credits in Use : NCB to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class unc_m2p_iio_credits_used.ncb_1 uncore io M2PCIe IIO Credits in Use : NCB to CMS Port 1 event=0x32,umask=8  01    M2PCIe IIO Credits in Use : NCB to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class unc_m2p_iio_credits_used.ncs_0 uncore io M2PCIe IIO Credits in Use : NCS to CMS Port 0 event=0x32,umask=0x10  01    M2PCIe IIO Credits in Use : NCS to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS message class unc_m2p_iio_credits_used.ncs_1 uncore io M2PCIe IIO Credits in Use : NCS to CMS Port 1 event=0x32,umask=0x20  01    M2PCIe IIO Credits in Use : NCS to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS message class unc_m2p_local_ded_p2p_crd_taken_0.m2iosf0_ncb uncore io Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCB event=0x46,umask=1  01     unc_m2p_local_ded_p2p_crd_taken_0.m2iosf0_ncs uncore io Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCS event=0x46,umask=2  01     unc_m2p_local_ded_p2p_crd_taken_0.m2iosf1_ncb uncore io Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCB event=0x46,umask=4  01     unc_m2p_local_ded_p2p_crd_taken_0.m2iosf1_ncs uncore io Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCS event=0x46,umask=8  01     unc_m2p_local_ded_p2p_crd_taken_0.m2iosf2_ncb uncore io Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCB event=0x46,umask=0x10  01     unc_m2p_local_ded_p2p_crd_taken_0.m2iosf2_ncs uncore io Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCS event=0x46,umask=0x20  01     unc_m2p_local_ded_p2p_crd_taken_0.m2iosf3_ncb uncore io Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCB event=0x46,umask=0x40  01     unc_m2p_local_ded_p2p_crd_taken_0.m2iosf3_ncs uncore io Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCS event=0x46,umask=0x80  01     unc_m2p_local_ded_p2p_crd_taken_1.m2iosf4_ncb uncore io Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCB event=0x47,umask=1  01     unc_m2p_local_ded_p2p_crd_taken_1.m2iosf4_ncs uncore io Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCS event=0x47,umask=2  01     unc_m2p_local_ded_p2p_crd_taken_1.m2iosf5_ncb uncore io Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCB event=0x47,umask=4  01     unc_m2p_local_ded_p2p_crd_taken_1.m2iosf5_ncs uncore io Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCS event=0x47,umask=8  01     unc_m2p_local_p2p_ded_returned_0.ms2iosf0_ncb uncore io Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCB event=0x19,umask=1  01     unc_m2p_local_p2p_ded_returned_0.ms2iosf0_ncs uncore io Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCS event=0x19,umask=2  01     unc_m2p_local_p2p_ded_returned_0.ms2iosf1_ncb uncore io Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCB event=0x19,umask=4  01     unc_m2p_local_p2p_ded_returned_0.ms2iosf1_ncs uncore io Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCS event=0x19,umask=8  01     unc_m2p_local_p2p_ded_returned_0.ms2iosf2_ncb uncore io Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCB event=0x19,umask=0x10  01     unc_m2p_local_p2p_ded_returned_0.ms2iosf2_ncs uncore io Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCS event=0x19,umask=0x20  01     unc_m2p_local_p2p_ded_returned_0.ms2iosf3_ncb uncore io Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCB event=0x19,umask=0x40  01     unc_m2p_local_p2p_ded_returned_0.ms2iosf3_ncs uncore io Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCS event=0x19,umask=0x80  01     unc_m2p_local_p2p_ded_returned_1.ms2iosf4_ncb uncore io Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCB event=0x1a,umask=1  01     unc_m2p_local_p2p_ded_returned_1.ms2iosf4_ncs uncore io Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCS event=0x1a,umask=2  01     unc_m2p_local_p2p_ded_returned_1.ms2iosf5_ncb uncore io Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCB event=0x1a,umask=4  01     unc_m2p_local_p2p_ded_returned_1.ms2iosf5_ncs uncore io Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCS event=0x1a,umask=8  01     unc_m2p_local_p2p_shar_returned.agent_0 uncore io Local P2P Shared Credits Returned : Agent0 event=0x17,umask=1  01     unc_m2p_local_p2p_shar_returned.agent_1 uncore io Local P2P Shared Credits Returned : Agent1 event=0x17,umask=2  01     unc_m2p_local_p2p_shar_returned.agent_2 uncore io Local P2P Shared Credits Returned : Agent2 event=0x17,umask=4  01     unc_m2p_local_shar_p2p_crd_returned.agent_0 uncore io Local Shared P2P Credit Returned to credit ring : Agent0 event=0x44,umask=1  01     unc_m2p_local_shar_p2p_crd_returned.agent_1 uncore io Local Shared P2P Credit Returned to credit ring : Agent1 event=0x44,umask=2  01     unc_m2p_local_shar_p2p_crd_returned.agent_2 uncore io Local Shared P2P Credit Returned to credit ring : Agent2 event=0x44,umask=4  01     unc_m2p_local_shar_p2p_crd_returned.agent_3 uncore io Local Shared P2P Credit Returned to credit ring : Agent3 event=0x44,umask=8  01     unc_m2p_local_shar_p2p_crd_returned.agent_4 uncore io Local Shared P2P Credit Returned to credit ring : Agent4 event=0x44,umask=0x10  01     unc_m2p_local_shar_p2p_crd_returned.agent_5 uncore io Local Shared P2P Credit Returned to credit ring : Agent5 event=0x44,umask=0x20  01     unc_m2p_local_shar_p2p_crd_taken_0.m2iosf0_ncb uncore io Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCB event=0x40,umask=1  01     unc_m2p_local_shar_p2p_crd_taken_0.m2iosf0_ncs uncore io Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCS event=0x40,umask=2  01     unc_m2p_local_shar_p2p_crd_taken_0.m2iosf1_ncb uncore io Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCB event=0x40,umask=4  01     unc_m2p_local_shar_p2p_crd_taken_0.m2iosf1_ncs uncore io Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCS event=0x40,umask=8  01     unc_m2p_local_shar_p2p_crd_taken_0.m2iosf2_ncb uncore io Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCB event=0x40,umask=0x10  01     unc_m2p_local_shar_p2p_crd_taken_0.m2iosf2_ncs uncore io Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCS event=0x40,umask=0x20  01     unc_m2p_local_shar_p2p_crd_taken_0.m2iosf3_ncb uncore io Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCB event=0x40,umask=0x40  01     unc_m2p_local_shar_p2p_crd_taken_0.m2iosf3_ncs uncore io Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCS event=0x40,umask=0x80  01     unc_m2p_local_shar_p2p_crd_taken_1.m2iosf4_ncb uncore io Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCB event=0x41,umask=1  01     unc_m2p_local_shar_p2p_crd_taken_1.m2iosf4_ncs uncore io Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCS event=0x41,umask=2  01     unc_m2p_local_shar_p2p_crd_taken_1.m2iosf5_ncb uncore io Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCB event=0x41,umask=4  01     unc_m2p_local_shar_p2p_crd_taken_1.m2iosf5_ncs uncore io Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCS event=0x41,umask=8  01     unc_m2p_local_shar_p2p_crd_wait_0.m2iosf0_ncb uncore io Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCB event=0x4a,umask=1  01     unc_m2p_local_shar_p2p_crd_wait_0.m2iosf0_ncs uncore io Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCS event=0x4a,umask=2  01     unc_m2p_local_shar_p2p_crd_wait_0.m2iosf1_ncb uncore io Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCB event=0x4a,umask=4  01     unc_m2p_local_shar_p2p_crd_wait_0.m2iosf1_ncs uncore io Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCS event=0x4a,umask=8  01     unc_m2p_local_shar_p2p_crd_wait_0.m2iosf2_ncb uncore io Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCB event=0x4a,umask=0x10  01     unc_m2p_local_shar_p2p_crd_wait_0.m2iosf2_ncs uncore io Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCS event=0x4a,umask=0x20  01     unc_m2p_local_shar_p2p_crd_wait_0.m2iosf3_ncb uncore io Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCB event=0x4a,umask=0x40  01     unc_m2p_local_shar_p2p_crd_wait_0.m2iosf3_ncs uncore io Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCS event=0x4a,umask=0x80  01     unc_m2p_local_shar_p2p_crd_wait_1.m2iosf4_ncb uncore io Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCB event=0x4b,umask=1  01     unc_m2p_local_shar_p2p_crd_wait_1.m2iosf4_ncs uncore io Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCS event=0x4b,umask=2  01     unc_m2p_local_shar_p2p_crd_wait_1.m2iosf5_ncb uncore io Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCB event=0x4b,umask=4  01     unc_m2p_local_shar_p2p_crd_wait_1.m2iosf5_ncs uncore io Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCS event=0x4b,umask=8  01     unc_m2p_p2p_crd_occupancy.all uncore io P2P Credit Occupancy : All event=0x14,umask=0x10  01     unc_m2p_p2p_crd_occupancy.local_ncb uncore io P2P Credit Occupancy : Local NCB event=0x14,umask=1  01     unc_m2p_p2p_crd_occupancy.local_ncs uncore io P2P Credit Occupancy : Local NCS event=0x14,umask=2  01     unc_m2p_p2p_crd_occupancy.remote_ncb uncore io P2P Credit Occupancy : Remote NCB event=0x14,umask=4  01     unc_m2p_p2p_crd_occupancy.remote_ncs uncore io P2P Credit Occupancy : Remote NCS event=0x14,umask=8  01     unc_m2p_p2p_ded_received.all uncore io Dedicated Credits Received : All event=0x16,umask=0x10  01     unc_m2p_p2p_ded_received.local_ncb uncore io Dedicated Credits Received : Local NCB event=0x16,umask=1  01     unc_m2p_p2p_ded_received.local_ncs uncore io Dedicated Credits Received : Local NCS event=0x16,umask=2  01     unc_m2p_p2p_ded_received.remote_ncb uncore io Dedicated Credits Received : Remote NCB event=0x16,umask=4  01     unc_m2p_p2p_ded_received.remote_ncs uncore io Dedicated Credits Received : Remote NCS event=0x16,umask=8  01     unc_m2p_p2p_shar_received.all uncore io Shared Credits  Received : All event=0x15,umask=0x10  01     unc_m2p_p2p_shar_received.local_ncb uncore io Shared Credits  Received : Local NCB event=0x15,umask=1  01     unc_m2p_p2p_shar_received.local_ncs uncore io Shared Credits  Received : Local NCS event=0x15,umask=2  01     unc_m2p_p2p_shar_received.remote_ncb uncore io Shared Credits  Received : Remote NCB event=0x15,umask=4  01     unc_m2p_p2p_shar_received.remote_ncs uncore io Shared Credits  Received : Remote NCS event=0x15,umask=8  01     unc_m2p_remote_ded_p2p_crd_taken_0.upi0_drs uncore io Remote Dedicated P2P Credit Taken - 0 : UPI0 - DRS event=0x48,umask=1  01     unc_m2p_remote_ded_p2p_crd_taken_0.upi0_ncb uncore io Remote Dedicated P2P Credit Taken - 0 : UPI0 - NCB event=0x48,umask=2  01     unc_m2p_remote_ded_p2p_crd_taken_0.upi0_ncs uncore io Remote Dedicated P2P Credit Taken - 0 : UPI0 - NCS event=0x48,umask=4  01     unc_m2p_remote_ded_p2p_crd_taken_0.upi1_drs uncore io Remote Dedicated P2P Credit Taken - 0 : UPI1 - DRS event=0x48,umask=8  01     unc_m2p_remote_ded_p2p_crd_taken_0.upi1_ncb uncore io Remote Dedicated P2P Credit Taken - 0 : UPI1 - NCB event=0x48,umask=0x10  01     unc_m2p_remote_ded_p2p_crd_taken_0.upi1_ncs uncore io Remote Dedicated P2P Credit Taken - 0 : UPI1 - NCS event=0x48,umask=0x20  01     unc_m2p_remote_ded_p2p_crd_taken_1.upi2_drs uncore io Remote Dedicated P2P Credit Taken - 1 : UPI2 - DRS event=0x49,umask=1  01     unc_m2p_remote_ded_p2p_crd_taken_1.upi2_ncb uncore io Remote Dedicated P2P Credit Taken - 1 : UPI2 - NCB event=0x49,umask=2  01     unc_m2p_remote_ded_p2p_crd_taken_1.upi2_ncs uncore io Remote Dedicated P2P Credit Taken - 1 : UPI2 - NCS event=0x49,umask=4  01     unc_m2p_remote_p2p_ded_returned.upi0_ncb uncore io Remote P2P Dedicated Credits Returned : UPI0 - NCB event=0x1b,umask=1  01     unc_m2p_remote_p2p_ded_returned.upi0_ncs uncore io Remote P2P Dedicated Credits Returned : UPI0 - NCS event=0x1b,umask=2  01     unc_m2p_remote_p2p_ded_returned.upi1_ncb uncore io Remote P2P Dedicated Credits Returned : UPI1 - NCB event=0x1b,umask=4  01     unc_m2p_remote_p2p_ded_returned.upi1_ncs uncore io Remote P2P Dedicated Credits Returned : UPI1 - NCS event=0x1b,umask=8  01     unc_m2p_remote_p2p_ded_returned.upi2_ncb uncore io Remote P2P Dedicated Credits Returned : UPI2 - NCB event=0x1b,umask=0x10  01     unc_m2p_remote_p2p_ded_returned.upi2_ncs uncore io Remote P2P Dedicated Credits Returned : UPI2 - NCS event=0x1b,umask=0x20  01     unc_m2p_remote_p2p_shar_returned.agent_0 uncore io Remote P2P Shared Credits Returned : Agent0 event=0x18,umask=1  01     unc_m2p_remote_p2p_shar_returned.agent_1 uncore io Remote P2P Shared Credits Returned : Agent1 event=0x18,umask=2  01     unc_m2p_remote_p2p_shar_returned.agent_2 uncore io Remote P2P Shared Credits Returned : Agent2 event=0x18,umask=4  01     unc_m2p_remote_shar_p2p_crd_returned.agent_0 uncore io Remote Shared P2P Credit Returned to credit ring : Agent0 event=0x45,umask=1  01     unc_m2p_remote_shar_p2p_crd_returned.agent_1 uncore io Remote Shared P2P Credit Returned to credit ring : Agent1 event=0x45,umask=2  01     unc_m2p_remote_shar_p2p_crd_returned.agent_2 uncore io Remote Shared P2P Credit Returned to credit ring : Agent2 event=0x45,umask=4  01     unc_m2p_remote_shar_p2p_crd_taken_0.upi0_drs uncore io Remote Shared P2P Credit Taken - 0 : UPI0 - DRS event=0x42,umask=1  01     unc_m2p_remote_shar_p2p_crd_taken_0.upi0_ncb uncore io Remote Shared P2P Credit Taken - 0 : UPI0 - NCB event=0x42,umask=2  01     unc_m2p_remote_shar_p2p_crd_taken_0.upi0_ncs uncore io Remote Shared P2P Credit Taken - 0 : UPI0 - NCS event=0x42,umask=4  01     unc_m2p_remote_shar_p2p_crd_taken_0.upi1_drs uncore io Remote Shared P2P Credit Taken - 0 : UPI1 - DRS event=0x42,umask=8  01     unc_m2p_remote_shar_p2p_crd_taken_0.upi1_ncb uncore io Remote Shared P2P Credit Taken - 0 : UPI1 - NCB event=0x42,umask=0x10  01     unc_m2p_remote_shar_p2p_crd_taken_0.upi1_ncs uncore io Remote Shared P2P Credit Taken - 0 : UPI1 - NCS event=0x42,umask=0x20  01     unc_m2p_remote_shar_p2p_crd_taken_1.upi2_drs uncore io Remote Shared P2P Credit Taken - 1 : UPI2 - DRS event=0x43,umask=1  01     unc_m2p_remote_shar_p2p_crd_taken_1.upi2_ncb uncore io Remote Shared P2P Credit Taken - 1 : UPI2 - NCB event=0x43,umask=2  01     unc_m2p_remote_shar_p2p_crd_taken_1.upi2_ncs uncore io Remote Shared P2P Credit Taken - 1 : UPI2 - NCS event=0x43,umask=4  01     unc_m2p_remote_shar_p2p_crd_wait_0.upi0_drs uncore io Waiting on Remote Shared P2P Credit - 0 : UPI0 - DRS event=0x4c,umask=1  01     unc_m2p_remote_shar_p2p_crd_wait_0.upi0_ncb uncore io Waiting on Remote Shared P2P Credit - 0 : UPI0 - NCB event=0x4c,umask=2  01     unc_m2p_remote_shar_p2p_crd_wait_0.upi0_ncs uncore io Waiting on Remote Shared P2P Credit - 0 : UPI0 - NCS event=0x4c,umask=4  01     unc_m2p_remote_shar_p2p_crd_wait_0.upi1_drs uncore io Waiting on Remote Shared P2P Credit - 0 : UPI1 - DRS event=0x4c,umask=8  01     unc_m2p_remote_shar_p2p_crd_wait_0.upi1_ncb uncore io Waiting on Remote Shared P2P Credit - 0 : UPI1 - NCB event=0x4c,umask=0x10  01     unc_m2p_remote_shar_p2p_crd_wait_0.upi1_ncs uncore io Waiting on Remote Shared P2P Credit - 0 : UPI1 - NCS event=0x4c,umask=0x20  01     unc_m2p_remote_shar_p2p_crd_wait_1.upi2_drs uncore io Waiting on Remote Shared P2P Credit - 1 : UPI2 - DRS event=0x4d,umask=1  01     unc_m2p_remote_shar_p2p_crd_wait_1.upi2_ncb uncore io Waiting on Remote Shared P2P Credit - 1 : UPI2 - NCB event=0x4d,umask=2  01     unc_m2p_remote_shar_p2p_crd_wait_1.upi2_ncs uncore io Waiting on Remote Shared P2P Credit - 1 : UPI2 - NCS event=0x4d,umask=4  01     unc_m2p_rxc_cycles_ne.all uncore io Ingress (from CMS) Queue Cycles Not Empty event=0x10,umask=0x80  01    Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty unc_m2p_rxc_cycles_ne.cha_idi uncore io Ingress (from CMS) Queue Cycles Not Empty event=0x10,umask=1  01    Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty unc_m2p_rxc_cycles_ne.cha_ncb uncore io Ingress (from CMS) Queue Cycles Not Empty event=0x10,umask=2  01    Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty unc_m2p_rxc_cycles_ne.cha_ncs uncore io Ingress (from CMS) Queue Cycles Not Empty event=0x10,umask=4  01    Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty unc_m2p_rxc_cycles_ne.iio_ncb uncore io Ingress (from CMS) Queue Cycles Not Empty event=0x10,umask=0x20  01    Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty unc_m2p_rxc_cycles_ne.iio_ncs uncore io Ingress (from CMS) Queue Cycles Not Empty event=0x10,umask=0x40  01    Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty unc_m2p_rxc_cycles_ne.upi_ncb uncore io Ingress (from CMS) Queue Cycles Not Empty event=0x10,umask=8  01    Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty unc_m2p_rxc_cycles_ne.upi_ncs uncore io Ingress (from CMS) Queue Cycles Not Empty event=0x10,umask=0x10  01    Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty unc_m2p_rxc_inserts.all uncore io Ingress (from CMS) Queue Inserts event=0x11,umask=0x80  01    Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency unc_m2p_rxc_inserts.cha_idi uncore io Ingress (from CMS) Queue Inserts event=0x11,umask=1  01    Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency unc_m2p_rxc_inserts.cha_ncb uncore io Ingress (from CMS) Queue Inserts event=0x11,umask=2  01    Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency unc_m2p_rxc_inserts.cha_ncs uncore io Ingress (from CMS) Queue Inserts event=0x11,umask=4  01    Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency unc_m2p_rxc_inserts.iio_ncb uncore io Ingress (from CMS) Queue Inserts event=0x11,umask=0x20  01    Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency unc_m2p_rxc_inserts.iio_ncs uncore io Ingress (from CMS) Queue Inserts event=0x11,umask=0x40  01    Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency unc_m2p_rxc_inserts.upi_ncb uncore io Ingress (from CMS) Queue Inserts event=0x11,umask=8  01    Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency unc_m2p_rxc_inserts.upi_ncs uncore io Ingress (from CMS) Queue Inserts event=0x11,umask=0x10  01    Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency unc_m2p_txc_credits.pmm uncore io UNC_M2P_TxC_CREDITS.PMM event=0x2d,umask=2  01     unc_m2p_txc_credits.prq uncore io UNC_M2P_TxC_CREDITS.PRQ event=0x2d,umask=1  01     unc_m2p_txc_cycles_full.pmm_block_0 uncore io Egress (to CMS) Cycles Full event=0x25,umask=0x80  01    Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent unc_m2p_txc_cycles_full.pmm_block_1 uncore io Egress (to CMS) Cycles Full event=0x25,umask=8  01    Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent unc_m2p_txc_cycles_ne.pmm_distress_0 uncore io Egress (to CMS) Cycles Not Empty event=0x23,umask=0x80  01    Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple egress buffers can be tracked at a given time using multiple counters unc_m2p_txc_cycles_ne.pmm_distress_1 uncore io Egress (to CMS) Cycles Not Empty event=0x23,umask=8  01    Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple egress buffers can be tracked at a given time using multiple counters uncore_m2hbm unc_m2hbm_clockticks uncore memory Cycles - at UCLK event=1  01     unc_m2hbm_cms_clockticks uncore memory CMS Clockticks event=0xc0  01     unc_m2hbm_direct2core_not_taken_dirstate uncore memory Cycles when direct to core mode (which bypasses the CHA) was disabled event=0x17,umask=7  01     unc_m2hbm_direct2core_not_taken_dirstate.non_cisgress uncore memory Cycles when direct to core mode, which bypasses the CHA, was disabled : Non Cisgress event=0x17,umask=2  01    Counts the number of time non cisgress D2C was not honoured by egress due to directory state constraints unc_m2hbm_direct2core_not_taken_notforked uncore memory Counts the time when FM didn't do d2c for fill reads (cross tile case) event=0x4a  01     unc_m2hbm_direct2core_txn_override uncore memory Number of reads in which direct to core transaction were overridden event=0x18,umask=3  01     unc_m2hbm_direct2core_txn_override.cisgress uncore memory Number of reads in which direct to core transaction was overridden : Cisgress event=0x18,umask=2  01     unc_m2hbm_direct2upi_not_taken_credits uncore memory Number of reads in which direct to Intel UPI transactions were overridden event=0x1b,umask=7  01     unc_m2hbm_direct2upi_not_taken_dirstate uncore memory Cycles when direct to Intel UPI was disabled event=0x1a,umask=7  01     unc_m2hbm_direct2upi_not_taken_dirstate.cisgress uncore memory Cycles when Direct2UPI was Disabled : Cisgress D2U Ignored event=0x1a,umask=4  01    Counts cisgress d2K that was not honored due to directory constraints unc_m2hbm_direct2upi_not_taken_dirstate.egress uncore memory Cycles when Direct2UPI was Disabled : Egress Ignored D2U event=0x1a,umask=1  01    Counts the number of time D2K was not honoured by egress due to directory state constraints unc_m2hbm_direct2upi_not_taken_dirstate.non_cisgress uncore memory Cycles when Direct2UPI was Disabled : Non Cisgress D2U Ignored event=0x1a,umask=2  01    Counts non cisgress d2K that was not honored due to directory constraints unc_m2hbm_direct2upi_txn_override uncore memory Number of reads that a message sent direct2 Intel UPI was overridden event=0x1c,umask=3  01     unc_m2hbm_direct2upi_txn_override.cisgress uncore memory Number of times a direct to UPI transaction was overridden event=0x1c,umask=2  01     unc_m2hbm_directory_hit.clean_a uncore memory Directory Hit : On NonDirty Line in A State event=0x1d,umask=0x80  01     unc_m2hbm_directory_hit.clean_i uncore memory Directory Hit : On NonDirty Line in I State event=0x1d,umask=0x10  01     unc_m2hbm_directory_hit.clean_p uncore memory Directory Hit : On NonDirty Line in L State event=0x1d,umask=0x40  01     unc_m2hbm_directory_hit.clean_s uncore memory Directory Hit : On NonDirty Line in S State event=0x1d,umask=0x20  01     unc_m2hbm_directory_hit.dirty_a uncore memory Directory Hit : On Dirty Line in A State event=0x1d,umask=8  01     unc_m2hbm_directory_hit.dirty_i uncore memory Directory Hit : On Dirty Line in I State event=0x1d,umask=1  01     unc_m2hbm_directory_hit.dirty_p uncore memory Directory Hit : On Dirty Line in L State event=0x1d,umask=4  01     unc_m2hbm_directory_hit.dirty_s uncore memory Directory Hit : On Dirty Line in S State event=0x1d,umask=2  01     unc_m2hbm_directory_lookup.any uncore memory Multi-socket cacheline Directory lookups (any state found) event=0x20,umask=1  01    Counts the number of hit data returns to egress with any directory to non persistent memory unc_m2hbm_directory_lookup.state_a uncore memory Multi-socket cacheline Directory lookups (cacheline found in A state) event=0x20,umask=8  01    Counts the number of hit data returns to egress with directory A to non persistent memory unc_m2hbm_directory_lookup.state_i uncore memory Multi-socket cacheline Directory lookup (cacheline found in I state) event=0x20,umask=2  01    Counts the number of hit data returns to egress with directory I to non persistent memory unc_m2hbm_directory_lookup.state_s uncore memory Multi-socket cacheline Directory lookup (cacheline found in S state) event=0x20,umask=4  01    Counts the number of hit data returns to egress with directory S to non persistent memory unc_m2hbm_directory_miss.clean_a uncore memory Directory Miss : On NonDirty Line in A State event=0x1e,umask=0x80  01     unc_m2hbm_directory_miss.clean_i uncore memory Directory Miss : On NonDirty Line in I State event=0x1e,umask=0x10  01     unc_m2hbm_directory_miss.clean_p uncore memory Directory Miss : On NonDirty Line in L State event=0x1e,umask=0x40  01     unc_m2hbm_directory_miss.clean_s uncore memory Directory Miss : On NonDirty Line in S State event=0x1e,umask=0x20  01     unc_m2hbm_directory_miss.dirty_a uncore memory Directory Miss : On Dirty Line in A State event=0x1e,umask=8  01     unc_m2hbm_directory_miss.dirty_i uncore memory Directory Miss : On Dirty Line in I State event=0x1e,umask=1  01     unc_m2hbm_directory_miss.dirty_p uncore memory Directory Miss : On Dirty Line in L State event=0x1e,umask=4  01     unc_m2hbm_directory_miss.dirty_s uncore memory Directory Miss : On Dirty Line in S State event=0x1e,umask=2  01     unc_m2hbm_directory_update.a2i uncore memory Multi-socket cacheline Directory update from A to I event=0x21,umask=0x320  01     unc_m2hbm_directory_update.a2s uncore memory Multi-socket cacheline Directory update from A to S event=0x21,umask=0x340  01     unc_m2hbm_directory_update.any uncore memory Multi-socket cacheline Directory update from/to Any state event=0x21,umask=0x301  01     unc_m2hbm_directory_update.a_to_i_hit_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,umask=0x120  01    Counts 1lm or 2lm hit  data returns that would result in directory update from A to I to non persistent memory unc_m2hbm_directory_update.a_to_i_miss_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,umask=0x220  01    Counts 2lm miss  data returns that would result in directory update from A to I to non persistent memory unc_m2hbm_directory_update.a_to_s_hit_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,umask=0x140  01    Counts 1lm or 2lm hit  data returns that would result in directory update from A to S to non persistent memory unc_m2hbm_directory_update.a_to_s_miss_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,umask=0x240  01    Counts 2lm miss  data returns that would result in directory update from A to S to non persistent memory unc_m2hbm_directory_update.hit_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,umask=0x101  01    Counts any 1lm or 2lm hit data return that would result in directory update to non persistent memory unc_m2hbm_directory_update.i2a uncore memory Multi-socket cacheline Directory update from I to A event=0x21,umask=0x304  01     unc_m2hbm_directory_update.i2s uncore memory Multi-socket cacheline Directory update from I to S event=0x21,umask=0x302  01     unc_m2hbm_directory_update.i_to_a_hit_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,umask=0x104  01    Counts 1lm or 2lm hit  data returns that would result in directory update from I to A to non persistent memory unc_m2hbm_directory_update.i_to_a_miss_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,umask=0x204  01    Counts 2lm miss  data returns that would result in directory update from I to A to non persistent memory unc_m2hbm_directory_update.i_to_s_hit_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,umask=0x102  01    Counts 1lm or 2lm hit  data returns that would result in directory update from I to S to non persistent memory unc_m2hbm_directory_update.i_to_s_miss_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,umask=0x202  01    Counts  2lm miss  data returns that would result in directory update from I to S to non persistent memory unc_m2hbm_directory_update.miss_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,umask=0x201  01    Counts any 2lm miss data return that would result in directory update to non persistent memory unc_m2hbm_directory_update.s2a uncore memory Multi-socket cacheline Directory update from S to A event=0x21,umask=0x310  01     unc_m2hbm_directory_update.s2i uncore memory Multi-socket cacheline Directory update from S to I event=0x21,umask=0x308  01     unc_m2hbm_directory_update.s_to_a_hit_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,umask=0x110  01    Counts 1lm or 2lm hit  data returns that would result in directory update from S to A to non persistent memory unc_m2hbm_directory_update.s_to_a_miss_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,umask=0x210  01    Counts 2lm miss  data returns that would result in directory update from S to A to non persistent memory unc_m2hbm_directory_update.s_to_i_hit_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,umask=0x108  01    Counts 1lm or 2lm hit  data returns that would result in directory update from S to I to non persistent memory unc_m2hbm_directory_update.s_to_i_miss_non_pmm uncore memory Multi-socket cacheline Directory Updates event=0x21,umask=0x208  01    Counts 2lm miss  data returns that would result in directory update from S to I to non persistent memory unc_m2hbm_distress.ad uncore memory Count distress signalled on AkAd cmp message event=0x67,umask=0x20  01     unc_m2hbm_distress.all uncore memory Count distress signalled on any packet type event=0x67,umask=1  01     unc_m2hbm_distress.bl_cmp uncore memory Count distress signalled on Bl Cmp message event=0x67,umask=0x40  01     unc_m2hbm_distress.crosstile_nmwr uncore memory Count distress signalled on NM fill write message event=0x67,umask=0x10  01     unc_m2hbm_distress.d2cha uncore memory Count distress signalled on D2Cha message event=0x67,umask=8  01     unc_m2hbm_distress.d2core uncore memory Count distress signalled on D2c message event=0x67,umask=2  01     unc_m2hbm_distress.d2upi uncore memory Count distress signalled on D2k message event=0x67,umask=4  01     unc_m2hbm_egress_ordering.iv_snoopgo_dn uncore memory Egress Blocking due to Ordering requirements : Down event=0xba,umask=0x80000004  01    Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m2hbm_egress_ordering.iv_snoopgo_up uncore memory Egress Blocking due to Ordering requirements : Up event=0xba,umask=0x80000001  01    Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m2hbm_igr_starve_winner.mask7 uncore memory Count when Starve Glocab counter is at 7 event=0x44,umask=0x80  01     unc_m2hbm_imc_reads.all uncore memory Reads to iMC issued event=0x24,umask=0x304  01     unc_m2hbm_imc_reads.ch0.all uncore memory UNC_M2HBM_IMC_READS.CH0.ALL event=0x24,umask=0x104  01     unc_m2hbm_imc_reads.ch0.normal uncore memory UNC_M2HBM_IMC_READS.CH0.NORMAL event=0x24,umask=0x101  01     unc_m2hbm_imc_reads.ch0_all uncore memory UNC_M2HBM_IMC_READS.CH0_ALL event=0x24,umask=0x104  01     unc_m2hbm_imc_reads.ch0_from_tgr uncore memory UNC_M2HBM_IMC_READS.CH0_FROM_TGR event=0x24,umask=0x140  01     unc_m2hbm_imc_reads.ch0_isoch uncore memory Critical Priority - Ch0 event=0x24,umask=0x102  01     unc_m2hbm_imc_reads.ch0_normal uncore memory UNC_M2HBM_IMC_READS.CH0_NORMAL event=0x24,umask=0x101  01     unc_m2hbm_imc_reads.ch1.all uncore memory UNC_M2HBM_IMC_READS.CH1.ALL event=0x24,umask=0x204  01     unc_m2hbm_imc_reads.ch1.normal uncore memory UNC_M2HBM_IMC_READS.CH1.NORMAL event=0x24,umask=0x201  01     unc_m2hbm_imc_reads.ch1_all uncore memory UNC_M2HBM_IMC_READS.CH1_ALL event=0x24,umask=0x204  01     unc_m2hbm_imc_reads.ch1_from_tgr uncore memory From TGR - Ch1 event=0x24,umask=0x240  01     unc_m2hbm_imc_reads.ch1_isoch uncore memory Critical Priority - Ch1 event=0x24,umask=0x202  01     unc_m2hbm_imc_reads.ch1_normal uncore memory UNC_M2HBM_IMC_READS.CH1_NORMAL event=0x24,umask=0x201  01     unc_m2hbm_imc_reads.from_tgr uncore memory From TGR - All Channels event=0x24,umask=0x340  01     unc_m2hbm_imc_reads.isoch uncore memory Critical Priority - All Channels event=0x24,umask=0x302  01     unc_m2hbm_imc_reads.normal uncore memory UNC_M2HBM_IMC_READS.NORMAL event=0x24,umask=0x301  01     unc_m2hbm_imc_writes.all uncore memory All Writes - All Channels event=0x25,umask=0x1810  01     unc_m2hbm_imc_writes.ch0.all uncore memory UNC_M2HBM_IMC_WRITES.CH0.ALL event=0x25,umask=0x810  01     unc_m2hbm_imc_writes.ch0.full uncore memory UNC_M2HBM_IMC_WRITES.CH0.FULL event=0x25,umask=0x801  01     unc_m2hbm_imc_writes.ch0.partial uncore memory UNC_M2HBM_IMC_WRITES.CH0.PARTIAL event=0x25,umask=0x802  01     unc_m2hbm_imc_writes.ch0_all uncore memory UNC_M2HBM_IMC_WRITES.CH0_ALL event=0x25,umask=0x810  01     unc_m2hbm_imc_writes.ch0_from_tgr uncore memory From TGR - Ch0 event=0x25  01     unc_m2hbm_imc_writes.ch0_full uncore memory UNC_M2HBM_IMC_WRITES.CH0_FULL event=0x25,umask=0x801  01     unc_m2hbm_imc_writes.ch0_full_isoch uncore memory ISOCH Full Line - Ch0 event=0x25,umask=0x804  01     unc_m2hbm_imc_writes.ch0_ni uncore memory Non-Inclusive - Ch0 event=0x25  01     unc_m2hbm_imc_writes.ch0_ni_miss uncore memory Non-Inclusive Miss - Ch0 event=0x25  01     unc_m2hbm_imc_writes.ch0_partial uncore memory UNC_M2HBM_IMC_WRITES.CH0_PARTIAL event=0x25,umask=0x802  01     unc_m2hbm_imc_writes.ch0_partial_isoch uncore memory ISOCH Partial - Ch0 event=0x25,umask=0x808  01     unc_m2hbm_imc_writes.ch1.all uncore memory All Writes - Ch1 event=0x25,umask=0x1010  01     unc_m2hbm_imc_writes.ch1.full uncore memory Full Line Non-ISOCH - Ch1 event=0x25,umask=0x1001  01     unc_m2hbm_imc_writes.ch1.partial uncore memory Partial Non-ISOCH - Ch1 event=0x25,umask=0x1002  01     unc_m2hbm_imc_writes.ch1_all uncore memory All Writes - Ch1 event=0x25,umask=0x1010  01     unc_m2hbm_imc_writes.ch1_from_tgr uncore memory From TGR - Ch1 event=0x25  01     unc_m2hbm_imc_writes.ch1_full uncore memory Full Line Non-ISOCH - Ch1 event=0x25,umask=0x1001  01     unc_m2hbm_imc_writes.ch1_full_isoch uncore memory ISOCH Full Line - Ch1 event=0x25,umask=0x1004  01     unc_m2hbm_imc_writes.ch1_ni uncore memory Non-Inclusive - Ch1 event=0x25  01     unc_m2hbm_imc_writes.ch1_ni_miss uncore memory Non-Inclusive Miss - Ch1 event=0x25  01     unc_m2hbm_imc_writes.ch1_partial uncore memory Partial Non-ISOCH - Ch1 event=0x25,umask=0x1002  01     unc_m2hbm_imc_writes.ch1_partial_isoch uncore memory ISOCH Partial - Ch1 event=0x25,umask=0x1008  01     unc_m2hbm_imc_writes.from_tgr uncore memory From TGR - All Channels event=0x25  01     unc_m2hbm_imc_writes.full uncore memory Full Non-ISOCH - All Channels event=0x25,umask=0x1801  01     unc_m2hbm_imc_writes.full_isoch uncore memory ISOCH Full Line - All Channels event=0x25,umask=0x1804  01     unc_m2hbm_imc_writes.ni uncore memory Non-Inclusive - All Channels event=0x25  01     unc_m2hbm_imc_writes.ni_miss uncore memory Non-Inclusive Miss - All Channels event=0x25  01     unc_m2hbm_imc_writes.partial uncore memory Partial Non-ISOCH - All Channels event=0x25,umask=0x1802  01     unc_m2hbm_imc_writes.partial_isoch uncore memory ISOCH Partial - All Channels event=0x25,umask=0x1808  01     unc_m2hbm_prefcam_cis_drops uncore memory UNC_M2HBM_PREFCAM_CIS_DROPS event=0x5c  01     unc_m2hbm_prefcam_demand_drops.ch0_upi uncore memory Data Prefetches Dropped event=0x58,umask=2  01     unc_m2hbm_prefcam_demand_drops.ch0_xpt uncore memory Data Prefetches Dropped event=0x58,umask=1  01     unc_m2hbm_prefcam_demand_drops.ch1_upi uncore memory Data Prefetches Dropped event=0x58,umask=8  01     unc_m2hbm_prefcam_demand_drops.ch1_xpt uncore memory Data Prefetches Dropped event=0x58,umask=4  01     unc_m2hbm_prefcam_demand_drops.upi_allch uncore memory Data Prefetches Dropped : UPI - All Channels event=0x58,umask=0xa  01     unc_m2hbm_prefcam_demand_drops.xpt_allch uncore memory Data Prefetches Dropped event=0x58,umask=5  01     unc_m2hbm_prefcam_demand_merge.upi_allch uncore memory : UPI - All Channels event=0x5d,umask=0xa  01     unc_m2hbm_prefcam_demand_merge.xpt_allch uncore memory : XPT - All Channels event=0x5d,umask=5  01     unc_m2hbm_prefcam_demand_no_merge.rd_merged uncore memory Demands Not Merged with CAMed Prefetches event=0x5e,umask=0x40  01     unc_m2hbm_prefcam_demand_no_merge.wr_merged uncore memory Demands Not Merged with CAMed Prefetches event=0x5e,umask=0x20  01     unc_m2hbm_prefcam_demand_no_merge.wr_squashed uncore memory Demands Not Merged with CAMed Prefetches event=0x5e,umask=0x10  01     unc_m2hbm_prefcam_inserts.ch0_upi uncore memory Prefetch CAM Inserts : UPI - Ch 0 event=0x56,umask=2  01     unc_m2hbm_prefcam_inserts.ch0_xpt uncore memory Prefetch CAM Inserts : XPT - Ch 0 event=0x56,umask=1  01     unc_m2hbm_prefcam_inserts.ch1_upi uncore memory Prefetch CAM Inserts : UPI - Ch 1 event=0x56,umask=8  01     unc_m2hbm_prefcam_inserts.ch1_xpt uncore memory Prefetch CAM Inserts : XPT - Ch 1 event=0x56,umask=4  01     unc_m2hbm_prefcam_inserts.upi_allch uncore memory Prefetch CAM Inserts : UPI - All Channels event=0x56,umask=0xa  01     unc_m2hbm_prefcam_inserts.xpt_allch uncore memory Prefetch CAM Inserts : XPT - All Channels event=0x56,umask=5  01    Prefetch CAM Inserts : XPT -All Channels unc_m2hbm_prefcam_occupancy.allch uncore memory Prefetch CAM Occupancy : All Channels event=0x54,umask=3  01     unc_m2hbm_prefcam_occupancy.ch0 uncore memory Prefetch CAM Occupancy : Channel 0 event=0x54,umask=1  01     unc_m2hbm_prefcam_occupancy.ch1 uncore memory Prefetch CAM Occupancy : Channel 1 event=0x54,umask=2  01     unc_m2hbm_prefcam_resp_miss.allch uncore memory All Channels event=0x5f,umask=3  01     unc_m2hbm_prefcam_resp_miss.ch0 uncore memory : Channel 0 event=0x5f,umask=1  01     unc_m2hbm_prefcam_resp_miss.ch1 uncore memory : Channel 1 event=0x5f,umask=2  01     unc_m2hbm_prefcam_rxc_deallocs.1lm_posted uncore memory UNC_M2HBM_PREFCAM_RxC_DEALLOCS.1LM_POSTED event=0x62,umask=2  01     unc_m2hbm_prefcam_rxc_deallocs.cis uncore memory UNC_M2HBM_PREFCAM_RxC_DEALLOCS.CIS event=0x62,umask=8  01     unc_m2hbm_prefcam_rxc_deallocs.squashed uncore memory UNC_M2HBM_PREFCAM_RxC_DEALLOCS.SQUASHED event=0x62,umask=1  01     unc_m2hbm_prefcam_rxc_occupancy uncore memory UNC_M2HBM_PREFCAM_RxC_OCCUPANCY event=0x60  01     unc_m2hbm_rxc_ad.inserts uncore memory AD Ingress (from CMS) : AD Ingress (from CMS) Allocations event=2,umask=1  01     unc_m2hbm_rxc_ad_inserts uncore memory AD Ingress (from CMS) : AD Ingress (from CMS) Allocations event=2,umask=1  01     unc_m2hbm_rxc_ad_occupancy uncore memory AD Ingress (from CMS) Occupancy event=3  01     unc_m2hbm_rxc_bl.inserts uncore memory BL Ingress (from CMS) : BL Ingress (from CMS) Allocations event=4,umask=1  01    Counts anytime a BL packet is added to Ingress unc_m2hbm_rxc_bl_inserts uncore memory BL Ingress (from CMS) : BL Ingress (from CMS) Allocations event=4,umask=1  01    Counts anytime a BL packet is added to Ingress unc_m2hbm_rxc_bl_occupancy uncore memory BL Ingress (from CMS) Occupancy event=5  01     unc_m2hbm_tgr_ad_credits uncore memory Number AD Ingress Credits event=0x2e  01     unc_m2hbm_tgr_bl_credits uncore memory Number BL Ingress Credits event=0x2f  01     unc_m2hbm_tracker_inserts.ch0 uncore memory Tracker Inserts : Channel 0 event=0x32,umask=0x104  01     unc_m2hbm_tracker_inserts.ch1 uncore memory Tracker Inserts : Channel 1 event=0x32,umask=0x204  01     unc_m2hbm_tracker_occupancy.ch0 uncore memory Tracker Occupancy : Channel 0 event=0x33,umask=1  01     unc_m2hbm_tracker_occupancy.ch1 uncore memory Tracker Occupancy : Channel 1 event=0x33,umask=2  01     unc_m2hbm_txc_ad.inserts uncore memory AD Egress (to CMS) : AD Egress (to CMS) Allocations event=6,umask=1  01    Counts anytime a AD packet is added to Egress unc_m2hbm_txc_ad_inserts uncore memory AD Egress (to CMS) : AD Egress (to CMS) Allocations event=6,umask=1  01    Counts anytime a AD packet is added to Egress unc_m2hbm_txc_ad_occupancy uncore memory AD Egress (to CMS) Occupancy event=7  01     unc_m2hbm_txc_bl.inserts_cms0 uncore memory BL Egress (to CMS) : Inserts - CMS0 - Near Side event=0xe,umask=0x101  01    Counts the number of BL transactions to CMS add port 0 unc_m2hbm_txc_bl.inserts_cms1 uncore memory BL Egress (to CMS) : Inserts - CMS1 - Far Side event=0xe,umask=0x201  01    Counts the number of BL transactions to CMS add port 1 unc_m2hbm_txc_bl_occupancy.all uncore memory BL Egress (to CMS) Occupancy : All event=0xf,umask=3  01     unc_m2hbm_txc_bl_occupancy.cms0 uncore memory BL Egress (to CMS) Occupancy : Common Mesh Stop - Near Side event=0xf,umask=1  01     unc_m2hbm_txc_bl_occupancy.cms1 uncore memory BL Egress (to CMS) Occupancy : Common Mesh Stop - Far Side event=0xf,umask=2  01     unc_m2hbm_wpq_flush.ch0 uncore memory WPQ Flush : Channel 0 event=0x42,umask=1  01     unc_m2hbm_wpq_flush.ch1 uncore memory WPQ Flush : Channel 1 event=0x42,umask=2  01     unc_m2hbm_wpq_no_reg_crd.chn0 uncore memory M2M and iMC WPQ Cycles w/Credits - Regular : Channel 0 event=0x37,umask=1  01     unc_m2hbm_wpq_no_reg_crd.chn1 uncore memory M2M and iMC WPQ Cycles w/Credits - Regular : Channel 1 event=0x37,umask=2  01     unc_m2hbm_wpq_no_spec_crd.chn0 uncore memory M2M and iMC WPQ Cycles w/Credits - Special : Channel 0 event=0x38,umask=1  01     unc_m2hbm_wpq_no_spec_crd.chn1 uncore memory M2M and iMC WPQ Cycles w/Credits - Special : Channel 1 event=0x38,umask=2  01     unc_m2hbm_wr_tracker_inserts.ch0 uncore memory Write Tracker Inserts : Channel 0 event=0x40,umask=1  01     unc_m2hbm_wr_tracker_inserts.ch1 uncore memory Write Tracker Inserts : Channel 1 event=0x40,umask=2  01     unc_m2hbm_wr_tracker_nonposted_inserts.ch0 uncore memory Write Tracker Non-Posted Inserts : Channel 0 event=0x4d,umask=1  01     unc_m2hbm_wr_tracker_nonposted_inserts.ch1 uncore memory Write Tracker Non-Posted Inserts : Channel 1 event=0x4d,umask=2  01     unc_m2hbm_wr_tracker_nonposted_occupancy.ch0 uncore memory Write Tracker Non-Posted Occupancy : Channel 0 event=0x4c,umask=1  01     unc_m2hbm_wr_tracker_nonposted_occupancy.ch1 uncore memory Write Tracker Non-Posted Occupancy : Channel 1 event=0x4c,umask=2  01     unc_m2hbm_wr_tracker_posted_inserts.ch0 uncore memory Write Tracker Posted Inserts : Channel 0 event=0x48,umask=1  01     unc_m2hbm_wr_tracker_posted_inserts.ch1 uncore memory Write Tracker Posted Inserts : Channel 1 event=0x48,umask=2  01     unc_m2hbm_wr_tracker_posted_occupancy.ch0 uncore memory Write Tracker Posted Occupancy : Channel 0 event=0x47,umask=1  01     unc_m2hbm_wr_tracker_posted_occupancy.ch1 uncore memory Write Tracker Posted Occupancy : Channel 1 event=0x47,umask=2  01     uncore_mchbm unc_mchbm_act_count.all uncore memory Activate due to read, write, underfill, or bypass event=2,umask=0xff  01    Counts the number of HBM Activate commands sent on this channel.  Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_mchbm_act_count.rd uncore memory Activate due to read event=2,umask=0x11  01    Counts the number of HBM Activate commands sent on this channel.  Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_mchbm_act_count.rd_pch0 uncore memory HBM Activate Count : Activate due to Read in PCH0 event=2,umask=1  01    Counts the number of HBM Activate commands sent on this channel.  Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_mchbm_act_count.rd_pch1 uncore memory HBM Activate Count : Activate due to Read in PCH1 event=2,umask=0x10  01    Counts the number of HBM Activate commands sent on this channel.  Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_mchbm_act_count.ufill uncore memory HBM Activate Count : Underfill Read transaction on Page Empty or Page Miss event=2,umask=0x44  01    Counts the number of HBM Activate commands sent on this channel.  Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_mchbm_act_count.ufill_pch0 uncore memory HBM Activate Count event=2,umask=4  01    Counts the number of HBM Activate commands sent on this channel.  Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_mchbm_act_count.ufill_pch1 uncore memory HBM Activate Count event=2,umask=0x40  01    Counts the number of HBM Activate commands sent on this channel.  Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_mchbm_act_count.wr uncore memory Activate due to write event=2,umask=0x22  01    Counts the number of HBM Activate commands sent on this channel.  Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_mchbm_act_count.wr_pch0 uncore memory HBM Activate Count : Activate due to Write in PCH0 event=2,umask=2  01    Counts the number of HBM Activate commands sent on this channel.  Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_mchbm_act_count.wr_pch1 uncore memory HBM Activate Count : Activate due to Write in PCH1 event=2,umask=0x20  01    Counts the number of HBM Activate commands sent on this channel.  Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_mchbm_cas_count.all uncore memory All CAS commands issued event=5,umask=0xff  01     unc_mchbm_cas_count.pch0 uncore memory Pseudo Channel 0 event=5,umask=0x40  01    HBM RD_CAS and WR_CAS Commands unc_mchbm_cas_count.pch1 uncore memory Pseudo Channel 1 event=5,umask=0x80  01    HBM RD_CAS and WR_CAS Commands unc_mchbm_cas_count.rd uncore memory Read CAS commands issued (regular and underfill) event=5,umask=0xcf  01     unc_mchbm_cas_count.rd_pre_reg uncore memory Regular read CAS commands with precharge event=5,umask=0xc2  01     unc_mchbm_cas_count.rd_pre_underfill uncore memory Underfill read CAS commands with precharge event=5,umask=0xc8  01     unc_mchbm_cas_count.rd_reg uncore memory Regular read CAS commands issued (does not include underfills) event=5,umask=0xc1  01     unc_mchbm_cas_count.rd_underfill uncore memory Underfill read CAS commands issued event=5,umask=0xc4  01     unc_mchbm_cas_count.wr uncore memory Write CAS commands issued event=5,umask=0xf0  01     unc_mchbm_cas_count.wr_nonpre uncore memory HBM RD_CAS and WR_CAS Commands. : HBM WR_CAS commands w/o auto-pre event=5,umask=0xd0  01     unc_mchbm_cas_count.wr_pre uncore memory Write CAS commands with precharge event=5,umask=0xe0  01     unc_mchbm_cas_issued_req_len.pch0 uncore memory Pseudo Channel 0 event=6,umask=0x40  01     unc_mchbm_cas_issued_req_len.pch1 uncore memory Pseudo Channel 1 event=6,umask=0x80  01     unc_mchbm_cas_issued_req_len.rd_32b uncore memory Read CAS Command in Interleaved Mode (32B) event=6,umask=0xc8  01     unc_mchbm_cas_issued_req_len.rd_64b uncore memory Read CAS Command in Regular Mode (64B) in Pseudochannel 0 event=6,umask=0xc1  01     unc_mchbm_cas_issued_req_len.rd_ufill_32b uncore memory Underfill Read CAS Command in Interleaved Mode (32B) event=6,umask=0xd0  01     unc_mchbm_cas_issued_req_len.rd_ufill_64b uncore memory Underfill Read CAS Command in Regular Mode (64B) in Pseudochannel 1 event=6,umask=0xc2  01     unc_mchbm_cas_issued_req_len.wr_32b uncore memory Write CAS Command in Interleaved Mode (32B) event=6,umask=0xe0  01     unc_mchbm_cas_issued_req_len.wr_64b uncore memory Write CAS Command in Regular Mode (64B) in Pseudochannel 0 event=6,umask=0xc4  01     unc_mchbm_clockticks uncore memory IMC Clockticks at DCLK frequency event=1,umask=1  01     unc_mchbm_ecc_correctable_errors uncore memory ECC Correctable Errors event=9  01    ECC Correctable Errors.  Counts the number of ECC errors detected and corrected by the iMC on this channel.  This counter is only useful with ECC devices.  This count will increment one time for each correction regardless of the number of bits corrected.  The iMC can correct up to 4 bit errors in independent channel mode and 8 bit errors in lockstep mode unc_mchbm_hbm_preall.pch0 uncore memory HBM Precharge All Commands event=0x44,umask=1  01    Counts the number of times that the precharge all command was sent unc_mchbm_hbm_preall.pch1 uncore memory HBM Precharge All Commands event=0x44,umask=2  01    Counts the number of times that the precharge all command was sent unc_mchbm_hbm_pre_all uncore memory All Precharge Commands event=0x44,umask=3  01    Precharge All Commands: Counts the number of times that the precharge all command was sent unc_mchbm_hclockticks uncore memory IMC Clockticks at HCLK frequency event=1  01     unc_mchbm_pre_count.all uncore memory All precharge events event=3,umask=0xff  01    Counts the number of HBM Precharge commands sent on this channel unc_mchbm_pre_count.pgt uncore memory Precharge from MC page table event=3,umask=0x88  01    Counts the number of HBM Precharge commands sent on this channel unc_mchbm_pre_count.pgt_pch0 uncore memory HBM Precharge commands. : Precharges from Page Table event=3,umask=8  01    Counts the number of HBM Precharge commands sent on this channel. : Equivalent to PAGE_EMPTY unc_mchbm_pre_count.pgt_pch1 uncore memory HBM Precharge commands event=3,umask=0x80  01    Counts the number of HBM Precharge commands sent on this channel unc_mchbm_pre_count.rd uncore memory Precharge due to read on page miss event=3,umask=0x11  01    Counts the number of HBM Precharge commands sent on this channel unc_mchbm_pre_count.rd_pch0 uncore memory HBM Precharge commands. : Precharge due to read event=3,umask=1  01    Counts the number of HBM Precharge commands sent on this channel. : Precharge from read bank scheduler unc_mchbm_pre_count.rd_pch1 uncore memory HBM Precharge commands event=3,umask=0x10  01    Counts the number of HBM Precharge commands sent on this channel unc_mchbm_pre_count.ufill uncore memory HBM Precharge commands event=3,umask=0x44  01    Counts the number of HBM Precharge commands sent on this channel unc_mchbm_pre_count.ufill_pch0 uncore memory HBM Precharge commands event=3,umask=4  01    Counts the number of HBM Precharge commands sent on this channel unc_mchbm_pre_count.ufill_pch1 uncore memory HBM Precharge commands event=3,umask=0x40  01    Counts the number of HBM Precharge commands sent on this channel unc_mchbm_pre_count.wr uncore memory Precharge due to write on page miss event=3,umask=0x22  01    Counts the number of HBM Precharge commands sent on this channel unc_mchbm_pre_count.wr_pch0 uncore memory HBM Precharge commands. : Precharge due to write event=3,umask=2  01    Counts the number of HBM Precharge commands sent on this channel. : Precharge from write bank scheduler unc_mchbm_pre_count.wr_pch1 uncore memory HBM Precharge commands event=3,umask=0x20  01    Counts the number of HBM Precharge commands sent on this channel unc_mchbm_rdb_full uncore memory Counts the number of cycles where the read buffer has greater than UMASK elements.  NOTE: Umask must be set to the maximum number of elements in the queue (24 entries for SPR) event=0x19  01     unc_mchbm_rdb_inserts uncore memory Counts the number of inserts into the read buffer event=0x17,umask=3  01     unc_mchbm_rdb_inserts.pch0 uncore memory Read Data Buffer Inserts event=0x17,umask=1  01     unc_mchbm_rdb_inserts.pch1 uncore memory Read Data Buffer Inserts event=0x17,umask=2  01     unc_mchbm_rdb_occupancy uncore memory Counts the number of elements in the read buffer per cycle event=0x1a  01     unc_mchbm_rpq_inserts.pch0 uncore memory Read Pending Queue Allocations event=0x10,umask=1  01    Read Pending Queue Allocations: Counts the number of allocations into the Read Pending Queue.  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This includes both ISOCH and non-ISOCH requests unc_mchbm_rpq_inserts.pch1 uncore memory Read Pending Queue Allocations event=0x10,umask=2  01    Read Pending Queue Allocations: Counts the number of allocations into the Read Pending Queue.  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This includes both ISOCH and non-ISOCH requests unc_mchbm_rpq_occupancy_pch0 uncore memory Read Pending Queue Occupancy event=0x80  01    Read Pending Queue Occupancy: Accumulates the occupancies of the Read Pending Queue each cycle.  This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory unc_mchbm_rpq_occupancy_pch1 uncore memory Read Pending Queue Occupancy event=0x81  01    Read Pending Queue Occupancy: Accumulates the occupancies of the Read Pending Queue each cycle.  This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory unc_mchbm_wpq_inserts.pch0 uncore memory Write Pending Queue Allocations event=0x20,umask=1  01    Write Pending Queue Allocations: Counts the number of allocations into the Write Pending Queue.  This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  They deallocate after being issued.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC unc_mchbm_wpq_inserts.pch1 uncore memory Write Pending Queue Allocations event=0x20,umask=2  01    Write Pending Queue Allocations: Counts the number of allocations into the Write Pending Queue.  This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  They deallocate after being issued.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC unc_mchbm_wpq_occupancy_pch0 uncore memory Write Pending Queue Occupancy event=0x82  01    Write Pending Queue Occupancy: Accumulates the occupancies of the Write Pending Queue each cycle.  This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to memory.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.  This is not to be confused with actually performing the write.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.  So, we provide filtering based on if the request has posted or not.  By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA.  The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory.  High average occupancies will generally coincide with high write major mode counts unc_mchbm_wpq_occupancy_pch1 uncore memory Write Pending Queue Occupancy event=0x83  01    Write Pending Queue Occupancy: Accumulates the occupancies of the Write Pending Queue each cycle.  This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to memory.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.  This is not to be confused with actually performing the write.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.  So, we provide filtering based on if the request has posted or not.  By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA.  The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory.  High average occupancies will generally coincide with high write major mode counts unc_mchbm_wpq_read_hit uncore memory Write Pending Queue CAM Match event=0x23  01    Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_mchbm_wpq_read_hit.pch0 uncore memory Write Pending Queue CAM Match event=0x23,umask=1  01    Write Pending Queue CAM Match: Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_mchbm_wpq_read_hit.pch1 uncore memory Write Pending Queue CAM Match event=0x23,umask=2  01    Write Pending Queue CAM Match: Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_mchbm_wpq_write_hit uncore memory Write Pending Queue CAM Match event=0x24  01    Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_mchbm_wpq_write_hit.pch0 uncore memory Write Pending Queue CAM Match event=0x24,umask=1  01    Write Pending Queue CAM Match: Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_mchbm_wpq_write_hit.pch1 uncore memory Write Pending Queue CAM Match event=0x24,umask=2  01    Write Pending Queue CAM Match: Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_m_act_count.all uncore memory Activate due to read, write, underfill, or bypass event=2,umask=0xff  01    DRAM Activate Count : Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_m_cas_count.all uncore memory All DRAM CAS commands issued event=5,umask=0xff  01    DRAM RD_CAS and WR_CAS Commands. : All DRAM Read and Write actions : DRAM RD_CAS and WR_CAS Commands : Counts the total number of DRAM CAS commands issued on this channel unc_m_cas_count.pch0 uncore memory DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 0 event=5,umask=0x40  01    DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 0 : DRAM RD_CAS and WR_CAS Commands unc_m_cas_count.pch1 uncore memory DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 1 event=5,umask=0x80  01    DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 1 : DRAM RD_CAS and WR_CAS Commands unc_m_cas_count.rd uncore memory All DRAM read CAS commands issued (including underfills) event=5,umask=0xcf  01    DRAM RD_CAS and WR_CAS Commands : Counts the total number of DRAM Read CAS commands issued on this channel.  This includes underfills unc_m_cas_count.rd_pre_reg uncore memory DRAM RD_CAS and WR_CAS Commands event=5,umask=0xc2  01    DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands unc_m_cas_count.rd_pre_underfill uncore memory DRAM RD_CAS and WR_CAS Commands event=5,umask=0xc8  01    DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands unc_m_cas_count.rd_reg uncore memory All DRAM read CAS commands issued (does not include underfills) event=5,umask=0xc1  01    DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/out auto-pre : DRAM RD_CAS and WR_CAS Commands : Counts the total number or DRAM Read CAS commands issued on this channel.  This includes both regular RD CAS commands as well as those with implicit Precharge.   We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills) unc_m_cas_count.rd_underfill uncore memory DRAM underfill read CAS commands issued event=5,umask=0xc4  01    DRAM RD_CAS and WR_CAS Commands. : Underfill Read Issued : DRAM RD_CAS and WR_CAS Commands unc_m_cas_count.wr uncore memory All DRAM write CAS commands issued event=5,umask=0xf0  01    DRAM RD_CAS and WR_CAS Commands : Counts the total number of DRAM Write CAS commands issued on this channel unc_m_cas_count.wr_nonpre uncore memory DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre event=5,umask=0xd0  01    DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre : DRAM RD_CAS and WR_CAS Commands unc_m_cas_count.wr_pre uncore memory DRAM RD_CAS and WR_CAS Commands event=5,umask=0xe0  01    DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands unc_m_cas_issued_req_len.pch0 uncore memory Pseudo Channel 0 event=6,umask=0x40  01     unc_m_cas_issued_req_len.pch1 uncore memory Pseudo Channel 1 event=6,umask=0x80  01     unc_m_cas_issued_req_len.rd_32b uncore memory Read CAS Command in Interleaved Mode (32B) event=6,umask=0xc8  01     unc_m_cas_issued_req_len.rd_64b uncore memory Read CAS Command in Regular Mode (64B) in Pseudochannel 0 event=6,umask=0xc1  01     unc_m_cas_issued_req_len.rd_ufill_32b uncore memory Underfill Read CAS Command in Interleaved Mode (32B) event=6,umask=0xd0  01     unc_m_cas_issued_req_len.rd_ufill_64b uncore memory Underfill Read CAS Command in Regular Mode (64B) in Pseudochannel 1 event=6,umask=0xc2  01     unc_m_cas_issued_req_len.wr_32b uncore memory Write CAS Command in Interleaved Mode (32B) event=6,umask=0xe0  01     unc_m_cas_issued_req_len.wr_64b uncore memory Write CAS Command in Regular Mode (64B) in Pseudochannel 0 event=6,umask=0xc4  01     unc_m_clockticks uncore memory IMC Clockticks at DCLK frequency event=1,umask=1  01    Number of DRAM DCLK clock cycles while the event is enabled unc_m_dram_pre_all uncore memory DRAM Precharge All Commands event=0x44,umask=3  01    DRAM Precharge All Commands : Counts the number of times that the precharge all command was sent unc_m_dram_refresh.high uncore memory Number of DRAM Refreshes Issued event=0x45,umask=0x24  01    Number of DRAM Refreshes Issued : Counts the number of refreshes issued unc_m_dram_refresh.high_all uncore memory Number of DRAM Refreshes Issued event=0x45,umask=0x24  01     unc_m_dram_refresh.high_pch0 uncore memory Number of DRAM Refreshes Issued event=0x45,umask=4  01     unc_m_dram_refresh.high_pch1 uncore memory Number of DRAM Refreshes Issued event=0x45,umask=0x20  01     unc_m_dram_refresh.panic uncore memory Number of DRAM Refreshes Issued event=0x45,umask=0x12  01    Number of DRAM Refreshes Issued : Counts the number of refreshes issued unc_m_dram_refresh.panic_all uncore memory Number of DRAM Refreshes Issued event=0x45,umask=0x12  01     unc_m_dram_refresh.panic_pch0 uncore memory Number of DRAM Refreshes Issued event=0x45,umask=2  01     unc_m_dram_refresh.panic_pch1 uncore memory Number of DRAM Refreshes Issued event=0x45,umask=0x10  01     unc_m_ecc_correctable_errors uncore memory ECC Correctable Errors event=9  01    ECC Correctable Errors : Counts the number of ECC errors detected and corrected by the iMC on this channel.  This counter is only useful with ECC DRAM devices.  This count will increment one time for each correction regardless of the number of bits corrected.  The iMC can correct up to 4 bit errors in independent channel mode and 8 bit errors in lockstep mode unc_m_hclockticks uncore memory IMC Clockticks at HCLK frequency event=1  01    Number of DRAM HCLK clock cycles while the event is enabled unc_m_pcls.rd uncore memory UNC_M_PCLS.RD event=0xa0,umask=5  01     unc_m_pcls.total uncore memory UNC_M_PCLS.TOTAL event=0xa0,umask=0xf  01     unc_m_pcls.wr uncore memory UNC_M_PCLS.WR event=0xa0,umask=0xa  01     unc_m_pmm_rpq_inserts uncore memory PMM Read Pending Queue inserts event=0xe3  01    Counts number of read requests allocated in the PMM Read Pending Queue unc_m_pmm_rpq_occupancy.all_sch0 uncore memory PMM Read Pending Queue occupancy event=0xe0,umask=1  01    Accumulates the per cycle occupancy of the PMM Read Pending Queue unc_m_pmm_rpq_occupancy.all_sch1 uncore memory PMM Read Pending Queue occupancy event=0xe0,umask=2  01    Accumulates the per cycle occupancy of the PMM Read Pending Queue unc_m_pmm_rpq_occupancy.gnt_wait_sch0 uncore memory PMM Read Pending Queue Occupancy event=0xe0,umask=0x10  01    PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue unc_m_pmm_rpq_occupancy.gnt_wait_sch1 uncore memory PMM Read Pending Queue Occupancy event=0xe0,umask=0x20  01    PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue unc_m_pmm_rpq_occupancy.no_gnt_sch0 uncore memory PMM Read Pending Queue Occupancy event=0xe0,umask=4  01    Accumulates the per cycle occupancy of the PMM Read Pending Queue unc_m_pmm_rpq_occupancy.no_gnt_sch1 uncore memory PMM Read Pending Queue Occupancy event=0xe0,umask=8  01    Accumulates the per cycle occupancy of the PMM Read Pending Queue unc_m_pmm_wpq_cycles_ne uncore memory PMM (for IXP) Write Queue Cycles Not Empty event=0xe5  01     unc_m_pmm_wpq_inserts uncore memory PMM Write Pending Queue inserts event=0xe7  01    Counts number of  write requests allocated in the PMM Write Pending Queue unc_m_pmm_wpq_occupancy.all uncore memory PMM Write Pending Queue Occupancy event=0xe4,umask=3  01    PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the Write Pending Queue to the PMM DIMM unc_m_pmm_wpq_occupancy.all_sch0 uncore memory PMM Write Pending Queue Occupancy event=0xe4,umask=1  01    PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue unc_m_pmm_wpq_occupancy.all_sch1 uncore memory PMM Write Pending Queue Occupancy event=0xe4,umask=2  01    PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue unc_m_pmm_wpq_occupancy.cas uncore memory PMM (for IXP) Write Pending Queue Occupancy event=0xe4,umask=0xc  01    PMM (for IXP) Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the Write Pending Queue to the IXP DIMM unc_m_pmm_wpq_occupancy.pwr uncore memory PMM (for IXP) Write Pending Queue Occupancy event=0xe4,umask=0x30  01    PMM (for IXP) Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the Write Pending Queue to the IXP DIMM unc_m_power_channel_ppd uncore memory Channel PPD Cycles event=0x85  01    Channel PPD Cycles : Number of cycles when all the ranks in the channel are in PPD mode.  If IBT=off is enabled, then this can be used to count those cycles.  If it is not enabled, then this can count the number of cycles when that could have been taken advantage of unc_m_power_cke_cycles.low_0 uncore memory CKE_ON_CYCLES by Rank : DIMM ID event=0x47,umask=1  01    CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_cke_cycles.low_1 uncore memory CKE_ON_CYCLES by Rank : DIMM ID event=0x47,umask=2  01    CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_cke_cycles.low_2 uncore memory CKE_ON_CYCLES by Rank : DIMM ID event=0x47,umask=4  01    CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_cke_cycles.low_3 uncore memory CKE_ON_CYCLES by Rank : DIMM ID event=0x47,umask=8  01    CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary) unc_m_power_crit_throttle_cycles.slot0 uncore memory Throttle Cycles for Rank 0 event=0x86,umask=1  01    Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1. : Thermal throttling is performed per DIMM.  We support 3 DIMMs per channel.  This ID allows us to filter by ID unc_m_power_crit_throttle_cycles.slot1 uncore memory Throttle Cycles for Rank 0 event=0x86,umask=2  01    Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1 unc_m_power_self_refresh uncore memory Clock-Enabled Self-Refresh event=0x43  01    Clock-Enabled Self-Refresh : Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock.  This happens in some package C-states.  For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing.  One use of this is for Monroe technology.  Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases unc_m_power_throttle_cycles.slot0 uncore memory Throttle Cycles for Rank 0 event=0x46,umask=1  01    Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1. : Thermal throttling is performed per DIMM.  We support 3 DIMMs per channel.  This ID allows us to filter by ID unc_m_power_throttle_cycles.slot1 uncore memory Throttle Cycles for Rank 0 event=0x46,umask=2  01    Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1 unc_m_pre_count.all uncore memory Precharge due to read, write, underfill, or PGT event=3,umask=0xff  01    DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.pgt uncore memory DRAM Precharge commands event=3,umask=0x88  01    DRAM Precharge commands.  Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.pgt_pch0 uncore memory DRAM Precharge commands. : Precharges from Page Table event=3,umask=8  01    DRAM Precharge commands. : Precharges from Page Table : Counts the number of DRAM Precharge commands sent on this channel. : Equivalent to PAGE_EMPTY unc_m_pre_count.pgt_pch1 uncore memory DRAM Precharge commands event=3,umask=0x80  01    DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.rd uncore memory Precharge due to read on page miss event=3,umask=0x11  01    DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.rd_pch0 uncore memory DRAM Precharge commands. : Precharge due to read event=3,umask=1  01    DRAM Precharge commands. : Precharge due to read : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from read bank scheduler unc_m_pre_count.rd_pch1 uncore memory DRAM Precharge commands event=3,umask=0x10  01    DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.ufill uncore memory DRAM Precharge commands event=3,umask=0x44  01    DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.ufill_pch0 uncore memory DRAM Precharge commands event=3,umask=4  01    DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.ufill_pch1 uncore memory DRAM Precharge commands event=3,umask=0x40  01    DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.wr uncore memory Precharge due to write on page miss event=3,umask=0x22  01    DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.wr_pch0 uncore memory DRAM Precharge commands. : Precharge due to write event=3,umask=2  01    DRAM Precharge commands. : Precharge due to write : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from write bank scheduler unc_m_pre_count.wr_pch1 uncore memory DRAM Precharge commands event=3,umask=0x20  01    DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel unc_m_rdb_full uncore memory Counts the number of cycles where the read buffer has greater than UMASK elements.  This includes reads to both DDR and PMEM.  NOTE: Umask must be set to the maximum number of elements in the queue (24 entries for SPR) event=0x19  01     unc_m_rdb_inserts uncore memory Counts the number of inserts into the read buffer destined for DDR.  Does not count reads destined for PMEM event=0x17,umask=3  01     unc_m_rdb_inserts.pch0 uncore memory Read Data Buffer Inserts event=0x17,umask=1  01     unc_m_rdb_inserts.pch1 uncore memory Read Data Buffer Inserts event=0x17,umask=2  01     unc_m_rdb_ne uncore memory Counts the number of cycles where there's at least one element in the read buffer.  This includes reads to both DDR and PMEM event=0x18,umask=3  01     unc_m_rdb_ne.pch0 uncore memory Read Data Buffer Not Empty event=0x18,umask=1  01     unc_m_rdb_ne.pch1 uncore memory Read Data Buffer Not Empty event=0x18,umask=2  01     unc_m_rdb_not_empty uncore memory Counts the number of cycles where there's at least one element in the read buffer.  This includes reads to both DDR and PMEM event=0x18,umask=3  01     unc_m_rdb_occupancy uncore memory Counts the number of elements in the read buffer, including reads to both DDR and PMEM event=0x1a  01     unc_m_rpq_inserts.pch0 uncore memory Read Pending Queue Allocations event=0x10,umask=1  01    Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue.  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This includes both ISOCH and non-ISOCH requests unc_m_rpq_inserts.pch1 uncore memory Read Pending Queue Allocations event=0x10,umask=2  01    Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue.  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This includes both ISOCH and non-ISOCH requests unc_m_rpq_occupancy_pch0 uncore memory Read Pending Queue Occupancy event=0x80  01    Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle.  This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory unc_m_rpq_occupancy_pch1 uncore memory Read Pending Queue Occupancy event=0x81  01    Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle.  This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory unc_m_sb_accesses.accepts uncore memory Scoreboard accepts event=0xd2,umask=5  01     unc_m_sb_accesses.fm_rd_cmps uncore memory Scoreboard Accesses : Write Accepts event=0xd2,umask=0x40  01     unc_m_sb_accesses.fm_wr_cmps uncore memory Scoreboard Accesses : Write Rejects event=0xd2,umask=0x80  01     unc_m_sb_accesses.nm_rd_cmps uncore memory Scoreboard Accesses : FM read completions event=0xd2,umask=0x10  01     unc_m_sb_accesses.nm_wr_cmps uncore memory Scoreboard Accesses : FM write completions event=0xd2,umask=0x20  01     unc_m_sb_accesses.rd_accepts uncore memory Scoreboard Accesses : Read Accepts event=0xd2,umask=1  01     unc_m_sb_accesses.rd_rejects uncore memory Scoreboard Accesses : Read Rejects event=0xd2,umask=2  01     unc_m_sb_accesses.rejects uncore memory Scoreboard rejects event=0xd2,umask=0xa  01     unc_m_sb_accesses.wr_accepts uncore memory Scoreboard Accesses : NM read completions event=0xd2,umask=4  01     unc_m_sb_accesses.wr_rejects uncore memory Scoreboard Accesses : NM write completions event=0xd2,umask=8  01     unc_m_sb_canary.alloc uncore memory : Alloc event=0xd9,umask=1  01     unc_m_sb_canary.dealloc uncore memory : Dealloc event=0xd9,umask=2  01     unc_m_sb_canary.fm_rd_starved uncore memory : Near Mem Write Starved event=0xd9,umask=0x20  01     unc_m_sb_canary.fm_tgr_wr_starved uncore memory : Far Mem Write Starved event=0xd9,umask=0x80  01     unc_m_sb_canary.fm_wr_starved uncore memory : Far Mem Read Starved event=0xd9,umask=0x40  01     unc_m_sb_canary.nm_rd_starved uncore memory : Valid event=0xd9,umask=8  01     unc_m_sb_canary.nm_wr_starved uncore memory : Near Mem Read Starved event=0xd9,umask=0x10  01     unc_m_sb_canary.vld uncore memory : Reject event=0xd9,umask=4  01     unc_m_sb_inserts.block_rds uncore memory Scoreboard Inserts : Block region reads event=0xd6,umask=0x10  01     unc_m_sb_inserts.block_wrs uncore memory Scoreboard Inserts : Block region writes event=0xd6,umask=0x20  01     unc_m_sb_inserts.pmm_rds uncore memory Scoreboard Inserts : Persistent Mem reads event=0xd6,umask=4  01     unc_m_sb_inserts.pmm_wrs uncore memory Scoreboard Inserts : Persistent Mem writes event=0xd6,umask=8  01     unc_m_sb_inserts.rds uncore memory Scoreboard Inserts : Reads event=0xd6,umask=1  01     unc_m_sb_inserts.wrs uncore memory Scoreboard Inserts : Writes event=0xd6,umask=2  01     unc_m_sb_occupancy.block_rds uncore memory Scoreboard Occupancy : Block region reads event=0xd5,umask=0x20  01     unc_m_sb_occupancy.block_wrs uncore memory Scoreboard Occupancy : Block region writes event=0xd5,umask=0x40  01     unc_m_sb_occupancy.pmm_rds uncore memory Scoreboard Occupancy : Persistent Mem reads event=0xd5,umask=4  01     unc_m_sb_occupancy.pmm_wrs uncore memory Scoreboard Occupancy : Persistent Mem writes event=0xd5,umask=8  01     unc_m_sb_occupancy.rds uncore memory Scoreboard Occupancy : Reads event=0xd5,umask=1  01     unc_m_sb_pref_inserts.all uncore memory Scoreboard Prefetch Inserts : All event=0xda,umask=1  01     unc_m_sb_pref_inserts.ddr uncore memory Scoreboard Prefetch Inserts : DDR4 event=0xda,umask=2  01     unc_m_sb_pref_inserts.pmm uncore memory Scoreboard Prefetch Inserts : PMM event=0xda,umask=4  01     unc_m_sb_pref_occupancy.all uncore memory Scoreboard Prefetch Occupancy : All event=0xdb,umask=1  01     unc_m_sb_pref_occupancy.ddr uncore memory Scoreboard Prefetch Occupancy : DDR4 event=0xdb,umask=2  01     unc_m_sb_pref_occupancy.pmm uncore memory Scoreboard Prefetch Occupancy : Persistent Mem event=0xdb,umask=4  01     unc_m_sb_reject.canary uncore memory Number of Scoreboard Requests Rejected event=0xd4,umask=8  01     unc_m_sb_reject.ddr_early_cmp uncore memory Number of Scoreboard Requests Rejected event=0xd4,umask=0x20  01     unc_m_sb_reject.fm_addr_cnflt uncore memory Number of Scoreboard Requests Rejected : FM requests rejected due to full address conflict event=0xd4,umask=2  01     unc_m_sb_reject.nm_set_cnflt uncore memory Number of Scoreboard Requests Rejected : NM requests rejected due to set conflict event=0xd4,umask=1  01     unc_m_sb_reject.patrol_set_cnflt uncore memory Number of Scoreboard Requests Rejected : Patrol requests rejected due to set conflict event=0xd4,umask=4  01     unc_m_sb_strv_alloc.fm_rd uncore memory : Far Mem Read - Set event=0xd7,umask=2  01     unc_m_sb_strv_alloc.fm_tgr uncore memory : Near Mem Read - Clear event=0xd7,umask=0x10  01     unc_m_sb_strv_alloc.fm_wr uncore memory : Far Mem Write - Set event=0xd7,umask=8  01     unc_m_sb_strv_alloc.nm_rd uncore memory : Near Mem Read - Set event=0xd7,umask=1  01     unc_m_sb_strv_alloc.nm_wr uncore memory : Near Mem Write - Set event=0xd7,umask=4  01     unc_m_sb_strv_dealloc.fm_rd uncore memory : Far Mem Read - Set event=0xde,umask=2  01     unc_m_sb_strv_dealloc.fm_tgr uncore memory : Near Mem Read - Clear event=0xde,umask=0x10  01     unc_m_sb_strv_dealloc.fm_wr uncore memory : Far Mem Write - Set event=0xde,umask=8  01     unc_m_sb_strv_dealloc.nm_rd uncore memory : Near Mem Read - Set event=0xde,umask=1  01     unc_m_sb_strv_dealloc.nm_wr uncore memory : Near Mem Write - Set event=0xde,umask=4  01     unc_m_sb_strv_occ.fm_rd uncore memory : Far Mem Read event=0xd8,umask=2  01     unc_m_sb_strv_occ.fm_tgr uncore memory : Near Mem Read - Clear event=0xd8,umask=0x10  01     unc_m_sb_strv_occ.fm_wr uncore memory : Far Mem Write event=0xd8,umask=8  01     unc_m_sb_strv_occ.nm_rd uncore memory : Near Mem Read event=0xd8,umask=1  01     unc_m_sb_strv_occ.nm_wr uncore memory : Near Mem Write event=0xd8,umask=4  01     unc_m_tagchk.hit uncore memory 2LM Tag check hit in near memory cache (DDR4) event=0xd3,umask=1  01     unc_m_tagchk.miss_clean uncore memory 2LM Tag check miss, no data at this line event=0xd3,umask=2  01     unc_m_tagchk.miss_dirty uncore memory 2LM Tag check miss, existing data may be evicted to PMM event=0xd3,umask=4  01     unc_m_tagchk.nm_rd_hit uncore memory 2LM Tag check hit due to memory read event=0xd3,umask=8  01     unc_m_tagchk.nm_wr_hit uncore memory 2LM Tag check hit due to memory write event=0xd3,umask=0x10  01     unc_m_wpq_inserts.pch0 uncore memory Write Pending Queue Allocations event=0x20,umask=1  01    Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue.  This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC unc_m_wpq_inserts.pch1 uncore memory Write Pending Queue Allocations event=0x20,umask=2  01    Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue.  This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC unc_m_wpq_occupancy_pch0 uncore memory Write Pending Queue Occupancy event=0x82  01    Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle.  This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.  So, we provide filtering based on if the request has posted or not.  By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA.  The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory.  High average occupancies will generally coincide with high write major mode counts unc_m_wpq_occupancy_pch1 uncore memory Write Pending Queue Occupancy event=0x83  01    Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle.  This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.  So, we provide filtering based on if the request has posted or not.  By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA.  The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory.  High average occupancies will generally coincide with high write major mode counts unc_p_clockticks uncore power PCU PCLK Clockticks event=1  01    Number of PCU PCLK Clock cycles while the event is enabled unc_p_fivr_ps_ps0_cycles uncore power Phase Shed 0 Cycles event=0x75  01    Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0 unc_p_fivr_ps_ps1_cycles uncore power Phase Shed 1 Cycles event=0x76  01    Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1 unc_p_fivr_ps_ps2_cycles uncore power Phase Shed 2 Cycles event=0x77  01    Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2 unc_p_fivr_ps_ps3_cycles uncore power Phase Shed 3 Cycles event=0x78  01    Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3 unc_p_freq_clip_avx256 uncore power AVX256 Frequency Clipping event=0x49  01     unc_p_freq_clip_avx512 uncore power AVX512 Frequency Clipping event=0x4a  01     unc_p_freq_max_limit_thermal_cycles uncore power Thermal Strongest Upper Limit Cycles event=4  01    Thermal Strongest Upper Limit Cycles : Number of cycles any frequency is reduced due to a thermal limit.  Count only if throttling is occurring unc_p_freq_max_power_cycles uncore power Power Strongest Upper Limit Cycles event=5  01    Power Strongest Upper Limit Cycles : Counts the number of cycles when power is the upper limit on frequency unc_p_freq_min_io_p_cycles uncore power IO P Limit Strongest Lower Limit Cycles event=0x73  01    IO P Limit Strongest Lower Limit Cycles : Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower.  This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW.  This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth unc_p_freq_trans_cycles uncore power Cycles spent changing Frequency event=0x74  01    Cycles spent changing Frequency : Counts the number of cycles when the system is changing frequency.  This can not be filtered by thread ID.  One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system unc_p_memory_phase_shedding_cycles uncore power Memory Phase Shedding Cycles event=0x2f  01    Memory Phase Shedding Cycles : Counts the number of cycles that the PCU has triggered memory phase shedding.  This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency unc_p_pkg_residency_c0_cycles uncore power Package C State Residency - C0 event=0x2a  01    Package C State Residency - C0 : Counts the number of cycles when the package was in C0.  This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert).  Residency events do not include transition times unc_p_pkg_residency_c2e_cycles uncore power Package C State Residency - C2E event=0x2b  01    Package C State Residency - C2E : Counts the number of cycles when the package was in C2E.  This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert).  Residency events do not include transition times unc_p_pkg_residency_c6_cycles uncore power Package C State Residency - C6 event=0x2d  01    Package C State Residency - C6 : Counts the number of cycles when the package was in C6.  This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert).  Residency events do not include transition times unc_p_pmax_throttled_cycles uncore power UNC_P_PMAX_THROTTLED_CYCLES event=6  01     unc_p_power_state_occupancy_cores_c0 uncore power Number of cores in C0 event=0x35  01    Number of cores in C0 : This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_power_state_occupancy_cores_c3 uncore power Number of cores in C3 event=0x36  01    Number of cores in C3 : This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_power_state_occupancy_cores_c6 uncore power Number of cores in C6 event=0x37  01    Number of cores in C6 : This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_prochot_external_cycles uncore power External Prochot event=0xa  01    External Prochot : Counts the number of cycles that we are in external PROCHOT mode.  This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip unc_p_prochot_internal_cycles uncore power Internal Prochot event=9  01    Internal Prochot : Counts the number of cycles that we are in Internal PROCHOT mode.  This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip unc_p_total_transition_cycles uncore power Total Core C State Transition Cycles event=0x72  01    Total Core C State Transition Cycles : Number of cycles spent performing core C state transitions across all cores core_reject_l2q.all cache Requests rejected by the L2Q event=0x31,period=200003  00    Counts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to ensure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoops dl1.dirty_eviction cache L1 Cache evictions for dirty data event=0x51,period=200003,umask=1  00    Counts when a modified (dirty) cache line is evicted from the data L1 cache and needs to be written back to memory.  No count will occur if the evicted line is clean, and hence does not require a writeback fetch_stall.icache_fill_pending_cycles cache Cycles code-fetch stalled due to an outstanding ICache miss event=0x86,period=200003,umask=2  00    Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss.  Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy l2_reject_xq.all cache Requests rejected by the XQ event=0x30,period=200003  00    Counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cacheable requests), L2 misses and L2 write-back victims longest_lat_cache.miss cache L2 cache request misses event=0x2e,period=200003,umask=0x41  00    Counts memory requests originating from the core that miss in the L2 cache longest_lat_cache.reference cache L2 cache requests event=0x2e,period=200003,umask=0x4f  00    Counts memory requests originating from the core that reference a cache line in the L2 cache mem_load_uops_retired.dram_hit cache Loads retired that came from DRAM (Precise event capable)  Supports address when precise (Must be precise) event=0xd1,period=200003,umask=0x80  00    Counts memory load uops retired where the data is retrieved from DRAM.  Event is counted at retirement, so the speculative loads are ignored.  A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit in the WCB or receive a HITM response  Supports address when precise (Must be precise) mem_load_uops_retired.hitm cache Memory uop retired where cross core or cross module HITM occurred (Precise event capable)  Supports address when precise (Must be precise) event=0xd1,period=200003,umask=0x20  00    Counts load uops retired where the cache line containing the data was in the modified state of another core or modules cache (HITM).  More specifically, this means that when the load address was checked by other caching agents (typically another processor) in the system, one of those caching agents indicated that they had a dirty copy of the data.  Loads that obtain a HITM response incur greater latency than most is typical for a load.  In addition, since HITM indicates that some other processor had this data in its cache, it implies that the data was shared between processors, or potentially was a lock or semaphore value.  This event is useful for locating sharing, false sharing, and contended locks  Supports address when precise (Must be precise) mem_load_uops_retired.l1_hit cache Load uops retired that hit L1 data cache (Precise event capable)  Supports address when precise (Must be precise) event=0xd1,period=200003,umask=1  00    Counts load uops retired that hit the L1 data cache  Supports address when precise (Must be precise) mem_load_uops_retired.l1_miss cache Load uops retired that missed L1 data cache (Precise event capable)  Supports address when precise (Must be precise) event=0xd1,period=200003,umask=8  00    Counts load uops retired that miss the L1 data cache  Supports address when precise (Must be precise) mem_load_uops_retired.l2_hit cache Load uops retired that hit L2 (Precise event capable)  Supports address when precise (Must be precise) event=0xd1,period=200003,umask=2  00    Counts load uops retired that hit in the L2 cache  Supports address when precise (Must be precise) mem_load_uops_retired.l2_miss cache Load uops retired that missed L2 (Precise event capable)  Supports address when precise (Must be precise) event=0xd1,period=200003,umask=0x10  00    Counts load uops retired that miss in the L2 cache  Supports address when precise (Must be precise) mem_load_uops_retired.wcb_hit cache Loads retired that hit WCB (Precise event capable)  Supports address when precise (Must be precise) event=0xd1,period=200003,umask=0x40  00    Counts memory load uops retired where the data is retrieved from the WCB (or fill buffer), indicating that the load found its data while that data was in the process of being brought into the L1 cache.  Typically a load will receive this indication when some other load or prefetch missed the L1 cache and was in the process of retrieving the cache line containing the data, but that process had not yet finished (and written the data back to the cache). For example, consider load X and Y, both referencing the same cache line that is not in the L1 cache.  If load X misses cache first, it obtains and WCB (or fill buffer) and begins the process of requesting the data.  When load Y requests the data, it will either hit the WCB, or the L1 cache, depending on exactly what time the request to Y occurs  Supports address when precise (Must be precise) mem_uops_retired.all cache Memory uops retired (Precise event capable)  Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x83  00    Counts the number of memory uops retired that is either a loads or a store or both  Supports address when precise (Must be precise) mem_uops_retired.all_loads cache Load uops retired (Precise event capable)  Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x81  00    Counts the number of load uops retired  Supports address when precise (Must be precise) mem_uops_retired.all_stores cache Store uops retired (Precise event capable)  Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x82  00    Counts the number of store uops retired  Supports address when precise (Must be precise) mem_uops_retired.lock_loads cache Locked load uops retired (Precise event capable)  Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x21  00    Counts locked memory uops retired.  This includes regular locks and bus locks. (To specifically count bus locks only, see the Offcore response event.)  A locked access is one with a lock prefix, or an exchange to memory.  See the SDM for a complete description of which memory load accesses are locks  Supports address when precise (Must be precise) mem_uops_retired.split cache Memory uops retired that split a cache-line (Precise event capable)  Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x43  00    Counts memory uops retired where the data requested spans a 64 byte cache line boundary  Supports address when precise (Must be precise) mem_uops_retired.split_loads cache Load uops retired that split a cache-line (Precise event capable)  Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x41  00    Counts load uops retired where the data requested spans a 64 byte cache line boundary  Supports address when precise (Must be precise) mem_uops_retired.split_stores cache Stores uops retired that split a cache-line (Precise event capable)  Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x42  00    Counts store uops retired where the data requested spans a 64 byte cache line boundary  Supports address when precise (Must be precise) offcore_response cache Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=1  00     offcore_response.any_data_rd.l2_hit cache Counts data reads (demand & prefetch) that hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000043091  00    Counts data reads (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.l2_miss.any cache Counts data reads (demand & prefetch) that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x3600003091  00    Counts data reads (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.l2_miss.hitm_other_core cache Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000003091  00    Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.l2_miss.hit_other_core_no_fwd cache Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x0400003091  00    Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data reads (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200003091  00    Counts data reads (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.l2_hit cache Counts data reads generated by L1 or L2 prefetchers that hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000043010  00    Counts data reads generated by L1 or L2 prefetchers that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.l2_miss.any cache Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x3600003010  00    Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.l2_miss.hitm_other_core cache Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000003010  00    Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.l2_miss.hit_other_core_no_fwd cache Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x0400003010  00    Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data reads generated by L1 or L2 prefetchers that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200003010  00    Counts data reads generated by L1 or L2 prefetchers that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.l2_hit cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x00000432b7  00    Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.l2_miss.any cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x36000032b7  00    Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.l2_miss.hitm_other_core cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x10000032b7  00    Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.l2_miss.hit_other_core_no_fwd cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x04000032b7  00    Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x02000032b7  00    Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.any_response cache Counts requests to the uncore subsystem that have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000018000  00    Counts requests to the uncore subsystem that have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.l2_hit cache Counts requests to the uncore subsystem that hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000048000  00    Counts requests to the uncore subsystem that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.l2_miss.hitm_other_core cache Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000008000  00    Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.l2_miss.hit_other_core_no_fwd cache Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x0400008000  00    Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.l2_miss.snoop_miss_or_no_snoop_needed cache Counts requests to the uncore subsystem that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200008000  00    Counts requests to the uncore subsystem that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.l2_hit cache Counts reads for ownership (RFO) requests (demand & prefetch) that hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040022  00    Counts reads for ownership (RFO) requests (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.l2_miss.any cache Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x3600000022  00    Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.l2_miss.hitm_other_core cache Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000022  00    Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.l2_miss.hit_other_core_no_fwd cache Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x0400000022  00    Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.l2_miss.snoop_miss_or_no_snoop_needed cache Counts reads for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000022  00    Counts reads for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.bus_locks.any_response cache Counts bus lock and split lock requests that have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010400  00    Counts bus lock and split lock requests that have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.l2_hit cache Counts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040008  00    Counts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.l2_miss.any cache Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x3600000008  00    Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.l2_miss.hitm_other_core cache Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000008  00    Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.l2_miss.hit_other_core_no_fwd cache Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x0400000008  00    Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.l2_miss.snoop_miss_or_no_snoop_needed cache Counts the number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000008  00    Counts the number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.l2_hit cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040004  00    Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.l2_miss.any cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x3600000004  00    Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.l2_miss.hit_other_core_no_fwd cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x0400000004  00    Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000004  00    Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.outstanding cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that are outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000004  00    Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.l2_hit cache Counts demand cacheable data reads of full cache lines that hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040001  00    Counts demand cacheable data reads of full cache lines that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.l2_miss.any cache Counts demand cacheable data reads of full cache lines that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x3600000001  00    Counts demand cacheable data reads of full cache lines that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.l2_miss.hitm_other_core cache Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000001  00    Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.l2_miss.hit_other_core_no_fwd cache Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x0400000001  00    Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts demand cacheable data reads of full cache lines that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000001  00    Counts demand cacheable data reads of full cache lines that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.outstanding cache Counts demand cacheable data reads of full cache lines that are outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000001  00    Counts demand cacheable data reads of full cache lines that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.l2_hit cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040002  00    Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.l2_miss.any cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x3600000002  00    Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.l2_miss.hitm_other_core cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000002  00    Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.l2_miss.hit_other_core_no_fwd cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x0400000002  00    Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.l2_miss.snoop_miss_or_no_snoop_needed cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000002  00    Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.outstanding cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that are outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000002  00    Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_hit cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040800  00    Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_miss.any cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x3600000800  00    Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_miss.hitm_other_core cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000800  00    Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_miss.hit_other_core_no_fwd cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x0400000800  00    Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_miss.snoop_miss_or_no_snoop_needed cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000800  00    Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.partial_reads.l2_miss.any cache Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x3600000080  00    Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.partial_streaming_stores.l2_hit cache Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000044000  00    Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.partial_streaming_stores.l2_miss.any cache Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x3600004000  00    Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.partial_streaming_stores.l2_miss.hitm_other_core cache Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000004000  00    Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.partial_streaming_stores.l2_miss.hit_other_core_no_fwd cache Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x0400004000  00    Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.partial_streaming_stores.l2_miss.snoop_miss_or_no_snoop_needed cache Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200004000  00    Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.partial_writes.l2_miss.any cache Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x3600000100  00    Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.l2_hit cache Counts data cache line reads generated by hardware L1 data cache prefetcher that hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000042000  00    Counts data cache line reads generated by hardware L1 data cache prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.l2_miss.any cache Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x3600002000  00    Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.l2_miss.hitm_other_core cache Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000002000  00    Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.l2_miss.hit_other_core_no_fwd cache Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x0400002000  00    Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data cache line reads generated by hardware L1 data cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200002000  00    Counts data cache line reads generated by hardware L1 data cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.l2_hit cache Counts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040010  00    Counts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.l2_miss.any cache Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x3600000010  00    Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.l2_miss.hitm_other_core cache Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000010  00    Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.l2_miss.hit_other_core_no_fwd cache Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x0400000010  00    Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000010  00    Counts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.l2_hit cache Counts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040020  00    Counts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.l2_miss.any cache Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x3600000020  00    Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.l2_miss.hitm_other_core cache Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000020  00    Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.l2_miss.hit_other_core_no_fwd cache Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x0400000020  00    Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.l2_miss.snoop_miss_or_no_snoop_needed cache Counts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000020  00    Counts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.streaming_stores.l2_hit cache Counts any data writes to uncacheable write combining (USWC) memory region  that hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000044800  00    Counts any data writes to uncacheable write combining (USWC) memory region  that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.streaming_stores.l2_miss.any cache Counts any data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x3600004800  00    Counts any data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.l2_hit cache Counts data cache lines requests by software prefetch instructions that hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000041000  00    Counts data cache lines requests by software prefetch instructions that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.l2_miss.any cache Counts data cache lines requests by software prefetch instructions that miss the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x3600001000  00    Counts data cache lines requests by software prefetch instructions that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.l2_miss.hitm_other_core cache Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000001000  00    Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.l2_miss.hit_other_core_no_fwd cache Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x0400001000  00    Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data cache lines requests by software prefetch instructions that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200001000  00    Counts data cache lines requests by software prefetch instructions that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) cycles_div_busy.fpdiv floating point Cycles the FP divide unit is busy event=0xcd,period=200003,umask=2  00    Counts core cycles the floating point divide unit is busy machine_clears.fp_assist floating point Machine clears due to FP assists event=0xc3,period=200003,umask=4  00    Counts machine clears due to floating point (FP) operations needing assists.  For instance, if the result was a floating point denormal, the hardware clears the pipeline and reissues uops to produce the correct IEEE compliant denormal result uops_retired.fpdiv floating point Floating point divide uops retired. (Precise Event Capable) (Must be precise) event=0xc2,period=2000003,umask=8  00    Counts the number of floating point divide uops retired (Must be precise) baclears.all frontend BACLEARs asserted for any branch type event=0xe6,period=200003,umask=1  00    Counts the number of times a BACLEAR is signaled for any reason, including, but not limited to indirect branch/call,  Jcc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditional branch/call, and returns baclears.cond frontend BACLEARs asserted for conditional branch event=0xe6,period=200003,umask=0x10  00    Counts BACLEARS on Jcc (Jump on Conditional Code/Jump if Condition is Met) branches baclears.return frontend BACLEARs asserted for return branch event=0xe6,period=200003,umask=8  00    Counts BACLEARS on return instructions decode_restriction.predecode_wrong frontend Decode restrictions due to predicting wrong instruction length event=0xe9,period=200003,umask=1  00    Counts the number of times the prediction (from the predecode cache) for instruction length is incorrect icache.accesses frontend References per ICache line. This event counts differently than Intel processors based on Silvermont microarchitecture event=0x80,period=200003,umask=3  00    Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line.  The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS.  Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line.
This event counts differently than Intel processors based on Silvermont microarchitecture icache.hit frontend References per ICache line that are available in the ICache (hit). This event counts differently than Intel processors based on Silvermont microarchitecture event=0x80,period=200003,umask=1  00    Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit).  The event strives to count on a cache line basis, so that multiple accesses which hit in a single cache line count as one ICACHE.HIT.  Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture icache.misses frontend References per ICache line that are not available in the ICache (miss). This event counts differently than Intel processors based on Silvermont microarchitecture event=0x80,period=200003,umask=2  00    Counts requests to the Instruction Cache (ICache)  for one or more bytes in an ICache Line and that cache line is not in the ICache (miss).  The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS.  Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture ms_decoded.ms_entry frontend MS decode starts event=0xe7,period=200003,umask=1  00    Counts the number of times the Microcode Sequencer (MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSROM.  The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine.  Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort that initiates a flow of uops.  The event will count MS startups for uops that are speculative, and subsequently cleared by branch mispredict or a machine clear machine_clears.memory_ordering memory Machine clears due to memory ordering issue event=0xc3,period=200003,umask=2  00    Counts machine clears due to memory ordering issues.  This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved as another core is in the process of modifying the data misalign_mem_ref.load_page_split memory Load uops that split a page (Precise event capable) (Must be precise) event=0x13,period=200003,umask=2  00    Counts when a memory load of a uop spans a page boundary (a split) is retired (Must be precise) misalign_mem_ref.store_page_split memory Store uops that split a page (Precise event capable) (Must be precise) event=0x13,period=200003,umask=4  00    Counts when a memory store of a uop spans a page boundary (a split) is retired (Must be precise) fetch_stall.all other Cycles code-fetch stalled due to any reason event=0x86,period=200003  00    Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes.  This will include cycles due to an ITLB miss, ICache miss and other events fetch_stall.itlb_fill_pending_cycles other Cycles code-fetch stalled due to an outstanding ITLB miss event=0x86,period=200003,umask=1  00    Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss.  Note: this event is not the same as page walk cycles to retrieve an instruction translation hw_interrupts.masked other Cycles hardware interrupts are masked event=0xcb,period=200003,umask=2  00    Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not hw_interrupts.pending_and_masked other Cycles pending interrupts are masked event=0xcb,period=200003,umask=4  00    Counts core cycles during which there are pending interrupts, but interrupts are masked (EFLAGS.IF = 0) hw_interrupts.received other Hardware interrupts received event=0xcb,period=203,umask=1  00    Counts hardware interrupts received by the processor br_inst_retired.all_branches pipeline Retired branch instructions (Precise event capable) (Must be precise) event=0xc4,period=200003  00    Counts branch instructions retired for all branch types.  This is an architectural performance event (Must be precise) br_inst_retired.all_taken_branches pipeline Retired taken branch instructions (Precise event capable) (Must be precise) event=0xc4,period=200003,umask=0x80  00    Counts the number of taken branch instructions retired (Must be precise) br_inst_retired.call pipeline Retired near call instructions (Precise event capable) (Must be precise) event=0xc4,period=200003,umask=0xf9  00    Counts near CALL branch instructions retired (Must be precise) br_inst_retired.far_branch pipeline Retired far branch instructions (Precise event capable) (Must be precise) event=0xc4,period=200003,umask=0xbf  00    Counts far branch instructions retired.  This includes far jump, far call and return, and Interrupt call and return (Must be precise) br_inst_retired.ind_call pipeline Retired near indirect call instructions (Precise event capable) (Must be precise) event=0xc4,period=200003,umask=0xfb  00    Counts near indirect CALL branch instructions retired (Must be precise) br_inst_retired.jcc pipeline Retired conditional branch instructions (Precise event capable) (Must be precise) event=0xc4,period=200003,umask=0x7e  00    Counts retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was taken and when it was not taken (Must be precise) br_inst_retired.non_return_ind pipeline Retired instructions of near indirect Jmp or call (Precise event capable) (Must be precise) event=0xc4,period=200003,umask=0xeb  00    Counts near indirect call or near indirect jmp branch instructions retired (Must be precise) br_inst_retired.rel_call pipeline Retired near relative call instructions (Precise event capable) (Must be precise) event=0xc4,period=200003,umask=0xfd  00    Counts near relative CALL branch instructions retired (Must be precise) br_inst_retired.return pipeline Retired near return instructions (Precise event capable) (Must be precise) event=0xc4,period=200003,umask=0xf7  00    Counts near return branch instructions retired (Must be precise) br_inst_retired.taken_jcc pipeline Retired conditional branch instructions that were taken (Precise event capable) (Must be precise) event=0xc4,period=200003,umask=0xfe  00    Counts Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were taken and does not count when the Jcc branch instruction were not taken (Must be precise) br_misp_retired.all_branches pipeline Retired mispredicted branch instructions (Precise event capable) (Must be precise) event=0xc5,period=200003  00    Counts mispredicted branch instructions retired including all branch types (Must be precise) br_misp_retired.ind_call pipeline Retired mispredicted near indirect call instructions (Precise event capable) (Must be precise) event=0xc5,period=200003,umask=0xfb  00    Counts mispredicted near indirect CALL branch instructions retired, where the target address taken was not what the processor predicted (Must be precise) br_misp_retired.jcc pipeline Retired mispredicted conditional branch instructions (Precise event capable) (Must be precise) event=0xc5,period=200003,umask=0x7e  00    Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was supposed to be taken and when it was not supposed to be taken (but the processor predicted the opposite condition) (Must be precise) br_misp_retired.non_return_ind pipeline Retired mispredicted instructions of near indirect Jmp or near indirect call. (Precise event capable) (Must be precise) event=0xc5,period=200003,umask=0xeb  00    Counts mispredicted branch instructions retired that were near indirect call or near indirect jmp, where the target address taken was not what the processor predicted (Must be precise) br_misp_retired.return pipeline Retired mispredicted near return instructions (Precise event capable) (Must be precise) event=0xc5,period=200003,umask=0xf7  00    Counts mispredicted near RET branch instructions retired, where the return address taken was not what the processor predicted (Must be precise) br_misp_retired.taken_jcc pipeline Retired mispredicted conditional branch instructions that were taken (Precise event capable) (Must be precise) event=0xc5,period=200003,umask=0xfe  00    Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were supposed to be taken but the processor predicted that it would not be taken (Must be precise) cpu_clk_unhalted.core pipeline Core cycles when core is not halted  (Fixed event) event=0x3c,period=2000003  00    Counts the number of core cycles while the core is not in a halt state.  The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time.  This event uses fixed counter 1.  You cannot collect a PEBs record for this event cpu_clk_unhalted.core_p pipeline Core cycles when core is not halted event=0x3c,period=2000003  00    Core cycles when core is not halted.  This event uses a (_P)rogrammable general purpose performance counter cpu_clk_unhalted.ref pipeline Reference cycles when core is not halted event=0x0,umask=0x03,period=2000003  00    Reference cycles when core is not halted.  This event uses a programmable general purpose performance counter cpu_clk_unhalted.ref_tsc pipeline Reference cycles when core is not halted  (Fixed event) event=0,period=2000003,umask=3  00    Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction.  In mobile systems the core frequency may change from time.  This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time.  This event uses fixed counter 2.  You cannot collect a PEBs record for this event cycles_div_busy.all pipeline Cycles a divider is busy event=0xcd,period=2000003  00    Counts core cycles if either divide unit is busy cycles_div_busy.idiv pipeline Cycles the integer divide unit is busy event=0xcd,period=200003,umask=1  00    Counts core cycles the integer divide unit is busy inst_retired.any pipeline Instructions retired (Fixed event) event=0xc0,period=2000003  00    Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers.  This event uses fixed counter 0.  You cannot collect a PEBs record for this event inst_retired.any_p pipeline Instructions retired (Precise event capable) (Must be precise) event=0xc0,period=2000003  00    Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers.  This is an architectural performance event.  This event uses a (_P)rogrammable general purpose performance counter. *This event is Precise Event capable:  The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event.  Note: Because PEBS records can be collected only on IA32_PMC0, only one event can use the PEBS facility at a time (Must be precise) issue_slots_not_consumed.any pipeline Unfilled issue slots per cycle event=0xca,period=200003  00    Counts the number of issue slots per core cycle that were not consumed by the backend due to either a full resource  in the backend (RESOURCE_FULL) or due to the processor recovering from some event (RECOVERY) issue_slots_not_consumed.recovery pipeline Unfilled issue slots per cycle to recover event=0xca,period=200003,umask=2  00    Counts the number of issue slots per core cycle that were not consumed by the backend because allocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g. the event is relevant during certain microcode flows).   Counts all issue slots blocked while within this window including slots where uops were not available in the Instruction Queue issue_slots_not_consumed.resource_full pipeline Unfilled issue slots per cycle because of a full resource in the backend event=0xca,period=200003,umask=1  00    Counts the number of issue slots per core cycle that were not consumed because of a full resource in the backend.  Including but not limited to resources such as the Re-order Buffer (ROB), reservation stations (RS), load/store buffers, physical registers, or any other needed machine resource that is currently unavailable.   Note that uops must be available for consumption in order for this event to fire.  If a uop is not available (Instruction Queue is empty), this event will not count ld_blocks.4k_alias pipeline Loads blocked because address has 4k partial address false dependence (Precise event capable) (Must be precise) event=3,period=200003,umask=4  00    Counts loads that block because their address modulo 4K matches a pending store (Must be precise) ld_blocks.all_block pipeline Loads blocked (Precise event capable) (Must be precise) event=3,period=200003,umask=0x10  00    Counts anytime a load that retires is blocked for any reason (Must be precise) ld_blocks.data_unknown pipeline Loads blocked due to store data not ready (Precise event capable) (Must be precise) event=3,period=200003,umask=1  00    Counts a load blocked from using a store forward, but did not occur because the store data was not available at the right time.  The forward might occur subsequently when the data is available (Must be precise) ld_blocks.store_forward pipeline Loads blocked due to store forward restriction (Precise event capable) (Must be precise) event=3,period=200003,umask=2  00    Counts a load blocked from using a store forward because of an address/size mismatch, only one of the loads blocked from each store will be counted (Must be precise) ld_blocks.utlb_miss pipeline Loads blocked because address in not in the UTLB (Precise event capable) (Must be precise) event=3,period=200003,umask=8  00    Counts loads blocked because they are unable to find their physical address in the micro TLB (UTLB) (Must be precise) machine_clears.all pipeline All machine clears event=0xc3,period=200003  00    Counts machine clears for any reason machine_clears.disambiguation pipeline Machine clears due to memory disambiguation event=0xc3,period=200003,umask=8  00    Counts machine clears due to memory disambiguation.  Memory disambiguation happens when a load which has been issued conflicts with a previous unretired store in the pipeline whose address was not known at issue time, but is later resolved to be the same as the load address machine_clears.smc pipeline Self-Modifying Code detected event=0xc3,period=200003,umask=1  00    Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification.  Self-modifying code (SMC) causes a severe penalty in all Intel(R) architecture processors uops_issued.any pipeline Uops issued to the back end per cycle event=0xe,period=200003  00    Counts uops issued by the front end and allocated into the back end of the machine.  This event counts uops that retire as well as uops that were speculatively executed but didn't retire. The sort of speculative uops that might be counted includes, but is not limited to those uops issued in the shadow of a miss-predicted branch, those uops that are inserted during an assist (such as for a denormal floating point result), and (previously allocated) uops that might be canceled during a machine clear uops_not_delivered.any pipeline Uops requested but not-delivered to the back-end per cycle event=0x9c,period=200003  00    This event used to measure front-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and the back-end has is not stalled. This event can be used to identify if the machine is truly front-end bound.  When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into uops in machine understandable format and putting them into a uop queue to be consumed by back end. The back-end then takes these uops, allocates the required resources.  When all resources are ready, uops are executed. If the back-end is not ready to accept uops from the front-end, then we do not want to count these as front-end bottlenecks.  However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more uops. This event counts only when back-end is requesting more uops and front-end is not able to provide them. When 3 uops are requested and no uops are delivered, the event counts 3. When 3 are requested, and only 1 is delivered, the event counts 2. When only 2 are delivered, the event counts 1. Alternatively stated, the event will not count if 3 uops are delivered, or if the back end is stalled and not requesting any uops at all.  Counts indicate missed opportunities for the front-end to deliver a uop to the back end. Some examples of conditions that cause front-end efficiencies are: ICache misses, ITLB misses, and decoder restrictions that limit the front-end bandwidth. Known Issues: Some uops require multiple allocation slots.  These uops will not be charged as a front end 'not delivered' opportunity, and will be regarded as a back end problem. For example, the INC instruction has one uop that requires 2 issue slots.  A stream of INC instructions will not count as UOPS_NOT_DELIVERED, even though only one instruction can be issued per clock.  The low uop issue rate for a stream of INC instructions is considered to be a back end issue uops_retired.any pipeline Uops retired (Precise event capable) (Must be precise) event=0xc2,period=2000003  00    Counts uops which retired (Must be precise) uops_retired.idiv pipeline Integer divide uops retired. (Precise Event Capable) (Must be precise) event=0xc2,period=2000003,umask=0x10  00    Counts the number of integer divide uops retired (Must be precise) uops_retired.ms pipeline MS uops retired (Precise event capable) (Must be precise) event=0xc2,period=2000003,umask=1  00    Counts uops retired that are from the complex flows issued by the micro-sequencer (MS).  Counts both the uops from a micro-coded instruction, and the uops that might be generated from a micro-coded assist (Must be precise) itlb.miss virtual memory ITLB misses event=0x81,period=200003,umask=4  00    Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) for a linear address of an instruction fetch.  It counts when new translation are filled into the ITLB.  The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB mem_uops_retired.dtlb_miss virtual memory Memory uops retired that missed the DTLB (Precise event capable)  Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x13  00    Counts uops retired that had a DTLB miss on load, store or either.  Note that when two distinct memory operations to the same page miss the DTLB, only one of them will be recorded as a DTLB miss  Supports address when precise (Must be precise) mem_uops_retired.dtlb_miss_loads virtual memory Load uops retired that missed the DTLB (Precise event capable)  Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x11  00    Counts load uops retired that caused a DTLB miss  Supports address when precise (Must be precise) mem_uops_retired.dtlb_miss_stores virtual memory Store uops retired that missed the DTLB (Precise event capable)  Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x12  00    Counts store uops retired that caused a DTLB miss  Supports address when precise (Must be precise) page_walks.cycles virtual memory Duration of page-walks in cycles event=5,period=200003,umask=3  00    Counts every core cycle a page-walk is in progress due to either a data memory operation or an instruction fetch page_walks.d_side_cycles virtual memory Duration of D-side page-walks in cycles event=5,period=200003,umask=1  00    Counts every core cycle when a Data-side (walks due to a data operation) page walk is in progress page_walks.i_side_cycles virtual memory Duration of I-side pagewalks in cycles event=5,period=200003,umask=2  00    Counts every core cycle when a Instruction-side (walks due to an instruction fetch) page walk is in progress core_reject_l2q.all cache Requests rejected by the L2Q event=0x31,period=200003  00    Counts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoops dl1.replacement cache L1 Cache evictions for dirty data event=0x51,period=200003,umask=1  00    Counts when a modified (dirty) cache line is evicted from the data L1 cache and needs to be written back to memory.  No count will occur if the evicted line is clean, and hence does not require a writeback offcore_response.any_data_rd.any_response cache Counts data reads (demand & prefetch) have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000013091  00    Counts data reads (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.l2_hit cache Counts data reads (demand & prefetch) hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000043091  00    Counts data reads (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.l2_miss.hitm_other_core cache Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000003091  00    Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200003091  00    Counts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.outstanding cache Counts data reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000003091  00    Counts data reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.any_response cache Counts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000013010  00    Counts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.l2_hit cache Counts data reads generated by L1 or L2 prefetchers hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000043010  00    Counts data reads generated by L1 or L2 prefetchers hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.l2_miss.hitm_other_core cache Counts data reads generated by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000003010  00    Counts data reads generated by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200003010  00    Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.outstanding cache Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000003010  00    Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.any_response cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x00000132b7  00    Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.l2_hit cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x00000432b7  00    Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.l2_miss.hitm_other_core cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x10000032b7  00    Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x02000032b7  00    Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.outstanding cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x40000032b7  00    Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.any_response cache Counts requests to the uncore subsystem have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000018000  00    Counts requests to the uncore subsystem have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.l2_hit cache Counts requests to the uncore subsystem hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000048000  00    Counts requests to the uncore subsystem hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.l2_miss.hitm_other_core cache Counts requests to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000008000  00    Counts requests to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.l2_miss.snoop_miss_or_no_snoop_needed cache Counts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200008000  00    Counts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.outstanding cache Counts requests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000008000  00    Counts requests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.any_response cache Counts reads for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010022  00    Counts reads for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.l2_hit cache Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040022  00    Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.l2_miss.hitm_other_core cache Counts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000022  00    Counts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.l2_miss.snoop_miss_or_no_snoop_needed cache Counts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000022  00    Counts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.outstanding cache Counts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000022  00    Counts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.bus_locks.any_response cache Counts bus lock and split lock requests have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010400  00    Counts bus lock and split lock requests have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.bus_locks.l2_hit cache Counts bus lock and split lock requests hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040400  00    Counts bus lock and split lock requests hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.bus_locks.l2_miss.hitm_other_core cache Counts bus lock and split lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000400  00    Counts bus lock and split lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.bus_locks.l2_miss.snoop_miss_or_no_snoop_needed cache Counts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000400  00    Counts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.bus_locks.outstanding cache Counts bus lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000400  00    Counts bus lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.any_response cache Counts the number of writeback transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010008  00    Counts the number of writeback transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.l2_hit cache Counts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040008  00    Counts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.l2_miss.hitm_other_core cache Counts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000008  00    Counts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.l2_miss.snoop_miss_or_no_snoop_needed cache Counts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000008  00    Counts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.outstanding cache Counts the number of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000008  00    Counts the number of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.any_response cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010004  00    Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.l2_hit cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040004  00    Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.l2_miss.hitm_other_core cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000004  00    Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000004  00    Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.outstanding cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000004  00    Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.any_response cache Counts demand cacheable data reads of full cache lines have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010001  00    Counts demand cacheable data reads of full cache lines have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.l2_hit cache Counts demand cacheable data reads of full cache lines hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040001  00    Counts demand cacheable data reads of full cache lines hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.l2_miss.hitm_other_core cache Counts demand cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000001  00    Counts demand cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000001  00    Counts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.outstanding cache Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000001  00    Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.any_response cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010002  00    Counts demand reads for ownership (RFO) requests generated by a write to full data cache line have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.l2_hit cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040002  00    Counts demand reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.l2_miss.hitm_other_core cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000002  00    Counts demand reads for ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.l2_miss.snoop_miss_or_no_snoop_needed cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000002  00    Counts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.outstanding cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000002  00    Counts demand reads for ownership (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.any_response cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010800  00    Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_hit cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040800  00    Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_miss.hitm_other_core cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000800  00    Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_miss.snoop_miss_or_no_snoop_needed cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000800  00    Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.outstanding cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000800  00    Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.any_response cache Counts data cache line reads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000012000  00    Counts data cache line reads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.l2_hit cache Counts data cache line reads generated by hardware L1 data cache prefetcher hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000042000  00    Counts data cache line reads generated by hardware L1 data cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.l2_miss.hitm_other_core cache Counts data cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000002000  00    Counts data cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200002000  00    Counts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.outstanding cache Counts data cache line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000002000  00    Counts data cache line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.any_response cache Counts data cacheline reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010010  00    Counts data cacheline reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.l2_hit cache Counts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040010  00    Counts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.l2_miss.hitm_other_core cache Counts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000010  00    Counts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000010  00    Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.outstanding cache Counts data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000010  00    Counts data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.any_response cache Counts reads for ownership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010020  00    Counts reads for ownership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.l2_hit cache Counts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000040020  00    Counts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.l2_miss.hitm_other_core cache Counts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000020  00    Counts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.l2_miss.snoop_miss_or_no_snoop_needed cache Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000020  00    Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.outstanding cache Counts reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000020  00    Counts reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.streaming_stores.any_response cache Counts any data writes to uncacheable write combining (USWC) memory region  have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000014800  00    Counts any data writes to uncacheable write combining (USWC) memory region  have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.streaming_stores.l2_hit cache Counts any data writes to uncacheable write combining (USWC) memory region  hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000044800  00    Counts any data writes to uncacheable write combining (USWC) memory region  hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.streaming_stores.l2_miss.hitm_other_core cache Counts any data writes to uncacheable write combining (USWC) memory region  miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000004800  00    Counts any data writes to uncacheable write combining (USWC) memory region  miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.streaming_stores.l2_miss.snoop_miss_or_no_snoop_needed cache Counts any data writes to uncacheable write combining (USWC) memory region  true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200004800  00    Counts any data writes to uncacheable write combining (USWC) memory region  true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.streaming_stores.outstanding cache Counts any data writes to uncacheable write combining (USWC) memory region  outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000004800  00    Counts any data writes to uncacheable write combining (USWC) memory region  outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.any_response cache Counts data cache lines requests by software prefetch instructions have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=1,offcore_rsp=0x0000011000  00    Counts data cache lines requests by software prefetch instructions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.l2_hit cache Counts data cache lines requests by software prefetch instructions hit the L2 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x0000041000  00    Counts data cache lines requests by software prefetch instructions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.l2_miss.hitm_other_core cache Counts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=1,offcore_rsp=0x1000001000  00    Counts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.l2_miss.snoop_miss_or_no_snoop_needed cache Counts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=1,offcore_rsp=0x0200001000  00    Counts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.outstanding cache Counts data cache lines requests by software prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000001000  00    Counts data cache lines requests by software prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) machine_clears.fp_assist floating point Machine clears due to FP assists event=0xc3,period=20003,umask=4  00    Counts machine clears due to floating point (FP) operations needing assists.  For instance, if the result was a floating point denormal, the hardware clears the pipeline and reissues uops to produce the correct IEEE compliant denormal result uops_retired.fpdiv floating point Floating point divide uops retired (Precise Event Capable) (Must be precise) event=0xc2,period=2000003,umask=8  00    Counts the number of floating point divide uops retired (Must be precise) machine_clears.memory_ordering memory Machine clears due to memory ordering issue event=0xc3,period=20003,umask=2  00    Counts machine clears due to memory ordering issues.  This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved - as another core is in the process of modifying the data fetch_stall.itlb_fill_pending_cycles other Cycles the code-fetch stalls and an ITLB miss is outstanding event=0x86,period=200003,umask=1  00    Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss.  Note: this event is not the same as page walk cycles to retrieve an instruction translation br_misp_retired.non_return_ind pipeline Retired mispredicted instructions of near indirect Jmp or near indirect call (Precise event capable) (Must be precise) event=0xc5,period=200003,umask=0xeb  00    Counts mispredicted branch instructions retired that were near indirect call or near indirect jmp, where the target address taken was not what the processor predicted (Must be precise) cpu_clk_unhalted.ref pipeline Reference cycles when core is not halted event=0x0,umask=0x03,period=2000003  00    Reference cycles when core is not halted.  This event uses a (_P)rogrammable general purpose performance counter inst_retired.any pipeline Instructions retired (Fixed event) (Must be precise) event=0xc0,period=2000003  00    Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers.  This event uses fixed counter 0.  You cannot collect a PEBs record for this event (Must be precise) inst_retired.prec_dist pipeline Instructions retired - using Reduced Skid PEBS feature (Must be precise) event=0xc0,period=2000003  00    Counts INST_RETIRED.ANY using the Reduced Skid PEBS feature that reduces the shadow in which events aren't counted allowing for a more unbiased distribution of samples across instructions retired (Must be precise) machine_clears.all pipeline All machine clears event=0xc3,period=20003  00    Counts machine clears for any reason machine_clears.disambiguation pipeline Machine clears due to memory disambiguation event=0xc3,period=20003,umask=8  00    Counts machine clears due to memory disambiguation.  Memory disambiguation happens when a load which has been issued conflicts with a previous unretired store in the pipeline whose address was not known at issue time, but is later resolved to be the same as the load address machine_clears.page_fault pipeline Machines clear due to a page fault event=0xc3,period=20003,umask=0x20  00    Counts the number of times that the machines clears due to a page fault. Covers both I-side and D-side(Loads/Stores) page faults. A page fault occurs when either page is not present, or an access violation machine_clears.smc pipeline Self-Modifying Code detected event=0xc3,period=20003,umask=1  00    Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification.  Self-modifying code (SMC) causes a severe penalty in all Intel(R) architecture processors uops_retired.idiv pipeline Integer divide uops retired (Precise Event Capable) (Must be precise) event=0xc2,period=2000003,umask=0x10  00    Counts the number of integer divide uops retired (Must be precise) dtlb_load_misses.walk_completed_1gb virtual memory Page walk completed due to a demand load to a 1GB page event=8,period=200003,umask=8  00    Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 1GB pages.  The page walks can end with or without a page fault dtlb_load_misses.walk_completed_2m_4m virtual memory Page walk completed due to a demand load to a 2M or 4M page event=8,period=200003,umask=4  00    Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 2M or 4M pages.  The page walks can end with or without a page fault dtlb_load_misses.walk_completed_4k virtual memory Page walk completed due to a demand load to a 4K page event=8,period=200003,umask=2  00    Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 4K pages.  The page walks can end with or without a page fault dtlb_load_misses.walk_pending virtual memory Page walks outstanding due to a demand load every cycle event=8,period=200003,umask=0x10  00    Counts once per cycle for each page walk occurring due to a load (demand data loads or SW prefetches). Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks dtlb_store_misses.walk_completed_1gb virtual memory Page walk completed due to a demand data store to a 1GB page event=0x49,period=2000003,umask=8  00    Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 1GB pages.  The page walks can end with or without a page fault dtlb_store_misses.walk_completed_2m_4m virtual memory Page walk completed due to a demand data store to a 2M or 4M page event=0x49,period=2000003,umask=4  00    Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M or 4M pages.  The page walks can end with or without a page fault dtlb_store_misses.walk_completed_4k virtual memory Page walk completed due to a demand data store to a 4K page event=0x49,period=2000003,umask=2  00    Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages.  The page walks can end with or without a page fault dtlb_store_misses.walk_pending virtual memory Page walks outstanding due to a demand data store every cycle event=0x49,period=200003,umask=0x10  00    Counts once per cycle for each page walk occurring due to a demand data store. Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks ept.walk_pending virtual memory Page walks outstanding due to walking the EPT every cycle event=0x4f,period=200003,umask=0x10  00    Counts once per cycle for each page walk only while traversing the Extended Page Table (EPT), and does not count during the rest of the translation.  The EPT is used for translating Guest-Physical Addresses to Physical Addresses for Virtual Machine Monitors (VMMs).  Average cycles per walk can be calculated by dividing the count by number of walks itlb_misses.walk_completed_1gb virtual memory Page walk completed due to an instruction fetch in a 1GB page event=0x85,period=2000003,umask=8  00    Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 1GB pages.  The page walks can end with or without a page fault itlb_misses.walk_completed_2m_4m virtual memory Page walk completed due to an instruction fetch in a 2M or 4M page event=0x85,period=2000003,umask=4  00    Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 2M or 4M pages.  The page walks can end with or without a page fault itlb_misses.walk_completed_4k virtual memory Page walk completed due to an instruction fetch in a 4K page event=0x85,period=2000003,umask=2  00    Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 4K pages.  The page walks can end with or without a page fault itlb_misses.walk_pending virtual memory Page walks outstanding due to an instruction fetch every cycle event=0x85,period=200003,umask=0x10  00    Counts once per cycle for each page walk occurring due to an instruction fetch. Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks tlb_flushes.stlb_any virtual memory STLB flushes event=0xbd,period=20003,umask=0x20  00    Counts STLB flushes.  The TLBs are flushed on instructions like INVLPG and MOV to CR3 mem_bound_stalls_ifetch.all cache Counts the number of unhalted cycles when the core is stalled due to an instruction cache or TLB miss event=0x35,period=1000003,umask=0x7f  00     mem_bound_stalls_ifetch.llc_hit cache Counts the number of unhalted cycles when the core is stalled due to an ICACHE or ITLB miss which hit in the LLC. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros event=0x35,period=1000003,umask=6  00     mem_bound_stalls_ifetch.llc_miss cache Counts the number of unhalted cycles when the core is stalled due to an ICACHE or ITLB miss which missed all the caches. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss event=0x35,period=1000003,umask=0x78  00     mem_bound_stalls_load.llc_hit cache Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros event=0x34,period=1000003,umask=6  00     mem_load_uops_l3_miss_retired.local_dram cache Counts the number of load ops retired that miss the L3 cache and hit in DRAM event=0xd3,period=1000003,umask=1  00     ocr.demand_data_rd.l3_miss memory Counts demand data reads that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00001  00    Counts demand data reads that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.demand_rfo.l3_miss memory Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00002  00    Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. Available PDIST counters: 0 topdown_bad_speculation.all pipeline Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION.ALL_P] event=0x73,period=1000003  00    Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION.ALL_P] topdown_bad_speculation.all_p pipeline Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION.ALL] event=0x73,period=1000003  00    Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION.ALL] topdown_be_bound.all pipeline Counts the number of retirement slots not consumed due to backend stalls [This event is alias to TOPDOWN_BE_BOUND.ALL_P] event=0x74,period=1000003  00     topdown_be_bound.all_p pipeline Counts the number of retirement slots not consumed due to backend stalls [This event is alias to TOPDOWN_BE_BOUND.ALL] event=0x74,period=1000003  00     topdown_fe_bound.all pipeline Counts the number of retirement slots not consumed due to front end stalls [This event is alias to TOPDOWN_FE_BOUND.ALL_P] event=0x71,period=1000003  00     topdown_fe_bound.all_p pipeline Counts the number of retirement slots not consumed due to front end stalls [This event is alias to TOPDOWN_FE_BOUND.ALL] event=0x71,period=1000003  00     topdown_retiring.all pipeline Counts the number of consumed retirement slots. [This event is alias to TOPDOWN_RETIRING.ALL_P] event=0x72,period=1000003  00     topdown_retiring.all_p pipeline Counts the number of consumed retirement slots. [This event is alias to TOPDOWN_RETIRING.ALL] event=0x72,period=1000003  00     uncore_chacms unc_chacms_clockticks uncore cache Clockticks for CMS units attached to CHA event=1  01     unc_chacms_ring_src_thrtl uncore cache Counts the number of cycles FAST trigger is received from the global FAST distress wire event=0x34  01     unc_cha_clockticks uncore cache Number of CHA clock cycles while the event is enabled event=1  01    Clockticks of the uncore caching and home agent (CHA) unc_cha_distress_asserted.dpt_any uncore cache Distress signal assertion for dynamic prefetch throttle (DPT).  Threshold for distress signal assertion reached in TOR or IRQ (immediate cause for triggering) event=0x59,umask=3  01     unc_cha_distress_asserted.dpt_irq uncore cache Distress signal assertion for dynamic prefetch throttle (DPT).  Threshold for distress signal assertion reached in IRQ (immediate cause for triggering) event=0x59,umask=1  01     unc_cha_distress_asserted.dpt_tor uncore cache Distress signal assertion for dynamic prefetch throttle (DPT).  Threshold for distress signal assertion reached in TOR (immediate cause for triggering) event=0x59,umask=2  01     unc_cha_imc_writes_count.full uncore cache Counts when a normal (Non-Isochronous) full line write is issued from the CHA to the any of the memory controller channels event=0x5b,umask=1  01     unc_cha_imc_writes_count.full_priority uncore cache CHA to iMC Full Line Writes Issued : ISOCH Full Line : Counts the total number of full line writes issued from the HA into the memory controller event=0x5b,umask=4  01     unc_cha_imc_writes_count.partial uncore cache CHA to iMC Full Line Writes Issued : Partial Non-ISOCH : Counts the total number of full line writes issued from the HA into the memory controller event=0x5b,umask=2  01     unc_cha_imc_writes_count.partial_priority uncore cache CHA to iMC Full Line Writes Issued : ISOCH Partial : Counts the total number of full line writes issued from the HA into the memory controller event=0x5b,umask=8  01     unc_cha_llc_lookup.code uncore cache Cache Lookups: CRd Requests event=0x34,umask=0x1bd0ff  01    Cache Lookups : CRd Requests unc_cha_llc_lookup.data_rd uncore cache Cache Lookups: Read Requests and Read Prefetches event=0x34,umask=0x1bc1ff  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.data_read_all uncore cache Cache Lookups: Read Requests, Read Prefetches, and Snoops event=0x34,umask=0x1fc1ff  01    Cache Lookups : Data Reads unc_cha_llc_lookup.data_read_local uncore cache Cache Lookups: Read Requests to Locally Homed Memory event=0x34,umask=0x841ff  01    Cache Lookups : Demand Data Reads, Core and LLC prefetches unc_cha_llc_lookup.data_read_miss uncore cache Cache Lookups: Read Requests, Read Prefetches, and Snoops which miss the Cache event=0x34,umask=0x1fc101  01    Cache Lookups : Data Read Misses unc_cha_llc_lookup.locally_homed_address uncore cache Cache Lookups: All Requests to Locally Homed Memory event=0x34,umask=0xbdfff  01    Cache Lookups : Transactions homed locally unc_cha_llc_lookup.local_code uncore cache Cache Lookups: Code Read Requests and Code Read Prefetches to Locally Homed Memory event=0x34,umask=0x19d0ff  01    Cache Lookups : CRd Requests unc_cha_llc_lookup.local_data_rd uncore cache Cache Lookups: Read Requests and Read Prefetches to Locally Homed Memory event=0x34,umask=0x19c1ff  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.local_dmnd_code uncore cache Cache Lookups: Code Read Requests to Locally Homed Memory event=0x34,umask=0x1850ff  01    Cache Lookups : CRd Requests unc_cha_llc_lookup.local_dmnd_data_rd uncore cache Cache Lookups: Read Requests to Locally Homed Memory event=0x34,umask=0x1841ff  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.local_dmnd_rfo uncore cache Cache Lookups: RFO Requests to Locally Homed Memory event=0x34,umask=0x1848ff  01    Cache Lookups : RFO Requests unc_cha_llc_lookup.local_llc_pf uncore cache Cache Lookups: LLC Prefetch Requests to Locally Homed Memory event=0x34,umask=0x189dff  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.local_pf uncore cache Cache Lookups: All Prefetches to Locally Homed Memory event=0x34,umask=0x199dff  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.local_pf_code uncore cache Cache Lookups: Code Prefetches to Locally Homed Memory event=0x34,umask=0x1910ff  01    Cache Lookups : CRd Requests unc_cha_llc_lookup.local_pf_data_rd uncore cache Cache Lookups: Read Prefetches to Locally Homed Memory event=0x34,umask=0x1981ff  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.local_pf_rfo uncore cache Cache Lookups: RFO Prefetches to Locally Homed Memory event=0x34,umask=0x1908ff  01    Cache Lookups : RFO Requests unc_cha_llc_lookup.local_rfo uncore cache Cache Lookups: RFO Requests and RFO Prefetches to Locally Homed Memory event=0x34,umask=0x19c8ff  01    Cache Lookups : RFO Requests unc_cha_llc_lookup.rfo uncore cache Cache Lookups: All RFO and RFO Prefetches event=0x34,umask=0x1bc8ff  01    Cache Lookups : All RFOs - Demand and Prefetches unc_cha_llc_lookup.rfo_local uncore cache Cache Lookups: RFO Requests and RFO Prefetches to Locally Homed Memory event=0x34,umask=0x9c8ff  01    Cache Lookups : Locally HOMed RFOs - Demand and Prefetches unc_cha_llc_lookup.write_local uncore cache Cache Lookups: Writes to Locally Homed Memory (includes writebacks from L1/L2) event=0x34,umask=0x842ff  01    Cache Lookups : Writes unc_cha_llc_victims.all uncore cache Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in event=0x37,umask=0xf  01    Lines Victimized : All Lines Victimized unc_cha_llc_victims.ia uncore cache Lines Victimized : IA traffic : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in event=0x37,umask=0x20  01     unc_cha_llc_victims.io uncore cache Lines Victimized : IO traffic : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in event=0x37,umask=0x10  01     unc_cha_llc_victims.local_all uncore cache Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in event=0x37,umask=0x200f  01    Lines Victimized : Local - All Lines unc_cha_llc_victims.local_e uncore cache Lines Victimized : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in event=0x37,umask=0x2002  01    Lines Victimized : Local - Lines in E State unc_cha_llc_victims.local_f uncore cache Lines Victimized : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in event=0x37,umask=0x2008  01    Lines Victimized : Local - Lines in F State unc_cha_llc_victims.local_m uncore cache Lines Victimized : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in event=0x37,umask=0x2001  01    Lines Victimized : Local - Lines in M State unc_cha_llc_victims.local_s uncore cache Lines Victimized : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in event=0x37,umask=0x2004  01    Lines Victimized : Local - Lines in S State unc_cha_llc_victims.total_e uncore cache Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in event=0x37,umask=2  01    Lines Victimized : Lines in E state unc_cha_llc_victims.total_m uncore cache Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in event=0x37,umask=1  01    Lines Victimized : Lines in M state unc_cha_llc_victims.total_s uncore cache Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in event=0x37,umask=4  01    Lines Victimized : Lines in S State unc_cha_misc.rfo_hit_s uncore cache Counts when a RFO (the Read for Ownership issued before a  write) request hit a cacheline in the S (Shared) state event=0x39,umask=8  01    Cbo Misc : RFO HitS unc_cha_osb.local_invitoe uncore cache OSB Snoop Broadcast : Local InvItoE : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB event=0x55,umask=1  01     unc_cha_osb.local_read uncore cache OSB Snoop Broadcast : Local Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB event=0x55,umask=2  01     unc_cha_osb.off_pwrheuristic uncore cache OSB Snoop Broadcast : Off : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB event=0x55,umask=0x20  01     unc_cha_osb.rfo_hits_snp_bcast uncore cache OSB Snoop Broadcast : RFO HitS Snoop Broadcast : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB event=0x55,umask=0x10  01     unc_cha_requests.invitoe uncore cache Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA event=0x50,umask=0x30  01    HA Read and Write Requests : InvalItoE unc_cha_requests.invitoe_local uncore cache Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA event=0x50,umask=0x10  01     unc_cha_requests.reads uncore cache Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a  write)  event=0x50,umask=3  01    HA Read and Write Requests : Reads unc_cha_requests.reads_local uncore cache Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a  write) event=0x50,umask=1  01     unc_cha_requests.writes uncore cache Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc event=0x50,umask=0xc  01    HA Read and Write Requests : Writes unc_cha_requests.writes_local uncore cache Counts  write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc event=0x50,umask=4  01     unc_cha_rxc_inserts.irq uncore cache Ingress (from CMS) Allocations : IRQ : Counts number of allocations per cycle into the specified Ingress queue event=0x13,umask=1  01     unc_cha_rxc_occupancy.irq uncore cache Ingress (from CMS) Occupancy : IRQ : Counts number of entries in the specified Ingress queue in each cycle event=0x11,umask=1  01     unc_cha_tor_inserts.all uncore cache All TOR Inserts event=0x35,umask=0xc001ffff  01    TOR Inserts : All unc_cha_tor_inserts.ia uncore cache All locally initiated requests from IA Cores event=0x35,umask=0xc001ff01  01    TOR Inserts : All requests from iA Cores unc_cha_tor_inserts.ia_clflush uncore cache CLFlush events that are initiated from the Core event=0x35,umask=0xc8c7ff01  01    TOR Inserts : CLFlushes issued by iA Cores unc_cha_tor_inserts.ia_clflushopt uncore cache CLFlushOpt events that are initiated from the Core event=0x35,umask=0xc8d7ff01  01    TOR Inserts : CLFlushOpts issued by iA Cores unc_cha_tor_inserts.ia_crd uncore cache Code read from local IA event=0x35,umask=0xc80fff01  01    TOR Inserts : CRDs issued by iA Cores unc_cha_tor_inserts.ia_crd_pref uncore cache Code read prefetch from local IA that miss the cache event=0x35,umask=0xc88fff01  01    TOR Inserts; Code read prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_drd_opt uncore cache Data read opt from local IA event=0x35,umask=0xc827ff01  01    TOR Inserts : DRd_Opts issued by iA Cores unc_cha_tor_inserts.ia_drd_opt_pref uncore cache Data read opt prefetch from local IA event=0x35,umask=0xc8a7ff01  01    TOR Inserts : DRd_Opt_Prefs issued by iA Cores unc_cha_tor_inserts.ia_hit uncore cache All locally initiated requests from IA Cores which hit the cache event=0x35,umask=0xc001fd01  01    TOR Inserts : All requests from iA Cores that Hit the LLC unc_cha_tor_inserts.ia_hit_crd uncore cache Code read from local IA that hit the cache event=0x35,umask=0xc80ffd01  01    TOR Inserts : CRds issued by iA Cores that Hit the LLC unc_cha_tor_inserts.ia_hit_crd_pref uncore cache Code read prefetch from local IA that hit the cache event=0x35,umask=0xc88ffd01  01    TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC unc_cha_tor_inserts.ia_hit_drd_opt uncore cache Data read opt from local IA that hit the cache event=0x35,umask=0xc827fd01  01    TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC unc_cha_tor_inserts.ia_hit_drd_opt_pref uncore cache Data read opt prefetch from local IA that hit the cache event=0x35,umask=0xc8a7fd01  01    TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC unc_cha_tor_inserts.ia_hit_itom uncore cache ItoM requests from local IA cores that hit the cache event=0x35,umask=0xcc47fd01  01    TOR Inserts : ItoMs issued by iA Cores that Hit LLC unc_cha_tor_inserts.ia_hit_llcprefcode uncore cache Last level cache prefetch code read from local IA that hit the cache event=0x35,umask=0xcccffd01  01    TOR Inserts : LLCPrefCode issued by iA Cores that hit the LLC unc_cha_tor_inserts.ia_hit_llcprefdata uncore cache Last level cache prefetch data read from local IA that hit the cache event=0x35,umask=0xccd7fd01  01    TOR Inserts : LLCPrefData issued by iA Cores that hit the LLC unc_cha_tor_inserts.ia_hit_llcprefrfo uncore cache Last level cache prefetch read for ownership from local IA that hit the cache event=0x35,umask=0xccc7fd01  01    TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC unc_cha_tor_inserts.ia_hit_rfo uncore cache Read for ownership from local IA that hit the cache event=0x35,umask=0xc807fd01  01    TOR Inserts : RFOs issued by iA Cores that Hit the LLC unc_cha_tor_inserts.ia_hit_rfo_pref uncore cache Read for ownership prefetch from local IA that hit the cache event=0x35,umask=0xc887fd01  01    TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC unc_cha_tor_inserts.ia_itom uncore cache ItoM events that are initiated from the Core event=0x35,umask=0xcc47ff01  01    TOR Inserts : ItoMs issued by iA Cores unc_cha_tor_inserts.ia_itomcachenear uncore cache ItoMCacheNear requests from local IA cores event=0x35,umask=0xcd47ff01  01    TOR Inserts : ItoMCacheNears issued by iA Cores unc_cha_tor_inserts.ia_llcprefcode uncore cache Last level cache prefetch code read from local IA event=0x35,umask=0xcccfff01  01    TOR Inserts : LLCPrefCode issued by iA Cores unc_cha_tor_inserts.ia_llcprefdata uncore cache Last level cache prefetch data read from local IA event=0x35,umask=0xccd7ff01  01    TOR Inserts : LLCPrefData issued by iA Cores unc_cha_tor_inserts.ia_llcprefrfo uncore cache Last level cache prefetch read for ownership from local IA event=0x35,umask=0xccc7ff01  01    TOR Inserts : LLCPrefRFO issued by iA Cores unc_cha_tor_inserts.ia_miss uncore cache All locally initiated requests from IA Cores which miss the cache event=0x35,umask=0xc001fe01  01    TOR Inserts : All requests from iA Cores that Missed the LLC unc_cha_tor_inserts.ia_miss_crd uncore cache Code read from local IA that miss the cache event=0x35,umask=0xc80ffe01  01    TOR Inserts : CRds issued by iA Cores that Missed the LLC unc_cha_tor_inserts.ia_miss_crd_local uncore cache CRDs from local IA cores to locally homed memory event=0x35,umask=0xc80efe01  01    TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally unc_cha_tor_inserts.ia_miss_crd_pref uncore cache Code read prefetch from local IA that miss the cache event=0x35,umask=0xc88ffe01  01    TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC unc_cha_tor_inserts.ia_miss_crd_pref_local uncore cache CRD Prefetches from local IA cores to locally homed memory event=0x35,umask=0xc88efe01  01    TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally unc_cha_tor_inserts.ia_miss_drd_opt uncore cache Data read opt from local IA that miss the cache event=0x35,umask=0xc827fe01  01    TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC unc_cha_tor_inserts.ia_miss_drd_opt_local uncore cache Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd_Opt, and which target local memory event=0x35,umask=0xc826fe01  01    TOR Inserts : DRd_Opt issued by iA Cores that Missed the LLC - HOMed locally unc_cha_tor_inserts.ia_miss_drd_opt_pref uncore cache Data read opt prefetch from local IA that miss the cache event=0x35,umask=0xc8a7fe01  01    TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC unc_cha_tor_inserts.ia_miss_drd_opt_pref_local uncore cache Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF_OPT, and target local memory event=0x35,umask=0xc8a6fe01  01    TOR Inserts : Data read opt prefetch from local iA that missed the LLC targeting local memory unc_cha_tor_inserts.ia_miss_itom uncore cache ItoM requests from local IA cores that miss the cache event=0x35,umask=0xcc47fe01  01    TOR Inserts : ItoMs issued by iA Cores that Missed LLC unc_cha_tor_inserts.ia_miss_llcprefcode uncore cache Last level cache prefetch code read from local IA that miss the cache event=0x35,umask=0xcccffe01  01    TOR Inserts : LLCPrefCode issued by iA Cores that missed the LLC unc_cha_tor_inserts.ia_miss_llcprefdata uncore cache Last level cache prefetch data read from local IA that miss the cache event=0x35,umask=0xccd7fe01  01    TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC unc_cha_tor_inserts.ia_miss_llcprefrfo uncore cache Last level cache prefetch read for ownership from local IA that miss the cache event=0x35,umask=0xccc7fe01  01    TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC unc_cha_tor_inserts.ia_miss_local_wcilf_ddr uncore cache WCILF requests from local IA cores to locally homed DDR addresses that miss the cache event=0x35,umask=0xc8668601  01    TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally unc_cha_tor_inserts.ia_miss_local_wcil_ddr uncore cache WCIL requests from local IA cores to locally homed DDR addresses that miss the cache event=0x35,umask=0xc86e8601  01    TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally unc_cha_tor_inserts.ia_miss_rfo uncore cache Read for ownership from local IA that miss the cache event=0x35,umask=0xc807fe01  01    TOR Inserts : RFOs issued by iA Cores that Missed the LLC unc_cha_tor_inserts.ia_miss_rfo_local uncore cache Read for ownership from local IA that miss the LLC targeting local memory event=0x35,umask=0xc806fe01  01    TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally unc_cha_tor_inserts.ia_miss_rfo_pref uncore cache Read for ownership prefetch from local IA that miss the cache event=0x35,umask=0xc887fe01  01    TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC unc_cha_tor_inserts.ia_miss_rfo_pref_local uncore cache Read for ownership prefetch from local IA that miss the LLC targeting local memory event=0x35,umask=0xc886fe01  01    TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally unc_cha_tor_inserts.ia_miss_ucrdf uncore cache UCRDF requests from local IA cores that miss the cache event=0x35,umask=0xc877de01  01    TOR Inserts : UCRdFs issued by iA Cores that Missed LLC unc_cha_tor_inserts.ia_miss_wcil uncore cache WCIL requests from a local IA core that miss the cache event=0x35,umask=0xc86ffe01  01    TOR Inserts : WCiLs issued by iA Cores that Missed the LLC unc_cha_tor_inserts.ia_miss_wcilf uncore cache WCILF requests from local IA core that miss the cache event=0x35,umask=0xc867fe01  01    TOR Inserts : WCiLF issued by iA Cores that Missed the LLC unc_cha_tor_inserts.ia_miss_wcilf_ddr uncore cache WCILF requests from local IA cores to DDR homed addresses which miss the cache event=0x35,umask=0xc8678601  01    TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC unc_cha_tor_inserts.ia_miss_wcil_ddr uncore cache WCIL requests from local IA cores to DDR homed addresses which miss the cache event=0x35,umask=0xc86f8601  01    TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC unc_cha_tor_inserts.ia_miss_wil uncore cache WIL requests from local IA cores that miss the cache event=0x35,umask=0xc87fde01  01    TOR Inserts : WiLs issued by iA Cores that Missed LLC unc_cha_tor_inserts.ia_rfo uncore cache Read for ownership from local IA event=0x35,umask=0xc807ff01  01    TOR Inserts : RFOs issued by iA Cores unc_cha_tor_inserts.ia_rfo_pref uncore cache Read for ownership prefetch from local IA event=0x35,umask=0xc887ff01  01    TOR Inserts : RFO_Prefs issued by iA Cores unc_cha_tor_inserts.ia_specitom uncore cache SpecItoM events that are initiated from the Core event=0x35,umask=0xcc57ff01  01    TOR Inserts : SpecItoMs issued by iA Cores unc_cha_tor_inserts.ia_wbeftoe uncore cache WbEFtoEs issued by iA Cores.  (Non Modified Write Backs) event=0x35,umask=0xcc3fff01  01    TOR Inserts : ItoMs issued by IO Devices that Hit the LLC unc_cha_tor_inserts.ia_wbeftoi uncore cache WbEFtoIs issued by iA Cores .  (Non Modified Write Backs) event=0x35,umask=0xcc37ff01  01    TOR Inserts : ItoMs issued by IO Devices that Hit the LLC unc_cha_tor_inserts.ia_wbmtoe uncore cache WbMtoEs issued by iA Cores .  (Modified Write Backs) event=0x35,umask=0xcc2fff01  01    TOR Inserts : ItoMs issued by IO Devices that Hit the LLC unc_cha_tor_inserts.ia_wbmtoi uncore cache WbMtoI requests from local IA cores event=0x35,umask=0xcc27ff01  01    TOR Inserts : WbMtoIs issued by iA Cores unc_cha_tor_inserts.ia_wbstoi uncore cache WbStoIs issued by iA Cores .  (Non Modified Write Backs) event=0x35,umask=0xcc67ff01  01    TOR Inserts : ItoMs issued by IO Devices that Hit the LLC unc_cha_tor_inserts.ia_wcil uncore cache WCIL requests from a local IA core event=0x35,umask=0xc86fff01  01    TOR Inserts : WCiLs issued by iA Cores unc_cha_tor_inserts.ia_wcilf uncore cache WCILF requests from local IA core event=0x35,umask=0xc867ff01  01    TOR Inserts : WCiLF issued by iA Cores unc_cha_tor_inserts.io uncore cache All TOR inserts from local IO devices event=0x35,umask=0xc001ff04  01    TOR Inserts : All requests from IO Devices unc_cha_tor_inserts.io_clflush uncore cache CLFlush requests from IO devices event=0x35,umask=0xc8c3ff04  01    TOR Inserts : CLFlushes issued by IO Devices unc_cha_tor_inserts.io_hit uncore cache All TOR inserts from local IO devices which hit the cache event=0x35,umask=0xc001fd04  01    TOR Inserts : All requests from IO Devices that hit the LLC unc_cha_tor_inserts.io_hit_itom uncore cache ItoMs from local IO devices which hit the cache event=0x35,umask=0xcc43fd04  01    TOR Inserts : ItoMs issued by IO Devices that Hit the LLC unc_cha_tor_inserts.io_hit_itomcachenear uncore cache ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC event=0x35,umask=0xcd43fd04  01    TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC unc_cha_tor_inserts.io_hit_pcirdcur uncore cache PCIRDCURs issued by IO devices which hit the LLC event=0x35,umask=0xc8f3fd04  01    TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC unc_cha_tor_inserts.io_hit_rfo uncore cache RFOs from local IO devices which hit the cache event=0x35,umask=0xc803fd04  01    TOR Inserts : RFOs issued by IO Devices that hit the LLC unc_cha_tor_inserts.io_itom uncore cache All TOR ItoM inserts from local IO devices event=0x35,umask=0xcc43ff04  01    TOR Inserts : ItoMs issued by IO Devices unc_cha_tor_inserts.io_itomcachenear uncore cache ItoMCacheNears, indicating a partial write request, from IO Devices event=0x35,umask=0xcd43ff04  01    TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices unc_cha_tor_inserts.io_miss uncore cache All TOR inserts from local IO devices which miss the cache event=0x35,umask=0xc001fe04  01    TOR Inserts : All requests from IO Devices that missed the LLC unc_cha_tor_inserts.io_miss_itom uncore cache All TOR ItoM inserts from local IO devices which miss the cache event=0x35,umask=0xcc43fe04  01    TOR Inserts : ItoMs issued by IO Devices that missed the LLC unc_cha_tor_inserts.io_miss_itomcachenear uncore cache ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC event=0x35,umask=0xcd43fe04  01    TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC unc_cha_tor_inserts.io_miss_pcirdcur uncore cache PCIRDCURs issued by IO devices which miss the LLC event=0x35,umask=0xc8f3fe04  01    TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC unc_cha_tor_inserts.io_miss_rfo uncore cache All TOR RFO inserts from local IO devices which miss the cache event=0x35,umask=0xc803fe04  01    TOR Inserts : RFOs issued by IO Devices that missed the LLC unc_cha_tor_inserts.io_pcirdcur uncore cache PCIRDCURs issued by IO devices event=0x35,umask=0xc8f3ff04  01    TOR Inserts : PCIRdCurs issued by IO Devices unc_cha_tor_inserts.io_rfo uncore cache RFOs from local IO devices event=0x35,umask=0xc803ff04  01    TOR Inserts : RFOs issued by IO Devices unc_cha_tor_inserts.io_wbmtoi uncore cache WBMtoI requests from IO devices event=0x35,umask=0xcc23ff04  01    TOR Inserts : WbMtoIs issued by IO Devices unc_cha_tor_inserts.llc_or_sf_evictions uncore cache TOR Inserts for SF or LLC Evictions event=0x35,umask=0xc001ff02  01    TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ) unc_cha_tor_inserts.loc_all uncore cache All locally initiated requests event=0x35,umask=0xc000ff05  01    TOR Inserts : All from Local iA and IO unc_cha_tor_inserts.loc_ia uncore cache All from Local iA event=0x35,umask=0xc000ff01  01    TOR Inserts : All from Local iA unc_cha_tor_inserts.loc_io uncore cache All from Local IO event=0x35,umask=0xc000ff04  01    TOR Inserts : All from Local IO unc_cha_tor_occupancy.all uncore cache Occupancy for all TOR entries event=0x36,umask=0xc001ffff  01    TOR Occupancy : All unc_cha_tor_occupancy.ia uncore cache TOR Occupancy for All locally initiated requests from IA Cores event=0x36,umask=0xc001ff01  01    TOR Occupancy : All requests from iA Cores unc_cha_tor_occupancy.ia_clflush uncore cache TOR Occupancy for CLFlush events that are initiated from the Core event=0x36,umask=0xc8c7ff01  01    TOR Occupancy : CLFlushes issued by iA Cores unc_cha_tor_occupancy.ia_clflushopt uncore cache TOR Occupancy for CLFlushOpt events that are initiated from the Core event=0x36,umask=0xc8d7ff01  01    TOR Occupancy : CLFlushOpts issued by iA Cores unc_cha_tor_occupancy.ia_crd uncore cache TOR Occupancy for Code read from local IA that miss the cache event=0x36,umask=0xc80fff01  01    TOR Occupancy : CRDs issued by iA Cores unc_cha_tor_occupancy.ia_crd_pref uncore cache TOR Occupancy for Code read prefetch from local IA that miss the cache event=0x36,umask=0xc88fff01  01    TOR Occupancy; Code read prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_drd_opt uncore cache TOR Occupancy for Data read opt from local IA that miss the cache event=0x36,umask=0xc827ff01  01    TOR Occupancy : DRd_Opts issued by iA Cores unc_cha_tor_occupancy.ia_drd_opt_pref uncore cache TOR Occupancy for Data read opt prefetch from local IA that miss the cache event=0x36,umask=0xc8a7ff01  01    TOR Occupancy : DRd_Opt_Prefs issued by iA Cores unc_cha_tor_occupancy.ia_hit uncore cache TOR Occupancy for All locally initiated requests from IA Cores which hit the cache event=0x36,umask=0xc001fd01  01    TOR Occupancy : All requests from iA Cores that Hit the LLC unc_cha_tor_occupancy.ia_hit_crd uncore cache TOR Occupancy for Code read from local IA that hit the cache event=0x36,umask=0xc80ffd01  01    TOR Occupancy : CRds issued by iA Cores that Hit the LLC unc_cha_tor_occupancy.ia_hit_crd_pref uncore cache TOR Occupancy for Code read prefetch from local IA that hit the cache event=0x36,umask=0xc88ffd01  01    TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC unc_cha_tor_occupancy.ia_hit_drd_opt uncore cache TOR Occupancy for Data read opt from local IA that hit the cache event=0x36,umask=0xc827fd01  01    TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC unc_cha_tor_occupancy.ia_hit_drd_opt_pref uncore cache TOR Occupancy for Data read opt prefetch from local IA that hit the cache event=0x36,umask=0xc8a7fd01  01    TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC unc_cha_tor_occupancy.ia_hit_itom uncore cache TOR Occupancy for ItoM requests from local IA cores that hit the cache event=0x36,umask=0xcc47fd01  01    TOR Occupancy : ItoMs issued by iA Cores that Hit LLC unc_cha_tor_occupancy.ia_hit_llcprefcode uncore cache TOR Occupancy for Last level cache prefetch code read from local IA that hit the cache event=0x36,umask=0xcccffd01  01    TOR Occupancy : LLCPrefCode issued by iA Cores that hit the LLC unc_cha_tor_occupancy.ia_hit_llcprefdata uncore cache TOR Occupancy for Last level cache prefetch data read from local IA that hit the cache event=0x36,umask=0xccd7fd01  01    TOR Occupancy : LLCPrefData issued by iA Cores that hit the LLC unc_cha_tor_occupancy.ia_hit_llcprefrfo uncore cache TOR Occupancy for Last level cache prefetch read for ownership from local IA that hit the cache event=0x36,umask=0xccc7fd01  01    TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC unc_cha_tor_occupancy.ia_hit_rfo uncore cache TOR Occupancy for Read for ownership from local IA that hit the cache event=0x36,umask=0xc807fd01  01    TOR Occupancy : RFOs issued by iA Cores that Hit the LLC unc_cha_tor_occupancy.ia_hit_rfo_pref uncore cache TOR Occupancy for Read for ownership prefetch from local IA that hit the cache event=0x36,umask=0xc887fd01  01    TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC unc_cha_tor_occupancy.ia_itom uncore cache TOR Occupancy for ItoM events that are initiated from the Core event=0x36,umask=0xcc47ff01  01    TOR Occupancy : ItoMs issued by iA Cores unc_cha_tor_occupancy.ia_itomcachenear uncore cache TOR Occupancy for ItoMCacheNear requests from local IA cores event=0x36,umask=0xcd47ff01  01    TOR Occupancy : ItoMCacheNears issued by iA Cores unc_cha_tor_occupancy.ia_llcprefcode uncore cache TOR Occupancy for Last level cache prefetch code read from local IA event=0x36,umask=0xcccfff01  01    TOR Occupancy : LLCPrefCode issued by iA Cores unc_cha_tor_occupancy.ia_llcprefdata uncore cache TOR Occupancy for Last level cache prefetch data read from local IA event=0x36,umask=0xccd7ff01  01    TOR Occupancy : LLCPrefData issued by iA Cores unc_cha_tor_occupancy.ia_llcprefrfo uncore cache TOR Occupancy for Last level cache prefetch read for ownership from local IA that miss the cache event=0x36,umask=0xccc7ff01  01    TOR Occupancy : LLCPrefRFO issued by iA Cores unc_cha_tor_occupancy.ia_miss uncore cache TOR Occupancy for All locally initiated requests from IA Cores which miss the cache event=0x36,umask=0xc001fe01  01    TOR Occupancy : All requests from iA Cores that Missed the LLC unc_cha_tor_occupancy.ia_miss_crd uncore cache TOR Occupancy for Code read from local IA that miss the cache event=0x36,umask=0xc80ffe01  01    TOR Occupancy : CRds issued by iA Cores that Missed the LLC unc_cha_tor_occupancy.ia_miss_crd_local uncore cache TOR Occupancy for CRDs from local IA cores to locally homed memory event=0x36,umask=0xc80efe01  01    TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally unc_cha_tor_occupancy.ia_miss_crd_pref uncore cache TOR Occupancy for Code read prefetch from local IA that miss the cache event=0x36,umask=0xc88ffe01  01    TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC unc_cha_tor_occupancy.ia_miss_crd_pref_local uncore cache TOR Occupancy for CRD Prefetches from local IA cores to locally homed memory event=0x36,umask=0xc88efe01  01    TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally unc_cha_tor_occupancy.ia_miss_drd_opt uncore cache TOR Occupancy for Data read opt from local IA that miss the cache event=0x36,umask=0xc827fe01  01    TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC unc_cha_tor_occupancy.ia_miss_drd_opt_pref uncore cache TOR Occupancy for Data read opt prefetch from local IA that miss the cache event=0x36,umask=0xc8a7fe01  01    TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC unc_cha_tor_occupancy.ia_miss_itom uncore cache TOR Occupancy for ItoM requests from local IA cores that miss the cache event=0x36,umask=0xcc47fe01  01    TOR Occupancy : ItoMs issued by iA Cores that Missed LLC unc_cha_tor_occupancy.ia_miss_llcprefcode uncore cache TOR Occupancy for Last level cache prefetch code read from local IA that miss the cache event=0x36,umask=0xcccffe01  01    TOR Occupancy : LLCPrefCode issued by iA Cores that missed the LLC unc_cha_tor_occupancy.ia_miss_llcprefdata uncore cache TOR Occupancy for Last level cache prefetch data read from local IA that miss the cache event=0x36,umask=0xccd7fe01  01    TOR Occupancy : LLCPrefData issued by iA Cores that missed the LLC unc_cha_tor_occupancy.ia_miss_llcprefrfo uncore cache TOR Occupancy for Last level cache prefetch read for ownership from local IA that miss the cache event=0x36,umask=0xccc7fe01  01    TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC unc_cha_tor_occupancy.ia_miss_local_wcilf_ddr uncore cache TOR Occupancy for WCILF requests from local IA cores to locally homed DDR addresses that miss the cache event=0x36,umask=0xc8668601  01    TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally unc_cha_tor_occupancy.ia_miss_local_wcil_ddr uncore cache TOR Occupancy for WCIL requests from local IA cores to locally homed DDR addresses that miss the cache event=0x36,umask=0xc86e8601  01    TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally unc_cha_tor_occupancy.ia_miss_rfo uncore cache TOR Occupancy for Read for ownership from local IA that miss the cache event=0x36,umask=0xc807fe01  01    TOR Occupancy : RFOs issued by iA Cores that Missed the LLC unc_cha_tor_occupancy.ia_miss_rfo_local uncore cache TOR Occupancy for Read for ownership from local IA that miss the cache event=0x36,umask=0xc806fe01  01    TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed locally unc_cha_tor_occupancy.ia_miss_rfo_pref uncore cache TOR Occupancy for Read for ownership prefetch from local IA that miss the cache event=0x36,umask=0xc887fe01  01    TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC unc_cha_tor_occupancy.ia_miss_rfo_pref_local uncore cache TOR Occupancy for Read for ownership prefetch from local IA that miss the cache event=0x36,umask=0xc886fe01  01    TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally unc_cha_tor_occupancy.ia_miss_ucrdf uncore cache TOR Occupancy for UCRDF requests from local IA cores that miss the cache event=0x36,umask=0xc877de01  01    TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC unc_cha_tor_occupancy.ia_miss_wcil uncore cache TOR Occupancy for WCIL requests from a local IA core that miss the cache event=0x36,umask=0xc86ffe01  01    TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC unc_cha_tor_occupancy.ia_miss_wcilf uncore cache TOR Occupancy for WCILF requests from local IA core that miss the cache event=0x36,umask=0xc867fe01  01    TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC unc_cha_tor_occupancy.ia_miss_wcilf_ddr uncore cache TOR Occupancy for WCILF requests from local IA cores to DDR homed addresses which miss the cache event=0x36,umask=0xc8678601  01    TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC unc_cha_tor_occupancy.ia_miss_wcil_ddr uncore cache TOR Occupancy for WCIL requests from local IA cores to DDR homed addresses which miss the cache event=0x36,umask=0xc86f8601  01    TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC unc_cha_tor_occupancy.ia_miss_wil uncore cache TOR Occupancy for WIL requests from local IA cores that miss the cache event=0x36,umask=0xc87fde01  01    TOR Occupancy : WiLs issued by iA Cores that Missed LLC unc_cha_tor_occupancy.ia_rfo uncore cache TOR Occupancy for Read for ownership from local IA that miss the cache event=0x36,umask=0xc807ff01  01    TOR Occupancy : RFOs issued by iA Cores unc_cha_tor_occupancy.ia_rfo_pref uncore cache TOR Occupancy for Read for ownership prefetch from local IA that miss the cache event=0x36,umask=0xc887ff01  01    TOR Occupancy : RFO_Prefs issued by iA Cores unc_cha_tor_occupancy.ia_specitom uncore cache TOR Occupancy for SpecItoM events that are initiated from the Core event=0x36,umask=0xcc57ff01  01    TOR Occupancy : SpecItoMs issued by iA Cores unc_cha_tor_occupancy.ia_wbmtoi uncore cache TOR Occupancy for WbMtoI requests from local IA cores event=0x36,umask=0xcc27ff01  01    TOR Occupancy : WbMtoIs issued by iA Cores unc_cha_tor_occupancy.ia_wcil uncore cache TOR Occupancy for WCIL requests from a local IA core event=0x36,umask=0xc86fff01  01    TOR Occupancy : WCiLs issued by iA Cores unc_cha_tor_occupancy.ia_wcilf uncore cache TOR Occupancy for WCILF requests from local IA core event=0x36,umask=0xc867ff01  01    TOR Occupancy : WCiLF issued by iA Cores unc_cha_tor_occupancy.io uncore cache TOR Occupancy for All TOR inserts from local IO devices event=0x36,umask=0xc001ff04  01    TOR Occupancy : All requests from IO Devices unc_cha_tor_occupancy.io_clflush uncore cache TOR Occupancy for CLFlush requests from IO devices event=0x36,umask=0xc8c3ff04  01    TOR Occupancy : CLFlushes issued by IO Devices unc_cha_tor_occupancy.io_hit uncore cache TOR Occupancy for All TOR inserts from local IO devices which hit the cache event=0x36,umask=0xc001fd04  01    TOR Occupancy : All requests from IO Devices that hit the LLC unc_cha_tor_occupancy.io_hit_itom uncore cache TOR Occupancy for ItoMs from local IO devices which hit the cache event=0x36,umask=0xcc43fd04  01    TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC unc_cha_tor_occupancy.io_hit_itomcachenear uncore cache TOR Occupancy for ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC event=0x36,umask=0xcd43fd04  01    TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC unc_cha_tor_occupancy.io_hit_pcirdcur uncore cache TOR Occupancy for PCIRDCURs issued by IO devices which hit the LLC event=0x36,umask=0xc8f3fd04  01    TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC unc_cha_tor_occupancy.io_hit_rfo uncore cache TOR Occupancy for RFOs from local IO devices which hit the cache event=0x36,umask=0xc803fd04  01    TOR Occupancy : RFOs issued by IO Devices that hit the LLC unc_cha_tor_occupancy.io_itom uncore cache TOR Occupancy for All TOR ItoM inserts from local IO devices event=0x36,umask=0xcc43ff04  01    TOR Occupancy : ItoMs issued by IO Devices unc_cha_tor_occupancy.io_itomcachenear uncore cache TOR Occupancy for ItoMCacheNears, indicating a partial write request, from IO Devices event=0x36,umask=0xcd43ff04  01    TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices unc_cha_tor_occupancy.io_miss uncore cache TOR Occupancy for All TOR inserts from local IO devices which miss the cache event=0x36,umask=0xc001fe04  01    TOR Occupancy : All requests from IO Devices that missed the LLC unc_cha_tor_occupancy.io_miss_itom uncore cache TOR Occupancy for All TOR ItoM inserts from local IO devices which miss the cache event=0x36,umask=0xcc43fe04  01    TOR Occupancy : ItoMs issued by IO Devices that missed the LLC unc_cha_tor_occupancy.io_miss_itomcachenear uncore cache TOR Occupancy for ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC event=0x36,umask=0xcd43fe04  01    TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC unc_cha_tor_occupancy.io_miss_pcirdcur uncore cache TOR Occupancy for PCIRDCURs issued by IO devices which miss the LLC event=0x36,umask=0xc8f3fe04  01    TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC unc_cha_tor_occupancy.io_miss_rfo uncore cache TOR Occupancy for All TOR RFO inserts from local IO devices which miss the cache event=0x36,umask=0xc803fe04  01    TOR Occupancy : RFOs issued by IO Devices that missed the LLC unc_cha_tor_occupancy.io_pcirdcur uncore cache TOR Occupancy for PCIRDCURs issued by IO devices event=0x36,umask=0xc8f3ff04  01    TOR Occupancy : PCIRdCurs issued by IO Devices unc_cha_tor_occupancy.io_rfo uncore cache TOR Occupancy for RFOs from local IO devices event=0x36,umask=0xc803ff04  01    TOR Occupancy : RFOs issued by IO Devices unc_cha_tor_occupancy.io_wbmtoi uncore cache TOR Occupancy for WBMtoI requests from IO devices event=0x36,umask=0xcc23ff04  01    TOR Occupancy : WbMtoIs issued by IO Devices unc_cha_tor_occupancy.loc_all uncore cache TOR Occupancy for All locally initiated requests event=0x36,umask=0xc000ff05  01    TOR Occupancy : All from Local iA and IO unc_cha_tor_occupancy.loc_ia uncore cache TOR Occupancy for All from Local iA event=0x36,umask=0xc000ff01  01    TOR Occupancy : All from Local iA unc_cha_tor_occupancy.loc_io uncore cache TOR Occupancy for All from Local IO event=0x36,umask=0xc000ff04  01    TOR Occupancy : All from Local IO uncore_b2cmi unc_b2cmi_clockticks uncore interconnect Clockticks of the mesh to memory (B2CMI) event=1  01     unc_b2cmi_direct2core_taken uncore interconnect Counts the number of times B2CMI egress did D2C (direct to core) event=0x16,umask=1  01     unc_b2cmi_direct2core_txn_override uncore interconnect Counts the number of times D2C wasn't honoured even though the incoming request had d2c set for non cisgress txn event=0x18,umask=1  01     unc_b2cmi_imc_reads.all uncore interconnect Counts any read event=0x24,umask=0x104  01     unc_b2cmi_imc_reads.normal uncore interconnect Counts normal reads issue to CMI event=0x24,umask=0x101  01     unc_b2cmi_imc_reads.to_ddr_as_mem uncore interconnect Counts reads to 1lm non persistent memory regions event=0x24,umask=0x108  01     unc_b2cmi_imc_writes.all uncore interconnect All Writes - All Channels event=0x25,umask=0x110  01     unc_b2cmi_imc_writes.full uncore interconnect Full Non-ISOCH - All Channels event=0x25,umask=0x101  01     unc_b2cmi_imc_writes.partial uncore interconnect Partial Non-ISOCH - All Channels event=0x25,umask=0x102  01     unc_b2cmi_imc_writes.to_ddr_as_mem uncore interconnect DDR - All Channels event=0x25,umask=0x120  01     unc_b2cmi_prefcam_inserts.ch0_xpt uncore interconnect Prefetch CAM Inserts : XPT - Ch 0 event=0x56,umask=1  01     unc_b2cmi_prefcam_inserts.xpt_allch uncore interconnect Prefetch CAM Inserts : XPT -All Channels event=0x56,umask=1  01    Prefetch CAM Inserts : XPT - All Channels unc_b2cmi_prefcam_occupancy.ch0 uncore interconnect Prefetch CAM Occupancy : Channel 0 event=0x54,umask=1  01     unc_b2cmi_tracker_inserts.ch0 uncore interconnect Tracker Inserts : Channel 0 event=0x32,umask=0x104  01     unc_b2cmi_tracker_occupancy.ch0 uncore interconnect Tracker Occupancy : Channel 0 event=0x33,umask=1  01     unc_b2cmi_wr_tracker_inserts.ch0 uncore interconnect Write Tracker Inserts : Channel 0 event=0x40,umask=1  01     unc_i_cache_total_occupancy.mem uncore interconnect Total Write Cache Occupancy : Mem event=0xf,umask=4  01     unc_i_clockticks uncore interconnect IRP Clockticks event=1  01     unc_i_faf_inserts uncore interconnect Inbound read requests received by the IRP and inserted into the FAF queue event=0x18  01     unc_i_misc1.lost_fwd uncore interconnect Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed event=0x1f,umask=0x10  01     unc_i_snoop_resp.all_hit_es uncore interconnect Snoop Hit E/S responses event=0x12,umask=0x74  01     unc_i_snoop_resp.all_hit_i uncore interconnect Snoop Hit I responses event=0x12,umask=0x72  01     unc_i_snoop_resp.all_hit_m uncore interconnect Snoop Hit M responses event=0x12,umask=0x78  01     unc_i_snoop_resp.all_miss uncore interconnect Snoop miss responses event=0x12,umask=0x71  01     unc_i_transactions.wr_pref uncore interconnect Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh event=0x11,umask=8  01     unc_iio_clockticks uncore io IIO Clockticks event=1  01     unc_iio_comp_buf_inserts.cmpd.all_parts uncore io PCIE Completion Buffer Inserts.  Counts once per 64 byte read issued from this PCIE device event=0xc2,ch_mask=0xff,fc_mask=7,umask=4  01     unc_iio_comp_buf_inserts.cmpd.part0 uncore io PCIE Completion Buffer Inserts.  Counts once per 64 byte read issued from this PCIE device event=0xc2,ch_mask=1,fc_mask=7,umask=4  01     unc_iio_comp_buf_inserts.cmpd.part1 uncore io PCIE Completion Buffer Inserts.  Counts once per 64 byte read issued from this PCIE device event=0xc2,ch_mask=2,fc_mask=7,umask=4  01     unc_iio_comp_buf_inserts.cmpd.part2 uncore io PCIE Completion Buffer Inserts.  Counts once per 64 byte read issued from this PCIE device event=0xc2,ch_mask=4,fc_mask=7,umask=4  01     unc_iio_comp_buf_inserts.cmpd.part3 uncore io PCIE Completion Buffer Inserts.  Counts once per 64 byte read issued from this PCIE device event=0xc2,ch_mask=8,fc_mask=7,umask=4  01     unc_iio_comp_buf_inserts.cmpd.part4 uncore io PCIE Completion Buffer Inserts.  Counts once per 64 byte read issued from this PCIE device event=0xc2,ch_mask=0x10,fc_mask=7,umask=4  01     unc_iio_comp_buf_inserts.cmpd.part5 uncore io PCIE Completion Buffer Inserts.  Counts once per 64 byte read issued from this PCIE device event=0xc2,ch_mask=0x20,fc_mask=7,umask=4  01     unc_iio_comp_buf_inserts.cmpd.part6 uncore io PCIE Completion Buffer Inserts.  Counts once per 64 byte read issued from this PCIE device event=0xc2,ch_mask=0x40,fc_mask=7,umask=4  01     unc_iio_comp_buf_inserts.cmpd.part7 uncore io PCIE Completion Buffer Inserts.  Counts once per 64 byte read issued from this PCIE device event=0xc2,ch_mask=0x80,fc_mask=7,umask=4  01     unc_iio_comp_buf_occupancy.cmpd.all_parts uncore io Count of allocations in the completion buffer event=0xd5,ch_mask=0xff,fc_mask=7,umask=0xff  01     unc_iio_comp_buf_occupancy.cmpd.part0 uncore io Count of allocations in the completion buffer event=0xd5,ch_mask=1,fc_mask=7,umask=1  01     unc_iio_comp_buf_occupancy.cmpd.part1 uncore io Count of allocations in the completion buffer event=0xd5,ch_mask=2,fc_mask=7,umask=2  01     unc_iio_comp_buf_occupancy.cmpd.part2 uncore io Count of allocations in the completion buffer event=0xd5,ch_mask=4,fc_mask=7,umask=4  01     unc_iio_comp_buf_occupancy.cmpd.part3 uncore io Count of allocations in the completion buffer event=0xd5,ch_mask=8,fc_mask=7,umask=8  01     unc_iio_comp_buf_occupancy.cmpd.part4 uncore io Count of allocations in the completion buffer event=0xd5,ch_mask=0x10,fc_mask=7,umask=0x10  01     unc_iio_comp_buf_occupancy.cmpd.part5 uncore io Count of allocations in the completion buffer event=0xd5,ch_mask=0x20,fc_mask=7,umask=0x20  01     unc_iio_comp_buf_occupancy.cmpd.part6 uncore io Count of allocations in the completion buffer event=0xd5,ch_mask=0x40,fc_mask=7,umask=0x40  01     unc_iio_comp_buf_occupancy.cmpd.part7 uncore io Count of allocations in the completion buffer event=0xd5,ch_mask=0x80,fc_mask=7,umask=0x80  01     unc_iio_data_req_by_cpu.mem_read.all_parts uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=0xff,fc_mask=7,umask=4  01     unc_iio_data_req_by_cpu.mem_read.part0 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=1,fc_mask=7,umask=4  01     unc_iio_data_req_by_cpu.mem_read.part1 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=2,fc_mask=7,umask=4  01     unc_iio_data_req_by_cpu.mem_read.part2 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=4,fc_mask=7,umask=4  01     unc_iio_data_req_by_cpu.mem_read.part3 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=8,fc_mask=7,umask=4  01     unc_iio_data_req_by_cpu.mem_read.part4 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=0x10,fc_mask=7,umask=4  01     unc_iio_data_req_by_cpu.mem_read.part5 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=0x20,fc_mask=7,umask=4  01     unc_iio_data_req_by_cpu.mem_read.part6 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=0x40,fc_mask=7,umask=4  01     unc_iio_data_req_by_cpu.mem_read.part7 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=0x80,fc_mask=7,umask=4  01     unc_iio_data_req_by_cpu.mem_write.all_parts uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=0xff,fc_mask=7,umask=1  01     unc_iio_data_req_by_cpu.mem_write.part0 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=1,fc_mask=7,umask=1  01     unc_iio_data_req_by_cpu.mem_write.part1 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=2,fc_mask=7,umask=1  01     unc_iio_data_req_by_cpu.mem_write.part2 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=4,fc_mask=7,umask=1  01     unc_iio_data_req_by_cpu.mem_write.part3 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=8,fc_mask=7,umask=1  01     unc_iio_data_req_by_cpu.mem_write.part4 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=0x10,fc_mask=7,umask=1  01     unc_iio_data_req_by_cpu.mem_write.part5 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=0x20,fc_mask=7,umask=1  01     unc_iio_data_req_by_cpu.mem_write.part6 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=0x40,fc_mask=7,umask=1  01     unc_iio_data_req_by_cpu.mem_write.part7 uncore io Data requested by the CPU : Core writing to Cards MMIO space event=0xc0,ch_mask=0x80,fc_mask=7,umask=1  01     unc_iio_data_req_of_cpu.mem_read.part0 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=1,fc_mask=7,umask=4  01     unc_iio_data_req_of_cpu.mem_read.part1 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=2,fc_mask=7,umask=4  01     unc_iio_data_req_of_cpu.mem_read.part2 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=4,fc_mask=7,umask=4  01     unc_iio_data_req_of_cpu.mem_read.part3 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=8,fc_mask=7,umask=4  01     unc_iio_data_req_of_cpu.mem_read.part4 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=0x10,fc_mask=7,umask=4  01     unc_iio_data_req_of_cpu.mem_read.part5 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=0x20,fc_mask=7,umask=4  01     unc_iio_data_req_of_cpu.mem_read.part6 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=0x40,fc_mask=7,umask=4  01     unc_iio_data_req_of_cpu.mem_read.part7 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=0x80,fc_mask=7,umask=4  01     unc_iio_data_req_of_cpu.mem_write.part0 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=1,fc_mask=7,umask=1  01     unc_iio_data_req_of_cpu.mem_write.part1 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=2,fc_mask=7,umask=1  01     unc_iio_data_req_of_cpu.mem_write.part2 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=4,fc_mask=7,umask=1  01     unc_iio_data_req_of_cpu.mem_write.part3 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=8,fc_mask=7,umask=1  01     unc_iio_data_req_of_cpu.mem_write.part4 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=0x10,fc_mask=7,umask=1  01     unc_iio_data_req_of_cpu.mem_write.part5 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=0x20,fc_mask=7,umask=1  01     unc_iio_data_req_of_cpu.mem_write.part6 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=0x40,fc_mask=7,umask=1  01     unc_iio_data_req_of_cpu.mem_write.part7 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=0x80,fc_mask=7,umask=1  01     unc_iio_data_req_of_cpu.peer_write.part0 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=1,fc_mask=7,umask=2  01     unc_iio_data_req_of_cpu.peer_write.part1 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=2,fc_mask=7,umask=2  01     unc_iio_data_req_of_cpu.peer_write.part2 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=4,fc_mask=7,umask=2  01     unc_iio_data_req_of_cpu.peer_write.part3 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=8,fc_mask=7,umask=2  01     unc_iio_data_req_of_cpu.peer_write.part4 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x10,fc_mask=7,umask=2  01     unc_iio_data_req_of_cpu.peer_write.part5 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x20,fc_mask=7,umask=2  01     unc_iio_data_req_of_cpu.peer_write.part6 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x40,fc_mask=7,umask=2  01     unc_iio_data_req_of_cpu.peer_write.part7 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x80,fc_mask=7,umask=2  01     unc_iio_iommu0.1g_hits uncore io IOTLB Hits to a 1G Page event=0x40,umask=0x10  01     unc_iio_iommu0.2m_hits uncore io IOTLB Hits to a 2M Page event=0x40,umask=8  01     unc_iio_iommu0.4k_hits uncore io IOTLB Hits to a 4K Page event=0x40,umask=4  01     unc_iio_iommu0.ctxt_cache_hits uncore io Context cache hits event=0x40,umask=0x80  01     unc_iio_iommu0.ctxt_cache_lookups uncore io Context cache lookups event=0x40,umask=0x40  01     unc_iio_iommu0.first_lookups uncore io IOTLB lookups first event=0x40,umask=1  01     unc_iio_iommu0.misses uncore io IOTLB Fills (same as IOTLB miss) event=0x40,umask=0x20  01     unc_iio_iommu1.num_mem_accesses uncore io IOMMU memory access (both low and high priority) event=0x41,umask=0xc0  01     unc_iio_iommu1.slpwc_1g_hits uncore io Second Level Page Walk Cache Hit to a 1G page event=0x41,umask=4  01     unc_iio_iommu1.slpwc_256t_hits uncore io Second Level Page Walk Cache Hit to a 256T page event=0x41,umask=0x10  01     unc_iio_iommu1.slpwc_512g_hits uncore io Second Level Page Walk Cache Hit to a 512G page event=0x41,umask=8  01     unc_iio_num_req_of_cpu_by_tgt.abort uncore io - event=0x8e,ch_mask=0xff,fc_mask=7,umask=0x80  01     unc_iio_num_req_of_cpu_by_tgt.confined_p2p uncore io - event=0x8e,ch_mask=0xff,fc_mask=7,umask=0x40  01     unc_iio_num_req_of_cpu_by_tgt.loc_p2p uncore io - event=0x8e,ch_mask=0xff,fc_mask=7,umask=0x20  01     unc_iio_num_req_of_cpu_by_tgt.mcast uncore io - event=0x8e,ch_mask=0xff,fc_mask=7,umask=2  01     unc_iio_num_req_of_cpu_by_tgt.mem uncore io - event=0x8e,ch_mask=0xff,fc_mask=7,umask=8  01     unc_iio_num_req_of_cpu_by_tgt.msgb uncore io - event=0x8e,ch_mask=0xff,fc_mask=7,umask=1  01     unc_iio_num_req_of_cpu_by_tgt.ubox uncore io - event=0x8e,ch_mask=0xff,fc_mask=7,umask=4  01     unc_iio_num_req_of_cpu_by_tgt.ubox_posted uncore io Posted requests sent by the integrated IO (IIO) controller to the Ubox, useful for counting message signaled interrupts (MSI) event=0x8e,ch_mask=0xff,fc_mask=1,umask=4  01    - unc_iio_pwt_occupancy uncore io All 9 bits of Page Walk Tracker Occupancy event=0x42  01     unc_iio_txn_req_by_cpu.mem_read.part0 uncore io Number Transactions requested by the CPU : Core reading from Cards MMIO space event=0xc1,ch_mask=1,fc_mask=7,umask=4  01     unc_iio_txn_req_by_cpu.mem_read.part1 uncore io Number Transactions requested by the CPU : Core reading from Cards MMIO space event=0xc1,ch_mask=2,fc_mask=7,umask=4  01     unc_iio_txn_req_by_cpu.mem_read.part2 uncore io Number Transactions requested by the CPU : Core reading from Cards MMIO space event=0xc1,ch_mask=4,fc_mask=7,umask=4  01     unc_iio_txn_req_by_cpu.mem_read.part3 uncore io Number Transactions requested by the CPU : Core reading from Cards MMIO space event=0xc1,ch_mask=8,fc_mask=7,umask=4  01     unc_iio_txn_req_by_cpu.mem_read.part4 uncore io Number Transactions requested by the CPU : Core reading from Cards MMIO space event=0xc1,ch_mask=0x10,fc_mask=7,umask=4  01     unc_iio_txn_req_by_cpu.mem_read.part5 uncore io Number Transactions requested by the CPU : Core reading from Cards MMIO space event=0xc1,ch_mask=0x20,fc_mask=7,umask=4  01     unc_iio_txn_req_by_cpu.mem_read.part6 uncore io Number Transactions requested by the CPU : Core reading from Cards MMIO space event=0xc1,ch_mask=0x40,fc_mask=7,umask=4  01     unc_iio_txn_req_by_cpu.mem_read.part7 uncore io Number Transactions requested by the CPU : Core reading from Cards MMIO space event=0xc1,ch_mask=0x80,fc_mask=7,umask=4  01     unc_iio_txn_req_by_cpu.mem_write.part0 uncore io Number Transactions requested by the CPU : Core writing to Cards MMIO space event=0xc1,ch_mask=1,fc_mask=7,umask=1  01     unc_iio_txn_req_by_cpu.mem_write.part1 uncore io Number Transactions requested by the CPU : Core writing to Cards MMIO space event=0xc1,ch_mask=2,fc_mask=7,umask=1  01     unc_iio_txn_req_by_cpu.mem_write.part2 uncore io Number Transactions requested by the CPU : Core writing to Cards MMIO space event=0xc1,ch_mask=4,fc_mask=7,umask=1  01     unc_iio_txn_req_by_cpu.mem_write.part3 uncore io Number Transactions requested by the CPU : Core writing to Cards MMIO space event=0xc1,ch_mask=8,fc_mask=7,umask=1  01     unc_iio_txn_req_by_cpu.mem_write.part4 uncore io Number Transactions requested by the CPU : Core writing to Cards MMIO space event=0xc1,ch_mask=0x10,fc_mask=7,umask=1  01     unc_iio_txn_req_by_cpu.mem_write.part5 uncore io Number Transactions requested by the CPU : Core writing to Cards MMIO space event=0xc1,ch_mask=0x20,fc_mask=7,umask=1  01     unc_iio_txn_req_by_cpu.mem_write.part6 uncore io Number Transactions requested by the CPU : Core writing to Cards MMIO space event=0xc1,ch_mask=0x40,fc_mask=7,umask=1  01     unc_iio_txn_req_by_cpu.mem_write.part7 uncore io Number Transactions requested by the CPU : Core writing to Cards MMIO space event=0xc1,ch_mask=0x80,fc_mask=7,umask=1  01     unc_iio_txn_req_of_cpu.mem_read.part0 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=1,fc_mask=7,umask=4  01     unc_iio_txn_req_of_cpu.mem_read.part1 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=2,fc_mask=7,umask=4  01     unc_iio_txn_req_of_cpu.mem_read.part2 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=4,fc_mask=7,umask=4  01     unc_iio_txn_req_of_cpu.mem_read.part3 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=8,fc_mask=7,umask=4  01     unc_iio_txn_req_of_cpu.mem_read.part4 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x10,fc_mask=7,umask=4  01     unc_iio_txn_req_of_cpu.mem_read.part5 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x20,fc_mask=7,umask=4  01     unc_iio_txn_req_of_cpu.mem_read.part6 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x40,fc_mask=7,umask=4  01     unc_iio_txn_req_of_cpu.mem_read.part7 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x80,fc_mask=7,umask=4  01     unc_iio_txn_req_of_cpu.mem_write.part0 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=1,fc_mask=7,umask=1  01     unc_iio_txn_req_of_cpu.mem_write.part1 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=2,fc_mask=7,umask=1  01     unc_iio_txn_req_of_cpu.mem_write.part2 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=4,fc_mask=7,umask=1  01     unc_iio_txn_req_of_cpu.mem_write.part3 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=8,fc_mask=7,umask=1  01     unc_iio_txn_req_of_cpu.mem_write.part4 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x10,fc_mask=7,umask=1  01     unc_iio_txn_req_of_cpu.mem_write.part5 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x20,fc_mask=7,umask=1  01     unc_iio_txn_req_of_cpu.mem_write.part6 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x40,fc_mask=7,umask=1  01     unc_iio_txn_req_of_cpu.mem_write.part7 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x80,fc_mask=7,umask=1  01     unc_iio_txn_req_of_cpu.peer_write.part0 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=1,fc_mask=7,umask=2  01     unc_iio_txn_req_of_cpu.peer_write.part1 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=2,fc_mask=7,umask=2  01     unc_iio_txn_req_of_cpu.peer_write.part2 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=4,fc_mask=7,umask=2  01     unc_iio_txn_req_of_cpu.peer_write.part3 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=8,fc_mask=7,umask=2  01     unc_iio_txn_req_of_cpu.peer_write.part4 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x10,fc_mask=7,umask=2  01     unc_iio_txn_req_of_cpu.peer_write.part5 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x20,fc_mask=7,umask=2  01     unc_iio_txn_req_of_cpu.peer_write.part6 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x40,fc_mask=7,umask=2  01     unc_iio_txn_req_of_cpu.peer_write.part7 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x80,fc_mask=7,umask=2  01     unc_m_act_count.all uncore memory DRAM Activate Count : Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates event=2,umask=0xf7  01     unc_m_act_count.rd uncore memory DRAM Activate Count : Read transaction on Page Empty or Page Miss : Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates event=2,umask=0xf1  01     unc_m_act_count.ufill uncore memory DRAM Activate Count : Underfill Read transaction on Page Empty or Page Miss : Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates event=2,umask=0xf4  01     unc_m_act_count.wr uncore memory DRAM Activate Count : Write transaction on Page Empty or Page Miss : Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates event=2,umask=0xf2  01     unc_m_cas_count_sch0.all uncore memory CAS count for SubChannel 0, all CAS operations event=5,umask=0xff  01     unc_m_cas_count_sch0.rd uncore memory CAS count for SubChannel 0, all reads event=5,umask=0xcf  01     unc_m_cas_count_sch0.rd_reg uncore memory CAS count for SubChannel 0 regular reads event=5,umask=0xc1  01     unc_m_cas_count_sch0.rd_underfill uncore memory CAS count for SubChannel 0 underfill reads event=5,umask=0xc4  01     unc_m_cas_count_sch0.wr uncore memory CAS count for SubChannel 0, all writes event=5,umask=0xf0  01     unc_m_cas_count_sch0.wr_nonpre uncore memory CAS count for SubChannel 0 regular writes event=5,umask=0xd0  01     unc_m_cas_count_sch0.wr_pre uncore memory CAS count for SubChannel 0 auto-precharge writes event=5,umask=0xe0  01     unc_m_cas_count_sch1.all uncore memory CAS count for SubChannel 1, all CAS operations event=6,umask=0xff  01     unc_m_cas_count_sch1.rd uncore memory CAS count for SubChannel 1, all reads event=6,umask=0xcf  01     unc_m_cas_count_sch1.rd_reg uncore memory CAS count for SubChannel 1 regular reads event=6,umask=0xc1  01     unc_m_cas_count_sch1.rd_underfill uncore memory CAS count for SubChannel 1 underfill reads event=6,umask=0xc4  01     unc_m_cas_count_sch1.wr uncore memory CAS count for SubChannel 1, all writes event=6,umask=0xf0  01     unc_m_cas_count_sch1.wr_nonpre uncore memory CAS count for SubChannel 1 regular writes event=6,umask=0xd0  01     unc_m_cas_count_sch1.wr_pre uncore memory CAS count for SubChannel 1 auto-precharge writes event=6,umask=0xe0  01     unc_m_clockticks uncore memory Number of DRAM DCLK clock cycles while the event is enabled.  DCLK is 1/4 of DRAM data rate event=1,umask=1  01    DRAM Clockticks unc_m_hclockticks uncore memory Number of DRAM HCLK clock cycles while the event is enabled event=1  01    DRAM Clockticks unc_m_mr4_2xref_cycles.sch0_dimm0 uncore memory # of cycles MR4 temp readings forced 2x refresh event=0xa7,umask=1  01    - unc_m_mr4_2xref_cycles.sch0_dimm1 uncore memory # of cycles MR4 temp readings forced 2x refresh event=0xa7,umask=2  01    - unc_m_mr4_2xref_cycles.sch1_dimm0 uncore memory # of cycles MR4 temp readings forced 2x refresh event=0xa7,umask=4  01    - unc_m_mr4_2xref_cycles.sch1_dimm1 uncore memory # of cycles MR4 temp readings forced 2x refresh event=0xa7,umask=8  01    - unc_m_pdc_mr4active_cycles.sch0_dimm0 uncore memory # of cycles MR4 MRRs was triggered/running event=0xa6,umask=1  01    - unc_m_pdc_mr4active_cycles.sch0_dimm1 uncore memory # of cycles MR4 MRRs was triggered/running event=0xa6,umask=2  01    - unc_m_pdc_mr4active_cycles.sch1_dimm0 uncore memory # of cycles MR4 MRRs was triggered/running event=0xa6,umask=4  01    - unc_m_pdc_mr4active_cycles.sch1_dimm1 uncore memory # of cycles MR4 MRRs was triggered/running event=0xa6,umask=8  01    - unc_m_powerdown_cycles.sch0_rank0 uncore memory # of cycles a given rank is in Power Down Mode event=0x47,umask=1  01    - unc_m_powerdown_cycles.sch0_rank1 uncore memory # of cycles a given rank is in Power Down Mode event=0x47,umask=2  01    - unc_m_powerdown_cycles.sch0_rank2 uncore memory # of cycles a given rank is in Power Down Mode event=0x47,umask=4  01    - unc_m_powerdown_cycles.sch0_rank3 uncore memory # of cycles a given rank is in Power Down Mode event=0x47,umask=8  01    - unc_m_powerdown_cycles.sch1_rank0 uncore memory # of cycles a given rank is in Power Down Mode event=0x47,umask=0x10  01    - unc_m_powerdown_cycles.sch1_rank1 uncore memory # of cycles a given rank is in Power Down Mode event=0x47,umask=0x20  01    - unc_m_powerdown_cycles.sch1_rank2 uncore memory # of cycles a given rank is in Power Down Mode event=0x47,umask=0x40  01    - unc_m_powerdown_cycles.sch1_rank3 uncore memory # of cycles a given rank is in Power Down Mode event=0x47,umask=0x80  01    - unc_m_power_channel_ppd_cycles uncore memory # of cycles a given rank is in Power Down Mode and all pages are closed event=0x88  01    - unc_m_power_critical_throttle_cycles.slot0 uncore memory # of cycles Throttling at Critical level on specified DIMM and throttle level is zero event=0x89,umask=1  01    - unc_m_power_critical_throttle_cycles.slot1 uncore memory # of cycles Throttling at Critical level on specified DIMM and throttle level is zero event=0x89,umask=2  01    - unc_m_power_throttle_cycles.bw_slot0 uncore memory UNC_M_POWER_THROTTLE_CYCLES.BW_SLOT0 event=0x46,umask=1  01     unc_m_power_throttle_cycles.bw_slot1 uncore memory UNC_M_POWER_THROTTLE_CYCLES.BW_SLOT1 event=0x46,umask=2  01     unc_m_power_throttle_cycles.mr4blken uncore memory MR4 temp reading is throttling event=0x46,umask=8  01    - unc_m_power_throttle_cycles.raplblk uncore memory RAPL is throttling event=0x46,umask=4  01    - unc_m_pre_count.all uncore memory DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel event=3,umask=0xff  01     unc_m_pre_count.pgt uncore memory DRAM Precharge commands. : Precharge due to (?) : Counts the number of DRAM Precharge commands sent on this channel event=3,umask=0xf8  01     unc_m_pre_count.rd uncore memory DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel event=3,umask=0xf1  01     unc_m_pre_count.ufill uncore memory DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel event=3,umask=0xf4  01     unc_m_pre_count.wr uncore memory DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel event=3,umask=0xf2  01     unc_m_rdb_inserts.sch0 uncore memory Read buffer inserts on subchannel 0 event=0x17,umask=0x40  01     unc_m_rdb_inserts.sch1 uncore memory Read buffer inserts on subchannel 1 event=0x17,umask=0x80  01     unc_m_rdb_occupancy_sch0 uncore memory Read buffer occupancy on subchannel 0 event=0x1a  01     unc_m_rdb_occupancy_sch1 uncore memory Read buffer occupancy on subchannel 1 event=0x1b  01     unc_m_rpq_inserts.pch0 uncore memory Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue.  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This includes both ISOCH and non-ISOCH requests event=0x10,umask=0x50  01     unc_m_rpq_inserts.pch1 uncore memory Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue.  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This includes both ISOCH and non-ISOCH requests event=0x10,umask=0xa0  01     unc_m_rpq_inserts.sch0_pch0 uncore memory Read Pending Queue inserts for subchannel 0, pseudochannel 0 event=0x10,umask=0x10  01     unc_m_rpq_inserts.sch0_pch1 uncore memory Read Pending Queue inserts for subchannel 0, pseudochannel 1 event=0x10,umask=0x20  01     unc_m_rpq_inserts.sch1_pch0 uncore memory Read Pending Queue inserts for subchannel 1, pseudochannel 0 event=0x10,umask=0x40  01     unc_m_rpq_inserts.sch1_pch1 uncore memory Read Pending Queue inserts for subchannel 1, pseudochannel 1 event=0x10,umask=0x80  01     unc_m_rpq_occupancy_sch0_pch0 uncore memory Read pending queue occupancy for subchannel 0, pseudochannel 0 event=0x80  01     unc_m_rpq_occupancy_sch0_pch1 uncore memory Read pending queue occupancy for subchannel 0, pseudochannel 1 event=0x81  01     unc_m_rpq_occupancy_sch1_pch0 uncore memory Read pending queue occupancy for subchannel 1, pseudochannel 0 event=0x82  01     unc_m_rpq_occupancy_sch1_pch1 uncore memory Read pending queue occupancy for subchannel 1, pseudochannel 1 event=0x83  01     unc_m_throttle_crit_cycles.slot0 uncore memory # of cycles Throttling at Critical level on specified DIMM event=0x8e,umask=1  01    - unc_m_throttle_crit_cycles.slot1 uncore memory # of cycles Throttling at Critical level on specified DIMM event=0x8e,umask=2  01    - unc_m_throttle_high_cycles.slot0 uncore memory # of cycles Throttling at High level on specified DIMM event=0x8d,umask=1  01    - unc_m_throttle_high_cycles.slot1 uncore memory # of cycles Throttling at High level on specified DIMM event=0x8d,umask=2  01    - unc_m_throttle_low_cycles.slot0 uncore memory # of cycles Throttling at Normal level on specified DIMM event=0x8b,umask=1  01    - unc_m_throttle_low_cycles.slot1 uncore memory # of cycles Throttling at Normal level on specified DIMM event=0x8b,umask=2  01    - unc_m_throttle_mid_cycles.slot0 uncore memory # of cycles Throttling at Mid level on specified DIMM event=0x8c,umask=1  01    - unc_m_throttle_mid_cycles.slot1 uncore memory # of cycles Throttling at Mid level on specified DIMM event=0x8c,umask=2  01    - unc_m_wpq_inserts.pch0 uncore memory Write Pending Queue Allocations event=0x22,umask=0x50  01     unc_m_wpq_inserts.pch1 uncore memory Write Pending Queue Allocations event=0x22,umask=0xa0  01     unc_m_wpq_inserts.sch0_pch0 uncore memory Write Pending Queue inserts for subchannel 0, pseudochannel 0 event=0x22,umask=0x10  01     unc_m_wpq_inserts.sch0_pch1 uncore memory Write Pending Queue inserts for subchannel 0, pseudochannel 1 event=0x22,umask=0x20  01     unc_m_wpq_inserts.sch1_pch0 uncore memory Write Pending Queue inserts for subchannel 1, pseudochannel 0 event=0x22,umask=0x40  01     unc_m_wpq_inserts.sch1_pch1 uncore memory Write Pending Queue inserts for subchannel 1, pseudochannel 1 event=0x22,umask=0x80  01     unc_m_wpq_occupancy_sch0_pch0 uncore memory Write pending queue occupancy for subchannel 0, pseudochannel 0 event=0x84  01     unc_m_wpq_occupancy_sch0_pch1 uncore memory Write pending queue occupancy for subchannel 0, pseudochannel 1 event=0x85  01     unc_m_wpq_occupancy_sch1_pch0 uncore memory Write pending queue occupancy for subchannel 1, pseudochannel 0 event=0x86  01     unc_m_wpq_occupancy_sch1_pch1 uncore memory Write pending queue occupancy for subchannel 1, pseudochannel 1 event=0x87  01     unc_p_clockticks uncore power PCU Clockticks event=1  01    PCU Clockticks:  The PCU runs off a fixed 1 GHz clock.  This event counts the number of pclk cycles measured while the counter was enabled.  The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time l2_request.hit cache All requests that hit L2 cache. [This event is alias to L2_RQSTS.HIT] event=0x24,period=200003,umask=0xdf  00    Counts all requests that hit L2 cache. [This event is alias to L2_RQSTS.HIT] l2_rqsts.hit cache All requests that hit L2 cache. [This event is alias to L2_REQUEST.HIT] event=0x24,period=200003,umask=0xdf  00    Counts all requests that hit L2 cache. [This event is alias to L2_REQUEST.HIT] mem_inst_retired.lock_loads cache Retired load instructions with locked access  Supports address when precise event=0xd0,period=100007,umask=0x21  00 63.76 15 5156 Counts retired load instructions with locked access. Available PDIST counters: 0  Supports address when precise mem_inst_retired.split_loads cache Retired load instructions that split across a cacheline boundary  Supports address when precise event=0xd0,period=100003,umask=0x41  00 3.97  4704 Counts retired load instructions that split across a cacheline boundary. Available PDIST counters: 0  Supports address when precise mem_inst_retired.split_stores cache Retired store instructions that split across a cacheline boundary  Supports address when precise event=0xd0,period=100003,umask=0x42  00 19.0  65535 Counts retired store instructions that split across a cacheline boundary. Available PDIST counters: 0  Supports address when precise mem_inst_retired.stlb_hit_loads cache Retired load instructions that hit the STLB  Supports address when precise event=0xd0,period=100003,umask=9  00 1.57  3424 Number of retired load instructions with a clean hit in the 2nd-level TLB (STLB). Available PDIST counters: 0  Supports address when precise mem_inst_retired.stlb_hit_stores cache Retired store instructions that hit the STLB  Supports address when precise event=0xd0,period=100003,umask=0xa  00 5.24  65535 Number of retired store instructions that hit in the 2nd-level TLB (STLB). Available PDIST counters: 0  Supports address when precise mem_load_l3_hit_retired.xsnp_fwd cache Retired load instructions whose data sources were HitM responses from shared L3  Supports address when precise event=0xd2,period=20011,umask=4  00 353.04  4472 Counts retired load instructions whose data sources were HitM responses from shared L3. Available PDIST counters: 0  Supports address when precise mem_load_l3_hit_retired.xsnp_miss cache Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache  Supports address when precise event=0xd2,period=20011,umask=1  00 125.27  830 Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache. Available PDIST counters: 0  Supports address when precise mem_load_l3_hit_retired.xsnp_no_fwd cache Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache  Supports address when precise event=0xd2,period=20011,umask=2  00 289.9  3939 Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache. Available PDIST counters: 0  Supports address when precise mem_load_l3_miss_retired.local_dram cache Retired load instructions which data sources missed L3 but serviced from dram homed in the local socket  Supports address when precise event=0xd3,period=100007,umask=1  00 115.83  4146 Retired load instructions which data sources missed L3 but serviced from DRAM homed in the local socket. Available PDIST counters: 0  Supports address when precise mem_load_l3_miss_retired.remote_cxl_mem cache Retired load instructions with remote cxl mem as the data source where the data request missed all caches event=0xd3,period=100007,umask=0x10  00    Counts retired load instructions with remote cxl mem as the data source and the data request missed L3. Available PDIST counters: 0 mem_load_l3_miss_retired.remote_dram cache MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM  Supports address when precise event=0xd3,period=1000003,umask=2  00 430.22  3572 MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM Available PDIST counters: 0  Supports address when precise mem_load_l3_miss_retired.remote_fwd cache Retired load instructions whose data sources was forwarded from a remote cache  Supports address when precise event=0xd3,period=100007,umask=8  00 125.36  8552 Retired load instructions whose data sources was forwarded from a remote cache. Available PDIST counters: 0  Supports address when precise mem_load_l3_miss_retired.remote_hitm cache MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM  Supports address when precise event=0xd3,period=1000003,umask=4  00 135.29  2580 MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM Available PDIST counters: 0  Supports address when precise mem_load_retired.l2_hit cache Retired load instructions with L2 cache hits as data sources  Supports address when precise event=0xd1,period=200003,umask=2  00 5.71  7140 Counts retired load instructions with L2 cache hits as data sources. Available PDIST counters: 0  Supports address when precise mem_load_retired.l3_hit cache Retired load instructions with L3 cache hits as data sources  Supports address when precise event=0xd1,period=100021,umask=4  00 57.64  5630 Counts retired load instructions with at least one uop that hit in the L3 cache. Available PDIST counters: 0  Supports address when precise mem_load_retired.local_cxl_mem cache Retired load instructions with local cxl mem as the data source where the data request missed all caches  Supports address when precise event=0xd1,period=1000003,umask=0x80  00    Counts retired load instructions with local cxl mem as the data source and the data request missed L3. Available PDIST counters: 0  Supports address when precise ocr.demand_data_rd.cxl_mem cache Counts demand data reads that were supplied by CXL MEM (Type 2 or Type 3) event=0x2a,period=100003,umask=1,offcore_rsp=0x703C00001  00    Counts demand data reads that were supplied by CXL MEM (Type 2 or Type 3). Available PDIST counters: 0 ocr.demand_data_rd.local_cxl_mem cache Counts demand data reads that were supplied by CXL MEM (Type 2 and Type 3) attached to local socket event=0x2a,period=100003,umask=1,offcore_rsp=0x700C00001  00    Counts demand data reads that were supplied by CXL MEM (Type 2 and Type 3) attached to local socket. Available PDIST counters: 0 ocr.demand_data_rd.remote_cxl_mem cache Counts demand data reads that were supplied by CXL MEM (Type 2 or Type 3) attached to another socket event=0x2a,period=100003,umask=1,offcore_rsp=0x703000001  00    Counts demand data reads that were supplied by CXL MEM (Type 2 or Type 3) attached to another socket. Available PDIST counters: 0 ocr.demand_rfo.cxl_mem cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by CXL MEM (Type 2 or Type 3) event=0x2a,period=100003,umask=1,offcore_rsp=0x703C00002  00    Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by CXL MEM (Type 2 or Type 3). Available PDIST counters: 0 ocr.demand_rfo.local_cxl_mem cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by CXL MEM (Type 2 and Type 3) attached to local socket event=0x2a,period=100003,umask=1,offcore_rsp=0x700C00002  00    Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by CXL MEM (Type 2 and Type 3) attached to local socket. Available PDIST counters: 0 ocr.demand_rfo.remote_cxl_mem cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by CXL MEM (Type 2 or Type 3) attached to another socket event=0x2a,period=100003,umask=1,offcore_rsp=0x703000002  00    Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by CXL MEM (Type 2 or Type 3) attached to another socket. Available PDIST counters: 0 ocr.reads_to_core.cxl_mem cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by CXL MEM (Type 2 or Type 3) event=0x2a,period=100003,umask=1,offcore_rsp=0x703C04477  00    Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by CXL MEM (Type 2 or Type 3). Available PDIST counters: 0 ocr.reads_to_core.local_cxl_mem cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by CXL MEM (Type 2 and Type 3) attached to local socket event=0x2a,period=100003,umask=1,offcore_rsp=0x700C04477  00    Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by CXL MEM (Type 2 and Type 3) attached to local socket. Available PDIST counters: 0 ocr.reads_to_core.remote_cxl_mem cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by CXL MEM (Type 2 or Type 3) attached to another socket event=0x2a,period=100003,umask=1,offcore_rsp=0x703004477  00    Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by CXL MEM (Type 2 or Type 3) attached to another socket. Available PDIST counters: 0 offcore_requests.mem_uc cache Offcore Uncacheable memory data read transactions event=0x21,period=100003,umask=0x20  00    This event counts noncacheable memory data read transactions arith.fpdiv_active floating point This event counts the cycles the floating point divider is busy event=0xb0,cmask=1,period=1000003,umask=1  00     frontend_retired.any_ant frontend Retired ANT branches event=0xc6,period=100007,umask=3,frontend=0x9  00    Always Not Taken (ANT) conditional retired branches (no BTB entry and not mispredicted) Available PDIST counters: 0 frontend_retired.any_dsb_miss frontend Retired Instructions who experienced DSB miss event=0xc6,period=100007,umask=3,frontend=0x1  00 2.46  65535 Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Available PDIST counters: 0 frontend_retired.dsb_miss frontend Retired Instructions who experienced a critical DSB miss event=0xc6,period=100007,umask=3,frontend=0x11  00    Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss. Available PDIST counters: 0 frontend_retired.itlb_miss frontend Retired Instructions who experienced iTLB true miss event=0xc6,period=100007,umask=3,frontend=0x14  00 41.96  980 Counts retired Instructions that experienced iTLB (Instruction TLB) true miss. Available PDIST counters: 0 frontend_retired.l1i_miss frontend Retired Instructions who experienced Instruction L1 Cache true miss event=0xc6,period=100007,umask=3,frontend=0x12  00 9.83  1785 Counts retired Instructions who experienced Instruction L1 Cache true miss. Available PDIST counters: 0 frontend_retired.l2_miss frontend Retired Instructions who experienced Instruction L2 Cache true miss event=0xc6,period=100007,umask=3,frontend=0x13  00 137.41  2854 Counts retired Instructions who experienced Instruction L2 Cache true miss. Available PDIST counters: 0 frontend_retired.latency_ge_1 frontend Retired instructions after front-end starvation of at least 1 cycle event=0xc6,period=100007,umask=3,frontend=0x600106  00    Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall. Available PDIST counters: 0 frontend_retired.latency_ge_128 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=3,frontend=0x608006  00    Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall. Available PDIST counters: 0 frontend_retired.latency_ge_16 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=3,frontend=0x601006  00    Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops. Available PDIST counters: 0 frontend_retired.latency_ge_2 frontend Retired instructions after front-end starvation of at least 2 cycles event=0xc6,period=100007,umask=3,frontend=0x600206  00    Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall. Available PDIST counters: 0 frontend_retired.latency_ge_256 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=3,frontend=0x610006  00    Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall. Available PDIST counters: 0 frontend_retired.latency_ge_2_bubbles_ge_1 frontend Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=3,frontend=0x100206  00    Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall. Available PDIST counters: 0 frontend_retired.latency_ge_32 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=3,frontend=0x602006  00    Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops. Available PDIST counters: 0 frontend_retired.latency_ge_4 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=3,frontend=0x600406  00    Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall. Available PDIST counters: 0 frontend_retired.latency_ge_512 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=3,frontend=0x620006  00    Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall. Available PDIST counters: 0 frontend_retired.latency_ge_64 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=3,frontend=0x604006  00    Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall. Available PDIST counters: 0 frontend_retired.latency_ge_8 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=3,frontend=0x600806  00    Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops. Available PDIST counters: 0 frontend_retired.late_swpf frontend I-Cache miss too close to Code Prefetch Instruction event=0xc6,period=100007,umask=3,frontend=0xA  00    Number of Instruction Cache demand miss in shadow of an on-going i-fetch cache-line triggered by PREFETCHIT0/1 instructions Available PDIST counters: 0 frontend_retired.misp_ant frontend Mispredicted Retired ANT branches event=0xc6,period=100007,umask=2,frontend=0x9  00    ANT retired branches that got just mispredicted Available PDIST counters: 0 frontend_retired.ms_flows frontend FRONTEND_RETIRED.MS_FLOWS event=0xc6,period=100007,umask=3,frontend=0x8  00 77.14  65535 FRONTEND_RETIRED.MS_FLOWS Available PDIST counters: 0 frontend_retired.stlb_miss frontend Retired Instructions who experienced STLB (2nd level TLB) true miss event=0xc6,period=100007,umask=3,frontend=0x15  00 206.85  754 Counts retired Instructions that experienced STLB (2nd level TLB) true miss. Available PDIST counters: 0 frontend_retired.unknown_branch frontend FRONTEND_RETIRED.UNKNOWN_BRANCH event=0xc6,period=100007,umask=3,frontend=0x17  00 3.85  532 FRONTEND_RETIRED.UNKNOWN_BRANCH Available PDIST counters: 0 idq_bubbles.core frontend This event counts a subset of the Topdown Slots event that when no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations event=0x9c,period=1000003,umask=1  00    This event counts a subset of the Topdown Slots event that when no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations. The count may be distributed among unhalted logical processors (hyper-threads) who share the same physical core, in processors that support Intel Hyper-Threading Technology. Software can use this event as the numerator for the Frontend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method idq_uops_not_delivered.core frontend Uops not delivered by IDQ when backend of the machine is not stalled event=0x9c,period=1000003,umask=1  00    Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle cycle_activity.cycles_l3_miss memory Cycles while L3 cache miss demand load is outstanding event=0xa3,cmask=2,period=1000003,umask=2  00     mem_trans_retired.load_latency_gt_1024 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles  Supports address when precise event=0xcd,period=53,umask=1,ldlat=0x400  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.  Reported latency may be longer than just the memory latency. Available PDIST counters: 0  Supports address when precise mem_trans_retired.load_latency_gt_128 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles  Supports address when precise event=0xcd,period=1009,umask=1,ldlat=0x80  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency. Available PDIST counters: 0  Supports address when precise mem_trans_retired.load_latency_gt_16 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles  Supports address when precise event=0xcd,period=20011,umask=1,ldlat=0x10  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency. Available PDIST counters: 0  Supports address when precise mem_trans_retired.load_latency_gt_2048 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles  Supports address when precise event=0xcd,period=23,umask=1,ldlat=0x800  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles.  Reported latency may be longer than just the memory latency. Available PDIST counters: 0  Supports address when precise mem_trans_retired.load_latency_gt_256 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles  Supports address when precise event=0xcd,period=503,umask=1,ldlat=0x100  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency. Available PDIST counters: 0  Supports address when precise mem_trans_retired.load_latency_gt_32 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles  Supports address when precise event=0xcd,period=100007,umask=1,ldlat=0x20  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency. Available PDIST counters: 0  Supports address when precise mem_trans_retired.load_latency_gt_4 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles  Supports address when precise event=0xcd,period=100003,umask=1,ldlat=0x4  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency. Available PDIST counters: 0  Supports address when precise mem_trans_retired.load_latency_gt_512 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles  Supports address when precise event=0xcd,period=101,umask=1,ldlat=0x200  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency. Available PDIST counters: 0  Supports address when precise mem_trans_retired.load_latency_gt_64 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles  Supports address when precise event=0xcd,period=2003,umask=1,ldlat=0x40  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency. Available PDIST counters: 0  Supports address when precise mem_trans_retired.load_latency_gt_8 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles  Supports address when precise event=0xcd,period=50021,umask=1,ldlat=0x8  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency. Available PDIST counters: 0  Supports address when precise br_misp_retired.all_branches_cost pipeline All mispredicted branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch event=0xc5,period=400009,umask=0x44  00    All mispredicted branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0 br_misp_retired.cond_cost pipeline Mispredicted conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch event=0xc5,period=400009,umask=0x51  00    Mispredicted conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0 br_misp_retired.cond_ntaken_cost pipeline Mispredicted non-taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch event=0xc5,period=400009,umask=0x50  00 6.11  888 Mispredicted non-taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0 br_misp_retired.cond_taken_cost pipeline Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch event=0xc5,period=400009,umask=0x41  00 5.09  2750 Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0 br_misp_retired.indirect_call_cost pipeline Mispredicted indirect CALL retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch event=0xc5,period=400009,umask=0x42  00 15.56  703 Mispredicted indirect CALL retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0 br_misp_retired.indirect_cost pipeline Mispredicted near indirect branch instructions retired (excluding returns). This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch event=0xc5,period=100003,umask=0xc0  00 11.07  1562 Mispredicted near indirect branch instructions retired (excluding returns). This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0 br_misp_retired.near_taken_cost pipeline Mispredicted taken near branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch event=0xc5,period=400009,umask=0x60  00    Mispredicted taken near branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0 br_misp_retired.ret_cost pipeline Mispredicted ret instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch event=0xc5,period=100007,umask=0x48  00 32.37 9 1082 Mispredicted ret instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0 inst_retired.nop pipeline Retired NOP instructions event=0xc0,period=2000003,umask=2  00    Counts all retired NOP or ENDBR32/64 or PREFETCHIT0/1 instructions topdown.backend_bound_slots pipeline This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions event=0xa4,period=10000003,umask=2  00    This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core, in processors that support Intel Hyper-Threading Technology. Software can use this event as the numerator for the Backend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method unc_chacms_clockticks uncore cache Clockticks for CMS units attached to CHA event=1  01    UNC_CHACMS_CLOCKTICKS unc_chacms_distress_asserted uncore cache UNC_CHACMS_DISTRESS_ASSERTED event=0x35  01     unc_cha_dir_lookup.no_snp uncore cache Counts transactions that looked into the multi-socket cacheline Directory state, and therefore did not send a snoop because the Directory indicated it was not needed event=0x53,umask=2  01     unc_cha_dir_lookup.snp uncore cache Counts  transactions that looked into the multi-socket cacheline Directory state, and sent one or more snoops, because the Directory indicated it was needed event=0x53,umask=1  01     unc_cha_dir_update.ha uncore cache Counts only multi-socket cacheline Directory state updates memory writes issued from the HA pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines event=0x54,umask=1  01     unc_cha_dir_update.tor uncore cache Counts only multi-socket cacheline Directory state updates due to memory writes issued from the TOR pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines event=0x54,umask=2  01     unc_cha_llc_lookup.all_remote uncore cache Cache Lookups: All Requests to Remotely Homed Memory event=0x34,umask=0x17e0ff  01    Cache Lookups : All transactions from Remote Agents unc_cha_llc_lookup.remotely_homed_address uncore cache Cache Lookups: All Requests to Remotely Homed Memory event=0x34,umask=0x15dfff  01    Cache Lookups : Transactions homed remotely : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Transaction whose address resides in a remote MC unc_cha_llc_lookup.remote_code uncore cache Cache Lookups: Code Read/Prefetch Requests from a Remote Socket event=0x34,umask=0x1a10ff  01    Cache Lookups : CRd Requests unc_cha_llc_lookup.remote_data_rd uncore cache Cache Lookups: Data Read/Prefetch Requests from a Remote Socket event=0x34,umask=0x1a01ff  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.remote_rfo uncore cache Cache Lookups: RFO Requests/Prefetches from a Remote Socket event=0x34,umask=0x1a08ff  01    Cache Lookups : RFO Requests unc_cha_llc_lookup.remote_snp uncore cache Cache Lookups: Snoop Requests from a Remote Socket event=0x34,umask=0x1c19ff  01    Counts the number of times the LLC was accessed unc_cha_llc_lookup.write_remote uncore cache Cache Lookups: Writes to Remotely Homed Memory (includes writebacks from L1/L2) event=0x34,umask=0x17c2ff  01    Cache Lookups : Remote Writes unc_cha_llc_victims.remote_all uncore cache Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in event=0x37,umask=0x800f  01    Lines Victimized : Remote - All Lines unc_cha_llc_victims.remote_e uncore cache Lines Victimized : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in event=0x37,umask=0x8002  01    Lines Victimized : Remote - Lines in E State unc_cha_llc_victims.remote_m uncore cache Lines Victimized : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in event=0x37,umask=0x8001  01    Lines Victimized : Remote - Lines in M State unc_cha_llc_victims.remote_s uncore cache Lines Victimized : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in event=0x37,umask=0x8004  01    Lines Victimized : Remote - Lines in S State unc_cha_osb.remote_read uncore cache OSB Snoop Broadcast : Remote Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB event=0x55,umask=4  01     unc_cha_remote_sf.alloc_exclusive uncore cache UNC_CHA_REMOTE_SF.ALLOC_EXCLUSIVE event=0x69,umask=0x10  01     unc_cha_remote_sf.alloc_shared uncore cache UNC_CHA_REMOTE_SF.ALLOC_SHARED event=0x69,umask=8  01     unc_cha_remote_sf.dealloc_evctcln uncore cache UNC_CHA_REMOTE_SF.DEALLOC_EVCTCLN event=0x69,umask=0x40  01     unc_cha_remote_sf.dirbacked_only uncore cache UNC_CHA_REMOTE_SF.DIRBACKED_ONLY event=0x69  01     unc_cha_remote_sf.hit_exclusive uncore cache UNC_CHA_REMOTE_SF.HIT_EXCLUSIVE event=0x69,umask=2  01     unc_cha_remote_sf.hit_shared uncore cache UNC_CHA_REMOTE_SF.HIT_SHARED event=0x69,umask=1  01     unc_cha_remote_sf.inclusive_only uncore cache UNC_CHA_REMOTE_SF.INCLUSIVE_ONLY event=0x69  01     unc_cha_remote_sf.miss uncore cache UNC_CHA_REMOTE_SF.MISS event=0x69,umask=4  01     unc_cha_remote_sf.update_exclusive uncore cache UNC_CHA_REMOTE_SF.UPDATE_EXCLUSIVE event=0x69  01     unc_cha_remote_sf.update_shared uncore cache UNC_CHA_REMOTE_SF.UPDATE_SHARED event=0x69,umask=0x80  01     unc_cha_remote_sf.victim_exclusive uncore cache UNC_CHA_REMOTE_SF.VICTIM_EXCLUSIVE event=0x69  01     unc_cha_remote_sf.victim_shared uncore cache UNC_CHA_REMOTE_SF.VICTIM_SHARED event=0x69  01     unc_cha_requests.invitoe_remote uncore cache Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA event=0x50,umask=0x20  01     unc_cha_requests.reads_remote uncore cache Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a  write) event=0x50,umask=2  01     unc_cha_requests.writes_remote uncore cache Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc) event=0x50,umask=8  01     unc_cha_sf_eviction.e_state uncore cache Counts snoop filter capacity evictions for entries tracking exclusive lines in the core's cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a core's cache replaces a tracked cacheline with a new cacheline event=0x3d,umask=2  01    Snoop Filter Capacity Evictions : E state unc_cha_sf_eviction.m_state uncore cache Counts snoop filter capacity evictions for entries tracking modified lines in the core's cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a core's cache replaces a tracked cacheline with a new cacheline event=0x3d,umask=1  01    Snoop Filter Capacity Evictions : M state unc_cha_sf_eviction.s_state uncore cache Counts snoop filter capacity evictions for entries tracking shared lines in the core's cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a core's cache replaces a tracked cacheline with a new cacheline event=0x3d,umask=4  01    Snoop Filter Capacity Evictions : S state unc_cha_tor_inserts.cxl_hit_clflush uncore cache CLFlush transactions from a CXL device which hit in the L3 event=0x35,umask=0x78c8c7fd20  01     unc_cha_tor_inserts.cxl_hit_fsrdcur uncore cache FsRdCur transactions from a CXL device which hit in the L3 event=0x35,umask=0x78c8effd20  01     unc_cha_tor_inserts.cxl_hit_fsrdcurptl uncore cache FsRdCurPtl transactions from a CXL device which hit in the L3 event=0x35,umask=0x78c9effd20  01     unc_cha_tor_inserts.cxl_hit_itom uncore cache ItoM transactions from a CXL device which hit in the L3 event=0x35,umask=0x78cc47fd20  01     unc_cha_tor_inserts.cxl_hit_itomwr uncore cache ItoMWr transactions from a CXL device which hit in the L3 event=0x35,umask=0x78cc4ffd20  01     unc_cha_tor_inserts.cxl_hit_mempushwr uncore cache MemPushWr transactions from a CXL device which hit in the L3 event=0x35,umask=0x78cc6ffd20  01     unc_cha_tor_inserts.cxl_hit_wcil uncore cache WCiL transactions from a CXL device which hit in the L3 event=0x35,umask=0x78c86ffd20  01     unc_cha_tor_inserts.cxl_hit_wcilf uncore cache WcilF transactions from a CXL device which hit in the L3 event=0x35,umask=0x78c867fd20  01     unc_cha_tor_inserts.cxl_hit_wil uncore cache WiL transactions from a CXL device which hit in the L3 event=0x35,umask=0x78c87ffd20  01     unc_cha_tor_inserts.cxl_miss_clflush uncore cache CLFlush transactions from a CXL device which miss the L3 event=0x35,umask=0x78c8c7fe20  01     unc_cha_tor_inserts.cxl_miss_fsrdcur uncore cache FsRdCur transactions from a CXL device which miss the L3 event=0x35,umask=0x78c8effe20  01     unc_cha_tor_inserts.cxl_miss_fsrdcurptl uncore cache FsRdCurPtl transactions from a CXL device which miss the L3 event=0x35,umask=0x78c9effe20  01     unc_cha_tor_inserts.cxl_miss_itom uncore cache ItoM transactions from a CXL device which miss the L3 event=0x35,umask=0x78cc47fe20  01     unc_cha_tor_inserts.cxl_miss_itomwr uncore cache ItoMWr transactions from a CXL device which miss the L3 event=0x35,umask=0x78cc4ffe20  01     unc_cha_tor_inserts.cxl_miss_mempushwr uncore cache MemPushWr transactions from a CXL device which miss the L3 event=0x35,umask=0x78cc6ffe20  01     unc_cha_tor_inserts.cxl_miss_wcil uncore cache WCiL transactions from a CXL device which miss the L3 event=0x35,umask=0x78c86ffe20  01     unc_cha_tor_inserts.cxl_miss_wcilf uncore cache WcilF transactions from a CXL device which miss the L3 event=0x35,umask=0x78c867fe20  01     unc_cha_tor_inserts.cxl_miss_wil uncore cache WiL transactions from a CXL device which miss the L3 event=0x35,umask=0x78c87ffe20  01     unc_cha_tor_inserts.ia_drd uncore cache Data read from local IA event=0x35,umask=0xc817ff01  01    TOR Inserts : DRds issued by iA Cores unc_cha_tor_inserts.ia_drdpte uncore cache DRd PTEs issued by iA Cores due to a page walk event=0x35,umask=0xc837ff01  01    TOR Inserts : DRdPte issued by iA Cores due to a page walk unc_cha_tor_inserts.ia_drd_pref uncore cache Data read prefetch from local IA event=0x35,umask=0xc897ff01  01    TOR Inserts : DRd_Prefs issued by iA Cores unc_cha_tor_inserts.ia_hit_drd uncore cache Data read from local IA that hit the cache event=0x35,umask=0xc817fd01  01    TOR Inserts : DRds issued by iA Cores that Hit the LLC unc_cha_tor_inserts.ia_hit_drdpte uncore cache DRd PTEs issued by iA Cores due to page walks that hit the LLC event=0x35,umask=0xc837fd01  01    TOR Inserts : DRdPte issued by iA Cores due to a page walk that hit the LLC unc_cha_tor_inserts.ia_hit_drd_pref uncore cache Data read prefetch from local IA that hit the cache event=0x35,umask=0xc897fd01  01    TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC unc_cha_tor_inserts.ia_miss_crd_pref_remote uncore cache CRD Prefetches from local IA cores to remotely homed memory event=0x35,umask=0xc88f7e01  01    TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely unc_cha_tor_inserts.ia_miss_crd_remote uncore cache CRDs from local IA cores to remotely homed memory event=0x35,umask=0xc80f7e01  01    TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely unc_cha_tor_inserts.ia_miss_drd uncore cache Data read from local IA that miss the cache event=0x35,umask=0xc817fe01  01    TOR Inserts : DRds issued by iA Cores that Missed the LLC unc_cha_tor_inserts.ia_miss_drdpte uncore cache DRd PTEs issued by iA Cores due to a page walk that missed the LLC event=0x35,umask=0xc837fe01  01    TOR Inserts : DRdPte issued by iA Cores due to a page walk that missed the LLC unc_cha_tor_inserts.ia_miss_drd_cxl_acc uncore cache DRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 memory expander card event=0x35,umask=0x10c8178201  01    DRds issued from an IA core which miss the L3 and target memory in a CXL type 2 memory expander card unc_cha_tor_inserts.ia_miss_drd_ddr uncore cache DRds issued by iA Cores targeting DDR Mem that Missed the LLC event=0x35,umask=0xc8178601  01    TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC unc_cha_tor_inserts.ia_miss_drd_local uncore cache Data read from local IA that miss the cache and targets local memory event=0x35,umask=0xc816fe01  01    TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally unc_cha_tor_inserts.ia_miss_drd_local_ddr uncore cache DRds from local IA cores to locally homed DDR addresses that miss the cache event=0x35,umask=0xc8168601  01    TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally unc_cha_tor_inserts.ia_miss_drd_local_pmm uncore cache DRds from local IA cores to locally homed PMM addresses that miss the cache event=0x35,umask=0xc8168a01  01    TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally unc_cha_tor_inserts.ia_miss_drd_pmm uncore cache DRds issued by iA Cores targeting PMM Mem that Missed the LLC event=0x35,umask=0xc8178a01  01    TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC unc_cha_tor_inserts.ia_miss_drd_pref uncore cache Data read prefetch from local IA that miss the cache event=0x35,umask=0xc897fe01  01    TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC unc_cha_tor_inserts.ia_miss_drd_pref_ddr uncore cache DRd Prefetches from local IA cores to DDR addresses that miss the cache event=0x35,umask=0xc8978601  01    TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC unc_cha_tor_inserts.ia_miss_drd_pref_local uncore cache Data read prefetch from local IA that miss the cache and targets local memory event=0x35,umask=0xc896fe01  01    Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF, and target local memory unc_cha_tor_inserts.ia_miss_drd_pref_local_ddr uncore cache DRd Prefetches from local IA cores to locally homed DDR addresses that miss the cache event=0x35,umask=0xc8968601  01    TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally unc_cha_tor_inserts.ia_miss_drd_pref_local_pmm uncore cache DRd Prefetches from local IA cores to locally homed PMM addresses that miss the cache event=0x35,umask=0xc8968a01  01    TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally unc_cha_tor_inserts.ia_miss_drd_pref_pmm uncore cache DRd Prefetches from local IA cores to PMM addresses that miss the cache event=0x35,umask=0xc8978a01  01    TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC unc_cha_tor_inserts.ia_miss_drd_pref_remote uncore cache Data read prefetch from local IA that miss the cache and targets remote memory event=0x35,umask=0xc8977e01  01    Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF, and target remote memory unc_cha_tor_inserts.ia_miss_drd_pref_remote_ddr uncore cache DRd Prefetches from local IA cores to remotely homed DDR addresses that miss the cache event=0x35,umask=0xc8970601  01    TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely unc_cha_tor_inserts.ia_miss_drd_pref_remote_pmm uncore cache DRd Prefetches from local IA cores to remotely homed PMM addresses that miss the cache event=0x35,umask=0xc8970a01  01    TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely unc_cha_tor_inserts.ia_miss_drd_remote uncore cache Data read from local IA that miss the cache and targets remote memory event=0x35,umask=0xc8177e01  01    TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely unc_cha_tor_inserts.ia_miss_drd_remote_ddr uncore cache DRds from local IA cores to remotely homed DDR addresses that miss the cache event=0x35,umask=0xc8170601  01    TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely unc_cha_tor_inserts.ia_miss_drd_remote_pmm uncore cache DRds from local IA cores to remotely homed PMM addresses that miss the cache event=0x35,umask=0xc8170a01  01    TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely unc_cha_tor_inserts.ia_miss_local_wcilf_pmm uncore cache WCILF requests from local IA cores to locally homed PMM addresses which miss the cache event=0x35,umask=0xc8668a01  01    TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally unc_cha_tor_inserts.ia_miss_local_wcil_pmm uncore cache WCIL requests from local IA cores to locally homed PMM addresses which miss the cache event=0x35,umask=0xc86e8a01  01    TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally unc_cha_tor_inserts.ia_miss_remote_wcilf_ddr uncore cache WCILF requests from local IA cores to remotely homed DDR addresses that miss the cache event=0x35,umask=0xc8670601  01    TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely unc_cha_tor_inserts.ia_miss_remote_wcilf_pmm uncore cache WCILF requests from local IA cores to remotely homed PMM addresses which miss the cache event=0x35,umask=0xc8670a01  01    TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely unc_cha_tor_inserts.ia_miss_remote_wcil_ddr uncore cache WCIL requests from local IA cores to remotely homed DDR addresses that miss the cache event=0x35,umask=0xc86f0601  01    TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely unc_cha_tor_inserts.ia_miss_remote_wcil_pmm uncore cache WCIL requests from local IA cores to remotely homed PMM addresses which miss the cache event=0x35,umask=0xc86f0a01  01    TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely unc_cha_tor_inserts.ia_miss_rfo_pref_remote uncore cache Read for ownership prefetch from local IA that miss the LLC targeting remote memory event=0x35,umask=0xc8877e01  01    TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely unc_cha_tor_inserts.ia_miss_rfo_remote uncore cache Read for ownership from local IA that miss the LLC targeting remote memory event=0x35,umask=0xc8077e01  01    TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely unc_cha_tor_inserts.ia_miss_wcilf_pmm uncore cache WCILF requests from local IA cores to PMM homed addresses which miss the cache event=0x35,umask=0xc8678a01  01    TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC unc_cha_tor_inserts.ia_miss_wcil_pmm uncore cache WCIL requests from a local IA core to PMM homed addresses that miss the cache event=0x35,umask=0xc86f8a01  01    TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC unc_cha_tor_inserts.io_itomcachenear_local uncore cache ItoMCacheNear (partial write) transactions from an IO device that addresses memory on the local socket event=0x35,umask=0xcd42ff04  01    TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that address memory on the local socket unc_cha_tor_inserts.io_itomcachenear_remote uncore cache ItoMCacheNear (partial write) transactions from an IO device that addresses memory on a remote socket event=0x35,umask=0xcd437f04  01    TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that address memory on a remote socket unc_cha_tor_inserts.io_itom_local uncore cache ItoM (write) transactions from an IO device that addresses memory on the local socket event=0x35,umask=0xcc42ff04  01    TOR Inserts : ItoM, indicating a write request, from IO Devices that address memory on the local socket unc_cha_tor_inserts.io_itom_remote uncore cache ItoM (write) transactions from an IO device that addresses memory on a remote socket event=0x35,umask=0xcc437f04  01    TOR Inserts : ItoM, indicating a write request, from IO Devices that address memory on a remote socket unc_cha_tor_inserts.io_pcirdcur_local uncore cache PCIRDCUR (read) transactions from an IO device that addresses memory on the local socket event=0x35,umask=0xc8f2ff04  01    TOR Inserts : PCIRdCurs issued by IO Devices that addresses memory on the local socket unc_cha_tor_inserts.io_pcirdcur_remote uncore cache PCIRDCUR (read) transactions from an IO device that addresses memory on a remote socket event=0x35,umask=0xc8f37f04  01    TOR Inserts : PCIRdCurs issued by IO Devices that addresses memory on a remote socket unc_cha_tor_inserts.rem_all uncore cache All remote requests (e.g. snoops, writebacks) that came from remote sockets event=0x35,umask=0xc001ffc8  01    TOR Inserts : All Remote Requests unc_cha_tor_inserts.rem_snps uncore cache All snoops to this LLC that came from remote sockets event=0x35,umask=0xc001ff08  01    TOR Inserts : All Snoops from Remote unc_cha_tor_occupancy.cxl_hit_clflush uncore cache TOR Occupancy for CLFlush transactions from a CXL device which hit in the L3 event=0x36,umask=0x78c8c7fd20  01     unc_cha_tor_occupancy.cxl_hit_fsrdcur uncore cache TOR Occupancy for FsRdCur transactions from a CXL device which hit in the L3 event=0x36,umask=0x78c8effd20  01     unc_cha_tor_occupancy.cxl_hit_fsrdcurptl uncore cache TOR Occupancy for FsRdCurPtl transactions from a CXL device which hit in the L3 event=0x36,umask=0x78c9effd20  01     unc_cha_tor_occupancy.cxl_hit_itom uncore cache TOR Occupancy for ItoM transactions from a CXL device which hit in the L3 event=0x36,umask=0x78cc47fd20  01     unc_cha_tor_occupancy.cxl_hit_itomwr uncore cache TOR Occupancy for ItoMWr transactions from a CXL device which hit in the L3 event=0x36,umask=0x78cc4ffd20  01     unc_cha_tor_occupancy.cxl_hit_mempushwr uncore cache TOR Occupancy for MemPushWr transactions from a CXL device which hit in the L3 event=0x36,umask=0x78cc6ffd20  01     unc_cha_tor_occupancy.cxl_hit_wcil uncore cache TOR Occupancy for WCiL transactions from a CXL device which hit in the L3 event=0x36,umask=0x78c86ffd20  01     unc_cha_tor_occupancy.cxl_hit_wcilf uncore cache TOR Occupancy for WcilF transactions from a CXL device which hit in the L3 event=0x36,umask=0x78c867fd20  01     unc_cha_tor_occupancy.cxl_hit_wil uncore cache TOR Occupancy for WiL transactions from a CXL device which hit in the L3 event=0x36,umask=0x78c87ffd20  01     unc_cha_tor_occupancy.cxl_miss_clflush uncore cache TOR Occupancy for CLFlush transactions from a CXL device which miss the L3 event=0x36,umask=0x78c8c7fe20  01     unc_cha_tor_occupancy.cxl_miss_fsrdcur uncore cache TOR Occupancy for FsRdCur transactions from a CXL device which miss the L3 event=0x36,umask=0x78c8effe20  01     unc_cha_tor_occupancy.cxl_miss_fsrdcurptl uncore cache TOR Occupancy for FsRdCurPtl transactions from a CXL device which miss the L3 event=0x36,umask=0x78c9effe20  01     unc_cha_tor_occupancy.cxl_miss_itom uncore cache TOR Occupancy for ItoM transactions from a CXL device which miss the L3 event=0x36,umask=0x78cc47fe20  01     unc_cha_tor_occupancy.cxl_miss_itomwr uncore cache TOR Occupancy for ItoMWr transactions from a CXL device which miss the L3 event=0x36,umask=0x78cc4ffe20  01     unc_cha_tor_occupancy.cxl_miss_mempushwr uncore cache TOR Occupancy for MemPushWr transactions from a CXL device which miss the L3 event=0x36,umask=0x78cc6ffe20  01     unc_cha_tor_occupancy.cxl_miss_wcil uncore cache TOR Occupancy for WCiL transactions from a CXL device which miss the L3 event=0x36,umask=0x78c86ffe20  01     unc_cha_tor_occupancy.cxl_miss_wcilf uncore cache TOR Occupancy for WcilF transactions from a CXL device which miss the L3 event=0x36,umask=0x78c867fe20  01     unc_cha_tor_occupancy.cxl_miss_wil uncore cache TOR Occupancy for WiL transactions from a CXL device which miss the L3 event=0x36,umask=0x78c87ffe20  01     unc_cha_tor_occupancy.ia_drd uncore cache TOR Occupancy for Data read from local IA that miss the cache event=0x36,umask=0xc817ff01  01    TOR Occupancy : DRds issued by iA Cores unc_cha_tor_occupancy.ia_drdpte uncore cache TOR Occupancy for DRd PTEs issued by iA Cores due to a page walk event=0x36,umask=0xc837ff01  01    TOR Occupancy : DRdPte issued by iA Cores due to a page walk unc_cha_tor_occupancy.ia_drd_pref uncore cache TOR Occupancy for Data read prefetch from local IA that miss the cache event=0x36,umask=0xc897ff01  01    TOR Occupancy : DRd_Prefs issued by iA Cores unc_cha_tor_occupancy.ia_hit_drd uncore cache TOR Occupancy for Data read from local IA that hit the cache event=0x36,umask=0xc817fd01  01    TOR Occupancy : DRds issued by iA Cores that Hit the LLC unc_cha_tor_occupancy.ia_hit_drdpte uncore cache TOR Occupancy for DRd PTEs issued by iA Cores due to page walks that hit the LLC event=0x36,umask=0xc837fd01  01    TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC unc_cha_tor_occupancy.ia_hit_drd_pref uncore cache TOR Occupancy for Data read prefetch from local IA that hit the cache event=0x36,umask=0xc897fd01  01    TOR Occupancy : DRd_Prefs issued by iA Cores that Hit the LLC unc_cha_tor_occupancy.ia_miss_crd_pref_remote uncore cache TOR Occupancy for CRD Prefetches from local IA cores to remotely homed memory event=0x36,umask=0xc88f7e01  01    TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely unc_cha_tor_occupancy.ia_miss_crd_remote uncore cache TOR Occupancy for CRDs from local IA cores to remotely homed memory event=0x36,umask=0xc80f7e01  01    TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely unc_cha_tor_occupancy.ia_miss_drd uncore cache TOR Occupancy for Data read from local IA that miss the cache event=0x36,umask=0xc817fe01  01    TOR Occupancy : DRds issued by iA Cores that Missed the LLC unc_cha_tor_occupancy.ia_miss_drdpte uncore cache TOR Occupancy for DRd PTEs issued by iA Cores due to a page walk that missed the LLC event=0x36,umask=0xc837fe01  01    TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC unc_cha_tor_occupancy.ia_miss_drd_ddr uncore cache TOR Occupancy for DRds issued by iA Cores targeting DDR Mem that Missed the LLC event=0x36,umask=0xc8178601  01    TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC unc_cha_tor_occupancy.ia_miss_drd_local uncore cache TOR Occupancy for Data read from local IA that miss the cache event=0x36,umask=0xc816fe01  01    TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally unc_cha_tor_occupancy.ia_miss_drd_local_ddr uncore cache TOR Occupancy for DRds from local IA cores to locally homed DDR addresses that miss the cache event=0x36,umask=0xc8168601  01    TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally unc_cha_tor_occupancy.ia_miss_drd_local_pmm uncore cache TOR Occupancy for DRds from local IA cores to locally homed PMM addresses that miss the cache event=0x36,umask=0xc8168a01  01    TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally unc_cha_tor_occupancy.ia_miss_drd_pmm uncore cache TOR Occupancy for DRds issued by iA Cores targeting PMM Mem that Missed the LLC event=0x36,umask=0xc8178a01  01    TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC unc_cha_tor_occupancy.ia_miss_drd_pref uncore cache TOR Occupancy for Data read prefetch from local IA that miss the cache event=0x36,umask=0xc897fe01  01    TOR Occupancy : DRd_Prefs issued by iA Cores that Missed the LLC unc_cha_tor_occupancy.ia_miss_drd_pref_ddr uncore cache TOR Occupancy for DRd Prefetches from local IA cores to DDR addresses that miss the cache event=0x36,umask=0xc8978601  01    TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC unc_cha_tor_occupancy.ia_miss_drd_pref_local uncore cache TOR Occupancy for Data read prefetch from local IA that miss the cache event=0x36,umask=0xc896fe01  01    TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_drd_pref_local_ddr uncore cache TOR Occupancy for DRd Prefetches from local IA cores to locally homed DDR addresses that miss the cache event=0x36,umask=0xc8968601  01    TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally unc_cha_tor_occupancy.ia_miss_drd_pref_local_pmm uncore cache TOR Occupancy for DRd Prefetches from local IA cores to locally homed PMM addresses that miss the cache event=0x36,umask=0xc8968a01  01    TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally unc_cha_tor_occupancy.ia_miss_drd_pref_pmm uncore cache TOR Occupancy for DRd Prefetches from local IA cores to PMM addresses that miss the cache event=0x36,umask=0xc8978a01  01    TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC unc_cha_tor_occupancy.ia_miss_drd_pref_remote uncore cache TOR Occupancy for Data read prefetch from local IA that miss the cache event=0x36,umask=0xc8977e01  01    TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_drd_pref_remote_ddr uncore cache TOR Occupancy for DRd Prefetches from local IA cores to remotely homed DDR addresses that miss the cache event=0x36,umask=0xc8970601  01    TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely unc_cha_tor_occupancy.ia_miss_drd_pref_remote_pmm uncore cache TOR Occupancy for DRd Prefetches from local IA cores to remotely homed PMM addresses that miss the cache event=0x36,umask=0xc8970a01  01    TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely unc_cha_tor_occupancy.ia_miss_drd_remote uncore cache TOR Occupancy for Data read from local IA that miss the cache event=0x36,umask=0xc8177e01  01    TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely unc_cha_tor_occupancy.ia_miss_drd_remote_ddr uncore cache TOR Occupancy for DRds from local IA cores to remotely homed DDR addresses that miss the cache event=0x36,umask=0xc8170601  01    TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely unc_cha_tor_occupancy.ia_miss_drd_remote_pmm uncore cache TOR Occupancy for DRds from local IA cores to remotely homed PMM addresses that miss the cache event=0x36,umask=0xc8170a01  01    TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely unc_cha_tor_occupancy.ia_miss_local_wcilf_pmm uncore cache TOR Occupancy for WCILF requests from local IA cores to locally homed PMM addresses which miss the cache event=0x36,umask=0xc8668a01  01    TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally unc_cha_tor_occupancy.ia_miss_local_wcil_pmm uncore cache TOR Occupancy for WCIL requests from local IA cores to locally homed PMM addresses which miss the cache event=0x36,umask=0xc86e8a01  01    TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally unc_cha_tor_occupancy.ia_miss_remote_wcilf_ddr uncore cache TOR Occupancy for WCILF requests from local IA cores to remotely homed DDR addresses that miss the cache event=0x36,umask=0xc8670601  01    TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely unc_cha_tor_occupancy.ia_miss_remote_wcilf_pmm uncore cache TOR Occupancy for WCILF requests from local IA cores to remotely homed PMM addresses which miss the cache event=0x36,umask=0xc8670a01  01    TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely unc_cha_tor_occupancy.ia_miss_remote_wcil_ddr uncore cache TOR Occupancy for WCIL requests from local IA cores to remotely homed DDR addresses that miss the cache event=0x36,umask=0xc86f0601  01    TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely unc_cha_tor_occupancy.ia_miss_remote_wcil_pmm uncore cache TOR Occupancy for WCIL requests from local IA cores to remotely homed PMM addresses which miss the cache event=0x36,umask=0xc86f0a01  01    TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely unc_cha_tor_occupancy.ia_miss_rfo_pref_remote uncore cache TOR Occupancy for Read for ownership prefetch from local IA that miss the cache event=0x36,umask=0xc8877e01  01    TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely unc_cha_tor_occupancy.ia_miss_rfo_remote uncore cache TOR Occupancy for Read for ownership from local IA that miss the cache event=0x36,umask=0xc8077e01  01    TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed remotely unc_cha_tor_occupancy.ia_miss_wcilf_pmm uncore cache TOR Occupancy for WCILF requests from local IA cores to PMM homed addresses which miss the cache event=0x36,umask=0xc8678a01  01    TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC unc_cha_tor_occupancy.ia_miss_wcil_pmm uncore cache TOR Occupancy for WCIL requests from a local IA core to PMM homed addresses that miss the cache event=0x36,umask=0xc86f8a01  01    TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC unc_cha_tor_occupancy.io_miss_itomcachenear_local uncore cache TOR Occupancy for ItoMCacheNear transactions from an IO device on the local socket that miss the cache event=0x36,umask=0xcd42fe04  01    TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC unc_cha_tor_occupancy.io_miss_itomcachenear_remote uncore cache TOR Occupancy for ItoMCacheNear transactions from an IO device on a remote socket that miss the cache event=0x36,umask=0xcd437e04  01    TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC unc_cha_tor_occupancy.io_miss_itom_local uncore cache TOR Occupancy for ItoM transactions from an IO device on the local socket that miss the cache event=0x36,umask=0xcc42fe04  01    TOR Occupancy : ItoMs issued by IO Devices that missed the LLC unc_cha_tor_occupancy.io_miss_itom_remote uncore cache TOR Occupancy for ItoM transactions from an IO device on a remote socket that miss the cache event=0x36,umask=0xcc437e04  01    TOR Occupancy : ItoMs issued by IO Devices that missed the LLC unc_cha_tor_occupancy.io_miss_pcirdcur_local uncore cache TOR Occupancy for PCIRDCUR transactions from an IO device on the local socket that miss the cache event=0x36,umask=0xc8f2fe04  01    TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC unc_cha_tor_occupancy.io_miss_pcirdcur_remote uncore cache TOR Occupancy for PCIRDCUR transactions from an IO device on a remote socket that miss the cache event=0x36,umask=0xc8f37e04  01    TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC unc_cha_tor_occupancy.rem_all uncore cache TOR Occupancy for All remote requests (e.g. snoops, writebacks) that came from remote sockets event=0x36,umask=0xc001ffc8  01    TOR Occupancy : All Remote Requests unc_cha_tor_occupancy.rem_snps uncore cache TOR Occupancy for All snoops to this LLC that came from remote sockets event=0x36,umask=0xc001ff08  01    TOR Occupancy : All Snoops from Remote uncore_b2cxl unc_b2cxl_clockticks uncore cxl B2CXL Clockticks event=1  01     unc_b2cmi_direct2core_not_taken_dirstate uncore interconnect Counts the number of time D2C was not honoured by egress due to directory state constraints event=0x17,umask=1  01     unc_b2cmi_direct2upi_not_taken_credits uncore interconnect Counts the number of d2k wasn't done due to credit constraints event=0x1b,umask=1  01     unc_b2cmi_direct2upi_not_taken_credits.egress uncore interconnect Direct to UPI Transactions - Ignored due to lack of credits : All : Counts the number of d2k wasn't done due to credit constraints event=0x1b,umask=1  01     unc_b2cmi_direct2upi_not_taken_dirstate uncore interconnect Counts the number of time D2K was not honoured by egress due to directory state constraints event=0x1a,umask=1  01     unc_b2cmi_direct2upi_not_taken_dirstate.egress uncore interconnect Cycles when Direct2UPI was Disabled : Egress Ignored D2U : Counts the number of time D2K was not honoured by egress due to directory state constraints event=0x1a,umask=1  01     unc_b2cmi_direct2upi_taken uncore interconnect Counts the number of times egress did D2K (Direct to KTI) event=0x19,umask=1  01     unc_b2cmi_direct2upi_txn_override uncore interconnect Counts the number of times D2K wasn't honoured even though the incoming request had d2k set for non cisgress txn event=0x1c,umask=1  01     unc_b2cmi_directory_hit.clean uncore interconnect Directory Hit Clean event=0x1d,umask=0x38  01     unc_b2cmi_directory_hit.clean_a uncore interconnect Directory Hit : On NonDirty Line in A State event=0x1d,umask=0x20  01     unc_b2cmi_directory_hit.clean_i uncore interconnect Directory Hit : On NonDirty Line in I State event=0x1d,umask=8  01     unc_b2cmi_directory_hit.clean_s uncore interconnect Directory Hit : On NonDirty Line in S State event=0x1d,umask=0x10  01     unc_b2cmi_directory_hit.dirty uncore interconnect Directory Hit Dirty (modified) event=0x1d,umask=7  01     unc_b2cmi_directory_hit.dirty_a uncore interconnect Directory Hit : On Dirty Line in A State event=0x1d,umask=4  01     unc_b2cmi_directory_hit.dirty_i uncore interconnect Directory Hit : On Dirty Line in I State event=0x1d,umask=1  01     unc_b2cmi_directory_hit.dirty_s uncore interconnect Directory Hit : On Dirty Line in S State event=0x1d,umask=2  01     unc_b2cmi_directory_lookup.any uncore interconnect Counts the number of 1lm or 2lm hit read data returns to egress with any directory to non persistent memory event=0x20,umask=1  01     unc_b2cmi_directory_lookup.state_a uncore interconnect Counts the number of 1lm or 2lm hit read data returns to egress with directory A to non persistent memory event=0x20,umask=8  01     unc_b2cmi_directory_lookup.state_i uncore interconnect Counts the number of 1lm or 2lm hit read data returns to egress with directory I to non persistent memory event=0x20,umask=2  01     unc_b2cmi_directory_lookup.state_s uncore interconnect Counts the number of 1lm or 2lm hit read data returns to egress with directory S to non persistent memory event=0x20,umask=4  01    Counts the number of 1lm or 2lm hit read  data returns to egress with directory S to non persistent memory unc_b2cmi_directory_miss.clean uncore interconnect Directory Miss Clean event=0x1e,umask=0x38  01     unc_b2cmi_directory_miss.clean_a uncore interconnect Directory Miss : On NonDirty Line in A State event=0x1e,umask=0x20  01     unc_b2cmi_directory_miss.clean_i uncore interconnect Directory Miss : On NonDirty Line in I State event=0x1e,umask=8  01     unc_b2cmi_directory_miss.clean_s uncore interconnect Directory Miss : On NonDirty Line in S State event=0x1e,umask=0x10  01     unc_b2cmi_directory_miss.dirty uncore interconnect Directory Miss Dirty (modified) event=0x1e,umask=7  01     unc_b2cmi_directory_miss.dirty_a uncore interconnect Directory Miss : On Dirty Line in A State event=0x1e,umask=4  01     unc_b2cmi_directory_miss.dirty_i uncore interconnect Directory Miss : On Dirty Line in I State event=0x1e,umask=1  01     unc_b2cmi_directory_miss.dirty_s uncore interconnect Directory Miss : On Dirty Line in S State event=0x1e,umask=2  01     unc_b2cmi_directory_update.a2i uncore interconnect Any A2I Transition event=0x21,umask=0x320  01     unc_b2cmi_directory_update.a2s uncore interconnect Any A2S Transition event=0x21,umask=0x340  01     unc_b2cmi_directory_update.any uncore interconnect Counts cisgress directory updates event=0x21,umask=0x301  01     unc_b2cmi_directory_update.hit_any uncore interconnect Counts any 1lm or 2lm hit data return that would result in directory update to non persistent memory (DRAM) event=0x21,umask=0x101  01     unc_b2cmi_directory_update.hit_x2a uncore interconnect Directory update in near memory to the A state event=0x21,umask=0x114  01     unc_b2cmi_directory_update.hit_x2i uncore interconnect Directory update in near memory to the I state event=0x21,umask=0x128  01     unc_b2cmi_directory_update.hit_x2s uncore interconnect Directory update in near memory to the S state event=0x21,umask=0x142  01     unc_b2cmi_directory_update.i2a uncore interconnect Any I2A Transition event=0x21,umask=0x304  01     unc_b2cmi_directory_update.i2s uncore interconnect Any I2S Transition event=0x21,umask=0x302  01     unc_b2cmi_directory_update.miss_x2a uncore interconnect Directory update in far memory to the A state event=0x21,umask=0x214  01     unc_b2cmi_directory_update.miss_x2i uncore interconnect Directory update in far memory to the I state event=0x21,umask=0x228  01     unc_b2cmi_directory_update.miss_x2s uncore interconnect Directory update in far memory to the S state event=0x21,umask=0x242  01     unc_b2cmi_directory_update.s2a uncore interconnect Any S2A Transition event=0x21,umask=0x310  01     unc_b2cmi_directory_update.s2i uncore interconnect Any S2I Transition event=0x21,umask=0x308  01     unc_b2cmi_directory_update.x2a uncore interconnect Directory update to the A state event=0x21,umask=0x314  01     unc_b2cmi_directory_update.x2i uncore interconnect Directory update to the I state event=0x21,umask=0x328  01     unc_b2cmi_directory_update.x2s uncore interconnect Directory update to the S state event=0x21,umask=0x342  01     unc_b2cmi_imc_reads.to_ddr_as_cache uncore interconnect Count reads to NM region event=0x24,umask=0x110  01     unc_b2cmi_imc_writes.ni uncore interconnect Non-Inclusive - All Channels event=0x25  01     unc_b2cmi_imc_writes.ni_miss uncore interconnect Non-Inclusive Miss - All Channels event=0x25  01     unc_b2cmi_imc_writes.to_ddr_as_cache uncore interconnect DDR, acting as Cache - All Channels event=0x25,umask=0x140  01     unc_b2cmi_prefcam_inserts.ch0_upi uncore interconnect Prefetch CAM Inserts : UPI - Ch 0 event=0x56,umask=2  01     unc_b2cmi_prefcam_inserts.upi_allch uncore interconnect Prefetch CAM Inserts : UPI - All Channels event=0x56,umask=2  01     unc_b2cmi_tag_hit.all uncore interconnect Counts the 2lm reads and WRNI which were a hit event=0x1f,umask=0xf  01     unc_b2cmi_tag_hit.rd_clean uncore interconnect Counts the 2lm reads which were a hit clean event=0x1f,umask=1  01     unc_b2cmi_tag_hit.rd_dirty uncore interconnect Counts the 2lm reads which were a hit dirty event=0x1f,umask=2  01     unc_b2cmi_tag_hit.wr_clean uncore interconnect Counts the 2lm WRNI which were a hit clean event=0x1f,umask=4  01     unc_b2cmi_tag_hit.wr_dirty uncore interconnect Counts the 2lm WRNI which were a hit dirty event=0x1f,umask=8  01     unc_b2cmi_tag_miss.clean uncore interconnect Counts the 2lm second way read miss for a WrNI event=0x4b,umask=5  01     unc_b2cmi_tag_miss.dirty uncore interconnect Counts the 2lm second way read miss for a WrNI event=0x4b,umask=0xa  01     unc_b2cmi_tag_miss.rd_2way uncore interconnect Counts the 2lm second way read miss for a Rd event=0x4b,umask=0x10  01     unc_b2cmi_tag_miss.rd_clean uncore interconnect Counts the 2lm reads which were a miss and the cache line is unmodified event=0x4b,umask=1  01     unc_b2cmi_tag_miss.rd_dirty uncore interconnect Counts the 2lm reads which were a miss and the cache line is modified event=0x4b,umask=2  01     unc_b2cmi_tag_miss.wr_2way uncore interconnect Counts the 2lm second way read miss for a WrNI event=0x4b,umask=0x20  01     unc_b2cmi_tag_miss.wr_clean uncore interconnect Counts the 2lm WRNI which were a miss and the cache line is unmodified event=0x4b,umask=4  01     unc_b2cmi_tag_miss.wr_dirty uncore interconnect Counts the 2lm WRNI which were a miss and the cache line is modified event=0x4b,umask=8  01     uncore_b2hot unc_b2hot_clockticks uncore interconnect UNC_B2HOT_CLOCKTICKS event=1,umask=1  01    Clockticks for the B2HOT unit uncore_b2upi unc_b2upi_clockticks uncore interconnect Number of uclks in domain event=1  01     unc_i_misc1.sec_rcvd_invld uncore interconnect Misc Events - Set 1 : Received Invalid : Secondary received a transfer that did not have sufficient MESI state event=0x1f,umask=0x20  01     unc_mdf_clockticks uncore interconnect MDF Clockticks event=1  01     unc_mdf_rxr_bypass.ad_bnc uncore interconnect Number of packets bypassing the ingress queue event=0x14,umask=1  01     unc_mdf_rxr_bypass.ad_crd uncore interconnect Number of packets bypassing the ingress queue event=0x14,umask=0x10  01     unc_mdf_rxr_bypass.ak uncore interconnect Number of packets bypassing the ingress queue event=0x14,umask=2  01     unc_mdf_rxr_bypass.bl_bnc uncore interconnect Number of packets bypassing the ingress queue event=0x14,umask=4  01     unc_mdf_rxr_bypass.bl_crd uncore interconnect Number of packets bypassing the ingress queue event=0x14,umask=0x20  01     unc_mdf_rxr_bypass.iv uncore interconnect Number of packets bypassing the ingress queue event=0x14,umask=8  01     unc_mdf_rxr_inserts.ad_bnc uncore interconnect Number of allocations into the Ingress  used to queue up requests from the mesh (AD_BNC) event=0x12,umask=1  01     unc_mdf_rxr_inserts.ad_crd uncore interconnect Number of allocations into the Ingress  used to queue up requests from the mesh (AD) event=0x12,umask=0x10  01     unc_mdf_rxr_inserts.ak uncore interconnect Number of allocations into the Ingress  used to queue up requests from the mesh (AK) event=0x12,umask=2  01     unc_mdf_rxr_inserts.bl_bnc uncore interconnect Number of allocations into the Ingress  used to queue up requests from the mesh (BL_BNC) event=0x12,umask=4  01     unc_mdf_rxr_inserts.bl_crd uncore interconnect Number of allocations into the Ingress  used to queue up requests from the mesh (BL_CRD) event=0x12,umask=0x20  01     unc_mdf_rxr_inserts.iv uncore interconnect Number of allocations into the Ingress  used to queue up requests from the mesh (IV) event=0x12,umask=8  01     unc_mdf_rxr_occupancy.ad_bnc uncore interconnect Occupancy counts for the Ingress buffer event=0x13,umask=1  01     unc_mdf_rxr_occupancy.ad_crd uncore interconnect Occupancy counts for the Ingress buffer event=0x13,umask=0x10  01     unc_mdf_rxr_occupancy.ak uncore interconnect Occupancy counts for the Ingress buffer event=0x13,umask=2  01     unc_mdf_rxr_occupancy.bl_bnc uncore interconnect Occupancy counts for the Ingress buffer event=0x13,umask=4  01     unc_mdf_rxr_occupancy.bl_crd uncore interconnect Occupancy counts for the Ingress buffer event=0x13,umask=0x20  01     unc_mdf_rxr_occupancy.iv uncore interconnect Occupancy counts for the Ingress buffer event=0x13,umask=8  01     unc_mdf_txr_bypass.ad_bnc uncore interconnect Egress bypasses for AD_BNC event=0x1e,umask=1  01     unc_mdf_txr_bypass.ad_crd uncore interconnect Egress bypasses for AD_CRD event=0x1e,umask=0x10  01     unc_mdf_txr_bypass.ak uncore interconnect Egress bypasses for AK event=0x1e,umask=2  01     unc_mdf_txr_bypass.bl_bnc uncore interconnect Egress bypasses for BL_BNC event=0x1e,umask=4  01     unc_mdf_txr_bypass.bl_crd uncore interconnect Egress bypasses for BL_CRD event=0x1e,umask=0x20  01     unc_mdf_txr_bypass.iv uncore interconnect Egress bypasses for IV event=0x1e,umask=8  01     unc_mdf_txr_inserts.ad_bnc uncore interconnect Number of egress inserts for AD_BNC event=0x1c,umask=1  01     unc_mdf_txr_inserts.ad_crd uncore interconnect Number of egress inserts for AD_CRD event=0x1c,umask=0x10  01     unc_mdf_txr_inserts.ak uncore interconnect Number of egress inserts for AK event=0x1c,umask=2  01     unc_mdf_txr_inserts.bl_bnc uncore interconnect Number of egress inserts for BL_BNC event=0x1c,umask=4  01     unc_mdf_txr_inserts.bl_crd uncore interconnect Number of egress inserts for BL_CRD event=0x1c,umask=0x20  01     unc_mdf_txr_inserts.iv uncore interconnect Number of egress inserts for IV event=0x1c,umask=8  01     unc_mdf_txr_occupancy.ad_bnc uncore interconnect Egress occupancy for AD_BNC event=0x1d,umask=1  01     unc_mdf_txr_occupancy.ad_crd uncore interconnect Egress occupancy for AD_CRD event=0x1d,umask=0x10  01     unc_mdf_txr_occupancy.ak uncore interconnect Egress occupancy for AK event=0x1d,umask=2  01     unc_mdf_txr_occupancy.bl_bnc uncore interconnect Egress occupancy for BL_BNC event=0x1d,umask=4  01     unc_mdf_txr_occupancy.bl_crd uncore interconnect Egress occupancy for BL_CRD event=0x1d,umask=0x20  01     unc_mdf_txr_occupancy.iv uncore interconnect Egress occupancy for IV event=0x1d,umask=8  01     unc_upi_clockticks uncore interconnect Number of UPI LL clock cycles while the event is enabled event=1  01    Number of kfclks unc_upi_l1_power_cycles uncore interconnect Cycles in L1 : Number of UPI qfclk cycles spent in L1 power mode.  L1 is a mode that totally shuts down a UPI link.  Use edge detect to count the number of instances when the UPI link entered L1.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode event=0x21  01     unc_upi_rxl_basic_hdr_match.ncb uncore interconnect Matches on Receive path of a UPI Port : Non-Coherent Bypass event=5,umask=0xe  01     unc_upi_rxl_basic_hdr_match.ncb_opc uncore interconnect Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode event=5,umask=0x10e  01     unc_upi_rxl_basic_hdr_match.ncs uncore interconnect Matches on Receive path of a UPI Port : Non-Coherent Standard event=5,umask=0xf  01     unc_upi_rxl_basic_hdr_match.ncs_opc uncore interconnect Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode event=5,umask=0x10f  01     unc_upi_rxl_basic_hdr_match.req uncore interconnect Matches on Receive path of a UPI Port : Request event=5,umask=8  01     unc_upi_rxl_basic_hdr_match.req_opc uncore interconnect Matches on Receive path of a UPI Port : Request, Match Opcode event=5,umask=0x108  01     unc_upi_rxl_basic_hdr_match.rspcnflt uncore interconnect Matches on Receive path of a UPI Port : Response - Conflict event=5,umask=0x1aa  01     unc_upi_rxl_basic_hdr_match.rspi uncore interconnect Matches on Receive path of a UPI Port : Response - Invalid event=5,umask=0x12a  01     unc_upi_rxl_basic_hdr_match.rsp_data uncore interconnect Matches on Receive path of a UPI Port : Response - Data event=5,umask=0xc  01     unc_upi_rxl_basic_hdr_match.rsp_data_opc uncore interconnect Matches on Receive path of a UPI Port : Response - Data, Match Opcode event=5,umask=0x10c  01     unc_upi_rxl_basic_hdr_match.rsp_nodata uncore interconnect Matches on Receive path of a UPI Port : Response - No Data event=5,umask=0xa  01     unc_upi_rxl_basic_hdr_match.rsp_nodata_opc uncore interconnect Matches on Receive path of a UPI Port : Response - No Data, Match Opcode event=5,umask=0x10a  01     unc_upi_rxl_basic_hdr_match.snp uncore interconnect Matches on Receive path of a UPI Port : Snoop event=5,umask=9  01     unc_upi_rxl_basic_hdr_match.snp_opc uncore interconnect Matches on Receive path of a UPI Port : Snoop, Match Opcode event=5,umask=0x109  01     unc_upi_rxl_basic_hdr_match.wb uncore interconnect Matches on Receive path of a UPI Port : Writeback event=5,umask=0xd  01     unc_upi_rxl_basic_hdr_match.wb_opc uncore interconnect Matches on Receive path of a UPI Port : Writeback, Match Opcode event=5,umask=0x10d  01     unc_upi_rxl_flits.all_data uncore interconnect Valid Flits Received : All Data : Shows legal flit time (hides impact of L0p and L0c) event=3,umask=0xf  01     unc_upi_rxl_flits.all_null uncore interconnect Null FLITs received from any slot event=3,umask=0x27  01    Valid Flits Received : Null FLITs received from any slot unc_upi_rxl_flits.data uncore interconnect Valid Flits Received : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting. event=3,umask=8  01     unc_upi_rxl_flits.idle uncore interconnect Valid Flits Received : Idle : Shows legal flit time (hides impact of L0p and L0c) event=3,umask=0x47  01     unc_upi_rxl_flits.llcrd uncore interconnect Valid Flits Received : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2 event=3,umask=0x10  01     unc_upi_rxl_flits.llctrl uncore interconnect Valid Flits Received : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet.  Enables counting of slot 0 LLCTRL messages event=3,umask=0x40  01     unc_upi_rxl_flits.non_data uncore interconnect Valid Flits Received : All Non Data : Shows legal flit time (hides impact of L0p and L0c) event=3,umask=0x97  01     unc_upi_rxl_flits.null uncore interconnect Valid Flits Received : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2 event=3,umask=0x20  01     unc_upi_rxl_flits.prothdr uncore interconnect Valid Flits Received : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits) event=3,umask=0x80  01     unc_upi_rxl_flits.slot0 uncore interconnect Valid Flits Received : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count event=3,umask=1  01     unc_upi_rxl_flits.slot1 uncore interconnect Valid Flits Received : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count event=3,umask=2  01     unc_upi_rxl_flits.slot2 uncore interconnect Valid Flits Received : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count event=3,umask=4  01     unc_upi_rxl_inserts.slot0 uncore interconnect RxQ Flit Buffer Allocations : Slot 0 : Number of allocations into the UPI Rx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime event=0x30,umask=1  01     unc_upi_rxl_inserts.slot1 uncore interconnect RxQ Flit Buffer Allocations : Slot 1 : Number of allocations into the UPI Rx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime event=0x30,umask=2  01     unc_upi_rxl_inserts.slot2 uncore interconnect RxQ Flit Buffer Allocations : Slot 2 : Number of allocations into the UPI Rx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime event=0x30,umask=4  01     unc_upi_rxl_occupancy.slot0 uncore interconnect RxQ Occupancy - All Packets : Slot 0 event=0x32,umask=1  01     unc_upi_rxl_occupancy.slot1 uncore interconnect RxQ Occupancy - All Packets : Slot 1 event=0x32,umask=2  01     unc_upi_rxl_occupancy.slot2 uncore interconnect RxQ Occupancy - All Packets : Slot 2 event=0x32,umask=4  01     unc_upi_txl0p_power_cycles uncore interconnect Cycles in L0p event=0x27  01     unc_upi_txl_basic_hdr_match.ncb uncore interconnect Matches on Transmit path of a UPI Port : Non-Coherent Bypass event=4,umask=0xe  01     unc_upi_txl_basic_hdr_match.ncb_opc uncore interconnect Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode event=4,umask=0x10e  01     unc_upi_txl_basic_hdr_match.ncs uncore interconnect Matches on Transmit path of a UPI Port : Non-Coherent Standard event=4,umask=0xf  01     unc_upi_txl_basic_hdr_match.ncs_opc uncore interconnect Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode event=4,umask=0x10f  01     unc_upi_txl_basic_hdr_match.req uncore interconnect Matches on Transmit path of a UPI Port : Request event=4,umask=8  01     unc_upi_txl_basic_hdr_match.req_opc uncore interconnect Matches on Transmit path of a UPI Port : Request, Match Opcode event=4,umask=0x108  01     unc_upi_txl_basic_hdr_match.rspcnflt uncore interconnect Matches on Transmit path of a UPI Port : Response - Conflict event=4,umask=0x1aa  01     unc_upi_txl_basic_hdr_match.rspi uncore interconnect Matches on Transmit path of a UPI Port : Response - Invalid event=4,umask=0x12a  01     unc_upi_txl_basic_hdr_match.rsp_data uncore interconnect Matches on Transmit path of a UPI Port : Response - Data event=4,umask=0xc  01     unc_upi_txl_basic_hdr_match.rsp_data_opc uncore interconnect Matches on Transmit path of a UPI Port : Response - Data, Match Opcode event=4,umask=0x10c  01     unc_upi_txl_basic_hdr_match.rsp_nodata uncore interconnect Matches on Transmit path of a UPI Port : Response - No Data event=4,umask=0xa  01     unc_upi_txl_basic_hdr_match.rsp_nodata_opc uncore interconnect Matches on Transmit path of a UPI Port : Response - No Data, Match Opcode event=4,umask=0x10a  01     unc_upi_txl_basic_hdr_match.snp uncore interconnect Matches on Transmit path of a UPI Port : Snoop event=4,umask=9  01     unc_upi_txl_basic_hdr_match.snp_opc uncore interconnect Matches on Transmit path of a UPI Port : Snoop, Match Opcode event=4,umask=0x109  01     unc_upi_txl_basic_hdr_match.wb uncore interconnect Matches on Transmit path of a UPI Port : Writeback event=4,umask=0xd  01     unc_upi_txl_basic_hdr_match.wb_opc uncore interconnect Matches on Transmit path of a UPI Port : Writeback, Match Opcode event=4,umask=0x10d  01     unc_upi_txl_flits.all_data uncore interconnect Valid Flits Sent : All Data : Counts number of data flits across this UPI link event=2,umask=0xf  01     unc_upi_txl_flits.all_null uncore interconnect All Null Flits event=2,umask=0x27  01    Valid Flits Sent : Idle unc_upi_txl_flits.data uncore interconnect Valid Flits Sent : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting. event=2,umask=8  01     unc_upi_txl_flits.idle uncore interconnect Valid Flits Sent : Idle : Shows legal flit time (hides impact of L0p and L0c) event=2,umask=0x47  01     unc_upi_txl_flits.llcrd uncore interconnect Valid Flits Sent : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2 event=2,umask=0x10  01     unc_upi_txl_flits.llctrl uncore interconnect Valid Flits Sent : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet.  Enables counting of slot 0 LLCTRL messages event=2,umask=0x40  01     unc_upi_txl_flits.non_data uncore interconnect Valid Flits Sent : All Non Data : Shows legal flit time (hides impact of L0p and L0c) event=2,umask=0x97  01    Valid Flits Sent : Null FLITs transmitted to any slot unc_upi_txl_flits.null uncore interconnect Valid Flits Sent : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2 event=2,umask=0x20  01     unc_upi_txl_flits.prothdr uncore interconnect Valid Flits Sent : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits) event=2,umask=0x80  01     unc_upi_txl_flits.slot0 uncore interconnect Valid Flits Sent : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count event=2,umask=1  01     unc_upi_txl_flits.slot1 uncore interconnect Valid Flits Sent : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count event=2,umask=2  01     unc_upi_txl_flits.slot2 uncore interconnect Valid Flits Sent : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count event=2,umask=4  01     unc_iio_data_req_by_cpu.peer_read.all_parts uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0xff,fc_mask=7,umask=8  01     unc_iio_data_req_by_cpu.peer_write.all_parts uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0xff,fc_mask=7,umask=2  01     unc_iio_data_req_of_cpu.mem_read.all_parts uncore io Counts once for every 4 bytes read from this card to memory.  This event does include reads to IO event=0x83,ch_mask=0xff,fc_mask=7,umask=4  01     unc_iio_data_req_of_cpu.mem_write.all_parts uncore io Counts once for every 4 bytes written from this card to memory.  This event does include writes to IO event=0x83,ch_mask=0xff,fc_mask=7,umask=1  01     unc_iio_data_req_of_cpu.peer_read.part0 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=1,fc_mask=7,umask=8  01     unc_iio_data_req_of_cpu.peer_read.part1 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=2,fc_mask=7,umask=8  01     unc_iio_data_req_of_cpu.peer_read.part2 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=4,fc_mask=7,umask=8  01     unc_iio_data_req_of_cpu.peer_read.part3 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=8,fc_mask=7,umask=8  01     unc_iio_data_req_of_cpu.peer_read.part4 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=0x10,fc_mask=7,umask=8  01     unc_iio_data_req_of_cpu.peer_read.part5 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=0x20,fc_mask=7,umask=8  01     unc_iio_data_req_of_cpu.peer_read.part6 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=0x40,fc_mask=7,umask=8  01     unc_iio_data_req_of_cpu.peer_read.part7 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=0x80,fc_mask=7,umask=8  01     unc_iio_data_req_of_cpu.peer_write.all_parts uncore io Counts once for every 4 bytes written from this card to a peer device's IO space event=0x83,ch_mask=0xff,fc_mask=7,umask=2  01     unc_iio_iommu0.all_lookups uncore io IOTLB lookups all event=0x40,umask=2  01     unc_iio_iommu1.num_mem_accesses_high uncore io IOMMU high priority memory access event=0x41,umask=0x80  01     unc_iio_iommu1.num_mem_accesses_low uncore io IOMMU low priority memory access event=0x41,umask=0x40  01     unc_iio_iommu1.slpwc_2m_hits uncore io Second Level Page Walk Cache Hit to a 2M page event=0x41,umask=2  01     unc_iio_iommu1.slpwc_cache_fills uncore io Second Level Page Walk Cache fill event=0x41,umask=0x20  01     unc_iio_iommu1.slpwc_cache_lookups uncore io Second Level Page Walk Cache lookup event=0x41,umask=1  01     unc_iio_iommu3.cyc_pwt_full uncore io Cycles PWT full event=0x43,umask=2  01     unc_iio_iommu3.int_cache_hits uncore io Interrupt Entry cache hit event=0x43,umask=0x80  01     unc_iio_iommu3.int_cache_lookups uncore io Interrupt Entry cache lookup event=0x43,umask=0x40  01     unc_iio_iommu3.num_inval_ctxt_cache uncore io Context Cache invalidation events event=0x43,umask=8  01     unc_iio_iommu3.num_inval_int_cache uncore io Interrupt Entry Cache invalidation events event=0x43,umask=0x20  01     unc_iio_iommu3.num_inval_iotlb uncore io IOTLB invalidation events event=0x43,umask=4  01     unc_iio_iommu3.num_inval_pasid_cache uncore io PASID Cache invalidation events event=0x43,umask=0x10  01     unc_iio_num_oustanding_req_from_cpu.to_io uncore io This event is deprecated. [This event is alias to UNC_IIO_NUM_OUTSTANDING_REQ_FROM_CPU.TO_IO] event=0xc5,ch_mask=0xff,fc_mask=7,umask=8  11     unc_iio_num_outstanding_req_from_cpu.to_io uncore io Occupancy of outbound request queue : To device : Counts number of outbound requests/completions IIO is currently processing [This event is alias to UNC_IIO_NUM_OUSTANDING_REQ_FROM_CPU.TO_IO] event=0xc5,ch_mask=0xff,fc_mask=7,umask=8  01     unc_iio_num_outstanding_req_of_cpu.data uncore io Passing data to be written event=0x88,ch_mask=0xff,fc_mask=7,umask=0x20  01     unc_iio_num_outstanding_req_of_cpu.final_rd_wr uncore io Issuing final read or write of line event=0x88,ch_mask=0xff,fc_mask=7,umask=8  01     unc_iio_num_outstanding_req_of_cpu.iommu_hit uncore io Processing response from IOMMU event=0x88,ch_mask=0xff,fc_mask=7,umask=2  01     unc_iio_num_outstanding_req_of_cpu.iommu_req uncore io Issuing to IOMMU event=0x88,ch_mask=0xff,fc_mask=7,umask=1  01     unc_iio_num_outstanding_req_of_cpu.req_own uncore io Request Ownership event=0x88,ch_mask=0xff,fc_mask=7,umask=4  01     unc_iio_num_outstanding_req_of_cpu.wr uncore io Writing line event=0x88,ch_mask=0xff,fc_mask=7,umask=0x10  01     unc_iio_num_req_of_cpu_by_tgt.rem_p2p uncore io - event=0x8e,ch_mask=0xff,fc_mask=7,umask=0x10  01     unc_iio_txn_req_by_cpu.mem_read.all_parts uncore io Number Transactions requested by the CPU : Core reading from Cards MMIO space event=0xc1,ch_mask=0xff,fc_mask=7,umask=4  01     unc_iio_txn_req_by_cpu.mem_write.all_parts uncore io Number Transactions requested by the CPU : Core writing to Cards MMIO space event=0xc1,ch_mask=0xff,fc_mask=7,umask=1  01     unc_iio_txn_req_by_cpu.peer_read.all_parts uncore io Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card event=0xc1,ch_mask=0xff,fc_mask=7,umask=8  01     unc_iio_txn_req_by_cpu.peer_write.all_parts uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0xff,fc_mask=7,umask=2  01     unc_iio_txn_req_of_cpu.peer_read.part0 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=1,fc_mask=7,umask=8  01     unc_iio_txn_req_of_cpu.peer_read.part1 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=2,fc_mask=7,umask=8  01     unc_iio_txn_req_of_cpu.peer_read.part2 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=4,fc_mask=7,umask=8  01     unc_iio_txn_req_of_cpu.peer_read.part3 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=8,fc_mask=7,umask=8  01     unc_iio_txn_req_of_cpu.peer_read.part4 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=0x10,fc_mask=7,umask=8  01     unc_iio_txn_req_of_cpu.peer_read.part5 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=0x20,fc_mask=7,umask=8  01     unc_iio_txn_req_of_cpu.peer_read.part6 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=0x40,fc_mask=7,umask=8  01     unc_iio_txn_req_of_cpu.peer_read.part7 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=0x80,fc_mask=7,umask=8  01     unc_m_cas_count_sch0.rd_non_underfill uncore memory CAS count for SubChannel 0 regular reads event=5,umask=0xc3  01     unc_m_cas_count_sch0.rd_pre_reg uncore memory CAS count for SubChannel 0 auto-precharge reads event=5,umask=0xc2  01     unc_m_cas_count_sch0.rd_pre_underfill uncore memory CAS count for SubChannel 0 auto-precharge underfill reads event=5,umask=0xc8  01     unc_m_cas_count_sch0.rd_underfill_all uncore memory CAS count for SubChannel 0 underfill reads event=5,umask=0xcc  01     unc_m_cas_count_sch1.rd_non_underfill uncore memory CAS count for SubChannel 1 regular reads event=6,umask=0xc3  01     unc_m_cas_count_sch1.rd_pre_reg uncore memory CAS count for SubChannel 1 auto-precharge reads event=6,umask=0xc2  01     unc_m_cas_count_sch1.rd_pre_underfill uncore memory CAS count for SubChannel 1 auto-precharge underfill reads event=6,umask=0xc8  01     unc_m_cas_count_sch1.rd_underfill_all uncore memory CAS count for SubChannel 1 underfill reads event=6,umask=0xcc  01     unc_m_mntcmd_refrate.refab1x uncore memory PMMNT is sending REF* commands while being in specified Refresh rate event=0x72,umask=1  01     unc_m_mntcmd_refrate.refab2x uncore memory PMMNT is sending REF* commands while being in specified Refresh rate event=0x72,umask=4  01     unc_m_mntcmd_refrate.refsb1x uncore memory PMMNT is sending REF* commands while being in specified Refresh rate event=0x72,umask=2  01     unc_m_mntcmd_refrate.refsb2x uncore memory PMMNT is sending REF* commands while being in specified Refresh rate event=0x72,umask=8  01     unc_m_mr4_2xref_cycles.sch0_dimm0 uncore memory # of cycles MR4 temp readings forced 2x refresh event=0xa7,umask=1  01     unc_m_mr4_2xref_cycles.sch0_dimm1 uncore memory # of cycles MR4 temp readings forced 2x refresh event=0xa7,umask=2  01     unc_m_mr4_2xref_cycles.sch1_dimm0 uncore memory # of cycles MR4 temp readings forced 2x refresh event=0xa7,umask=4  01     unc_m_mr4_2xref_cycles.sch1_dimm1 uncore memory # of cycles MR4 temp readings forced 2x refresh event=0xa7,umask=8  01     unc_m_pdc_mr4active_cycles.sch0_dimm0 uncore memory # of cycles MR4 MRRs was triggered/running event=0xa6,umask=1  01     unc_m_pdc_mr4active_cycles.sch0_dimm1 uncore memory # of cycles MR4 MRRs was triggered/running event=0xa6,umask=2  01     unc_m_pdc_mr4active_cycles.sch1_dimm0 uncore memory # of cycles MR4 MRRs was triggered/running event=0xa6,umask=4  01     unc_m_pdc_mr4active_cycles.sch1_dimm1 uncore memory # of cycles MR4 MRRs was triggered/running event=0xa6,umask=8  01     unc_m_powerdown_cycles.sch0_rank0 uncore memory # of cycles a given rank is in Power Down Mode event=0x47,umask=1  01     unc_m_powerdown_cycles.sch0_rank1 uncore memory # of cycles a given rank is in Power Down Mode event=0x47,umask=2  01     unc_m_powerdown_cycles.sch0_rank2 uncore memory # of cycles a given rank is in Power Down Mode event=0x47,umask=4  01     unc_m_powerdown_cycles.sch0_rank3 uncore memory # of cycles a given rank is in Power Down Mode event=0x47,umask=8  01     unc_m_powerdown_cycles.sch1_rank0 uncore memory # of cycles a given rank is in Power Down Mode event=0x47,umask=0x10  01     unc_m_powerdown_cycles.sch1_rank1 uncore memory # of cycles a given rank is in Power Down Mode event=0x47,umask=0x20  01     unc_m_powerdown_cycles.sch1_rank2 uncore memory # of cycles a given rank is in Power Down Mode event=0x47,umask=0x40  01     unc_m_powerdown_cycles.sch1_rank3 uncore memory # of cycles a given rank is in Power Down Mode event=0x47,umask=0x80  01     unc_m_power_channel_ppd_cycles uncore memory # of cycles a given rank is in Power Down Mode and all pages are closed event=0x88  01     unc_m_power_critical_throttle_cycles.slot0 uncore memory # of cycles Throttling at Critical level on specified DIMM and throttle level is zero event=0x89,umask=1  01     unc_m_power_critical_throttle_cycles.slot1 uncore memory # of cycles Throttling at Critical level on specified DIMM and throttle level is zero event=0x89,umask=2  01     unc_m_power_throttle_cycles.mr4blken uncore memory MR4 temp reading is throttling event=0x46,umask=8  01     unc_m_power_throttle_cycles.raplblk uncore memory RAPL is throttling event=0x46,umask=4  01     unc_m_self_refresh.enter_success uncore memory subevent0 - # of cycles all ranks were in SR subevent1 - # of times all ranks went into SR subevent2 -# of times  ps_sr_active asserted (SRE) subevent3 - # of times ps_sr_active deasserted (SRX) subevent4 - # of times PS-&>Refresh ps_sr_req asserted (SRE) subevent5 - # of times PS-&>Refresh ps_sr_req deasserted (SRX) subevent6 - # of cycles PSCtrlr FSM was in FATAL event=0x43,umask=2  01     unc_m_self_refresh.enter_success_cycles uncore memory # of cycles all ranks were in SR event=0x43,umask=1  01     unc_m_throttle_crit_cycles.slot0 uncore memory # of cycles Throttling at Critical level on specified DIMM event=0x8e,umask=1  01     unc_m_throttle_crit_cycles.slot1 uncore memory # of cycles Throttling at Critical level on specified DIMM event=0x8e,umask=2  01     unc_m_throttle_high_cycles.slot0 uncore memory # of cycles Throttling at High level on specified DIMM event=0x8d,umask=1  01     unc_m_throttle_high_cycles.slot1 uncore memory # of cycles Throttling at High level on specified DIMM event=0x8d,umask=2  01     unc_m_throttle_low_cycles.slot0 uncore memory # of cycles Throttling at Normal level on specified DIMM event=0x8b,umask=1  01     unc_m_throttle_low_cycles.slot1 uncore memory # of cycles Throttling at Normal level on specified DIMM event=0x8b,umask=2  01     unc_m_throttle_mid_cycles.slot0 uncore memory # of cycles Throttling at Mid level on specified DIMM event=0x8c,umask=1  01     unc_m_throttle_mid_cycles.slot1 uncore memory # of cycles Throttling at Mid level on specified DIMM event=0x8c,umask=2  01     l1d.replacement cache L1D data line replacements event=0x51,period=2000003,umask=1  00    This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache l1d_pend_miss.pending cache L1D miss outstanding duration in cycles event=0x48,period=2000003,umask=1  00    Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences l1d_pend_miss.pending_cycles cache Cycles with L1D load Misses outstanding event=0x48,cmask=1,period=2000003,umask=1  00     l1d_pend_miss.request_fb_full cache Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e event=0x48,period=2000003,umask=2  00     l2_demand_rqsts.wb_hit cache Not rejected writebacks that hit L2 cache event=0x27,period=200003,umask=0x50  00     l2_lines_in.all cache L2 cache lines filling L2 event=0xf1,period=100003,umask=7  00    This event counts the number of L2 cache lines brought into the L2 cache.  Lines are filled into the L2 cache when there was an L2 miss l2_lines_in.e cache L2 cache lines in E state filling L2 event=0xf1,period=100003,umask=4  00     l2_lines_in.i cache L2 cache lines in I state filling L2 event=0xf1,period=100003,umask=1  00     l2_lines_in.s cache L2 cache lines in S state filling L2 event=0xf1,period=100003,umask=2  00     l2_lines_out.demand_dirty cache Dirty L2 cache lines evicted by demand event=0xf2,period=100003,umask=6  00     l2_rqsts.all_code_rd cache L2 code requests event=0x24,period=200003,umask=0xe4  00    Counts all L2 code requests l2_rqsts.all_demand_data_rd cache Demand Data Read requests  Spec update: HSD78, HSM80 event=0x24,period=200003,umask=0xe1  00    Counts any demand and L1 HW prefetch data load requests to L2  Spec update: HSD78, HSM80 l2_rqsts.all_demand_miss cache Demand requests that miss L2 cache  Spec update: HSD78, HSM80 event=0x24,period=200003,umask=0x27  00     l2_rqsts.all_demand_references cache Demand requests to L2 cache  Spec update: HSD78, HSM80 event=0x24,period=200003,umask=0xe7  00     l2_rqsts.all_pf cache Requests from L2 hardware prefetchers event=0x24,period=200003,umask=0xf8  00    Counts all L2 HW prefetcher requests l2_rqsts.all_rfo cache RFO requests to L2 cache event=0x24,period=200003,umask=0xe2  00    Counts all L2 store RFO requests l2_rqsts.code_rd_hit cache L2 cache hits when fetching instructions, code reads event=0x24,period=200003,umask=0xc4  00    Number of instruction fetches that hit the L2 cache l2_rqsts.code_rd_miss cache L2 cache misses when fetching instructions event=0x24,period=200003,umask=0x24  00    Number of instruction fetches that missed the L2 cache l2_rqsts.demand_data_rd_hit cache Demand Data Read requests that hit L2 cache  Spec update: HSD78, HSM80 event=0x24,period=200003,umask=0xc1  00    Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache  Spec update: HSD78, HSM80 l2_rqsts.demand_data_rd_miss cache Demand Data Read miss L2, no rejects  Spec update: HSD78, HSM80 event=0x24,period=200003,umask=0x21  00    Demand data read requests that missed L2, no rejects  Spec update: HSD78, HSM80 l2_rqsts.l2_pf_hit cache L2 prefetch requests that hit L2 cache event=0x24,period=200003,umask=0xd0  00    Counts all L2 HW prefetcher requests that hit L2 l2_rqsts.l2_pf_miss cache L2 prefetch requests that miss L2 cache event=0x24,period=200003,umask=0x30  00    Counts all L2 HW prefetcher requests that missed L2 l2_rqsts.miss cache All requests that miss L2 cache  Spec update: HSD78, HSM80 event=0x24,period=200003,umask=0x3f  00    All requests that missed L2  Spec update: HSD78, HSM80 l2_rqsts.references cache All L2 requests  Spec update: HSD78, HSM80 event=0x24,period=200003,umask=0xff  00    All requests to L2 cache  Spec update: HSD78, HSM80 l2_rqsts.rfo_hit cache RFO requests that hit L2 cache event=0x24,period=200003,umask=0xc2  00    Counts the number of store RFO requests that hit the L2 cache l2_rqsts.rfo_miss cache RFO requests that miss L2 cache event=0x24,period=200003,umask=0x22  00    Counts the number of store RFO requests that miss the L2 cache l2_trans.all_pf cache L2 or L3 HW prefetches that access L2 cache event=0xf0,period=200003,umask=8  00    Any MLC or L3 HW prefetch accessing L2, including rejects l2_trans.all_requests cache Transactions accessing L2 pipe event=0xf0,period=200003,umask=0x80  00     l2_trans.code_rd cache L2 cache accesses when fetching instructions event=0xf0,period=200003,umask=4  00     l2_trans.demand_data_rd cache Demand Data Read requests that access L2 cache event=0xf0,period=200003,umask=1  00    Demand data read requests that access L2 cache l2_trans.l1d_wb cache L1D writebacks that access L2 cache event=0xf0,period=200003,umask=0x10  00     l2_trans.l2_fill cache L2 fill requests that access L2 cache event=0xf0,period=200003,umask=0x20  00     l2_trans.l2_wb cache L2 writebacks that access L2 cache event=0xf0,period=200003,umask=0x40  00     l2_trans.rfo cache RFO requests that access L2 cache event=0xf0,period=200003,umask=2  00     lock_cycles.cache_lock_duration cache Cycles when L1D is locked event=0x63,period=2000003,umask=2  00    Cycles in which the L1D is locked longest_lat_cache.miss cache Core-originated cacheable demand requests missed L3 event=0x2e,period=100003,umask=0x41  00    This event counts each cache miss condition for references to the last level cache longest_lat_cache.reference cache Core-originated cacheable demand requests that refer to L3 event=0x2e,period=100003,umask=0x4f  00    This event counts requests originating from the core that reference a cache line in the last level cache mem_load_uops_l3_hit_retired.xsnp_hit cache Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache  Supports address when precise.  Spec update: HSD29, HSD25, HSM26, HSM30 (Precise event) event=0xd2,period=20011,umask=2  00     mem_load_uops_l3_hit_retired.xsnp_hitm cache Retired load uops which data sources were HitM responses from shared L3  Supports address when precise.  Spec update: HSD29, HSD25, HSM26, HSM30 (Precise event) event=0xd2,period=20011,umask=4  00     mem_load_uops_l3_hit_retired.xsnp_miss cache Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache  Supports address when precise.  Spec update: HSD29, HSD25, HSM26, HSM30 (Precise event) event=0xd2,period=20011,umask=1  00     mem_load_uops_l3_hit_retired.xsnp_none cache Retired load uops which data sources were hits in L3 without snoops required  Supports address when precise.  Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event) event=0xd2,period=100003,umask=8  00     mem_load_uops_l3_miss_retired.local_dram cache Data from local DRAM either Snoop not needed or Snoop Miss (RspI)  Supports address when precise.  Spec update: HSD74, HSD29, HSD25, HSM30 (Precise event) event=0xd3,period=100003,umask=1  00    This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches  Supports address when precise.  Spec update: HSD74, HSD29, HSD25, HSM30 (Precise event) mem_load_uops_retired.hit_lfb cache Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready  Supports address when precise.  Spec update: HSM30 (Precise event) event=0xd1,period=100003,umask=0x40  00     mem_load_uops_retired.l1_hit cache Retired load uops with L1 cache hits as data sources  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event) event=0xd1,period=2000003,umask=1  00     mem_load_uops_retired.l1_miss cache Retired load uops misses in L1 cache as data sources  Supports address when precise.  Spec update: HSM30 (Precise event) event=0xd1,period=100003,umask=8  00    Retired load uops missed L1 cache as data sources  Supports address when precise.  Spec update: HSM30 (Precise event) mem_load_uops_retired.l2_hit cache Retired load uops with L2 cache hits as data sources  Supports address when precise.  Spec update: HSD76, HSD29, HSM30 (Precise event) event=0xd1,period=100003,umask=2  00     mem_load_uops_retired.l2_miss cache Miss in mid-level (L2) cache. Excludes Unknown data-source  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event) event=0xd1,period=50021,umask=0x10  00    Retired load uops missed L2. Unknown data source excluded  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event) mem_load_uops_retired.l3_hit cache Retired load uops which data sources were data hits in L3 without snoops required  Supports address when precise.  Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event) event=0xd1,period=50021,umask=4  00    Retired load uops with L3 cache hits as data sources  Supports address when precise.  Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event) mem_load_uops_retired.l3_miss cache Miss in last-level (L3) cache. Excludes Unknown data-source  Supports address when precise.  Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event) event=0xd1,period=100003,umask=0x20  00    Retired load uops missed L3. Excludes unknown data source   Supports address when precise.  Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event) mem_uops_retired.all_loads cache Retired load uops  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event) event=0xd0,period=2000003,umask=0x81  00    Counts all retired load uops. This event accounts for SW prefetch uops of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event) mem_uops_retired.all_stores cache Retired store uops  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event) event=0xd0,period=2000003,umask=0x82  00    Counts all retired store uops  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event) mem_uops_retired.lock_loads cache Retired load uops with locked access  Supports address when precise.  Spec update: HSD76, HSD29, HSM30 (Precise event) event=0xd0,period=100003,umask=0x21  00     mem_uops_retired.split_loads cache Retired load uops that split across a cacheline boundary  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event) event=0xd0,period=100003,umask=0x41  00     mem_uops_retired.split_stores cache Retired store uops that split across a cacheline boundary  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event) event=0xd0,period=100003,umask=0x42  00     mem_uops_retired.stlb_miss_loads cache Retired load uops that miss the STLB  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event) event=0xd0,period=100003,umask=0x11  00     mem_uops_retired.stlb_miss_stores cache Retired store uops that miss the STLB  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event) event=0xd0,period=100003,umask=0x12  00     offcore_requests.all_data_rd cache Demand and prefetch data reads event=0xb0,period=100003,umask=8  00    Data read requests sent to uncore (demand and prefetch) offcore_requests.demand_code_rd cache Cacheable and noncacheable code read requests event=0xb0,period=100003,umask=2  00    Demand code read requests sent to uncore offcore_requests.demand_data_rd cache Demand Data Read requests sent to uncore  Spec update: HSD78, HSM80 event=0xb0,period=100003,umask=1  00    Demand data read requests sent to uncore  Spec update: HSD78, HSM80 offcore_requests.demand_rfo cache Demand RFO requests including regular RFOs, locks, ItoM event=0xb0,period=100003,umask=4  00    Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM offcore_requests_buffer.sq_full cache Offcore requests buffer cannot take more entries for this thread core event=0xb2,period=2000003,umask=1  00     offcore_requests_outstanding.all_data_rd cache Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore  Spec update: HSD62, HSD61, HSM63 event=0x60,period=2000003,umask=8  00    Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles  Spec update: HSD62, HSD61, HSM63 offcore_requests_outstanding.cycles_with_data_rd cache Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore  Spec update: HSD62, HSD61, HSM63 event=0x60,cmask=1,period=2000003,umask=8  00     offcore_requests_outstanding.cycles_with_demand_data_rd cache Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore  Spec update: HSD78, HSD62, HSD61, HSM63, HSM80 event=0x60,cmask=1,period=2000003,umask=1  00     offcore_requests_outstanding.cycles_with_demand_rfo cache Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle  Spec update: HSD62, HSD61, HSM63 event=0x60,cmask=1,period=2000003,umask=4  00     offcore_requests_outstanding.demand_code_rd cache Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle  Spec update: HSD62, HSD61, HSM63 event=0x60,period=2000003,umask=2  00    Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles  Spec update: HSD62, HSD61, HSM63 offcore_requests_outstanding.demand_data_rd cache Offcore outstanding Demand Data Read transactions in uncore queue  Spec update: HSD78, HSD62, HSD61, HSM63, HSM80 event=0x60,period=2000003,umask=1  00    Offcore outstanding demand data read transactions in SQ to uncore. Set Cmask=1 to count cycles  Spec update: HSD78, HSD62, HSD61, HSM63, HSM80 offcore_requests_outstanding.demand_data_rd_ge_6 cache Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue  Spec update: HSD78, HSD62, HSD61, HSM63, HSM80 event=0x60,cmask=6,period=2000003,umask=1  00     offcore_requests_outstanding.demand_rfo cache Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore  Spec update: HSD62, HSD61, HSM63 event=0x60,period=2000003,umask=4  00    Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles  Spec update: HSD62, HSD61, HSM63 offcore_response.all_code_rd.l3_hit.hit_other_core_no_fwd cache Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0244  00     offcore_response.all_data_rd.l3_hit.hitm_other_core cache Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0091  00     offcore_response.all_data_rd.l3_hit.hit_other_core_no_fwd cache Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0091  00     offcore_response.all_reads.l3_hit.hitm_other_core cache hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C07F7  00     offcore_response.all_reads.l3_hit.hit_other_core_no_fwd cache hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C07F7  00     offcore_response.all_requests.l3_hit.any_response cache Counts all requests hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C8FFF  00     offcore_response.all_rfo.l3_hit.hitm_other_core cache Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0122  00     offcore_response.all_rfo.l3_hit.hit_other_core_no_fwd cache Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0122  00     offcore_response.demand_code_rd.l3_hit.hitm_other_core cache Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0004  00     offcore_response.demand_code_rd.l3_hit.hit_other_core_no_fwd cache Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0004  00     offcore_response.demand_data_rd.l3_hit.hitm_other_core cache Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0001  00     offcore_response.demand_data_rd.l3_hit.hit_other_core_no_fwd cache Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0001  00     offcore_response.demand_rfo.l3_hit.hitm_other_core cache Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0002  00     offcore_response.demand_rfo.l3_hit.hit_other_core_no_fwd cache Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0002  00     offcore_response.pf_l2_code_rd.l3_hit.any_response cache Counts all prefetch (that bring data to LLC only) code reads hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0040  00     offcore_response.pf_l2_data_rd.l3_hit.any_response cache Counts prefetch (that bring data to L2) data reads hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0010  00     offcore_response.pf_l2_rfo.l3_hit.any_response cache Counts all prefetch (that bring data to L2) RFOs hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0020  00     offcore_response.pf_l3_code_rd.l3_hit.any_response cache Counts prefetch (that bring data to LLC only) code reads hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0200  00     offcore_response.pf_l3_data_rd.l3_hit.any_response cache Counts all prefetch (that bring data to LLC only) data reads hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0080  00     offcore_response.pf_l3_rfo.l3_hit.any_response cache Counts all prefetch (that bring data to LLC only) RFOs hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0100  00     sq_misc.split_lock cache Split locks in SQ event=0xf4,period=100003,umask=0x10  00     avx_insts.all floating point Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores.  May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX event=0xc6,period=2000003,umask=7  00    Note that a whole rep string only counts AVX_INST.ALL once fp_assist.any floating point Cycles with any input/output SSE or FP assist event=0xca,cmask=1,period=100003,umask=0x1e  00    Cycles with any input/output SSE* or FP assists fp_assist.simd_input floating point Number of SIMD FP assists due to input values event=0xca,period=100003,umask=0x10  00     fp_assist.simd_output floating point Number of SIMD FP assists due to Output values event=0xca,period=100003,umask=8  00    Number of SIMD FP assists due to output values fp_assist.x87_input floating point Number of X87 assists due to input value event=0xca,period=100003,umask=4  00    Number of X87 FP assists due to input values fp_assist.x87_output floating point Number of X87 assists due to output value event=0xca,period=100003,umask=2  00    Number of X87 FP assists due to output values move_elimination.simd_eliminated floating point Number of SIMD Move Elimination candidate uops that were eliminated event=0x58,period=1000003,umask=2  00    Number of SIMD move elimination candidate uops that were eliminated move_elimination.simd_not_eliminated floating point Number of SIMD Move Elimination candidate uops that were not eliminated event=0x58,period=1000003,umask=8  00    Number of SIMD move elimination candidate uops that were not eliminated other_assists.avx_to_sse floating point Number of transitions from AVX-256 to legacy SSE when penalty applicable  Spec update: HSD56, HSM57 event=0xc1,period=100003,umask=8  00     other_assists.sse_to_avx floating point Number of transitions from SSE to AVX-256 when penalty applicable  Spec update: HSD56, HSM57 event=0xc1,period=100003,umask=0x10  00     baclears.any frontend Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end event=0xe6,period=100003,umask=0x1f  00    Number of front end re-steers due to BPU misprediction dsb2mite_switches.penalty_cycles frontend Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles event=0xab,period=2000003,umask=2  00     icache.hit frontend Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches event=0x80,period=2000003,umask=1  00     icache.ifdata_stall frontend Cycles where a code fetch is stalled due to L1 instruction-cache miss event=0x80,period=2000003,umask=4  00     icache.ifetch_stall frontend Cycles where a code fetch is stalled due to L1 instruction-cache miss event=0x80,period=2000003,umask=4  00     icache.misses frontend Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses event=0x80,period=200003,umask=2  00    This event counts Instruction Cache (ICACHE) misses idq.all_dsb_cycles_4_uops frontend Cycles Decode Stream Buffer (DSB) is delivering 4 Uops event=0x79,cmask=4,period=2000003,umask=0x18  00    Counts cycles DSB is delivered four uops. Set Cmask = 4 idq.all_dsb_cycles_any_uops frontend Cycles Decode Stream Buffer (DSB) is delivering any Uop event=0x79,cmask=1,period=2000003,umask=0x18  00    Counts cycles DSB is delivered at least one uops. Set Cmask = 1 idq.all_mite_cycles_4_uops frontend Cycles MITE is delivering 4 Uops event=0x79,cmask=4,period=2000003,umask=0x24  00    Counts cycles MITE is delivered four uops. Set Cmask = 4 idq.all_mite_cycles_any_uops frontend Cycles MITE is delivering any Uop event=0x79,cmask=1,period=2000003,umask=0x24  00    Counts cycles MITE is delivered at least one uop. Set Cmask = 1 idq.dsb_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path event=0x79,cmask=1,period=2000003,umask=8  00     idq.dsb_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path event=0x79,period=2000003,umask=8  00    Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles idq.empty frontend Instruction Decode Queue (IDQ) empty cycles  Spec update: HSD135 event=0x79,period=2000003,umask=2  00    Counts cycles the IDQ is empty  Spec update: HSD135 idq.mite_all_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,period=2000003,umask=0x3c  00    Number of uops delivered to IDQ from any path idq.mite_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,cmask=1,period=2000003,umask=4  00     idq.mite_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,period=2000003,umask=4  00    Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles idq.ms_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,period=2000003,umask=0x30  00    This event counts cycles during which the microcode sequencer assisted the Front-end in delivering uops.  Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder.  Using other instructions, if possible, will usually improve performance idq.ms_dsb_cycles frontend Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,period=2000003,umask=0x10  00     idq.ms_dsb_occur frontend Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,edge=1,period=2000003,umask=0x10  00     idq.ms_dsb_uops frontend Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x10  00    Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery idq.ms_mite_uops frontend Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x20  00    Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles idq.ms_uops frontend Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x30  00    This event counts uops delivered by the Front-end with the assistance of the microcode sequencer.  Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder.  Using other instructions, if possible, will usually improve performance idq_uops_not_delivered.core frontend Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled  Spec update: HSD135 event=0x9c,period=2000003,umask=1  00    This event count the number of undelivered (unallocated) uops from the Front-end to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. The Front-end can allocate up to 4 uops per cycle so this event can increment 0-4 times per cycle depending on the number of unallocated uops. This event is counted on a per-core basis  Spec update: HSD135 idq_uops_not_delivered.cycles_0_uops_deliv.core frontend Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled  Spec update: HSD135 event=0x9c,cmask=4,period=2000003,umask=1  00    This event counts the number cycles during which the Front-end allocated exactly zero uops to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled.  This event is counted on a per-core basis  Spec update: HSD135 idq_uops_not_delivered.cycles_fe_was_ok frontend Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE  Spec update: HSD135 event=0x9c,cmask=1,inv=1,period=2000003,umask=1  00     idq_uops_not_delivered.cycles_le_1_uop_deliv.core frontend Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled  Spec update: HSD135 event=0x9c,cmask=3,period=2000003,umask=1  00     idq_uops_not_delivered.cycles_le_2_uop_deliv.core frontend Cycles with less than 2 uops delivered by the front end  Spec update: HSD135 event=0x9c,cmask=2,period=2000003,umask=1  00     idq_uops_not_delivered.cycles_le_3_uop_deliv.core frontend Cycles with less than 3 uops delivered by the front end  Spec update: HSD135 event=0x9c,cmask=1,period=2000003,umask=1  00     hle_retired.aborted memory Number of times an HLE execution aborted due to any reasons (multiple categories may count as one) (Precise event) event=0xc8,period=2000003,umask=4  00     hle_retired.aborted_misc1 memory Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts) event=0xc8,period=2000003,umask=8  00     hle_retired.aborted_misc2 memory Number of times an HLE execution aborted due to uncommon conditions event=0xc8,period=2000003,umask=0x10  00     hle_retired.aborted_misc3 memory Number of times an HLE execution aborted due to HLE-unfriendly instructions event=0xc8,period=2000003,umask=0x20  00     hle_retired.aborted_misc4 memory Number of times an HLE execution aborted due to incompatible memory type  Spec update: HSD65 event=0xc8,period=2000003,umask=0x40  00     hle_retired.aborted_misc5 memory Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts) event=0xc8,period=2000003,umask=0x80  00     hle_retired.commit memory Number of times an HLE execution successfully committed event=0xc8,period=2000003,umask=2  00     hle_retired.start memory Number of times an HLE execution started event=0xc8,period=2000003,umask=1  00     machine_clears.memory_ordering memory Counts the number of machine clears due to memory order conflicts event=0xc3,period=100003,umask=2  00    This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline.  Machine clears can have a significant performance impact if they are happening frequently mem_trans_retired.load_latency_gt_128 memory Randomly selected loads with latency value being above 128  Supports address when precise.  Spec update: HSD76, HSD25, HSM26 (Must be precise) event=0xcd,period=1009,umask=1,ldlat=0x80  00     mem_trans_retired.load_latency_gt_16 memory Randomly selected loads with latency value being above 16  Supports address when precise.  Spec update: HSD76, HSD25, HSM26 (Must be precise) event=0xcd,period=20011,umask=1,ldlat=0x10  00     mem_trans_retired.load_latency_gt_256 memory Randomly selected loads with latency value being above 256  Supports address when precise.  Spec update: HSD76, HSD25, HSM26 (Must be precise) event=0xcd,period=503,umask=1,ldlat=0x100  00     mem_trans_retired.load_latency_gt_32 memory Randomly selected loads with latency value being above 32  Supports address when precise.  Spec update: HSD76, HSD25, HSM26 (Must be precise) event=0xcd,period=100003,umask=1,ldlat=0x20  00     mem_trans_retired.load_latency_gt_4 memory Randomly selected loads with latency value being above 4  Supports address when precise.  Spec update: HSD76, HSD25, HSM26 (Must be precise) event=0xcd,period=100003,umask=1,ldlat=0x4  00     mem_trans_retired.load_latency_gt_512 memory Randomly selected loads with latency value being above 512  Supports address when precise.  Spec update: HSD76, HSD25, HSM26 (Must be precise) event=0xcd,period=101,umask=1,ldlat=0x200  00     mem_trans_retired.load_latency_gt_64 memory Randomly selected loads with latency value being above 64  Supports address when precise.  Spec update: HSD76, HSD25, HSM26 (Must be precise) event=0xcd,period=2003,umask=1,ldlat=0x40  00     mem_trans_retired.load_latency_gt_8 memory Randomly selected loads with latency value being above 8  Supports address when precise.  Spec update: HSD76, HSD25, HSM26 (Must be precise) event=0xcd,period=50021,umask=1,ldlat=0x8  00     misalign_mem_ref.loads memory Speculative cache line split load uops dispatched to L1 cache event=5,period=2000003,umask=1  00    Speculative cache-line split load uops dispatched to L1D misalign_mem_ref.stores memory Speculative cache line split STA uops dispatched to L1 cache event=5,period=2000003,umask=2  00    Speculative cache-line split store-address uops dispatched to L1D offcore_response.all_code_rd.l3_miss.any_response memory Counts all demand & prefetch code reads miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00244  00     offcore_response.all_code_rd.l3_miss.local_dram memory Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x100400244  00     offcore_response.all_data_rd.l3_miss.any_response memory Counts all demand & prefetch data reads miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00091  00     offcore_response.all_data_rd.l3_miss.local_dram memory Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x100400091  00     offcore_response.all_reads.l3_miss.any_response memory miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC007F7  00     offcore_response.all_reads.l3_miss.local_dram memory miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x1004007F7  00     offcore_response.all_requests.l3_miss.any_response memory Counts all requests miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC08FFF  00     offcore_response.all_rfo.l3_miss.any_response memory Counts all demand & prefetch RFOs miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00122  00     offcore_response.all_rfo.l3_miss.local_dram memory Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x100400122  00     offcore_response.demand_code_rd.l3_miss.any_response memory Counts all demand code reads miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00004  00     offcore_response.demand_code_rd.l3_miss.local_dram memory Counts all demand code reads miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x100400004  00     offcore_response.demand_data_rd.l3_miss.any_response memory Counts demand data reads miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00001  00     offcore_response.demand_data_rd.l3_miss.local_dram memory Counts demand data reads miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x100400001  00     offcore_response.demand_rfo.l3_miss.any_response memory Counts all demand data writes (RFOs) miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00002  00     offcore_response.demand_rfo.l3_miss.local_dram memory Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x100400002  00     offcore_response.pf_l2_code_rd.l3_miss.any_response memory Counts all prefetch (that bring data to LLC only) code reads miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00040  00     offcore_response.pf_l2_data_rd.l3_miss.any_response memory Counts prefetch (that bring data to L2) data reads miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00010  00     offcore_response.pf_l2_rfo.l3_miss.any_response memory Counts all prefetch (that bring data to L2) RFOs miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00020  00     offcore_response.pf_l3_code_rd.l3_miss.any_response memory Counts prefetch (that bring data to LLC only) code reads miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00200  00     offcore_response.pf_l3_data_rd.l3_miss.any_response memory Counts all prefetch (that bring data to LLC only) data reads miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00080  00     offcore_response.pf_l3_rfo.l3_miss.any_response memory Counts all prefetch (that bring data to LLC only) RFOs miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00100  00     rtm_retired.aborted memory Number of times an RTM execution aborted due to any reasons (multiple categories may count as one) (Precise event) event=0xc9,period=2000003,umask=4  00     rtm_retired.aborted_misc1 memory Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts) event=0xc9,period=2000003,umask=8  00     rtm_retired.aborted_misc2 memory Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts) event=0xc9,period=2000003,umask=0x10  00     rtm_retired.aborted_misc3 memory Number of times an RTM execution aborted due to HLE-unfriendly instructions event=0xc9,period=2000003,umask=0x20  00     rtm_retired.aborted_misc4 memory Number of times an RTM execution aborted due to incompatible memory type  Spec update: HSD65 event=0xc9,period=2000003,umask=0x40  00     rtm_retired.aborted_misc5 memory Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt) event=0xc9,period=2000003,umask=0x80  00     rtm_retired.commit memory Number of times an RTM execution successfully committed event=0xc9,period=2000003,umask=2  00     rtm_retired.start memory Number of times an RTM execution started event=0xc9,period=2000003,umask=1  00     tx_exec.misc2 memory Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region event=0x5d,period=2000003,umask=2  00     tx_exec.misc3 memory Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded event=0x5d,period=2000003,umask=4  00     tx_exec.misc4 memory Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region event=0x5d,period=2000003,umask=8  00     tx_mem.abort_capacity_write memory Number of times a transactional abort was signaled due to a data capacity limitation for transactional writes event=0x54,period=2000003,umask=2  00     tx_mem.abort_conflict memory Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address event=0x54,period=2000003,umask=1  00     tx_mem.abort_hle_elision_buffer_mismatch memory Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer event=0x54,period=2000003,umask=0x10  00     tx_mem.abort_hle_elision_buffer_not_empty memory Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero event=0x54,period=2000003,umask=8  00     tx_mem.abort_hle_elision_buffer_unsupported_alignment memory Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer event=0x54,period=2000003,umask=0x20  00     tx_mem.abort_hle_store_to_elided_lock memory Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer event=0x54,period=2000003,umask=4  00     tx_mem.hle_elision_buffer_full memory Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero event=0x54,period=2000003,umask=0x40  00     cpl_cycles.ring0 other Unhalted core cycles when the thread is in ring 0 event=0x5c,period=2000003,umask=1  00     cpl_cycles.ring0_trans other Number of intervals between processor halts while thread is in ring 0 event=0x5c,cmask=1,edge=1,period=100003,umask=1  00     cpl_cycles.ring123 other Unhalted core cycles when thread is in rings 1, 2, or 3 event=0x5c,period=2000003,umask=2  00    Unhalted core cycles when the thread is not in ring 0 lock_cycles.split_lock_uc_lock_duration other Cycles when L1 and L2 are locked due to UC or split lock event=0x63,period=2000003,umask=1  00    Cycles in which the L1D and L2 are locked, due to a UC lock or split lock arith.divider_uops pipeline Any uop executed by the Divider. (This includes all divide uops, sqrt, ...) event=0x14,period=2000003,umask=2  00     br_inst_exec.all_branches pipeline Speculative and retired  branches event=0x88,period=200003,umask=0xff  00    Counts all near executed branches (not necessarily retired) br_inst_exec.all_conditional pipeline Speculative and retired macro-conditional branches event=0x88,period=200003,umask=0xc1  00     br_inst_exec.all_direct_jmp pipeline Speculative and retired macro-unconditional branches excluding calls and indirects event=0x88,period=200003,umask=0xc2  00     br_inst_exec.all_direct_near_call pipeline Speculative and retired direct near calls event=0x88,period=200003,umask=0xd0  00     br_inst_exec.all_indirect_jump_non_call_ret pipeline Speculative and retired indirect branches excluding calls and returns event=0x88,period=200003,umask=0xc4  00     br_inst_exec.all_indirect_near_return pipeline Speculative and retired indirect return branches event=0x88,period=200003,umask=0xc8  00     br_inst_exec.nontaken_conditional pipeline Not taken macro-conditional branches event=0x88,period=200003,umask=0x41  00     br_inst_exec.taken_conditional pipeline Taken speculative and retired macro-conditional branches event=0x88,period=200003,umask=0x81  00     br_inst_exec.taken_direct_jump pipeline Taken speculative and retired macro-conditional branch instructions excluding calls and indirects event=0x88,period=200003,umask=0x82  00     br_inst_exec.taken_direct_near_call pipeline Taken speculative and retired direct near calls event=0x88,period=200003,umask=0x90  00     br_inst_exec.taken_indirect_jump_non_call_ret pipeline Taken speculative and retired indirect branches excluding calls and returns event=0x88,period=200003,umask=0x84  00     br_inst_exec.taken_indirect_near_call pipeline Taken speculative and retired indirect calls event=0x88,period=200003,umask=0xa0  00     br_inst_exec.taken_indirect_near_return pipeline Taken speculative and retired indirect branches with return mnemonic event=0x88,period=200003,umask=0x88  00     br_inst_retired.all_branches pipeline All (macro) branch instructions retired event=0xc4,period=400009  00    Branch instructions at retirement br_inst_retired.all_branches_pebs pipeline All (macro) branch instructions retired (Must be precise) event=0xc4,period=400009,umask=4  00     br_inst_retired.conditional pipeline Conditional branch instructions retired (Precise event) event=0xc4,period=400009,umask=1  00    Counts the number of conditional branch instructions retired (Precise event) br_inst_retired.far_branch pipeline Far branch instructions retired event=0xc4,period=100003,umask=0x40  00    Number of far branches retired br_inst_retired.near_call pipeline Direct and indirect near call instructions retired (Precise event) event=0xc4,period=100003,umask=2  00     br_inst_retired.near_call_r3 pipeline Direct and indirect macro near call instructions retired (captured in ring 3) (Precise event) event=0xc4,period=100003,umask=2  00     br_inst_retired.near_return pipeline Return instructions retired (Precise event) event=0xc4,period=100003,umask=8  00    Counts the number of near return instructions retired (Precise event) br_inst_retired.near_taken pipeline Taken branch instructions retired (Precise event) event=0xc4,period=400009,umask=0x20  00    Number of near taken branches retired (Precise event) br_inst_retired.not_taken pipeline Not taken branch instructions retired event=0xc4,period=400009,umask=0x10  00    Counts the number of not taken branch instructions retired br_misp_exec.all_branches pipeline Speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0xff  00    Counts all near executed branches (not necessarily retired) br_misp_exec.all_conditional pipeline Speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0xc1  00     br_misp_exec.all_indirect_jump_non_call_ret pipeline Mispredicted indirect branches excluding calls and returns event=0x89,period=200003,umask=0xc4  00     br_misp_exec.nontaken_conditional pipeline Not taken speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0x41  00     br_misp_exec.taken_conditional pipeline Taken speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0x81  00     br_misp_exec.taken_indirect_jump_non_call_ret pipeline Taken speculative and retired mispredicted indirect branches excluding calls and returns event=0x89,period=200003,umask=0x84  00     br_misp_exec.taken_return_near pipeline Taken speculative and retired mispredicted indirect branches with return mnemonic event=0x89,period=200003,umask=0x88  00     br_misp_retired.all_branches pipeline All mispredicted macro branch instructions retired event=0xc5,period=400009  00    Mispredicted branch instructions at retirement br_misp_retired.all_branches_pebs pipeline Mispredicted macro branch instructions retired (Must be precise) event=0xc5,period=400009,umask=4  00    This event counts all mispredicted branch instructions retired. This is a precise event (Must be precise) br_misp_retired.conditional pipeline Mispredicted conditional branch instructions retired (Precise event) event=0xc5,period=400009,umask=1  00     br_misp_retired.near_taken pipeline number of near branch instructions retired that were mispredicted and taken (Precise event) event=0xc5,period=400009,umask=0x20  00    Number of near branch instructions retired that were taken but mispredicted (Precise event) cpu_clk_thread_unhalted.ref_xclk pipeline Reference cycles when the thread is unhalted (counts at 100 MHz rate) event=0x3c,period=100003,umask=1  00    Increments at the frequency of XCLK (100 MHz) when not halted cpu_clk_unhalted.ref_tsc pipeline Reference cycles when the core is not in halt state event=0,period=2000003,umask=3  00    This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state cpu_clk_unhalted.ref_xclk pipeline Reference cycles when the thread is unhalted (counts at 100 MHz rate) event=0x3c,period=100003,umask=1  00    Reference cycles when the thread is unhalted. (counts at 100 MHz rate) cpu_clk_unhalted.thread pipeline Core cycles when the thread is not in halt state event=0x3c,period=2000003  00    This event counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling cpu_clk_unhalted.thread_p pipeline Thread cycles when thread is not in halt state event=0x3c,period=2000003  00    Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling cycle_activity.cycles_l1d_pending pipeline Cycles with pending L1 cache miss loads event=0xa3,cmask=8,period=2000003,umask=8  00    Cycles with pending L1 data cache miss loads. Set Cmask=8 to count cycle cycle_activity.cycles_l2_pending pipeline Cycles with pending L2 cache miss loads  Spec update: HSD78, HSM63, HSM80 event=0xa3,cmask=1,period=2000003,umask=1  00    Cycles with pending L2 miss loads. Set Cmask=2 to count cycle  Spec update: HSD78, HSM63, HSM80 cycle_activity.cycles_ldm_pending pipeline Cycles with pending memory loads event=0xa3,cmask=2,period=2000003,umask=2  00    Cycles with pending memory loads. Set Cmask=2 to count cycle cycle_activity.cycles_no_execute pipeline This event increments by 1 for every cycle where there was no execute for this thread event=0xa3,cmask=4,period=2000003,umask=4  00    This event counts cycles during which no instructions were executed in the execution stage of the pipeline cycle_activity.stalls_l1d_pending pipeline Execution stalls due to L1 data cache misses event=0xa3,cmask=12,period=2000003,umask=0xc  00    Execution stalls due to L1 data cache miss loads. Set Cmask=0CH cycle_activity.stalls_l2_pending pipeline Execution stalls due to L2 cache misses  Spec update: HSM63, HSM80 event=0xa3,cmask=5,period=2000003,umask=5  00    Number of loads missed L2  Spec update: HSM63, HSM80 cycle_activity.stalls_ldm_pending pipeline Execution stalls due to memory subsystem event=0xa3,cmask=6,period=2000003,umask=6  00    This event counts cycles during which no instructions were executed in the execution stage of the pipeline and there were memory instructions pending (waiting for data) ild_stall.iq_full pipeline Stall cycles because IQ is full event=0x87,period=2000003,umask=4  00    Stall cycles due to IQ is full ild_stall.lcp pipeline Stalls caused by changing prefix length of the instruction event=0x87,period=2000003,umask=1  00    This event counts cycles where the decoder is stalled on an instruction with a length changing prefix (LCP) inst_retired.any pipeline Instructions retired from execution  Spec update: HSD140, HSD143 event=0xc0,period=2000003  00    This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. INST_RETIRED.ANY is counted by a designated fixed counter, leaving the programmable counters available for other events. Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions  Spec update: HSD140, HSD143 inst_retired.any_p pipeline Number of instructions retired. General Counter   - architectural event  Spec update: HSD11, HSD140 event=0xc0,period=2000003  00    Number of instructions at retirement  Spec update: HSD11, HSD140 inst_retired.prec_dist pipeline Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution  Spec update: HSD140 (Must be precise) event=0xc0,period=2000003,umask=1  00     inst_retired.x87 pipeline FP operations retired. X87 FP operations that have no exceptions: Counts also flows that have several X87 or flows that use X87 uops in the exception handling event=0xc0,period=2000003,umask=2  00    This is a non-precise version (that is, does not use PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling int_misc.recovery_cycles pipeline Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke) event=0xd,cmask=1,period=2000003,umask=3  00    This event counts the number of cycles spent waiting for a recovery after an event such as a processor nuke, JEClear, assist, hle/rtm abort etc ld_blocks.store_forward pipeline loads blocked by overlapping with store buffer that cannot be forwarded event=3,period=100003,umask=2  00    This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load.  The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. The penalty for blocked store forwarding is that the load must wait for the store to write its value to the cache before it can be issued ld_blocks_partial.address_alias pipeline False dependencies in MOB due to partial compare on address event=7,period=100003,umask=1  00    Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K.  This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline which can have a performance impact load_hit_pre.hw_pf pipeline Not software-prefetch load dispatches that hit FB allocated for hardware prefetch event=0x4c,period=100003,umask=2  00    Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch load_hit_pre.sw_pf pipeline Not software-prefetch load dispatches that hit FB allocated for software prefetch event=0x4c,period=100003,umask=1  00    Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch lsd.uops pipeline Number of Uops delivered by the LSD event=0xa8,period=2000003,umask=1  00    Number of uops delivered by the LSD machine_clears.cycles pipeline Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes event=0xc3,period=2000003,umask=1  00     machine_clears.maskmov pipeline This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0 event=0xc3,period=100003,umask=0x20  00     machine_clears.smc pipeline Self-modifying code (SMC) detected event=0xc3,period=100003,umask=4  00    This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear.  Machine clears can have a significant performance impact if they are happening frequently move_elimination.int_eliminated pipeline Number of integer Move Elimination candidate uops that were eliminated event=0x58,period=1000003,umask=1  00    Number of integer move elimination candidate uops that were eliminated move_elimination.int_not_eliminated pipeline Number of integer Move Elimination candidate uops that were not eliminated event=0x58,period=1000003,umask=4  00    Number of integer move elimination candidate uops that were not eliminated other_assists.any_wb_assist pipeline Number of times any microcode assist is invoked by HW upon uop writeback event=0xc1,period=100003,umask=0x40  00    Number of microcode assists invoked by HW upon uop writeback resource_stalls.any pipeline Resource-related stall cycles  Spec update: HSD135 event=0xa2,period=2000003,umask=1  00    Cycles allocation is stalled due to resource related reason  Spec update: HSD135 resource_stalls.rob pipeline Cycles stalled due to re-order buffer full event=0xa2,period=2000003,umask=0x10  00     resource_stalls.rs pipeline Cycles stalled due to no eligible RS entry available event=0xa2,period=2000003,umask=4  00     resource_stalls.sb pipeline Cycles stalled due to no store buffers available. (not including draining form sync) event=0xa2,period=2000003,umask=8  00    This event counts cycles during which no instructions were allocated because no Store Buffers (SB) were available rob_misc_events.lbr_inserts pipeline Count cases of saving new LBR event=0xcc,period=2000003,umask=0x20  00    Count cases of saving new LBR records by hardware rs_events.empty_cycles pipeline Cycles when Reservation Station (RS) is empty for the thread event=0x5e,period=2000003,umask=1  00    This event counts cycles when the Reservation Station ( RS ) is empty for the thread. The RS is a structure that buffers allocated micro-ops from the Front-end. If there are many cycles when the RS is empty, it may represent an underflow of instructions delivered from the Front-end uops_dispatched_port.port_0 pipeline Cycles per thread when uops are executed in port 0 event=0xa1,period=2000003,umask=1  00     uops_dispatched_port.port_1 pipeline Cycles per thread when uops are executed in port 1 event=0xa1,period=2000003,umask=2  00     uops_dispatched_port.port_2 pipeline Cycles per thread when uops are executed in port 2 event=0xa1,period=2000003,umask=4  00     uops_dispatched_port.port_3 pipeline Cycles per thread when uops are executed in port 3 event=0xa1,period=2000003,umask=8  00     uops_dispatched_port.port_4 pipeline Cycles per thread when uops are executed in port 4 event=0xa1,period=2000003,umask=0x10  00     uops_dispatched_port.port_5 pipeline Cycles per thread when uops are executed in port 5 event=0xa1,period=2000003,umask=0x20  00     uops_dispatched_port.port_6 pipeline Cycles per thread when uops are executed in port 6 event=0xa1,period=2000003,umask=0x40  00     uops_dispatched_port.port_7 pipeline Cycles per thread when uops are executed in port 7 event=0xa1,period=2000003,umask=0x80  00     uops_executed.core pipeline Number of uops executed on the core  Spec update: HSD30, HSM31 event=0xb1,period=2000003,umask=2  00    Counts total number of uops to be executed per-core each cycle  Spec update: HSD30, HSM31 uops_executed.core_cycles_ge_1 pipeline Cycles at least 1 micro-op is executed from any thread on physical core  Spec update: HSD30, HSM31 event=0xb1,cmask=1,period=2000003,umask=2  00     uops_executed.core_cycles_ge_2 pipeline Cycles at least 2 micro-op is executed from any thread on physical core  Spec update: HSD30, HSM31 event=0xb1,cmask=2,period=2000003,umask=2  00     uops_executed.core_cycles_ge_3 pipeline Cycles at least 3 micro-op is executed from any thread on physical core  Spec update: HSD30, HSM31 event=0xb1,cmask=3,period=2000003,umask=2  00     uops_executed.core_cycles_ge_4 pipeline Cycles at least 4 micro-op is executed from any thread on physical core  Spec update: HSD30, HSM31 event=0xb1,cmask=4,period=2000003,umask=2  00     uops_executed.core_cycles_none pipeline Cycles with no micro-ops executed from any thread on physical core  Spec update: HSD30, HSM31 event=0xb1,inv=1,period=2000003,umask=2  00     uops_executed.cycles_ge_1_uop_exec pipeline Cycles where at least 1 uop was executed per-thread  Spec update: HSD144, HSD30, HSM31 event=0xb1,cmask=1,period=2000003,umask=1  00    This events counts the cycles where at least one uop was executed. It is counted per thread  Spec update: HSD144, HSD30, HSM31 uops_executed.cycles_ge_2_uops_exec pipeline Cycles where at least 2 uops were executed per-thread  Spec update: HSD144, HSD30, HSM31 event=0xb1,cmask=2,period=2000003,umask=1  00    This events counts the cycles where at least two uop were executed. It is counted per thread  Spec update: HSD144, HSD30, HSM31 uops_executed.cycles_ge_3_uops_exec pipeline Cycles where at least 3 uops were executed per-thread  Spec update: HSD144, HSD30, HSM31 event=0xb1,cmask=3,period=2000003,umask=1  00    This events counts the cycles where at least three uop were executed. It is counted per thread  Spec update: HSD144, HSD30, HSM31 uops_executed.cycles_ge_4_uops_exec pipeline Cycles where at least 4 uops were executed per-thread  Spec update: HSD144, HSD30, HSM31 event=0xb1,cmask=4,period=2000003,umask=1  00     uops_executed.stall_cycles pipeline Counts number of cycles no uops were dispatched to be executed on this thread  Spec update: HSD144, HSD30, HSM31 event=0xb1,cmask=1,inv=1,period=2000003,umask=1  00     uops_executed_port.port_0 pipeline Cycles per thread when uops are executed in port 0 event=0xa1,period=2000003,umask=1  00    Cycles which a uop is dispatched on port 0 in this thread uops_executed_port.port_1 pipeline Cycles per thread when uops are executed in port 1 event=0xa1,period=2000003,umask=2  00    Cycles which a uop is dispatched on port 1 in this thread uops_executed_port.port_2 pipeline Cycles per thread when uops are executed in port 2 event=0xa1,period=2000003,umask=4  00    Cycles which a uop is dispatched on port 2 in this thread uops_executed_port.port_3 pipeline Cycles per thread when uops are executed in port 3 event=0xa1,period=2000003,umask=8  00    Cycles which a uop is dispatched on port 3 in this thread uops_executed_port.port_4 pipeline Cycles per thread when uops are executed in port 4 event=0xa1,period=2000003,umask=0x10  00    Cycles which a uop is dispatched on port 4 in this thread uops_executed_port.port_5 pipeline Cycles per thread when uops are executed in port 5 event=0xa1,period=2000003,umask=0x20  00    Cycles which a uop is dispatched on port 5 in this thread uops_executed_port.port_6 pipeline Cycles per thread when uops are executed in port 6 event=0xa1,period=2000003,umask=0x40  00    Cycles which a uop is dispatched on port 6 in this thread uops_executed_port.port_7 pipeline Cycles per thread when uops are executed in port 7 event=0xa1,period=2000003,umask=0x80  00    Cycles which a uop is dispatched on port 7 in this thread uops_issued.any pipeline Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS) event=0xe,period=2000003,umask=1  00    This event counts the number of uops issued by the Front-end of the pipeline to the Back-end. This event is counted at the allocation stage and will count both retired and non-retired uops uops_issued.core_stall_cycles pipeline Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads event=0xe,any=1,cmask=1,inv=1,period=2000003,umask=1  00     uops_issued.flags_merge pipeline Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch event=0xe,period=2000003,umask=0x10  00    Number of flags-merge uops allocated. Such uops add delay uops_issued.single_mul pipeline Number of Multiply packed/scalar single precision uops allocated event=0xe,period=2000003,umask=0x40  00    Number of multiply packed/scalar single precision uops allocated uops_issued.slow_lea pipeline Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not event=0xe,period=2000003,umask=0x20  00    Number of slow LEA or similar uops allocated. Such uop has 3 sources (for example, 2 sources + immediate) regardless of whether it is a result of LEA instruction or not uops_issued.stall_cycles pipeline Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread event=0xe,cmask=1,inv=1,period=2000003,umask=1  00     uops_retired.all pipeline Actually retired uops (Precise event) event=0xc2,period=2000003,umask=1  00    Counts the number of micro-ops retired. Use Cmask=1 and invert to count active cycles or stalled cycles (Precise event) uops_retired.core_stall_cycles pipeline Cycles without actually retired uops event=0xc2,any=1,cmask=1,inv=1,period=2000003,umask=1  00     uops_retired.retire_slots pipeline Retirement slots used (Precise event) event=0xc2,period=2000003,umask=2  00    This event counts the number of retirement slots used each cycle.  There are potentially 4 slots that can be used each cycle - meaning, 4 uops or 4 instructions could retire each cycle (Precise event) uops_retired.stall_cycles pipeline Cycles without actually retired uops event=0xc2,cmask=1,inv=1,period=2000003,umask=1  00     uops_retired.total_cycles pipeline Cycles with less than 10 actually retired uops event=0xc2,cmask=16,inv=1,period=2000003,umask=1  00     unc_cbo_cache_lookup.extsnp_es uncore cache L3 Lookup external snoop request that access cache and found line in E or S-state event=0x34,umask=0x46  01     unc_cbo_cache_lookup.extsnp_i uncore cache L3 Lookup external snoop request that access cache and found line in I-state event=0x34,umask=0x48  01     unc_cbo_cache_lookup.extsnp_m uncore cache L3 Lookup external snoop request that access cache and found line in M-state event=0x34,umask=0x41  01     unc_cbo_cache_lookup.extsnp_mesi uncore cache L3 Lookup external snoop request that access cache and found line in MESI-state event=0x34,umask=0x4f  01     unc_cbo_cache_lookup.write_i uncore cache L3 Lookup write request that access cache and found line in I-state event=0x34,umask=0x28  01     unc_cbo_xsnp_response.hitm_eviction uncore cache A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core event=0x22,umask=0x88  01     unc_cbo_xsnp_response.hitm_external uncore cache An external snoop hits a modified line in some processor core event=0x22,umask=0x28  01     unc_cbo_xsnp_response.hit_eviction uncore cache A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core event=0x22,umask=0x84  01     unc_cbo_xsnp_response.hit_external uncore cache An external snoop hits a non-modified line in some processor core event=0x22,umask=0x24  01     unc_cbo_xsnp_response.miss_external uncore cache An external snoop misses in some processor core event=0x22,umask=0x21  01     unc_arb_coh_trk_occupancy.all uncore interconnect Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory) event=0x83,umask=1  01     unc_arb_trk_occupancy.cycles_with_any_request uncore interconnect Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC event=0x80,cmask=1,umask=1  01     dtlb_load_misses.miss_causes_a_walk virtual memory Load misses in all DTLB levels that cause page walks event=8,period=100003,umask=1  00    Misses in all TLB levels that cause a page walk of any page size dtlb_load_misses.pde_cache_miss virtual memory DTLB demand load misses with low part of linear-to-physical address translation missed event=8,period=100003,umask=0x80  00     dtlb_load_misses.stlb_hit virtual memory Load operations that miss the first DTLB level but hit the second and do not cause page walks event=8,period=2000003,umask=0x60  00    Number of cache load STLB hits. No page walk dtlb_load_misses.stlb_hit_2m virtual memory Load misses that miss the  DTLB and hit the STLB (2M) event=8,period=2000003,umask=0x40  00    This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks dtlb_load_misses.stlb_hit_4k virtual memory Load misses that miss the  DTLB and hit the STLB (4K) event=8,period=2000003,umask=0x20  00    This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks dtlb_load_misses.walk_completed virtual memory Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size event=8,period=100003,umask=0xe  00    Completed page walks in any TLB of any page size due to demand load misses dtlb_load_misses.walk_completed_1g virtual memory Load miss in all TLB levels causes a page walk that completes. (1G) event=8,period=2000003,umask=8  00     dtlb_load_misses.walk_completed_2m_4m virtual memory Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M) event=8,period=2000003,umask=4  00    Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels dtlb_load_misses.walk_completed_4k virtual memory Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K) event=8,period=2000003,umask=2  00    Completed page walks due to demand load misses that caused 4K page walks in any TLB levels dtlb_load_misses.walk_duration virtual memory Cycles when PMH is busy with page walks event=8,period=2000003,umask=0x10  00    This event counts cycles when the  page miss handler (PMH) is servicing page walks caused by DTLB load misses dtlb_store_misses.miss_causes_a_walk virtual memory Store misses in all DTLB levels that cause page walks event=0x49,period=100003,umask=1  00    Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G) dtlb_store_misses.pde_cache_miss virtual memory DTLB store misses with low part of linear-to-physical address translation missed event=0x49,period=100003,umask=0x80  00     dtlb_store_misses.stlb_hit_2m virtual memory Store misses that miss the  DTLB and hit the STLB (2M) event=0x49,period=100003,umask=0x40  00    This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks dtlb_store_misses.stlb_hit_4k virtual memory Store misses that miss the  DTLB and hit the STLB (4K) event=0x49,period=100003,umask=0x20  00    This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks dtlb_store_misses.walk_completed virtual memory Store misses in all DTLB levels that cause completed page walks event=0x49,period=100003,umask=0xe  00    Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G) dtlb_store_misses.walk_completed_1g virtual memory Store misses in all DTLB levels that cause completed page walks. (1G) event=0x49,period=100003,umask=8  00     dtlb_store_misses.walk_completed_2m_4m virtual memory Store misses in all DTLB levels that cause completed page walks (2M/4M) event=0x49,period=100003,umask=4  00    Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure dtlb_store_misses.walk_completed_4k virtual memory Store miss in all TLB levels causes a page walk that completes. (4K) event=0x49,period=100003,umask=2  00    Completed page walks due to store misses in one or more TLB levels of 4K page structure dtlb_store_misses.walk_duration virtual memory Cycles when PMH is busy with page walks event=0x49,period=100003,umask=0x10  00    This event counts cycles when the  page miss handler (PMH) is servicing page walks caused by DTLB store misses ept.walk_cycles virtual memory Cycle count for an Extended Page table walk event=0x4f,period=2000003,umask=0x10  00     itlb.itlb_flush virtual memory Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages event=0xae,period=100003,umask=1  00    Counts the number of ITLB flushes, includes 4k/2M/4M pages itlb_misses.miss_causes_a_walk virtual memory Misses at all ITLB levels that cause page walks event=0x85,period=100003,umask=1  00    Misses in ITLB that causes a page walk of any page size itlb_misses.stlb_hit virtual memory Operations that miss the first ITLB level but hit the second and do not cause any page walks event=0x85,period=100003,umask=0x60  00    ITLB misses that hit STLB. No page walk itlb_misses.stlb_hit_2m virtual memory Code misses that miss the  DTLB and hit the STLB (2M) event=0x85,period=100003,umask=0x40  00    ITLB misses that hit STLB (2M) itlb_misses.stlb_hit_4k virtual memory Core misses that miss the  DTLB and hit the STLB (4K) event=0x85,period=100003,umask=0x20  00    ITLB misses that hit STLB (4K) itlb_misses.walk_completed virtual memory Misses in all ITLB levels that cause completed page walks event=0x85,period=100003,umask=0xe  00    Completed page walks in ITLB of any page size itlb_misses.walk_completed_1g virtual memory Store miss in all TLB levels causes a page walk that completes. (1G) event=0x85,period=100003,umask=8  00     itlb_misses.walk_completed_2m_4m virtual memory Code miss in all TLB levels causes a page walk that completes. (2M/4M) event=0x85,period=100003,umask=4  00    Completed page walks due to misses in ITLB 2M/4M page entries itlb_misses.walk_completed_4k virtual memory Code miss in all TLB levels causes a page walk that completes. (4K) event=0x85,period=100003,umask=2  00    Completed page walks due to misses in ITLB 4K page entries itlb_misses.walk_duration virtual memory Cycles when PMH is busy with page walks event=0x85,period=100003,umask=0x10  00    This event counts cycles when the  page miss handler (PMH) is servicing page walks caused by ITLB misses page_walker_loads.dtlb_l1 virtual memory Number of DTLB page walker hits in the L1+FB event=0xbc,period=2000003,umask=0x11  00    Number of DTLB page walker loads that hit in the L1+FB page_walker_loads.dtlb_l2 virtual memory Number of DTLB page walker hits in the L2 event=0xbc,period=2000003,umask=0x12  00    Number of DTLB page walker loads that hit in the L2 page_walker_loads.dtlb_l3 virtual memory Number of DTLB page walker hits in the L3 + XSNP  Spec update: HSD25 event=0xbc,period=2000003,umask=0x14  00    Number of DTLB page walker loads that hit in the L3  Spec update: HSD25 page_walker_loads.dtlb_memory virtual memory Number of DTLB page walker hits in Memory  Spec update: HSD25 event=0xbc,period=2000003,umask=0x18  00    Number of DTLB page walker loads from memory  Spec update: HSD25 page_walker_loads.ept_dtlb_l1 virtual memory Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB event=0xbc,period=2000003,umask=0x41  00     page_walker_loads.ept_dtlb_l2 virtual memory Counts the number of Extended Page Table walks from the DTLB that hit in the L2 event=0xbc,period=2000003,umask=0x42  00     page_walker_loads.ept_dtlb_l3 virtual memory Counts the number of Extended Page Table walks from the DTLB that hit in the L3 event=0xbc,period=2000003,umask=0x44  00     page_walker_loads.ept_dtlb_memory virtual memory Counts the number of Extended Page Table walks from the DTLB that hit in memory event=0xbc,period=2000003,umask=0x48  00     page_walker_loads.ept_itlb_l1 virtual memory Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB event=0xbc,period=2000003,umask=0x81  00     page_walker_loads.ept_itlb_l2 virtual memory Counts the number of Extended Page Table walks from the ITLB that hit in the L2 event=0xbc,period=2000003,umask=0x82  00     page_walker_loads.ept_itlb_l3 virtual memory Counts the number of Extended Page Table walks from the ITLB that hit in the L2 event=0xbc,period=2000003,umask=0x84  00     page_walker_loads.ept_itlb_memory virtual memory Counts the number of Extended Page Table walks from the ITLB that hit in memory event=0xbc,period=2000003,umask=0x88  00     page_walker_loads.itlb_l1 virtual memory Number of ITLB page walker hits in the L1+FB event=0xbc,period=2000003,umask=0x21  00    Number of ITLB page walker loads that hit in the L1+FB page_walker_loads.itlb_l2 virtual memory Number of ITLB page walker hits in the L2 event=0xbc,period=2000003,umask=0x22  00    Number of ITLB page walker loads that hit in the L2 page_walker_loads.itlb_l3 virtual memory Number of ITLB page walker hits in the L3 + XSNP  Spec update: HSD25 event=0xbc,period=2000003,umask=0x24  00    Number of ITLB page walker loads that hit in the L3  Spec update: HSD25 page_walker_loads.itlb_memory virtual memory Number of ITLB page walker hits in Memory  Spec update: HSD25 event=0xbc,period=2000003,umask=0x28  00    Number of ITLB page walker loads from memory  Spec update: HSD25 tlb_flush.dtlb_thread virtual memory DTLB flush attempts of the thread-specific entries event=0xbd,period=100003,umask=1  00     tlb_flush.stlb_any virtual memory STLB flush attempts event=0xbd,period=100003,umask=0x20  00    Count number of STLB flush attempts mem_load_uops_l3_miss_retired.remote_dram cache Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event) event=0xd3,period=100003,umask=4  00     mem_load_uops_l3_miss_retired.remote_fwd cache Retired load uop whose Data Source was: forwarded from remote cache  Supports address when precise.  Spec update: HSM30 (Precise event) event=0xd3,period=100003,umask=0x20  00     mem_load_uops_l3_miss_retired.remote_hitm cache Retired load uop whose Data Source was: Remote cache HITM  Supports address when precise.  Spec update: HSM30 (Precise event) event=0xd3,period=100003,umask=0x10  00     offcore_response.demand_code_rd.llc_hit.hitm_other_core cache Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0004  00     offcore_response.demand_code_rd.llc_hit.hit_other_core_no_fwd cache Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0004  00     offcore_response.demand_data_rd.llc_hit.hitm_other_core cache Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0001  00     offcore_response.demand_data_rd.llc_hit.hit_other_core_no_fwd cache Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0001  00     offcore_response.demand_rfo.llc_hit.hit_other_core_no_fwd cache Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0002  00     offcore_response.pf_l2_code_rd.llc_hit.any_response cache Counts all prefetch (that bring data to LLC only) code reads hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0040  00     offcore_response.pf_l2_data_rd.llc_hit.any_response cache Counts prefetch (that bring data to L2) data reads hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0010  00     offcore_response.pf_l2_rfo.llc_hit.any_response cache Counts all prefetch (that bring data to L2) RFOs hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0020  00     offcore_response.pf_llc_data_rd.llc_hit.any_response cache Counts all prefetch (that bring data to LLC only) data reads hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0080  00     offcore_response.all_code_rd.llc_miss.local_dram memory Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x600400244  00     offcore_response.all_data_rd.llc_miss.local_dram memory Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x600400091  00     offcore_response.all_data_rd.llc_miss.remote_dram memory Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63F800091  00     offcore_response.all_data_rd.llc_miss.remote_hit_forward memory Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00091  00     offcore_response.all_reads.llc_miss.local_dram memory Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x6004007F7  00     offcore_response.all_reads.llc_miss.remote_dram memory Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63F8007F7  00     offcore_response.all_reads.llc_miss.remote_hit_forward memory Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC007F7  00     offcore_response.all_rfo.llc_miss.local_dram memory Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x600400122  00     offcore_response.demand_code_rd.llc_miss.any_response memory Counts all demand code reads miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00004  00     offcore_response.demand_code_rd.llc_miss.local_dram memory Counts all demand code reads miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x600400004  00     offcore_response.demand_data_rd.llc_miss.any_response memory Counts demand data reads miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00001  00     offcore_response.demand_data_rd.llc_miss.local_dram memory Counts demand data reads miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x600400001  00     offcore_response.demand_rfo.llc_miss.local_dram memory Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x600400002  00     offcore_response.pf_l2_code_rd.llc_miss.any_response memory Counts all prefetch (that bring data to LLC only) code reads miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00040  00     offcore_response.pf_l2_data_rd.llc_miss.any_response memory Counts prefetch (that bring data to L2) data reads miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00010  00     offcore_response.pf_l2_rfo.llc_miss.any_response memory Counts all prefetch (that bring data to L2) RFOs miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00020  00     offcore_response.pf_llc_data_rd.llc_miss.any_response memory Counts all prefetch (that bring data to LLC only) data reads miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00080  00     unc_c_llc_victims.s_state uncore cache Lines in S State event=0x37,umask=4  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_c_ring_ad_used.all uncore cache AD Ring In Use; All event=0x1b,umask=0xf  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.down uncore cache AD Ring In Use; Down event=0x1b,umask=0xc  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.down_even uncore cache AD Ring In Use; Down and Even event=0x1b,umask=4  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity unc_c_ring_ad_used.down_odd uncore cache AD Ring In Use; Down and Odd event=0x1b,umask=8  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_c_ring_ad_used.up uncore cache AD Ring In Use; Up event=0x1b,umask=3  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.up_even uncore cache AD Ring In Use; Up and Even event=0x1b,umask=1  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_c_ring_ad_used.up_odd uncore cache AD Ring In Use; Up and Odd event=0x1b,umask=2  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_c_ring_ak_used.all uncore cache AK Ring In Use; All event=0x1c,umask=0xf  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.down_even uncore cache AK Ring In Use; Down and Even event=0x1c,umask=4  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity unc_c_ring_ak_used.down_odd uncore cache AK Ring In Use; Down and Odd event=0x1c,umask=8  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_c_ring_ak_used.up_even uncore cache AK Ring In Use; Up and Even event=0x1c,umask=1  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_c_ring_ak_used.up_odd uncore cache AK Ring In Use; Up and Odd event=0x1c,umask=2  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_c_ring_bl_used.all uncore cache BL Ring in Use; Down event=0x1d,umask=0xf  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.down_even uncore cache BL Ring in Use; Down and Even event=0x1d,umask=4  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity unc_c_ring_bl_used.down_odd uncore cache BL Ring in Use; Down and Odd event=0x1d,umask=8  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_c_ring_bl_used.up_even uncore cache BL Ring in Use; Up and Even event=0x1d,umask=1  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_c_ring_bl_used.up_odd uncore cache BL Ring in Use; Up and Odd event=0x1d,umask=2  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_c_ring_iv_used.any uncore cache BL Ring in Use; Any event=0x1e,umask=0xf  01    Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in HSX  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity unc_c_ring_iv_used.dn uncore cache BL Ring in Use; Any event=0x1e,umask=0xc  01    Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in HSX  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity unc_c_ring_iv_used.down uncore cache BL Ring in Use; Down event=0x1e,umask=0xcc  01    Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in HSX  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters for Down polarity unc_c_ring_iv_used.up uncore cache BL Ring in Use; Any event=0x1e,umask=3  01    Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in HSX  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity unc_c_ring_sink_starved.ad uncore cache UNC_C_RING_SINK_STARVED.AD event=6,umask=1  01     unc_c_ring_sink_starved.ak uncore cache UNC_C_RING_SINK_STARVED.AK event=6,umask=2  01     unc_c_ring_sink_starved.bl uncore cache UNC_C_RING_SINK_STARVED.BL event=6,umask=4  01     unc_c_ring_sink_starved.iv uncore cache UNC_C_RING_SINK_STARVED.IV event=6,umask=8  01     unc_c_tor_inserts.local_opcode uncore cache TOR Inserts; Local Memory - Opcode Matched event=0x35,umask=0x21  01    Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions, satisfied by an opcode,  inserted into the TOR that are satisfied by locally HOMed memory unc_h_snoop_resp.rspsfwd uncore cache Shared line forwarded from remote cache event=0x21,umask=8  0164Bytes    Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspSFwd.  This is returned when a remote caching agent forwards data but holds on to its currently copy.  This is common for data and code reads that hit in a remote socket in E or F state unc_h_snp_resp_recv_local.rspsfwd uncore cache Snoop Responses Received Local; RspSFwd event=0x60,umask=8  01    Number of snoop responses received for a Local  request; Filters for a snoop response of RspSFwd.  This is returned when a remote caching agent forwards data but holds on to its currently copy.  This is common for data and code reads that hit in a remote socket in E or F state unc_i_transactions.writes uncore interconnect Inbound Transaction Count; Writes event=0x16,umask=2  01    Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only write requests.  Each write request should have a prefetch, so there is no need to explicitly track these requests.  For writes that are tickled and have to retry, the counter will be incremented for each retry unc_q_clockticks uncore interconnect Number of qfclks event=0x14  01    Counts the number of clocks in the QPI LL.  This clock runs at 1/4th the GT/s speed of the QPI link.  For example, a 4GT/s link will have qfclk or 1GHz.  HSX does not support dynamic link speeds, so this frequency is fixed unc_q_rxl_crc_errors.normal_op uncore interconnect CRC Errors Detected; Normal Operations event=3,umask=2  01    Number of CRC errors detected in the QPI Agent.  Each QPI flit incorporates 8 bits of CRC for error detection.  This counts the number of flits where the CRC was able to detect an error.  After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during normal operation unc_s_ring_ad_used.down_even uncore interconnect AD Ring In Use; Down and Event event=0x1b,umask=4  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity unc_s_ring_ad_used.down_odd uncore interconnect AD Ring In Use; Down and Odd event=0x1b,umask=8  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_s_ring_ad_used.up_even uncore interconnect AD Ring In Use; Up and Even event=0x1b,umask=1  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_s_ring_ad_used.up_odd uncore interconnect AD Ring In Use; Up and Odd event=0x1b,umask=2  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_s_ring_ak_used.down_even uncore interconnect AK Ring In Use; Down and Event event=0x1c,umask=4  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity unc_s_ring_ak_used.down_odd uncore interconnect AK Ring In Use; Down and Odd event=0x1c,umask=8  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_s_ring_ak_used.up_even uncore interconnect AK Ring In Use; Up and Even event=0x1c,umask=1  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_s_ring_ak_used.up_odd uncore interconnect AK Ring In Use; Up and Odd event=0x1c,umask=2  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_s_ring_bl_used.down_even uncore interconnect BL Ring in Use; Down and Event event=0x1d,umask=4  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity unc_s_ring_bl_used.down_odd uncore interconnect BL Ring in Use; Down and Odd event=0x1d,umask=8  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity unc_s_ring_bl_used.up_even uncore interconnect BL Ring in Use; Up and Even event=0x1d,umask=1  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity unc_s_ring_bl_used.up_odd uncore interconnect BL Ring in Use; Up and Odd event=0x1d,umask=2  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity unc_u_clockticks uncore interconnect UNC_U_CLOCKTICKS event=0  01     unc_m_clockticks uncore memory DRAM Clockticks event=0  01     unc_p_clockticks uncore power pclk Cycles event=0  01    The PCU runs off a fixed 800 MHz clock.  This event counts the number of pclk cycles measured while the counter was enabled.  The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time unc_p_freq_band0_cycles uncore power Frequency Residency event=0xb  01    Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  One can use all four counters with this event, so it is possible to track up to 4 configurable bands.  One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency unc_p_freq_band1_cycles uncore power Frequency Residency event=0xc  01    Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  One can use all four counters with this event, so it is possible to track up to 4 configurable bands.  One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency unc_p_freq_band2_cycles uncore power Frequency Residency event=0xd  01    Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  One can use all four counters with this event, so it is possible to track up to 4 configurable bands.  One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency unc_p_freq_band3_cycles uncore power Frequency Residency event=0xe  01    Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  One can use all four counters with this event, so it is possible to track up to 4 configurable bands.  One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency unc_p_ufs_transitions_no_change uncore power UNC_P_UFS_TRANSITIONS_NO_CHANGE event=0x79  01    Ring GV with same final and initial frequency l1d_pend_miss.l2_stall cache Number of cycles a demand request has waited due to L1D due to lack of L2 resources event=0x48,period=1000003,umask=4  00    Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses l2_lines_out.non_silent cache Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fill event=0xf2,period=200003,umask=2  00    Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3 l2_lines_out.silent cache Non-modified cache lines that are silently dropped by L2 cache event=0xf2,period=200003,umask=1  00    Counts the number of lines that are silently dropped by L2 cache. These lines are typically in Shared or Exclusive state. A non-threaded event l2_lines_out.useless_hwpf cache Cache lines that have been L2 hardware prefetched but not used by demand accesses event=0xf2,period=200003,umask=4  00    Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cache l2_rqsts.miss cache This event is deprecated event=0x24,period=200003,umask=0x3f  10     l2_rqsts.references cache This event is deprecated event=0x24,period=200003,umask=0xff  10     mem_inst_retired.all_loads cache Retired load instructions  Supports address when precise event=0xd0,period=1000003,umask=0x81  00    Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW  Supports address when precise mem_inst_retired.all_stores cache Retired store instructions  Supports address when precise event=0xd0,period=1000003,umask=0x82  00    Counts all retired store instructions  Supports address when precise mem_inst_retired.any cache All retired memory instructions  Supports address when precise event=0xd0,period=1000003,umask=0x83  00    Counts all retired memory instructions - loads and stores  Supports address when precise mem_inst_retired.lock_loads cache Retired load instructions with locked access  Supports address when precise event=0xd0,period=100007,umask=0x21  00    Counts retired load instructions with locked access  Supports address when precise mem_inst_retired.split_loads cache Retired load instructions that split across a cacheline boundary  Supports address when precise event=0xd0,period=100003,umask=0x41  00    Counts retired load instructions that split across a cacheline boundary  Supports address when precise mem_inst_retired.split_stores cache Retired store instructions that split across a cacheline boundary  Supports address when precise event=0xd0,period=100003,umask=0x42  00    Counts retired store instructions that split across a cacheline boundary  Supports address when precise mem_inst_retired.stlb_miss_loads cache Retired load instructions that miss the STLB  Supports address when precise event=0xd0,period=100003,umask=0x11  00    Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB)  Supports address when precise mem_inst_retired.stlb_miss_stores cache Retired store instructions that miss the STLB  Supports address when precise event=0xd0,period=100003,umask=0x12  00    Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB)  Supports address when precise mem_load_l3_hit_retired.xsnp_hit cache Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache  Supports address when precise event=0xd2,period=20011,umask=2  00    Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache  Supports address when precise mem_load_l3_hit_retired.xsnp_hitm cache Retired load instructions whose data sources were HitM responses from shared L3  Supports address when precise event=0xd2,period=20011,umask=4  00    Counts retired load instructions whose data sources were HitM responses from shared L3  Supports address when precise mem_load_l3_hit_retired.xsnp_miss cache Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache  Supports address when precise event=0xd2,period=20011,umask=1  00    Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache  Supports address when precise mem_load_l3_hit_retired.xsnp_none cache Retired load instructions whose data sources were hits in L3 without snoops required  Supports address when precise event=0xd2,period=100003,umask=8  00    Counts retired load instructions whose data sources were hits in L3 without snoops required  Supports address when precise mem_load_misc_retired.uc cache Retired instructions with at least 1 uncacheable load or Bus Lock  Supports address when precise event=0xd4,period=100007,umask=4  00    Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock)  Supports address when precise mem_load_retired.fb_hit cache Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1  Supports address when precise event=0xd1,period=100007,umask=0x40  00    Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready  Supports address when precise mem_load_retired.l1_hit cache Retired load instructions with L1 cache hits as data sources  Supports address when precise event=0xd1,period=1000003,umask=1  00    Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source  Supports address when precise mem_load_retired.l1_miss cache Retired load instructions missed L1 cache as data sources  Supports address when precise event=0xd1,period=200003,umask=8  00    Counts retired load instructions with at least one uop that missed in the L1 cache  Supports address when precise mem_load_retired.l2_hit cache Retired load instructions with L2 cache hits as data sources  Supports address when precise event=0xd1,period=200003,umask=2  00    Counts retired load instructions with L2 cache hits as data sources  Supports address when precise mem_load_retired.l2_miss cache Retired load instructions missed L2 cache as data sources  Supports address when precise event=0xd1,period=100021,umask=0x10  00    Counts retired load instructions missed L2 cache as data sources  Supports address when precise mem_load_retired.l3_hit cache Retired load instructions with L3 cache hits as data sources  Supports address when precise event=0xd1,period=100021,umask=4  00    Counts retired load instructions with at least one uop that hit in the L3 cache  Supports address when precise mem_load_retired.l3_miss cache Retired load instructions missed L3 cache as data sources  Supports address when precise event=0xd1,period=50021,umask=0x20  00    Counts retired load instructions with at least one uop that missed in the L3 cache  Supports address when precise ocr.demand_code_rd.any_response cache Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10004  00     ocr.demand_code_rd.l3_hit.any cache Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent or not event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC03C0004  00     ocr.demand_code_rd.l3_hit.snoop_hitm cache Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0004  00     ocr.demand_code_rd.l3_hit.snoop_hit_no_fwd cache Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0004  00     ocr.demand_code_rd.l3_hit.snoop_miss cache Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent but no other cores had the data event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0004  00     ocr.demand_code_rd.l3_hit.snoop_not_needed cache Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was not needed to satisfy the request event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0004  00     ocr.demand_code_rd.l3_hit.snoop_sent cache Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent event=0xb7,period=100003,umask=1,offcore_rsp=0x1E003C0004  00     ocr.demand_data_rd.any_response cache Counts demand data reads that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10001  00     ocr.demand_data_rd.l3_hit.any cache Counts demand data reads that hit a cacheline in the L3 where a snoop was sent or not event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC03C0001  00     ocr.demand_data_rd.l3_hit.snoop_hitm cache Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0001  00     ocr.demand_data_rd.l3_hit.snoop_hit_no_fwd cache Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0001  00     ocr.demand_data_rd.l3_hit.snoop_miss cache Counts demand data reads that hit a cacheline in the L3 where a snoop was sent but no other cores had the data event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0001  00     ocr.demand_data_rd.l3_hit.snoop_not_needed cache Counts demand data reads that hit a cacheline in the L3 where a snoop was not needed to satisfy the request event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0001  00     ocr.demand_data_rd.l3_hit.snoop_sent cache Counts demand data reads that hit a cacheline in the L3 where a snoop was sent event=0xb7,period=100003,umask=1,offcore_rsp=0x1E003C0001  00     ocr.demand_rfo.any_response cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10002  00     ocr.demand_rfo.l3_hit.any cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC03C0002  00     ocr.demand_rfo.l3_hit.snoop_hitm cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0002  00     ocr.demand_rfo.l3_hit.snoop_hit_no_fwd cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0002  00     ocr.demand_rfo.l3_hit.snoop_miss cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0002  00     ocr.demand_rfo.l3_hit.snoop_not_needed cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0002  00     ocr.demand_rfo.l3_hit.snoop_sent cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent event=0xb7,period=100003,umask=1,offcore_rsp=0x1E003C0002  00     ocr.hwpf_l1d_and_swpf.any_response cache Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10400  00     ocr.hwpf_l1d_and_swpf.l3_hit.any cache Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC03C0400  00     ocr.hwpf_l1d_and_swpf.l3_hit.snoop_miss cache Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0400  00     ocr.hwpf_l1d_and_swpf.l3_hit.snoop_not_needed cache Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0400  00     ocr.hwpf_l2_data_rd.any_response cache Counts hardware prefetch data reads (which bring data to L2)  that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10010  00     ocr.hwpf_l2_data_rd.l3_hit.any cache Counts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop was sent or not event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC03C0010  00     ocr.hwpf_l2_data_rd.l3_hit.snoop_hitm cache Counts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0010  00     ocr.hwpf_l2_data_rd.l3_hit.snoop_hit_no_fwd cache Counts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0010  00     ocr.hwpf_l2_data_rd.l3_hit.snoop_miss cache Counts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop was sent but no other cores had the data event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0010  00     ocr.hwpf_l2_data_rd.l3_hit.snoop_not_needed cache Counts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop was not needed to satisfy the request event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0010  00     ocr.hwpf_l2_data_rd.l3_hit.snoop_sent cache Counts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop was sent event=0xb7,period=100003,umask=1,offcore_rsp=0x1E003C0010  00     ocr.hwpf_l2_rfo.any_response cache Counts hardware prefetch RFOs (which bring data to L2) that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10020  00     ocr.hwpf_l2_rfo.l3_hit.any cache Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC03C0020  00     ocr.hwpf_l2_rfo.l3_hit.snoop_hitm cache Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0020  00     ocr.hwpf_l2_rfo.l3_hit.snoop_hit_no_fwd cache Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0020  00     ocr.hwpf_l2_rfo.l3_hit.snoop_miss cache Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C0020  00     ocr.hwpf_l2_rfo.l3_hit.snoop_not_needed cache Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0020  00     ocr.hwpf_l2_rfo.l3_hit.snoop_sent cache Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent event=0xb7,period=100003,umask=1,offcore_rsp=0x1E003C0020  00     ocr.hwpf_l3.l3_hit.any cache Counts hardware prefetches to the L3 only that hit a cacheline in the L3 where a snoop was sent or not event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC03C2380  00     ocr.other.l3_hit.snoop_hit_no_fwd cache Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C8000  00     ocr.other.l3_hit.snoop_miss cache Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent but no other cores had the data event=0xb7,period=100003,umask=1,offcore_rsp=0x2003C8000  00     ocr.other.l3_hit.snoop_not_needed cache Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was not needed to satisfy the request event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C8000  00     ocr.other.l3_hit.snoop_sent cache Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent event=0xb7,period=100003,umask=1,offcore_rsp=0x1E003C8000  00     ocr.streaming_wr.l3_hit.any cache Counts streaming stores that hit a cacheline in the L3 where a snoop was sent or not event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC03C0800  00     offcore_requests.all_requests cache Counts memory transactions sent to the uncore event=0xb0,period=100003,umask=0x80  00    Counts memory transactions sent to the uncore including requests initiated by the core, all L3 prefetches, reads resulting from page walks, and snoop responses offcore_requests_outstanding.all_data_rd cache For every cycle, increments by the number of outstanding data read requests pending event=0x60,period=1000003,umask=8  00    For every cycle, increments by the number of outstanding data read requests pending.  Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3.  Reads due to page walks resulting from any request type will also be counted.  Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor offcore_requests_outstanding.cycles_with_data_rd cache Cycles where at least 1 outstanding data read request is pending event=0x60,cmask=1,period=1000003,umask=8  00    Cycles where at least 1 outstanding data read request is pending.  Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3.  Reads due to page walks resulting from any request type will also be counted.  Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor offcore_requests_outstanding.cycles_with_demand_code_rd cache Cycles with outstanding code read requests pending event=0x60,cmask=1,period=1000003,umask=2  00    Cycles with outstanding code read requests pending.  Code Read requests include both cacheable and non-cacheable Code Reads.  Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor offcore_requests_outstanding.cycles_with_demand_rfo cache Cycles where at least 1 outstanding Demand RFO request is pending event=0x60,cmask=1,period=1000003,umask=4  00    Cycles where at least 1 outstanding Demand RFO request is pending.   RFOs are initiated by a core as part of a data store operation.  Demand RFO requests include RFOs, locks, and ItoM transactions.  Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor offcore_requests_outstanding.demand_data_rd cache For every cycle, increments by the number of outstanding demand data read requests pending event=0x60,period=1000003,umask=1  00    For every cycle, increments by the number of outstanding demand data read requests pending.   Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor offcore_requests_outstanding.demand_rfo cache Store Read transactions pending for off-core. Highly correlated event=0x60,period=1000003,umask=4  00    Counts the number of off-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO transaction is considered to be in the Off-core outstanding state between L2 cache miss and transaction completion sq_misc.bus_lock cache Counts bus locks, accounts for cache line split locks and UC locks event=0xf4,period=100003,umask=0x10  00    Counts the more expensive bus lock needed to enforce cache coherency for certain memory accesses that need to be done atomically.  Can be created by issuing an atomic instruction (via the LOCK prefix) which causes a cache line split or accesses uncacheable memory sq_misc.sq_full cache Cycles the queue waiting for offcore responses is full event=0xf4,period=100003,umask=4  00    Counts the cycles for which the thread is active and the queue waiting for responses from the uncore cannot take any more entries sw_prefetch_access.any cache Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed event=0x32,period=100003,umask=0xf  00     sw_prefetch_access.nta cache Number of PREFETCHNTA instructions executed event=0x32,period=100003,umask=1  00    Counts the number of PREFETCHNTA instructions executed sw_prefetch_access.prefetchw cache Number of PREFETCHW instructions executed event=0x32,period=100003,umask=8  00    Counts the number of PREFETCHW instructions executed sw_prefetch_access.t0 cache Number of PREFETCHT0 instructions executed event=0x32,period=100003,umask=2  00    Counts the number of PREFETCHT0 instructions executed sw_prefetch_access.t1_t2 cache Number of PREFETCHT1 or PREFETCHT2 instructions executed event=0x32,period=100003,umask=4  00    Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed fp_arith_inst_retired.scalar floating point Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below.  Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element event=0xc7,period=1000003,umask=3  00    Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.vector floating point Number of any Vector retired FP arithmetic instructions event=0xc7,period=1000003,umask=0xfc  00     decode.lcp frontend Stalls caused by changing prefix length of the instruction. [This event is alias to ILD_STALL.LCP] event=0x87,period=500009,umask=1  00    Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to ILD_STALL.LCP] dsb2mite_switches.count frontend Decode Stream Buffer (DSB)-to-MITE transitions count event=0xab,cmask=1,edge=1,period=100003,umask=2  00    Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitions dsb2mite_switches.penalty_cycles frontend DSB-to-MITE switch true penalty cycles event=0xab,period=100003,umask=2  00    Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE frontend_retired.any_dsb_miss frontend Retired Instructions who experienced DSB miss event=0xc6,period=100007,umask=1,frontend=0x1  00    Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss frontend_retired.dsb_miss frontend Retired Instructions who experienced a critical DSB miss event=0xc6,period=100007,umask=1,frontend=0x11  00    Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss frontend_retired.itlb_miss frontend Retired Instructions who experienced iTLB true miss event=0xc6,period=100007,umask=1,frontend=0x14  00    Counts retired Instructions that experienced iTLB (Instruction TLB) true miss frontend_retired.l1i_miss frontend Retired Instructions who experienced Instruction L1 Cache true miss event=0xc6,period=100007,umask=1,frontend=0x12  00    Counts retired Instructions who experienced Instruction L1 Cache true miss frontend_retired.l2_miss frontend Retired Instructions who experienced Instruction L2 Cache true miss event=0xc6,period=100007,umask=1,frontend=0x13  00    Counts retired Instructions who experienced Instruction L2 Cache true miss frontend_retired.latency_ge_1 frontend Retired instructions after front-end starvation of at least 1 cycle event=0xc6,period=100007,umask=1,frontend=0x500106  00    Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall frontend_retired.latency_ge_128 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=1,frontend=0x508006  00    Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall frontend_retired.latency_ge_16 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=1,frontend=0x501006  00    Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops frontend_retired.latency_ge_2 frontend Retired instructions after front-end starvation of at least 2 cycles event=0xc6,period=100007,umask=1,frontend=0x500206  00    Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall frontend_retired.latency_ge_256 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=1,frontend=0x510006  00    Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall frontend_retired.latency_ge_2_bubbles_ge_1 frontend Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=1,frontend=0x100206  00    Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall frontend_retired.latency_ge_32 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=1,frontend=0x502006  00    Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops frontend_retired.latency_ge_4 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=1,frontend=0x500406  00    Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall frontend_retired.latency_ge_512 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=1,frontend=0x520006  00    Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall frontend_retired.latency_ge_64 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=1,frontend=0x504006  00    Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall frontend_retired.latency_ge_8 frontend Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall event=0xc6,period=100007,umask=1,frontend=0x500806  00    Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops frontend_retired.stlb_miss frontend Retired Instructions who experienced STLB (2nd level TLB) true miss event=0xc6,period=100007,umask=1,frontend=0x15  00    Counts retired Instructions that experienced STLB (2nd level TLB) true miss icache_16b.ifdata_stall frontend Cycles where a code fetch is stalled due to L1 instruction cache miss. [This event is alias to ICACHE_DATA.STALLS] event=0x80,period=500009,umask=4  00    Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity. [This event is alias to ICACHE_DATA.STALLS] icache_64b.iftag_hit frontend Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity event=0x83,period=200003,umask=1  00    Counts instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses icache_64b.iftag_miss frontend Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity event=0x83,period=200003,umask=2  00    Counts instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses icache_64b.iftag_stall frontend Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS] event=0x83,period=200003,umask=4  00    Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS] icache_data.stalls frontend Cycles where a code fetch is stalled due to L1 instruction cache miss. [This event is alias to ICACHE_16B.IFDATA_STALL] event=0x80,period=500009,umask=4  00    Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity. [This event is alias to ICACHE_16B.IFDATA_STALL] icache_tag.stalls frontend Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL] event=0x83,period=200003,umask=4  00    Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL] idq.dsb_cycles_ok frontend Cycles DSB is delivering optimal number of Uops event=0x79,cmask=5,period=2000003,umask=8  00    Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the DSB (Decode Stream Buffer) path. Count includes uops that may 'bypass' the IDQ idq.mite_cycles_ok frontend Cycles MITE is delivering optimal number of Uops event=0x79,cmask=5,period=2000003,umask=4  00    Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB) idq.ms_cycles_any frontend Cycles when uops are being delivered to IDQ while MS is busy event=0x79,cmask=1,period=2000003,umask=0x30  00    Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE idq.ms_switches frontend Number of switches from DSB or MITE to the MS event=0x79,cmask=1,edge=1,period=100003,umask=0x30  00    Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer idq.ms_uops frontend Uops delivered to IDQ while MS is busy event=0x79,period=100003,umask=0x30  00    Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS idq_uops_not_delivered.cycles_0_uops_deliv.core frontend Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled event=0x9c,cmask=5,period=1000003,umask=1  00    Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle idq_uops_not_delivered.cycles_fe_was_ok frontend Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled event=0x9c,cmask=1,inv=1,period=1000003,umask=1  00    Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle hle_retired.aborted memory Number of times an HLE execution aborted due to any reasons (multiple categories may count as one) event=0xc8,period=100003,umask=4  00    Counts the number of times HLE abort was triggered hle_retired.aborted_events memory Number of times an HLE execution aborted due to unfriendly events (such as interrupts) event=0xc8,period=100003,umask=0x80  00    Counts the number of times an HLE execution aborted due to unfriendly events (such as interrupts) hle_retired.aborted_mem memory Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts) event=0xc8,period=100003,umask=8  00    Counts the number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts) hle_retired.aborted_unfriendly memory Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.) event=0xc8,period=100003,umask=0x20  00    Counts the number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.) hle_retired.commit memory Number of times an HLE execution successfully committed event=0xc8,period=100003,umask=2  00    Counts the number of times HLE commit succeeded hle_retired.start memory Number of times an HLE execution started event=0xc8,period=100003,umask=1  00    Counts the number of times we entered an HLE region. Does not count nested transactions ocr.demand_code_rd.dram memory Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request event=0xb7,period=100003,umask=1,offcore_rsp=0x184000004  00     ocr.demand_code_rd.l3_miss memory Counts demand instruction fetches and L1 instruction cache prefetches that was not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00004  00     ocr.demand_code_rd.local_dram memory Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request event=0xb7,period=100003,umask=1,offcore_rsp=0x184000004  00     ocr.demand_data_rd.dram memory Counts demand data reads that DRAM supplied the request event=0xb7,period=100003,umask=1,offcore_rsp=0x184000001  00     ocr.demand_data_rd.l3_miss memory Counts demand data reads that was not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00001  00     ocr.demand_data_rd.local_dram memory Counts demand data reads that DRAM supplied the request event=0xb7,period=100003,umask=1,offcore_rsp=0x184000001  00     ocr.demand_rfo.dram memory Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request event=0xb7,period=100003,umask=1,offcore_rsp=0x184000002  00     ocr.demand_rfo.l3_miss memory Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that was not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00002  00     ocr.demand_rfo.local_dram memory Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request event=0xb7,period=100003,umask=1,offcore_rsp=0x184000002  00     ocr.hwpf_l1d_and_swpf.dram memory Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request event=0xb7,period=100003,umask=1,offcore_rsp=0x184000400  00     ocr.hwpf_l1d_and_swpf.l3_miss memory Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that was not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00400  00     ocr.hwpf_l1d_and_swpf.local_dram memory Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request event=0xb7,period=100003,umask=1,offcore_rsp=0x184000400  00     ocr.hwpf_l2_data_rd.dram memory Counts hardware prefetch data reads (which bring data to L2)  that DRAM supplied the request event=0xb7,period=100003,umask=1,offcore_rsp=0x184000010  00     ocr.hwpf_l2_data_rd.l3_miss memory Counts hardware prefetch data reads (which bring data to L2)  that was not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00010  00     ocr.hwpf_l2_data_rd.local_dram memory Counts hardware prefetch data reads (which bring data to L2)  that DRAM supplied the request event=0xb7,period=100003,umask=1,offcore_rsp=0x184000010  00     ocr.hwpf_l2_rfo.dram memory Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request event=0xb7,period=100003,umask=1,offcore_rsp=0x184000020  00     ocr.hwpf_l2_rfo.l3_miss memory Counts hardware prefetch RFOs (which bring data to L2) that was not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00020  00     ocr.hwpf_l2_rfo.local_dram memory Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request event=0xb7,period=100003,umask=1,offcore_rsp=0x184000020  00     ocr.other.dram memory Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request event=0xb7,period=100003,umask=1,offcore_rsp=0x184008000  00     ocr.other.l3_miss memory Counts miscellaneous requests, such as I/O and un-cacheable accesses that was not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC08000  00     ocr.other.local_dram memory Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request event=0xb7,period=100003,umask=1,offcore_rsp=0x184008000  00     ocr.streaming_wr.dram memory Counts streaming stores that DRAM supplied the request event=0xb7,period=100003,umask=1,offcore_rsp=0x184000800  00     ocr.streaming_wr.l3_miss memory Counts streaming stores that was not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC00800  00     ocr.streaming_wr.local_dram memory Counts streaming stores that DRAM supplied the request event=0xb7,period=100003,umask=1,offcore_rsp=0x184000800  00     offcore_requests.l3_miss_demand_data_rd memory Counts demand data read requests that miss the L3 cache event=0xb0,period=100003,umask=0x10  00     offcore_requests_outstanding.cycles_with_l3_miss_demand_data_rd memory Cycles where at least one demand data read request known to have missed the L3 cache is pending event=0x60,cmask=1,period=1000003,umask=0x10  00    Cycles where at least one demand data read request known to have missed the L3 cache is pending.  Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known to have missed the L3 cache rtm_retired.aborted memory Number of times an RTM execution aborted event=0xc9,period=100003,umask=4  00    Counts the number of times RTM abort was triggered tx_exec.misc2 memory Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region event=0x5d,period=100003,umask=2  00    Counts Unfriendly TSX abort triggered by a vzeroupper instruction tx_exec.misc3 memory Number of times an instruction execution caused the transactional nest count supported to be exceeded event=0x5d,period=100003,umask=4  00    Counts Unfriendly TSX abort triggered by a nest count that is too deep tx_mem.abort_hle_elision_buffer_mismatch memory Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer event=0x54,period=100003,umask=0x10  00    Counts the number of times a TSX Abort was triggered due to release/commit but data and address mismatch tx_mem.abort_hle_elision_buffer_not_empty memory Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero event=0x54,period=100003,umask=8  00    Counts the number of times a TSX Abort was triggered due to commit but Lock Buffer not empty tx_mem.abort_hle_elision_buffer_unsupported_alignment memory Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer event=0x54,period=100003,umask=0x20  00    Counts the number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer tx_mem.abort_hle_store_to_elided_lock memory Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer event=0x54,period=100003,umask=4  00    Counts the number of times a TSX Abort was triggered due to a non-release/commit store to lock tx_mem.hle_elision_buffer_full memory Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero event=0x54,period=100003,umask=0x40  00    Counts the number of times we could not allocate Lock Buffer core_power.lvl0_turbo_license other Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule event=0x28,period=200003,umask=7  00    Counts Core cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes core_power.lvl1_turbo_license other Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule event=0x28,period=200003,umask=0x18  00    Counts Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions ocr.other.any_response other Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x18000  00     ocr.streaming_wr.any_response other Counts streaming stores that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10800  00     arith.divider_active pipeline Cycles when divide unit is busy executing divide or square root operations event=0x14,cmask=1,period=1000003,umask=9  00    Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations arith.fp_divider_active pipeline ARITH.FP_DIVIDER_ACTIVE event=0x14,cmask=1,period=1000003,umask=1  00     assists.any pipeline Number of occurrences where a microcode assist is invoked by hardware event=0xc1,period=100003,umask=7  00    Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists br_inst_retired.all_branches pipeline All branch instructions retired event=0xc4,period=400009  00    Counts all branch instructions retired br_inst_retired.cond pipeline Conditional branch instructions retired event=0xc4,period=400009,umask=0x11  00    Counts conditional branch instructions retired br_inst_retired.cond_ntaken pipeline Not taken branch instructions retired event=0xc4,period=400009,umask=0x10  00    Counts not taken branch instructions retired br_inst_retired.cond_taken pipeline Taken conditional branch instructions retired event=0xc4,period=400009,umask=1  00    Counts taken conditional branch instructions retired br_inst_retired.far_branch pipeline Far branch instructions retired event=0xc4,period=100007,umask=0x40  00    Counts far branch instructions retired br_inst_retired.indirect pipeline Indirect near branch instructions retired (excluding returns) event=0xc4,period=100003,umask=0x80  00    Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch br_inst_retired.near_call pipeline Direct and indirect near call instructions retired event=0xc4,period=100007,umask=2  00    Counts both direct and indirect near call instructions retired br_inst_retired.near_return pipeline Return instructions retired event=0xc4,period=100007,umask=8  00    Counts return instructions retired br_inst_retired.near_taken pipeline Taken branch instructions retired event=0xc4,period=400009,umask=0x20  00    Counts taken branch instructions retired br_misp_retired.all_branches pipeline All mispredicted branch instructions retired event=0xc5,period=50021  00    Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch.  When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path br_misp_retired.cond pipeline Mispredicted conditional branch instructions retired event=0xc5,period=50021,umask=0x11  00    Counts mispredicted conditional branch instructions retired br_misp_retired.cond_ntaken pipeline Mispredicted non-taken conditional branch instructions retired event=0xc5,period=50021,umask=0x10  00    Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken br_misp_retired.cond_taken pipeline number of branch instructions retired that were mispredicted and taken event=0xc5,period=50021,umask=1  00    Counts taken conditional mispredicted branch instructions retired br_misp_retired.indirect pipeline All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch) event=0xc5,period=50021,umask=0x80  00    Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch) br_misp_retired.indirect_call pipeline Mispredicted indirect CALL instructions retired event=0xc5,period=50021,umask=2  00    Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect br_misp_retired.near_taken pipeline Number of near branch instructions retired that were mispredicted and taken event=0xc5,period=50021,umask=0x20  00    Counts number of near branch instructions retired that were mispredicted and taken br_misp_retired.ret pipeline This event counts the number of mispredicted ret instructions retired. Non PEBS event=0xc5,period=50021,umask=8  00    This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired cpu_clk_unhalted.ref_tsc pipeline Reference cycles when the core is not in halt state event=0,period=2000003,umask=3  00    Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case cpu_clk_unhalted.ref_xclk pipeline Core crystal clock cycles when the thread is unhalted event=0x3c,period=25003,umask=1  00    Counts core crystal clock cycles when the thread is unhalted cycle_activity.stalls_mem_any pipeline Execution stalls while memory subsystem has an outstanding load event=0xa3,cmask=20,period=1000003,umask=0x14  00     ild_stall.lcp pipeline Stalls caused by changing prefix length of the instruction. [This event is alias to DECODE.LCP] event=0x87,period=500009,umask=1  00    Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to DECODE.LCP] inst_retired.any pipeline Number of instructions retired. Fixed Counter - architectural event event=0xc0,period=2000003  00    Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter inst_retired.any_p pipeline Number of instructions retired. General Counter - architectural event event=0xc0,period=2000003  00    Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter inst_retired.nop pipeline Number of all retired NOP instructions event=0xc0,period=2000003,umask=2  00     inst_retired.prec_dist pipeline Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution event=0,period=2000003,umask=1  00    A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0 inst_retired.stall_cycles pipeline Cycles without actually retired instructions event=0xc0,cmask=1,inv=1,period=1000003,umask=1  00    This event counts cycles without actually retired instructions int_misc.all_recovery_cycles pipeline Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall event=0xd,cmask=1,period=2000003,umask=3  00    Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall int_misc.clears_count pipeline Clears speculative count event=0xd,cmask=1,edge=1,period=500009,umask=1  00    Counts the number of speculative clears due to any type of branch misprediction or machine clears int_misc.clear_resteer_cycles pipeline Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path event=0xd,period=500009,umask=0x80  00    Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path int_misc.recovery_cycles pipeline Core cycles the allocator was stalled due to recovery from earlier clear event for this thread event=0xd,period=500009,umask=1  00    Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event int_misc.uop_dropping pipeline TMA slots where uops got dropped event=0xd,period=1000003,umask=0x10  00    Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons ld_blocks.no_sr pipeline The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use event=3,period=100003,umask=8  00    Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use ld_blocks_partial.address_alias pipeline False dependencies due to partial compare on address event=7,period=100003,umask=1  00    Counts the number of times a load got blocked due to false dependencies due to partial compare on address load_hit_prefetch.swpf pipeline Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch event=0x4c,period=100003,umask=1  00    Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions lsd.cycles_ok pipeline Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder event=0xa8,cmask=5,period=2000003,umask=1  00    Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector) misc_retired.lbr_inserts pipeline Increments whenever there is an update to the LBR array event=0xcc,period=100003,umask=0x20  00    Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR to be enabled properly misc_retired.pause_inst pipeline Number of retired PAUSE instructions. This event is not supported on first SKL and KBL products event=0xcc,period=100003,umask=0x40  00    Counts number of retired PAUSE instructions. This event is not supported on first SKL and KBL products rs_events.empty_cycles pipeline Cycles when Reservation Station (RS) is empty for the thread event=0x5e,period=1000003,umask=1  00    Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses) rs_events.empty_end pipeline Counts end of periods where the Reservation Station (RS) was empty event=0x5e,cmask=1,edge=1,inv=1,period=100003,umask=1  00    Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events) topdown.backend_bound_slots pipeline TMA slots where no uops were being issued due to lack of back-end resources event=0xa4,period=10000003,umask=2  00    Counts the number of Top-down Microarchitecture Analysis (TMA) method's  slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources uops_decoded.dec0 pipeline Number of uops decoded out of instructions exclusively fetched by decoder 0 event=0x56,period=1000003,umask=1  00    Uops exclusively fetched by decoder 0 uops_dispatched.port_0 pipeline Number of uops executed on port 0 event=0xa1,period=2000003,umask=1  00    Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0 uops_dispatched.port_1 pipeline Number of uops executed on port 1 event=0xa1,period=2000003,umask=2  00    Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1 uops_dispatched.port_2_3 pipeline Number of uops executed on port 2 and 3 event=0xa1,period=2000003,umask=4  00    Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 2 and 3 uops_dispatched.port_4_9 pipeline Number of uops executed on port 4 and 9 event=0xa1,period=2000003,umask=0x10  00    Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9 uops_dispatched.port_5 pipeline Number of uops executed on port 5 event=0xa1,period=2000003,umask=0x20  00    Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5 uops_dispatched.port_6 pipeline Number of uops executed on port 6 event=0xa1,period=2000003,umask=0x40  00    Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6 uops_dispatched.port_7_8 pipeline Number of uops executed on port 7 and 8 event=0xa1,period=2000003,umask=0x80  00    Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 7 and 8 uops_issued.any pipeline Uops that RAT issues to RS event=0xe,period=2000003,umask=1  00    Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS) uops_issued.stall_cycles pipeline Cycles when RAT does not issue Uops to RS for the thread event=0xe,cmask=1,inv=1,period=1000003,umask=1  00    Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread uops_issued.vector_width_mismatch pipeline Uops inserted at issue-stage in order to preserve upper bits of vector registers event=0xe,period=100003,umask=2  00    Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to 'Mixing Intel AVX and Intel SSE Code' section of the Optimization Guide uops_retired.stall_cycles pipeline Cycles without actually retired uops event=0xc2,cmask=1,inv=1,period=1000003,umask=2  00    This event counts cycles without actually retired uops uops_retired.total_cycles pipeline Cycles with less than 10 actually retired uops event=0xc2,cmask=10,inv=1,period=1000003,umask=2  00    Counts the number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event unc_arb_coh_trk_requests.all uncore interconnect Number of entries allocated. Account for Any type: e.g. Snoop,  etc event=0x84,umask=1  01     unc_arb_trk_requests.all uncore interconnect Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic event=0x81,umask=1  01     dtlb_load_misses.stlb_hit virtual memory Loads that miss the DTLB and hit the STLB event=8,period=100003,umask=0x20  00    Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB) dtlb_load_misses.walk_active virtual memory Cycles when at least one PMH is busy with a page walk for a demand load event=8,cmask=1,period=100003,umask=0x10  00    Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load dtlb_load_misses.walk_completed_1g virtual memory Page walks completed due to a demand data load to a 1G page event=8,period=100003,umask=8  00    Counts completed page walks  (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_load_misses.walk_completed_2m_4m virtual memory Page walks completed due to a demand data load to a 2M/4M page event=8,period=100003,umask=4  00    Counts completed page walks  (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_load_misses.walk_completed_4k virtual memory Page walks completed due to a demand data load to a 4K page event=8,period=100003,umask=2  00    Counts completed page walks  (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_load_misses.walk_pending virtual memory Number of page walks outstanding for a demand load in the PMH each cycle event=8,period=100003,umask=0x10  00    Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle dtlb_store_misses.stlb_hit virtual memory Stores that miss the DTLB and hit the STLB event=0x49,period=100003,umask=0x20  00    Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB) dtlb_store_misses.walk_active virtual memory Cycles when at least one PMH is busy with a page walk for a store event=0x49,cmask=1,period=100003,umask=0x10  00    Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store dtlb_store_misses.walk_completed_1g virtual memory Page walks completed due to a demand data store to a 1G page event=0x49,period=100003,umask=8  00    Counts completed page walks  (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_completed_2m_4m virtual memory Page walks completed due to a demand data store to a 2M/4M page event=0x49,period=100003,umask=4  00    Counts completed page walks  (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_completed_4k virtual memory Page walks completed due to a demand data store to a 4K page event=0x49,period=100003,umask=2  00    Counts completed page walks  (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault dtlb_store_misses.walk_pending virtual memory Number of page walks outstanding for a store in the PMH each cycle event=0x49,period=100003,umask=0x10  00    Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle itlb_misses.stlb_hit virtual memory Instruction fetch requests that miss the ITLB and hit the STLB event=0x85,period=100003,umask=0x20  00    Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB) itlb_misses.walk_active virtual memory Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request event=0x85,cmask=1,period=100003,umask=0x10  00    Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request itlb_misses.walk_pending virtual memory Number of page walks outstanding for an outstanding code request in the PMH each cycle event=0x85,period=100003,umask=0x10  00    Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle core_snoop_response.i_fwd_fe cache Hit snoop reply with data, line invalidated event=0xef,period=1000003,umask=0x20  00    Counts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's cache, after the data is forwarded back to the requestor and indicating the data was found unmodified in the (FE) Forward or Exclusive State in this cores caches cache.  A single snoop response from the core counts on all hyperthreads of the core core_snoop_response.i_fwd_m cache HitM snoop reply with data, line invalidated event=0xef,period=1000003,umask=0x10  00    Counts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's caches, after the data is forwarded back to the requestor, and indicating the data was found modified(M) in this cores caches cache (aka HitM response).  A single snoop response from the core counts on all hyperthreads of the core core_snoop_response.i_hit_fse cache Hit snoop reply without sending the data, line invalidated event=0xef,period=1000003,umask=2  00    Counts responses to snoops indicating the line will now be (I)nvalidated in this core's caches without being forwarded back to the requestor. The line was in Forward, Shared or Exclusive (FSE) state in this cores caches.  A single snoop response from the core counts on all hyperthreads of the core core_snoop_response.miss cache Line not found snoop reply event=0xef,period=1000003,umask=1  00    Counts responses to snoops indicating that the data was not found (IHitI) in this core's caches. A single snoop response from the core counts on all hyperthreads of the Core core_snoop_response.s_fwd_fe cache Hit snoop reply with data, line kept in Shared state event=0xef,period=1000003,umask=0x40  00    Counts responses to snoops indicating the line may be kept on this core in the (S)hared state, after the data is forwarded back to the requestor, initially the data was found in the cache in the (FS) Forward or Shared state.  A single snoop response from the core counts on all hyperthreads of the core core_snoop_response.s_fwd_m cache HitM snoop reply with data, line kept in Shared state event=0xef,period=1000003,umask=8  00    Counts responses to snoops indicating the line may be kept on this core in the (S)hared state, after the data is forwarded back to the requestor, initially the data was found in the cache in the (M)odified state.  A single snoop response from the core counts on all hyperthreads of the core core_snoop_response.s_hit_fse cache Hit snoop reply without sending the data, line kept in Shared state event=0xef,period=1000003,umask=4  00    Counts responses to snoops indicating the line was kept on this core in the (S)hared state, and that the data was found unmodified but not forwarded back to the requestor, initially the data was found in the cache in the (FSE) Forward, Shared state or Exclusive state.  A single snoop response from the core counts on all hyperthreads of the core l2_lines_out.non_silent cache Cache lines that are evicted by L2 cache when triggered by an L2 cache fill event=0xf2,period=200003,umask=2  00    Counts the number of lines that are evicted by the L2 cache due to L2 cache fills.  Evicted lines are delivered to the L3, which may or may not cache them, according to system load and priorities mem_load_l3_hit_retired.xsnp_fwd cache Retired load instructions whose data sources were HitM responses from shared L3  Supports address when precise event=0xd2,period=20011,umask=4  00    Counts retired load instructions whose data sources were HitM responses from shared L3  Supports address when precise mem_load_l3_hit_retired.xsnp_hit cache This event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD  Supports address when precise event=0xd2,period=20011,umask=2  10     mem_load_l3_hit_retired.xsnp_hitm cache This event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD  Supports address when precise event=0xd2,period=20011,umask=4  10     mem_load_l3_hit_retired.xsnp_no_fwd cache Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache  Supports address when precise event=0xd2,period=20011,umask=2  00    Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache  Supports address when precise mem_load_l3_miss_retired.local_dram cache Retired load instructions which data sources missed L3 but serviced from local dram  Supports address when precise event=0xd3,period=100007,umask=1  00    Retired load instructions which data sources missed L3 but serviced from local DRAM  Supports address when precise mem_load_l3_miss_retired.remote_dram cache Retired load instructions which data sources missed L3 but serviced from remote dram  Supports address when precise event=0xd3,period=100007,umask=2  00     mem_load_l3_miss_retired.remote_hitm cache Retired load instructions whose data sources was remote HITM  Supports address when precise event=0xd3,period=100007,umask=4  00     mem_load_l3_miss_retired.remote_pmm cache Retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches  Supports address when precise event=0xd3,period=100007,umask=0x10  00    Counts retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode)  Supports address when precise mem_load_retired.local_pmm cache Retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches  Supports address when precise event=0xd1,period=100003,umask=0x80  00    Counts retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode)  Supports address when precise ocr.demand_code_rd.l3_hit cache Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0004  00     ocr.demand_code_rd.l3_hit.snoop_hitm cache Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0004  00     ocr.demand_code_rd.snc_cache.hitm cache Counts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=1,offcore_rsp=0x1008000004  00     ocr.demand_code_rd.snc_cache.hit_with_fwd cache Counts demand instruction fetches and L1 instruction cache prefetches that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=1,offcore_rsp=0x808000004  00     ocr.demand_data_rd.l3_hit cache Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0001  00     ocr.demand_data_rd.l3_hit.snoop_hitm cache Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0001  00     ocr.demand_data_rd.l3_hit.snoop_hit_no_fwd cache Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0001  00     ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd cache Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0001  00     ocr.demand_data_rd.local_pmm cache Counts demand data reads that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster event=0xb7,period=100003,umask=1,offcore_rsp=0x100400001  00     ocr.demand_data_rd.pmm cache Counts demand data reads that were supplied by PMM event=0xb7,period=100003,umask=1,offcore_rsp=0x703C00001  00     ocr.demand_data_rd.remote_cache.snoop_hitm cache Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data event=0xb7,period=100003,umask=1,offcore_rsp=0x1030000001  00     ocr.demand_data_rd.remote_cache.snoop_hit_with_fwd cache Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core event=0xb7,period=100003,umask=1,offcore_rsp=0x830000001  00     ocr.demand_data_rd.remote_pmm cache Counts demand data reads that were supplied by PMM attached to another socket event=0xb7,period=100003,umask=1,offcore_rsp=0x703000001  00     ocr.demand_data_rd.snc_cache.hitm cache Counts demand data reads that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=1,offcore_rsp=0x1008000001  00     ocr.demand_data_rd.snc_cache.hit_with_fwd cache Counts demand data reads that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=1,offcore_rsp=0x808000001  00     ocr.demand_data_rd.snc_pmm cache Counts demand data reads that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=1,offcore_rsp=0x700800001  00     ocr.demand_rfo.any_response cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x3F3FFC0002  00     ocr.demand_rfo.l3_hit cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0002  00     ocr.demand_rfo.l3_hit.snoop_hitm cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0002  00     ocr.demand_rfo.local_pmm cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster event=0xb7,period=100003,umask=1,offcore_rsp=0x100400002  00     ocr.demand_rfo.pmm cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM event=0xb7,period=100003,umask=1,offcore_rsp=0x703C00002  00     ocr.demand_rfo.remote_pmm cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to another socket event=0xb7,period=100003,umask=1,offcore_rsp=0x703000002  00     ocr.demand_rfo.snc_cache.hitm cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=1,offcore_rsp=0x1008000002  00     ocr.demand_rfo.snc_cache.hit_with_fwd cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=1,offcore_rsp=0x808000002  00     ocr.demand_rfo.snc_pmm cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=1,offcore_rsp=0x700800002  00     ocr.hwpf_l1d_and_swpf.l3_hit cache Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0400  00     ocr.hwpf_l2.any_response cache Counts hardware prefetch (which bring data to L2) that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10070  00     ocr.hwpf_l3.any_response cache Counts hardware prefetches to the L3 only that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x12380  00     ocr.hwpf_l3.l3_hit cache Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket event=0xb7,period=100003,umask=1,offcore_rsp=0x80082380  00     ocr.hwpf_l3.remote cache Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket event=0xb7,period=100003,umask=1,offcore_rsp=0x90002380  00     ocr.itom.remote cache Counts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket event=0xb7,period=100003,umask=1,offcore_rsp=0x90000002  00     ocr.prefetches.l3_hit cache Counts hardware and software prefetches to all cache levels that hit in the L3 or were snooped from another core's caches on the same socket event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C27F0  00     ocr.reads_to_core.any_response cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x3F3FFC0477  00     ocr.reads_to_core.l3_hit cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket event=0xb7,period=100003,umask=1,offcore_rsp=0x3F003C0477  00     ocr.reads_to_core.l3_hit.snoop_hitm cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0477  00     ocr.reads_to_core.l3_hit.snoop_hit_no_fwd cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0477  00     ocr.reads_to_core.l3_hit.snoop_hit_with_fwd cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0477  00     ocr.reads_to_core.local_pmm cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster event=0xb7,period=100003,umask=1,offcore_rsp=0x100400477  00     ocr.reads_to_core.local_socket_pmm cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster event=0xb7,period=100003,umask=1,offcore_rsp=0x700C00477  00     ocr.reads_to_core.remote cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socket event=0xb7,period=100003,umask=1,offcore_rsp=0x3F33000477  00     ocr.reads_to_core.remote_cache.snoop_fwd cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified) event=0xb7,period=100003,umask=1,offcore_rsp=0x1830000477  00     ocr.reads_to_core.remote_cache.snoop_hitm cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data event=0xb7,period=100003,umask=1,offcore_rsp=0x1030000477  00     ocr.reads_to_core.remote_cache.snoop_hit_with_fwd cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core event=0xb7,period=100003,umask=1,offcore_rsp=0x830000477  00     ocr.reads_to_core.remote_pmm cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to another socket event=0xb7,period=100003,umask=1,offcore_rsp=0x703000477  00     ocr.reads_to_core.snc_cache.hitm cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=1,offcore_rsp=0x1008000477  00     ocr.reads_to_core.snc_cache.hit_with_fwd cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=1,offcore_rsp=0x808000477  00     ocr.reads_to_core.snc_pmm cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=1,offcore_rsp=0x700800477  00     ocr.streaming_wr.l3_hit cache Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket event=0xb7,period=100003,umask=1,offcore_rsp=0x80080800  00     offcore_requests.demand_code_rd cache Counts cacheable and non-cacheable code reads to the core event=0xb0,period=100003,umask=2  00    Counts both cacheable and non-cacheable code reads to the core offcore_requests_outstanding.demand_code_rd cache For every cycle, increments by the number of outstanding code read requests pending event=0x60,period=1000003,umask=2  00    For every cycle, increments by the number of outstanding code read requests pending.  Code Read requests include both cacheable and non-cacheable Code Reads.   Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor ocr.demand_code_rd.dram memory Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x73C000004  00     ocr.demand_code_rd.l3_miss memory Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00004  00     ocr.demand_code_rd.l3_miss_local memory Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84400004  00     ocr.demand_code_rd.local_dram memory Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster event=0xb7,period=100003,umask=1,offcore_rsp=0x104000004  00     ocr.demand_code_rd.snc_dram memory Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=1,offcore_rsp=0x708000004  00     ocr.demand_data_rd.dram memory Counts demand data reads that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x73C000001  00     ocr.demand_data_rd.l3_miss memory Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00001  00     ocr.demand_data_rd.l3_miss_local memory Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84400001  00     ocr.demand_data_rd.local_dram memory Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster event=0xb7,period=100003,umask=1,offcore_rsp=0x104000001  00     ocr.demand_data_rd.remote_dram memory Counts demand data reads that were supplied by DRAM attached to another socket event=0xb7,period=100003,umask=1,offcore_rsp=0x730000001  00     ocr.demand_data_rd.snc_dram memory Counts demand data reads that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=1,offcore_rsp=0x708000001  00     ocr.demand_rfo.dram memory Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x73C000002  00     ocr.demand_rfo.l3_miss memory Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches event=0xb7,period=100003,umask=1,offcore_rsp=0x3F3FC00002  00     ocr.demand_rfo.l3_miss_local memory Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket event=0xb7,period=100003,umask=1,offcore_rsp=0x3F04400002  00     ocr.demand_rfo.local_dram memory Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster event=0xb7,period=100003,umask=1,offcore_rsp=0x104000002  00     ocr.demand_rfo.snc_dram memory Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=1,offcore_rsp=0x708000002  00     ocr.hwpf_l1d_and_swpf.dram memory Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x73C000400  00     ocr.hwpf_l1d_and_swpf.l3_miss memory Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00400  00     ocr.hwpf_l1d_and_swpf.l3_miss_local memory Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84400400  00     ocr.hwpf_l1d_and_swpf.local_dram memory Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster event=0xb7,period=100003,umask=1,offcore_rsp=0x104000400  00     ocr.hwpf_l3.l3_miss memory Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches event=0xb7,period=100003,umask=1,offcore_rsp=0x94002380  00     ocr.hwpf_l3.l3_miss_local memory Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0xb7,period=100003,umask=1,offcore_rsp=0x84002380  00     ocr.itom.l3_miss_local memory Counts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0xb7,period=100003,umask=1,offcore_rsp=0x84000002  00     ocr.other.l3_miss memory Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC08000  00     ocr.other.l3_miss_local memory Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0xb7,period=100003,umask=1,offcore_rsp=0x3F84408000  00     ocr.prefetches.l3_miss_local memory Counts hardware and software prefetches to all cache levels that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0xb7,period=100003,umask=1,offcore_rsp=0x3F844027F0  00     ocr.reads_to_core.dram memory Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x73C000477  00     ocr.reads_to_core.l3_miss memory Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches event=0xb7,period=100003,umask=1,offcore_rsp=0x3F3FC00477  00     ocr.reads_to_core.l3_miss_local memory Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket event=0xb7,period=100003,umask=1,offcore_rsp=0x3F04400477  00     ocr.reads_to_core.l3_miss_local_socket memory Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster event=0xb7,period=100003,umask=1,offcore_rsp=0x70CC00477  00     ocr.reads_to_core.local_dram memory Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster event=0xb7,period=100003,umask=1,offcore_rsp=0x104000477  00     ocr.reads_to_core.local_socket_dram memory Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster event=0xb7,period=100003,umask=1,offcore_rsp=0x70C000477  00     ocr.reads_to_core.remote_dram memory Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket event=0xb7,period=100003,umask=1,offcore_rsp=0x730000477  00     ocr.reads_to_core.remote_memory memory Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or PMM attached to another socket event=0xb7,period=100003,umask=1,offcore_rsp=0x731800477  00     ocr.reads_to_core.snc_dram memory Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=1,offcore_rsp=0x708000477  00     ocr.streaming_wr.l3_miss memory Counts streaming stores that missed the local socket's L1, L2, and L3 caches event=0xb7,period=100003,umask=1,offcore_rsp=0x94000800  00     ocr.streaming_wr.l3_miss_local memory Counts streaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0xb7,period=100003,umask=1,offcore_rsp=0x84000800  00     ocr.write_estimate.memory memory Counts Demand RFOs, ItoM's, PREFECTHW's, Hardware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted in a store to Memory (DRAM or PMM) event=0xb7,period=100003,umask=1,offcore_rsp=0xFBFF80822  00     offcore_requests_outstanding.l3_miss_demand_data_rd memory This event is deprecated event=0x60,period=2000003,umask=0x10  10     offcore_requests_outstanding.l3_miss_demand_data_rd_ge_6 memory Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache event=0x60,cmask=6,period=2000003,umask=0x10  00    Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache.  Note that this event does not capture all elapsed cycles while the requests are outstanding - only cycles from when the requests were known to have missed the L3 cache br_misp_retired.indirect_call pipeline Mispredicted indirect CALL instructions retired event=0xc5,period=50021,umask=2  00    Counts retired mispredicted indirect (near taken) calls, including both register and memory indirect unc_cha_2lm_nm_invitox.local uncore cache This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL event=0x65,umask=1  11     unc_cha_2lm_nm_invitox.remote uncore cache This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE event=0x65,umask=2  11     unc_cha_2lm_nm_invitox.setconflict uncore cache This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT event=0x65,umask=4  11     unc_cha_2lm_nm_setconflicts.llc uncore cache This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC event=0x64,umask=2  11     unc_cha_2lm_nm_setconflicts.sf uncore cache This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF event=0x64,umask=1  11     unc_cha_2lm_nm_setconflicts.tor uncore cache This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR event=0x64,umask=4  11     unc_cha_2lm_nm_setconflicts2.memwr uncore cache This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR event=0x70,umask=2  11     unc_cha_2lm_nm_setconflicts2.memwrni uncore cache This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI event=0x70,umask=4  11     unc_cha_ag0_ad_crd_acquired0.tgr0 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 0 event=0x80,umask=1  01    CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired0.tgr1 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 1 event=0x80,umask=2  01    CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired0.tgr2 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 2 event=0x80,umask=4  01    CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired0.tgr3 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 3 event=0x80,umask=8  01    CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired0.tgr4 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 4 event=0x80,umask=0x10  01    CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired0.tgr5 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 5 event=0x80,umask=0x20  01    CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired0.tgr6 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 6 event=0x80,umask=0x40  01    CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired0.tgr7 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 7 event=0x80,umask=0x80  01    CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired1.tgr10 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 10 event=0x81,umask=4  01    CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired1.tgr8 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 8 event=0x81,umask=1  01    CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_acquired1.tgr9 uncore cache CMS Agent0 AD Credits Acquired : For Transgress 9 event=0x81,umask=2  01    CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy0.tgr0 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 0 event=0x82,umask=1  01    CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy0.tgr1 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 1 event=0x82,umask=2  01    CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy0.tgr2 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 2 event=0x82,umask=4  01    CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy0.tgr3 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 3 event=0x82,umask=8  01    CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy0.tgr4 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 4 event=0x82,umask=0x10  01    CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy0.tgr5 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 5 event=0x82,umask=0x20  01    CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy0.tgr6 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 6 event=0x82,umask=0x40  01    CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy0.tgr7 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 7 event=0x82,umask=0x80  01    CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy1.tgr10 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 10 event=0x83,umask=4  01    CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy1.tgr8 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 8 event=0x83,umask=1  01    CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_ad_crd_occupancy1.tgr9 uncore cache CMS Agent0 AD Credits Occupancy : For Transgress 9 event=0x83,umask=2  01    CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired0.tgr0 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 0 event=0x88,umask=1  01    CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired0.tgr1 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 1 event=0x88,umask=2  01    CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired0.tgr2 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 2 event=0x88,umask=4  01    CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired0.tgr3 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 3 event=0x88,umask=8  01    CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired0.tgr4 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 4 event=0x88,umask=0x10  01    CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired0.tgr5 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 5 event=0x88,umask=0x20  01    CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired0.tgr6 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 6 event=0x88,umask=0x40  01    CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired0.tgr7 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 7 event=0x88,umask=0x80  01    CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired1.tgr10 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 10 event=0x89,umask=4  01    CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired1.tgr8 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 8 event=0x89,umask=1  01    CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_acquired1.tgr9 uncore cache CMS Agent0 BL Credits Acquired : For Transgress 9 event=0x89,umask=2  01    CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy0.tgr0 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 0 event=0x8a,umask=1  01    CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy0.tgr1 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 1 event=0x8a,umask=2  01    CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy0.tgr2 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 2 event=0x8a,umask=4  01    CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy0.tgr3 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 3 event=0x8a,umask=8  01    CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy0.tgr4 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 4 event=0x8a,umask=0x10  01    CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy0.tgr5 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 5 event=0x8a,umask=0x20  01    CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy0.tgr6 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 6 event=0x8a,umask=0x40  01    CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy0.tgr7 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 7 event=0x8a,umask=0x80  01    CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy1.tgr10 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 10 event=0x8b,umask=4  01    CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy1.tgr8 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 8 event=0x8b,umask=1  01    CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag0_bl_crd_occupancy1.tgr9 uncore cache CMS Agent0 BL Credits Occupancy : For Transgress 9 event=0x8b,umask=2  01    CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired0.tgr0 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 0 event=0x84,umask=1  01    CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired0.tgr1 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 1 event=0x84,umask=2  01    CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired0.tgr2 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 2 event=0x84,umask=4  01    CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired0.tgr3 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 3 event=0x84,umask=8  01    CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired0.tgr4 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 4 event=0x84,umask=0x10  01    CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired0.tgr5 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 5 event=0x84,umask=0x20  01    CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired0.tgr6 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 6 event=0x84,umask=0x40  01    CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired0.tgr7 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 7 event=0x84,umask=0x80  01    CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired1.tgr10 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 10 event=0x85,umask=4  01    CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired1.tgr8 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 8 event=0x85,umask=1  01    CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_acquired1.tgr9 uncore cache CMS Agent1 AD Credits Acquired : For Transgress 9 event=0x85,umask=2  01    CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy0.tgr0 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 0 event=0x86,umask=1  01    CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy0.tgr1 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 1 event=0x86,umask=2  01    CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy0.tgr2 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 2 event=0x86,umask=4  01    CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy0.tgr3 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 3 event=0x86,umask=8  01    CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy0.tgr4 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 4 event=0x86,umask=0x10  01    CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy0.tgr5 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 5 event=0x86,umask=0x20  01    CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy0.tgr6 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 6 event=0x86,umask=0x40  01    CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy0.tgr7 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 7 event=0x86,umask=0x80  01    CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy1.tgr10 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 10 event=0x87,umask=4  01    CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy1.tgr8 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 8 event=0x87,umask=1  01    CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_ad_crd_occupancy1.tgr9 uncore cache CMS Agent1 AD Credits Occupancy : For Transgress 9 event=0x87,umask=2  01    CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired0.tgr0 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 0 event=0x8c,umask=1  01    CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired0.tgr1 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 1 event=0x8c,umask=2  01    CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired0.tgr2 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 2 event=0x8c,umask=4  01    CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired0.tgr3 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 3 event=0x8c,umask=8  01    CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired0.tgr4 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 4 event=0x8c,umask=0x10  01    CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired0.tgr5 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 5 event=0x8c,umask=0x20  01    CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired0.tgr6 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 4 event=0x8c,umask=0x40  01    CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired0.tgr7 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 5 event=0x8c,umask=0x80  01    CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired1.tgr10 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 10 event=0x8d,umask=4  01    CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired1.tgr8 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 8 event=0x8d,umask=1  01    CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_acquired1.tgr9 uncore cache CMS Agent1 BL Credits Acquired : For Transgress 9 event=0x8d,umask=2  01    CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy0.tgr0 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 0 event=0x8e,umask=1  01    CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy0.tgr1 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 1 event=0x8e,umask=2  01    CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy0.tgr2 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 2 event=0x8e,umask=4  01    CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy0.tgr3 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 3 event=0x8e,umask=8  01    CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy0.tgr4 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 4 event=0x8e,umask=0x10  01    CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy0.tgr5 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 5 event=0x8e,umask=0x20  01    CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy0.tgr6 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 6 event=0x8e,umask=0x40  01    CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy0.tgr7 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 7 event=0x8e,umask=0x80  01    CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy1.tgr10 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 10 event=0x8f,umask=4  01    CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy1.tgr8 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 8 event=0x8f,umask=1  01    CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_ag1_bl_crd_occupancy1.tgr9 uncore cache CMS Agent1 BL Credits Occupancy : For Transgress 9 event=0x8f,umask=2  01    CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_cha_clockticks uncore cache Clockticks of the uncore caching and home agent (CHA) event=0  01     unc_cha_counter0_occupancy uncore cache Counter 0 Occupancy event=0x1f  01    Counter 0 Occupancy : Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0.   The filtering available is found in the control register - threshold, invert and edge detect.   E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry unc_cha_dir_lookup.no_snp uncore cache Multi-socket cacheline directory state lookups : Snoop Not Needed event=0x53,umask=2  01    Multi-socket cacheline directory state lookups : Snoop Not Needed : Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to. : Filters for transactions that did not have to send any snoops because the directory was clean unc_cha_dir_lookup.snp uncore cache Multi-socket cacheline directory state lookups : Snoop Needed event=0x53,umask=1  01    Multi-socket cacheline directory state lookups : Snoop Needed : Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to. : Filters for transactions that had to send one or more snoops because the directory was not clean unc_cha_dir_update.ha uncore cache Multi-socket cacheline directory state updates; memory write due to directory update from the home agent (HA) pipe event=0x54,umask=1  01    Counts only multi-socket cacheline directory state updates memory writes issued from the home agent (HA) pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines unc_cha_dir_update.tor uncore cache Multi-socket cacheline directory state updates; memory write due to directory update from (table of requests) TOR pipe event=0x54,umask=2  01    Counts only multi-socket cacheline directory state updates due to memory writes issued from the table of requests (TOR) pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines unc_cha_distress_asserted.dpt_local uncore cache Distress signal asserted : DPT Local event=0xaf,umask=4  01    Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile unc_cha_distress_asserted.dpt_stall_iv uncore cache Distress signal asserted : DPT Stalled - IV event=0xaf,umask=0x40  01    Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled unc_cha_distress_asserted.dpt_stall_nocrd uncore cache Distress signal asserted : DPT Stalled -  No Credit event=0xaf,umask=0x80  01    Distress signal asserted : DPT Stalled -  No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled unc_cha_distress_asserted.horz uncore cache Distress signal asserted : Horizontal event=0xaf,umask=2  01    Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions unc_cha_distress_asserted.pmm_local uncore cache Distress signal asserted : PMM Local event=0xaf,umask=0x10  01    Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic unc_cha_distress_asserted.pmm_nonlocal uncore cache Distress signal asserted : PMM Remote event=0xaf,umask=0x20  01    Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic unc_cha_distress_asserted.vert uncore cache Distress signal asserted : Vertical event=0xaf,umask=1  01    Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions unc_cha_hitme_hit.shared_ownreq uncore cache Counts Number of Hits in HitMe Cache : Remote socket ownership read requests that hit in S state event=0x5f,umask=4  01    Counts Number of Hits in HitMe Cache : Remote socket ownership read requests that hit in S state. : Shared hit and op is RdInvOwn, RdInv, Inv* unc_cha_hitme_hit.wbmtoe uncore cache Counts Number of Hits in HitMe Cache : Remote socket WBMtoE requests event=0x5f,umask=8  01     unc_cha_hitme_hit.wbmtoi_or_s uncore cache Counts Number of Hits in HitMe Cache : Remote socket writeback to I or S requests event=0x5f,umask=0x10  01    Counts Number of Hits in HitMe Cache : Remote socket writeback to I or S requests : op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoS unc_cha_hitme_lookup.read uncore cache Counts Number of times HitMe Cache is accessed : Remote socket read requests event=0x5e,umask=1  01    Counts Number of times HitMe Cache is accessed : Remote socket read requests : op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv* unc_cha_hitme_lookup.write uncore cache Counts Number of times HitMe Cache is accessed : Remote socket write (i.e. writeback) requests event=0x5e,umask=2  01    Counts Number of times HitMe Cache is accessed : Remote socket write (i.e. writeback) requests : op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS unc_cha_hitme_miss.notshared_rdinvown uncore cache Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests that are not to shared line event=0x60,umask=0x40  01    Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests that are not to shared line : No SF/LLC HitS/F and op is RdInvOwn unc_cha_hitme_miss.read_or_inv uncore cache Counts Number of Misses in HitMe Cache : Remote socket read or invalidate requests event=0x60,umask=0x80  01    Counts Number of Misses in HitMe Cache : Remote socket read or invalidate requests : op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv* unc_cha_hitme_miss.shared_rdinvown uncore cache Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests to shared line event=0x60,umask=0x20  01    Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests to shared line : SF/LLC HitS/F and op is RdInvOwn unc_cha_horz_ring_ad_in_use.left_even uncore cache Horizontal AD Ring In Use : Left and Even event=0xb6,umask=1  01    Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ad_in_use.left_odd uncore cache Horizontal AD Ring In Use : Left and Odd event=0xb6,umask=2  01    Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ad_in_use.right_even uncore cache Horizontal AD Ring In Use : Right and Even event=0xb6,umask=4  01    Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ad_in_use.right_odd uncore cache Horizontal AD Ring In Use : Right and Odd event=0xb6,umask=8  01    Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_akc_in_use.left_even uncore cache Horizontal AK Ring In Use : Left and Even event=0xbb,umask=1  01    Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_akc_in_use.left_odd uncore cache Horizontal AK Ring In Use : Left and Odd event=0xbb,umask=2  01    Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_akc_in_use.right_even uncore cache Horizontal AK Ring In Use : Right and Even event=0xbb,umask=4  01    Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_akc_in_use.right_odd uncore cache Horizontal AK Ring In Use : Right and Odd event=0xbb,umask=8  01    Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ak_in_use.left_even uncore cache Horizontal AK Ring In Use : Left and Even event=0xb7,umask=1  01    Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ak_in_use.left_odd uncore cache Horizontal AK Ring In Use : Left and Odd event=0xb7,umask=2  01    Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ak_in_use.right_even uncore cache Horizontal AK Ring In Use : Right and Even event=0xb7,umask=4  01    Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_ak_in_use.right_odd uncore cache Horizontal AK Ring In Use : Right and Odd event=0xb7,umask=8  01    Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_bl_in_use.left_even uncore cache Horizontal BL Ring in Use : Left and Even event=0xb8,umask=1  01    Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_bl_in_use.left_odd uncore cache Horizontal BL Ring in Use : Left and Odd event=0xb8,umask=2  01    Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_bl_in_use.right_even uncore cache Horizontal BL Ring in Use : Right and Even event=0xb8,umask=4  01    Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_bl_in_use.right_odd uncore cache Horizontal BL Ring in Use : Right and Odd event=0xb8,umask=8  01    Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_horz_ring_iv_in_use.left uncore cache Horizontal IV Ring in Use : Left event=0xb9,umask=1  01    Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_cha_horz_ring_iv_in_use.right uncore cache Horizontal IV Ring in Use : Right event=0xb9,umask=4  01    Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_cha_imc_writes_count.full uncore cache CHA to iMC Full Line Writes Issued : Full Line Non-ISOCH event=0x5b,umask=1  01    Counts when a normal (Non-Isochronous) full line write is issued from the CHA to any of the memory controller channels unc_cha_llc_lookup.all_remote uncore cache Cache Lookups : All transactions from Remote Agents event=0x34,umask=0x1e20ff  01    Cache Lookups : All transactions from Remote Agents : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing unc_cha_llc_lookup.any_f uncore cache Cache Lookups : All Request Filter event=0x34  01    Cache Lookups : All Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Any local or remote transaction to the LLC, including prefetch unc_cha_llc_lookup.code uncore cache This event is deprecated event=0x34,umask=0x1bd0ff  11     unc_cha_llc_lookup.code_local uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ_LOCAL event=0x34,umask=0x19d0ff  11     unc_cha_llc_lookup.code_read uncore cache Cache Lookups : Code Reads event=0x34,umask=0x1bd0ff  01    Cache Lookups : Code Reads : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing unc_cha_llc_lookup.code_read_f uncore cache Cache Lookups : CRd Request Filter event=0x34  01    Cache Lookups : CRd Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC.  This includes CRd prefetch unc_cha_llc_lookup.code_read_local uncore cache Cache Lookups : CRd Requests that come from the local socket (usually the core) event=0x34,umask=0x19d0ff  01    Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC.  This includes CRd prefetch unc_cha_llc_lookup.code_read_miss uncore cache Cache Lookups : Code Read Misses event=0x34,umask=0x1bd001  01    Cache Lookups : Code Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing unc_cha_llc_lookup.code_read_remote uncore cache Cache Lookups : CRd Requests that come from a Remote socket event=0x34,umask=0x1a10ff  01    Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC.  This includes CRd prefetch unc_cha_llc_lookup.code_remote uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ_REMOTE event=0x34,umask=0x1a10ff  11     unc_cha_llc_lookup.corepref_or_dmnd_local_f uncore cache Cache Lookups : Local request Filter event=0x34  01    Cache Lookups : Local request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Any local transaction to the LLC, including prefetches from the Core unc_cha_llc_lookup.data_rd uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ event=0x34,umask=0x1bc1ff  11     unc_cha_llc_lookup.data_read uncore cache Cache and Snoop Filter Lookups; Data Read Request event=0x34,umask=0x1bc1ff  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.data_read_all uncore cache This event is deprecated event=0x34,umask=0x1fc1ff  11     unc_cha_llc_lookup.data_read_f uncore cache Cache Lookups : Data Read Request Filter event=0x34  01    Cache Lookups : Data Read Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Read transactions unc_cha_llc_lookup.data_read_local uncore cache Cache and Snoop Filter Lookups; Data Read Request that come from the local socket (usually the core) event=0x34,umask=0x19c1ff  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.data_read_miss uncore cache Cache Lookups : Data Read Misses event=0x34,umask=0x1bc101  01    Cache Lookups : Data Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing unc_cha_llc_lookup.data_read_remote uncore cache Cache and Snoop Filter Lookups; Data Read Requests that come from a Remote socket event=0x34,umask=0x1a01ff  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.dmnd_read_local uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL event=0x34,umask=0x841ff  11     unc_cha_llc_lookup.e uncore cache Cache Lookups : E State event=0x34,umask=0x20  01    Cache Lookups : E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Hit Exclusive State unc_cha_llc_lookup.f uncore cache Cache Lookups : F State event=0x34,umask=0x80  01    Cache Lookups : F State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Hit Forward State unc_cha_llc_lookup.flush_inv_local uncore cache Cache Lookups : Flush or Invalidate Requests that come from the local socket (usually the core) event=0x34,umask=0x1844ff  01    Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing unc_cha_llc_lookup.flush_inv_remote uncore cache Cache Lookups : Flush or Invalidate requests that come from a Remote socket event=0x34,umask=0x1a04ff  01    Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing unc_cha_llc_lookup.flush_or_inv_f uncore cache Cache Lookups : Flush or Invalidate Filter event=0x34  01    Cache Lookups : Flush or Invalidate Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing unc_cha_llc_lookup.i uncore cache Cache Lookups : I State event=0x34,umask=1  01    Cache Lookups : I State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Miss unc_cha_llc_lookup.llcpref_local uncore cache Cache and Snoop Filter Lookups; Prefetch requests to the LLC that come from the local socket (usually the core) event=0x34,umask=0x189dff  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_llc_lookup.llcpref_local_f uncore cache Cache Lookups : Local LLC prefetch requests (from LLC) Filter event=0x34  01    Cache Lookups : Local LLC prefetch requests (from LLC) Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Any local LLC prefetch to the LLC unc_cha_llc_lookup.llc_pf_local uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL event=0x34,umask=0x189dff  11     unc_cha_llc_lookup.locally_homed_address uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LOC_HOM event=0x34,umask=0xbdfff  11     unc_cha_llc_lookup.local_f uncore cache Cache Lookups : Transactions homed locally Filter event=0x34  01    Cache Lookups : Transactions homed locally Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Transaction whose address resides in the local MC unc_cha_llc_lookup.loc_hom uncore cache Cache Lookups : Transactions homed locally event=0x34,umask=0xbdfff  01    Cache Lookups : Transactions homed locally : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Transaction whose address resides in the local MC unc_cha_llc_lookup.m uncore cache Cache Lookups : M State event=0x34,umask=0x40  01    Cache Lookups : M State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Hit Modified State unc_cha_llc_lookup.miss_all uncore cache Cache Lookups : All Misses event=0x34,umask=0x1fe001  01    Cache Lookups : All Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing unc_cha_llc_lookup.other_req_f uncore cache Cache Lookups : Write Request Filter event=0x34  01    Cache Lookups : Write Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Writeback transactions to the LLC  This includes all write transactions -- both Cacheable and UC unc_cha_llc_lookup.pref_or_dmnd_remote_f uncore cache Cache Lookups : Remote non-snoop request Filter event=0x34  01    Cache Lookups : Remote non-snoop request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Non-snoop transactions to the LLC from remote agent unc_cha_llc_lookup.read uncore cache Cache Lookups : Reads event=0x34,umask=0x1bd9ff  01    Cache Lookups : Reads : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing unc_cha_llc_lookup.read_local_loc_hom uncore cache Cache Lookups : Locally Requested Reads that are Locally HOMed event=0x34,umask=0x9d9ff  01    Cache Lookups : Locally Requested Reads that are Locally HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing unc_cha_llc_lookup.read_local_rem_hom uncore cache Cache Lookups : Locally Requested Reads that are Remotely HOMed event=0x34,umask=0x11d9ff  01    Cache Lookups : Locally Requested Reads that are Remotely HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing unc_cha_llc_lookup.read_miss uncore cache Cache Lookups : Read Misses event=0x34,umask=0x1bd901  01    Cache Lookups : Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing unc_cha_llc_lookup.read_miss_loc_hom uncore cache Cache Lookups : Locally HOMed Read Misses event=0x34,umask=0xbd901  01    Cache Lookups : Locally HOMed Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing unc_cha_llc_lookup.read_miss_rem_hom uncore cache Cache Lookups : Remotely HOMed Read Misses event=0x34,umask=0x13d901  01    Cache Lookups : Remotely HOMed Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing unc_cha_llc_lookup.read_or_snoop_remote_miss_rem_hom uncore cache Cache Lookups : Remotely requested Read or Snoop Misses that are Remotely HOMed event=0x34,umask=0x161901  01    Cache Lookups : Remotely requested Read or Snoop Misses that are Remotely HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing unc_cha_llc_lookup.read_remote_loc_hom uncore cache Cache Lookups : Remotely Requested Reads that are Locally HOMed event=0x34,umask=0xa19ff  01    Cache Lookups : Remotely Requested Reads that are Locally HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing unc_cha_llc_lookup.read_sf_hit uncore cache Cache Lookups : Reads that Hit the Snoop Filter event=0x34,umask=0x1bd90e  01    Cache Lookups : Reads that Hit the Snoop Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing unc_cha_llc_lookup.remotely_homed_address uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REM_HOM event=0x34,umask=0x15dfff  11     unc_cha_llc_lookup.remote_f uncore cache Cache Lookups : Transactions homed remotely Filter event=0x34  01    Cache Lookups : Transactions homed remotely Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Transaction whose address resides in a remote MC unc_cha_llc_lookup.remote_snoop_f uncore cache Cache Lookups : Remote snoop request Filter event=0x34  01    Cache Lookups : Remote snoop request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Snoop transactions to the LLC from remote agent unc_cha_llc_lookup.rem_hom uncore cache Cache Lookups : Transactions homed remotely event=0x34,umask=0x15dfff  01    Cache Lookups : Transactions homed remotely : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Transaction whose address resides in a remote MC unc_cha_llc_lookup.rfo_f uncore cache Cache Lookups : RFO Request Filter event=0x34  01    Cache Lookups : RFO Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC.  This includes RFO prefetch unc_cha_llc_lookup.rfo_local uncore cache Cache Lookups : RFO Requests that come from the local socket (usually the core) event=0x34,umask=0x19c8ff  01    Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC.  This includes RFO prefetch unc_cha_llc_lookup.rfo_miss uncore cache Cache Lookups : RFO Misses event=0x34,umask=0x1bc801  01    Cache Lookups : RFO Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing unc_cha_llc_lookup.rfo_pref_local uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.RFO_LOCAL event=0x34,umask=0x888ff  11     unc_cha_llc_lookup.rfo_remote uncore cache Cache Lookups : RFO Requests that come from a Remote socket event=0x34,umask=0x1a08ff  01    Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC.  This includes RFO prefetch unc_cha_llc_lookup.s uncore cache Cache Lookups : S State event=0x34,umask=0x10  01    Cache Lookups : S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Hit Shared State unc_cha_llc_lookup.sf_e uncore cache Cache Lookups : SnoopFilter - E State event=0x34,umask=4  01    Cache Lookups : SnoopFilter - E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : SF Hit Exclusive State unc_cha_llc_lookup.sf_h uncore cache Cache Lookups : SnoopFilter - H State event=0x34,umask=8  01    Cache Lookups : SnoopFilter - H State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : SF Hit HitMe State unc_cha_llc_lookup.sf_s uncore cache Cache Lookups : SnoopFilter - S State event=0x34,umask=2  01    Cache Lookups : SnoopFilter - S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : SF Hit Shared State unc_cha_llc_lookup.writes_and_other uncore cache Cache Lookups : Filters Requests for those that write info into the cache event=0x34,umask=0x1a42ff  01    Cache Lookups : Write Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Writeback transactions from L2 to the LLC  This includes all write transactions -- both Cacheable and UC unc_cha_llc_lookup.write_local uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER event=0x34,umask=0x842ff  11     unc_cha_llc_lookup.write_remote uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER event=0x34,umask=0x17c2ff  11     unc_cha_llc_victims.all uncore cache Lines Victimized : All Lines Victimized event=0x37,umask=0xf  01    Lines Victimized : All Lines Victimized : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.local_all uncore cache Lines Victimized : Local - All Lines event=0x37,umask=0x200f  01    Lines Victimized : Local - All Lines : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.local_e uncore cache Lines Victimized : Local - Lines in E State event=0x37,umask=0x2002  01    Lines Victimized : Local - Lines in E State : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.local_m uncore cache Lines Victimized : Local - Lines in M State event=0x37,umask=0x2001  01    Lines Victimized : Local - Lines in M State : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.local_s uncore cache Lines Victimized : Local - Lines in S State event=0x37,umask=0x2004  01    Lines Victimized : Local - Lines in S State : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.remote_all uncore cache Lines Victimized : Remote - All Lines event=0x37,umask=0x800f  01    Lines Victimized : Remote - All Lines : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.remote_e uncore cache Lines Victimized : Remote - Lines in E State event=0x37,umask=0x8002  01    Lines Victimized : Remote - Lines in E State : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.remote_m uncore cache Lines Victimized : Remote - Lines in M State event=0x37,umask=0x8001  01    Lines Victimized : Remote - Lines in M State : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_llc_victims.remote_s uncore cache Lines Victimized : Remote - Lines in S State event=0x37,umask=0x8004  01    Lines Victimized : Remote - Lines in S State : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_cha_misc_external.mbe_inst0 uncore cache Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0 event=0xe6,umask=1  01     unc_cha_misc_external.mbe_inst1 uncore cache Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1 event=0xe6,umask=2  01     unc_cha_pipe_reject.adegrcredit uncore cache Pipe Rejects event=0x42  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.akegrcredit uncore cache Pipe Rejects event=0x42  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.allrsfways_res uncore cache Pipe Rejects event=0x42  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.blegrcredit uncore cache Pipe Rejects event=0x42  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.fsf_vicp uncore cache Pipe Rejects event=0x42  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.gotrack_allowsnp uncore cache Pipe Rejects event=0x42,umask=4  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.gotrack_allwayrsv uncore cache Pipe Rejects event=0x42,umask=0x10  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.gotrack_pamatch uncore cache Pipe Rejects event=0x42,umask=2  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.gotrack_waymatch uncore cache Pipe Rejects event=0x42,umask=8  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.hacredit uncore cache Pipe Rejects event=0x42  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.idx_inpipe uncore cache Pipe Rejects event=0x42  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.ipq_setmatch_vicp uncore cache Pipe Rejects event=0x42  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.irq_pmm uncore cache Pipe Rejects event=0x42,umask=0x20  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.irq_setmatch_vicp uncore cache Pipe Rejects event=0x42  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.ismq_setmatch_vicp uncore cache Pipe Rejects event=0x42  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.ivegrcredit uncore cache Pipe Rejects event=0x42  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.llc_ways_res uncore cache Pipe Rejects event=0x42  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.notallowsnoop uncore cache Pipe Rejects event=0x42  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.one_fsf_vic uncore cache Pipe Rejects event=0x42  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.one_rsp_con uncore cache Pipe Rejects event=0x42  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.pmm_memmode_tormatch_multi uncore cache Pipe Rejects event=0x42  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.pmm_memmode_tor_match uncore cache Pipe Rejects event=0x42  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.prq_pmm uncore cache Pipe Rejects event=0x42,umask=0x40  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.ptl_inpipe uncore cache Pipe Rejects event=0x42,umask=0x80  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.rmw_setmatch uncore cache Pipe Rejects event=0x42,umask=1  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.rrq_setmatch_vicp uncore cache Pipe Rejects event=0x42  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.setmatchentrywsct uncore cache Pipe Rejects event=0x42  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.sf_ways_res uncore cache Pipe Rejects event=0x42  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.topa_match uncore cache Pipe Rejects event=0x42  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.torid_match_go_p uncore cache Pipe Rejects event=0x42  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.vn_ad_req uncore cache Pipe Rejects event=0x42  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.vn_ad_rsp uncore cache Pipe Rejects event=0x42  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.vn_bl_rsp uncore cache Pipe Rejects event=0x42  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pipe_reject.way_match uncore cache Pipe Rejects event=0x42  01    Pipe Rejects : More Miscellaneous events in the Cbo unc_cha_pmm_memmode_nm_setconflicts.llc uncore cache PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC event=0x64,umask=2  01    PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC : NM evictions due to another read to the same near memory set in the LLC unc_cha_pmm_memmode_nm_setconflicts.sf uncore cache PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC event=0x64,umask=1  01    PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC : NM evictions due to another read to the same near memory set in the SF unc_cha_pmm_memmode_nm_setconflicts.tor uncore cache PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in TOR event=0x64,umask=4  01    PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in TOR : No Reject in the CHA due to a pending read to the same near memory set in the TOR unc_cha_pmm_qos_occupancy.ddr_slow_fifo uncore cache UNC_CHA_PMM_QOS_OCCUPANCY.DDR_SLOW_FIFO event=0x67,umask=1  01    : count # of SLOW TOR Request inserted to ha_pmm_tor_req_fifo unc_cha_read_no_credits.mc10 uncore cache CHA iMC CHNx READ Credits Empty : MC10 event=0x58  01    CHA iMC CHNx READ Credits Empty : MC10 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 10 only unc_cha_read_no_credits.mc11 uncore cache CHA iMC CHNx READ Credits Empty : MC11 event=0x58  01    CHA iMC CHNx READ Credits Empty : MC11 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 11 only unc_cha_read_no_credits.mc12 uncore cache CHA iMC CHNx READ Credits Empty : MC12 event=0x58  01    CHA iMC CHNx READ Credits Empty : MC12 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 12 only unc_cha_read_no_credits.mc13 uncore cache CHA iMC CHNx READ Credits Empty : MC13 event=0x58  01    CHA iMC CHNx READ Credits Empty : MC13 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 13 only unc_cha_read_no_credits.mc6 uncore cache CHA iMC CHNx READ Credits Empty : MC6 event=0x58,umask=0x40  01    CHA iMC CHNx READ Credits Empty : MC6 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 6 only unc_cha_read_no_credits.mc7 uncore cache CHA iMC CHNx READ Credits Empty : MC7 event=0x58,umask=0x80  01    CHA iMC CHNx READ Credits Empty : MC7 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 7 only unc_cha_read_no_credits.mc8 uncore cache CHA iMC CHNx READ Credits Empty : MC8 event=0x58  01    CHA iMC CHNx READ Credits Empty : MC8 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 8 only unc_cha_read_no_credits.mc9 uncore cache CHA iMC CHNx READ Credits Empty : MC9 event=0x58  01    CHA iMC CHNx READ Credits Empty : MC9 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 9 only unc_cha_requests.invitoe uncore cache Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and remote INVITOE requests sent to the CHA's home agent event=0x50,umask=0x30  01    Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA unc_cha_requests.invitoe_local uncore cache Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and are sent to the CHA's home agent event=0x50,umask=0x10  01    Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA unc_cha_requests.invitoe_remote uncore cache Remote INVITOE requests (exclusive ownership of a cache line without receiving data) sent to the CHA's home agent event=0x50,umask=0x20  01    Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA unc_cha_requests.reads uncore cache Local read requests that miss the SF/LLC and remote read requests sent to the CHA's home agent event=0x50,umask=3  01    Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a  write)  unc_cha_requests.reads_local uncore cache Local read requests that miss the SF/LLC and are sent to the CHA's home agent event=0x50,umask=1  01    Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a  write) unc_cha_requests.reads_remote uncore cache Remote read requests sent to the CHA's home agent event=0x50,umask=2  01    Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a  write) unc_cha_requests.writes uncore cache Local write requests that miss the SF/LLC and remote write requests sent to the CHA's home agent event=0x50,umask=0xc  01    Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc unc_cha_requests.writes_local uncore cache Local write requests that miss the SF/LLC and are sent to the CHA's home agent event=0x50,umask=4  01    Counts  write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc unc_cha_requests.writes_remote uncore cache Remote write requests sent to the CHA's home agent event=0x50,umask=8  01    Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc) unc_cha_ring_bounces_horz.ad uncore cache Messages that bounced on the Horizontal Ring. : AD event=0xac,umask=1  01    Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_cha_ring_bounces_horz.ak uncore cache Messages that bounced on the Horizontal Ring. : AK event=0xac,umask=2  01    Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_cha_ring_bounces_horz.bl uncore cache Messages that bounced on the Horizontal Ring. : BL event=0xac,umask=4  01    Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_cha_ring_bounces_horz.iv uncore cache Messages that bounced on the Horizontal Ring. : IV event=0xac,umask=8  01    Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_cha_ring_bounces_vert.ad uncore cache Messages that bounced on the Vertical Ring. : AD event=0xaa,umask=1  01    Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_cha_ring_bounces_vert.ak uncore cache Messages that bounced on the Vertical Ring. : Acknowledgements to core event=0xaa,umask=2  01    Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_cha_ring_bounces_vert.akc uncore cache Messages that bounced on the Vertical Ring event=0xaa,umask=0x10  01    Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_cha_ring_bounces_vert.bl uncore cache Messages that bounced on the Vertical Ring. : Data Responses to core event=0xaa,umask=4  01    Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_cha_ring_bounces_vert.iv uncore cache Messages that bounced on the Vertical Ring. : Snoops of processor's cache event=0xaa,umask=8  01    Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_cha_ring_sink_starved_horz.ad uncore cache Sink Starvation on Horizontal Ring : AD event=0xad,umask=1  01     unc_cha_ring_sink_starved_horz.ak uncore cache Sink Starvation on Horizontal Ring : AK event=0xad,umask=2  01     unc_cha_ring_sink_starved_horz.ak_ag1 uncore cache Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1 event=0xad,umask=0x20  01     unc_cha_ring_sink_starved_horz.bl uncore cache Sink Starvation on Horizontal Ring : BL event=0xad,umask=4  01     unc_cha_ring_sink_starved_horz.iv uncore cache Sink Starvation on Horizontal Ring : IV event=0xad,umask=8  01     unc_cha_ring_sink_starved_vert.ad uncore cache Sink Starvation on Vertical Ring : AD event=0xab,umask=1  01     unc_cha_ring_sink_starved_vert.ak uncore cache Sink Starvation on Vertical Ring : Acknowledgements to core event=0xab,umask=2  01     unc_cha_ring_sink_starved_vert.akc uncore cache Sink Starvation on Vertical Ring event=0xab,umask=0x10  01     unc_cha_ring_sink_starved_vert.bl uncore cache Sink Starvation on Vertical Ring : Data Responses to core event=0xab,umask=4  01     unc_cha_ring_sink_starved_vert.iv uncore cache Sink Starvation on Vertical Ring : Snoops of processor's cache event=0xab,umask=8  01     unc_cha_ring_src_thrtl uncore cache Source Throttle event=0xae  01     unc_cha_rxc_occupancy.irq uncore cache Ingress (from CMS) Occupancy : IRQ event=0x11,umask=1  01    Ingress (from CMS) Occupancy : IRQ : Counts number of entries in the specified Ingress queue in each cycle unc_cha_rxr_busy_starved.ad_all uncore cache Transgress Injection Starvation : AD - All event=0xe5,umask=0x11  01    Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority : All == Credited + Uncredited unc_cha_rxr_busy_starved.ad_crd uncore cache Transgress Injection Starvation : AD - Credited event=0xe5,umask=0x10  01    Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority unc_cha_rxr_busy_starved.ad_uncrd uncore cache Transgress Injection Starvation : AD - Uncredited event=0xe5,umask=1  01    Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority unc_cha_rxr_busy_starved.bl_all uncore cache Transgress Injection Starvation : BL - All event=0xe5,umask=0x44  01    Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority : All == Credited + Uncredited unc_cha_rxr_busy_starved.bl_crd uncore cache Transgress Injection Starvation : BL - Credited event=0xe5,umask=0x40  01    Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority unc_cha_rxr_busy_starved.bl_uncrd uncore cache Transgress Injection Starvation : BL - Uncredited event=0xe5,umask=4  01    Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority unc_cha_rxr_bypass.ad_all uncore cache Transgress Ingress Bypass : AD - All event=0xe2,umask=0x11  01    Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited unc_cha_rxr_bypass.ad_crd uncore cache Transgress Ingress Bypass : AD - Credited event=0xe2,umask=0x10  01    Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.ad_uncrd uncore cache Transgress Ingress Bypass : AD - Uncredited event=0xe2,umask=1  01    Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.ak uncore cache Transgress Ingress Bypass : AK event=0xe2,umask=2  01    Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.akc_uncrd uncore cache Transgress Ingress Bypass : AKC - Uncredited event=0xe2,umask=0x80  01    Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.bl_all uncore cache Transgress Ingress Bypass : BL - All event=0xe2,umask=0x44  01    Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited unc_cha_rxr_bypass.bl_crd uncore cache Transgress Ingress Bypass : BL - Credited event=0xe2,umask=0x40  01    Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.bl_uncrd uncore cache Transgress Ingress Bypass : BL - Uncredited event=0xe2,umask=4  01    Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress unc_cha_rxr_bypass.iv uncore cache Transgress Ingress Bypass : IV event=0xe2,umask=8  01    Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress unc_cha_rxr_crd_starved.ad_all uncore cache Transgress Injection Starvation : AD - All event=0xe3,umask=0x11  01    Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited unc_cha_rxr_crd_starved.ad_crd uncore cache Transgress Injection Starvation : AD - Credited event=0xe3,umask=0x10  01    Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.ad_uncrd uncore cache Transgress Injection Starvation : AD - Uncredited event=0xe3,umask=1  01    Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.ak uncore cache Transgress Injection Starvation : AK event=0xe3,umask=2  01    Transgress Injection Starvation : AK : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.bl_all uncore cache Transgress Injection Starvation : BL - All event=0xe3,umask=0x44  01    Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited unc_cha_rxr_crd_starved.bl_crd uncore cache Transgress Injection Starvation : BL - Credited event=0xe3,umask=0x40  01    Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.bl_uncrd uncore cache Transgress Injection Starvation : BL - Uncredited event=0xe3,umask=4  01    Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.ifv uncore cache Transgress Injection Starvation : IFV - Credited event=0xe3,umask=0x80  01    Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved.iv uncore cache Transgress Injection Starvation : IV event=0xe3,umask=8  01    Transgress Injection Starvation : IV : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_crd_starved_1 uncore cache Transgress Injection Starvation event=0xe4  01    Transgress Injection Starvation : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_cha_rxr_inserts.ad_all uncore cache Transgress Ingress Allocations : AD - All event=0xe1,umask=0x11  01    Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_cha_rxr_inserts.ad_crd uncore cache Transgress Ingress Allocations : AD - Credited event=0xe1,umask=0x10  01    Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.ad_uncrd uncore cache Transgress Ingress Allocations : AD - Uncredited event=0xe1,umask=1  01    Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.ak uncore cache Transgress Ingress Allocations : AK event=0xe1,umask=2  01    Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.akc_uncrd uncore cache Transgress Ingress Allocations : AKC - Uncredited event=0xe1,umask=0x80  01    Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.bl_all uncore cache Transgress Ingress Allocations : BL - All event=0xe1,umask=0x44  01    Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_cha_rxr_inserts.bl_crd uncore cache Transgress Ingress Allocations : BL - Credited event=0xe1,umask=0x40  01    Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.bl_uncrd uncore cache Transgress Ingress Allocations : BL - Uncredited event=0xe1,umask=4  01    Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_cha_rxr_inserts.iv uncore cache Transgress Ingress Allocations : IV event=0xe1,umask=8  01    Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.ad_all uncore cache Transgress Ingress Occupancy : AD - All event=0xe0,umask=0x11  01    Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_cha_rxr_occupancy.ad_crd uncore cache Transgress Ingress Occupancy : AD - Credited event=0xe0,umask=0x10  01    Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.ad_uncrd uncore cache Transgress Ingress Occupancy : AD - Uncredited event=0xe0,umask=1  01    Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.ak uncore cache Transgress Ingress Occupancy : AK event=0xe0,umask=2  01    Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.akc_uncrd uncore cache Transgress Ingress Occupancy : AKC - Uncredited event=0xe0,umask=0x80  01    Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.bl_all uncore cache Transgress Ingress Occupancy : BL - All event=0xe0,umask=0x44  01    Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_cha_rxr_occupancy.bl_crd uncore cache Transgress Ingress Occupancy : BL - Credited event=0xe0,umask=0x20  01    Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.bl_uncrd uncore cache Transgress Ingress Occupancy : BL - Uncredited event=0xe0,umask=4  01    Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_cha_rxr_occupancy.iv uncore cache Transgress Ingress Occupancy : IV event=0xe0,umask=8  01    Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_cha_sf_eviction.e_state uncore cache Snoop filter capacity evictions for E-state entries event=0x3d,umask=2  01    Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline unc_cha_sf_eviction.m_state uncore cache Snoop filter capacity evictions for M-state entries event=0x3d,umask=1  01    Counts snoop filter capacity evictions for entries tracking modified lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline unc_cha_sf_eviction.s_state uncore cache Snoop filter capacity evictions for S-state entries event=0x3d,umask=4  01    Counts snoop filter capacity evictions for entries tracking shared lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline unc_cha_snoops_sent.bcst_local uncore cache Snoops Sent : Broadcast snoops for Local Requests event=0x51,umask=0x10  01    Snoops Sent : Broadcast snoops for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast snoops issued by the HA responding to local requests unc_cha_snoops_sent.bcst_remote uncore cache Snoops Sent : Broadcast snoops for Remote Requests event=0x51,umask=0x20  01    Snoops Sent : Broadcast snoops for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast snoops issued by the HA responding to remote requests unc_cha_snoops_sent.direct_local uncore cache Snoops Sent : Directed snoops for Local Requests event=0x51,umask=0x40  01    Snoops Sent : Directed snoops for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of directed snoops issued by the HA responding to local requests unc_cha_snoops_sent.direct_remote uncore cache Snoops Sent : Directed snoops for Remote Requests event=0x51,umask=0x80  01    Snoops Sent : Directed snoops for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of directed snoops issued by the HA responding to remote requests unc_cha_snoops_sent.local uncore cache Snoops Sent : Snoops sent for Local Requests event=0x51,umask=4  01    Snoops Sent : Snoops sent for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast or directed snoops issued by the HA responding to local requests unc_cha_snoops_sent.remote uncore cache Snoops Sent : Snoops sent for Remote Requests event=0x51,umask=8  01    Snoops Sent : Snoops sent for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast or directed snoops issued by the HA responding to remote requests unc_cha_snoop_resp.rspi uncore cache Snoop Responses Received : RspI event=0x5c,umask=1  01    Counts when a transaction with the opcode type RspI Snoop Response was received which indicates the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO: the Read for Ownership issued before a write hits non-modified data) unc_cha_snoop_resp.rspifwd uncore cache Snoop Responses Received : RspIFwd event=0x5c,umask=4  01    Counts when a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states.  This is commonly returned with RFO (the Read for Ownership issued before a write) transactions.  The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward)  states unc_cha_snoop_resp.rsps uncore cache Snoop Responses Received : RspS event=0x5c,umask=2  01    Counts when a transaction with the opcode type RspS Snoop Response was received which indicates when a remote cache has data but is not forwarding it.  It is a way to let the requesting socket know that it cannot allocate the data in E state.  No data is sent with S RspS unc_cha_snoop_resp.rspsfwd uncore cache Snoop Responses Received : RspSFwd event=0x5c,umask=8  01    Counts when a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy.  This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state unc_cha_snoop_resp_local.rspsfwd uncore cache Snoop Responses Received Local : RspSFwd event=0x5d,umask=8  01    Snoop Responses Received Local : RspSFwd : Number of snoop responses received for a Local  request : Filters for a snoop response of RspSFwd to local CA requests.  This is returned when a remote caching agent forwards data but holds on to its currently copy.  This is common for data and code reads that hit in a remote socket in E or F state unc_cha_stall0_no_txr_horz_crd_ad_ag0.tgr0 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 0 event=0xd0,umask=1  01    Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag0.tgr1 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 1 event=0xd0,umask=2  01    Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag0.tgr2 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 2 event=0xd0,umask=4  01    Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag0.tgr3 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 3 event=0xd0,umask=8  01    Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag0.tgr4 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 4 event=0xd0,umask=0x10  01    Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag0.tgr5 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 5 event=0xd0,umask=0x20  01    Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag0.tgr6 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 6 event=0xd0,umask=0x40  01    Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag0.tgr7 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 7 event=0xd0,umask=0x80  01    Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag1.tgr0 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 0 event=0xd2,umask=1  01    Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag1.tgr1 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 1 event=0xd2,umask=2  01    Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag1.tgr2 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 2 event=0xd2,umask=4  01    Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag1.tgr3 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 3 event=0xd2,umask=8  01    Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag1.tgr4 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 4 event=0xd2,umask=0x10  01    Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag1.tgr5 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 5 event=0xd2,umask=0x20  01    Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag1.tgr6 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 6 event=0xd2,umask=0x40  01    Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_ad_ag1.tgr7 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 7 event=0xd2,umask=0x80  01    Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag0.tgr0 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 0 event=0xd4,umask=1  01    Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag0.tgr1 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 1 event=0xd4,umask=2  01    Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag0.tgr2 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 2 event=0xd4,umask=4  01    Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag0.tgr3 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 3 event=0xd4,umask=8  01    Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag0.tgr4 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 4 event=0xd4,umask=0x10  01    Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag0.tgr5 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 5 event=0xd4,umask=0x20  01    Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag0.tgr6 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 6 event=0xd4,umask=0x40  01    Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag0.tgr7 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 7 event=0xd4,umask=0x80  01    Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag1.tgr0 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 0 event=0xd6,umask=1  01    Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag1.tgr1 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 1 event=0xd6,umask=2  01    Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag1.tgr2 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 2 event=0xd6,umask=4  01    Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag1.tgr3 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 3 event=0xd6,umask=8  01    Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag1.tgr4 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 4 event=0xd6,umask=0x10  01    Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag1.tgr5 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 5 event=0xd6,umask=0x20  01    Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag1.tgr6 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 6 event=0xd6,umask=0x40  01    Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall0_no_txr_horz_crd_bl_ag1.tgr7 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 7 event=0xd6,umask=0x80  01    Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_ad_ag0.tgr10 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 10 event=0xd1,umask=4  01    Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_ad_ag0.tgr8 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 8 event=0xd1,umask=1  01    Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_ad_ag0.tgr9 uncore cache Stall on No AD Agent0 Transgress Credits : For Transgress 9 event=0xd1,umask=2  01    Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_ad_ag1_1.tgr10 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 10 event=0xd3,umask=4  01    Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_ad_ag1_1.tgr8 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 8 event=0xd3,umask=1  01    Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_ad_ag1_1.tgr9 uncore cache Stall on No AD Agent1 Transgress Credits : For Transgress 9 event=0xd3,umask=2  01    Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_bl_ag0_1.tgr10 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 10 event=0xd5,umask=4  01    Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_bl_ag0_1.tgr8 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 8 event=0xd5,umask=1  01    Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_bl_ag0_1.tgr9 uncore cache Stall on No BL Agent0 Transgress Credits : For Transgress 9 event=0xd5,umask=2  01    Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_bl_ag1_1.tgr10 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 10 event=0xd7,umask=4  01    Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_bl_ag1_1.tgr8 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 8 event=0xd7,umask=1  01    Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_stall1_no_txr_horz_crd_bl_ag1_1.tgr9 uncore cache Stall on No BL Agent1 Transgress Credits : For Transgress 9 event=0xd7,umask=2  01    Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_cha_tor_inserts.all uncore cache TOR Inserts : All event=0x35,umask=0xc001ffff  01    TOR Inserts : All : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ddr uncore cache TOR Inserts : DDR4 Access event=0x35  01    TOR Inserts : DDR4 Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ddr4 uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.DDR event=0x35  11     unc_cha_tor_inserts.evict uncore cache TOR Inserts : SF/LLC Evictions event=0x35,umask=2  01    TOR Inserts : SF/LLC Evictions : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ) unc_cha_tor_inserts.hit uncore cache TOR Inserts : Just Hits event=0x35  01    TOR Inserts : Just Hits : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia uncore cache TOR Inserts : All requests from iA Cores event=0x35,umask=0xc001ff01  01    TOR Inserts : All requests from iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_clflush uncore cache TOR Inserts : CLFlushes issued by iA Cores event=0x35,umask=0xc8c7ff01  01    TOR Inserts : CLFlushes issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_clflushopt uncore cache TOR Inserts : CLFlushOpts issued by iA Cores event=0x35,umask=0xc8d7ff01  01    TOR Inserts : CLFlushOpts issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_crd uncore cache TOR Inserts : CRDs issued by iA Cores event=0x35,umask=0xc80fff01  01    TOR Inserts : CRDs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_drd uncore cache TOR Inserts : DRds issued by iA Cores event=0x35,umask=0xc817ff01  01    TOR Inserts : DRds issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_drd_opt uncore cache TOR Inserts : DRd_Opts issued by iA Cores event=0x35,umask=0xc827ff01  01    TOR Inserts : DRd_Opts issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_drd_opt_pref uncore cache TOR Inserts : DRd_Opt_Prefs issued by iA Cores event=0x35,umask=0xc8a7ff01  01    TOR Inserts : DRd_Opt_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_drd_pref uncore cache TOR Inserts : DRd_Prefs issued by iA Cores event=0x35,umask=0xc897ff01  01    TOR Inserts : DRd_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit uncore cache TOR Inserts : All requests from iA Cores that Hit the LLC event=0x35,umask=0xc001fd01  01    TOR Inserts : All requests from iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_crd uncore cache TOR Inserts : CRds issued by iA Cores that Hit the LLC event=0x35,umask=0xc80ffd01  01    TOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_crd_pref uncore cache TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC event=0x35,umask=0xc88ffd01  01    TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_drd uncore cache TOR Inserts : DRds issued by iA Cores that Hit the LLC event=0x35,umask=0xc817fd01  01    TOR Inserts : DRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_drd_opt uncore cache TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC event=0x35,umask=0xc827fd01  01    TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_drd_opt_pref uncore cache TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC event=0x35,umask=0xc8a7fd01  01    TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_drd_pref uncore cache TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC event=0x35,umask=0xc897fd01  01    TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_itom uncore cache TOR Inserts : ItoMs issued by iA Cores that Hit LLC event=0x35,umask=0xcc47fd01  01    TOR Inserts : ItoMs issued by iA Cores that Hit LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_llcprefcode uncore cache TOR Inserts : LLCPrefCode issued by iA Cores that hit the LLC event=0x35,umask=0xcccffd01  01    TOR Inserts : LLCPrefCode issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_llcprefcrd uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE event=0x35,umask=0xcccffd01  11     unc_cha_tor_inserts.ia_hit_llcprefdata uncore cache TOR Inserts : LLCPrefData issued by iA Cores that hit the LLC event=0x35,umask=0xccd7fd01  01    TOR Inserts : LLCPrefData issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_llcprefdrd uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA event=0x35,umask=0xccd7fd01  11     unc_cha_tor_inserts.ia_hit_llcprefrfo uncore cache TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC event=0x35,umask=0xccc7fd01  01    TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_rfo uncore cache TOR Inserts : RFOs issued by iA Cores that Hit the LLC event=0x35,umask=0xc807fd01  01    TOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_rfo_pref uncore cache TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC event=0x35,umask=0xc887fd01  01    TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_hit_specitom uncore cache TOR Inserts : SpecItoMs issued by iA Cores that hit in the LLC event=0x35,umask=0xcc57fd01  01    TOR Inserts : SpecItoMs issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_itom uncore cache TOR Inserts : ItoMs issued by iA Cores event=0x35,umask=0xcc47ff01  01    TOR Inserts : ItoMs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_itomcachenear uncore cache TOR Inserts : ItoMCacheNears issued by iA Cores event=0x35,umask=0xcd47ff01  01    TOR Inserts : ItoMCacheNears issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_llcprefcode uncore cache TOR Inserts : LLCPrefCode issued by iA Cores event=0x35,umask=0xcccfff01  01    TOR Inserts : LLCPrefCode issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_llcprefdata uncore cache TOR Inserts : LLCPrefData issued by iA Cores event=0x35,umask=0xccd7ff01  01    TOR Inserts : LLCPrefData issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_llcprefrfo uncore cache TOR Inserts : LLCPrefRFO issued by iA Cores event=0x35,umask=0xccc7ff01  01    TOR Inserts : LLCPrefRFO issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss uncore cache TOR Inserts : All requests from iA Cores that Missed the LLC event=0x35,umask=0xc001fe01  01    TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd uncore cache TOR Inserts : CRds issued by iA Cores that Missed the LLC event=0x35,umask=0xc80ffe01  01    TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd_local uncore cache TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally event=0x35,umask=0xc80efe01  01    TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd_pref uncore cache TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC event=0x35,umask=0xc88ffe01  01    TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd_pref_local uncore cache TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally event=0x35,umask=0xc88efe01  01    TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd_pref_remote uncore cache TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely event=0x35,umask=0xc88f7e01  01    TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_crd_remote uncore cache TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely event=0x35,umask=0xc80f7e01  01    TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd uncore cache TOR Inserts : DRds issued by iA Cores that Missed the LLC event=0x35,umask=0xc817fe01  01    TOR Inserts : DRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_ddr uncore cache TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC event=0x35,umask=0xc8178601  01    TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_local uncore cache TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally event=0x35,umask=0xc816fe01  01    TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_local_ddr uncore cache TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally event=0x35,umask=0xc8168601  01    TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_local_pmm uncore cache TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally event=0x35,umask=0xc8168a01  01    TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_opt uncore cache TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC event=0x35,umask=0xc827fe01  01    TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_opt_pref uncore cache TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC event=0x35,umask=0xc8a7fe01  01    TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pmm uncore cache TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC event=0x35,umask=0xc8178a01  01    TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref uncore cache TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC event=0x35,umask=0xc897fe01  01    TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_ddr uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC event=0x35,umask=0xc8978601  01    TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_local uncore cache TOR Inserts; DRd Pref misses from local IA event=0x35,umask=0xc896fe01  01    TOR Inserts; Data read prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_drd_pref_local_ddr uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally event=0x35,umask=0xc8968601  01    TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_local_pmm uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally event=0x35,umask=0xc8968a01  01    TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_pmm uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC event=0x35,umask=0xc8978a01  01    TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_remote uncore cache TOR Inserts; DRd Pref misses from local IA event=0x35,umask=0xc8977e01  01    TOR Inserts; Data read prefetch from remote IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_drd_pref_remote_ddr uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely event=0x35,umask=0xc8970601  01    TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_pref_remote_pmm uncore cache TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely event=0x35,umask=0xc8970a01  01    TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_remote uncore cache TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely event=0x35,umask=0xc8177e01  01    TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_remote_ddr uncore cache TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely event=0x35,umask=0xc8170601  01    TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_remote_pmm uncore cache TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely event=0x35,umask=0xc8170a01  01    TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_full_streaming_wr uncore cache TOR Inserts; WCiLF misses from local IA event=0x35,umask=0xc867fe01  01    TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_full_streaming_wr_ddr uncore cache TOR Inserts; WCiLF misses from local IA event=0x35,umask=0xc8678601  01    TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_full_streaming_wr_dram uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR event=0x35,umask=0xc8678601  11     unc_cha_tor_inserts.ia_miss_full_streaming_wr_local_ddr uncore cache TOR Inserts; WCiLF misses from local IA event=0x35,umask=0xc8668601  01    TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_full_streaming_wr_local_dram uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR event=0x35,umask=0xc8668601  11     unc_cha_tor_inserts.ia_miss_full_streaming_wr_local_pmm uncore cache TOR Inserts; WCiLF misses from local IA event=0x35,umask=0xc8668a01  01    TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_full_streaming_wr_pmm uncore cache TOR Inserts; WCiLF misses from local IA event=0x35,umask=0xc8678a01  01    TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_full_streaming_wr_remote_ddr uncore cache TOR Inserts; WCiLF misses from local IA event=0x35,umask=0xc8670601  01    TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_full_streaming_wr_remote_dram uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR event=0x35,umask=0xc8670601  11     unc_cha_tor_inserts.ia_miss_full_streaming_wr_remote_pmm uncore cache TOR Inserts; WCiLF misses from local IA event=0x35,umask=0xc8670a01  01    TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_itom uncore cache TOR Inserts : ItoMs issued by iA Cores that Missed LLC event=0x35,umask=0xcc47fe01  01    TOR Inserts : ItoMs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_llcprefcode uncore cache TOR Inserts : LLCPrefCode issued by iA Cores that missed the LLC event=0x35,umask=0xcccffe01  01    TOR Inserts : LLCPrefCode issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_llcprefdata uncore cache TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC event=0x35,umask=0xccd7fe01  01    TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_llcprefrfo uncore cache TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC event=0x35,umask=0xccc7fe01  01    TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_local_wcilf_ddr uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally event=0x35,umask=0xc8668601  01    TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_local_wcilf_pmm uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally event=0x35,umask=0xc8668a01  01    TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_local_wcil_ddr uncore cache TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally event=0x35,umask=0xc86e8601  01    TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_local_wcil_pmm uncore cache TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally event=0x35,umask=0xc86e8a01  01    TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_partial_streaming_wr uncore cache TOR Inserts; WCiL misses from local IA event=0x35,umask=0xc86ffe01  01    TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_partial_streaming_wr_ddr uncore cache TOR Inserts; WCiL misses from local IA event=0x35,umask=0xc86f8601  01    TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_partial_streaming_wr_dram uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR event=0x35,umask=0xc86f8601  11     unc_cha_tor_inserts.ia_miss_partial_streaming_wr_local_ddr uncore cache TOR Inserts; WCiL misses from local IA event=0x35,umask=0xc86e8601  01    TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_partial_streaming_wr_local_dram uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR event=0x35,umask=0xc86e8601  11     unc_cha_tor_inserts.ia_miss_partial_streaming_wr_local_pmm uncore cache TOR Inserts; WCiL misses from local IA event=0x35,umask=0xc86e8a01  01    TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_partial_streaming_wr_pmm uncore cache TOR Inserts; WCiL misses from local IA event=0x35,umask=0xc86f8a01  01    TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_partial_streaming_wr_remote_ddr uncore cache TOR Inserts; WCiL misses from local IA event=0x35,umask=0xc86f0601  01    TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_partial_streaming_wr_remote_dram uncore cache This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR event=0x35,umask=0xc86f0601  11     unc_cha_tor_inserts.ia_miss_partial_streaming_wr_remote_pmm uncore cache TOR Inserts; WCiL misses from local IA event=0x35,umask=0xc86f0a01  01    TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_remote_wcilf_ddr uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely event=0x35,umask=0xc8670601  01    TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_remote_wcilf_pmm uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remote memory event=0x35,umask=0xc8670a01  01    TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_remote_wcil_ddr uncore cache TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely event=0x35,umask=0xc86f0601  01    TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_remote_wcil_pmm uncore cache TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely event=0x35,umask=0xc86f0a01  01    TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_rfo uncore cache TOR Inserts : RFOs issued by iA Cores that Missed the LLC event=0x35,umask=0xc807fe01  01    TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_rfo_local uncore cache TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally event=0x35,umask=0xc806fe01  01    TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_rfo_pref uncore cache TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC event=0x35,umask=0xc887fe01  01    TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_rfo_pref_local uncore cache TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally event=0x35,umask=0xc886fe01  01    TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_rfo_pref_remote uncore cache TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely event=0x35,umask=0xc8877e01  01    TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_rfo_remote uncore cache TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely event=0x35,umask=0xc8077e01  01    TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_specitom uncore cache TOR Inserts : SpecItoMs issued by iA Cores that missed the LLC event=0x35,umask=0xcc57fe01  01    TOR Inserts : SpecItoMs issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_ucrdf uncore cache TOR Inserts : UCRdFs issued by iA Cores that Missed LLC event=0x35,umask=0xc877de01  01    TOR Inserts : UCRdFs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcil uncore cache TOR Inserts : WCiLs issued by iA Cores that Missed the LLC event=0x35,umask=0xc86ffe01  01    TOR Inserts : WCiLs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcilf uncore cache TOR Inserts : WCiLF issued by iA Cores that Missed the LLC event=0x35,umask=0xc867fe01  01    TOR Inserts : WCiLF issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcilf_ddr uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC event=0x35,umask=0xc8678601  01    TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcilf_pmm uncore cache TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC event=0x35,umask=0xc8678a01  01    TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcil_ddr uncore cache TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC event=0x35,umask=0xc86f8601  01    TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcil_pmm uncore cache TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC event=0x35,umask=0xc86f8a01  01    TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wil uncore cache TOR Inserts : WiLs issued by iA Cores that Missed LLC event=0x35,umask=0xc87fde01  01    TOR Inserts : WiLs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_rfo uncore cache TOR Inserts : RFOs issued by iA Cores event=0x35,umask=0xc807ff01  01    TOR Inserts : RFOs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_rfo_pref uncore cache TOR Inserts : RFO_Prefs issued by iA Cores event=0x35,umask=0xc887ff01  01    TOR Inserts : RFO_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_specitom uncore cache TOR Inserts : SpecItoMs issued by iA Cores event=0x35,umask=0xcc57ff01  01    TOR Inserts : SpecItoMs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wbeftoi uncore cache TOR Inserts : WBEFtoIs issued by an IA Core.  Non Modified Write Backs event=0x35,umask=0xcc37ff01  01    WbEFtoIs issued by iA Cores .  (Non Modified Write Backs)  :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.  Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wbmtoe uncore cache TOR Inserts : WBMtoEs issued by an IA Core.  Non Modified Write Backs event=0x35,umask=0xcc2fff01  01    WbMtoEs issued by iA Cores .  (Non Modified Write Backs)  :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.  Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wbstoi uncore cache TOR Inserts : WBStoIs issued by an IA Core.  Non Modified Write Backs event=0x35,umask=0xcc67ff01  01    WbStoIs issued by iA Cores .  (Non Modified Write Backs)  :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.  Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wcil uncore cache TOR Inserts : WCiLs issued by iA Cores event=0x35,umask=0xc86fff01  01    TOR Inserts : WCiLs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_wcilf uncore cache TOR Inserts : WCiLF issued by iA Cores event=0x35,umask=0xc867ff01  01    TOR Inserts : WCiLF issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io uncore cache TOR Inserts : All requests from IO Devices event=0x35,umask=0xc001ff04  01    TOR Inserts : All requests from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_clflush uncore cache TOR Inserts : CLFlushes issued by IO Devices event=0x35,umask=0xc8c3ff04  01    TOR Inserts : CLFlushes issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_hit uncore cache TOR Inserts : All requests from IO Devices that hit the LLC event=0x35,umask=0xc001fd04  01    TOR Inserts : All requests from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_hit_itom uncore cache TOR Inserts : ItoMs issued by IO Devices that Hit the LLC event=0x35,umask=0xcc43fd04  01    TOR Inserts : ItoMs issued by IO Devices that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_hit_pcirdcur uncore cache TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC event=0x35,umask=0xc8f3fd04  01    TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_hit_rfo uncore cache TOR Inserts : RFOs issued by IO Devices that hit the LLC event=0x35,umask=0xc803fd04  01    TOR Inserts : RFOs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_itom uncore cache TOR Inserts : ItoMs issued by IO Devices event=0x35,umask=0xcc43ff04  01    TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_itomcachenear uncore cache TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices event=0x35,umask=0xcd43ff04  01    TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_itomcachenear_local uncore cache TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to locally HOMed memory event=0x35,umask=0xcd42ff04  01    TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_itomcachenear_remote uncore cache TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to remotely HOMed memory event=0x35,umask=0xcd437f04  01    TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_itom_local uncore cache TOR Inserts : ItoMs issued by IO Devices to locally HOMed memory event=0x35,umask=0xcc42ff04  01    TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_itom_remote uncore cache TOR Inserts : ItoMs issued by IO Devices to remotely HOMed memory event=0x35,umask=0xcc437f04  01    TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_miss uncore cache TOR Inserts : All requests from IO Devices that missed the LLC event=0x35,umask=0xc001fe04  01    TOR Inserts : All requests from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_miss_itom uncore cache TOR Inserts : ItoMs issued by IO Devices that missed the LLC event=0x35,umask=0xcc43fe04  01    TOR Inserts : ItoMs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_miss_pcirdcur uncore cache TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC event=0x35,umask=0xc8f3fe04  01    TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_miss_rfo uncore cache TOR Inserts : RFOs issued by IO Devices that missed the LLC event=0x35,umask=0xc803fe04  01    TOR Inserts : RFOs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_pcirdcur uncore cache TOR Inserts : PCIRdCurs issued by IO Devices event=0x35,umask=0xc8f3ff04  01    TOR Inserts : PCIRdCurs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_pcirdcur_local uncore cache PCIRDCUR (read) transactions from an IO device that addresses memory on the local socket event=0x35,umask=0xc8f2ff04  01    TOR Inserts : PCIRdCurs issued by IO Devices and targets local memory : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_pcirdcur_remote uncore cache PCIRDCUR (read) transactions from an IO device that addresses memory on a remote socket event=0x35,umask=0xc8f37f04  01    TOR Inserts : PCIRdCurs issued by IO Devices and targets remote memory : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_rfo uncore cache TOR Inserts : RFOs issued by IO Devices event=0x35,umask=0xc803ff04  01    TOR Inserts : RFOs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.io_wbmtoi uncore cache TOR Inserts : WbMtoIs issued by IO Devices event=0x35,umask=0xcc23ff04  01    TOR Inserts : WbMtoIs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ipq uncore cache TOR Inserts : IPQ event=0x35,umask=8  01    TOR Inserts : IPQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.irq_ia uncore cache TOR Inserts : IRQ - iA event=0x35,umask=1  01    TOR Inserts : IRQ - iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts. : From an iA Core unc_cha_tor_inserts.irq_non_ia uncore cache TOR Inserts : IRQ - Non iA event=0x35,umask=0x10  01    TOR Inserts : IRQ - Non iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.isoc uncore cache TOR Inserts : Just ISOC event=0x35  01    TOR Inserts : Just ISOC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.local_tgt uncore cache TOR Inserts : Just Local Targets event=0x35  01    TOR Inserts : Just Local Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.loc_all uncore cache TOR Inserts : All from Local iA and IO event=0x35,umask=0xc000ff05  01    TOR Inserts : All from Local iA and IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts. : All locally initiated requests unc_cha_tor_inserts.loc_ia uncore cache TOR Inserts : All from Local iA event=0x35,umask=0xc000ff01  01    TOR Inserts : All from Local iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts. : All locally initiated requests from iA Cores unc_cha_tor_inserts.loc_io uncore cache TOR Inserts : All from Local IO event=0x35,umask=0xc000ff04  01    TOR Inserts : All from Local IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts. : All locally generated IO traffic unc_cha_tor_inserts.match_opc uncore cache TOR Inserts : Match the Opcode in b[29:19] of the extended umask field event=0x35  01    TOR Inserts : Match the Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.miss uncore cache TOR Inserts : Just Misses event=0x35  01    TOR Inserts : Just Misses : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.mmcfg uncore cache TOR Inserts : MMCFG Access event=0x35  01    TOR Inserts : MMCFG Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.nearmem uncore cache TOR Inserts : Just NearMem event=0x35  01    TOR Inserts : Just NearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.noncoh uncore cache TOR Inserts : Just NonCoherent event=0x35  01    TOR Inserts : Just NonCoherent : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.not_nearmem uncore cache TOR Inserts : Just NotNearMem event=0x35  01    TOR Inserts : Just NotNearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.pmm uncore cache TOR Inserts : PMM Access event=0x35  01    TOR Inserts : PMM Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.premorph_opc uncore cache TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field event=0x35  01    TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.prq_iosf uncore cache TOR Inserts : PRQ - IOSF event=0x35,umask=4  01    TOR Inserts : PRQ - IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts. : From a PCIe Device unc_cha_tor_inserts.prq_non_iosf uncore cache TOR Inserts : PRQ - Non IOSF event=0x35,umask=0x20  01    TOR Inserts : PRQ - Non IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.remote_tgt uncore cache TOR Inserts : Just Remote Targets event=0x35  01    TOR Inserts : Just Remote Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.rrq uncore cache TOR Inserts : RRQ event=0x35,umask=0x40  01    TOR Inserts : RRQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.wbq uncore cache TOR Inserts : WBQ event=0x35,umask=0x80  01    TOR Inserts : WBQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ddr uncore cache TOR Occupancy : DDR4 Access event=0x36  01    TOR Occupancy : DDR4 Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.evict uncore cache TOR Occupancy : SF/LLC Evictions event=0x36,umask=2  01    TOR Occupancy : SF/LLC Evictions : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ) unc_cha_tor_occupancy.hit uncore cache TOR Occupancy : Just Hits event=0x36  01    TOR Occupancy : Just Hits : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia uncore cache TOR Occupancy : All requests from iA Cores event=0x36,umask=0xc001ff01  01    TOR Occupancy : All requests from iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_crd uncore cache TOR Occupancy : CRDs issued by iA Cores event=0x36,umask=0xc80fff01  01    TOR Occupancy : CRDs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_drd uncore cache TOR Occupancy : DRds issued by iA Cores event=0x36,umask=0xc817ff01  01    TOR Occupancy : DRds issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_drd_opt uncore cache TOR Occupancy : DRd_Opts issued by iA Cores event=0x36,umask=0xc827ff01  01    TOR Occupancy : DRd_Opts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_drd_opt_pref uncore cache TOR Occupancy : DRd_Opt_Prefs issued by iA Cores event=0x36,umask=0xc8a7ff01  01    TOR Occupancy : DRd_Opt_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_drd_pref uncore cache TOR Occupancy : DRd_Prefs issued by iA Cores event=0x36,umask=0xc897ff01  01    TOR Occupancy : DRd_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit uncore cache TOR Occupancy : All requests from iA Cores that Hit the LLC event=0x36,umask=0xc001fd01  01    TOR Occupancy : All requests from iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_crd uncore cache TOR Occupancy : CRds issued by iA Cores that Hit the LLC event=0x36,umask=0xc80ffd01  01    TOR Occupancy : CRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_crd_pref uncore cache TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC event=0x36,umask=0xc88ffd01  01    TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_drd uncore cache TOR Occupancy : DRds issued by iA Cores that Hit the LLC event=0x36,umask=0xc817fd01  01    TOR Occupancy : DRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_drd_opt uncore cache TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC event=0x36,umask=0xc827fd01  01    TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_drd_opt_pref uncore cache TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC event=0x36,umask=0xc8a7fd01  01    TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_drd_pref uncore cache TOR Occupancy : DRd_Prefs issued by iA Cores that Hit the LLC event=0x36,umask=0xc897fd01  01    TOR Occupancy : DRd_Prefs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_llcprefcode uncore cache TOR Occupancy : LLCPrefCode issued by iA Cores that hit the LLC event=0x36,umask=0xcccffd01  01    TOR Occupancy : LLCPrefCode issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_llcprefdata uncore cache TOR Occupancy : LLCPrefData issued by iA Cores that hit the LLC event=0x36,umask=0xccd7fd01  01    TOR Occupancy : LLCPrefData issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_llcprefrfo uncore cache TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC event=0x36,umask=0xccc7fd01  01    TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_rfo uncore cache TOR Occupancy : RFOs issued by iA Cores that Hit the LLC event=0x36,umask=0xc807fd01  01    TOR Occupancy : RFOs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_rfo_pref uncore cache TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC event=0x36,umask=0xc887fd01  01    TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_llcprefcode uncore cache TOR Occupancy : LLCPrefCode issued by iA Cores event=0x36,umask=0xcccfff01  01    TOR Occupancy : LLCPrefCode issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_llcprefdata uncore cache TOR Occupancy : LLCPrefData issued by iA Cores event=0x36,umask=0xccd7ff01  01    TOR Occupancy : LLCPrefData issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_llcprefrfo uncore cache TOR Occupancy : LLCPrefRFO issued by iA Cores event=0x36,umask=0xccc7ff01  01    TOR Occupancy : LLCPrefRFO issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss uncore cache TOR Occupancy : All requests from iA Cores that Missed the LLC event=0x36,umask=0xc001fe01  01    TOR Occupancy : All requests from iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_crd uncore cache TOR Occupancy : CRds issued by iA Cores that Missed the LLC event=0x36,umask=0xc80ffe01  01    TOR Occupancy : CRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_crd_pref uncore cache TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC event=0x36,umask=0xc88ffe01  01    TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd uncore cache TOR Occupancy : DRds issued by iA Cores that Missed the LLC event=0x36,umask=0xc817fe01  01    TOR Occupancy : DRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_ddr uncore cache TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC event=0x36,umask=0xc8178601  01    TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_local uncore cache TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally event=0x36,umask=0xc816fe01  01    TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_opt uncore cache TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC event=0x36,umask=0xc827fe01  01    TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_opt_pref uncore cache TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC event=0x36,umask=0xc8a7fe01  01    TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_pmm uncore cache TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC event=0x36,umask=0xc8178a01  01    TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_pref uncore cache TOR Occupancy : DRd_Prefs issued by iA Cores that Missed the LLC event=0x36,umask=0xc897fe01  01    TOR Occupancy : DRd_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_remote uncore cache TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely event=0x36,umask=0xc8177e01  01    TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_full_streaming_wr uncore cache TOR Occupancy; WCiLF misses from local IA event=0x36,umask=0xc867fe01  01    TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_full_streaming_wr_ddr uncore cache TOR Occupancy; WCiLF misses from local IA event=0x36,umask=0xc8678601  01    TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_full_streaming_wr_local_ddr uncore cache TOR Occupancy; WCiLF misses from local IA event=0x36,umask=0xc8668601  01    TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_full_streaming_wr_local_pmm uncore cache TOR Occupancy; WCiLF misses from local IA event=0x36,umask=0xc8668a01  01    TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_full_streaming_wr_pmm uncore cache TOR Occupancy; WCiLF misses from local IA event=0x36,umask=0xc8678a01  01    TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_full_streaming_wr_remote_ddr uncore cache TOR Occupancy; WCiLF misses from local IA event=0x36,umask=0xc8670601  01    TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_full_streaming_wr_remote_pmm uncore cache TOR Occupancy; WCiLF misses from local IA event=0x36,umask=0xc8670a01  01    TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_llcprefcode uncore cache TOR Occupancy : LLCPrefCode issued by iA Cores that missed the LLC event=0x36,umask=0xcccffe01  01    TOR Occupancy : LLCPrefCode issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_llcprefdata uncore cache TOR Occupancy : LLCPrefData issued by iA Cores that missed the LLC event=0x36,umask=0xccd7fe01  01    TOR Occupancy : LLCPrefData issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_llcprefrfo uncore cache TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC event=0x36,umask=0xccc7fe01  01    TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_partial_streaming_wr uncore cache TOR Occupancy; WCiL misses from local IA event=0x36,umask=0xc86ffe01  01    TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_partial_streaming_wr_ddr uncore cache TOR Occupancy; WCiL misses from local IA event=0x36,umask=0xc86f8601  01    TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_partial_streaming_wr_local_ddr uncore cache TOR Occupancy; WCiL misses from local IA event=0x36,umask=0xc86e8601  01    TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_partial_streaming_wr_local_pmm uncore cache TOR Occupancy; WCiL misses from local IA event=0x36,umask=0xc86e8a01  01    TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_partial_streaming_wr_pmm uncore cache TOR Occupancy; WCiL misses from local IA event=0x36,umask=0xc86f8a01  01    TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_partial_streaming_wr_remote_ddr uncore cache TOR Occupancy; WCiL misses from local IA event=0x36,umask=0xc86f0601  01    TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_partial_streaming_wr_remote_pmm uncore cache TOR Occupancy; WCiL misses from local IA event=0x36,umask=0xc86f0a01  01    TOR Occupancy; Data read from local IA that misses in the snoop filter unc_cha_tor_occupancy.ia_miss_rfo uncore cache TOR Occupancy : RFOs issued by iA Cores that Missed the LLC event=0x36,umask=0xc807fe01  01    TOR Occupancy : RFOs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_rfo_local uncore cache TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed locally event=0x36,umask=0xc806fe01  01    TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_rfo_pref uncore cache TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC event=0x36,umask=0xc887fe01  01    TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_rfo_pref_local uncore cache TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally event=0x36,umask=0xc886fe01  01    TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_rfo_pref_remote uncore cache TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely event=0x36,umask=0xc8877e01  01    TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_rfo_remote uncore cache TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed remotely event=0x36,umask=0xc8077e01  01    TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_specitom uncore cache TOR Occupancy : SpecItoMs issued by iA Cores that missed the LLC event=0x36,umask=0xcc57fe01  01    TOR Occupancy : SpecItoMs issued by iA Cores that missed the LLC: For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_rfo uncore cache TOR Occupancy : RFOs issued by iA Cores event=0x36,umask=0xc807ff01  01    TOR Occupancy : RFOs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_rfo_pref uncore cache TOR Occupancy : RFO_Prefs issued by iA Cores event=0x36,umask=0xc887ff01  01    TOR Occupancy : RFO_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io uncore cache TOR Occupancy : All requests from IO Devices event=0x36,umask=0xc001ff04  01    TOR Occupancy : All requests from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_hit uncore cache TOR Occupancy : All requests from IO Devices that hit the LLC event=0x36,umask=0xc001fd04  01    TOR Occupancy : All requests from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_hit_itom uncore cache TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC event=0x36,umask=0xcc43fd04  01    TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_hit_pcirdcur uncore cache TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC event=0x36,umask=0xc8f3fd04  01    TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_hit_rfo uncore cache TOR Occupancy : RFOs issued by IO Devices that hit the LLC event=0x36,umask=0xc803fd04  01    TOR Occupancy : RFOs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_itom uncore cache TOR Occupancy : ItoMs issued by IO Devices event=0x36,umask=0xcc43ff04  01    TOR Occupancy : ItoMs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss uncore cache TOR Occupancy : All requests from IO Devices that missed the LLC event=0x36,umask=0xc001fe04  01    TOR Occupancy : All requests from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_itom uncore cache TOR Occupancy : ItoMs issued by IO Devices that missed the LLC event=0x36,umask=0xcc43fe04  01    TOR Occupancy : ItoMs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_pcirdcur uncore cache TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC event=0x36,umask=0xc8f3fe04  01    TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_miss_rfo uncore cache TOR Occupancy : RFOs issued by IO Devices that missed the LLC event=0x36,umask=0xc803fe04  01    TOR Occupancy : RFOs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_pcirdcur uncore cache TOR Occupancy : PCIRdCurs issued by IO Devices event=0x36,umask=0xc8f3ff04  01    TOR Occupancy : PCIRdCurs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.io_rfo uncore cache TOR Occupancy : RFOs issued by IO Devices event=0x36,umask=0xc803ff04  01    TOR Occupancy : RFOs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ipq uncore cache TOR Occupancy : IPQ event=0x36,umask=8  01    TOR Occupancy : IPQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.irq_ia uncore cache TOR Occupancy : IRQ - iA event=0x36,umask=1  01    TOR Occupancy : IRQ - iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts. : From an iA Core unc_cha_tor_occupancy.irq_non_ia uncore cache TOR Occupancy : IRQ - Non iA event=0x36,umask=0x10  01    TOR Occupancy : IRQ - Non iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.isoc uncore cache TOR Occupancy : Just ISOC event=0x36  01    TOR Occupancy : Just ISOC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.local_tgt uncore cache TOR Occupancy : Just Local Targets event=0x36  01    TOR Occupancy : Just Local Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.loc_all uncore cache TOR Occupancy : All from Local iA and IO event=0x36,umask=0xc000ff05  01    TOR Occupancy : All from Local iA and IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts. : All locally initiated requests unc_cha_tor_occupancy.loc_ia uncore cache TOR Occupancy : All from Local iA event=0x36,umask=0xc000ff01  01    TOR Occupancy : All from Local iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts. : All locally initiated requests from iA Cores unc_cha_tor_occupancy.loc_io uncore cache TOR Occupancy : All from Local IO event=0x36,umask=0xc000ff04  01    TOR Occupancy : All from Local IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts. : All locally generated IO traffic unc_cha_tor_occupancy.match_opc uncore cache TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field event=0x36  01    TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.miss uncore cache TOR Occupancy : Just Misses event=0x36  01    TOR Occupancy : Just Misses : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.mmcfg uncore cache TOR Occupancy : MMCFG Access event=0x36  01    TOR Occupancy : MMCFG Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.nearmem uncore cache TOR Occupancy : Just NearMem event=0x36  01    TOR Occupancy : Just NearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.noncoh uncore cache TOR Occupancy : Just NonCoherent event=0x36  01    TOR Occupancy : Just NonCoherent : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.not_nearmem uncore cache TOR Occupancy : Just NotNearMem event=0x36  01    TOR Occupancy : Just NotNearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.pmm uncore cache TOR Occupancy : PMM Access event=0x36  01    TOR Occupancy : PMM Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.premorph_opc uncore cache TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field event=0x36  01    TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.prq uncore cache TOR Occupancy : PRQ - IOSF event=0x36,umask=4  01    TOR Occupancy : PRQ - IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts. : From a PCIe Device unc_cha_tor_occupancy.prq_non_iosf uncore cache TOR Occupancy : PRQ - Non IOSF event=0x36,umask=0x20  01    TOR Occupancy : PRQ - Non IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.remote_tgt uncore cache TOR Occupancy : Just Remote Targets event=0x36  01    TOR Occupancy : Just Remote Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts unc_cha_txr_horz_ads_used.ad_all uncore cache CMS Horizontal ADS Used : AD - All event=0xa6,umask=0x11  01    CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_cha_txr_horz_ads_used.ad_crd uncore cache CMS Horizontal ADS Used : AD - Credited event=0xa6,umask=0x10  01    CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_horz_ads_used.ad_uncrd uncore cache CMS Horizontal ADS Used : AD - Uncredited event=0xa6,umask=1  01    CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_horz_ads_used.bl_all uncore cache CMS Horizontal ADS Used : BL - All event=0xa6,umask=0x44  01    CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_cha_txr_horz_ads_used.bl_crd uncore cache CMS Horizontal ADS Used : BL - Credited event=0xa6,umask=0x40  01    CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_horz_ads_used.bl_uncrd uncore cache CMS Horizontal ADS Used : BL - Uncredited event=0xa6,umask=4  01    CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.ad_all uncore cache CMS Horizontal Bypass Used : AD - All event=0xa7,umask=0x11  01    CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_cha_txr_horz_bypass.ad_crd uncore cache CMS Horizontal Bypass Used : AD - Credited event=0xa7,umask=0x10  01    CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.ad_uncrd uncore cache CMS Horizontal Bypass Used : AD - Uncredited event=0xa7,umask=1  01    CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.ak uncore cache CMS Horizontal Bypass Used : AK event=0xa7,umask=2  01    CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.akc_uncrd uncore cache CMS Horizontal Bypass Used : AKC - Uncredited event=0xa7,umask=0x80  01    CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.bl_all uncore cache CMS Horizontal Bypass Used : BL - All event=0xa7,umask=0x44  01    CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_cha_txr_horz_bypass.bl_crd uncore cache CMS Horizontal Bypass Used : BL - Credited event=0xa7,umask=0x40  01    CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.bl_uncrd uncore cache CMS Horizontal Bypass Used : BL - Uncredited event=0xa7,umask=4  01    CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_bypass.iv uncore cache CMS Horizontal Bypass Used : IV event=0xa7,umask=8  01    CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_cha_txr_horz_cycles_full.ad_all uncore cache Cycles CMS Horizontal Egress Queue is Full : AD - All event=0xa2,umask=0x11  01    Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_cha_txr_horz_cycles_full.ad_crd uncore cache Cycles CMS Horizontal Egress Queue is Full : AD - Credited event=0xa2,umask=0x10  01    Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.ad_uncrd uncore cache Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited event=0xa2,umask=1  01    Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.ak uncore cache Cycles CMS Horizontal Egress Queue is Full : AK event=0xa2,umask=2  01    Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.akc_uncrd uncore cache Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited event=0xa2,umask=0x80  01    Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.bl_all uncore cache Cycles CMS Horizontal Egress Queue is Full : BL - All event=0xa2,umask=0x44  01    Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_cha_txr_horz_cycles_full.bl_crd uncore cache Cycles CMS Horizontal Egress Queue is Full : BL - Credited event=0xa2,umask=0x40  01    Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.bl_uncrd uncore cache Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited event=0xa2,umask=4  01    Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_full.iv uncore cache Cycles CMS Horizontal Egress Queue is Full : IV event=0xa2,umask=8  01    Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.ad_all uncore cache Cycles CMS Horizontal Egress Queue is Not Empty : AD - All event=0xa3,umask=0x11  01    Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_cha_txr_horz_cycles_ne.ad_crd uncore cache Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited event=0xa3,umask=0x10  01    Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.ad_uncrd uncore cache Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited event=0xa3,umask=1  01    Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.ak uncore cache Cycles CMS Horizontal Egress Queue is Not Empty : AK event=0xa3,umask=2  01    Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.akc_uncrd uncore cache Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited event=0xa3,umask=0x80  01    Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.bl_all uncore cache Cycles CMS Horizontal Egress Queue is Not Empty : BL - All event=0xa3,umask=0x44  01    Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_cha_txr_horz_cycles_ne.bl_crd uncore cache Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited event=0xa3,umask=0x40  01    Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.bl_uncrd uncore cache Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited event=0xa3,umask=4  01    Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_cycles_ne.iv uncore cache Cycles CMS Horizontal Egress Queue is Not Empty : IV event=0xa3,umask=8  01    Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.ad_all uncore cache CMS Horizontal Egress Inserts : AD - All event=0xa1,umask=0x11  01    CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_cha_txr_horz_inserts.ad_crd uncore cache CMS Horizontal Egress Inserts : AD - Credited event=0xa1,umask=0x10  01    CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.ad_uncrd uncore cache CMS Horizontal Egress Inserts : AD - Uncredited event=0xa1,umask=1  01    CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.ak uncore cache CMS Horizontal Egress Inserts : AK event=0xa1,umask=2  01    CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.akc_uncrd uncore cache CMS Horizontal Egress Inserts : AKC - Uncredited event=0xa1,umask=0x80  01    CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.bl_all uncore cache CMS Horizontal Egress Inserts : BL - All event=0xa1,umask=0x44  01    CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_cha_txr_horz_inserts.bl_crd uncore cache CMS Horizontal Egress Inserts : BL - Credited event=0xa1,umask=0x40  01    CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.bl_uncrd uncore cache CMS Horizontal Egress Inserts : BL - Uncredited event=0xa1,umask=4  01    CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_inserts.iv uncore cache CMS Horizontal Egress Inserts : IV event=0xa1,umask=8  01    CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_nack.ad_all uncore cache CMS Horizontal Egress NACKs : AD - All event=0xa4,umask=0x11  01    CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited unc_cha_txr_horz_nack.ad_crd uncore cache CMS Horizontal Egress NACKs : AD - Credited event=0xa4,umask=0x10  01    CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.ad_uncrd uncore cache CMS Horizontal Egress NACKs : AD - Uncredited event=0xa4,umask=1  01    CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.ak uncore cache CMS Horizontal Egress NACKs : AK event=0xa4,umask=2  01    CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.akc_uncrd uncore cache CMS Horizontal Egress NACKs : AKC - Uncredited event=0xa4,umask=0x80  01    CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.bl_all uncore cache CMS Horizontal Egress NACKs : BL - All event=0xa4,umask=0x44  01    CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited unc_cha_txr_horz_nack.bl_crd uncore cache CMS Horizontal Egress NACKs : BL - Credited event=0xa4,umask=0x40  01    CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.bl_uncrd uncore cache CMS Horizontal Egress NACKs : BL - Uncredited event=0xa4,umask=4  01    CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_nack.iv uncore cache CMS Horizontal Egress NACKs : IV event=0xa4,umask=8  01    CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_cha_txr_horz_occupancy.ad_all uncore cache CMS Horizontal Egress Occupancy : AD - All event=0xa0,umask=0x11  01    CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_cha_txr_horz_occupancy.ad_crd uncore cache CMS Horizontal Egress Occupancy : AD - Credited event=0xa0,umask=0x10  01    CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.ad_uncrd uncore cache CMS Horizontal Egress Occupancy : AD - Uncredited event=0xa0,umask=1  01    CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.ak uncore cache CMS Horizontal Egress Occupancy : AK event=0xa0,umask=2  01    CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.akc_uncrd uncore cache CMS Horizontal Egress Occupancy : AKC - Uncredited event=0xa0,umask=0x80  01    CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.bl_all uncore cache CMS Horizontal Egress Occupancy : BL - All event=0xa0,umask=0x44  01    CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_cha_txr_horz_occupancy.bl_crd uncore cache CMS Horizontal Egress Occupancy : BL - Credited event=0xa0,umask=0x40  01    CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.bl_uncrd uncore cache CMS Horizontal Egress Occupancy : BL - Uncredited event=0xa0,umask=4  01    CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_occupancy.iv uncore cache CMS Horizontal Egress Occupancy : IV event=0xa0,umask=8  01    CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_cha_txr_horz_starved.ad_all uncore cache CMS Horizontal Egress Injection Starvation : AD - All event=0xa5,umask=1  01    CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited unc_cha_txr_horz_starved.ad_uncrd uncore cache CMS Horizontal Egress Injection Starvation : AD - Uncredited event=0xa5,umask=1  01    CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_cha_txr_horz_starved.ak uncore cache CMS Horizontal Egress Injection Starvation : AK event=0xa5,umask=2  01    CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_cha_txr_horz_starved.akc_uncrd uncore cache CMS Horizontal Egress Injection Starvation : AKC - Uncredited event=0xa5,umask=0x80  01    CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_cha_txr_horz_starved.bl_all uncore cache CMS Horizontal Egress Injection Starvation : BL - All event=0xa5,umask=4  01    CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited unc_cha_txr_horz_starved.bl_uncrd uncore cache CMS Horizontal Egress Injection Starvation : BL - Uncredited event=0xa5,umask=4  01    CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_cha_txr_horz_starved.iv uncore cache CMS Horizontal Egress Injection Starvation : IV event=0xa5,umask=8  01    CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_cha_txr_vert_ads_used.ad_ag0 uncore cache CMS Vertical ADS Used : AD - Agent 0 event=0x9c,umask=1  01    CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_vert_ads_used.ad_ag1 uncore cache CMS Vertical ADS Used : AD - Agent 1 event=0x9c,umask=0x10  01    CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_vert_ads_used.bl_ag0 uncore cache CMS Vertical ADS Used : BL - Agent 0 event=0x9c,umask=4  01    CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_vert_ads_used.bl_ag1 uncore cache CMS Vertical ADS Used : BL - Agent 1 event=0x9c,umask=0x40  01    CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.ad_ag0 uncore cache CMS Vertical ADS Used : AD - Agent 0 event=0x9d,umask=1  01    CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.ad_ag1 uncore cache CMS Vertical ADS Used : AD - Agent 1 event=0x9d,umask=0x10  01    CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.ak_ag0 uncore cache CMS Vertical ADS Used : AK - Agent 0 event=0x9d,umask=2  01    CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.ak_ag1 uncore cache CMS Vertical ADS Used : AK - Agent 1 event=0x9d,umask=0x20  01    CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.bl_ag0 uncore cache CMS Vertical ADS Used : BL - Agent 0 event=0x9d,umask=4  01    CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.bl_ag1 uncore cache CMS Vertical ADS Used : BL - Agent 1 event=0x9d,umask=0x40  01    CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass.iv_ag1 uncore cache CMS Vertical ADS Used : IV - Agent 1 event=0x9d,umask=8  01    CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass_1.akc_ag0 uncore cache CMS Vertical ADS Used : AKC - Agent 0 event=0x9e,umask=1  01    CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_bypass_1.akc_ag1 uncore cache CMS Vertical ADS Used : AKC - Agent 1 event=0x9e,umask=2  01    CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_cha_txr_vert_cycles_full0.ad_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 event=0x94,umask=1  01    Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_cycles_full0.ad_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 event=0x94,umask=0x10  01    Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests unc_cha_txr_vert_cycles_full0.ak_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 event=0x94,umask=2  01    Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_cha_txr_vert_cycles_full0.ak_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 event=0x94,umask=0x20  01    Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_cha_txr_vert_cycles_full0.bl_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 event=0x94,umask=4  01    Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations unc_cha_txr_vert_cycles_full0.bl_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 event=0x94,umask=0x40  01    Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache unc_cha_txr_vert_cycles_full0.iv_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 event=0x94,umask=8  01    Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores unc_cha_txr_vert_cycles_full1.akc_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 event=0x95,umask=1  01    Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_cycles_full1.akc_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 event=0x95,umask=2  01    Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_cha_txr_vert_cycles_ne0.ad_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 event=0x96,umask=1  01    Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_cycles_ne0.ad_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 event=0x96,umask=0x10  01    Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests unc_cha_txr_vert_cycles_ne0.ak_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 event=0x96,umask=2  01    Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_cha_txr_vert_cycles_ne0.ak_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 event=0x96,umask=0x20  01    Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_cha_txr_vert_cycles_ne0.bl_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 event=0x96,umask=4  01    Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations unc_cha_txr_vert_cycles_ne0.bl_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 event=0x96,umask=0x40  01    Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache unc_cha_txr_vert_cycles_ne0.iv_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 event=0x96,umask=8  01    Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores unc_cha_txr_vert_cycles_ne1.akc_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 event=0x97,umask=1  01    Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_cycles_ne1.akc_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 event=0x97,umask=2  01    Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_cha_txr_vert_inserts0.ad_ag0 uncore cache CMS Vert Egress Allocations : AD - Agent 0 event=0x92,umask=1  01    CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_inserts0.ad_ag1 uncore cache CMS Vert Egress Allocations : AD - Agent 1 event=0x92,umask=0x10  01    CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests unc_cha_txr_vert_inserts0.ak_ag0 uncore cache CMS Vert Egress Allocations : AK - Agent 0 event=0x92,umask=2  01    CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_cha_txr_vert_inserts0.ak_ag1 uncore cache CMS Vert Egress Allocations : AK - Agent 1 event=0x92,umask=0x20  01    CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_cha_txr_vert_inserts0.bl_ag0 uncore cache CMS Vert Egress Allocations : BL - Agent 0 event=0x92,umask=4  01    CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations unc_cha_txr_vert_inserts0.bl_ag1 uncore cache CMS Vert Egress Allocations : BL - Agent 1 event=0x92,umask=0x40  01    CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache unc_cha_txr_vert_inserts0.iv_ag0 uncore cache CMS Vert Egress Allocations : IV - Agent 0 event=0x92,umask=8  01    CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores unc_cha_txr_vert_inserts1.akc_ag0 uncore cache CMS Vert Egress Allocations : AKC - Agent 0 event=0x93,umask=1  01    CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_inserts1.akc_ag1 uncore cache CMS Vert Egress Allocations : AKC - Agent 1 event=0x93,umask=2  01    CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_cha_txr_vert_nack0.ad_ag0 uncore cache CMS Vertical Egress NACKs : AD - Agent 0 event=0x98,umask=1  01    CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack0.ad_ag1 uncore cache CMS Vertical Egress NACKs : AD - Agent 1 event=0x98,umask=0x10  01    CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack0.ak_ag0 uncore cache CMS Vertical Egress NACKs : AK - Agent 0 event=0x98,umask=2  01    CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack0.ak_ag1 uncore cache CMS Vertical Egress NACKs : AK - Agent 1 event=0x98,umask=0x20  01    CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack0.bl_ag0 uncore cache CMS Vertical Egress NACKs : BL - Agent 0 event=0x98,umask=4  01    CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack0.bl_ag1 uncore cache CMS Vertical Egress NACKs : BL - Agent 1 event=0x98,umask=0x40  01    CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack0.iv_ag0 uncore cache CMS Vertical Egress NACKs : IV event=0x98,umask=8  01    CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack1.akc_ag0 uncore cache CMS Vertical Egress NACKs : AKC - Agent 0 event=0x99,umask=1  01    CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_nack1.akc_ag1 uncore cache CMS Vertical Egress NACKs : AKC - Agent 1 event=0x99,umask=2  01    CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_cha_txr_vert_occupancy0.ad_ag0 uncore cache CMS Vert Egress Occupancy : AD - Agent 0 event=0x90,umask=1  01    CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_occupancy0.ad_ag1 uncore cache CMS Vert Egress Occupancy : AD - Agent 1 event=0x90,umask=0x10  01    CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests unc_cha_txr_vert_occupancy0.ak_ag0 uncore cache CMS Vert Egress Occupancy : AK - Agent 0 event=0x90,umask=2  01    CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_cha_txr_vert_occupancy0.ak_ag1 uncore cache CMS Vert Egress Occupancy : AK - Agent 1 event=0x90,umask=0x20  01    CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_cha_txr_vert_occupancy0.bl_ag0 uncore cache CMS Vert Egress Occupancy : BL - Agent 0 event=0x90,umask=4  01    CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations unc_cha_txr_vert_occupancy0.bl_ag1 uncore cache CMS Vert Egress Occupancy : BL - Agent 1 event=0x90,umask=0x40  01    CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache unc_cha_txr_vert_occupancy0.iv_ag0 uncore cache CMS Vert Egress Occupancy : IV - Agent 0 event=0x90,umask=8  01    CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores unc_cha_txr_vert_occupancy1.akc_ag0 uncore cache CMS Vert Egress Occupancy : AKC - Agent 0 event=0x91,umask=1  01    CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_cha_txr_vert_occupancy1.akc_ag1 uncore cache CMS Vert Egress Occupancy : AKC - Agent 1 event=0x91,umask=2  01    CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_cha_txr_vert_starved0.ad_ag0 uncore cache CMS Vertical Egress Injection Starvation : AD - Agent 0 event=0x9a,umask=1  01    CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved0.ad_ag1 uncore cache CMS Vertical Egress Injection Starvation : AD - Agent 1 event=0x9a,umask=0x10  01    CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved0.ak_ag0 uncore cache CMS Vertical Egress Injection Starvation : AK - Agent 0 event=0x9a,umask=2  01    CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved0.ak_ag1 uncore cache CMS Vertical Egress Injection Starvation : AK - Agent 1 event=0x9a,umask=0x20  01    CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved0.bl_ag0 uncore cache CMS Vertical Egress Injection Starvation : BL - Agent 0 event=0x9a,umask=4  01    CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved0.bl_ag1 uncore cache CMS Vertical Egress Injection Starvation : BL - Agent 1 event=0x9a,umask=0x40  01    CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved0.iv_ag0 uncore cache CMS Vertical Egress Injection Starvation : IV event=0x9a,umask=8  01    CMS Vertical Egress Injection Starvation : IV : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved1.akc_ag0 uncore cache CMS Vertical Egress Injection Starvation : AKC - Agent 0 event=0x9b,umask=1  01    CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved1.akc_ag1 uncore cache CMS Vertical Egress Injection Starvation : AKC - Agent 1 event=0x9b,umask=2  01    CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_txr_vert_starved1.tgc uncore cache CMS Vertical Egress Injection Starvation : AKC - Agent 0 event=0x9b,umask=4  01    CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_cha_vert_ring_ad_in_use.dn_even uncore cache Vertical AD Ring In Use : Down and Even event=0xb0,umask=4  01    Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ad_in_use.dn_odd uncore cache Vertical AD Ring In Use : Down and Odd event=0xb0,umask=8  01    Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ad_in_use.up_even uncore cache Vertical AD Ring In Use : Up and Even event=0xb0,umask=1  01    Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ad_in_use.up_odd uncore cache Vertical AD Ring In Use : Up and Odd event=0xb0,umask=2  01    Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_akc_in_use.dn_even uncore cache Vertical AKC Ring In Use : Down and Even event=0xb4,umask=4  01    Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_akc_in_use.dn_odd uncore cache Vertical AKC Ring In Use : Down and Odd event=0xb4,umask=8  01    Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_akc_in_use.up_even uncore cache Vertical AKC Ring In Use : Up and Even event=0xb4,umask=1  01    Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_akc_in_use.up_odd uncore cache Vertical AKC Ring In Use : Up and Odd event=0xb4,umask=2  01    Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ak_in_use.dn_even uncore cache Vertical AK Ring In Use : Down and Even event=0xb1,umask=4  01    Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ak_in_use.dn_odd uncore cache Vertical AK Ring In Use : Down and Odd event=0xb1,umask=8  01    Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ak_in_use.up_even uncore cache Vertical AK Ring In Use : Up and Even event=0xb1,umask=1  01    Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_ak_in_use.up_odd uncore cache Vertical AK Ring In Use : Up and Odd event=0xb1,umask=2  01    Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_bl_in_use.dn_even uncore cache Vertical BL Ring in Use : Down and Even event=0xb2,umask=4  01    Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_bl_in_use.dn_odd uncore cache Vertical BL Ring in Use : Down and Odd event=0xb2,umask=8  01    Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_bl_in_use.up_even uncore cache Vertical BL Ring in Use : Up and Even event=0xb2,umask=1  01    Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_bl_in_use.up_odd uncore cache Vertical BL Ring in Use : Up and Odd event=0xb2,umask=2  01    Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_iv_in_use.dn uncore cache Vertical IV Ring in Use : Down event=0xb3,umask=4  01    Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_cha_vert_ring_iv_in_use.up uncore cache Vertical IV Ring in Use : Up event=0xb3,umask=1  01    Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_cha_vert_ring_tgc_in_use.dn_even uncore cache Vertical TGC Ring In Use : Down and Even event=0xb5,umask=4  01    Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_tgc_in_use.dn_odd uncore cache Vertical TGC Ring In Use : Down and Odd event=0xb5,umask=8  01    Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_tgc_in_use.up_even uncore cache Vertical TGC Ring In Use : Up and Even event=0xb5,umask=1  01    Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_vert_ring_tgc_in_use.up_odd uncore cache Vertical TGC Ring In Use : Up and Odd event=0xb5,umask=2  01    Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_cha_write_no_credits.mc10 uncore cache CHA iMC CHNx WRITE Credits Empty : MC10 event=0x5a  01    CHA iMC CHNx WRITE Credits Empty : MC10 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 10 only unc_cha_write_no_credits.mc11 uncore cache CHA iMC CHNx WRITE Credits Empty : MC11 event=0x5a  01    CHA iMC CHNx WRITE Credits Empty : MC11 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 11 only unc_cha_write_no_credits.mc12 uncore cache CHA iMC CHNx WRITE Credits Empty : MC12 event=0x5a  01    CHA iMC CHNx WRITE Credits Empty : MC12 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 12 only unc_cha_write_no_credits.mc13 uncore cache CHA iMC CHNx WRITE Credits Empty : MC13 event=0x5a  01    CHA iMC CHNx WRITE Credits Empty : MC13 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 13 only unc_cha_write_no_credits.mc6 uncore cache CHA iMC CHNx WRITE Credits Empty : MC6 event=0x5a,umask=0x40  01    CHA iMC CHNx WRITE Credits Empty : MC6 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 6 only unc_cha_write_no_credits.mc7 uncore cache CHA iMC CHNx WRITE Credits Empty : MC7 event=0x5a,umask=0x80  01    CHA iMC CHNx WRITE Credits Empty : MC7 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 7 only unc_cha_write_no_credits.mc8 uncore cache CHA iMC CHNx WRITE Credits Empty : MC8 event=0x5a  01    CHA iMC CHNx WRITE Credits Empty : MC8 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 8 only unc_cha_write_no_credits.mc9 uncore cache CHA iMC CHNx WRITE Credits Empty : MC9 event=0x5a  01    CHA iMC CHNx WRITE Credits Empty : MC9 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 9 only unc_i_cache_total_occupancy.any uncore interconnect Total Write Cache Occupancy : Any Source event=0xf,umask=1  01    Total Write Cache Occupancy : Any Source : Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events. : Tracks all requests from any source port unc_i_cache_total_occupancy.iv_q uncore interconnect Total Write Cache Occupancy : Snoops event=0xf,umask=2  01    Total Write Cache Occupancy : Snoops : Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events unc_i_clockticks uncore interconnect Clockticks of the IO coherency tracker (IRP) event=1  01     unc_i_coherent_ops.clflush uncore interconnect Coherent Ops : CLFlush event=0x10,umask=0x80  01    Coherent Ops : CLFlush : Counts the number of coherency related operations serviced by the IRP unc_i_coherent_ops.wbmtoi uncore interconnect Coherent Ops : WbMtoI event=0x10,umask=0x40  01    Coherent Ops : WbMtoI : Counts the number of coherency related operations serviced by the IRP unc_i_p2p_inserts uncore interconnect P2P Requests event=0x14  01    P2P Requests : P2P requests from the ITC unc_i_p2p_occupancy uncore interconnect P2P Occupancy event=0x15  01    P2P Occupancy : P2P B & S Queue Occupancy unc_i_p2p_transactions.cmpl uncore interconnect P2P Transactions : P2P completions event=0x13,umask=8  01     unc_i_p2p_transactions.loc uncore interconnect P2P Transactions : match if local only event=0x13,umask=0x40  01     unc_i_p2p_transactions.loc_and_tgt_match uncore interconnect P2P Transactions : match if local and target matches event=0x13,umask=0x80  01     unc_i_p2p_transactions.msg uncore interconnect P2P Transactions : P2P Message event=0x13,umask=4  01     unc_i_p2p_transactions.rd uncore interconnect P2P Transactions : P2P reads event=0x13,umask=1  01     unc_i_p2p_transactions.rem uncore interconnect P2P Transactions : Match if remote only event=0x13,umask=0x10  01     unc_i_p2p_transactions.rem_and_tgt_match uncore interconnect P2P Transactions : match if remote and target matches event=0x13,umask=0x20  01     unc_i_p2p_transactions.wr uncore interconnect P2P Transactions : P2P Writes event=0x13,umask=2  01     unc_i_transactions.atomic uncore interconnect Inbound Transaction Count : Atomic event=0x11,umask=0x10  01    Inbound Transaction Count : Atomic : Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks the number of atomic transactions unc_i_transactions.other uncore interconnect Inbound Transaction Count : Other event=0x11,umask=0x20  01    Inbound Transaction Count : Other : Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks the number of 'other' kinds of transactions unc_i_transactions.writes uncore interconnect Inbound Transaction Count : Writes event=0x11,umask=2  01    Inbound Transaction Count : Writes : Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks only write requests.  Each write request should have a prefetch, so there is no need to explicitly track these requests.  For writes that are tickled and have to retry, the counter will be incremented for each retry unc_i_txr2_ad01_stall_credit_cycles uncore interconnect UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES event=0x1c  01    : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no Egress Credits available on AD0, A1 or AD0&AD1 both. Stalls on both AD0 and AD1 will count as 2 unc_m2m_ag0_ad_crd_acquired0.tgr0 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 0 event=0x80,umask=1  01    CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired0.tgr1 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 1 event=0x80,umask=2  01    CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired0.tgr2 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 2 event=0x80,umask=4  01    CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired0.tgr3 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 3 event=0x80,umask=8  01    CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired0.tgr4 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 4 event=0x80,umask=0x10  01    CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired0.tgr5 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 5 event=0x80,umask=0x20  01    CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired0.tgr6 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 6 event=0x80,umask=0x40  01    CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired0.tgr7 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 7 event=0x80,umask=0x80  01    CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired1.tgr10 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 10 event=0x81,umask=4  01    CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired1.tgr8 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 8 event=0x81,umask=1  01    CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_acquired1.tgr9 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 9 event=0x81,umask=2  01    CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy0.tgr0 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 0 event=0x82,umask=1  01    CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy0.tgr1 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 1 event=0x82,umask=2  01    CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy0.tgr2 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 2 event=0x82,umask=4  01    CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy0.tgr3 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 3 event=0x82,umask=8  01    CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy0.tgr4 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 4 event=0x82,umask=0x10  01    CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy0.tgr5 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 5 event=0x82,umask=0x20  01    CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy0.tgr6 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 6 event=0x82,umask=0x40  01    CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy0.tgr7 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 7 event=0x82,umask=0x80  01    CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy1.tgr10 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 10 event=0x83,umask=4  01    CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy1.tgr8 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 8 event=0x83,umask=1  01    CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_ad_crd_occupancy1.tgr9 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 9 event=0x83,umask=2  01    CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired0.tgr0 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 0 event=0x88,umask=1  01    CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired0.tgr1 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 1 event=0x88,umask=2  01    CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired0.tgr2 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 2 event=0x88,umask=4  01    CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired0.tgr3 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 3 event=0x88,umask=8  01    CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired0.tgr4 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 4 event=0x88,umask=0x10  01    CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired0.tgr5 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 5 event=0x88,umask=0x20  01    CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired0.tgr6 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 6 event=0x88,umask=0x40  01    CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired0.tgr7 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 7 event=0x88,umask=0x80  01    CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired1.tgr10 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 10 event=0x89,umask=4  01    CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired1.tgr8 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 8 event=0x89,umask=1  01    CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_acquired1.tgr9 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 9 event=0x89,umask=2  01    CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy0.tgr0 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 0 event=0x8a,umask=1  01    CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy0.tgr1 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 1 event=0x8a,umask=2  01    CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy0.tgr2 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 2 event=0x8a,umask=4  01    CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy0.tgr3 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 3 event=0x8a,umask=8  01    CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy0.tgr4 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 4 event=0x8a,umask=0x10  01    CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy0.tgr5 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 5 event=0x8a,umask=0x20  01    CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy0.tgr6 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 6 event=0x8a,umask=0x40  01    CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy0.tgr7 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 7 event=0x8a,umask=0x80  01    CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy1.tgr10 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 10 event=0x8b,umask=4  01    CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy1.tgr8 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 8 event=0x8b,umask=1  01    CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag0_bl_crd_occupancy1.tgr9 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 9 event=0x8b,umask=2  01    CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired0.tgr0 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 0 event=0x84,umask=1  01    CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired0.tgr1 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 1 event=0x84,umask=2  01    CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired0.tgr2 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 2 event=0x84,umask=4  01    CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired0.tgr3 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 3 event=0x84,umask=8  01    CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired0.tgr4 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 4 event=0x84,umask=0x10  01    CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired0.tgr5 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 5 event=0x84,umask=0x20  01    CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired0.tgr6 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 6 event=0x84,umask=0x40  01    CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired0.tgr7 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 7 event=0x84,umask=0x80  01    CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired1.tgr10 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 10 event=0x85,umask=4  01    CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired1.tgr8 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 8 event=0x85,umask=1  01    CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_acquired1.tgr9 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 9 event=0x85,umask=2  01    CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy0.tgr0 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 0 event=0x86,umask=1  01    CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy0.tgr1 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 1 event=0x86,umask=2  01    CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy0.tgr2 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 2 event=0x86,umask=4  01    CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy0.tgr3 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 3 event=0x86,umask=8  01    CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy0.tgr4 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 4 event=0x86,umask=0x10  01    CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy0.tgr5 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 5 event=0x86,umask=0x20  01    CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy0.tgr6 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 6 event=0x86,umask=0x40  01    CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy0.tgr7 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 7 event=0x86,umask=0x80  01    CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy1.tgr10 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 10 event=0x87,umask=4  01    CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy1.tgr8 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 8 event=0x87,umask=1  01    CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_ad_crd_occupancy1.tgr9 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 9 event=0x87,umask=2  01    CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired0.tgr0 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 0 event=0x8c,umask=1  01    CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired0.tgr1 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 1 event=0x8c,umask=2  01    CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired0.tgr2 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 2 event=0x8c,umask=4  01    CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired0.tgr3 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 3 event=0x8c,umask=8  01    CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired0.tgr4 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 4 event=0x8c,umask=0x10  01    CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired0.tgr5 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 5 event=0x8c,umask=0x20  01    CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired0.tgr6 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 4 event=0x8c,umask=0x40  01    CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired0.tgr7 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 5 event=0x8c,umask=0x80  01    CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired1.tgr10 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 10 event=0x8d,umask=4  01    CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired1.tgr8 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 8 event=0x8d,umask=1  01    CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_acquired1.tgr9 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 9 event=0x8d,umask=2  01    CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy0.tgr0 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 0 event=0x8e,umask=1  01    CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy0.tgr1 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 1 event=0x8e,umask=2  01    CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy0.tgr2 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 2 event=0x8e,umask=4  01    CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy0.tgr3 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 3 event=0x8e,umask=8  01    CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy0.tgr4 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 4 event=0x8e,umask=0x10  01    CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy0.tgr5 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 5 event=0x8e,umask=0x20  01    CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy0.tgr6 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 6 event=0x8e,umask=0x40  01    CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy0.tgr7 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 7 event=0x8e,umask=0x80  01    CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy1.tgr10 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 10 event=0x8f,umask=4  01    CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy1.tgr8 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 8 event=0x8f,umask=1  01    CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_ag1_bl_crd_occupancy1.tgr9 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 9 event=0x8f,umask=2  01    CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2m_bypass_m2m_egress.not_taken uncore interconnect M2M to iMC Bypass : Not Taken event=0x22,umask=2  01     unc_m2m_bypass_m2m_egress.taken uncore interconnect M2M to iMC Bypass : Taken event=0x22,umask=1  01     unc_m2m_bypass_m2m_ingress.not_taken uncore interconnect M2M to iMC Bypass : Not Taken event=0x21,umask=2  01     unc_m2m_bypass_m2m_ingress.taken uncore interconnect M2M to iMC Bypass : Taken event=0x21,umask=1  01     unc_m2m_clockticks uncore interconnect Clockticks of the mesh to memory (M2M) event=0  01     unc_m2m_direct2core_not_taken_dirstate uncore interconnect Cycles when direct to core mode, which bypasses the CHA, was disabled event=0x24  01     unc_m2m_direct2core_not_taken_notforked uncore interconnect UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED event=0x60  01     unc_m2m_direct2core_txn_override uncore interconnect Number of reads in which direct to core transaction was overridden event=0x25  01     unc_m2m_direct2upi_not_taken_credits uncore interconnect Number of reads in which direct to Intel UPI transactions were overridden event=0x28  01     unc_m2m_direct2upi_not_taken_dirstate uncore interconnect Cycles when Direct2UPI was Disabled event=0x27  01     unc_m2m_direct2upi_txn_override uncore interconnect Number of reads that a message sent direct2 Intel UPI was overridden event=0x29  01    Clockticks of the mesh to PCI (M2P) unc_m2m_directory_hit.clean_a uncore interconnect Directory Hit : On NonDirty Line in A State event=0x2a,umask=0x80  01     unc_m2m_directory_hit.clean_i uncore interconnect Directory Hit : On NonDirty Line in I State event=0x2a,umask=0x10  01     unc_m2m_directory_hit.clean_p uncore interconnect Directory Hit : On NonDirty Line in L State event=0x2a,umask=0x40  01     unc_m2m_directory_hit.clean_s uncore interconnect Directory Hit : On NonDirty Line in S State event=0x2a,umask=0x20  01     unc_m2m_directory_hit.dirty_a uncore interconnect Directory Hit : On Dirty Line in A State event=0x2a,umask=8  01     unc_m2m_directory_hit.dirty_i uncore interconnect Directory Hit : On Dirty Line in I State event=0x2a,umask=1  01     unc_m2m_directory_hit.dirty_p uncore interconnect Directory Hit : On Dirty Line in L State event=0x2a,umask=4  01     unc_m2m_directory_hit.dirty_s uncore interconnect Directory Hit : On Dirty Line in S State event=0x2a,umask=2  01     unc_m2m_directory_lookup.any uncore interconnect Multi-socket cacheline Directory Lookups : Found in any state event=0x2d,umask=1  01     unc_m2m_directory_lookup.state_a uncore interconnect Multi-socket cacheline Directory Lookups : Found in A state event=0x2d,umask=8  01     unc_m2m_directory_lookup.state_i uncore interconnect Multi-socket cacheline Directory Lookups : Found in I state event=0x2d,umask=2  01     unc_m2m_directory_lookup.state_s uncore interconnect Multi-socket cacheline Directory Lookups : Found in S state event=0x2d,umask=4  01     unc_m2m_directory_miss.clean_a uncore interconnect Directory Miss : On NonDirty Line in A State event=0x2b,umask=0x80  01     unc_m2m_directory_miss.clean_i uncore interconnect Directory Miss : On NonDirty Line in I State event=0x2b,umask=0x10  01     unc_m2m_directory_miss.clean_p uncore interconnect Directory Miss : On NonDirty Line in L State event=0x2b,umask=0x40  01     unc_m2m_directory_miss.clean_s uncore interconnect Directory Miss : On NonDirty Line in S State event=0x2b,umask=0x20  01     unc_m2m_directory_miss.dirty_a uncore interconnect Directory Miss : On Dirty Line in A State event=0x2b,umask=8  01     unc_m2m_directory_miss.dirty_i uncore interconnect Directory Miss : On Dirty Line in I State event=0x2b,umask=1  01     unc_m2m_directory_miss.dirty_p uncore interconnect Directory Miss : On Dirty Line in L State event=0x2b,umask=4  01     unc_m2m_directory_miss.dirty_s uncore interconnect Directory Miss : On Dirty Line in S State event=0x2b,umask=2  01     unc_m2m_directory_update.any uncore interconnect Multi-socket cacheline Directory Updates : From/to any state. Note: event counts are incorrect in 2LM mode event=0x2e,umask=1  01     unc_m2m_distress_asserted.dpt_local uncore interconnect Distress signal asserted : DPT Local event=0xaf,umask=4  01    Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile unc_m2m_distress_asserted.dpt_nonlocal uncore interconnect Distress signal asserted : DPT Remote event=0xaf,umask=8  01    Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile unc_m2m_distress_asserted.dpt_stall_iv uncore interconnect Distress signal asserted : DPT Stalled - IV event=0xaf,umask=0x40  01    Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled unc_m2m_distress_asserted.dpt_stall_nocrd uncore interconnect Distress signal asserted : DPT Stalled -  No Credit event=0xaf,umask=0x80  01    Distress signal asserted : DPT Stalled -  No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled unc_m2m_distress_asserted.horz uncore interconnect Distress signal asserted : Horizontal event=0xaf,umask=2  01    Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions unc_m2m_distress_asserted.pmm_local uncore interconnect Distress signal asserted : PMM Local event=0xaf,umask=0x10  01    Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic unc_m2m_distress_asserted.pmm_nonlocal uncore interconnect Distress signal asserted : PMM Remote event=0xaf,umask=0x20  01    Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic unc_m2m_distress_asserted.vert uncore interconnect Distress signal asserted : Vertical event=0xaf,umask=1  01    Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions unc_m2m_distress_pmm uncore interconnect UNC_M2M_DISTRESS_PMM event=0xf2  01     unc_m2m_distress_pmm_memmode uncore interconnect UNC_M2M_DISTRESS_PMM_MEMMODE event=0xf1  01     unc_m2m_egress_ordering.iv_snoopgo_dn uncore interconnect Egress Blocking due to Ordering requirements : Down event=0xba,umask=4  01    Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m2m_egress_ordering.iv_snoopgo_up uncore interconnect Egress Blocking due to Ordering requirements : Up event=0xba,umask=1  01    Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements unc_m2m_horz_ring_ad_in_use.left_even uncore interconnect Horizontal AD Ring In Use : Left and Even event=0xb6,umask=1  01    Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ad_in_use.left_odd uncore interconnect Horizontal AD Ring In Use : Left and Odd event=0xb6,umask=2  01    Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ad_in_use.right_even uncore interconnect Horizontal AD Ring In Use : Right and Even event=0xb6,umask=4  01    Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ad_in_use.right_odd uncore interconnect Horizontal AD Ring In Use : Right and Odd event=0xb6,umask=8  01    Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_akc_in_use.left_even uncore interconnect Horizontal AK Ring In Use : Left and Even event=0xbb,umask=1  01    Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_akc_in_use.left_odd uncore interconnect Horizontal AK Ring In Use : Left and Odd event=0xbb,umask=2  01    Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_akc_in_use.right_even uncore interconnect Horizontal AK Ring In Use : Right and Even event=0xbb,umask=4  01    Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_akc_in_use.right_odd uncore interconnect Horizontal AK Ring In Use : Right and Odd event=0xbb,umask=8  01    Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ak_in_use.left_even uncore interconnect Horizontal AK Ring In Use : Left and Even event=0xb7,umask=1  01    Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ak_in_use.left_odd uncore interconnect Horizontal AK Ring In Use : Left and Odd event=0xb7,umask=2  01    Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ak_in_use.right_even uncore interconnect Horizontal AK Ring In Use : Right and Even event=0xb7,umask=4  01    Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_ak_in_use.right_odd uncore interconnect Horizontal AK Ring In Use : Right and Odd event=0xb7,umask=8  01    Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_bl_in_use.left_even uncore interconnect Horizontal BL Ring in Use : Left and Even event=0xb8,umask=1  01    Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_bl_in_use.left_odd uncore interconnect Horizontal BL Ring in Use : Left and Odd event=0xb8,umask=2  01    Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_bl_in_use.right_even uncore interconnect Horizontal BL Ring in Use : Right and Even event=0xb8,umask=4  01    Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_bl_in_use.right_odd uncore interconnect Horizontal BL Ring in Use : Right and Odd event=0xb8,umask=8  01    Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_horz_ring_iv_in_use.left uncore interconnect Horizontal IV Ring in Use : Left event=0xb9,umask=1  01    Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2m_horz_ring_iv_in_use.right uncore interconnect Horizontal IV Ring in Use : Right event=0xb9,umask=4  01    Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2m_imc_reads.all uncore interconnect M2M Reads Issued to iMC : All, regardless of priority. - All Channels event=0x37,umask=0x704  01     unc_m2m_imc_reads.ch0_all uncore interconnect M2M Reads Issued to iMC : All, regardless of priority. - Ch0 event=0x37,umask=0x104  01     unc_m2m_imc_reads.ch0_from_tgr uncore interconnect M2M Reads Issued to iMC : From TGR - Ch0 event=0x37,umask=0x140  01     unc_m2m_imc_reads.ch0_isoch uncore interconnect M2M Reads Issued to iMC : Critical Priority - Ch0 event=0x37,umask=0x102  01     unc_m2m_imc_reads.ch0_normal uncore interconnect M2M Reads Issued to iMC : Normal Priority - Ch0 event=0x37,umask=0x101  01     unc_m2m_imc_reads.ch0_to_ddr_as_cache uncore interconnect M2M Reads Issued to iMC : DDR, acting as Cache - Ch0 event=0x37,umask=0x110  01     unc_m2m_imc_reads.ch0_to_ddr_as_mem uncore interconnect M2M Reads Issued to iMC : DDR - Ch0 event=0x37,umask=0x108  01     unc_m2m_imc_reads.ch0_to_pmm uncore interconnect M2M Reads Issued to iMC : PMM - Ch0 event=0x37,umask=0x120  01    M2M Reads Issued to iMC : PMM - Ch0 : Counts all PMM dimm read requests(full line) sent from M2M to iMC unc_m2m_imc_reads.ch1_all uncore interconnect M2M Reads Issued to iMC : All, regardless of priority. - Ch1 event=0x37,umask=0x204  01     unc_m2m_imc_reads.ch1_from_tgr uncore interconnect M2M Reads Issued to iMC : From TGR - Ch1 event=0x37,umask=0x240  01     unc_m2m_imc_reads.ch1_isoch uncore interconnect M2M Reads Issued to iMC : Critical Priority - Ch1 event=0x37,umask=0x202  01     unc_m2m_imc_reads.ch1_normal uncore interconnect M2M Reads Issued to iMC : Normal Priority - Ch1 event=0x37,umask=0x201  01     unc_m2m_imc_reads.ch1_to_ddr_as_cache uncore interconnect M2M Reads Issued to iMC : DDR, acting as Cache - Ch1 event=0x37,umask=0x210  01     unc_m2m_imc_reads.ch1_to_ddr_as_mem uncore interconnect M2M Reads Issued to iMC : DDR - Ch1 event=0x37,umask=0x208  01     unc_m2m_imc_reads.ch1_to_pmm uncore interconnect M2M Reads Issued to iMC : PMM - Ch1 event=0x37,umask=0x220  01    M2M Reads Issued to iMC : PMM - Ch1 : Counts all PMM dimm read requests(full line) sent from M2M to iMC unc_m2m_imc_reads.ch2_from_tgr uncore interconnect M2M Reads Issued to iMC : From TGR - Ch2 event=0x37,umask=0x440  01     unc_m2m_imc_reads.from_tgr uncore interconnect M2M Reads Issued to iMC : From TGR - All Channels event=0x37,umask=0x740  01     unc_m2m_imc_reads.isoch uncore interconnect M2M Reads Issued to iMC : Critical Priority - All Channels event=0x37,umask=0x702  01     unc_m2m_imc_reads.normal uncore interconnect M2M Reads Issued to iMC : Normal Priority - All Channels event=0x37,umask=0x701  01     unc_m2m_imc_reads.to_ddr_as_cache uncore interconnect M2M Reads Issued to iMC : DDR, acting as Cache - All Channels event=0x37,umask=0x710  01     unc_m2m_imc_reads.to_ddr_as_mem uncore interconnect M2M Reads Issued to iMC : DDR - All Channels event=0x37,umask=0x708  01     unc_m2m_imc_reads.to_pmm uncore interconnect M2M Reads Issued to iMC : PMM - All Channels event=0x37,umask=0x720  01     unc_m2m_imc_writes.all uncore interconnect M2M Writes Issued to iMC : All Writes - All Channels event=0x38,umask=0x1c10  01     unc_m2m_imc_writes.ch0_all uncore interconnect M2M Writes Issued to iMC : All Writes - Ch0 event=0x38,umask=0x410  01     unc_m2m_imc_writes.ch0_from_tgr uncore interconnect M2M Writes Issued to iMC : From TGR - Ch0 event=0x38  01     unc_m2m_imc_writes.ch0_full uncore interconnect M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch0 event=0x38,umask=0x401  01     unc_m2m_imc_writes.ch0_full_isoch uncore interconnect M2M Writes Issued to iMC : ISOCH Full Line - Ch0 event=0x38,umask=0x404  01     unc_m2m_imc_writes.ch0_ni uncore interconnect M2M Writes Issued to iMC : Non-Inclusive - Ch0 event=0x38  01     unc_m2m_imc_writes.ch0_ni_miss uncore interconnect M2M Writes Issued to iMC : Non-Inclusive Miss - Ch0 event=0x38  01     unc_m2m_imc_writes.ch0_partial uncore interconnect M2M Writes Issued to iMC : Partial Non-ISOCH - Ch0 event=0x38,umask=0x402  01     unc_m2m_imc_writes.ch0_partial_isoch uncore interconnect M2M Writes Issued to iMC : ISOCH Partial - Ch0 event=0x38,umask=0x408  01     unc_m2m_imc_writes.ch0_to_ddr_as_cache uncore interconnect M2M Writes Issued to iMC : DDR, acting as Cache - Ch0 event=0x38,umask=0x440  01     unc_m2m_imc_writes.ch0_to_ddr_as_mem uncore interconnect M2M Writes Issued to iMC : DDR - Ch0 event=0x38,umask=0x420  01     unc_m2m_imc_writes.ch0_to_pmm uncore interconnect M2M Writes Issued to iMC : PMM - Ch0 event=0x38,umask=0x480  01    M2M Writes Issued to iMC : PMM - Ch0 : Counts all PMM dimm writes requests(full line and partial) sent from M2M to iMC unc_m2m_imc_writes.ch1_all uncore interconnect M2M Writes Issued to iMC : All Writes - Ch1 event=0x38,umask=0x810  01     unc_m2m_imc_writes.ch1_from_tgr uncore interconnect M2M Writes Issued to iMC : From TGR - Ch1 event=0x38  01     unc_m2m_imc_writes.ch1_full uncore interconnect M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch1 event=0x38,umask=0x801  01     unc_m2m_imc_writes.ch1_full_isoch uncore interconnect M2M Writes Issued to iMC : ISOCH Full Line - Ch1 event=0x38,umask=0x804  01     unc_m2m_imc_writes.ch1_ni uncore interconnect M2M Writes Issued to iMC : Non-Inclusive - Ch1 event=0x38  01     unc_m2m_imc_writes.ch1_ni_miss uncore interconnect M2M Writes Issued to iMC : Non-Inclusive Miss - Ch1 event=0x38  01     unc_m2m_imc_writes.ch1_partial uncore interconnect M2M Writes Issued to iMC : Partial Non-ISOCH - Ch1 event=0x38,umask=0x802  01     unc_m2m_imc_writes.ch1_partial_isoch uncore interconnect M2M Writes Issued to iMC : ISOCH Partial - Ch1 event=0x38,umask=0x808  01     unc_m2m_imc_writes.ch1_to_ddr_as_cache uncore interconnect M2M Writes Issued to iMC : DDR, acting as Cache - Ch1 event=0x38,umask=0x840  01     unc_m2m_imc_writes.ch1_to_ddr_as_mem uncore interconnect M2M Writes Issued to iMC : DDR - Ch1 event=0x38,umask=0x820  01     unc_m2m_imc_writes.ch1_to_pmm uncore interconnect M2M Writes Issued to iMC : PMM - Ch1 event=0x38,umask=0x880  01    M2M Writes Issued to iMC : PMM - Ch1 : Counts all PMM dimm writes requests(full line and partial) sent from M2M to iMC unc_m2m_imc_writes.from_tgr uncore interconnect M2M Writes Issued to iMC : From TGR - All Channels event=0x38  01     unc_m2m_imc_writes.full uncore interconnect M2M Writes Issued to iMC : Full Line Non-ISOCH - All Channels event=0x38,umask=0x1c01  01     unc_m2m_imc_writes.full_isoch uncore interconnect M2M Writes Issued to iMC : ISOCH Full Line - All Channels event=0x38,umask=0x1c04  01     unc_m2m_imc_writes.ni uncore interconnect M2M Writes Issued to iMC : Non-Inclusive - All Channels event=0x38  01     unc_m2m_imc_writes.ni_miss uncore interconnect M2M Writes Issued to iMC : Non-Inclusive Miss - All Channels event=0x38  01     unc_m2m_imc_writes.partial uncore interconnect M2M Writes Issued to iMC : Partial Non-ISOCH - All Channels event=0x38,umask=0x1c02  01     unc_m2m_imc_writes.partial_isoch uncore interconnect M2M Writes Issued to iMC : ISOCH Partial - All Channels event=0x38,umask=0x1c08  01     unc_m2m_imc_writes.to_ddr_as_cache uncore interconnect M2M Writes Issued to iMC : DDR, acting as Cache - All Channels event=0x38,umask=0x1c40  01     unc_m2m_imc_writes.to_ddr_as_mem uncore interconnect M2M Writes Issued to iMC : DDR - All Channels event=0x38,umask=0x1c20  01     unc_m2m_imc_writes.to_pmm uncore interconnect M2M Writes Issued to iMC : PMM - All Channels event=0x38,umask=0x1c80  01     unc_m2m_mirr_wrq_inserts uncore interconnect Write Tracker Inserts event=0x64  01     unc_m2m_mirr_wrq_occupancy uncore interconnect Write Tracker Occupancy event=0x65  01     unc_m2m_misc_external.mbe_inst0 uncore interconnect Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0 event=0xe6,umask=1  01     unc_m2m_misc_external.mbe_inst1 uncore interconnect Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1 event=0xe6,umask=2  01     unc_m2m_pkt_match.mc uncore interconnect Number Packet Header Matches : MC Match event=0x4c,umask=2  01     unc_m2m_pkt_match.mesh uncore interconnect Number Packet Header Matches : Mesh Match event=0x4c,umask=1  01     unc_m2m_prefcam_cis_drops uncore interconnect UNC_M2M_PREFCAM_CIS_DROPS event=0x73  01     unc_m2m_prefcam_cycles_full.allch uncore interconnect Prefetch CAM Cycles Full : All Channels event=0x6b,umask=7  01     unc_m2m_prefcam_cycles_full.ch0 uncore interconnect Prefetch CAM Cycles Full : Channel 0 event=0x6b,umask=1  01     unc_m2m_prefcam_cycles_full.ch1 uncore interconnect Prefetch CAM Cycles Full : Channel 1 event=0x6b,umask=2  01     unc_m2m_prefcam_cycles_full.ch2 uncore interconnect Prefetch CAM Cycles Full : Channel 2 event=0x6b,umask=4  01     unc_m2m_prefcam_cycles_ne.allch uncore interconnect Prefetch CAM Cycles Not Empty : All Channels event=0x6c,umask=7  01     unc_m2m_prefcam_cycles_ne.ch0 uncore interconnect Prefetch CAM Cycles Not Empty : Channel 0 event=0x6c,umask=1  01     unc_m2m_prefcam_cycles_ne.ch1 uncore interconnect Prefetch CAM Cycles Not Empty : Channel 1 event=0x6c,umask=2  01     unc_m2m_prefcam_cycles_ne.ch2 uncore interconnect Prefetch CAM Cycles Not Empty : Channel 2 event=0x6c,umask=4  01     unc_m2m_prefcam_deallocs.ch0_hita0_inval uncore interconnect Prefetch CAM Deallocs event=0x6e,umask=1  01     unc_m2m_prefcam_deallocs.ch0_hita1_inval uncore interconnect Prefetch CAM Deallocs event=0x6e,umask=2  01     unc_m2m_prefcam_deallocs.ch0_miss_inval uncore interconnect Prefetch CAM Deallocs event=0x6e,umask=4  01     unc_m2m_prefcam_deallocs.ch0_rsp_pdreset uncore interconnect Prefetch CAM Deallocs event=0x6e,umask=8  01     unc_m2m_prefcam_deallocs.ch1_hita0_inval uncore interconnect Prefetch CAM Deallocs event=0x6e,umask=0x10  01     unc_m2m_prefcam_deallocs.ch1_hita1_inval uncore interconnect Prefetch CAM Deallocs event=0x6e,umask=0x20  01     unc_m2m_prefcam_deallocs.ch1_miss_inval uncore interconnect Prefetch CAM Deallocs event=0x6e,umask=0x40  01     unc_m2m_prefcam_deallocs.ch1_rsp_pdreset uncore interconnect Prefetch CAM Deallocs event=0x6e,umask=0x80  01     unc_m2m_prefcam_deallocs.ch2_hita0_inval uncore interconnect Prefetch CAM Deallocs event=0x6e  01     unc_m2m_prefcam_deallocs.ch2_hita1_inval uncore interconnect Prefetch CAM Deallocs event=0x6e  01     unc_m2m_prefcam_deallocs.ch2_miss_inval uncore interconnect Prefetch CAM Deallocs event=0x6e  01     unc_m2m_prefcam_deallocs.ch2_rsp_pdreset uncore interconnect Prefetch CAM Deallocs event=0x6e  01     unc_m2m_prefcam_demand_drops.ch0_upi uncore interconnect Data Prefetches Dropped : UPI - Ch 0 event=0x6f,umask=2  01     unc_m2m_prefcam_demand_drops.ch0_xpt uncore interconnect Data Prefetches Dropped : XPT - Ch 0 event=0x6f,umask=1  01     unc_m2m_prefcam_demand_drops.ch1_upi uncore interconnect Data Prefetches Dropped : UPI - Ch 1 event=0x6f,umask=8  01     unc_m2m_prefcam_demand_drops.ch1_xpt uncore interconnect Data Prefetches Dropped : XPT - Ch 1 event=0x6f,umask=4  01     unc_m2m_prefcam_demand_drops.ch2_upi uncore interconnect Data Prefetches Dropped : UPI - Ch 2 event=0x6f,umask=0x20  01     unc_m2m_prefcam_demand_drops.ch2_xpt uncore interconnect Data Prefetches Dropped : XPT - Ch 2 event=0x6f,umask=0x10  01     unc_m2m_prefcam_demand_drops.upi_allch uncore interconnect Data Prefetches Dropped : UPI - All Channels event=0x6f,umask=0x2a  01     unc_m2m_prefcam_demand_drops.xpt_allch uncore interconnect Data Prefetches Dropped : XPT - All Channels event=0x6f,umask=0x15  01     unc_m2m_prefcam_demand_merge.ch0_xptupi uncore interconnect Demands Merged with CAMed Prefetches : XPT & UPI- Ch 0 event=0x74,umask=1  01    Demands Merged with CAMed Prefetches : XPT & UPI - Ch 0 unc_m2m_prefcam_demand_merge.ch1_xptupi uncore interconnect Demands Merged with CAMed Prefetches : XPT & UPI - Ch 1 event=0x74,umask=4  01    Demands Merged with CAMed Prefetches : XPT & UPI- Ch 1 unc_m2m_prefcam_demand_merge.ch2_xptupi uncore interconnect Demands Merged with CAMed Prefetches : XPT & UPI- Ch 2 event=0x74,umask=0x10  01    Demands Merged with CAMed Prefetches : XPT & UPI - Ch 2 unc_m2m_prefcam_demand_merge.xptupi_allch uncore interconnect Demands Merged with CAMed Prefetches : XPT & UPI- All Channels event=0x74,umask=0x15  01    Demands Merged with CAMed Prefetches : XPT & UPI - All Channels unc_m2m_prefcam_demand_no_merge.ch0_xptupi uncore interconnect Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 0 event=0x75,umask=1  01    Demands Not Merged with CAMed Prefetches : XPT & UPI- Ch 0 unc_m2m_prefcam_demand_no_merge.ch1_xptupi uncore interconnect Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 1 event=0x75,umask=4  01    Demands Not Merged with CAMed Prefetches : XPT & UPI- Ch 1 unc_m2m_prefcam_demand_no_merge.ch2_xptupi uncore interconnect Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 2 event=0x75,umask=0x10  01     unc_m2m_prefcam_demand_no_merge.xptupi_allch uncore interconnect Demands Not Merged with CAMed Prefetches : XPT & UPI - All Channels event=0x75,umask=0x15  01     unc_m2m_prefcam_drop_reasons_ch0.errorblk_rxc uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70,umask=0x10  01     unc_m2m_prefcam_drop_reasons_ch0.not_pf_sad_region uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70,umask=2  01     unc_m2m_prefcam_drop_reasons_ch0.pf_ad_crd uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70,umask=0x20  01     unc_m2m_prefcam_drop_reasons_ch0.pf_cam_full uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70,umask=0x40  01     unc_m2m_prefcam_drop_reasons_ch0.pf_cam_hit uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70,umask=4  01     unc_m2m_prefcam_drop_reasons_ch0.pf_secure_drop uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70,umask=1  01     unc_m2m_prefcam_drop_reasons_ch0.rpq_proxy uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70  01     unc_m2m_prefcam_drop_reasons_ch0.stop_b2b uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70,umask=8  01     unc_m2m_prefcam_drop_reasons_ch0.upi_thresh uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70  01     unc_m2m_prefcam_drop_reasons_ch0.wpq_proxy uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70,umask=0x80  01     unc_m2m_prefcam_drop_reasons_ch0.xpt_thresh uncore interconnect Data Prefetches Dropped Ch0 - Reasons event=0x70  01     unc_m2m_prefcam_drop_reasons_ch1.errorblk_rxc uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71,umask=0x10  01     unc_m2m_prefcam_drop_reasons_ch1.not_pf_sad_region uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71,umask=2  01     unc_m2m_prefcam_drop_reasons_ch1.pf_ad_crd uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71,umask=0x20  01     unc_m2m_prefcam_drop_reasons_ch1.pf_cam_full uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71,umask=0x40  01     unc_m2m_prefcam_drop_reasons_ch1.pf_cam_hit uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71,umask=4  01     unc_m2m_prefcam_drop_reasons_ch1.pf_secure_drop uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71,umask=1  01     unc_m2m_prefcam_drop_reasons_ch1.rpq_proxy uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71  01     unc_m2m_prefcam_drop_reasons_ch1.stop_b2b uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71,umask=8  01     unc_m2m_prefcam_drop_reasons_ch1.upi_thresh uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71  01     unc_m2m_prefcam_drop_reasons_ch1.wpq_proxy uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71,umask=0x80  01     unc_m2m_prefcam_drop_reasons_ch1.xpt_thresh uncore interconnect Data Prefetches Dropped Ch1 - Reasons event=0x71  01     unc_m2m_prefcam_drop_reasons_ch2.errorblk_rxc uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72,umask=0x10  01     unc_m2m_prefcam_drop_reasons_ch2.not_pf_sad_region uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72,umask=2  01     unc_m2m_prefcam_drop_reasons_ch2.pf_ad_crd uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72,umask=0x20  01     unc_m2m_prefcam_drop_reasons_ch2.pf_cam_full uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72,umask=0x40  01     unc_m2m_prefcam_drop_reasons_ch2.pf_cam_hit uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72,umask=4  01     unc_m2m_prefcam_drop_reasons_ch2.pf_secure_drop uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72,umask=1  01     unc_m2m_prefcam_drop_reasons_ch2.rpq_proxy uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72  01     unc_m2m_prefcam_drop_reasons_ch2.stop_b2b uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72,umask=8  01     unc_m2m_prefcam_drop_reasons_ch2.upi_thresh uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72  01     unc_m2m_prefcam_drop_reasons_ch2.wpq_proxy uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72,umask=0x80  01     unc_m2m_prefcam_drop_reasons_ch2.xpt_thresh uncore interconnect Data Prefetches Dropped Ch2 - Reasons event=0x72  01     unc_m2m_prefcam_inserts.ch0_upi uncore interconnect Prefetch CAM Inserts : UPI - Ch 0 event=0x6d,umask=2  01     unc_m2m_prefcam_inserts.ch0_xpt uncore interconnect Prefetch CAM Inserts : XPT - Ch 0 event=0x6d,umask=1  01     unc_m2m_prefcam_inserts.ch1_upi uncore interconnect Prefetch CAM Inserts : UPI - Ch 1 event=0x6d,umask=8  01     unc_m2m_prefcam_inserts.ch1_xpt uncore interconnect Prefetch CAM Inserts : XPT - Ch 1 event=0x6d,umask=4  01     unc_m2m_prefcam_inserts.ch2_upi uncore interconnect Prefetch CAM Inserts : UPI - Ch 2 event=0x6d,umask=0x20  01     unc_m2m_prefcam_inserts.ch2_xpt uncore interconnect Prefetch CAM Inserts : XPT - Ch 2 event=0x6d,umask=0x10  01     unc_m2m_prefcam_inserts.upi_allch uncore interconnect Prefetch CAM Inserts : UPI - All Channels event=0x6d,umask=0x2a  01     unc_m2m_prefcam_inserts.xpt_allch uncore interconnect Prefetch CAM Inserts : XPT - All Channels event=0x6d,umask=0x15  01     unc_m2m_prefcam_occupancy.allch uncore interconnect Prefetch CAM Occupancy : All Channels event=0x6a,umask=7  01     unc_m2m_prefcam_occupancy.ch0 uncore interconnect Prefetch CAM Occupancy : Channel 0 event=0x6a,umask=1  01     unc_m2m_prefcam_occupancy.ch1 uncore interconnect Prefetch CAM Occupancy : Channel 1 event=0x6a,umask=2  01     unc_m2m_prefcam_occupancy.ch2 uncore interconnect Prefetch CAM Occupancy : Channel 2 event=0x6a,umask=4  01     unc_m2m_prefcam_resp_miss.allch uncore interconnect : All Channels event=0x76,umask=7  01     unc_m2m_prefcam_resp_miss.ch0 uncore interconnect : Channel 0 event=0x76,umask=1  01     unc_m2m_prefcam_resp_miss.ch1 uncore interconnect : Channel 1 event=0x76,umask=2  01     unc_m2m_prefcam_resp_miss.ch2 uncore interconnect : Channel 2 event=0x76,umask=4  01     unc_m2m_prefcam_rxc_cycles_ne uncore interconnect UNC_M2M_PREFCAM_RxC_CYCLES_NE event=0x79  01     unc_m2m_prefcam_rxc_deallocs.1lm_posted uncore interconnect UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED event=0x7a,umask=2  01     unc_m2m_prefcam_rxc_deallocs.cis uncore interconnect UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS event=0x7a,umask=8  01     unc_m2m_prefcam_rxc_deallocs.pmm_memmode_accept uncore interconnect UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT event=0x7a,umask=4  01     unc_m2m_prefcam_rxc_deallocs.squashed uncore interconnect UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED event=0x7a,umask=1  01     unc_m2m_prefcam_rxc_inserts uncore interconnect UNC_M2M_PREFCAM_RxC_INSERTS event=0x78  01     unc_m2m_prefcam_rxc_occupancy uncore interconnect UNC_M2M_PREFCAM_RxC_OCCUPANCY event=0x77  01     unc_m2m_ring_bounces_horz.ad uncore interconnect Messages that bounced on the Horizontal Ring. : AD event=0xac,umask=1  01    Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2m_ring_bounces_horz.ak uncore interconnect Messages that bounced on the Horizontal Ring. : AK event=0xac,umask=2  01    Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2m_ring_bounces_horz.bl uncore interconnect Messages that bounced on the Horizontal Ring. : BL event=0xac,umask=4  01    Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2m_ring_bounces_horz.iv uncore interconnect Messages that bounced on the Horizontal Ring. : IV event=0xac,umask=8  01    Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2m_ring_bounces_vert.ad uncore interconnect Messages that bounced on the Vertical Ring. : AD event=0xaa,umask=1  01    Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2m_ring_bounces_vert.ak uncore interconnect Messages that bounced on the Vertical Ring. : Acknowledgements to core event=0xaa,umask=2  01    Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2m_ring_bounces_vert.akc uncore interconnect Messages that bounced on the Vertical Ring event=0xaa,umask=0x10  01    Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2m_ring_bounces_vert.bl uncore interconnect Messages that bounced on the Vertical Ring. : Data Responses to core event=0xaa,umask=4  01    Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2m_ring_bounces_vert.iv uncore interconnect Messages that bounced on the Vertical Ring. : Snoops of processor's cache event=0xaa,umask=8  01    Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2m_ring_sink_starved_horz.ad uncore interconnect Sink Starvation on Horizontal Ring : AD event=0xad,umask=1  01     unc_m2m_ring_sink_starved_horz.ak uncore interconnect Sink Starvation on Horizontal Ring : AK event=0xad,umask=2  01     unc_m2m_ring_sink_starved_horz.ak_ag1 uncore interconnect Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1 event=0xad,umask=0x20  01     unc_m2m_ring_sink_starved_horz.bl uncore interconnect Sink Starvation on Horizontal Ring : BL event=0xad,umask=4  01     unc_m2m_ring_sink_starved_horz.iv uncore interconnect Sink Starvation on Horizontal Ring : IV event=0xad,umask=8  01     unc_m2m_ring_sink_starved_vert.ad uncore interconnect Sink Starvation on Vertical Ring : AD event=0xab,umask=1  01     unc_m2m_ring_sink_starved_vert.ak uncore interconnect Sink Starvation on Vertical Ring : Acknowledgements to core event=0xab,umask=2  01     unc_m2m_ring_sink_starved_vert.akc uncore interconnect Sink Starvation on Vertical Ring event=0xab,umask=0x10  01     unc_m2m_ring_sink_starved_vert.bl uncore interconnect Sink Starvation on Vertical Ring : Data Responses to core event=0xab,umask=4  01     unc_m2m_ring_sink_starved_vert.iv uncore interconnect Sink Starvation on Vertical Ring : Snoops of processor's cache event=0xab,umask=8  01     unc_m2m_ring_src_thrtl uncore interconnect Source Throttle event=0xae  01     unc_m2m_rpq_no_reg_crd.ch0 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Regular : Channel 0 event=0x43,umask=1  01     unc_m2m_rpq_no_reg_crd.ch1 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Regular : Channel 1 event=0x43,umask=2  01     unc_m2m_rpq_no_reg_crd.ch2 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Regular : Channel 2 event=0x43,umask=4  01     unc_m2m_rpq_no_reg_crd_pmm.chn0 uncore interconnect M2M->iMC RPQ Cycles w/Credits - PMM : Channel 0 event=0x4f,umask=1  01     unc_m2m_rpq_no_reg_crd_pmm.chn1 uncore interconnect M2M->iMC RPQ Cycles w/Credits - PMM : Channel 1 event=0x4f,umask=2  01     unc_m2m_rpq_no_reg_crd_pmm.chn2 uncore interconnect M2M->iMC RPQ Cycles w/Credits - PMM : Channel 2 event=0x4f,umask=4  01     unc_m2m_rpq_no_spec_crd.ch0 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Special : Channel 0 event=0x44,umask=1  01     unc_m2m_rpq_no_spec_crd.ch1 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Special : Channel 1 event=0x44,umask=2  01     unc_m2m_rpq_no_spec_crd.ch2 uncore interconnect M2M to iMC RPQ Cycles w/Credits - Special : Channel 2 event=0x44,umask=4  01     unc_m2m_rxc_ad_inserts uncore interconnect AD Ingress (from CMS) Allocations event=1  01     unc_m2m_rxc_ad_pref_occupancy uncore interconnect AD Ingress (from CMS) Occupancy - Prefetches event=0x77  01     unc_m2m_rxc_ak_wr_cmp uncore interconnect AK Egress (to CMS) Allocations event=0x5c  01     unc_m2m_rxr_busy_starved.ad_all uncore interconnect Transgress Injection Starvation : AD - All event=0xe5,umask=0x11  01    Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority : All == Credited + Uncredited unc_m2m_rxr_busy_starved.ad_crd uncore interconnect Transgress Injection Starvation : AD - Credited event=0xe5,umask=0x10  01    Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority unc_m2m_rxr_busy_starved.ad_uncrd uncore interconnect Transgress Injection Starvation : AD - Uncredited event=0xe5,umask=1  01    Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority unc_m2m_rxr_busy_starved.bl_all uncore interconnect Transgress Injection Starvation : BL - All event=0xe5,umask=0x44  01    Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority : All == Credited + Uncredited unc_m2m_rxr_busy_starved.bl_crd uncore interconnect Transgress Injection Starvation : BL - Credited event=0xe5,umask=0x40  01    Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority unc_m2m_rxr_busy_starved.bl_uncrd uncore interconnect Transgress Injection Starvation : BL - Uncredited event=0xe5,umask=4  01    Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority unc_m2m_rxr_bypass.ad_all uncore interconnect Transgress Ingress Bypass : AD - All event=0xe2,umask=0x11  01    Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited unc_m2m_rxr_bypass.ad_crd uncore interconnect Transgress Ingress Bypass : AD - Credited event=0xe2,umask=0x10  01    Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.ad_uncrd uncore interconnect Transgress Ingress Bypass : AD - Uncredited event=0xe2,umask=1  01    Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.ak uncore interconnect Transgress Ingress Bypass : AK event=0xe2,umask=2  01    Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.akc_uncrd uncore interconnect Transgress Ingress Bypass : AKC - Uncredited event=0xe2,umask=0x80  01    Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.bl_all uncore interconnect Transgress Ingress Bypass : BL - All event=0xe2,umask=0x44  01    Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited unc_m2m_rxr_bypass.bl_crd uncore interconnect Transgress Ingress Bypass : BL - Credited event=0xe2,umask=0x40  01    Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.bl_uncrd uncore interconnect Transgress Ingress Bypass : BL - Uncredited event=0xe2,umask=4  01    Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress unc_m2m_rxr_bypass.iv uncore interconnect Transgress Ingress Bypass : IV event=0xe2,umask=8  01    Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress unc_m2m_rxr_crd_starved.ad_all uncore interconnect Transgress Injection Starvation : AD - All event=0xe3,umask=0x11  01    Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited unc_m2m_rxr_crd_starved.ad_crd uncore interconnect Transgress Injection Starvation : AD - Credited event=0xe3,umask=0x10  01    Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.ad_uncrd uncore interconnect Transgress Injection Starvation : AD - Uncredited event=0xe3,umask=1  01    Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.ak uncore interconnect Transgress Injection Starvation : AK event=0xe3,umask=2  01    Transgress Injection Starvation : AK : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.bl_all uncore interconnect Transgress Injection Starvation : BL - All event=0xe3,umask=0x44  01    Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited unc_m2m_rxr_crd_starved.bl_crd uncore interconnect Transgress Injection Starvation : BL - Credited event=0xe3,umask=0x40  01    Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.bl_uncrd uncore interconnect Transgress Injection Starvation : BL - Uncredited event=0xe3,umask=4  01    Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.ifv uncore interconnect Transgress Injection Starvation : IFV - Credited event=0xe3,umask=0x80  01    Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved.iv uncore interconnect Transgress Injection Starvation : IV event=0xe3,umask=8  01    Transgress Injection Starvation : IV : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_crd_starved_1 uncore interconnect Transgress Injection Starvation event=0xe4  01    Transgress Injection Starvation : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2m_rxr_inserts.ad_all uncore interconnect Transgress Ingress Allocations : AD - All event=0xe1,umask=0x11  01    Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m2m_rxr_inserts.ad_crd uncore interconnect Transgress Ingress Allocations : AD - Credited event=0xe1,umask=0x10  01    Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.ad_uncrd uncore interconnect Transgress Ingress Allocations : AD - Uncredited event=0xe1,umask=1  01    Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.ak uncore interconnect Transgress Ingress Allocations : AK event=0xe1,umask=2  01    Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.akc_uncrd uncore interconnect Transgress Ingress Allocations : AKC - Uncredited event=0xe1,umask=0x80  01    Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.bl_all uncore interconnect Transgress Ingress Allocations : BL - All event=0xe1,umask=0x44  01    Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m2m_rxr_inserts.bl_crd uncore interconnect Transgress Ingress Allocations : BL - Credited event=0xe1,umask=0x40  01    Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.bl_uncrd uncore interconnect Transgress Ingress Allocations : BL - Uncredited event=0xe1,umask=4  01    Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_inserts.iv uncore interconnect Transgress Ingress Allocations : IV event=0xe1,umask=8  01    Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.ad_all uncore interconnect Transgress Ingress Occupancy : AD - All event=0xe0,umask=0x11  01    Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m2m_rxr_occupancy.ad_crd uncore interconnect Transgress Ingress Occupancy : AD - Credited event=0xe0,umask=0x10  01    Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.ad_uncrd uncore interconnect Transgress Ingress Occupancy : AD - Uncredited event=0xe0,umask=1  01    Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.ak uncore interconnect Transgress Ingress Occupancy : AK event=0xe0,umask=2  01    Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.akc_uncrd uncore interconnect Transgress Ingress Occupancy : AKC - Uncredited event=0xe0,umask=0x80  01    Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.bl_all uncore interconnect Transgress Ingress Occupancy : BL - All event=0xe0,umask=0x44  01    Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m2m_rxr_occupancy.bl_crd uncore interconnect Transgress Ingress Occupancy : BL - Credited event=0xe0,umask=0x20  01    Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.bl_uncrd uncore interconnect Transgress Ingress Occupancy : BL - Uncredited event=0xe0,umask=4  01    Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m2m_rxr_occupancy.iv uncore interconnect Transgress Ingress Occupancy : IV event=0xe0,umask=8  01    Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m2m_scoreboard_ad_retry_accepts uncore interconnect UNC_M2M_SCOREBOARD_AD_RETRY_ACCEPTS event=0x33  01     unc_m2m_scoreboard_ad_retry_rejects uncore interconnect UNC_M2M_SCOREBOARD_AD_RETRY_REJECTS event=0x34  01     unc_m2m_scoreboard_bl_retry_accepts uncore interconnect Retry - Mem Mirroring Mode event=0x35  01     unc_m2m_scoreboard_bl_retry_rejects uncore interconnect Retry - Mem Mirroring Mode event=0x36  01     unc_m2m_scoreboard_rd_accepts uncore interconnect Scoreboard Accepts event=0x2f  01     unc_m2m_scoreboard_rd_rejects uncore interconnect Scoreboard Rejects event=0x30  01     unc_m2m_scoreboard_wr_accepts uncore interconnect Scoreboard Accepts event=0x31  01     unc_m2m_scoreboard_wr_rejects uncore interconnect Scoreboard Rejects event=0x32  01     unc_m2m_stall0_no_txr_horz_crd_ad_ag0.tgr0 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 0 event=0xd0,umask=1  01    Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag0.tgr1 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 1 event=0xd0,umask=2  01    Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag0.tgr2 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 2 event=0xd0,umask=4  01    Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag0.tgr3 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 3 event=0xd0,umask=8  01    Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag0.tgr4 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 4 event=0xd0,umask=0x10  01    Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag0.tgr5 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 5 event=0xd0,umask=0x20  01    Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag0.tgr6 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 6 event=0xd0,umask=0x40  01    Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag0.tgr7 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 7 event=0xd0,umask=0x80  01    Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag1.tgr0 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 0 event=0xd2,umask=1  01    Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag1.tgr1 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 1 event=0xd2,umask=2  01    Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag1.tgr2 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 2 event=0xd2,umask=4  01    Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag1.tgr3 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 3 event=0xd2,umask=8  01    Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag1.tgr4 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 4 event=0xd2,umask=0x10  01    Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag1.tgr5 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 5 event=0xd2,umask=0x20  01    Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag1.tgr6 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 6 event=0xd2,umask=0x40  01    Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_ad_ag1.tgr7 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 7 event=0xd2,umask=0x80  01    Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag0.tgr0 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 0 event=0xd4,umask=1  01    Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag0.tgr1 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 1 event=0xd4,umask=2  01    Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag0.tgr2 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 2 event=0xd4,umask=4  01    Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag0.tgr3 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 3 event=0xd4,umask=8  01    Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag0.tgr4 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 4 event=0xd4,umask=0x10  01    Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag0.tgr5 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 5 event=0xd4,umask=0x20  01    Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag0.tgr6 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 6 event=0xd4,umask=0x40  01    Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag0.tgr7 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 7 event=0xd4,umask=0x80  01    Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag1.tgr0 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 0 event=0xd6,umask=1  01    Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag1.tgr1 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 1 event=0xd6,umask=2  01    Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag1.tgr2 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 2 event=0xd6,umask=4  01    Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag1.tgr3 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 3 event=0xd6,umask=8  01    Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag1.tgr4 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 4 event=0xd6,umask=0x10  01    Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag1.tgr5 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 5 event=0xd6,umask=0x20  01    Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag1.tgr6 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 6 event=0xd6,umask=0x40  01    Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall0_no_txr_horz_crd_bl_ag1.tgr7 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 7 event=0xd6,umask=0x80  01    Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_ad_ag0.tgr10 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 10 event=0xd1,umask=4  01    Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_ad_ag0.tgr8 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 8 event=0xd1,umask=1  01    Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_ad_ag0.tgr9 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 9 event=0xd1,umask=2  01    Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_ad_ag1_1.tgr10 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 10 event=0xd3,umask=4  01    Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_ad_ag1_1.tgr8 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 8 event=0xd3,umask=1  01    Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_ad_ag1_1.tgr9 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 9 event=0xd3,umask=2  01    Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_bl_ag0_1.tgr10 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 10 event=0xd5,umask=4  01    Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_bl_ag0_1.tgr8 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 8 event=0xd5,umask=1  01    Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_bl_ag0_1.tgr9 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 9 event=0xd5,umask=2  01    Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_bl_ag1_1.tgr10 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 10 event=0xd7,umask=4  01    Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_bl_ag1_1.tgr8 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 8 event=0xd7,umask=1  01    Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_stall1_no_txr_horz_crd_bl_ag1_1.tgr9 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 9 event=0xd7,umask=2  01    Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2m_tag_hit.nm_rd_hit_clean uncore interconnect Tag Hit : Clean NearMem Read Hit event=0x2c,umask=1  01    Tag Hit : Clean NearMem Read Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts clean full line read hits (reads and RFOs) unc_m2m_tag_hit.nm_rd_hit_dirty uncore interconnect Tag Hit : Dirty NearMem Read Hit event=0x2c,umask=2  01    Tag Hit : Dirty NearMem Read Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts dirty full line read hits (reads and RFOs) unc_m2m_tag_hit.nm_ufill_hit_clean uncore interconnect Tag Hit : Clean NearMem Underfill Hit event=0x2c,umask=4  01    Tag Hit : Clean NearMem Underfill Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts clean underfill hits due to a partial write unc_m2m_tag_hit.nm_ufill_hit_dirty uncore interconnect Tag Hit : Dirty NearMem Underfill Hit event=0x2c,umask=8  01    Tag Hit : Dirty NearMem Underfill Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts dirty underfill read hits due to a partial write unc_m2m_tag_miss uncore interconnect Tag Miss event=0x61  01     unc_m2m_tracker_full.ch0 uncore interconnect Tracker Cycles Full : Channel 0 event=0x45,umask=1  01     unc_m2m_tracker_full.ch1 uncore interconnect Tracker Cycles Full : Channel 1 event=0x45,umask=2  01     unc_m2m_tracker_full.ch2 uncore interconnect Tracker Cycles Full : Channel 2 event=0x45,umask=4  01     unc_m2m_tracker_inserts.ch0 uncore interconnect Tracker Inserts : Channel 0 event=0x49,umask=1  01     unc_m2m_tracker_inserts.ch1 uncore interconnect Tracker Inserts : Channel 1 event=0x49,umask=2  01     unc_m2m_tracker_inserts.ch2 uncore interconnect Tracker Inserts : Channel 2 event=0x49,umask=4  01     unc_m2m_tracker_ne.ch0 uncore interconnect Tracker Cycles Not Empty : Channel 0 event=0x46,umask=1  01     unc_m2m_tracker_ne.ch1 uncore interconnect Tracker Cycles Not Empty : Channel 1 event=0x46,umask=2  01     unc_m2m_tracker_ne.ch2 uncore interconnect Tracker Cycles Not Empty : Channel 2 event=0x46,umask=4  01     unc_m2m_tracker_occupancy.ch0 uncore interconnect Tracker Occupancy : Channel 0 event=0x47,umask=1  01     unc_m2m_tracker_occupancy.ch1 uncore interconnect Tracker Occupancy : Channel 1 event=0x47,umask=2  01     unc_m2m_tracker_occupancy.ch2 uncore interconnect Tracker Occupancy : Channel 2 event=0x47,umask=4  01     unc_m2m_txc_ak.crd_cbo uncore interconnect Outbound Ring Transactions on AK : CRD Transactions to Cbo event=0x39,umask=2  01     unc_m2m_txc_ak.ndr uncore interconnect Outbound Ring Transactions on AK : NDR Transactions event=0x39,umask=1  01     unc_m2m_txc_akc_credits uncore interconnect AKC Credits event=0x5f  01     unc_m2m_txc_ak_credits_acquired.cms0 uncore interconnect AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side event=0x1d,umask=1  01     unc_m2m_txc_ak_credits_acquired.cms1 uncore interconnect AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side event=0x1d,umask=2  01     unc_m2m_txc_ak_cycles_full.all uncore interconnect AK Egress (to CMS) Full : All event=0x14,umask=3  01     unc_m2m_txc_ak_cycles_full.cms0 uncore interconnect AK Egress (to CMS) Full : Common Mesh Stop - Near Side event=0x14,umask=1  01     unc_m2m_txc_ak_cycles_full.cms1 uncore interconnect AK Egress (to CMS) Full : Common Mesh Stop - Far Side event=0x14,umask=2  01     unc_m2m_txc_ak_cycles_full.rdcrd0 uncore interconnect AK Egress (to CMS) Full event=0x14,umask=8  01     unc_m2m_txc_ak_cycles_full.rdcrd1 uncore interconnect AK Egress (to CMS) Full event=0x14,umask=0x88  01     unc_m2m_txc_ak_cycles_full.wrcmp0 uncore interconnect AK Egress (to CMS) Full event=0x14,umask=0x20  01     unc_m2m_txc_ak_cycles_full.wrcmp1 uncore interconnect AK Egress (to CMS) Full event=0x14,umask=0xa0  01     unc_m2m_txc_ak_cycles_full.wrcrd0 uncore interconnect AK Egress (to CMS) Full event=0x14,umask=0x10  01     unc_m2m_txc_ak_cycles_full.wrcrd1 uncore interconnect AK Egress (to CMS) Full event=0x14,umask=0x90  01     unc_m2m_txc_ak_cycles_ne.all uncore interconnect AK Egress (to CMS) Not Empty : All event=0x13,umask=3  01     unc_m2m_txc_ak_cycles_ne.cms0 uncore interconnect AK Egress (to CMS) Not Empty : Common Mesh Stop - Near Side event=0x13,umask=1  01     unc_m2m_txc_ak_cycles_ne.cms1 uncore interconnect AK Egress (to CMS) Not Empty : Common Mesh Stop - Far Side event=0x13,umask=2  01     unc_m2m_txc_ak_cycles_ne.rdcrd uncore interconnect AK Egress (to CMS) Not Empty event=0x13,umask=8  01     unc_m2m_txc_ak_cycles_ne.wrcmp uncore interconnect AK Egress (to CMS) Not Empty event=0x13,umask=0x20  01     unc_m2m_txc_ak_cycles_ne.wrcrd uncore interconnect AK Egress (to CMS) Not Empty event=0x13,umask=0x10  01     unc_m2m_txc_ak_inserts.all uncore interconnect AK Egress (to CMS) Allocations : All event=0x11,umask=3  01     unc_m2m_txc_ak_inserts.cms0 uncore interconnect AK Egress (to CMS) Allocations : Common Mesh Stop - Near Side event=0x11,umask=1  01     unc_m2m_txc_ak_inserts.cms1 uncore interconnect AK Egress (to CMS) Allocations : Common Mesh Stop - Far Side event=0x11,umask=2  01     unc_m2m_txc_ak_inserts.pref_rd_cam_hit uncore interconnect AK Egress (to CMS) Allocations event=0x11,umask=0x40  01     unc_m2m_txc_ak_inserts.rdcrd uncore interconnect AK Egress (to CMS) Allocations event=0x11,umask=8  01     unc_m2m_txc_ak_inserts.wrcmp uncore interconnect AK Egress (to CMS) Allocations event=0x11,umask=0x20  01     unc_m2m_txc_ak_inserts.wrcrd uncore interconnect AK Egress (to CMS) Allocations event=0x11,umask=0x10  01     unc_m2m_txc_ak_no_credit_cycles.cms0 uncore interconnect Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side event=0x1f,umask=1  01     unc_m2m_txc_ak_no_credit_cycles.cms1 uncore interconnect Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side event=0x1f,umask=2  01     unc_m2m_txc_ak_no_credit_stalled.cms0 uncore interconnect Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side event=0x20,umask=1  01     unc_m2m_txc_ak_no_credit_stalled.cms1 uncore interconnect Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side event=0x20,umask=2  01     unc_m2m_txc_ak_occupancy.all uncore interconnect AK Egress (to CMS) Occupancy : All event=0x12,umask=3  01     unc_m2m_txc_ak_occupancy.cms0 uncore interconnect AK Egress (to CMS) Occupancy : Common Mesh Stop - Near Side event=0x12,umask=1  01     unc_m2m_txc_ak_occupancy.cms1 uncore interconnect AK Egress (to CMS) Occupancy : Common Mesh Stop - Far Side event=0x12,umask=2  01     unc_m2m_txc_ak_occupancy.rdcrd uncore interconnect AK Egress (to CMS) Occupancy event=0x12,umask=8  01     unc_m2m_txc_ak_occupancy.wrcmp uncore interconnect AK Egress (to CMS) Occupancy event=0x12,umask=0x20  01     unc_m2m_txc_ak_occupancy.wrcrd uncore interconnect AK Egress (to CMS) Occupancy event=0x12,umask=0x10  01     unc_m2m_txc_bl.drs_cache uncore interconnect Outbound DRS Ring Transactions to Cache : Data to Cache event=0x40,umask=1  01     unc_m2m_txc_bl.drs_core uncore interconnect Outbound DRS Ring Transactions to Cache : Data to Core event=0x40,umask=2  01     unc_m2m_txc_bl.drs_upi uncore interconnect Outbound DRS Ring Transactions to Cache : Data to QPI event=0x40,umask=4  01     unc_m2m_txc_bl_credits_acquired.cms0 uncore interconnect BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side event=0x19,umask=1  01     unc_m2m_txc_bl_credits_acquired.cms1 uncore interconnect BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side event=0x19,umask=2  01     unc_m2m_txc_bl_cycles_full.all uncore interconnect BL Egress (to CMS) Full : All event=0x18,umask=3  01     unc_m2m_txc_bl_cycles_full.cms0 uncore interconnect BL Egress (to CMS) Full : Common Mesh Stop - Near Side event=0x18,umask=1  01     unc_m2m_txc_bl_cycles_full.cms1 uncore interconnect BL Egress (to CMS) Full : Common Mesh Stop - Far Side event=0x18,umask=2  01     unc_m2m_txc_bl_cycles_ne.all uncore interconnect BL Egress (to CMS) Not Empty : All event=0x17,umask=3  01     unc_m2m_txc_bl_cycles_ne.cms0 uncore interconnect BL Egress (to CMS) Not Empty : Common Mesh Stop - Near Side event=0x17,umask=1  01     unc_m2m_txc_bl_cycles_ne.cms1 uncore interconnect BL Egress (to CMS) Not Empty : Common Mesh Stop - Far Side event=0x17,umask=2  01     unc_m2m_txc_bl_inserts.all uncore interconnect BL Egress (to CMS) Allocations : All event=0x15,umask=3  01     unc_m2m_txc_bl_inserts.cms0 uncore interconnect BL Egress (to CMS) Allocations : Common Mesh Stop - Near Side event=0x15,umask=1  01     unc_m2m_txc_bl_inserts.cms1 uncore interconnect BL Egress (to CMS) Allocations : Common Mesh Stop - Far Side event=0x15,umask=2  01     unc_m2m_txc_bl_no_credit_cycles.cms0 uncore interconnect Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side event=0x1b,umask=1  01     unc_m2m_txc_bl_no_credit_cycles.cms1 uncore interconnect Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side event=0x1b,umask=2  01     unc_m2m_txc_bl_no_credit_stalled.cms0 uncore interconnect Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side event=0x1c,umask=1  01     unc_m2m_txc_bl_no_credit_stalled.cms1 uncore interconnect Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side event=0x1c,umask=2  01     unc_m2m_txr_horz_ads_used.ad_all uncore interconnect CMS Horizontal ADS Used : AD - All event=0xa6,umask=0x11  01    CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m2m_txr_horz_ads_used.ad_crd uncore interconnect CMS Horizontal ADS Used : AD - Credited event=0xa6,umask=0x10  01    CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_horz_ads_used.ad_uncrd uncore interconnect CMS Horizontal ADS Used : AD - Uncredited event=0xa6,umask=1  01    CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_horz_ads_used.bl_all uncore interconnect CMS Horizontal ADS Used : BL - All event=0xa6,umask=0x44  01    CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m2m_txr_horz_ads_used.bl_crd uncore interconnect CMS Horizontal ADS Used : BL - Credited event=0xa6,umask=0x40  01    CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_horz_ads_used.bl_uncrd uncore interconnect CMS Horizontal ADS Used : BL - Uncredited event=0xa6,umask=4  01    CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.ad_all uncore interconnect CMS Horizontal Bypass Used : AD - All event=0xa7,umask=0x11  01    CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m2m_txr_horz_bypass.ad_crd uncore interconnect CMS Horizontal Bypass Used : AD - Credited event=0xa7,umask=0x10  01    CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.ad_uncrd uncore interconnect CMS Horizontal Bypass Used : AD - Uncredited event=0xa7,umask=1  01    CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.ak uncore interconnect CMS Horizontal Bypass Used : AK event=0xa7,umask=2  01    CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.akc_uncrd uncore interconnect CMS Horizontal Bypass Used : AKC - Uncredited event=0xa7,umask=0x80  01    CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.bl_all uncore interconnect CMS Horizontal Bypass Used : BL - All event=0xa7,umask=0x44  01    CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m2m_txr_horz_bypass.bl_crd uncore interconnect CMS Horizontal Bypass Used : BL - Credited event=0xa7,umask=0x40  01    CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.bl_uncrd uncore interconnect CMS Horizontal Bypass Used : BL - Uncredited event=0xa7,umask=4  01    CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_bypass.iv uncore interconnect CMS Horizontal Bypass Used : IV event=0xa7,umask=8  01    CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2m_txr_horz_cycles_full.ad_all uncore interconnect Cycles CMS Horizontal Egress Queue is Full : AD - All event=0xa2,umask=0x11  01    Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2m_txr_horz_cycles_full.ad_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Full : AD - Credited event=0xa2,umask=0x10  01    Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.ad_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited event=0xa2,umask=1  01    Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.ak uncore interconnect Cycles CMS Horizontal Egress Queue is Full : AK event=0xa2,umask=2  01    Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.akc_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited event=0xa2,umask=0x80  01    Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.bl_all uncore interconnect Cycles CMS Horizontal Egress Queue is Full : BL - All event=0xa2,umask=0x44  01    Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2m_txr_horz_cycles_full.bl_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Full : BL - Credited event=0xa2,umask=0x40  01    Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.bl_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited event=0xa2,umask=4  01    Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_full.iv uncore interconnect Cycles CMS Horizontal Egress Queue is Full : IV event=0xa2,umask=8  01    Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.ad_all uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : AD - All event=0xa3,umask=0x11  01    Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2m_txr_horz_cycles_ne.ad_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited event=0xa3,umask=0x10  01    Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.ad_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited event=0xa3,umask=1  01    Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.ak uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : AK event=0xa3,umask=2  01    Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.akc_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited event=0xa3,umask=0x80  01    Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.bl_all uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : BL - All event=0xa3,umask=0x44  01    Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2m_txr_horz_cycles_ne.bl_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited event=0xa3,umask=0x40  01    Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.bl_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited event=0xa3,umask=4  01    Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_cycles_ne.iv uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : IV event=0xa3,umask=8  01    Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.ad_all uncore interconnect CMS Horizontal Egress Inserts : AD - All event=0xa1,umask=0x11  01    CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2m_txr_horz_inserts.ad_crd uncore interconnect CMS Horizontal Egress Inserts : AD - Credited event=0xa1,umask=0x10  01    CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.ad_uncrd uncore interconnect CMS Horizontal Egress Inserts : AD - Uncredited event=0xa1,umask=1  01    CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.ak uncore interconnect CMS Horizontal Egress Inserts : AK event=0xa1,umask=2  01    CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.akc_uncrd uncore interconnect CMS Horizontal Egress Inserts : AKC - Uncredited event=0xa1,umask=0x80  01    CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.bl_all uncore interconnect CMS Horizontal Egress Inserts : BL - All event=0xa1,umask=0x44  01    CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2m_txr_horz_inserts.bl_crd uncore interconnect CMS Horizontal Egress Inserts : BL - Credited event=0xa1,umask=0x40  01    CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.bl_uncrd uncore interconnect CMS Horizontal Egress Inserts : BL - Uncredited event=0xa1,umask=4  01    CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_inserts.iv uncore interconnect CMS Horizontal Egress Inserts : IV event=0xa1,umask=8  01    CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_nack.ad_all uncore interconnect CMS Horizontal Egress NACKs : AD - All event=0xa4,umask=0x11  01    CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited unc_m2m_txr_horz_nack.ad_crd uncore interconnect CMS Horizontal Egress NACKs : AD - Credited event=0xa4,umask=0x10  01    CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.ad_uncrd uncore interconnect CMS Horizontal Egress NACKs : AD - Uncredited event=0xa4,umask=1  01    CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.ak uncore interconnect CMS Horizontal Egress NACKs : AK event=0xa4,umask=2  01    CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.akc_uncrd uncore interconnect CMS Horizontal Egress NACKs : AKC - Uncredited event=0xa4,umask=0x80  01    CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.bl_all uncore interconnect CMS Horizontal Egress NACKs : BL - All event=0xa4,umask=0x44  01    CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited unc_m2m_txr_horz_nack.bl_crd uncore interconnect CMS Horizontal Egress NACKs : BL - Credited event=0xa4,umask=0x40  01    CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.bl_uncrd uncore interconnect CMS Horizontal Egress NACKs : BL - Uncredited event=0xa4,umask=4  01    CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_nack.iv uncore interconnect CMS Horizontal Egress NACKs : IV event=0xa4,umask=8  01    CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2m_txr_horz_occupancy.ad_all uncore interconnect CMS Horizontal Egress Occupancy : AD - All event=0xa0,umask=0x11  01    CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2m_txr_horz_occupancy.ad_crd uncore interconnect CMS Horizontal Egress Occupancy : AD - Credited event=0xa0,umask=0x10  01    CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.ad_uncrd uncore interconnect CMS Horizontal Egress Occupancy : AD - Uncredited event=0xa0,umask=1  01    CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.ak uncore interconnect CMS Horizontal Egress Occupancy : AK event=0xa0,umask=2  01    CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.akc_uncrd uncore interconnect CMS Horizontal Egress Occupancy : AKC - Uncredited event=0xa0,umask=0x80  01    CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.bl_all uncore interconnect CMS Horizontal Egress Occupancy : BL - All event=0xa0,umask=0x44  01    CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2m_txr_horz_occupancy.bl_crd uncore interconnect CMS Horizontal Egress Occupancy : BL - Credited event=0xa0,umask=0x40  01    CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.bl_uncrd uncore interconnect CMS Horizontal Egress Occupancy : BL - Uncredited event=0xa0,umask=4  01    CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_occupancy.iv uncore interconnect CMS Horizontal Egress Occupancy : IV event=0xa0,umask=8  01    CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2m_txr_horz_starved.ad_all uncore interconnect CMS Horizontal Egress Injection Starvation : AD - All event=0xa5,umask=1  01    CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited unc_m2m_txr_horz_starved.ad_uncrd uncore interconnect CMS Horizontal Egress Injection Starvation : AD - Uncredited event=0xa5,umask=1  01    CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2m_txr_horz_starved.ak uncore interconnect CMS Horizontal Egress Injection Starvation : AK event=0xa5,umask=2  01    CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2m_txr_horz_starved.akc_uncrd uncore interconnect CMS Horizontal Egress Injection Starvation : AKC - Uncredited event=0xa5,umask=0x80  01    CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2m_txr_horz_starved.bl_all uncore interconnect CMS Horizontal Egress Injection Starvation : BL - All event=0xa5,umask=4  01    CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited unc_m2m_txr_horz_starved.bl_uncrd uncore interconnect CMS Horizontal Egress Injection Starvation : BL - Uncredited event=0xa5,umask=4  01    CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2m_txr_horz_starved.iv uncore interconnect CMS Horizontal Egress Injection Starvation : IV event=0xa5,umask=8  01    CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2m_txr_vert_ads_used.ad_ag0 uncore interconnect CMS Vertical ADS Used : AD - Agent 0 event=0x9c,umask=1  01    CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_vert_ads_used.ad_ag1 uncore interconnect CMS Vertical ADS Used : AD - Agent 1 event=0x9c,umask=0x10  01    CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_vert_ads_used.bl_ag0 uncore interconnect CMS Vertical ADS Used : BL - Agent 0 event=0x9c,umask=4  01    CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_vert_ads_used.bl_ag1 uncore interconnect CMS Vertical ADS Used : BL - Agent 1 event=0x9c,umask=0x40  01    CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.ad_ag0 uncore interconnect CMS Vertical ADS Used : AD - Agent 0 event=0x9d,umask=1  01    CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.ad_ag1 uncore interconnect CMS Vertical ADS Used : AD - Agent 1 event=0x9d,umask=0x10  01    CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.ak_ag0 uncore interconnect CMS Vertical ADS Used : AK - Agent 0 event=0x9d,umask=2  01    CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.ak_ag1 uncore interconnect CMS Vertical ADS Used : AK - Agent 1 event=0x9d,umask=0x20  01    CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.bl_ag0 uncore interconnect CMS Vertical ADS Used : BL - Agent 0 event=0x9d,umask=4  01    CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.bl_ag1 uncore interconnect CMS Vertical ADS Used : BL - Agent 1 event=0x9d,umask=0x40  01    CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass.iv_ag1 uncore interconnect CMS Vertical ADS Used : IV - Agent 1 event=0x9d,umask=8  01    CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass_1.akc_ag0 uncore interconnect CMS Vertical ADS Used : AKC - Agent 0 event=0x9e,umask=1  01    CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_bypass_1.akc_ag1 uncore interconnect CMS Vertical ADS Used : AKC - Agent 1 event=0x9e,umask=2  01    CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2m_txr_vert_cycles_full0.ad_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 event=0x94,umask=1  01    Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_cycles_full0.ad_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 event=0x94,umask=0x10  01    Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests unc_m2m_txr_vert_cycles_full0.ak_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 event=0x94,umask=2  01    Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_m2m_txr_vert_cycles_full0.ak_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 event=0x94,umask=0x20  01    Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m2m_txr_vert_cycles_full0.bl_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 event=0x94,umask=4  01    Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations unc_m2m_txr_vert_cycles_full0.bl_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 event=0x94,umask=0x40  01    Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache unc_m2m_txr_vert_cycles_full0.iv_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 event=0x94,umask=8  01    Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores unc_m2m_txr_vert_cycles_full1.akc_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 event=0x95,umask=1  01    Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_cycles_full1.akc_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 event=0x95,umask=2  01    Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_m2m_txr_vert_cycles_ne0.ad_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 event=0x96,umask=1  01    Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_cycles_ne0.ad_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 event=0x96,umask=0x10  01    Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests unc_m2m_txr_vert_cycles_ne0.ak_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 event=0x96,umask=2  01    Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_m2m_txr_vert_cycles_ne0.ak_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 event=0x96,umask=0x20  01    Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m2m_txr_vert_cycles_ne0.bl_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 event=0x96,umask=4  01    Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations unc_m2m_txr_vert_cycles_ne0.bl_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 event=0x96,umask=0x40  01    Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache unc_m2m_txr_vert_cycles_ne0.iv_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 event=0x96,umask=8  01    Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores unc_m2m_txr_vert_cycles_ne1.akc_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 event=0x97,umask=1  01    Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_cycles_ne1.akc_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 event=0x97,umask=2  01    Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_m2m_txr_vert_inserts0.ad_ag0 uncore interconnect CMS Vert Egress Allocations : AD - Agent 0 event=0x92,umask=1  01    CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_inserts0.ad_ag1 uncore interconnect CMS Vert Egress Allocations : AD - Agent 1 event=0x92,umask=0x10  01    CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests unc_m2m_txr_vert_inserts0.ak_ag0 uncore interconnect CMS Vert Egress Allocations : AK - Agent 0 event=0x92,umask=2  01    CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_m2m_txr_vert_inserts0.ak_ag1 uncore interconnect CMS Vert Egress Allocations : AK - Agent 1 event=0x92,umask=0x20  01    CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m2m_txr_vert_inserts0.bl_ag0 uncore interconnect CMS Vert Egress Allocations : BL - Agent 0 event=0x92,umask=4  01    CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations unc_m2m_txr_vert_inserts0.bl_ag1 uncore interconnect CMS Vert Egress Allocations : BL - Agent 1 event=0x92,umask=0x40  01    CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache unc_m2m_txr_vert_inserts0.iv_ag0 uncore interconnect CMS Vert Egress Allocations : IV - Agent 0 event=0x92,umask=8  01    CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores unc_m2m_txr_vert_inserts1.akc_ag0 uncore interconnect CMS Vert Egress Allocations : AKC - Agent 0 event=0x93,umask=1  01    CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_inserts1.akc_ag1 uncore interconnect CMS Vert Egress Allocations : AKC - Agent 1 event=0x93,umask=2  01    CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_m2m_txr_vert_nack0.ad_ag0 uncore interconnect CMS Vertical Egress NACKs : AD - Agent 0 event=0x98,umask=1  01    CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack0.ad_ag1 uncore interconnect CMS Vertical Egress NACKs : AD - Agent 1 event=0x98,umask=0x10  01    CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack0.ak_ag0 uncore interconnect CMS Vertical Egress NACKs : AK - Agent 0 event=0x98,umask=2  01    CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack0.ak_ag1 uncore interconnect CMS Vertical Egress NACKs : AK - Agent 1 event=0x98,umask=0x20  01    CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack0.bl_ag0 uncore interconnect CMS Vertical Egress NACKs : BL - Agent 0 event=0x98,umask=4  01    CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack0.bl_ag1 uncore interconnect CMS Vertical Egress NACKs : BL - Agent 1 event=0x98,umask=0x40  01    CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack0.iv_ag0 uncore interconnect CMS Vertical Egress NACKs : IV event=0x98,umask=8  01    CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack1.akc_ag0 uncore interconnect CMS Vertical Egress NACKs : AKC - Agent 0 event=0x99,umask=1  01    CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_nack1.akc_ag1 uncore interconnect CMS Vertical Egress NACKs : AKC - Agent 1 event=0x99,umask=2  01    CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2m_txr_vert_occupancy0.ad_ag0 uncore interconnect CMS Vert Egress Occupancy : AD - Agent 0 event=0x90,umask=1  01    CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_occupancy0.ad_ag1 uncore interconnect CMS Vert Egress Occupancy : AD - Agent 1 event=0x90,umask=0x10  01    CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests unc_m2m_txr_vert_occupancy0.ak_ag0 uncore interconnect CMS Vert Egress Occupancy : AK - Agent 0 event=0x90,umask=2  01    CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_m2m_txr_vert_occupancy0.ak_ag1 uncore interconnect CMS Vert Egress Occupancy : AK - Agent 1 event=0x90,umask=0x20  01    CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m2m_txr_vert_occupancy0.bl_ag0 uncore interconnect CMS Vert Egress Occupancy : BL - Agent 0 event=0x90,umask=4  01    CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations unc_m2m_txr_vert_occupancy0.bl_ag1 uncore interconnect CMS Vert Egress Occupancy : BL - Agent 1 event=0x90,umask=0x40  01    CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache unc_m2m_txr_vert_occupancy0.iv_ag0 uncore interconnect CMS Vert Egress Occupancy : IV - Agent 0 event=0x90,umask=8  01    CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores unc_m2m_txr_vert_occupancy1.akc_ag0 uncore interconnect CMS Vert Egress Occupancy : AKC - Agent 0 event=0x91,umask=1  01    CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_m2m_txr_vert_occupancy1.akc_ag1 uncore interconnect CMS Vert Egress Occupancy : AKC - Agent 1 event=0x91,umask=2  01    CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_m2m_txr_vert_starved0.ad_ag0 uncore interconnect CMS Vertical Egress Injection Starvation : AD - Agent 0 event=0x9a,umask=1  01    CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved0.ad_ag1 uncore interconnect CMS Vertical Egress Injection Starvation : AD - Agent 1 event=0x9a,umask=0x10  01    CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved0.ak_ag0 uncore interconnect CMS Vertical Egress Injection Starvation : AK - Agent 0 event=0x9a,umask=2  01    CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved0.ak_ag1 uncore interconnect CMS Vertical Egress Injection Starvation : AK - Agent 1 event=0x9a,umask=0x20  01    CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved0.bl_ag0 uncore interconnect CMS Vertical Egress Injection Starvation : BL - Agent 0 event=0x9a,umask=4  01    CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved0.bl_ag1 uncore interconnect CMS Vertical Egress Injection Starvation : BL - Agent 1 event=0x9a,umask=0x40  01    CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved0.iv_ag0 uncore interconnect CMS Vertical Egress Injection Starvation : IV event=0x9a,umask=8  01    CMS Vertical Egress Injection Starvation : IV : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved1.akc_ag0 uncore interconnect CMS Vertical Egress Injection Starvation : AKC - Agent 0 event=0x9b,umask=1  01    CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved1.akc_ag1 uncore interconnect CMS Vertical Egress Injection Starvation : AKC - Agent 1 event=0x9b,umask=2  01    CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_txr_vert_starved1.tgc uncore interconnect CMS Vertical Egress Injection Starvation : AKC - Agent 0 event=0x9b,umask=4  01    CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2m_vert_ring_ad_in_use.dn_even uncore interconnect Vertical AD Ring In Use : Down and Even event=0xb0,umask=4  01    Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ad_in_use.dn_odd uncore interconnect Vertical AD Ring In Use : Down and Odd event=0xb0,umask=8  01    Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ad_in_use.up_even uncore interconnect Vertical AD Ring In Use : Up and Even event=0xb0,umask=1  01    Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ad_in_use.up_odd uncore interconnect Vertical AD Ring In Use : Up and Odd event=0xb0,umask=2  01    Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_akc_in_use.dn_even uncore interconnect Vertical AKC Ring In Use : Down and Even event=0xb4,umask=4  01    Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_akc_in_use.dn_odd uncore interconnect Vertical AKC Ring In Use : Down and Odd event=0xb4,umask=8  01    Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_akc_in_use.up_even uncore interconnect Vertical AKC Ring In Use : Up and Even event=0xb4,umask=1  01    Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_akc_in_use.up_odd uncore interconnect Vertical AKC Ring In Use : Up and Odd event=0xb4,umask=2  01    Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ak_in_use.dn_even uncore interconnect Vertical AK Ring In Use : Down and Even event=0xb1,umask=4  01    Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ak_in_use.dn_odd uncore interconnect Vertical AK Ring In Use : Down and Odd event=0xb1,umask=8  01    Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ak_in_use.up_even uncore interconnect Vertical AK Ring In Use : Up and Even event=0xb1,umask=1  01    Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_ak_in_use.up_odd uncore interconnect Vertical AK Ring In Use : Up and Odd event=0xb1,umask=2  01    Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_bl_in_use.dn_even uncore interconnect Vertical BL Ring in Use : Down and Even event=0xb2,umask=4  01    Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_bl_in_use.dn_odd uncore interconnect Vertical BL Ring in Use : Down and Odd event=0xb2,umask=8  01    Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_bl_in_use.up_even uncore interconnect Vertical BL Ring in Use : Up and Even event=0xb2,umask=1  01    Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_bl_in_use.up_odd uncore interconnect Vertical BL Ring in Use : Up and Odd event=0xb2,umask=2  01    Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_iv_in_use.dn uncore interconnect Vertical IV Ring in Use : Down event=0xb3,umask=4  01    Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2m_vert_ring_iv_in_use.up uncore interconnect Vertical IV Ring in Use : Up event=0xb3,umask=1  01    Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2m_vert_ring_tgc_in_use.dn_even uncore interconnect Vertical TGC Ring In Use : Down and Even event=0xb5,umask=4  01    Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_tgc_in_use.dn_odd uncore interconnect Vertical TGC Ring In Use : Down and Odd event=0xb5,umask=8  01    Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_tgc_in_use.up_even uncore interconnect Vertical TGC Ring In Use : Up and Even event=0xb5,umask=1  01    Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_vert_ring_tgc_in_use.up_odd uncore interconnect Vertical TGC Ring In Use : Up and Odd event=0xb5,umask=2  01    Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2m_wpq_flush.ch0 uncore interconnect WPQ Flush : Channel 0 event=0x58,umask=1  01     unc_m2m_wpq_flush.ch1 uncore interconnect WPQ Flush : Channel 1 event=0x58,umask=2  01     unc_m2m_wpq_flush.ch2 uncore interconnect WPQ Flush : Channel 2 event=0x58,umask=4  01     unc_m2m_wpq_no_reg_crd.chn0 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular : Channel 0 event=0x4d,umask=1  01     unc_m2m_wpq_no_reg_crd.chn1 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular : Channel 1 event=0x4d,umask=2  01     unc_m2m_wpq_no_reg_crd.chn2 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Regular : Channel 2 event=0x4d,umask=4  01     unc_m2m_wpq_no_reg_crd_pmm.chn0 uncore interconnect M2M->iMC WPQ Cycles w/Credits - PMM : Channel 0 event=0x51,umask=1  01     unc_m2m_wpq_no_reg_crd_pmm.chn1 uncore interconnect M2M->iMC WPQ Cycles w/Credits - PMM : Channel 1 event=0x51,umask=2  01     unc_m2m_wpq_no_reg_crd_pmm.chn2 uncore interconnect M2M->iMC WPQ Cycles w/Credits - PMM : Channel 2 event=0x51,umask=4  01     unc_m2m_wpq_no_spec_crd.chn0 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Special : Channel 0 event=0x4e,umask=1  01     unc_m2m_wpq_no_spec_crd.chn1 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Special : Channel 1 event=0x4e,umask=2  01     unc_m2m_wpq_no_spec_crd.chn2 uncore interconnect M2M->iMC WPQ Cycles w/Credits - Special : Channel 2 event=0x4e,umask=4  01     unc_m2m_wr_tracker_full.ch0 uncore interconnect Write Tracker Cycles Full : Channel 0 event=0x4a,umask=1  01     unc_m2m_wr_tracker_full.ch1 uncore interconnect Write Tracker Cycles Full : Channel 1 event=0x4a,umask=2  01     unc_m2m_wr_tracker_full.ch2 uncore interconnect Write Tracker Cycles Full : Channel 2 event=0x4a,umask=4  01     unc_m2m_wr_tracker_full.mirr uncore interconnect Write Tracker Cycles Full : Mirror event=0x4a,umask=8  01     unc_m2m_wr_tracker_inserts.ch0 uncore interconnect Write Tracker Inserts : Channel 0 event=0x56,umask=1  01     unc_m2m_wr_tracker_inserts.ch1 uncore interconnect Write Tracker Inserts : Channel 1 event=0x56,umask=2  01     unc_m2m_wr_tracker_inserts.ch2 uncore interconnect Write Tracker Inserts : Channel 2 event=0x56,umask=4  01     unc_m2m_wr_tracker_ne.ch0 uncore interconnect Write Tracker Cycles Not Empty : Channel 0 event=0x4b,umask=1  01     unc_m2m_wr_tracker_ne.ch1 uncore interconnect Write Tracker Cycles Not Empty : Channel 1 event=0x4b,umask=2  01     unc_m2m_wr_tracker_ne.ch2 uncore interconnect Write Tracker Cycles Not Empty : Channel 2 event=0x4b,umask=4  01     unc_m2m_wr_tracker_ne.mirr uncore interconnect Write Tracker Cycles Not Empty : Mirror event=0x4b,umask=8  01     unc_m2m_wr_tracker_ne.mirr_nontgr uncore interconnect Write Tracker Cycles Not Empty event=0x4b,umask=0x10  01     unc_m2m_wr_tracker_ne.mirr_pwr uncore interconnect Write Tracker Cycles Not Empty event=0x4b,umask=0x20  01     unc_m2m_wr_tracker_nonposted_inserts.ch0 uncore interconnect Write Tracker Non-Posted Inserts : Channel 0 event=0x63,umask=1  01     unc_m2m_wr_tracker_nonposted_inserts.ch1 uncore interconnect Write Tracker Non-Posted Inserts : Channel 1 event=0x63,umask=2  01     unc_m2m_wr_tracker_nonposted_inserts.ch2 uncore interconnect Write Tracker Non-Posted Inserts : Channel 2 event=0x63,umask=4  01     unc_m2m_wr_tracker_nonposted_occupancy.ch0 uncore interconnect Write Tracker Non-Posted Occupancy : Channel 0 event=0x62,umask=1  01     unc_m2m_wr_tracker_nonposted_occupancy.ch1 uncore interconnect Write Tracker Non-Posted Occupancy : Channel 1 event=0x62,umask=2  01     unc_m2m_wr_tracker_nonposted_occupancy.ch2 uncore interconnect Write Tracker Non-Posted Occupancy : Channel 2 event=0x62,umask=4  01     unc_m2m_wr_tracker_occupancy.ch0 uncore interconnect Write Tracker Occupancy : Channel 0 event=0x55,umask=1  01     unc_m2m_wr_tracker_occupancy.ch1 uncore interconnect Write Tracker Occupancy : Channel 1 event=0x55,umask=2  01     unc_m2m_wr_tracker_occupancy.ch2 uncore interconnect Write Tracker Occupancy : Channel 2 event=0x55,umask=4  01     unc_m2m_wr_tracker_occupancy.mirr uncore interconnect Write Tracker Occupancy : Mirror event=0x55,umask=8  01     unc_m2m_wr_tracker_occupancy.mirr_nontgr uncore interconnect Write Tracker Occupancy event=0x55,umask=0x10  01     unc_m2m_wr_tracker_occupancy.mirr_pwr uncore interconnect Write Tracker Occupancy event=0x55,umask=0x20  01     unc_m2m_wr_tracker_posted_inserts.ch0 uncore interconnect Write Tracker Posted Inserts : Channel 0 event=0x5e,umask=1  01     unc_m2m_wr_tracker_posted_inserts.ch1 uncore interconnect Write Tracker Posted Inserts : Channel 1 event=0x5e,umask=2  01     unc_m2m_wr_tracker_posted_inserts.ch2 uncore interconnect Write Tracker Posted Inserts : Channel 2 event=0x5e,umask=4  01     unc_m2m_wr_tracker_posted_occupancy.ch0 uncore interconnect Write Tracker Posted Occupancy : Channel 0 event=0x5d,umask=1  01     unc_m2m_wr_tracker_posted_occupancy.ch1 uncore interconnect Write Tracker Posted Occupancy : Channel 1 event=0x5d,umask=2  01     unc_m2m_wr_tracker_posted_occupancy.ch2 uncore interconnect Write Tracker Posted Occupancy : Channel 2 event=0x5d,umask=4  01     unc_m3upi_ag0_ad_crd_acquired0.tgr0 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 0 event=0x80,umask=1  01    CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired0.tgr1 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 1 event=0x80,umask=2  01    CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired0.tgr2 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 2 event=0x80,umask=4  01    CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired0.tgr3 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 3 event=0x80,umask=8  01    CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired0.tgr4 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 4 event=0x80,umask=0x10  01    CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired0.tgr5 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 5 event=0x80,umask=0x20  01    CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired0.tgr6 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 6 event=0x80,umask=0x40  01    CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired0.tgr7 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 7 event=0x80,umask=0x80  01    CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired1.tgr10 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 10 event=0x81,umask=4  01    CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired1.tgr8 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 8 event=0x81,umask=1  01    CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_acquired1.tgr9 uncore interconnect CMS Agent0 AD Credits Acquired : For Transgress 9 event=0x81,umask=2  01    CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy0.tgr0 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 0 event=0x82,umask=1  01    CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy0.tgr1 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 1 event=0x82,umask=2  01    CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy0.tgr2 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 2 event=0x82,umask=4  01    CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy0.tgr3 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 3 event=0x82,umask=8  01    CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy0.tgr4 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 4 event=0x82,umask=0x10  01    CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy0.tgr5 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 5 event=0x82,umask=0x20  01    CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy0.tgr6 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 6 event=0x82,umask=0x40  01    CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy0.tgr7 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 7 event=0x82,umask=0x80  01    CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy1.tgr10 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 10 event=0x83,umask=4  01    CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy1.tgr8 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 8 event=0x83,umask=1  01    CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_ad_crd_occupancy1.tgr9 uncore interconnect CMS Agent0 AD Credits Occupancy : For Transgress 9 event=0x83,umask=2  01    CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired0.tgr0 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 0 event=0x88,umask=1  01    CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired0.tgr1 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 1 event=0x88,umask=2  01    CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired0.tgr2 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 2 event=0x88,umask=4  01    CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired0.tgr3 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 3 event=0x88,umask=8  01    CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired0.tgr4 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 4 event=0x88,umask=0x10  01    CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired0.tgr5 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 5 event=0x88,umask=0x20  01    CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired0.tgr6 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 6 event=0x88,umask=0x40  01    CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired0.tgr7 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 7 event=0x88,umask=0x80  01    CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired1.tgr10 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 10 event=0x89,umask=4  01    CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired1.tgr8 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 8 event=0x89,umask=1  01    CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_acquired1.tgr9 uncore interconnect CMS Agent0 BL Credits Acquired : For Transgress 9 event=0x89,umask=2  01    CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy0.tgr0 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 0 event=0x8a,umask=1  01    CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy0.tgr1 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 1 event=0x8a,umask=2  01    CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy0.tgr2 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 2 event=0x8a,umask=4  01    CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy0.tgr3 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 3 event=0x8a,umask=8  01    CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy0.tgr4 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 4 event=0x8a,umask=0x10  01    CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy0.tgr5 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 5 event=0x8a,umask=0x20  01    CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy0.tgr6 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 6 event=0x8a,umask=0x40  01    CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy0.tgr7 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 7 event=0x8a,umask=0x80  01    CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy1.tgr10 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 10 event=0x8b,umask=4  01    CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy1.tgr8 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 8 event=0x8b,umask=1  01    CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag0_bl_crd_occupancy1.tgr9 uncore interconnect CMS Agent0 BL Credits Occupancy : For Transgress 9 event=0x8b,umask=2  01    CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired0.tgr0 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 0 event=0x84,umask=1  01    CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired0.tgr1 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 1 event=0x84,umask=2  01    CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired0.tgr2 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 2 event=0x84,umask=4  01    CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired0.tgr3 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 3 event=0x84,umask=8  01    CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired0.tgr4 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 4 event=0x84,umask=0x10  01    CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired0.tgr5 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 5 event=0x84,umask=0x20  01    CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired0.tgr6 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 6 event=0x84,umask=0x40  01    CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired0.tgr7 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 7 event=0x84,umask=0x80  01    CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired1.tgr10 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 10 event=0x85,umask=4  01    CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired1.tgr8 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 8 event=0x85,umask=1  01    CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_acquired1.tgr9 uncore interconnect CMS Agent1 AD Credits Acquired : For Transgress 9 event=0x85,umask=2  01    CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy0.tgr0 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 0 event=0x86,umask=1  01    CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy0.tgr1 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 1 event=0x86,umask=2  01    CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy0.tgr2 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 2 event=0x86,umask=4  01    CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy0.tgr3 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 3 event=0x86,umask=8  01    CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy0.tgr4 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 4 event=0x86,umask=0x10  01    CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy0.tgr5 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 5 event=0x86,umask=0x20  01    CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy0.tgr6 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 6 event=0x86,umask=0x40  01    CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy0.tgr7 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 7 event=0x86,umask=0x80  01    CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy1.tgr10 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 10 event=0x87,umask=4  01    CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy1.tgr8 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 8 event=0x87,umask=1  01    CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_ad_crd_occupancy1.tgr9 uncore interconnect CMS Agent1 AD Credits Occupancy : For Transgress 9 event=0x87,umask=2  01    CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired0.tgr0 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 0 event=0x8c,umask=1  01    CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired0.tgr1 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 1 event=0x8c,umask=2  01    CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired0.tgr2 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 2 event=0x8c,umask=4  01    CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired0.tgr3 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 3 event=0x8c,umask=8  01    CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired0.tgr4 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 4 event=0x8c,umask=0x10  01    CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired0.tgr5 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 5 event=0x8c,umask=0x20  01    CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired0.tgr6 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 4 event=0x8c,umask=0x40  01    CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired0.tgr7 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 5 event=0x8c,umask=0x80  01    CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired1.tgr10 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 10 event=0x8d,umask=4  01    CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired1.tgr8 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 8 event=0x8d,umask=1  01    CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_acquired1.tgr9 uncore interconnect CMS Agent1 BL Credits Acquired : For Transgress 9 event=0x8d,umask=2  01    CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy0.tgr0 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 0 event=0x8e,umask=1  01    CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy0.tgr1 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 1 event=0x8e,umask=2  01    CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy0.tgr2 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 2 event=0x8e,umask=4  01    CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy0.tgr3 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 3 event=0x8e,umask=8  01    CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy0.tgr4 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 4 event=0x8e,umask=0x10  01    CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy0.tgr5 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 5 event=0x8e,umask=0x20  01    CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy0.tgr6 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 6 event=0x8e,umask=0x40  01    CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy0.tgr7 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 7 event=0x8e,umask=0x80  01    CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy1.tgr10 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 10 event=0x8f,umask=4  01    CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy1.tgr8 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 8 event=0x8f,umask=1  01    CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_ag1_bl_crd_occupancy1.tgr9 uncore interconnect CMS Agent1 BL Credits Occupancy : For Transgress 9 event=0x8f,umask=2  01    CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m3upi_clockticks uncore interconnect Clockticks of the mesh to UPI (M3UPI) event=1  01    Clockticks of the mesh to UPI (M3UPI) : Counts the number of uclks in the M3 uclk domain.  This could be slightly different than the count in the Ubox because of enable/freeze delays.  However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles unc_m3upi_distress_asserted.dpt_local uncore interconnect Distress signal asserted : DPT Local event=0xaf,umask=4  01    Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile unc_m3upi_distress_asserted.dpt_nonlocal uncore interconnect Distress signal asserted : DPT Remote event=0xaf,umask=8  01    Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile unc_m3upi_distress_asserted.dpt_stall_iv uncore interconnect Distress signal asserted : DPT Stalled - IV event=0xaf,umask=0x40  01    Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled unc_m3upi_distress_asserted.dpt_stall_nocrd uncore interconnect Distress signal asserted : DPT Stalled -  No Credit event=0xaf,umask=0x80  01    Distress signal asserted : DPT Stalled -  No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled unc_m3upi_distress_asserted.horz uncore interconnect Distress signal asserted : Horizontal event=0xaf,umask=2  01    Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions unc_m3upi_distress_asserted.pmm_local uncore interconnect Distress signal asserted : PMM Local event=0xaf,umask=0x10  01    Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic unc_m3upi_distress_asserted.pmm_nonlocal uncore interconnect Distress signal asserted : PMM Remote event=0xaf,umask=0x20  01    Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic unc_m3upi_distress_asserted.vert uncore interconnect Distress signal asserted : Vertical event=0xaf,umask=1  01    Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions unc_m3upi_horz_ring_ad_in_use.left_even uncore interconnect Horizontal AD Ring In Use : Left and Even event=0xb6,umask=1  01    Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ad_in_use.left_odd uncore interconnect Horizontal AD Ring In Use : Left and Odd event=0xb6,umask=2  01    Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ad_in_use.right_even uncore interconnect Horizontal AD Ring In Use : Right and Even event=0xb6,umask=4  01    Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ad_in_use.right_odd uncore interconnect Horizontal AD Ring In Use : Right and Odd event=0xb6,umask=8  01    Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_akc_in_use.left_even uncore interconnect Horizontal AK Ring In Use : Left and Even event=0xbb,umask=1  01    Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_akc_in_use.left_odd uncore interconnect Horizontal AK Ring In Use : Left and Odd event=0xbb,umask=2  01    Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_akc_in_use.right_even uncore interconnect Horizontal AK Ring In Use : Right and Even event=0xbb,umask=4  01    Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_akc_in_use.right_odd uncore interconnect Horizontal AK Ring In Use : Right and Odd event=0xbb,umask=8  01    Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ak_in_use.left_even uncore interconnect Horizontal AK Ring In Use : Left and Even event=0xb7,umask=1  01    Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ak_in_use.left_odd uncore interconnect Horizontal AK Ring In Use : Left and Odd event=0xb7,umask=2  01    Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ak_in_use.right_even uncore interconnect Horizontal AK Ring In Use : Right and Even event=0xb7,umask=4  01    Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_ak_in_use.right_odd uncore interconnect Horizontal AK Ring In Use : Right and Odd event=0xb7,umask=8  01    Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_bl_in_use.left_even uncore interconnect Horizontal BL Ring in Use : Left and Even event=0xb8,umask=1  01    Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_bl_in_use.left_odd uncore interconnect Horizontal BL Ring in Use : Left and Odd event=0xb8,umask=2  01    Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_bl_in_use.right_even uncore interconnect Horizontal BL Ring in Use : Right and Even event=0xb8,umask=4  01    Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_bl_in_use.right_odd uncore interconnect Horizontal BL Ring in Use : Right and Odd event=0xb8,umask=8  01    Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_horz_ring_iv_in_use.left uncore interconnect Horizontal IV Ring in Use : Left event=0xb9,umask=1  01    Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m3upi_horz_ring_iv_in_use.right uncore interconnect Horizontal IV Ring in Use : Right event=0xb9,umask=4  01    Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m3upi_misc_external.mbe_inst0 uncore interconnect Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0 event=0xe6,umask=1  01     unc_m3upi_misc_external.mbe_inst1 uncore interconnect Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1 event=0xe6,umask=2  01     unc_m3upi_ring_bounces_horz.ad uncore interconnect Messages that bounced on the Horizontal Ring. : AD event=0xac,umask=1  01    Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m3upi_ring_bounces_horz.ak uncore interconnect Messages that bounced on the Horizontal Ring. : AK event=0xac,umask=2  01    Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m3upi_ring_bounces_horz.bl uncore interconnect Messages that bounced on the Horizontal Ring. : BL event=0xac,umask=4  01    Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m3upi_ring_bounces_horz.iv uncore interconnect Messages that bounced on the Horizontal Ring. : IV event=0xac,umask=8  01    Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m3upi_ring_bounces_vert.ad uncore interconnect Messages that bounced on the Vertical Ring. : AD event=0xaa,umask=1  01    Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m3upi_ring_bounces_vert.ak uncore interconnect Messages that bounced on the Vertical Ring. : Acknowledgements to core event=0xaa,umask=2  01    Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m3upi_ring_bounces_vert.akc uncore interconnect Messages that bounced on the Vertical Ring event=0xaa,umask=0x10  01    Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m3upi_ring_bounces_vert.bl uncore interconnect Messages that bounced on the Vertical Ring. : Data Responses to core event=0xaa,umask=4  01    Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m3upi_ring_bounces_vert.iv uncore interconnect Messages that bounced on the Vertical Ring. : Snoops of processor's cache event=0xaa,umask=8  01    Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m3upi_ring_sink_starved_horz.ad uncore interconnect Sink Starvation on Horizontal Ring : AD event=0xad,umask=1  01     unc_m3upi_ring_sink_starved_horz.ak uncore interconnect Sink Starvation on Horizontal Ring : AK event=0xad,umask=2  01     unc_m3upi_ring_sink_starved_horz.ak_ag1 uncore interconnect Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1 event=0xad,umask=0x20  01     unc_m3upi_ring_sink_starved_horz.bl uncore interconnect Sink Starvation on Horizontal Ring : BL event=0xad,umask=4  01     unc_m3upi_ring_sink_starved_horz.iv uncore interconnect Sink Starvation on Horizontal Ring : IV event=0xad,umask=8  01     unc_m3upi_ring_sink_starved_vert.ad uncore interconnect Sink Starvation on Vertical Ring : AD event=0xab,umask=1  01     unc_m3upi_ring_sink_starved_vert.ak uncore interconnect Sink Starvation on Vertical Ring : Acknowledgements to core event=0xab,umask=2  01     unc_m3upi_ring_sink_starved_vert.akc uncore interconnect Sink Starvation on Vertical Ring event=0xab,umask=0x10  01     unc_m3upi_ring_sink_starved_vert.bl uncore interconnect Sink Starvation on Vertical Ring : Data Responses to core event=0xab,umask=4  01     unc_m3upi_ring_sink_starved_vert.iv uncore interconnect Sink Starvation on Vertical Ring : Snoops of processor's cache event=0xab,umask=8  01     unc_m3upi_ring_src_thrtl uncore interconnect Source Throttle event=0xae  01     unc_m3upi_rxc_cycles_ne_vn1.ad_req uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD event=0x44,umask=1  01    VN1 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD : Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_cycles_ne_vn1.ad_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD event=0x44,umask=4  01    VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD : Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_cycles_ne_vn1.ad_snp uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD event=0x44,umask=2  01    VN1 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD : Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_rxc_cycles_ne_vn1.bl_ncb uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL event=0x44,umask=0x20  01    VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL : Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_rxc_cycles_ne_vn1.bl_ncs uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL event=0x44,umask=0x40  01    VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL : Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_cycles_ne_vn1.bl_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL event=0x44,umask=8  01    VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL : Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_cycles_ne_vn1.bl_wb uncore interconnect VN1 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL event=0x44,umask=0x10  01    VN1 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL : Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_inserts_vn0.ad_req uncore interconnect VN0 Ingress (from CMS) Queue - Inserts : REQ on AD event=0x41,umask=1  01    VN0 Ingress (from CMS) Queue - Inserts : REQ on AD : Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_inserts_vn0.ad_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Inserts : RSP on AD event=0x41,umask=4  01    VN0 Ingress (from CMS) Queue - Inserts : RSP on AD : Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_inserts_vn0.ad_snp uncore interconnect VN0 Ingress (from CMS) Queue - Inserts : SNP on AD event=0x41,umask=2  01    VN0 Ingress (from CMS) Queue - Inserts : SNP on AD : Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_rxc_inserts_vn0.bl_ncb uncore interconnect VN0 Ingress (from CMS) Queue - Inserts : NCB on BL event=0x41,umask=0x20  01    VN0 Ingress (from CMS) Queue - Inserts : NCB on BL : Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_rxc_inserts_vn0.bl_ncs uncore interconnect VN0 Ingress (from CMS) Queue - Inserts : NCS on BL event=0x41,umask=0x40  01    VN0 Ingress (from CMS) Queue - Inserts : NCS on BL : Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_inserts_vn0.bl_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Inserts : RSP on BL event=0x41,umask=8  01    VN0 Ingress (from CMS) Queue - Inserts : RSP on BL : Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_inserts_vn0.bl_wb uncore interconnect VN0 Ingress (from CMS) Queue - Inserts : WB on BL event=0x41,umask=0x10  01    VN0 Ingress (from CMS) Queue - Inserts : WB on BL : Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_inserts_vn1.ad_req uncore interconnect VN1 Ingress (from CMS) Queue - Inserts : REQ on AD event=0x42,umask=1  01    VN1 Ingress (from CMS) Queue - Inserts : REQ on AD : Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_inserts_vn1.ad_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Inserts : RSP on AD event=0x42,umask=4  01    VN1 Ingress (from CMS) Queue - Inserts : RSP on AD : Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_inserts_vn1.ad_snp uncore interconnect VN1 Ingress (from CMS) Queue - Inserts : SNP on AD event=0x42,umask=2  01    VN1 Ingress (from CMS) Queue - Inserts : SNP on AD : Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_rxc_inserts_vn1.bl_ncb uncore interconnect VN1 Ingress (from CMS) Queue - Inserts : NCB on BL event=0x42,umask=0x20  01    VN1 Ingress (from CMS) Queue - Inserts : NCB on BL : Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_rxc_inserts_vn1.bl_ncs uncore interconnect VN1 Ingress (from CMS) Queue - Inserts : NCS on BL event=0x42,umask=0x40  01    VN1 Ingress (from CMS) Queue - Inserts : NCS on BL : Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_inserts_vn1.bl_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Inserts : RSP on BL event=0x42,umask=8  01    VN1 Ingress (from CMS) Queue - Inserts : RSP on BL : Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_inserts_vn1.bl_wb uncore interconnect VN1 Ingress (from CMS) Queue - Inserts : WB on BL event=0x42,umask=0x10  01    VN1 Ingress (from CMS) Queue - Inserts : WB on BL : Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_occupancy_vn0.ad_req uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy : REQ on AD event=0x45,umask=1  01    VN0 Ingress (from CMS) Queue - Occupancy : REQ on AD : Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency. : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_occupancy_vn0.ad_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy : RSP on AD event=0x45,umask=4  01    VN0 Ingress (from CMS) Queue - Occupancy : RSP on AD : Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_occupancy_vn0.ad_snp uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy : SNP on AD event=0x45,umask=2  01    VN0 Ingress (from CMS) Queue - Occupancy : SNP on AD : Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency. : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_rxc_occupancy_vn0.bl_ncb uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy : NCB on BL event=0x45,umask=0x20  01    VN0 Ingress (from CMS) Queue - Occupancy : NCB on BL : Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_rxc_occupancy_vn0.bl_ncs uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy : NCS on BL event=0x45,umask=0x40  01    VN0 Ingress (from CMS) Queue - Occupancy : NCS on BL : Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_occupancy_vn0.bl_rsp uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy : RSP on BL event=0x45,umask=8  01    VN0 Ingress (from CMS) Queue - Occupancy : RSP on BL : Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_occupancy_vn0.bl_wb uncore interconnect VN0 Ingress (from CMS) Queue - Occupancy : WB on BL event=0x45,umask=0x10  01    VN0 Ingress (from CMS) Queue - Occupancy : WB on BL : Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency. : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxc_occupancy_vn1.ad_req uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy : REQ on AD event=0x46,umask=1  01    VN1 Ingress (from CMS) Queue - Occupancy : REQ on AD : Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency. : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses unc_m3upi_rxc_occupancy_vn1.ad_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy : RSP on AD event=0x46,umask=4  01    VN1 Ingress (from CMS) Queue - Occupancy : RSP on AD : Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_occupancy_vn1.ad_snp uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy : SNP on AD event=0x46,umask=2  01    VN1 Ingress (from CMS) Queue - Occupancy : SNP on AD : Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency. : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops unc_m3upi_rxc_occupancy_vn1.bl_ncb uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy : NCB on BL event=0x46,umask=0x20  01    VN1 Ingress (from CMS) Queue - Occupancy : NCB on BL : Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns unc_m3upi_rxc_occupancy_vn1.bl_ncs uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy : NCS on BL event=0x46,umask=0x40  01    VN1 Ingress (from CMS) Queue - Occupancy : NCS on BL : Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Standard (NCS) messages on BL unc_m3upi_rxc_occupancy_vn1.bl_rsp uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy : RSP on BL event=0x46,umask=8  01    VN1 Ingress (from CMS) Queue - Occupancy : RSP on BL : Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP) unc_m3upi_rxc_occupancy_vn1.bl_wb uncore interconnect VN1 Ingress (from CMS) Queue - Occupancy : WB on BL event=0x46,umask=0x10  01    VN1 Ingress (from CMS) Queue - Occupancy : WB on BL : Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency. : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB unc_m3upi_rxr_busy_starved.ad_all uncore interconnect Transgress Injection Starvation : AD - All event=0xe5,umask=0x11  01    Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority : All == Credited + Uncredited unc_m3upi_rxr_busy_starved.ad_crd uncore interconnect Transgress Injection Starvation : AD - Credited event=0xe5,umask=0x10  01    Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority unc_m3upi_rxr_busy_starved.ad_uncrd uncore interconnect Transgress Injection Starvation : AD - Uncredited event=0xe5,umask=1  01    Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority unc_m3upi_rxr_busy_starved.bl_all uncore interconnect Transgress Injection Starvation : BL - All event=0xe5,umask=0x44  01    Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority : All == Credited + Uncredited unc_m3upi_rxr_busy_starved.bl_crd uncore interconnect Transgress Injection Starvation : BL - Credited event=0xe5,umask=0x40  01    Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority unc_m3upi_rxr_busy_starved.bl_uncrd uncore interconnect Transgress Injection Starvation : BL - Uncredited event=0xe5,umask=4  01    Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority unc_m3upi_rxr_bypass.ad_all uncore interconnect Transgress Ingress Bypass : AD - All event=0xe2,umask=0x11  01    Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited unc_m3upi_rxr_bypass.ad_crd uncore interconnect Transgress Ingress Bypass : AD - Credited event=0xe2,umask=0x10  01    Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.ad_uncrd uncore interconnect Transgress Ingress Bypass : AD - Uncredited event=0xe2,umask=1  01    Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.ak uncore interconnect Transgress Ingress Bypass : AK event=0xe2,umask=2  01    Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.akc_uncrd uncore interconnect Transgress Ingress Bypass : AKC - Uncredited event=0xe2,umask=0x80  01    Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.bl_all uncore interconnect Transgress Ingress Bypass : BL - All event=0xe2,umask=0x44  01    Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited unc_m3upi_rxr_bypass.bl_crd uncore interconnect Transgress Ingress Bypass : BL - Credited event=0xe2,umask=0x40  01    Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.bl_uncrd uncore interconnect Transgress Ingress Bypass : BL - Uncredited event=0xe2,umask=4  01    Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress unc_m3upi_rxr_bypass.iv uncore interconnect Transgress Ingress Bypass : IV event=0xe2,umask=8  01    Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress unc_m3upi_rxr_crd_starved.ad_all uncore interconnect Transgress Injection Starvation : AD - All event=0xe3,umask=0x11  01    Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited unc_m3upi_rxr_crd_starved.ad_crd uncore interconnect Transgress Injection Starvation : AD - Credited event=0xe3,umask=0x10  01    Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.ad_uncrd uncore interconnect Transgress Injection Starvation : AD - Uncredited event=0xe3,umask=1  01    Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.ak uncore interconnect Transgress Injection Starvation : AK event=0xe3,umask=2  01    Transgress Injection Starvation : AK : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.bl_all uncore interconnect Transgress Injection Starvation : BL - All event=0xe3,umask=0x44  01    Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited unc_m3upi_rxr_crd_starved.bl_crd uncore interconnect Transgress Injection Starvation : BL - Credited event=0xe3,umask=0x40  01    Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.bl_uncrd uncore interconnect Transgress Injection Starvation : BL - Uncredited event=0xe3,umask=4  01    Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.ifv uncore interconnect Transgress Injection Starvation : IFV - Credited event=0xe3,umask=0x80  01    Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved.iv uncore interconnect Transgress Injection Starvation : IV event=0xe3,umask=8  01    Transgress Injection Starvation : IV : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_crd_starved_1 uncore interconnect Transgress Injection Starvation event=0xe4  01    Transgress Injection Starvation : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m3upi_rxr_inserts.ad_all uncore interconnect Transgress Ingress Allocations : AD - All event=0xe1,umask=0x11  01    Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m3upi_rxr_inserts.ad_crd uncore interconnect Transgress Ingress Allocations : AD - Credited event=0xe1,umask=0x10  01    Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.ad_uncrd uncore interconnect Transgress Ingress Allocations : AD - Uncredited event=0xe1,umask=1  01    Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.ak uncore interconnect Transgress Ingress Allocations : AK event=0xe1,umask=2  01    Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.akc_uncrd uncore interconnect Transgress Ingress Allocations : AKC - Uncredited event=0xe1,umask=0x80  01    Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.bl_all uncore interconnect Transgress Ingress Allocations : BL - All event=0xe1,umask=0x44  01    Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m3upi_rxr_inserts.bl_crd uncore interconnect Transgress Ingress Allocations : BL - Credited event=0xe1,umask=0x40  01    Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.bl_uncrd uncore interconnect Transgress Ingress Allocations : BL - Uncredited event=0xe1,umask=4  01    Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_inserts.iv uncore interconnect Transgress Ingress Allocations : IV event=0xe1,umask=8  01    Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.ad_all uncore interconnect Transgress Ingress Occupancy : AD - All event=0xe0,umask=0x11  01    Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m3upi_rxr_occupancy.ad_crd uncore interconnect Transgress Ingress Occupancy : AD - Credited event=0xe0,umask=0x10  01    Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.ad_uncrd uncore interconnect Transgress Ingress Occupancy : AD - Uncredited event=0xe0,umask=1  01    Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.ak uncore interconnect Transgress Ingress Occupancy : AK event=0xe0,umask=2  01    Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.akc_uncrd uncore interconnect Transgress Ingress Occupancy : AKC - Uncredited event=0xe0,umask=0x80  01    Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.bl_all uncore interconnect Transgress Ingress Occupancy : BL - All event=0xe0,umask=0x44  01    Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m3upi_rxr_occupancy.bl_crd uncore interconnect Transgress Ingress Occupancy : BL - Credited event=0xe0,umask=0x20  01    Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.bl_uncrd uncore interconnect Transgress Ingress Occupancy : BL - Uncredited event=0xe0,umask=4  01    Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m3upi_rxr_occupancy.iv uncore interconnect Transgress Ingress Occupancy : IV event=0xe0,umask=8  01    Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m3upi_stall0_no_txr_horz_crd_ad_ag0.tgr0 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 0 event=0xd0,umask=1  01    Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag0.tgr1 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 1 event=0xd0,umask=2  01    Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag0.tgr2 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 2 event=0xd0,umask=4  01    Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag0.tgr3 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 3 event=0xd0,umask=8  01    Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag0.tgr4 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 4 event=0xd0,umask=0x10  01    Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag0.tgr5 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 5 event=0xd0,umask=0x20  01    Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag0.tgr6 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 6 event=0xd0,umask=0x40  01    Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag0.tgr7 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 7 event=0xd0,umask=0x80  01    Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag1.tgr0 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 0 event=0xd2,umask=1  01    Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag1.tgr1 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 1 event=0xd2,umask=2  01    Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag1.tgr2 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 2 event=0xd2,umask=4  01    Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag1.tgr3 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 3 event=0xd2,umask=8  01    Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag1.tgr4 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 4 event=0xd2,umask=0x10  01    Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag1.tgr5 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 5 event=0xd2,umask=0x20  01    Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag1.tgr6 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 6 event=0xd2,umask=0x40  01    Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_ad_ag1.tgr7 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 7 event=0xd2,umask=0x80  01    Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag0.tgr0 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 0 event=0xd4,umask=1  01    Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag0.tgr1 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 1 event=0xd4,umask=2  01    Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag0.tgr2 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 2 event=0xd4,umask=4  01    Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag0.tgr3 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 3 event=0xd4,umask=8  01    Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag0.tgr4 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 4 event=0xd4,umask=0x10  01    Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag0.tgr5 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 5 event=0xd4,umask=0x20  01    Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag0.tgr6 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 6 event=0xd4,umask=0x40  01    Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag0.tgr7 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 7 event=0xd4,umask=0x80  01    Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag1.tgr0 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 0 event=0xd6,umask=1  01    Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag1.tgr1 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 1 event=0xd6,umask=2  01    Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag1.tgr2 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 2 event=0xd6,umask=4  01    Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag1.tgr3 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 3 event=0xd6,umask=8  01    Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag1.tgr4 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 4 event=0xd6,umask=0x10  01    Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag1.tgr5 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 5 event=0xd6,umask=0x20  01    Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag1.tgr6 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 6 event=0xd6,umask=0x40  01    Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall0_no_txr_horz_crd_bl_ag1.tgr7 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 7 event=0xd6,umask=0x80  01    Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_ad_ag0.tgr10 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 10 event=0xd1,umask=4  01    Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_ad_ag0.tgr8 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 8 event=0xd1,umask=1  01    Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_ad_ag0.tgr9 uncore interconnect Stall on No AD Agent0 Transgress Credits : For Transgress 9 event=0xd1,umask=2  01    Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_ad_ag1_1.tgr10 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 10 event=0xd3,umask=4  01    Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_ad_ag1_1.tgr8 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 8 event=0xd3,umask=1  01    Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_ad_ag1_1.tgr9 uncore interconnect Stall on No AD Agent1 Transgress Credits : For Transgress 9 event=0xd3,umask=2  01    Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_bl_ag0_1.tgr10 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 10 event=0xd5,umask=4  01    Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_bl_ag0_1.tgr8 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 8 event=0xd5,umask=1  01    Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_bl_ag0_1.tgr9 uncore interconnect Stall on No BL Agent0 Transgress Credits : For Transgress 9 event=0xd5,umask=2  01    Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_bl_ag1_1.tgr10 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 10 event=0xd7,umask=4  01    Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_bl_ag1_1.tgr8 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 8 event=0xd7,umask=1  01    Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_stall1_no_txr_horz_crd_bl_ag1_1.tgr9 uncore interconnect Stall on No BL Agent1 Transgress Credits : For Transgress 9 event=0xd7,umask=2  01    Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m3upi_txr_horz_ads_used.ad_all uncore interconnect CMS Horizontal ADS Used : AD - All event=0xa6,umask=0x11  01    CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m3upi_txr_horz_ads_used.ad_crd uncore interconnect CMS Horizontal ADS Used : AD - Credited event=0xa6,umask=0x10  01    CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_horz_ads_used.ad_uncrd uncore interconnect CMS Horizontal ADS Used : AD - Uncredited event=0xa6,umask=1  01    CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_horz_ads_used.bl_all uncore interconnect CMS Horizontal ADS Used : BL - All event=0xa6,umask=0x44  01    CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m3upi_txr_horz_ads_used.bl_crd uncore interconnect CMS Horizontal ADS Used : BL - Credited event=0xa6,umask=0x40  01    CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_horz_ads_used.bl_uncrd uncore interconnect CMS Horizontal ADS Used : BL - Uncredited event=0xa6,umask=4  01    CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.ad_all uncore interconnect CMS Horizontal Bypass Used : AD - All event=0xa7,umask=0x11  01    CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m3upi_txr_horz_bypass.ad_crd uncore interconnect CMS Horizontal Bypass Used : AD - Credited event=0xa7,umask=0x10  01    CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.ad_uncrd uncore interconnect CMS Horizontal Bypass Used : AD - Uncredited event=0xa7,umask=1  01    CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.ak uncore interconnect CMS Horizontal Bypass Used : AK event=0xa7,umask=2  01    CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.akc_uncrd uncore interconnect CMS Horizontal Bypass Used : AKC - Uncredited event=0xa7,umask=0x80  01    CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.bl_all uncore interconnect CMS Horizontal Bypass Used : BL - All event=0xa7,umask=0x44  01    CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m3upi_txr_horz_bypass.bl_crd uncore interconnect CMS Horizontal Bypass Used : BL - Credited event=0xa7,umask=0x40  01    CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.bl_uncrd uncore interconnect CMS Horizontal Bypass Used : BL - Uncredited event=0xa7,umask=4  01    CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_bypass.iv uncore interconnect CMS Horizontal Bypass Used : IV event=0xa7,umask=8  01    CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m3upi_txr_horz_cycles_full.ad_all uncore interconnect Cycles CMS Horizontal Egress Queue is Full : AD - All event=0xa2,umask=0x11  01    Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m3upi_txr_horz_cycles_full.ad_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Full : AD - Credited event=0xa2,umask=0x10  01    Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.ad_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited event=0xa2,umask=1  01    Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.ak uncore interconnect Cycles CMS Horizontal Egress Queue is Full : AK event=0xa2,umask=2  01    Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.akc_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited event=0xa2,umask=0x80  01    Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.bl_all uncore interconnect Cycles CMS Horizontal Egress Queue is Full : BL - All event=0xa2,umask=0x44  01    Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m3upi_txr_horz_cycles_full.bl_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Full : BL - Credited event=0xa2,umask=0x40  01    Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.bl_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited event=0xa2,umask=4  01    Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_full.iv uncore interconnect Cycles CMS Horizontal Egress Queue is Full : IV event=0xa2,umask=8  01    Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.ad_all uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : AD - All event=0xa3,umask=0x11  01    Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m3upi_txr_horz_cycles_ne.ad_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited event=0xa3,umask=0x10  01    Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.ad_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited event=0xa3,umask=1  01    Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.ak uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : AK event=0xa3,umask=2  01    Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.akc_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited event=0xa3,umask=0x80  01    Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.bl_all uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : BL - All event=0xa3,umask=0x44  01    Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m3upi_txr_horz_cycles_ne.bl_crd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited event=0xa3,umask=0x40  01    Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.bl_uncrd uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited event=0xa3,umask=4  01    Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_cycles_ne.iv uncore interconnect Cycles CMS Horizontal Egress Queue is Not Empty : IV event=0xa3,umask=8  01    Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.ad_all uncore interconnect CMS Horizontal Egress Inserts : AD - All event=0xa1,umask=0x11  01    CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m3upi_txr_horz_inserts.ad_crd uncore interconnect CMS Horizontal Egress Inserts : AD - Credited event=0xa1,umask=0x10  01    CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.ad_uncrd uncore interconnect CMS Horizontal Egress Inserts : AD - Uncredited event=0xa1,umask=1  01    CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.ak uncore interconnect CMS Horizontal Egress Inserts : AK event=0xa1,umask=2  01    CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.akc_uncrd uncore interconnect CMS Horizontal Egress Inserts : AKC - Uncredited event=0xa1,umask=0x80  01    CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.bl_all uncore interconnect CMS Horizontal Egress Inserts : BL - All event=0xa1,umask=0x44  01    CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m3upi_txr_horz_inserts.bl_crd uncore interconnect CMS Horizontal Egress Inserts : BL - Credited event=0xa1,umask=0x40  01    CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.bl_uncrd uncore interconnect CMS Horizontal Egress Inserts : BL - Uncredited event=0xa1,umask=4  01    CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_inserts.iv uncore interconnect CMS Horizontal Egress Inserts : IV event=0xa1,umask=8  01    CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_nack.ad_all uncore interconnect CMS Horizontal Egress NACKs : AD - All event=0xa4,umask=0x11  01    CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited unc_m3upi_txr_horz_nack.ad_crd uncore interconnect CMS Horizontal Egress NACKs : AD - Credited event=0xa4,umask=0x10  01    CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.ad_uncrd uncore interconnect CMS Horizontal Egress NACKs : AD - Uncredited event=0xa4,umask=1  01    CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.ak uncore interconnect CMS Horizontal Egress NACKs : AK event=0xa4,umask=2  01    CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.akc_uncrd uncore interconnect CMS Horizontal Egress NACKs : AKC - Uncredited event=0xa4,umask=0x80  01    CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.bl_all uncore interconnect CMS Horizontal Egress NACKs : BL - All event=0xa4,umask=0x44  01    CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited unc_m3upi_txr_horz_nack.bl_crd uncore interconnect CMS Horizontal Egress NACKs : BL - Credited event=0xa4,umask=0x40  01    CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.bl_uncrd uncore interconnect CMS Horizontal Egress NACKs : BL - Uncredited event=0xa4,umask=4  01    CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_nack.iv uncore interconnect CMS Horizontal Egress NACKs : IV event=0xa4,umask=8  01    CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m3upi_txr_horz_occupancy.ad_all uncore interconnect CMS Horizontal Egress Occupancy : AD - All event=0xa0,umask=0x11  01    CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m3upi_txr_horz_occupancy.ad_crd uncore interconnect CMS Horizontal Egress Occupancy : AD - Credited event=0xa0,umask=0x10  01    CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.ad_uncrd uncore interconnect CMS Horizontal Egress Occupancy : AD - Uncredited event=0xa0,umask=1  01    CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.ak uncore interconnect CMS Horizontal Egress Occupancy : AK event=0xa0,umask=2  01    CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.akc_uncrd uncore interconnect CMS Horizontal Egress Occupancy : AKC - Uncredited event=0xa0,umask=0x80  01    CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.bl_all uncore interconnect CMS Horizontal Egress Occupancy : BL - All event=0xa0,umask=0x44  01    CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m3upi_txr_horz_occupancy.bl_crd uncore interconnect CMS Horizontal Egress Occupancy : BL - Credited event=0xa0,umask=0x40  01    CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.bl_uncrd uncore interconnect CMS Horizontal Egress Occupancy : BL - Uncredited event=0xa0,umask=4  01    CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_occupancy.iv uncore interconnect CMS Horizontal Egress Occupancy : IV event=0xa0,umask=8  01    CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m3upi_txr_horz_starved.ad_all uncore interconnect CMS Horizontal Egress Injection Starvation : AD - All event=0xa5,umask=1  01    CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited unc_m3upi_txr_horz_starved.ad_uncrd uncore interconnect CMS Horizontal Egress Injection Starvation : AD - Uncredited event=0xa5,umask=1  01    CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m3upi_txr_horz_starved.ak uncore interconnect CMS Horizontal Egress Injection Starvation : AK event=0xa5,umask=2  01    CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m3upi_txr_horz_starved.akc_uncrd uncore interconnect CMS Horizontal Egress Injection Starvation : AKC - Uncredited event=0xa5,umask=0x80  01    CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m3upi_txr_horz_starved.bl_all uncore interconnect CMS Horizontal Egress Injection Starvation : BL - All event=0xa5,umask=4  01    CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited unc_m3upi_txr_horz_starved.bl_uncrd uncore interconnect CMS Horizontal Egress Injection Starvation : BL - Uncredited event=0xa5,umask=4  01    CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m3upi_txr_horz_starved.iv uncore interconnect CMS Horizontal Egress Injection Starvation : IV event=0xa5,umask=8  01    CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m3upi_txr_vert_ads_used.ad_ag0 uncore interconnect CMS Vertical ADS Used : AD - Agent 0 event=0x9c,umask=1  01    CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_vert_ads_used.ad_ag1 uncore interconnect CMS Vertical ADS Used : AD - Agent 1 event=0x9c,umask=0x10  01    CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_vert_ads_used.bl_ag0 uncore interconnect CMS Vertical ADS Used : BL - Agent 0 event=0x9c,umask=4  01    CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_vert_ads_used.bl_ag1 uncore interconnect CMS Vertical ADS Used : BL - Agent 1 event=0x9c,umask=0x40  01    CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.ad_ag0 uncore interconnect CMS Vertical ADS Used : AD - Agent 0 event=0x9d,umask=1  01    CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.ad_ag1 uncore interconnect CMS Vertical ADS Used : AD - Agent 1 event=0x9d,umask=0x10  01    CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.ak_ag0 uncore interconnect CMS Vertical ADS Used : AK - Agent 0 event=0x9d,umask=2  01    CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.ak_ag1 uncore interconnect CMS Vertical ADS Used : AK - Agent 1 event=0x9d,umask=0x20  01    CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.bl_ag0 uncore interconnect CMS Vertical ADS Used : BL - Agent 0 event=0x9d,umask=4  01    CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.bl_ag1 uncore interconnect CMS Vertical ADS Used : BL - Agent 1 event=0x9d,umask=0x40  01    CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass.iv_ag1 uncore interconnect CMS Vertical ADS Used : IV - Agent 1 event=0x9d,umask=8  01    CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass_1.akc_ag0 uncore interconnect CMS Vertical ADS Used : AKC - Agent 0 event=0x9e,umask=1  01    CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_bypass_1.akc_ag1 uncore interconnect CMS Vertical ADS Used : AKC - Agent 1 event=0x9e,umask=2  01    CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m3upi_txr_vert_cycles_full0.ad_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 event=0x94,umask=1  01    Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_cycles_full0.ad_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 event=0x94,umask=0x10  01    Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests unc_m3upi_txr_vert_cycles_full0.ak_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 event=0x94,umask=2  01    Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_cycles_full0.ak_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 event=0x94,umask=0x20  01    Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m3upi_txr_vert_cycles_full0.bl_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 event=0x94,umask=4  01    Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations unc_m3upi_txr_vert_cycles_full0.bl_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 event=0x94,umask=0x40  01    Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache unc_m3upi_txr_vert_cycles_full0.iv_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 event=0x94,umask=8  01    Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores unc_m3upi_txr_vert_cycles_full1.akc_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 event=0x95,umask=1  01    Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_cycles_full1.akc_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 event=0x95,umask=2  01    Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_cycles_ne0.ad_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 event=0x96,umask=1  01    Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_cycles_ne0.ad_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 event=0x96,umask=0x10  01    Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests unc_m3upi_txr_vert_cycles_ne0.ak_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 event=0x96,umask=2  01    Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_cycles_ne0.ak_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 event=0x96,umask=0x20  01    Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m3upi_txr_vert_cycles_ne0.bl_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 event=0x96,umask=4  01    Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations unc_m3upi_txr_vert_cycles_ne0.bl_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 event=0x96,umask=0x40  01    Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache unc_m3upi_txr_vert_cycles_ne0.iv_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 event=0x96,umask=8  01    Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores unc_m3upi_txr_vert_cycles_ne1.akc_ag0 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 event=0x97,umask=1  01    Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_cycles_ne1.akc_ag1 uncore interconnect Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 event=0x97,umask=2  01    Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_inserts0.ad_ag0 uncore interconnect CMS Vert Egress Allocations : AD - Agent 0 event=0x92,umask=1  01    CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_inserts0.ad_ag1 uncore interconnect CMS Vert Egress Allocations : AD - Agent 1 event=0x92,umask=0x10  01    CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests unc_m3upi_txr_vert_inserts0.ak_ag0 uncore interconnect CMS Vert Egress Allocations : AK - Agent 0 event=0x92,umask=2  01    CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_inserts0.ak_ag1 uncore interconnect CMS Vert Egress Allocations : AK - Agent 1 event=0x92,umask=0x20  01    CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m3upi_txr_vert_inserts0.bl_ag0 uncore interconnect CMS Vert Egress Allocations : BL - Agent 0 event=0x92,umask=4  01    CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations unc_m3upi_txr_vert_inserts0.bl_ag1 uncore interconnect CMS Vert Egress Allocations : BL - Agent 1 event=0x92,umask=0x40  01    CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache unc_m3upi_txr_vert_inserts0.iv_ag0 uncore interconnect CMS Vert Egress Allocations : IV - Agent 0 event=0x92,umask=8  01    CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores unc_m3upi_txr_vert_inserts1.akc_ag0 uncore interconnect CMS Vert Egress Allocations : AKC - Agent 0 event=0x93,umask=1  01    CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_inserts1.akc_ag1 uncore interconnect CMS Vert Egress Allocations : AKC - Agent 1 event=0x93,umask=2  01    CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_nack0.ad_ag0 uncore interconnect CMS Vertical Egress NACKs : AD - Agent 0 event=0x98,umask=1  01    CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack0.ad_ag1 uncore interconnect CMS Vertical Egress NACKs : AD - Agent 1 event=0x98,umask=0x10  01    CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack0.ak_ag0 uncore interconnect CMS Vertical Egress NACKs : AK - Agent 0 event=0x98,umask=2  01    CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack0.ak_ag1 uncore interconnect CMS Vertical Egress NACKs : AK - Agent 1 event=0x98,umask=0x20  01    CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack0.bl_ag0 uncore interconnect CMS Vertical Egress NACKs : BL - Agent 0 event=0x98,umask=4  01    CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack0.bl_ag1 uncore interconnect CMS Vertical Egress NACKs : BL - Agent 1 event=0x98,umask=0x40  01    CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack0.iv_ag0 uncore interconnect CMS Vertical Egress NACKs : IV event=0x98,umask=8  01    CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack1.akc_ag0 uncore interconnect CMS Vertical Egress NACKs : AKC - Agent 0 event=0x99,umask=1  01    CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_nack1.akc_ag1 uncore interconnect CMS Vertical Egress NACKs : AKC - Agent 1 event=0x99,umask=2  01    CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m3upi_txr_vert_occupancy0.ad_ag0 uncore interconnect CMS Vert Egress Occupancy : AD - Agent 0 event=0x90,umask=1  01    CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_occupancy0.ad_ag1 uncore interconnect CMS Vert Egress Occupancy : AD - Agent 1 event=0x90,umask=0x10  01    CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests unc_m3upi_txr_vert_occupancy0.ak_ag0 uncore interconnect CMS Vert Egress Occupancy : AK - Agent 0 event=0x90,umask=2  01    CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_occupancy0.ak_ag1 uncore interconnect CMS Vert Egress Occupancy : AK - Agent 1 event=0x90,umask=0x20  01    CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m3upi_txr_vert_occupancy0.bl_ag0 uncore interconnect CMS Vert Egress Occupancy : BL - Agent 0 event=0x90,umask=4  01    CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations unc_m3upi_txr_vert_occupancy0.bl_ag1 uncore interconnect CMS Vert Egress Occupancy : BL - Agent 1 event=0x90,umask=0x40  01    CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache unc_m3upi_txr_vert_occupancy0.iv_ag0 uncore interconnect CMS Vert Egress Occupancy : IV - Agent 0 event=0x90,umask=8  01    CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores unc_m3upi_txr_vert_occupancy1.akc_ag0 uncore interconnect CMS Vert Egress Occupancy : AKC - Agent 0 event=0x91,umask=1  01    CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_m3upi_txr_vert_occupancy1.akc_ag1 uncore interconnect CMS Vert Egress Occupancy : AKC - Agent 1 event=0x91,umask=2  01    CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_m3upi_txr_vert_starved0.ad_ag0 uncore interconnect CMS Vertical Egress Injection Starvation : AD - Agent 0 event=0x9a,umask=1  01    CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved0.ad_ag1 uncore interconnect CMS Vertical Egress Injection Starvation : AD - Agent 1 event=0x9a,umask=0x10  01    CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved0.ak_ag0 uncore interconnect CMS Vertical Egress Injection Starvation : AK - Agent 0 event=0x9a,umask=2  01    CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved0.ak_ag1 uncore interconnect CMS Vertical Egress Injection Starvation : AK - Agent 1 event=0x9a,umask=0x20  01    CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved0.bl_ag0 uncore interconnect CMS Vertical Egress Injection Starvation : BL - Agent 0 event=0x9a,umask=4  01    CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved0.bl_ag1 uncore interconnect CMS Vertical Egress Injection Starvation : BL - Agent 1 event=0x9a,umask=0x40  01    CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved0.iv_ag0 uncore interconnect CMS Vertical Egress Injection Starvation : IV event=0x9a,umask=8  01    CMS Vertical Egress Injection Starvation : IV : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved1.akc_ag0 uncore interconnect CMS Vertical Egress Injection Starvation : AKC - Agent 0 event=0x9b,umask=1  01    CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved1.akc_ag1 uncore interconnect CMS Vertical Egress Injection Starvation : AKC - Agent 1 event=0x9b,umask=2  01    CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_txr_vert_starved1.tgc uncore interconnect CMS Vertical Egress Injection Starvation : AKC - Agent 0 event=0x9b,umask=4  01    CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m3upi_vert_ring_ad_in_use.dn_even uncore interconnect Vertical AD Ring In Use : Down and Even event=0xb0,umask=4  01    Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ad_in_use.dn_odd uncore interconnect Vertical AD Ring In Use : Down and Odd event=0xb0,umask=8  01    Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ad_in_use.up_even uncore interconnect Vertical AD Ring In Use : Up and Even event=0xb0,umask=1  01    Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ad_in_use.up_odd uncore interconnect Vertical AD Ring In Use : Up and Odd event=0xb0,umask=2  01    Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_akc_in_use.dn_even uncore interconnect Vertical AKC Ring In Use : Down and Even event=0xb4,umask=4  01    Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_akc_in_use.dn_odd uncore interconnect Vertical AKC Ring In Use : Down and Odd event=0xb4,umask=8  01    Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_akc_in_use.up_even uncore interconnect Vertical AKC Ring In Use : Up and Even event=0xb4,umask=1  01    Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_akc_in_use.up_odd uncore interconnect Vertical AKC Ring In Use : Up and Odd event=0xb4,umask=2  01    Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ak_in_use.dn_even uncore interconnect Vertical AK Ring In Use : Down and Even event=0xb1,umask=4  01    Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ak_in_use.dn_odd uncore interconnect Vertical AK Ring In Use : Down and Odd event=0xb1,umask=8  01    Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ak_in_use.up_even uncore interconnect Vertical AK Ring In Use : Up and Even event=0xb1,umask=1  01    Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_ak_in_use.up_odd uncore interconnect Vertical AK Ring In Use : Up and Odd event=0xb1,umask=2  01    Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_bl_in_use.dn_even uncore interconnect Vertical BL Ring in Use : Down and Even event=0xb2,umask=4  01    Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_bl_in_use.dn_odd uncore interconnect Vertical BL Ring in Use : Down and Odd event=0xb2,umask=8  01    Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_bl_in_use.up_even uncore interconnect Vertical BL Ring in Use : Up and Even event=0xb2,umask=1  01    Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_bl_in_use.up_odd uncore interconnect Vertical BL Ring in Use : Up and Odd event=0xb2,umask=2  01    Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_iv_in_use.dn uncore interconnect Vertical IV Ring in Use : Down event=0xb3,umask=4  01    Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m3upi_vert_ring_iv_in_use.up uncore interconnect Vertical IV Ring in Use : Up event=0xb3,umask=1  01    Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m3upi_vert_ring_tgc_in_use.dn_even uncore interconnect Vertical TGC Ring In Use : Down and Even event=0xb5,umask=4  01    Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_tgc_in_use.dn_odd uncore interconnect Vertical TGC Ring In Use : Down and Odd event=0xb5,umask=8  01    Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_tgc_in_use.up_even uncore interconnect Vertical TGC Ring In Use : Up and Even event=0xb5,umask=1  01    Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_vert_ring_tgc_in_use.up_odd uncore interconnect Vertical TGC Ring In Use : Up and Odd event=0xb5,umask=2  01    Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m3upi_xpt_pftch.lost_qfull uncore interconnect UNC_M3UPI_XPT_PFTCH.LOST_QFULL event=0x61,umask=0x20  01    : xpt prefetch message was dropped because it was overwritten by new message while prefetch queue was full unc_upi_clockticks uncore interconnect Number of kfclks event=1  01    Number of kfclks : Counts the number of clocks in the UPI LL.  This clock runs at 1/8th the GT/s speed of the UPI link.  For example, a 8GT/s link will have qfclk or 1GHz.  Current products do not support dynamic link speeds, so this frequency is fixed unc_upi_rxl_basic_hdr_match.req uncore interconnect Matches on Receive path of a UPI Port : Request event=5,umask=8  01    Matches on Receive path of a UPI Port : Request : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.req_opc uncore interconnect Matches on Receive path of a UPI Port : Request, Match Opcode event=5,umask=0x108  01    Matches on Receive path of a UPI Port : Request, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.rspcnflt uncore interconnect Matches on Receive path of a UPI Port : Response - Conflict event=5,umask=0x1aa  01    Matches on Receive path of a UPI Port : Response - Conflict : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.rspi uncore interconnect Matches on Receive path of a UPI Port : Response - Invalid event=5,umask=0x12a  01    Matches on Receive path of a UPI Port : Response - Invalid : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.rsp_data uncore interconnect Matches on Receive path of a UPI Port : Response - Data event=5,umask=0xc  01    Matches on Receive path of a UPI Port : Response - Data : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.rsp_data_opc uncore interconnect Matches on Receive path of a UPI Port : Response - Data, Match Opcode event=5,umask=0x10c  01    Matches on Receive path of a UPI Port : Response - Data, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.rsp_nodata uncore interconnect Matches on Receive path of a UPI Port : Response - No Data event=5,umask=0xa  01    Matches on Receive path of a UPI Port : Response - No Data : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.rsp_nodata_opc uncore interconnect Matches on Receive path of a UPI Port : Response - No Data, Match Opcode event=5,umask=0x10a  01    Matches on Receive path of a UPI Port : Response - No Data, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.snp uncore interconnect Matches on Receive path of a UPI Port : Snoop event=5,umask=9  01    Matches on Receive path of a UPI Port : Snoop : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.snp_opc uncore interconnect Matches on Receive path of a UPI Port : Snoop, Match Opcode event=5,umask=0x109  01    Matches on Receive path of a UPI Port : Snoop, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.wb uncore interconnect Matches on Receive path of a UPI Port : Writeback event=5,umask=0xd  01    Matches on Receive path of a UPI Port : Writeback : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_basic_hdr_match.wb_opc uncore interconnect Matches on Receive path of a UPI Port : Writeback, Match Opcode event=5,umask=0x10d  01    Matches on Receive path of a UPI Port : Writeback, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_rxl_crc_llr_req_transmit uncore interconnect LLR Requests Sent event=8  01    LLR Requests Sent : Number of LLR Requests were transmitted.  This should generally be <= the number of CRC errors detected.  If multiple errors are detected before the Rx side receives a LLC_REQ_ACK from the Tx side, there is no need to send more LLR_REQ_NACKs unc_upi_rxl_credits_consumed_vna uncore interconnect VNA Credit Consumed event=0x38  01    VNA Credit Consumed : Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed unc_upi_rxl_flits.all_null uncore interconnect Valid Flits Received : Null FLITs received from any slot event=3,umask=0x27  01    Valid Flits Received : Null FLITs received from any slot : Shows legal flit time (hides impact of L0p and L0c) unc_upi_rxl_flits.idle uncore interconnect Valid Flits Received : Null FLITs received from any slot event=3,umask=0x47  01    Valid Flits Received : Null FLITs received from any slot : Shows legal flit time (hides impact of L0p and L0c) unc_upi_txl_basic_hdr_match.req uncore interconnect Matches on Transmit path of a UPI Port : Request event=4,umask=8  01    Matches on Transmit path of a UPI Port : Request : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.req_opc uncore interconnect Matches on Transmit path of a UPI Port : Request, Match Opcode event=4,umask=0x108  01    Matches on Transmit path of a UPI Port : Request, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.rspcnflt uncore interconnect Matches on Transmit path of a UPI Port : Response - Conflict event=4,umask=0x1aa  01    Matches on Transmit path of a UPI Port : Response - Conflict : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.rspi uncore interconnect Matches on Transmit path of a UPI Port : Response - Invalid event=4,umask=0x12a  01    Matches on Transmit path of a UPI Port : Response - Invalid : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.rsp_data uncore interconnect Matches on Transmit path of a UPI Port : Response - Data event=4,umask=0xc  01    Matches on Transmit path of a UPI Port : Response - Data : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.rsp_data_opc uncore interconnect Matches on Transmit path of a UPI Port : Response - Data, Match Opcode event=4,umask=0x10c  01    Matches on Transmit path of a UPI Port : Response - Data, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.rsp_nodata uncore interconnect Matches on Transmit path of a UPI Port : Response - No Data event=4,umask=0xa  01    Matches on Transmit path of a UPI Port : Response - No Data : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.rsp_nodata_opc uncore interconnect Matches on Transmit path of a UPI Port : Response - No Data, Match Opcode event=4,umask=0x10a  01    Matches on Transmit path of a UPI Port : Response - No Data, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.snp uncore interconnect Matches on Transmit path of a UPI Port : Snoop event=4,umask=9  01    Matches on Transmit path of a UPI Port : Snoop : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.snp_opc uncore interconnect Matches on Transmit path of a UPI Port : Snoop, Match Opcode event=4,umask=0x109  01    Matches on Transmit path of a UPI Port : Snoop, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.wb uncore interconnect Matches on Transmit path of a UPI Port : Writeback event=4,umask=0xd  01    Matches on Transmit path of a UPI Port : Writeback : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_basic_hdr_match.wb_opc uncore interconnect Matches on Transmit path of a UPI Port : Writeback, Match Opcode event=4,umask=0x10d  01    Matches on Transmit path of a UPI Port : Writeback, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled unc_upi_txl_flits.all_data uncore interconnect Valid Flits Sent : All Data event=2,umask=0xf  01    Valid Flits Sent : All Data : Shows legal flit time (hides impact of L0p and L0c) unc_upi_txl_flits.all_null uncore interconnect Valid Flits Sent : Null FLITs transmitted to any slot event=2,umask=0x27  01    Valid Flits Sent : Null FLITs transmitted to any slot : Shows legal flit time (hides impact of L0p and L0c) unc_u_lock_cycles uncore interconnect IDI Lock/SplitLock Cycles event=0x44  01    IDI Lock/SplitLock Cycles : Number of times an IDI Lock/SplitLock sequence was started unc_iio_clockticks uncore io Clockticks of the integrated IO (IIO) traffic controller event=1  01    Clockticks of the integrated IO (IIO) traffic controller : Increments counter once every Traffic Controller clock, the LSCLK (500MHz) unc_iio_clockticks_freerun uncore io Free running counter that increments for IIO clocktick event=0xff,umask=0x10  01    Free running counter that increments for integrated IO (IIO) traffic controller clockticks unc_iio_comp_buf_inserts.cmpd.all uncore io PCIe Completion Buffer Inserts : All Ports event=0xc2,ch_mask=0xff,fc_mask=4,umask=3  01     unc_iio_comp_buf_inserts.cmpd.all_parts uncore io PCIe Completion Buffer Inserts of completions with data: Part 0-7 event=0xc2,ch_mask=0xff,fc_mask=4,umask=3  01    PCIe Completion Buffer Inserts of completions with data : Part 0-7 unc_iio_comp_buf_inserts.cmpd.part0 uncore io PCIe Completion Buffer Inserts of completions with data: Part 0 event=0xc2,ch_mask=1,fc_mask=4,umask=3  01    PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_comp_buf_inserts.cmpd.part1 uncore io PCIe Completion Buffer Inserts of completions with data: Part 1 event=0xc2,ch_mask=2,fc_mask=4,umask=3  01    PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1 unc_iio_comp_buf_inserts.cmpd.part2 uncore io PCIe Completion Buffer Inserts of completions with data: Part 2 event=0xc2,ch_mask=4,fc_mask=4,umask=3  01    PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2 unc_iio_comp_buf_inserts.cmpd.part3 uncore io PCIe Completion Buffer Inserts of completions with data: Part 3 event=0xc2,ch_mask=8,fc_mask=4,umask=3  01    PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3 unc_iio_comp_buf_inserts.cmpd.part4 uncore io PCIe Completion Buffer Inserts of completions with data: Part 4 event=0xc2,ch_mask=0x10,fc_mask=4,umask=3  01    PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4 unc_iio_comp_buf_inserts.cmpd.part5 uncore io PCIe Completion Buffer Inserts of completions with data: Part 5 event=0xc2,ch_mask=0x20,fc_mask=4,umask=3  01    PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5 unc_iio_comp_buf_inserts.cmpd.part6 uncore io PCIe Completion Buffer Inserts of completions with data: Part 6 event=0xc2,ch_mask=0x40,fc_mask=4,umask=3  01    PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6 unc_iio_comp_buf_inserts.cmpd.part7 uncore io PCIe Completion Buffer Inserts of completions with data: Part 7 event=0xc2,ch_mask=0x80,fc_mask=4,umask=3  01    PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7 unc_iio_comp_buf_occupancy.cmpd.all uncore io PCIe Completion Buffer Occupancy of completions with data : Part 0-7 event=0xd5,fc_mask=4,umask=0xff  01    PCIe Completion Buffer Occupancy : Part 0-7 unc_iio_comp_buf_occupancy.cmpd.all_parts uncore io PCIe Completion Buffer Occupancy of completions with data : Part 0-7 event=0xd5,fc_mask=4,umask=0xff  01    PCIe Completion Buffer Occupancy : Part 0-7 unc_iio_comp_buf_occupancy.cmpd.part0 uncore io PCIe Completion Buffer Occupancy of completions with data : Part 0 event=0xd5,fc_mask=4,umask=1  01    PCIe Completion Buffer Occupancy : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_comp_buf_occupancy.cmpd.part1 uncore io PCIe Completion Buffer Occupancy of completions with data : Part 1 event=0xd5,fc_mask=4,umask=2  01    PCIe Completion Buffer Occupancy : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1 unc_iio_comp_buf_occupancy.cmpd.part2 uncore io PCIe Completion Buffer Occupancy of completions with data : Part 2 event=0xd5,fc_mask=4,umask=4  01    PCIe Completion Buffer Occupancy : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2 unc_iio_comp_buf_occupancy.cmpd.part3 uncore io PCIe Completion Buffer Occupancy of completions with data : Part 3 event=0xd5,fc_mask=4,umask=8  01    PCIe Completion Buffer Occupancy : Part 3 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3 unc_iio_comp_buf_occupancy.cmpd.part4 uncore io PCIe Completion Buffer Occupancy of completions with data : Part 4 event=0xd5,fc_mask=4,umask=0x10  01    PCIe Completion Buffer Occupancy : Part 4 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4 unc_iio_comp_buf_occupancy.cmpd.part5 uncore io PCIe Completion Buffer Occupancy of completions with data : Part 5 event=0xd5,fc_mask=4,umask=0x20  01    PCIe Completion Buffer Occupancy : Part 5 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5 unc_iio_comp_buf_occupancy.cmpd.part6 uncore io PCIe Completion Buffer Occupancy of completions with data : Part 6 event=0xd5,fc_mask=4,umask=0x40  01    PCIe Completion Buffer Occupancy : Part 6 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6 unc_iio_comp_buf_occupancy.cmpd.part7 uncore io PCIe Completion Buffer Occupancy of completions with data : Part 7 event=0xd5,fc_mask=4,umask=0x80  01    PCIe Completion Buffer Occupancy : Part 7 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7 unc_iio_data_req_by_cpu.cfg_read.iommu0 uncore io Data requested by the CPU : Core reading from Card's PCICFG space event=0xc0,ch_mask=0x100,fc_mask=7,umask=0x40  01    Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_by_cpu.cfg_read.iommu1 uncore io Data requested by the CPU : Core reading from Card's PCICFG space event=0xc0,ch_mask=0x200,fc_mask=7,umask=0x40  01    Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_by_cpu.cfg_read.part0 uncore io Data requested by the CPU : Core reading from Card's PCICFG space event=0xc0,ch_mask=1,fc_mask=7,umask=0x40  01    Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.cfg_read.part1 uncore io Data requested by the CPU : Core reading from Card's PCICFG space event=0xc0,ch_mask=2,fc_mask=7,umask=0x40  01    Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.cfg_read.part2 uncore io Data requested by the CPU : Core reading from Card's PCICFG space event=0xc0,ch_mask=4,fc_mask=7,umask=0x40  01    Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.cfg_read.part3 uncore io Data requested by the CPU : Core reading from Card's PCICFG space event=0xc0,ch_mask=8,fc_mask=7,umask=0x40  01    Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.cfg_read.part4 uncore io Data requested by the CPU : Core reading from Card's PCICFG space event=0xc0,ch_mask=0x10,fc_mask=7,umask=0x40  01    Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_by_cpu.cfg_read.part5 uncore io Data requested by the CPU : Core reading from Card's PCICFG space event=0xc0,ch_mask=0x20,fc_mask=7,umask=0x40  01    Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_by_cpu.cfg_read.part6 uncore io Data requested by the CPU : Core reading from Card's PCICFG space event=0xc0,ch_mask=0x40,fc_mask=7,umask=0x40  01    Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_by_cpu.cfg_read.part7 uncore io Data requested by the CPU : Core reading from Card's PCICFG space event=0xc0,ch_mask=0x80,fc_mask=7,umask=0x40  01    Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_by_cpu.cfg_write.iommu0 uncore io Data requested by the CPU : Core writing to Card's PCICFG space event=0xc0,ch_mask=0x100,fc_mask=7,umask=0x10  01    Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_by_cpu.cfg_write.iommu1 uncore io Data requested by the CPU : Core writing to Card's PCICFG space event=0xc0,ch_mask=0x200,fc_mask=7,umask=0x10  01    Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_by_cpu.cfg_write.part0 uncore io Data requested by the CPU : Core writing to Card's PCICFG space event=0xc0,ch_mask=1,fc_mask=7,umask=0x10  01    Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.cfg_write.part1 uncore io Data requested by the CPU : Core writing to Card's PCICFG space event=0xc0,ch_mask=2,fc_mask=7,umask=0x10  01    Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.cfg_write.part2 uncore io Data requested by the CPU : Core writing to Card's PCICFG space event=0xc0,ch_mask=4,fc_mask=7,umask=0x10  01    Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.cfg_write.part3 uncore io Data requested by the CPU : Core writing to Card's PCICFG space event=0xc0,ch_mask=8,fc_mask=7,umask=0x10  01    Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.cfg_write.part4 uncore io Data requested by the CPU : Core writing to Card's PCICFG space event=0xc0,ch_mask=0x10,fc_mask=7,umask=0x10  01    Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_by_cpu.cfg_write.part5 uncore io Data requested by the CPU : Core writing to Card's PCICFG space event=0xc0,ch_mask=0x20,fc_mask=7,umask=0x10  01    Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_by_cpu.cfg_write.part6 uncore io Data requested by the CPU : Core writing to Card's PCICFG space event=0xc0,ch_mask=0x40,fc_mask=7,umask=0x10  01    Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_by_cpu.cfg_write.part7 uncore io Data requested by the CPU : Core writing to Card's PCICFG space event=0xc0,ch_mask=0x80,fc_mask=7,umask=0x10  01    Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_by_cpu.io_read.iommu0 uncore io Data requested by the CPU : Core reading from Card's IO space event=0xc0,ch_mask=0x100,fc_mask=7,umask=0x80  01    Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_by_cpu.io_read.iommu1 uncore io Data requested by the CPU : Core reading from Card's IO space event=0xc0,ch_mask=0x200,fc_mask=7,umask=0x80  01    Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_by_cpu.io_read.part0 uncore io Data requested by the CPU : Core reading from Card's IO space event=0xc0,ch_mask=1,fc_mask=7,umask=0x80  01    Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.io_read.part1 uncore io Data requested by the CPU : Core reading from Card's IO space event=0xc0,ch_mask=2,fc_mask=7,umask=0x80  01    Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.io_read.part2 uncore io Data requested by the CPU : Core reading from Card's IO space event=0xc0,ch_mask=4,fc_mask=7,umask=0x80  01    Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.io_read.part3 uncore io Data requested by the CPU : Core reading from Card's IO space event=0xc0,ch_mask=8,fc_mask=7,umask=0x80  01    Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.io_read.part4 uncore io Data requested by the CPU : Core reading from Card's IO space event=0xc0,ch_mask=0x10,fc_mask=7,umask=0x80  01    Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_by_cpu.io_read.part5 uncore io Data requested by the CPU : Core reading from Card's IO space event=0xc0,ch_mask=0x20,fc_mask=7,umask=0x80  01    Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_by_cpu.io_read.part6 uncore io Data requested by the CPU : Core reading from Card's IO space event=0xc0,ch_mask=0x40,fc_mask=7,umask=0x80  01    Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_by_cpu.io_read.part7 uncore io Data requested by the CPU : Core reading from Card's IO space event=0xc0,ch_mask=0x80,fc_mask=7,umask=0x80  01    Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_by_cpu.io_write.iommu0 uncore io Data requested by the CPU : Core writing to Card's IO space event=0xc0,ch_mask=0x100,fc_mask=7,umask=0x20  01    Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_by_cpu.io_write.iommu1 uncore io Data requested by the CPU : Core writing to Card's IO space event=0xc0,ch_mask=0x200,fc_mask=7,umask=0x20  01    Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_by_cpu.io_write.part0 uncore io Data requested by the CPU : Core writing to Card's IO space event=0xc0,ch_mask=1,fc_mask=7,umask=0x20  01    Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.io_write.part1 uncore io Data requested by the CPU : Core writing to Card's IO space event=0xc0,ch_mask=2,fc_mask=7,umask=0x20  01    Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.io_write.part2 uncore io Data requested by the CPU : Core writing to Card's IO space event=0xc0,ch_mask=4,fc_mask=7,umask=0x20  01    Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.io_write.part3 uncore io Data requested by the CPU : Core writing to Card's IO space event=0xc0,ch_mask=8,fc_mask=7,umask=0x20  01    Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.io_write.part4 uncore io Data requested by the CPU : Core writing to Card's IO space event=0xc0,ch_mask=0x10,fc_mask=7,umask=0x20  01    Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_by_cpu.io_write.part5 uncore io Data requested by the CPU : Core writing to Card's IO space event=0xc0,ch_mask=0x20,fc_mask=7,umask=0x20  01    Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_by_cpu.io_write.part6 uncore io Data requested by the CPU : Core writing to Card's IO space event=0xc0,ch_mask=0x40,fc_mask=7,umask=0x20  01    Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_by_cpu.io_write.part7 uncore io Data requested by the CPU : Core writing to Card's IO space event=0xc0,ch_mask=0x80,fc_mask=7,umask=0x20  01    Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_by_cpu.mem_read.iommu0 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=0x100,fc_mask=7,umask=4  01    Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_by_cpu.mem_read.iommu1 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=0x200,fc_mask=7,umask=4  01    Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_by_cpu.mem_read.part0 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=1,fc_mask=7,umask=4  01    Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.mem_read.part1 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=2,fc_mask=7,umask=4  01    Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.mem_read.part2 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=4,fc_mask=7,umask=4  01    Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.mem_read.part3 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=8,fc_mask=7,umask=4  01    Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.mem_read.part4 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=0x10,fc_mask=7,umask=4  01    Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_by_cpu.mem_read.part5 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=0x20,fc_mask=7,umask=4  01    Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_by_cpu.mem_read.part6 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=0x40,fc_mask=7,umask=4  01    Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_by_cpu.mem_read.part7 uncore io Data requested by the CPU : Core reporting completion of Card read from Core DRAM event=0xc0,ch_mask=0x80,fc_mask=7,umask=4  01    Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_by_cpu.mem_write.iommu0 uncore io Data requested by the CPU : Core writing to Card's MMIO space event=0xc0,ch_mask=0x100,fc_mask=7,umask=1  01    Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_by_cpu.mem_write.iommu1 uncore io Data requested by the CPU : Core writing to Card's MMIO space event=0xc0,ch_mask=0x200,fc_mask=7,umask=1  01    Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_by_cpu.mem_write.part0 uncore io Data requested by the CPU : Core writing to Card's MMIO space event=0xc0,ch_mask=1,fc_mask=7,umask=1  01    Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.mem_write.part1 uncore io Data requested by the CPU : Core writing to Card's MMIO space event=0xc0,ch_mask=2,fc_mask=7,umask=1  01    Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.mem_write.part2 uncore io Data requested by the CPU : Core writing to Card's MMIO space event=0xc0,ch_mask=4,fc_mask=7,umask=1  01    Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.mem_write.part3 uncore io Data requested by the CPU : Core writing to Card's MMIO space event=0xc0,ch_mask=8,fc_mask=7,umask=1  01    Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.mem_write.part4 uncore io Data requested by the CPU : Core writing to Card's MMIO space event=0xc0,ch_mask=0x10,fc_mask=7,umask=1  01    Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_by_cpu.mem_write.part5 uncore io Data requested by the CPU : Core writing to Card's MMIO space event=0xc0,ch_mask=0x20,fc_mask=7,umask=1  01    Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_by_cpu.mem_write.part6 uncore io Data requested by the CPU : Core writing to Card's MMIO space event=0xc0,ch_mask=0x40,fc_mask=7,umask=1  01    Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_by_cpu.mem_write.part7 uncore io Data requested by the CPU : Core writing to Card's MMIO space event=0xc0,ch_mask=0x80,fc_mask=7,umask=1  01    Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_by_cpu.peer_read.iommu0 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x100,fc_mask=7,umask=8  01    Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_by_cpu.peer_read.iommu1 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x200,fc_mask=7,umask=8  01    Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_by_cpu.peer_read.part0 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=1,fc_mask=7,umask=8  01    Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.peer_read.part1 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=2,fc_mask=7,umask=8  01    Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.peer_read.part2 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=4,fc_mask=7,umask=8  01    Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.peer_read.part3 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=8,fc_mask=7,umask=8  01    Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.peer_read.part4 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x10,fc_mask=7,umask=8  01    Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_by_cpu.peer_read.part5 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x20,fc_mask=7,umask=8  01    Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_by_cpu.peer_read.part6 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x40,fc_mask=7,umask=8  01    Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_by_cpu.peer_read.part7 uncore io Data requested by the CPU : Another card (different IIO stack) reading from this card event=0xc0,ch_mask=0x80,fc_mask=7,umask=8  01    Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_by_cpu.peer_write.iommu0 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x100,fc_mask=7,umask=2  01    Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_by_cpu.peer_write.iommu1 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x200,fc_mask=7,umask=2  01    Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_by_cpu.peer_write.part0 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=1,fc_mask=7,umask=2  01    Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_by_cpu.peer_write.part1 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=2,fc_mask=7,umask=2  01    Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_by_cpu.peer_write.part2 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=4,fc_mask=7,umask=2  01    Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_by_cpu.peer_write.part3 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=8,fc_mask=7,umask=2  01    Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_by_cpu.peer_write.part4 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x10,fc_mask=7,umask=2  01    Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_by_cpu.peer_write.part5 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x20,fc_mask=7,umask=2  01    Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_by_cpu.peer_write.part6 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x40,fc_mask=7,umask=2  01    Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_by_cpu.peer_write.part7 uncore io Data requested by the CPU : Another card (different IIO stack) writing to this card event=0xc0,ch_mask=0x80,fc_mask=7,umask=2  01    Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_of_cpu.atomic.iommu0 uncore io Data requested of the CPU : Atomic requests targeting DRAM event=0x83,ch_mask=0x100,fc_mask=7,umask=0x10  01    Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_of_cpu.atomic.iommu1 uncore io Data requested of the CPU : Atomic requests targeting DRAM event=0x83,ch_mask=0x200,fc_mask=7,umask=0x10  01    Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_of_cpu.atomic.part0 uncore io Data requested of the CPU : Atomic requests targeting DRAM event=0x83,ch_mask=1,fc_mask=7,umask=0x10  01    Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.atomic.part1 uncore io Data requested of the CPU : Atomic requests targeting DRAM event=0x83,ch_mask=2,fc_mask=7,umask=0x10  01    Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.atomic.part2 uncore io Data requested of the CPU : Atomic requests targeting DRAM event=0x83,ch_mask=4,fc_mask=7,umask=0x10  01    Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.atomic.part3 uncore io Data requested of the CPU : Atomic requests targeting DRAM event=0x83,ch_mask=8,fc_mask=7,umask=0x10  01    Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.atomic.part4 uncore io Data requested of the CPU : Atomic requests targeting DRAM event=0x83,ch_mask=0x10,fc_mask=7,umask=0x10  01    Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_of_cpu.atomic.part5 uncore io Data requested of the CPU : Atomic requests targeting DRAM event=0x83,ch_mask=0x20,fc_mask=7,umask=0x10  01    Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_of_cpu.atomic.part6 uncore io Data requested of the CPU : Atomic requests targeting DRAM event=0x83,ch_mask=0x40,fc_mask=7,umask=0x10  01    Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_of_cpu.atomic.part7 uncore io Data requested of the CPU : Atomic requests targeting DRAM event=0x83,ch_mask=0x80,fc_mask=7,umask=0x10  01    Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_of_cpu.cmpd.iommu0 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0x100,fc_mask=7,umask=0x80  01    Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_of_cpu.cmpd.iommu1 uncore io Data requested of the CPU : CmpD - device sending completion to CPU request event=0x83,ch_mask=0x200,fc_mask=7,umask=0x80  01    Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_of_cpu.mem_read.iommu0 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=0x100,fc_mask=7,umask=4  01    Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_of_cpu.mem_read.iommu1 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=0x200,fc_mask=7,umask=4  01    Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_of_cpu.mem_read.part0 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=1,fc_mask=7,umask=4  01    Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.mem_read.part1 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=2,fc_mask=7,umask=4  01    Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_read.part2 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=4,fc_mask=7,umask=4  01    Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.mem_read.part3 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=8,fc_mask=7,umask=4  01    Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.mem_read.part4 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=0x10,fc_mask=7,umask=4  01    Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_of_cpu.mem_read.part5 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=0x20,fc_mask=7,umask=4  01    Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_of_cpu.mem_read.part6 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=0x40,fc_mask=7,umask=4  01    Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_of_cpu.mem_read.part7 uncore io Four byte data request of the CPU : Card reading from DRAM event=0x83,ch_mask=0x80,fc_mask=7,umask=4  01    Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_of_cpu.mem_write.iommu0 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=0x100,fc_mask=7,umask=1  01    Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_of_cpu.mem_write.iommu1 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=0x200,fc_mask=7,umask=1  01    Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_of_cpu.mem_write.part0 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=1,fc_mask=7,umask=1  01    Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.mem_write.part1 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=2,fc_mask=7,umask=1  01    Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_write.part2 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=4,fc_mask=7,umask=1  01    Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.mem_write.part3 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=8,fc_mask=7,umask=1  01    Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.mem_write.part4 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=0x10,fc_mask=7,umask=1  01    Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_of_cpu.mem_write.part5 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=0x20,fc_mask=7,umask=1  01    Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_of_cpu.mem_write.part6 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=0x40,fc_mask=7,umask=1  01    Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_of_cpu.mem_write.part7 uncore io Four byte data request of the CPU : Card writing to DRAM event=0x83,ch_mask=0x80,fc_mask=7,umask=1  01    Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_of_cpu.msg.iommu0 uncore io Data requested of the CPU : Messages event=0x83,ch_mask=0x100,fc_mask=7,umask=0x40  01    Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_of_cpu.msg.iommu1 uncore io Data requested of the CPU : Messages event=0x83,ch_mask=0x200,fc_mask=7,umask=0x40  01    Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_of_cpu.msg.part0 uncore io Data requested of the CPU : Messages event=0x83,ch_mask=1,fc_mask=7,umask=0x40  01    Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.msg.part1 uncore io Data requested of the CPU : Messages event=0x83,ch_mask=2,fc_mask=7,umask=0x40  01    Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.msg.part2 uncore io Data requested of the CPU : Messages event=0x83,ch_mask=4,fc_mask=7,umask=0x40  01    Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.msg.part3 uncore io Data requested of the CPU : Messages event=0x83,ch_mask=8,fc_mask=7,umask=0x40  01    Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.msg.part4 uncore io Data requested of the CPU : Messages event=0x83,ch_mask=0x10,fc_mask=7,umask=0x40  01    Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_of_cpu.msg.part5 uncore io Data requested of the CPU : Messages event=0x83,ch_mask=0x20,fc_mask=7,umask=0x40  01    Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_of_cpu.msg.part6 uncore io Data requested of the CPU : Messages event=0x83,ch_mask=0x40,fc_mask=7,umask=0x40  01    Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_of_cpu.msg.part7 uncore io Data requested of the CPU : Messages event=0x83,ch_mask=0x80,fc_mask=7,umask=0x40  01    Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_of_cpu.peer_read.iommu0 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=0x100,fc_mask=7,umask=8  01    Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_of_cpu.peer_read.iommu1 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=0x200,fc_mask=7,umask=8  01    Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_of_cpu.peer_read.part0 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=1,fc_mask=7,umask=8  01    Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.peer_read.part1 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=2,fc_mask=7,umask=8  01    Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.peer_read.part2 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=4,fc_mask=7,umask=8  01    Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.peer_read.part3 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=8,fc_mask=7,umask=8  01    Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.peer_read.part4 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=0x10,fc_mask=7,umask=8  01    Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_of_cpu.peer_read.part5 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=0x20,fc_mask=7,umask=8  01    Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_of_cpu.peer_read.part6 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=0x40,fc_mask=7,umask=8  01    Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_of_cpu.peer_read.part7 uncore io Data requested of the CPU : Card reading from another Card (same or different stack) event=0x83,ch_mask=0x80,fc_mask=7,umask=8  01    Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_data_req_of_cpu.peer_write.iommu0 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x100,fc_mask=7,umask=2  01    Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_data_req_of_cpu.peer_write.iommu1 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x200,fc_mask=7,umask=2  01    Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_data_req_of_cpu.peer_write.part0 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=1,fc_mask=7,umask=2  01    Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.peer_write.part1 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=2,fc_mask=7,umask=2  01    Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.peer_write.part2 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=4,fc_mask=7,umask=2  01    Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.peer_write.part3 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=8,fc_mask=7,umask=2  01    Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.peer_write.part4 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x10,fc_mask=7,umask=2  01    Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_data_req_of_cpu.peer_write.part5 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x20,fc_mask=7,umask=2  01    Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_data_req_of_cpu.peer_write.part6 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x40,fc_mask=7,umask=2  01    Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_data_req_of_cpu.peer_write.part7 uncore io Data requested of the CPU : Card writing to another Card (same or different stack) event=0x83,ch_mask=0x80,fc_mask=7,umask=2  01    Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_iommu0.all_lookups uncore io : IOTLB lookups all event=0x40,umask=2  01    : IOTLB lookups all : Some transactions have to look up IOTLB multiple times.  Counts every time a request looks up IOTLB unc_iio_iommu0.misses uncore io : IOTLB Fills (same as IOTLB miss) event=0x40,umask=0x20  01    : IOTLB Fills (same as IOTLB miss) : When a transaction misses IOTLB, it does a page walk to look up memory and bring in the relevant page translation. Counts when this page translation is written to IOTLB unc_iio_iommu1.cyc_pwt_full uncore io : Cycles PWT full event=0x41,umask=0x80  01    : Cycles PWT full : Counts cycles the IOMMU has reached its maximum limit for outstanding page walks unc_iio_iommu1.num_mem_accesses uncore io : IOMMU memory access event=0x41,umask=0x40  01    : IOMMU memory access : IOMMU sends out memory fetches when it misses the cache look up which is indicated by this signal.  M2IOSF only uses low priority channel unc_iio_iommu1.pwc_1g_hits uncore io : PWC Hit to a 1G page event=0x41,umask=8  01    : PWC Hit to a 1G page : Counts each time a transaction's first look up hits the SLPWC at the 1G level unc_iio_iommu1.pwc_2m_hits uncore io : PWC Hit to a 2M page event=0x41,umask=4  01    : PWC Hit to a 2M page : Counts each time a transaction's first look up hits the SLPWC at the 2M level unc_iio_iommu1.pwc_4k_hits uncore io : PWC Hit to a 4K page event=0x41,umask=2  01    : PWC Hit to a 4K page : Counts each time a transaction's first look up hits the SLPWC at the 4K level unc_iio_iommu1.pwc_512g_hits uncore io : PWT Hit to a 256T page event=0x41,umask=0x10  01    : PWT Hit to a 256T page : Counts each time a transaction's first look up hits the SLPWC at the 512G level unc_iio_iommu3.int_cache_hits uncore io : Interrupt Entry cache hit event=0x43,umask=0x80  01    : Interrupt Entry cache hit : Counts each time a transaction's first look up hits the IEC unc_iio_iommu3.int_cache_lookups uncore io : Interrupt Entry cache lookup event=0x43,umask=0x40  01    : Interrupt Entry cache lookup : Counts the number of transaction looks up that interrupt remapping cache unc_iio_iommu3.num_ctxt_cache_inval_device uncore io : Device-selective Context cache invalidation cycles event=0x43,umask=0x20  01    : Device-selective Context cache invalidation cycles : Counts number of Device selective context cache invalidation events unc_iio_iommu3.num_ctxt_cache_inval_domain uncore io : Domain-selective Context cache invalidation cycles event=0x43,umask=0x10  01    : Domain-selective Context cache invalidation cycles : Counts number of Domain selective context cache invalidation events unc_iio_iommu3.num_ctxt_cache_inval_gbl uncore io : Context cache global invalidation cycles event=0x43,umask=8  01    : Context cache global invalidation cycles : Counts number of Context Cache global invalidation events unc_iio_iommu3.num_inval_domain uncore io : Domain-selective IOTLB invalidation cycles event=0x43,umask=2  01    : Domain-selective IOTLB invalidation cycles : Counts number of Domain selective invalidation events unc_iio_iommu3.num_inval_gbl uncore io : Global IOTLB invalidation cycles event=0x43,umask=1  01    : Global IOTLB invalidation cycles : Indicates that IOMMU is doing global invalidation unc_iio_iommu3.num_inval_page uncore io : Page-selective IOTLB invalidation cycles event=0x43,umask=4  01    : Page-selective IOTLB invalidation cycles : Counts number of Page-selective within Domain Invalidation events unc_iio_nothing uncore io Counting disabled event=0x80  01     unc_iio_num_oustanding_req_from_cpu.to_io uncore io Occupancy of outbound request queue : To device event=0xc5,ch_mask=0xff,fc_mask=7,umask=8  01    Occupancy of outbound request queue : To device : Counts number of outbound requests/completions IIO is currently processing unc_iio_num_outstanding_req_of_cpu.data uncore io : Passing data to be written event=0x88,ch_mask=0xff,fc_mask=7,umask=0x20  01    : Passing data to be written : Only for posted requests unc_iio_num_outstanding_req_of_cpu.final_rd_wr uncore io : Issuing final read or write of line event=0x88,ch_mask=0xff,fc_mask=7,umask=8  01     unc_iio_num_outstanding_req_of_cpu.iommu_hit uncore io : Processing response from IOMMU event=0x88,ch_mask=0xff,fc_mask=7,umask=2  01     unc_iio_num_outstanding_req_of_cpu.iommu_req uncore io : Issuing to IOMMU event=0x88,ch_mask=0xff,fc_mask=7,umask=1  01     unc_iio_num_outstanding_req_of_cpu.req_own uncore io : Request Ownership event=0x88,ch_mask=0xff,fc_mask=7,umask=4  01    : Request Ownership : Only for posted requests unc_iio_num_outstanding_req_of_cpu.wr uncore io : Writing line event=0x88,ch_mask=0xff,fc_mask=7,umask=0x10  01    : Writing line : Only for posted requests unc_iio_num_req_from_cpu.itc uncore io Number requests sent to PCIe from main die : From ITC event=0xc2,ch_mask=0xff,fc_mask=7,umask=2  01    Number requests sent to PCIe from main die : From ITC : Confined P2P unc_iio_num_req_from_cpu.prealloc uncore io Number requests sent to PCIe from main die : Completion allocations event=0xc2,ch_mask=0xff,fc_mask=7,umask=4  01     unc_iio_num_req_of_cpu.all.drop uncore io Number requests PCIe makes of the main die : Drop request event=0x85,ch_mask=0xff,fc_mask=7,umask=2  01    Number requests PCIe makes of the main die : Drop request : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU. : Packet error detected, must be dropped unc_iio_num_req_of_cpu.commit.all uncore io Number requests PCIe makes of the main die : All event=0x85,ch_mask=0xff,fc_mask=7,umask=1  01    Number requests PCIe makes of the main die : All : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU unc_iio_num_tgt_matched_req_of_cpu uncore io ITC address map 1 event=0x8f  01     unc_iio_pwt_occupancy uncore io PWT occupancy event=0x42  01    PWT occupancy : Indicates how many page walks are outstanding at any point in time unc_iio_req_from_pcie_cl_cmpl.data uncore io PCIe Request - cacheline complete : Passing data to be written event=0x91,ch_mask=0xff,fc_mask=7,umask=0x20  01    PCIe Request - cacheline complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests unc_iio_req_from_pcie_cl_cmpl.final_rd_wr uncore io PCIe Request - cacheline complete : Issuing final read or write of line event=0x91,ch_mask=0xff,fc_mask=7,umask=8  01    PCIe Request - cacheline complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line unc_iio_req_from_pcie_cl_cmpl.req_own uncore io PCIe Request - cacheline complete : Request Ownership event=0x91,ch_mask=0xff,fc_mask=7,umask=4  01    PCIe Request - cacheline complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests unc_iio_req_from_pcie_cl_cmpl.wr uncore io PCIe Request - cacheline complete : Writing line event=0x91,ch_mask=0xff,fc_mask=7,umask=0x10  01    PCIe Request - cacheline complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests unc_iio_req_from_pcie_cmpl.data uncore io PCIe Request complete : Passing data to be written event=0x92,ch_mask=0xff,fc_mask=7,umask=0x20  01    PCIe Request complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests unc_iio_req_from_pcie_cmpl.final_rd_wr uncore io PCIe Request complete : Issuing final read or write of line event=0x92,ch_mask=0xff,fc_mask=7,umask=8  01    PCIe Request complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a single PCIe request completes all its cacheline granular requests, it advances pointer unc_iio_req_from_pcie_cmpl.iommu_hit uncore io PCIe Request complete : Processing response from IOMMU event=0x92,ch_mask=0xff,fc_mask=7,umask=2  01    PCIe Request complete : Processing response from IOMMU : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a single PCIe request completes all its cacheline granular requests, it advances pointer unc_iio_req_from_pcie_cmpl.iommu_req uncore io PCIe Request complete : Issuing to IOMMU event=0x92,ch_mask=0xff,fc_mask=7,umask=1  01    PCIe Request complete : Issuing to IOMMU : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a single PCIe request completes all its cacheline granular requests, it advances pointer unc_iio_req_from_pcie_cmpl.req_own uncore io PCIe Request complete : Request Ownership event=0x92,ch_mask=0xff,fc_mask=7,umask=4  01    PCIe Request complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests unc_iio_req_from_pcie_cmpl.wr uncore io PCIe Request complete : Writing line event=0x92,ch_mask=0xff,fc_mask=7,umask=0x10  01    PCIe Request complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests unc_iio_symbol_times uncore io Symbol Times on Link event=0x82  01    Symbol Times on Link : Gen1 - increment once every 4nS, Gen2 - increment once every 2nS, Gen3 - increment once every 1nS unc_iio_txn_req_by_cpu.cfg_read.iommu0 uncore io Number Transactions requested by the CPU : Core reading from Card's PCICFG space event=0xc1,ch_mask=0x100,fc_mask=7,umask=0x40  01    Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_by_cpu.cfg_read.iommu1 uncore io Number Transactions requested by the CPU : Core reading from Card's PCICFG space event=0xc1,ch_mask=0x200,fc_mask=7,umask=0x40  01    Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_by_cpu.cfg_read.part0 uncore io Number Transactions requested by the CPU : Core reading from Card's PCICFG space event=0xc1,ch_mask=1,fc_mask=7,umask=0x40  01    Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.cfg_read.part1 uncore io Number Transactions requested by the CPU : Core reading from Card's PCICFG space event=0xc1,ch_mask=2,fc_mask=7,umask=0x40  01    Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.cfg_read.part2 uncore io Number Transactions requested by the CPU : Core reading from Card's PCICFG space event=0xc1,ch_mask=4,fc_mask=7,umask=0x40  01    Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.cfg_read.part3 uncore io Number Transactions requested by the CPU : Core reading from Card's PCICFG space event=0xc1,ch_mask=8,fc_mask=7,umask=0x40  01    Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.cfg_read.part4 uncore io Number Transactions requested by the CPU : Core reading from Card's PCICFG space event=0xc1,ch_mask=0x10,fc_mask=7,umask=0x40  01    Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_by_cpu.cfg_read.part5 uncore io Number Transactions requested by the CPU : Core reading from Card's PCICFG space event=0xc1,ch_mask=0x20,fc_mask=7,umask=0x40  01    Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_by_cpu.cfg_read.part6 uncore io Number Transactions requested by the CPU : Core reading from Card's PCICFG space event=0xc1,ch_mask=0x40,fc_mask=7,umask=0x40  01    Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_by_cpu.cfg_read.part7 uncore io Number Transactions requested by the CPU : Core reading from Card's PCICFG space event=0xc1,ch_mask=0x80,fc_mask=7,umask=0x40  01    Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_by_cpu.cfg_write.iommu0 uncore io Number Transactions requested by the CPU : Core writing to Card's PCICFG space event=0xc1,ch_mask=0x100,fc_mask=7,umask=0x10  01    Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_by_cpu.cfg_write.iommu1 uncore io Number Transactions requested by the CPU : Core writing to Card's PCICFG space event=0xc1,ch_mask=0x200,fc_mask=7,umask=0x10  01    Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_by_cpu.cfg_write.part0 uncore io Number Transactions requested by the CPU : Core writing to Card's PCICFG space event=0xc1,ch_mask=1,fc_mask=7,umask=0x10  01    Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.cfg_write.part1 uncore io Number Transactions requested by the CPU : Core writing to Card's PCICFG space event=0xc1,ch_mask=2,fc_mask=7,umask=0x10  01    Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.cfg_write.part2 uncore io Number Transactions requested by the CPU : Core writing to Card's PCICFG space event=0xc1,ch_mask=4,fc_mask=7,umask=0x10  01    Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.cfg_write.part3 uncore io Number Transactions requested by the CPU : Core writing to Card's PCICFG space event=0xc1,ch_mask=8,fc_mask=7,umask=0x10  01    Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.cfg_write.part4 uncore io Number Transactions requested by the CPU : Core writing to Card's PCICFG space event=0xc1,ch_mask=0x10,fc_mask=7,umask=0x10  01    Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_by_cpu.cfg_write.part5 uncore io Number Transactions requested by the CPU : Core writing to Card's PCICFG space event=0xc1,ch_mask=0x20,fc_mask=7,umask=0x10  01    Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_by_cpu.cfg_write.part6 uncore io Number Transactions requested by the CPU : Core writing to Card's PCICFG space event=0xc1,ch_mask=0x40,fc_mask=7,umask=0x10  01    Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_by_cpu.cfg_write.part7 uncore io Number Transactions requested by the CPU : Core writing to Card's PCICFG space event=0xc1,ch_mask=0x80,fc_mask=7,umask=0x10  01    Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_by_cpu.io_read.iommu0 uncore io Number Transactions requested by the CPU : Core reading from Card's IO space event=0xc1,ch_mask=0x100,fc_mask=7,umask=0x80  01    Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_by_cpu.io_read.iommu1 uncore io Number Transactions requested by the CPU : Core reading from Card's IO space event=0xc1,ch_mask=0x200,fc_mask=7,umask=0x80  01    Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_by_cpu.io_read.part0 uncore io Number Transactions requested by the CPU : Core reading from Card's IO space event=0xc1,ch_mask=1,fc_mask=7,umask=0x80  01    Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.io_read.part1 uncore io Number Transactions requested by the CPU : Core reading from Card's IO space event=0xc1,ch_mask=2,fc_mask=7,umask=0x80  01    Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.io_read.part2 uncore io Number Transactions requested by the CPU : Core reading from Card's IO space event=0xc1,ch_mask=4,fc_mask=7,umask=0x80  01    Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.io_read.part3 uncore io Number Transactions requested by the CPU : Core reading from Card's IO space event=0xc1,ch_mask=8,fc_mask=7,umask=0x80  01    Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.io_read.part4 uncore io Number Transactions requested by the CPU : Core reading from Card's IO space event=0xc1,ch_mask=0x10,fc_mask=7,umask=0x80  01    Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_by_cpu.io_read.part5 uncore io Number Transactions requested by the CPU : Core reading from Card's IO space event=0xc1,ch_mask=0x20,fc_mask=7,umask=0x80  01    Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_by_cpu.io_read.part6 uncore io Number Transactions requested by the CPU : Core reading from Card's IO space event=0xc1,ch_mask=0x40,fc_mask=7,umask=0x80  01    Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_by_cpu.io_read.part7 uncore io Number Transactions requested by the CPU : Core reading from Card's IO space event=0xc1,ch_mask=0x80,fc_mask=7,umask=0x80  01    Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_by_cpu.io_write.iommu0 uncore io Number Transactions requested by the CPU : Core writing to Card's IO space event=0xc1,ch_mask=0x100,fc_mask=7,umask=0x20  01    Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_by_cpu.io_write.iommu1 uncore io Number Transactions requested by the CPU : Core writing to Card's IO space event=0xc1,ch_mask=0x200,fc_mask=7,umask=0x20  01    Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_by_cpu.io_write.part0 uncore io Number Transactions requested by the CPU : Core writing to Card's IO space event=0xc1,ch_mask=1,fc_mask=7,umask=0x20  01    Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.io_write.part1 uncore io Number Transactions requested by the CPU : Core writing to Card's IO space event=0xc1,ch_mask=2,fc_mask=7,umask=0x20  01    Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.io_write.part2 uncore io Number Transactions requested by the CPU : Core writing to Card's IO space event=0xc1,ch_mask=4,fc_mask=7,umask=0x20  01    Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.io_write.part3 uncore io Number Transactions requested by the CPU : Core writing to Card's IO space event=0xc1,ch_mask=8,fc_mask=7,umask=0x20  01    Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.io_write.part4 uncore io Number Transactions requested by the CPU : Core writing to Card's IO space event=0xc1,ch_mask=0x10,fc_mask=7,umask=0x20  01    Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_by_cpu.io_write.part5 uncore io Number Transactions requested by the CPU : Core writing to Card's IO space event=0xc1,ch_mask=0x20,fc_mask=7,umask=0x20  01    Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_by_cpu.io_write.part6 uncore io Number Transactions requested by the CPU : Core writing to Card's IO space event=0xc1,ch_mask=0x40,fc_mask=7,umask=0x20  01    Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_by_cpu.io_write.part7 uncore io Number Transactions requested by the CPU : Core writing to Card's IO space event=0xc1,ch_mask=0x80,fc_mask=7,umask=0x20  01    Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_by_cpu.mem_read.iommu0 uncore io Number Transactions requested by the CPU : Core reading from Card's MMIO space event=0xc1,ch_mask=0x100,fc_mask=7,umask=4  01    Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_by_cpu.mem_read.iommu1 uncore io Number Transactions requested by the CPU : Core reading from Card's MMIO space event=0xc1,ch_mask=0x200,fc_mask=7,umask=4  01    Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_by_cpu.mem_read.part0 uncore io Number Transactions requested by the CPU : Core reading from Card's MMIO space event=0xc1,ch_mask=1,fc_mask=7,umask=4  01    Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.mem_read.part1 uncore io Number Transactions requested by the CPU : Core reading from Card's MMIO space event=0xc1,ch_mask=2,fc_mask=7,umask=4  01    Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.mem_read.part2 uncore io Number Transactions requested by the CPU : Core reading from Card's MMIO space event=0xc1,ch_mask=4,fc_mask=7,umask=4  01    Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.mem_read.part3 uncore io Number Transactions requested by the CPU : Core reading from Card's MMIO space event=0xc1,ch_mask=8,fc_mask=7,umask=4  01    Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.mem_read.part4 uncore io Number Transactions requested by the CPU : Core reading from Card's MMIO space event=0xc1,ch_mask=0x10,fc_mask=7,umask=4  01    Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_by_cpu.mem_read.part5 uncore io Number Transactions requested by the CPU : Core reading from Card's MMIO space event=0xc1,ch_mask=0x20,fc_mask=7,umask=4  01    Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_by_cpu.mem_read.part6 uncore io Number Transactions requested by the CPU : Core reading from Card's MMIO space event=0xc1,ch_mask=0x40,fc_mask=7,umask=4  01    Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_by_cpu.mem_read.part7 uncore io Number Transactions requested by the CPU : Core reading from Card's MMIO space event=0xc1,ch_mask=0x80,fc_mask=7,umask=4  01    Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_by_cpu.mem_write.iommu0 uncore io Number Transactions requested by the CPU : Core writing to Card's MMIO space event=0xc1,ch_mask=0x100,fc_mask=7,umask=1  01    Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_by_cpu.mem_write.iommu1 uncore io Number Transactions requested by the CPU : Core writing to Card's MMIO space event=0xc1,ch_mask=0x200,fc_mask=7,umask=1  01    Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_by_cpu.mem_write.part0 uncore io Number Transactions requested by the CPU : Core writing to Card's MMIO space event=0xc1,ch_mask=1,fc_mask=7,umask=1  01    Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.mem_write.part1 uncore io Number Transactions requested by the CPU : Core writing to Card's MMIO space event=0xc1,ch_mask=2,fc_mask=7,umask=1  01    Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.mem_write.part2 uncore io Number Transactions requested by the CPU : Core writing to Card's MMIO space event=0xc1,ch_mask=4,fc_mask=7,umask=1  01    Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.mem_write.part3 uncore io Number Transactions requested by the CPU : Core writing to Card's MMIO space event=0xc1,ch_mask=8,fc_mask=7,umask=1  01    Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.mem_write.part4 uncore io Number Transactions requested by the CPU : Core writing to Card's MMIO space event=0xc1,ch_mask=0x10,fc_mask=7,umask=1  01    Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_by_cpu.mem_write.part5 uncore io Number Transactions requested by the CPU : Core writing to Card's MMIO space event=0xc1,ch_mask=0x20,fc_mask=7,umask=1  01    Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_by_cpu.mem_write.part6 uncore io Number Transactions requested by the CPU : Core writing to Card's MMIO space event=0xc1,ch_mask=0x40,fc_mask=7,umask=1  01    Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_by_cpu.mem_write.part7 uncore io Number Transactions requested by the CPU : Core writing to Card's MMIO space event=0xc1,ch_mask=0x80,fc_mask=7,umask=1  01    Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_by_cpu.peer_read.iommu0 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card event=0xc1,ch_mask=0x100,fc_mask=7,umask=8  01    Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_by_cpu.peer_read.iommu1 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card event=0xc1,ch_mask=0x200,fc_mask=7,umask=8  01    Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_by_cpu.peer_read.part0 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card event=0xc1,ch_mask=1,fc_mask=7,umask=8  01    Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_by_cpu.peer_read.part1 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card event=0xc1,ch_mask=2,fc_mask=7,umask=8  01    Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_by_cpu.peer_read.part2 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card event=0xc1,ch_mask=4,fc_mask=7,umask=8  01    Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_by_cpu.peer_read.part3 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card event=0xc1,ch_mask=8,fc_mask=7,umask=8  01    Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_by_cpu.peer_read.part4 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card event=0xc1,ch_mask=0x10,fc_mask=7,umask=8  01    Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_by_cpu.peer_read.part5 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card event=0xc1,ch_mask=0x20,fc_mask=7,umask=8  01    Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_by_cpu.peer_read.part6 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card event=0xc1,ch_mask=0x40,fc_mask=7,umask=8  01    Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_by_cpu.peer_read.part7 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card event=0xc1,ch_mask=0x80,fc_mask=7,umask=8  01    Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_by_cpu.peer_write.iommu0 uncore io Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card event=0xc1,ch_mask=0x200,fc_mask=7,umask=2  01    Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_of_cpu.atomic.iommu0 uncore io Number Transactions requested of the CPU : Atomic requests targeting DRAM event=0x84,ch_mask=0x100,fc_mask=7,umask=0x10  01    Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_of_cpu.atomic.iommu1 uncore io Number Transactions requested of the CPU : Atomic requests targeting DRAM event=0x84,ch_mask=0x200,fc_mask=7,umask=0x10  01    Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_of_cpu.atomic.part0 uncore io Number Transactions requested of the CPU : Atomic requests targeting DRAM event=0x84,ch_mask=1,fc_mask=7,umask=0x10  01    Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.atomic.part1 uncore io Number Transactions requested of the CPU : Atomic requests targeting DRAM event=0x84,ch_mask=2,fc_mask=7,umask=0x10  01    Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.atomic.part2 uncore io Number Transactions requested of the CPU : Atomic requests targeting DRAM event=0x84,ch_mask=4,fc_mask=7,umask=0x10  01    Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_of_cpu.atomic.part3 uncore io Number Transactions requested of the CPU : Atomic requests targeting DRAM event=0x84,ch_mask=8,fc_mask=7,umask=0x10  01    Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.atomic.part4 uncore io Number Transactions requested of the CPU : Atomic requests targeting DRAM event=0x84,ch_mask=0x10,fc_mask=7,umask=0x10  01    Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_of_cpu.atomic.part5 uncore io Number Transactions requested of the CPU : Atomic requests targeting DRAM event=0x84,ch_mask=0x20,fc_mask=7,umask=0x10  01    Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_of_cpu.atomic.part6 uncore io Number Transactions requested of the CPU : Atomic requests targeting DRAM event=0x84,ch_mask=0x40,fc_mask=7,umask=0x10  01    Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_of_cpu.atomic.part7 uncore io Number Transactions requested of the CPU : Atomic requests targeting DRAM event=0x84,ch_mask=0x80,fc_mask=7,umask=0x10  01    Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_of_cpu.cmpd.iommu0 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=0x100,fc_mask=7,umask=0x80  01    Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_of_cpu.cmpd.iommu1 uncore io Number Transactions requested of the CPU : CmpD - device sending completion to CPU request event=0x84,ch_mask=0x200,fc_mask=7,umask=0x80  01    Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_of_cpu.mem_read.iommu0 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x100,fc_mask=7,umask=4  01    Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_of_cpu.mem_read.iommu1 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x200,fc_mask=7,umask=4  01    Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_of_cpu.mem_read.part0 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=1,fc_mask=7,umask=4  01    Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.mem_read.part1 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=2,fc_mask=7,umask=4  01    Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.mem_read.part2 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=4,fc_mask=7,umask=4  01    Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_of_cpu.mem_read.part3 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=8,fc_mask=7,umask=4  01    Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.mem_read.part4 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x10,fc_mask=7,umask=4  01    Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_of_cpu.mem_read.part5 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x20,fc_mask=7,umask=4  01    Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_of_cpu.mem_read.part6 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x40,fc_mask=7,umask=4  01    Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_of_cpu.mem_read.part7 uncore io Number Transactions requested of the CPU : Card reading from DRAM event=0x84,ch_mask=0x80,fc_mask=7,umask=4  01    Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_of_cpu.mem_write.iommu0 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x100,fc_mask=7,umask=1  01    Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_of_cpu.mem_write.iommu1 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x200,fc_mask=7,umask=1  01    Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_of_cpu.mem_write.part0 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=1,fc_mask=7,umask=1  01    Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.mem_write.part1 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=2,fc_mask=7,umask=1  01    Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.mem_write.part2 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=4,fc_mask=7,umask=1  01    Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_of_cpu.mem_write.part3 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=8,fc_mask=7,umask=1  01    Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.mem_write.part4 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x10,fc_mask=7,umask=1  01    Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_of_cpu.mem_write.part5 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x20,fc_mask=7,umask=1  01    Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_of_cpu.mem_write.part6 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x40,fc_mask=7,umask=1  01    Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_of_cpu.mem_write.part7 uncore io Number Transactions requested of the CPU : Card writing to DRAM event=0x84,ch_mask=0x80,fc_mask=7,umask=1  01    Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_of_cpu.msg.iommu0 uncore io Number Transactions requested of the CPU : Messages event=0x84,ch_mask=0x100,fc_mask=7,umask=0x40  01    Number Transactions requested of the CPU : Messages : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_of_cpu.msg.iommu1 uncore io Number Transactions requested of the CPU : Messages event=0x84,ch_mask=0x200,fc_mask=7,umask=0x40  01    Number Transactions requested of the CPU : Messages : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_of_cpu.msg.part0 uncore io Number Transactions requested of the CPU : Messages event=0x84,ch_mask=1,fc_mask=7,umask=0x40  01    Number Transactions requested of the CPU : Messages : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.msg.part1 uncore io Number Transactions requested of the CPU : Messages event=0x84,ch_mask=2,fc_mask=7,umask=0x40  01    Number Transactions requested of the CPU : Messages : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.msg.part2 uncore io Number Transactions requested of the CPU : Messages event=0x84,ch_mask=4,fc_mask=7,umask=0x40  01    Number Transactions requested of the CPU : Messages : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_of_cpu.msg.part3 uncore io Number Transactions requested of the CPU : Messages event=0x84,ch_mask=8,fc_mask=7,umask=0x40  01    Number Transactions requested of the CPU : Messages : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.msg.part4 uncore io Number Transactions requested of the CPU : Messages event=0x84,ch_mask=0x10,fc_mask=7,umask=0x40  01    Number Transactions requested of the CPU : Messages : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_of_cpu.msg.part5 uncore io Number Transactions requested of the CPU : Messages event=0x84,ch_mask=0x20,fc_mask=7,umask=0x40  01    Number Transactions requested of the CPU : Messages : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_of_cpu.msg.part6 uncore io Number Transactions requested of the CPU : Messages event=0x84,ch_mask=0x40,fc_mask=7,umask=0x40  01    Number Transactions requested of the CPU : Messages : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_of_cpu.msg.part7 uncore io Number Transactions requested of the CPU : Messages event=0x84,ch_mask=0x80,fc_mask=7,umask=0x40  01    Number Transactions requested of the CPU : Messages : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_of_cpu.peer_read.iommu0 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=0x100,fc_mask=7,umask=8  01    Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_of_cpu.peer_read.iommu1 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=0x200,fc_mask=7,umask=8  01    Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_iio_txn_req_of_cpu.peer_read.part0 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=1,fc_mask=7,umask=8  01    Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_txn_req_of_cpu.peer_read.part1 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=2,fc_mask=7,umask=8  01    Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_txn_req_of_cpu.peer_read.part2 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=4,fc_mask=7,umask=8  01    Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_txn_req_of_cpu.peer_read.part3 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=8,fc_mask=7,umask=8  01    Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_txn_req_of_cpu.peer_read.part4 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=0x10,fc_mask=7,umask=8  01    Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 unc_iio_txn_req_of_cpu.peer_read.part5 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=0x20,fc_mask=7,umask=8  01    Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 unc_iio_txn_req_of_cpu.peer_read.part6 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=0x40,fc_mask=7,umask=8  01    Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 unc_iio_txn_req_of_cpu.peer_read.part7 uncore io Number Transactions requested of the CPU : Card reading from another Card (same or different stack) event=0x84,ch_mask=0x80,fc_mask=7,umask=8  01    Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 unc_iio_txn_req_of_cpu.peer_write.iommu0 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x100,fc_mask=7,umask=2  01    Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0 unc_iio_txn_req_of_cpu.peer_write.iommu1 uncore io Number Transactions requested of the CPU : Card writing to another Card (same or different stack) event=0x84,ch_mask=0x200,fc_mask=7,umask=2  01    Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1 unc_m2p_ag0_ad_crd_acquired0.tgr0 uncore io CMS Agent0 AD Credits Acquired : For Transgress 0 event=0x80,umask=1  01    CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_acquired0.tgr1 uncore io CMS Agent0 AD Credits Acquired : For Transgress 1 event=0x80,umask=2  01    CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_acquired0.tgr2 uncore io CMS Agent0 AD Credits Acquired : For Transgress 2 event=0x80,umask=4  01    CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_acquired0.tgr3 uncore io CMS Agent0 AD Credits Acquired : For Transgress 3 event=0x80,umask=8  01    CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_acquired0.tgr4 uncore io CMS Agent0 AD Credits Acquired : For Transgress 4 event=0x80,umask=0x10  01    CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_acquired0.tgr5 uncore io CMS Agent0 AD Credits Acquired : For Transgress 5 event=0x80,umask=0x20  01    CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_acquired0.tgr6 uncore io CMS Agent0 AD Credits Acquired : For Transgress 6 event=0x80,umask=0x40  01    CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_acquired0.tgr7 uncore io CMS Agent0 AD Credits Acquired : For Transgress 7 event=0x80,umask=0x80  01    CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_acquired1.tgr10 uncore io CMS Agent0 AD Credits Acquired : For Transgress 10 event=0x81,umask=4  01    CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_acquired1.tgr8 uncore io CMS Agent0 AD Credits Acquired : For Transgress 8 event=0x81,umask=1  01    CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_acquired1.tgr9 uncore io CMS Agent0 AD Credits Acquired : For Transgress 9 event=0x81,umask=2  01    CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy0.tgr0 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 0 event=0x82,umask=1  01    CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy0.tgr1 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 1 event=0x82,umask=2  01    CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy0.tgr2 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 2 event=0x82,umask=4  01    CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy0.tgr3 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 3 event=0x82,umask=8  01    CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy0.tgr4 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 4 event=0x82,umask=0x10  01    CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy0.tgr5 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 5 event=0x82,umask=0x20  01    CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy0.tgr6 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 6 event=0x82,umask=0x40  01    CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy0.tgr7 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 7 event=0x82,umask=0x80  01    CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy1.tgr10 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 10 event=0x83,umask=4  01    CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy1.tgr8 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 8 event=0x83,umask=1  01    CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_ad_crd_occupancy1.tgr9 uncore io CMS Agent0 AD Credits Occupancy : For Transgress 9 event=0x83,umask=2  01    CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired0.tgr0 uncore io CMS Agent0 BL Credits Acquired : For Transgress 0 event=0x88,umask=1  01    CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired0.tgr1 uncore io CMS Agent0 BL Credits Acquired : For Transgress 1 event=0x88,umask=2  01    CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired0.tgr2 uncore io CMS Agent0 BL Credits Acquired : For Transgress 2 event=0x88,umask=4  01    CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired0.tgr3 uncore io CMS Agent0 BL Credits Acquired : For Transgress 3 event=0x88,umask=8  01    CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired0.tgr4 uncore io CMS Agent0 BL Credits Acquired : For Transgress 4 event=0x88,umask=0x10  01    CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired0.tgr5 uncore io CMS Agent0 BL Credits Acquired : For Transgress 5 event=0x88,umask=0x20  01    CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired0.tgr6 uncore io CMS Agent0 BL Credits Acquired : For Transgress 6 event=0x88,umask=0x40  01    CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired0.tgr7 uncore io CMS Agent0 BL Credits Acquired : For Transgress 7 event=0x88,umask=0x80  01    CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired1.tgr10 uncore io CMS Agent0 BL Credits Acquired : For Transgress 10 event=0x89,umask=4  01    CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired1.tgr8 uncore io CMS Agent0 BL Credits Acquired : For Transgress 8 event=0x89,umask=1  01    CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_acquired1.tgr9 uncore io CMS Agent0 BL Credits Acquired : For Transgress 9 event=0x89,umask=2  01    CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy0.tgr0 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 0 event=0x8a,umask=1  01    CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy0.tgr1 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 1 event=0x8a,umask=2  01    CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy0.tgr2 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 2 event=0x8a,umask=4  01    CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy0.tgr3 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 3 event=0x8a,umask=8  01    CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy0.tgr4 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 4 event=0x8a,umask=0x10  01    CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy0.tgr5 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 5 event=0x8a,umask=0x20  01    CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy0.tgr6 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 6 event=0x8a,umask=0x40  01    CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy0.tgr7 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 7 event=0x8a,umask=0x80  01    CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy1.tgr10 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 10 event=0x8b,umask=4  01    CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy1.tgr8 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 8 event=0x8b,umask=1  01    CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag0_bl_crd_occupancy1.tgr9 uncore io CMS Agent0 BL Credits Occupancy : For Transgress 9 event=0x8b,umask=2  01    CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired0.tgr0 uncore io CMS Agent1 AD Credits Acquired : For Transgress 0 event=0x84,umask=1  01    CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired0.tgr1 uncore io CMS Agent1 AD Credits Acquired : For Transgress 1 event=0x84,umask=2  01    CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired0.tgr2 uncore io CMS Agent1 AD Credits Acquired : For Transgress 2 event=0x84,umask=4  01    CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired0.tgr3 uncore io CMS Agent1 AD Credits Acquired : For Transgress 3 event=0x84,umask=8  01    CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired0.tgr4 uncore io CMS Agent1 AD Credits Acquired : For Transgress 4 event=0x84,umask=0x10  01    CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired0.tgr5 uncore io CMS Agent1 AD Credits Acquired : For Transgress 5 event=0x84,umask=0x20  01    CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired0.tgr6 uncore io CMS Agent1 AD Credits Acquired : For Transgress 6 event=0x84,umask=0x40  01    CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired0.tgr7 uncore io CMS Agent1 AD Credits Acquired : For Transgress 7 event=0x84,umask=0x80  01    CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired1.tgr10 uncore io CMS Agent1 AD Credits Acquired : For Transgress 10 event=0x85,umask=4  01    CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired1.tgr8 uncore io CMS Agent1 AD Credits Acquired : For Transgress 8 event=0x85,umask=1  01    CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_acquired1.tgr9 uncore io CMS Agent1 AD Credits Acquired : For Transgress 9 event=0x85,umask=2  01    CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy0.tgr0 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 0 event=0x86,umask=1  01    CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy0.tgr1 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 1 event=0x86,umask=2  01    CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy0.tgr2 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 2 event=0x86,umask=4  01    CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy0.tgr3 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 3 event=0x86,umask=8  01    CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy0.tgr4 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 4 event=0x86,umask=0x10  01    CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy0.tgr5 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 5 event=0x86,umask=0x20  01    CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy0.tgr6 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 6 event=0x86,umask=0x40  01    CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy0.tgr7 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 7 event=0x86,umask=0x80  01    CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy1.tgr10 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 10 event=0x87,umask=4  01    CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy1.tgr8 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 8 event=0x87,umask=1  01    CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_ad_crd_occupancy1.tgr9 uncore io CMS Agent1 AD Credits Occupancy : For Transgress 9 event=0x87,umask=2  01    CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired0.tgr0 uncore io CMS Agent1 BL Credits Acquired : For Transgress 0 event=0x8c,umask=1  01    CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired0.tgr1 uncore io CMS Agent1 BL Credits Acquired : For Transgress 1 event=0x8c,umask=2  01    CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired0.tgr2 uncore io CMS Agent1 BL Credits Acquired : For Transgress 2 event=0x8c,umask=4  01    CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired0.tgr3 uncore io CMS Agent1 BL Credits Acquired : For Transgress 3 event=0x8c,umask=8  01    CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired0.tgr4 uncore io CMS Agent1 BL Credits Acquired : For Transgress 4 event=0x8c,umask=0x10  01    CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired0.tgr5 uncore io CMS Agent1 BL Credits Acquired : For Transgress 5 event=0x8c,umask=0x20  01    CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired0.tgr6 uncore io CMS Agent1 BL Credits Acquired : For Transgress 4 event=0x8c,umask=0x40  01    CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired0.tgr7 uncore io CMS Agent1 BL Credits Acquired : For Transgress 5 event=0x8c,umask=0x80  01    CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired1.tgr10 uncore io CMS Agent1 BL Credits Acquired : For Transgress 10 event=0x8d,umask=4  01    CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired1.tgr8 uncore io CMS Agent1 BL Credits Acquired : For Transgress 8 event=0x8d,umask=1  01    CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_acquired1.tgr9 uncore io CMS Agent1 BL Credits Acquired : For Transgress 9 event=0x8d,umask=2  01    CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy0.tgr0 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 0 event=0x8e,umask=1  01    CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy0.tgr1 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 1 event=0x8e,umask=2  01    CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy0.tgr2 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 2 event=0x8e,umask=4  01    CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy0.tgr3 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 3 event=0x8e,umask=8  01    CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy0.tgr4 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 4 event=0x8e,umask=0x10  01    CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy0.tgr5 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 5 event=0x8e,umask=0x20  01    CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy0.tgr6 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 6 event=0x8e,umask=0x40  01    CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy0.tgr7 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 7 event=0x8e,umask=0x80  01    CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy1.tgr10 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 10 event=0x8f,umask=4  01    CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy1.tgr8 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 8 event=0x8f,umask=1  01    CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_ag1_bl_crd_occupancy1.tgr9 uncore io CMS Agent1 BL Credits Occupancy : For Transgress 9 event=0x8f,umask=2  01    CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress unc_m2p_clockticks uncore io Clockticks of the mesh to PCI (M2P) event=1  01    Clockticks of the mesh to PCI (M2P) : Counts the number of uclks in the M3 uclk domain.  This could be slightly different than the count in the Ubox because of enable/freeze delays.  However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles unc_m2p_distress_asserted.dpt_local uncore io Distress signal asserted : DPT Local event=0xaf,umask=4  01    Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile unc_m2p_distress_asserted.dpt_nonlocal uncore io Distress signal asserted : DPT Remote event=0xaf,umask=8  01    Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile unc_m2p_distress_asserted.dpt_stall_iv uncore io Distress signal asserted : DPT Stalled - IV event=0xaf,umask=0x40  01    Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled unc_m2p_distress_asserted.dpt_stall_nocrd uncore io Distress signal asserted : DPT Stalled -  No Credit event=0xaf,umask=0x80  01    Distress signal asserted : DPT Stalled -  No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled unc_m2p_distress_asserted.horz uncore io Distress signal asserted : Horizontal event=0xaf,umask=2  01    Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions unc_m2p_distress_asserted.pmm_local uncore io Distress signal asserted : PMM Local event=0xaf,umask=0x10  01    Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic unc_m2p_distress_asserted.pmm_nonlocal uncore io Distress signal asserted : PMM Remote event=0xaf,umask=0x20  01    Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic unc_m2p_distress_asserted.vert uncore io Distress signal asserted : Vertical event=0xaf,umask=1  01    Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions unc_m2p_horz_ring_ad_in_use.left_even uncore io Horizontal AD Ring In Use : Left and Even event=0xb6,umask=1  01    Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_ad_in_use.left_odd uncore io Horizontal AD Ring In Use : Left and Odd event=0xb6,umask=2  01    Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_ad_in_use.right_even uncore io Horizontal AD Ring In Use : Right and Even event=0xb6,umask=4  01    Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_ad_in_use.right_odd uncore io Horizontal AD Ring In Use : Right and Odd event=0xb6,umask=8  01    Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_akc_in_use.left_even uncore io Horizontal AK Ring In Use : Left and Even event=0xbb,umask=1  01    Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_akc_in_use.left_odd uncore io Horizontal AK Ring In Use : Left and Odd event=0xbb,umask=2  01    Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_akc_in_use.right_even uncore io Horizontal AK Ring In Use : Right and Even event=0xbb,umask=4  01    Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_akc_in_use.right_odd uncore io Horizontal AK Ring In Use : Right and Odd event=0xbb,umask=8  01    Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_ak_in_use.left_even uncore io Horizontal AK Ring In Use : Left and Even event=0xb7,umask=1  01    Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_ak_in_use.left_odd uncore io Horizontal AK Ring In Use : Left and Odd event=0xb7,umask=2  01    Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_ak_in_use.right_even uncore io Horizontal AK Ring In Use : Right and Even event=0xb7,umask=4  01    Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_ak_in_use.right_odd uncore io Horizontal AK Ring In Use : Right and Odd event=0xb7,umask=8  01    Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_bl_in_use.left_even uncore io Horizontal BL Ring in Use : Left and Even event=0xb8,umask=1  01    Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_bl_in_use.left_odd uncore io Horizontal BL Ring in Use : Left and Odd event=0xb8,umask=2  01    Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_bl_in_use.right_even uncore io Horizontal BL Ring in Use : Right and Even event=0xb8,umask=4  01    Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_bl_in_use.right_odd uncore io Horizontal BL Ring in Use : Right and Odd event=0xb8,umask=8  01    Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_horz_ring_iv_in_use.left uncore io Horizontal IV Ring in Use : Left event=0xb9,umask=1  01    Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2p_horz_ring_iv_in_use.right uncore io Horizontal IV Ring in Use : Right event=0xb9,umask=4  01    Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2p_local_p2p_ded_returned_0.ms2iosf3_ncb uncore io Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCB event=0x19,umask=0x10  01     unc_m2p_local_p2p_ded_returned_0.ms2iosf3_ncs uncore io Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCS event=0x19,umask=0x20  01     unc_m2p_misc_external.mbe_inst0 uncore io Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0 event=0xe6,umask=1  01     unc_m2p_misc_external.mbe_inst1 uncore io Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1 event=0xe6,umask=2  01     unc_m2p_ring_bounces_horz.ad uncore io Messages that bounced on the Horizontal Ring. : AD event=0xac,umask=1  01    Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2p_ring_bounces_horz.ak uncore io Messages that bounced on the Horizontal Ring. : AK event=0xac,umask=2  01    Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2p_ring_bounces_horz.bl uncore io Messages that bounced on the Horizontal Ring. : BL event=0xac,umask=4  01    Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2p_ring_bounces_horz.iv uncore io Messages that bounced on the Horizontal Ring. : IV event=0xac,umask=8  01    Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type unc_m2p_ring_bounces_vert.ad uncore io Messages that bounced on the Vertical Ring. : AD event=0xaa,umask=1  01    Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2p_ring_bounces_vert.ak uncore io Messages that bounced on the Vertical Ring. : Acknowledgements to core event=0xaa,umask=2  01    Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2p_ring_bounces_vert.akc uncore io Messages that bounced on the Vertical Ring event=0xaa,umask=0x10  01    Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2p_ring_bounces_vert.bl uncore io Messages that bounced on the Vertical Ring. : Data Responses to core event=0xaa,umask=4  01    Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2p_ring_bounces_vert.iv uncore io Messages that bounced on the Vertical Ring. : Snoops of processor's cache event=0xaa,umask=8  01    Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type unc_m2p_ring_sink_starved_horz.ad uncore io Sink Starvation on Horizontal Ring : AD event=0xad,umask=1  01     unc_m2p_ring_sink_starved_horz.ak uncore io Sink Starvation on Horizontal Ring : AK event=0xad,umask=2  01     unc_m2p_ring_sink_starved_horz.ak_ag1 uncore io Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1 event=0xad,umask=0x20  01     unc_m2p_ring_sink_starved_horz.bl uncore io Sink Starvation on Horizontal Ring : BL event=0xad,umask=4  01     unc_m2p_ring_sink_starved_horz.iv uncore io Sink Starvation on Horizontal Ring : IV event=0xad,umask=8  01     unc_m2p_ring_sink_starved_vert.ad uncore io Sink Starvation on Vertical Ring : AD event=0xab,umask=1  01     unc_m2p_ring_sink_starved_vert.ak uncore io Sink Starvation on Vertical Ring : Acknowledgements to core event=0xab,umask=2  01     unc_m2p_ring_sink_starved_vert.akc uncore io Sink Starvation on Vertical Ring event=0xab,umask=0x10  01     unc_m2p_ring_sink_starved_vert.bl uncore io Sink Starvation on Vertical Ring : Data Responses to core event=0xab,umask=4  01     unc_m2p_ring_sink_starved_vert.iv uncore io Sink Starvation on Vertical Ring : Snoops of processor's cache event=0xab,umask=8  01     unc_m2p_ring_src_thrtl uncore io Source Throttle event=0xae  01     unc_m2p_rxr_busy_starved.ad_all uncore io Transgress Injection Starvation : AD - All event=0xe5,umask=0x11  01    Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority : All == Credited + Uncredited unc_m2p_rxr_busy_starved.ad_crd uncore io Transgress Injection Starvation : AD - Credited event=0xe5,umask=0x10  01    Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority unc_m2p_rxr_busy_starved.ad_uncrd uncore io Transgress Injection Starvation : AD - Uncredited event=0xe5,umask=1  01    Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority unc_m2p_rxr_busy_starved.bl_all uncore io Transgress Injection Starvation : BL - All event=0xe5,umask=0x44  01    Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority : All == Credited + Uncredited unc_m2p_rxr_busy_starved.bl_crd uncore io Transgress Injection Starvation : BL - Credited event=0xe5,umask=0x40  01    Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority unc_m2p_rxr_busy_starved.bl_uncrd uncore io Transgress Injection Starvation : BL - Uncredited event=0xe5,umask=4  01    Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority unc_m2p_rxr_bypass.ad_all uncore io Transgress Ingress Bypass : AD - All event=0xe2,umask=0x11  01    Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited unc_m2p_rxr_bypass.ad_crd uncore io Transgress Ingress Bypass : AD - Credited event=0xe2,umask=0x10  01    Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress unc_m2p_rxr_bypass.ad_uncrd uncore io Transgress Ingress Bypass : AD - Uncredited event=0xe2,umask=1  01    Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress unc_m2p_rxr_bypass.ak uncore io Transgress Ingress Bypass : AK event=0xe2,umask=2  01    Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress unc_m2p_rxr_bypass.akc_uncrd uncore io Transgress Ingress Bypass : AKC - Uncredited event=0xe2,umask=0x80  01    Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress unc_m2p_rxr_bypass.bl_all uncore io Transgress Ingress Bypass : BL - All event=0xe2,umask=0x44  01    Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited unc_m2p_rxr_bypass.bl_crd uncore io Transgress Ingress Bypass : BL - Credited event=0xe2,umask=0x40  01    Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress unc_m2p_rxr_bypass.bl_uncrd uncore io Transgress Ingress Bypass : BL - Uncredited event=0xe2,umask=4  01    Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress unc_m2p_rxr_bypass.iv uncore io Transgress Ingress Bypass : IV event=0xe2,umask=8  01    Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress unc_m2p_rxr_crd_starved.ad_all uncore io Transgress Injection Starvation : AD - All event=0xe3,umask=0x11  01    Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited unc_m2p_rxr_crd_starved.ad_crd uncore io Transgress Injection Starvation : AD - Credited event=0xe3,umask=0x10  01    Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2p_rxr_crd_starved.ad_uncrd uncore io Transgress Injection Starvation : AD - Uncredited event=0xe3,umask=1  01    Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2p_rxr_crd_starved.ak uncore io Transgress Injection Starvation : AK event=0xe3,umask=2  01    Transgress Injection Starvation : AK : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2p_rxr_crd_starved.bl_all uncore io Transgress Injection Starvation : BL - All event=0xe3,umask=0x44  01    Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited unc_m2p_rxr_crd_starved.bl_crd uncore io Transgress Injection Starvation : BL - Credited event=0xe3,umask=0x40  01    Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2p_rxr_crd_starved.bl_uncrd uncore io Transgress Injection Starvation : BL - Uncredited event=0xe3,umask=4  01    Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2p_rxr_crd_starved.ifv uncore io Transgress Injection Starvation : IFV - Credited event=0xe3,umask=0x80  01    Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2p_rxr_crd_starved.iv uncore io Transgress Injection Starvation : IV event=0xe3,umask=8  01    Transgress Injection Starvation : IV : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2p_rxr_crd_starved_1 uncore io Transgress Injection Starvation event=0xe4  01    Transgress Injection Starvation : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit unc_m2p_rxr_inserts.ad_all uncore io Transgress Ingress Allocations : AD - All event=0xe1,umask=0x11  01    Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m2p_rxr_inserts.ad_crd uncore io Transgress Ingress Allocations : AD - Credited event=0xe1,umask=0x10  01    Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_inserts.ad_uncrd uncore io Transgress Ingress Allocations : AD - Uncredited event=0xe1,umask=1  01    Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_inserts.ak uncore io Transgress Ingress Allocations : AK event=0xe1,umask=2  01    Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_inserts.akc_uncrd uncore io Transgress Ingress Allocations : AKC - Uncredited event=0xe1,umask=0x80  01    Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_inserts.bl_all uncore io Transgress Ingress Allocations : BL - All event=0xe1,umask=0x44  01    Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m2p_rxr_inserts.bl_crd uncore io Transgress Ingress Allocations : BL - Credited event=0xe1,umask=0x40  01    Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_inserts.bl_uncrd uncore io Transgress Ingress Allocations : BL - Uncredited event=0xe1,umask=4  01    Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_inserts.iv uncore io Transgress Ingress Allocations : IV event=0xe1,umask=8  01    Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_occupancy.ad_all uncore io Transgress Ingress Occupancy : AD - All event=0xe0,umask=0x11  01    Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m2p_rxr_occupancy.ad_crd uncore io Transgress Ingress Occupancy : AD - Credited event=0xe0,umask=0x10  01    Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_occupancy.ad_uncrd uncore io Transgress Ingress Occupancy : AD - Uncredited event=0xe0,umask=1  01    Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_occupancy.ak uncore io Transgress Ingress Occupancy : AK event=0xe0,umask=2  01    Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_occupancy.akc_uncrd uncore io Transgress Ingress Occupancy : AKC - Uncredited event=0xe0,umask=0x80  01    Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_occupancy.bl_all uncore io Transgress Ingress Occupancy : BL - All event=0xe0,umask=0x44  01    Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited unc_m2p_rxr_occupancy.bl_crd uncore io Transgress Ingress Occupancy : BL - Credited event=0xe0,umask=0x20  01    Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_occupancy.bl_uncrd uncore io Transgress Ingress Occupancy : BL - Uncredited event=0xe0,umask=4  01    Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m2p_rxr_occupancy.iv uncore io Transgress Ingress Occupancy : IV event=0xe0,umask=8  01    Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh unc_m2p_stall0_no_txr_horz_crd_ad_ag0.tgr0 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 0 event=0xd0,umask=1  01    Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag0.tgr1 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 1 event=0xd0,umask=2  01    Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag0.tgr2 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 2 event=0xd0,umask=4  01    Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag0.tgr3 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 3 event=0xd0,umask=8  01    Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag0.tgr4 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 4 event=0xd0,umask=0x10  01    Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag0.tgr5 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 5 event=0xd0,umask=0x20  01    Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag0.tgr6 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 6 event=0xd0,umask=0x40  01    Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag0.tgr7 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 7 event=0xd0,umask=0x80  01    Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag1.tgr0 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 0 event=0xd2,umask=1  01    Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag1.tgr1 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 1 event=0xd2,umask=2  01    Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag1.tgr2 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 2 event=0xd2,umask=4  01    Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag1.tgr3 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 3 event=0xd2,umask=8  01    Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag1.tgr4 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 4 event=0xd2,umask=0x10  01    Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag1.tgr5 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 5 event=0xd2,umask=0x20  01    Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag1.tgr6 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 6 event=0xd2,umask=0x40  01    Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_ad_ag1.tgr7 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 7 event=0xd2,umask=0x80  01    Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag0.tgr0 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 0 event=0xd4,umask=1  01    Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag0.tgr1 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 1 event=0xd4,umask=2  01    Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag0.tgr2 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 2 event=0xd4,umask=4  01    Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag0.tgr3 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 3 event=0xd4,umask=8  01    Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag0.tgr4 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 4 event=0xd4,umask=0x10  01    Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag0.tgr5 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 5 event=0xd4,umask=0x20  01    Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag0.tgr6 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 6 event=0xd4,umask=0x40  01    Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag0.tgr7 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 7 event=0xd4,umask=0x80  01    Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag1.tgr0 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 0 event=0xd6,umask=1  01    Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag1.tgr1 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 1 event=0xd6,umask=2  01    Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag1.tgr2 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 2 event=0xd6,umask=4  01    Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag1.tgr3 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 3 event=0xd6,umask=8  01    Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag1.tgr4 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 4 event=0xd6,umask=0x10  01    Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag1.tgr5 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 5 event=0xd6,umask=0x20  01    Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag1.tgr6 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 6 event=0xd6,umask=0x40  01    Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall0_no_txr_horz_crd_bl_ag1.tgr7 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 7 event=0xd6,umask=0x80  01    Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_ad_ag0.tgr10 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 10 event=0xd1,umask=4  01    Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_ad_ag0.tgr8 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 8 event=0xd1,umask=1  01    Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_ad_ag0.tgr9 uncore io Stall on No AD Agent0 Transgress Credits : For Transgress 9 event=0xd1,umask=2  01    Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_ad_ag1_1.tgr10 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 10 event=0xd3,umask=4  01    Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_ad_ag1_1.tgr8 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 8 event=0xd3,umask=1  01    Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_ad_ag1_1.tgr9 uncore io Stall on No AD Agent1 Transgress Credits : For Transgress 9 event=0xd3,umask=2  01    Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_bl_ag0_1.tgr10 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 10 event=0xd5,umask=4  01    Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_bl_ag0_1.tgr8 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 8 event=0xd5,umask=1  01    Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_bl_ag0_1.tgr9 uncore io Stall on No BL Agent0 Transgress Credits : For Transgress 9 event=0xd5,umask=2  01    Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_bl_ag1_1.tgr10 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 10 event=0xd7,umask=4  01    Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_bl_ag1_1.tgr8 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 8 event=0xd7,umask=1  01    Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_stall1_no_txr_horz_crd_bl_ag1_1.tgr9 uncore io Stall on No BL Agent1 Transgress Credits : For Transgress 9 event=0xd7,umask=2  01    Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress unc_m2p_txc_cycles_full.ad_0 uncore io Egress (to CMS) Cycles Full event=0x25,umask=1  01    Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent unc_m2p_txc_cycles_full.ad_1 uncore io Egress (to CMS) Cycles Full event=0x25,umask=0x10  01    Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent unc_m2p_txc_cycles_full.ak_0 uncore io Egress (to CMS) Cycles Full event=0x25,umask=2  01    Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent unc_m2p_txc_cycles_full.ak_1 uncore io Egress (to CMS) Cycles Full event=0x25,umask=0x20  01    Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent unc_m2p_txc_cycles_full.bl_0 uncore io Egress (to CMS) Cycles Full event=0x25,umask=4  01    Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent unc_m2p_txc_cycles_full.bl_1 uncore io Egress (to CMS) Cycles Full event=0x25,umask=0x40  01    Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent unc_m2p_txc_cycles_ne.ad_0 uncore io Egress (to CMS) Cycles Not Empty event=0x23,umask=1  01    Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple egress buffers can be tracked at a given time using multiple counters unc_m2p_txc_cycles_ne.ad_1 uncore io Egress (to CMS) Cycles Not Empty event=0x23,umask=0x10  01    Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple egress buffers can be tracked at a given time using multiple counters unc_m2p_txc_cycles_ne.ak_0 uncore io Egress (to CMS) Cycles Not Empty event=0x23,umask=2  01    Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple egress buffers can be tracked at a given time using multiple counters unc_m2p_txc_cycles_ne.ak_1 uncore io Egress (to CMS) Cycles Not Empty event=0x23,umask=0x20  01    Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple egress buffers can be tracked at a given time using multiple counters unc_m2p_txc_cycles_ne.bl_0 uncore io Egress (to CMS) Cycles Not Empty event=0x23,umask=4  01    Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple egress buffers can be tracked at a given time using multiple counters unc_m2p_txc_cycles_ne.bl_1 uncore io Egress (to CMS) Cycles Not Empty event=0x23,umask=0x40  01    Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple egress buffers can be tracked at a given time using multiple counters unc_m2p_txc_inserts.ad_0 uncore io Egress (to CMS) Ingress event=0x24,umask=1  01    Egress (to CMS) Ingress : Counts the number of number of messages inserted into the  the M2PCIe Egress queue.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy unc_m2p_txc_inserts.ad_1 uncore io Egress (to CMS) Ingress event=0x24,umask=0x10  01    Egress (to CMS) Ingress : Counts the number of number of messages inserted into the  the M2PCIe Egress queue.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy unc_m2p_txc_inserts.ak_crd_0 uncore io Egress (to CMS) Ingress event=0x24,umask=8  01    Egress (to CMS) Ingress : Counts the number of number of messages inserted into the  the M2PCIe Egress queue.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy unc_m2p_txc_inserts.ak_crd_1 uncore io Egress (to CMS) Ingress event=0x24,umask=0x80  01    Egress (to CMS) Ingress : Counts the number of number of messages inserted into the  the M2PCIe Egress queue.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy unc_m2p_txc_inserts.bl_0 uncore io Egress (to CMS) Ingress event=0x24,umask=4  01    Egress (to CMS) Ingress : Counts the number of number of messages inserted into the  the M2PCIe Egress queue.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy unc_m2p_txc_inserts.bl_1 uncore io Egress (to CMS) Ingress event=0x24,umask=0x40  01    Egress (to CMS) Ingress : Counts the number of number of messages inserted into the  the M2PCIe Egress queue.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy unc_m2p_txr_horz_ads_used.ad_all uncore io CMS Horizontal ADS Used : AD - All event=0xa6,umask=0x11  01    CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m2p_txr_horz_ads_used.ad_crd uncore io CMS Horizontal ADS Used : AD - Credited event=0xa6,umask=0x10  01    CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2p_txr_horz_ads_used.ad_uncrd uncore io CMS Horizontal ADS Used : AD - Uncredited event=0xa6,umask=1  01    CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2p_txr_horz_ads_used.bl_all uncore io CMS Horizontal ADS Used : BL - All event=0xa6,umask=0x44  01    CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m2p_txr_horz_ads_used.bl_crd uncore io CMS Horizontal ADS Used : BL - Credited event=0xa6,umask=0x40  01    CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2p_txr_horz_ads_used.bl_uncrd uncore io CMS Horizontal ADS Used : BL - Uncredited event=0xa6,umask=4  01    CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2p_txr_horz_bypass.ad_all uncore io CMS Horizontal Bypass Used : AD - All event=0xa7,umask=0x11  01    CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m2p_txr_horz_bypass.ad_crd uncore io CMS Horizontal Bypass Used : AD - Credited event=0xa7,umask=0x10  01    CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2p_txr_horz_bypass.ad_uncrd uncore io CMS Horizontal Bypass Used : AD - Uncredited event=0xa7,umask=1  01    CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2p_txr_horz_bypass.ak uncore io CMS Horizontal Bypass Used : AK event=0xa7,umask=2  01    CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2p_txr_horz_bypass.akc_uncrd uncore io CMS Horizontal Bypass Used : AKC - Uncredited event=0xa7,umask=0x80  01    CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2p_txr_horz_bypass.bl_all uncore io CMS Horizontal Bypass Used : BL - All event=0xa7,umask=0x44  01    CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited unc_m2p_txr_horz_bypass.bl_crd uncore io CMS Horizontal Bypass Used : BL - Credited event=0xa7,umask=0x40  01    CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2p_txr_horz_bypass.bl_uncrd uncore io CMS Horizontal Bypass Used : BL - Uncredited event=0xa7,umask=4  01    CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2p_txr_horz_bypass.iv uncore io CMS Horizontal Bypass Used : IV event=0xa7,umask=8  01    CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent unc_m2p_txr_horz_cycles_full.ad_all uncore io Cycles CMS Horizontal Egress Queue is Full : AD - All event=0xa2,umask=0x11  01    Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2p_txr_horz_cycles_full.ad_crd uncore io Cycles CMS Horizontal Egress Queue is Full : AD - Credited event=0xa2,umask=0x10  01    Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_full.ad_uncrd uncore io Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited event=0xa2,umask=1  01    Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_full.ak uncore io Cycles CMS Horizontal Egress Queue is Full : AK event=0xa2,umask=2  01    Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_full.akc_uncrd uncore io Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited event=0xa2,umask=0x80  01    Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_full.bl_all uncore io Cycles CMS Horizontal Egress Queue is Full : BL - All event=0xa2,umask=0x44  01    Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2p_txr_horz_cycles_full.bl_crd uncore io Cycles CMS Horizontal Egress Queue is Full : BL - Credited event=0xa2,umask=0x40  01    Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_full.bl_uncrd uncore io Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited event=0xa2,umask=4  01    Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_full.iv uncore io Cycles CMS Horizontal Egress Queue is Full : IV event=0xa2,umask=8  01    Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_ne.ad_all uncore io Cycles CMS Horizontal Egress Queue is Not Empty : AD - All event=0xa3,umask=0x11  01    Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2p_txr_horz_cycles_ne.ad_crd uncore io Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited event=0xa3,umask=0x10  01    Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_ne.ad_uncrd uncore io Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited event=0xa3,umask=1  01    Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_ne.ak uncore io Cycles CMS Horizontal Egress Queue is Not Empty : AK event=0xa3,umask=2  01    Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_ne.akc_uncrd uncore io Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited event=0xa3,umask=0x80  01    Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_ne.bl_all uncore io Cycles CMS Horizontal Egress Queue is Not Empty : BL - All event=0xa3,umask=0x44  01    Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2p_txr_horz_cycles_ne.bl_crd uncore io Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited event=0xa3,umask=0x40  01    Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_ne.bl_uncrd uncore io Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited event=0xa3,umask=4  01    Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_cycles_ne.iv uncore io Cycles CMS Horizontal Egress Queue is Not Empty : IV event=0xa3,umask=8  01    Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_inserts.ad_all uncore io CMS Horizontal Egress Inserts : AD - All event=0xa1,umask=0x11  01    CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2p_txr_horz_inserts.ad_crd uncore io CMS Horizontal Egress Inserts : AD - Credited event=0xa1,umask=0x10  01    CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_inserts.ad_uncrd uncore io CMS Horizontal Egress Inserts : AD - Uncredited event=0xa1,umask=1  01    CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_inserts.ak uncore io CMS Horizontal Egress Inserts : AK event=0xa1,umask=2  01    CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_inserts.akc_uncrd uncore io CMS Horizontal Egress Inserts : AKC - Uncredited event=0xa1,umask=0x80  01    CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_inserts.bl_all uncore io CMS Horizontal Egress Inserts : BL - All event=0xa1,umask=0x44  01    CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2p_txr_horz_inserts.bl_crd uncore io CMS Horizontal Egress Inserts : BL - Credited event=0xa1,umask=0x40  01    CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_inserts.bl_uncrd uncore io CMS Horizontal Egress Inserts : BL - Uncredited event=0xa1,umask=4  01    CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_inserts.iv uncore io CMS Horizontal Egress Inserts : IV event=0xa1,umask=8  01    CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_nack.ad_all uncore io CMS Horizontal Egress NACKs : AD - All event=0xa4,umask=0x11  01    CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited unc_m2p_txr_horz_nack.ad_crd uncore io CMS Horizontal Egress NACKs : AD - Credited event=0xa4,umask=0x10  01    CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2p_txr_horz_nack.ad_uncrd uncore io CMS Horizontal Egress NACKs : AD - Uncredited event=0xa4,umask=1  01    CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2p_txr_horz_nack.ak uncore io CMS Horizontal Egress NACKs : AK event=0xa4,umask=2  01    CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2p_txr_horz_nack.akc_uncrd uncore io CMS Horizontal Egress NACKs : AKC - Uncredited event=0xa4,umask=0x80  01    CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2p_txr_horz_nack.bl_all uncore io CMS Horizontal Egress NACKs : BL - All event=0xa4,umask=0x44  01    CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited unc_m2p_txr_horz_nack.bl_crd uncore io CMS Horizontal Egress NACKs : BL - Credited event=0xa4,umask=0x40  01    CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2p_txr_horz_nack.bl_uncrd uncore io CMS Horizontal Egress NACKs : BL - Uncredited event=0xa4,umask=4  01    CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2p_txr_horz_nack.iv uncore io CMS Horizontal Egress NACKs : IV event=0xa4,umask=8  01    CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring unc_m2p_txr_horz_occupancy.ad_all uncore io CMS Horizontal Egress Occupancy : AD - All event=0xa0,umask=0x11  01    CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2p_txr_horz_occupancy.ad_crd uncore io CMS Horizontal Egress Occupancy : AD - Credited event=0xa0,umask=0x10  01    CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_occupancy.ad_uncrd uncore io CMS Horizontal Egress Occupancy : AD - Uncredited event=0xa0,umask=1  01    CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_occupancy.ak uncore io CMS Horizontal Egress Occupancy : AK event=0xa0,umask=2  01    CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_occupancy.akc_uncrd uncore io CMS Horizontal Egress Occupancy : AKC - Uncredited event=0xa0,umask=0x80  01    CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_occupancy.bl_all uncore io CMS Horizontal Egress Occupancy : BL - All event=0xa0,umask=0x44  01    CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited unc_m2p_txr_horz_occupancy.bl_crd uncore io CMS Horizontal Egress Occupancy : BL - Credited event=0xa0,umask=0x40  01    CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_occupancy.bl_uncrd uncore io CMS Horizontal Egress Occupancy : BL - Uncredited event=0xa0,umask=4  01    CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_occupancy.iv uncore io CMS Horizontal Egress Occupancy : IV event=0xa0,umask=8  01    CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh unc_m2p_txr_horz_starved.ad_all uncore io CMS Horizontal Egress Injection Starvation : AD - All event=0xa5,umask=1  01    CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited unc_m2p_txr_horz_starved.ad_uncrd uncore io CMS Horizontal Egress Injection Starvation : AD - Uncredited event=0xa5,umask=1  01    CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2p_txr_horz_starved.ak uncore io CMS Horizontal Egress Injection Starvation : AK event=0xa5,umask=2  01    CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2p_txr_horz_starved.akc_uncrd uncore io CMS Horizontal Egress Injection Starvation : AKC - Uncredited event=0xa5,umask=0x80  01    CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2p_txr_horz_starved.bl_all uncore io CMS Horizontal Egress Injection Starvation : BL - All event=0xa5,umask=4  01    CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited unc_m2p_txr_horz_starved.bl_uncrd uncore io CMS Horizontal Egress Injection Starvation : BL - Uncredited event=0xa5,umask=4  01    CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2p_txr_horz_starved.iv uncore io CMS Horizontal Egress Injection Starvation : IV event=0xa5,umask=8  01    CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time unc_m2p_txr_vert_ads_used.ad_ag0 uncore io CMS Vertical ADS Used : AD - Agent 0 event=0x9c,umask=1  01    CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2p_txr_vert_ads_used.ad_ag1 uncore io CMS Vertical ADS Used : AD - Agent 1 event=0x9c,umask=0x10  01    CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2p_txr_vert_ads_used.bl_ag0 uncore io CMS Vertical ADS Used : BL - Agent 0 event=0x9c,umask=4  01    CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2p_txr_vert_ads_used.bl_ag1 uncore io CMS Vertical ADS Used : BL - Agent 1 event=0x9c,umask=0x40  01    CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent unc_m2p_txr_vert_bypass.ad_ag0 uncore io CMS Vertical ADS Used : AD - Agent 0 event=0x9d,umask=1  01    CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2p_txr_vert_bypass.ad_ag1 uncore io CMS Vertical ADS Used : AD - Agent 1 event=0x9d,umask=0x10  01    CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2p_txr_vert_bypass.ak_ag0 uncore io CMS Vertical ADS Used : AK - Agent 0 event=0x9d,umask=2  01    CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2p_txr_vert_bypass.ak_ag1 uncore io CMS Vertical ADS Used : AK - Agent 1 event=0x9d,umask=0x20  01    CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2p_txr_vert_bypass.bl_ag0 uncore io CMS Vertical ADS Used : BL - Agent 0 event=0x9d,umask=4  01    CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2p_txr_vert_bypass.bl_ag1 uncore io CMS Vertical ADS Used : BL - Agent 1 event=0x9d,umask=0x40  01    CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2p_txr_vert_bypass.iv_ag1 uncore io CMS Vertical ADS Used : IV - Agent 1 event=0x9d,umask=8  01    CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2p_txr_vert_bypass_1.akc_ag0 uncore io CMS Vertical ADS Used : AKC - Agent 0 event=0x9e,umask=1  01    CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2p_txr_vert_bypass_1.akc_ag1 uncore io CMS Vertical ADS Used : AKC - Agent 1 event=0x9e,umask=2  01    CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent unc_m2p_txr_vert_cycles_full0.ad_ag0 uncore io Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 event=0x94,umask=1  01    Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_m2p_txr_vert_cycles_full0.ad_ag1 uncore io Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 event=0x94,umask=0x10  01    Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests unc_m2p_txr_vert_cycles_full0.ak_ag0 uncore io Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 event=0x94,umask=2  01    Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_m2p_txr_vert_cycles_full0.ak_ag1 uncore io Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 event=0x94,umask=0x20  01    Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m2p_txr_vert_cycles_full0.bl_ag0 uncore io Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 event=0x94,umask=4  01    Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations unc_m2p_txr_vert_cycles_full0.bl_ag1 uncore io Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 event=0x94,umask=0x40  01    Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache unc_m2p_txr_vert_cycles_full0.iv_ag0 uncore io Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 event=0x94,umask=8  01    Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores unc_m2p_txr_vert_cycles_full1.akc_ag0 uncore io Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 event=0x95,umask=1  01    Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_m2p_txr_vert_cycles_full1.akc_ag1 uncore io Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 event=0x95,umask=2  01    Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_m2p_txr_vert_cycles_ne0.ad_ag0 uncore io Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 event=0x96,umask=1  01    Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_m2p_txr_vert_cycles_ne0.ad_ag1 uncore io Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 event=0x96,umask=0x10  01    Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests unc_m2p_txr_vert_cycles_ne0.ak_ag0 uncore io Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 event=0x96,umask=2  01    Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_m2p_txr_vert_cycles_ne0.ak_ag1 uncore io Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 event=0x96,umask=0x20  01    Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m2p_txr_vert_cycles_ne0.bl_ag0 uncore io Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 event=0x96,umask=4  01    Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations unc_m2p_txr_vert_cycles_ne0.bl_ag1 uncore io Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 event=0x96,umask=0x40  01    Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache unc_m2p_txr_vert_cycles_ne0.iv_ag0 uncore io Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 event=0x96,umask=8  01    Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores unc_m2p_txr_vert_cycles_ne1.akc_ag0 uncore io Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 event=0x97,umask=1  01    Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_m2p_txr_vert_cycles_ne1.akc_ag1 uncore io Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 event=0x97,umask=2  01    Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_m2p_txr_vert_inserts0.ad_ag0 uncore io CMS Vert Egress Allocations : AD - Agent 0 event=0x92,umask=1  01    CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_m2p_txr_vert_inserts0.ad_ag1 uncore io CMS Vert Egress Allocations : AD - Agent 1 event=0x92,umask=0x10  01    CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests unc_m2p_txr_vert_inserts0.ak_ag0 uncore io CMS Vert Egress Allocations : AK - Agent 0 event=0x92,umask=2  01    CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_m2p_txr_vert_inserts0.ak_ag1 uncore io CMS Vert Egress Allocations : AK - Agent 1 event=0x92,umask=0x20  01    CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m2p_txr_vert_inserts0.bl_ag0 uncore io CMS Vert Egress Allocations : BL - Agent 0 event=0x92,umask=4  01    CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations unc_m2p_txr_vert_inserts0.bl_ag1 uncore io CMS Vert Egress Allocations : BL - Agent 1 event=0x92,umask=0x40  01    CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache unc_m2p_txr_vert_inserts0.iv_ag0 uncore io CMS Vert Egress Allocations : IV - Agent 0 event=0x92,umask=8  01    CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores unc_m2p_txr_vert_inserts1.akc_ag0 uncore io CMS Vert Egress Allocations : AKC - Agent 0 event=0x93,umask=1  01    CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_m2p_txr_vert_inserts1.akc_ag1 uncore io CMS Vert Egress Allocations : AKC - Agent 1 event=0x93,umask=2  01    CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_m2p_txr_vert_nack0.ad_ag0 uncore io CMS Vertical Egress NACKs : AD - Agent 0 event=0x98,umask=1  01    CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2p_txr_vert_nack0.ad_ag1 uncore io CMS Vertical Egress NACKs : AD - Agent 1 event=0x98,umask=0x10  01    CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2p_txr_vert_nack0.ak_ag0 uncore io CMS Vertical Egress NACKs : AK - Agent 0 event=0x98,umask=2  01    CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2p_txr_vert_nack0.ak_ag1 uncore io CMS Vertical Egress NACKs : AK - Agent 1 event=0x98,umask=0x20  01    CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2p_txr_vert_nack0.bl_ag0 uncore io CMS Vertical Egress NACKs : BL - Agent 0 event=0x98,umask=4  01    CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2p_txr_vert_nack0.bl_ag1 uncore io CMS Vertical Egress NACKs : BL - Agent 1 event=0x98,umask=0x40  01    CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2p_txr_vert_nack0.iv_ag0 uncore io CMS Vertical Egress NACKs : IV event=0x98,umask=8  01    CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2p_txr_vert_nack1.akc_ag0 uncore io CMS Vertical Egress NACKs : AKC - Agent 0 event=0x99,umask=1  01    CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2p_txr_vert_nack1.akc_ag1 uncore io CMS Vertical Egress NACKs : AKC - Agent 1 event=0x99,umask=2  01    CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring unc_m2p_txr_vert_occupancy0.ad_ag0 uncore io CMS Vert Egress Occupancy : AD - Agent 0 event=0x90,umask=1  01    CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_m2p_txr_vert_occupancy0.ad_ag1 uncore io CMS Vert Egress Occupancy : AD - Agent 1 event=0x90,umask=0x10  01    CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests unc_m2p_txr_vert_occupancy0.ak_ag0 uncore io CMS Vert Egress Occupancy : AK - Agent 0 event=0x90,umask=2  01    CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_m2p_txr_vert_occupancy0.ak_ag1 uncore io CMS Vert Egress Occupancy : AK - Agent 1 event=0x90,umask=0x20  01    CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring unc_m2p_txr_vert_occupancy0.bl_ag0 uncore io CMS Vert Egress Occupancy : BL - Agent 0 event=0x90,umask=4  01    CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations unc_m2p_txr_vert_occupancy0.bl_ag1 uncore io CMS Vert Egress Occupancy : BL - Agent 1 event=0x90,umask=0x40  01    CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache unc_m2p_txr_vert_occupancy0.iv_ag0 uncore io CMS Vert Egress Occupancy : IV - Agent 0 event=0x90,umask=8  01    CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores unc_m2p_txr_vert_occupancy1.akc_ag0 uncore io CMS Vert Egress Occupancy : AKC - Agent 0 event=0x91,umask=1  01    CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses unc_m2p_txr_vert_occupancy1.akc_ag1 uncore io CMS Vert Egress Occupancy : AKC - Agent 1 event=0x91,umask=2  01    CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses unc_m2p_txr_vert_starved0.ad_ag0 uncore io CMS Vertical Egress Injection Starvation : AD - Agent 0 event=0x9a,umask=1  01    CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2p_txr_vert_starved0.ad_ag1 uncore io CMS Vertical Egress Injection Starvation : AD - Agent 1 event=0x9a,umask=0x10  01    CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2p_txr_vert_starved0.ak_ag0 uncore io CMS Vertical Egress Injection Starvation : AK - Agent 0 event=0x9a,umask=2  01    CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2p_txr_vert_starved0.ak_ag1 uncore io CMS Vertical Egress Injection Starvation : AK - Agent 1 event=0x9a,umask=0x20  01    CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2p_txr_vert_starved0.bl_ag0 uncore io CMS Vertical Egress Injection Starvation : BL - Agent 0 event=0x9a,umask=4  01    CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2p_txr_vert_starved0.bl_ag1 uncore io CMS Vertical Egress Injection Starvation : BL - Agent 1 event=0x9a,umask=0x40  01    CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2p_txr_vert_starved0.iv_ag0 uncore io CMS Vertical Egress Injection Starvation : IV event=0x9a,umask=8  01    CMS Vertical Egress Injection Starvation : IV : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2p_txr_vert_starved1.akc_ag0 uncore io CMS Vertical Egress Injection Starvation : AKC - Agent 0 event=0x9b,umask=1  01    CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2p_txr_vert_starved1.akc_ag1 uncore io CMS Vertical Egress Injection Starvation : AKC - Agent 1 event=0x9b,umask=2  01    CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2p_txr_vert_starved1.tgc uncore io CMS Vertical Egress Injection Starvation : AKC - Agent 0 event=0x9b,umask=4  01    CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time unc_m2p_vert_ring_ad_in_use.dn_even uncore io Vertical AD Ring In Use : Down and Even event=0xb0,umask=4  01    Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_ad_in_use.dn_odd uncore io Vertical AD Ring In Use : Down and Odd event=0xb0,umask=8  01    Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_ad_in_use.up_even uncore io Vertical AD Ring In Use : Up and Even event=0xb0,umask=1  01    Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_ad_in_use.up_odd uncore io Vertical AD Ring In Use : Up and Odd event=0xb0,umask=2  01    Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_akc_in_use.dn_even uncore io Vertical AKC Ring In Use : Down and Even event=0xb4,umask=4  01    Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_akc_in_use.dn_odd uncore io Vertical AKC Ring In Use : Down and Odd event=0xb4,umask=8  01    Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_akc_in_use.up_even uncore io Vertical AKC Ring In Use : Up and Even event=0xb4,umask=1  01    Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_akc_in_use.up_odd uncore io Vertical AKC Ring In Use : Up and Odd event=0xb4,umask=2  01    Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_ak_in_use.dn_even uncore io Vertical AK Ring In Use : Down and Even event=0xb1,umask=4  01    Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_ak_in_use.dn_odd uncore io Vertical AK Ring In Use : Down and Odd event=0xb1,umask=8  01    Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_ak_in_use.up_even uncore io Vertical AK Ring In Use : Up and Even event=0xb1,umask=1  01    Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_ak_in_use.up_odd uncore io Vertical AK Ring In Use : Up and Odd event=0xb1,umask=2  01    Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_bl_in_use.dn_even uncore io Vertical BL Ring in Use : Down and Even event=0xb2,umask=4  01    Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_bl_in_use.dn_odd uncore io Vertical BL Ring in Use : Down and Odd event=0xb2,umask=8  01    Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_bl_in_use.up_even uncore io Vertical BL Ring in Use : Up and Even event=0xb2,umask=1  01    Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_bl_in_use.up_odd uncore io Vertical BL Ring in Use : Up and Odd event=0xb2,umask=2  01    Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_iv_in_use.dn uncore io Vertical IV Ring in Use : Down event=0xb3,umask=4  01    Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2p_vert_ring_iv_in_use.up uncore io Vertical IV Ring in Use : Up event=0xb3,umask=1  01    Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD unc_m2p_vert_ring_tgc_in_use.dn_even uncore io Vertical TGC Ring In Use : Down and Even event=0xb5,umask=4  01    Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_tgc_in_use.dn_odd uncore io Vertical TGC Ring In Use : Down and Odd event=0xb5,umask=8  01    Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_tgc_in_use.up_even uncore io Vertical TGC Ring In Use : Up and Even event=0xb5,umask=1  01    Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m2p_vert_ring_tgc_in_use.up_odd uncore io Vertical TGC Ring In Use : Up and Odd event=0xb5,umask=2  01    Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_m_act_count.all uncore memory DRAM Activate Count : All Activates event=1,umask=0xb  01    DRAM Activate Count : All Activates : Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_m_act_count.byp uncore memory DRAM Activate Count : Activate due to Bypass event=1,umask=8  01    DRAM Activate Count : Activate due to Bypass : Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_m_cas_count.all uncore memory All DRAM CAS commands issued event=4,umask=0x3f  01    Counts the total number of DRAM CAS commands issued on this channel unc_m_cas_count.rd uncore memory All DRAM read CAS commands issued (including underfills) event=4,umask=0xf  01    Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issued on this channel.  This includes underfills unc_m_cas_count.rd_pre_reg uncore memory DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre event=4,umask=2  01    DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre : DRAM RD_CAS and WR_CAS Commands : Counts the total number or DRAM Read CAS commands issued on this channel.  This includes both regular RD CAS commands as well as those with explicit Precharge.  AutoPre is only used in systems that are using closed page policy.  We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills) unc_m_cas_count.rd_pre_underfill uncore memory DRAM RD_CAS and WR_CAS Commands event=4,umask=8  01    DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands unc_m_cas_count.rd_reg uncore memory All DRAM read CAS commands issued (does not include underfills) event=4,umask=1  01    Counts the total number of DRAM Read CAS commands issued on this channel.  This includes both regular RD CAS commands as well as those with implicit Precharge.   We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills) unc_m_cas_count.rd_underfill uncore memory DRAM underfill read CAS commands issued event=4,umask=4  01    Counts the total of DRAM Read CAS commands issued due to an underfill unc_m_cas_count.wr uncore memory All DRAM write CAS commands issued event=4,umask=0x30  01    Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-pre, on this channel unc_m_cas_count.wr_nonpre uncore memory DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre event=4,umask=0x10  01    DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre : DRAM RD_CAS and WR_CAS Commands unc_m_cas_count.wr_pre uncore memory DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre event=4,umask=0x20  01    DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre : DRAM RD_CAS and WR_CAS Commands unc_m_clockticks_freerun uncore memory Free running counter that increments for the Memory Controller event=0xff,umask=0x10  01     unc_m_dram_pre_all uncore memory DRAM Precharge All Commands event=0x44  01    DRAM Precharge All Commands : Counts the number of times that the precharge all command was sent unc_m_dram_refresh.high uncore memory Number of DRAM Refreshes Issued event=0x45,umask=4  01    Number of DRAM Refreshes Issued : Counts the number of refreshes issued unc_m_dram_refresh.opportunistic uncore memory Number of DRAM Refreshes Issued event=0x45,umask=1  01    Number of DRAM Refreshes Issued : Counts the number of refreshes issued unc_m_dram_refresh.panic uncore memory Number of DRAM Refreshes Issued event=0x45,umask=2  01    Number of DRAM Refreshes Issued : Counts the number of refreshes issued unc_m_hclockticks uncore memory Half clockticks for IMC event=0xff  01     unc_m_parity_errors uncore memory UNC_M_PARITY_ERRORS event=0x2c  01     unc_m_pcls.rd uncore memory UNC_M_PCLS.RD event=0xa0,umask=1  01     unc_m_pcls.total uncore memory UNC_M_PCLS.TOTAL event=0xa0,umask=4  01     unc_m_pcls.wr uncore memory UNC_M_PCLS.WR event=0xa0,umask=2  01     unc_m_pmm_cmd1.all uncore memory PMM Commands : All event=0xea,umask=1  01    PMM Commands : All : Counts all commands issued to PMM unc_m_pmm_cmd1.misc uncore memory PMM Commands : Misc Commands (error, flow ACKs) event=0xea,umask=0x80  01     unc_m_pmm_cmd1.misc_gnt uncore memory PMM Commands : Misc GNTs event=0xea,umask=0x40  01     unc_m_pmm_cmd1.rd uncore memory PMM Commands : Reads - RPQ event=0xea,umask=2  01    PMM Commands : Reads - RPQ : Counts read requests issued to the PMM RPQ unc_m_pmm_cmd1.rpq_gnts uncore memory PMM Commands : RPQ GNTs event=0xea,umask=0x10  01     unc_m_pmm_cmd1.ufill_rd uncore memory PMM Commands : Underfill reads event=0xea,umask=8  01    PMM Commands : Underfill reads : Counts underfill read commands, due to a partial write, issued to PMM unc_m_pmm_cmd1.wpq_gnts uncore memory PMM Commands : Underfill GNTs event=0xea,umask=0x20  01     unc_m_pmm_cmd1.wr uncore memory PMM Commands : Writes event=0xea,umask=4  01    PMM Commands : Writes : Counts write commands issued to PMM unc_m_pmm_cmd2.nodata_exp uncore memory PMM Commands - Part 2 : Expected No data packet (ERID matched NDP encoding) event=0xeb,umask=2  01     unc_m_pmm_cmd2.nodata_unexp uncore memory PMM Commands - Part 2 : Unexpected No data packet (ERID matched a Read, but data was a NDP) event=0xeb,umask=4  01     unc_m_pmm_cmd2.opp_rd uncore memory PMM Commands - Part 2 : Opportunistic Reads event=0xeb,umask=1  01     unc_m_pmm_cmd2.pmm_ecc_error uncore memory PMM Commands - Part 2 : ECC Errors event=0xeb,umask=0x20  01     unc_m_pmm_cmd2.pmm_erid_error uncore memory PMM Commands - Part 2 : ERID detectable parity error event=0xeb,umask=0x40  01     unc_m_pmm_cmd2.pmm_erid_starved uncore memory PMM Commands - Part 2 event=0xeb,umask=0x80  01     unc_m_pmm_cmd2.reqs_slot0 uncore memory PMM Commands - Part 2 : Read Requests - Slot 0 event=0xeb,umask=8  01     unc_m_pmm_cmd2.reqs_slot1 uncore memory PMM Commands - Part 2 : Read Requests - Slot 1 event=0xeb,umask=0x10  01     unc_m_pmm_rpq_inserts uncore memory PMM Read Queue Inserts event=0xe3  01    PMM Read Queue Inserts : Counts number of read requests allocated in the PMM Read Pending Queue.   This includes both ISOCH and non-ISOCH requests unc_m_pmm_rpq_occupancy.all uncore memory PMM Read Pending Queue Occupancy event=0xe0,umask=1  01    PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue unc_m_pmm_rpq_occupancy.gnt_wait uncore memory PMM Read Pending Queue Occupancy event=0xe0,umask=4  01    PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue unc_m_pmm_rpq_occupancy.no_gnt uncore memory PMM Read Pending Queue Occupancy event=0xe0,umask=2  01    PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue unc_m_pmm_wpq_flush uncore memory UNC_M_PMM_WPQ_FLUSH event=0xe8  01     unc_m_pmm_wpq_flush_cyc uncore memory UNC_M_PMM_WPQ_FLUSH_CYC event=0xe9  01     unc_m_pmm_wpq_inserts uncore memory PMM Write Queue Inserts event=0xe7  01    PMM Write Queue Inserts : Counts number of  write requests allocated in the PMM Write Pending Queue unc_m_pmm_wpq_occupancy.all uncore memory PMM Write Pending Queue Occupancy event=0xe4,umask=1  01    PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue unc_m_pmm_wpq_occupancy.cas uncore memory PMM Write Pending Queue Occupancy event=0xe4,umask=2  01    PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue unc_m_pmm_wpq_occupancy.pwr uncore memory PMM Write Pending Queue Occupancy event=0xe4,umask=4  01    PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue unc_m_pre_count.all uncore memory DRAM Precharge commands event=2,umask=0x1c  01    DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.page_miss uncore memory DRAM Precharge commands. : Precharge due to page miss event=2,umask=0xc  01    DRAM Precharge commands. : Precharge due to page miss : Counts the number of DRAM Precharge commands sent on this channel. : Pages Misses are due to precharges from bank scheduler (rd/wr requests) unc_m_pre_count.pgt uncore memory DRAM Precharge commands. : Precharge due to page table event=2,umask=0x10  01    DRAM Precharge commands. : Precharge due to page table : Counts the number of DRAM Precharge commands sent on this channel. : Precharges from Page Table unc_m_pre_count.rd uncore memory DRAM Precharge commands. : Precharge due to read event=2,umask=4  01    DRAM Precharge commands. : Precharge due to read : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from read bank scheduler unc_m_pre_count.wr uncore memory DRAM Precharge commands. : Precharge due to write event=2,umask=8  01    DRAM Precharge commands. : Precharge due to write : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from write bank scheduler unc_m_rdb_full uncore memory Read Data Buffer Full event=0x19  01     unc_m_rdb_inserts uncore memory Read Data Buffer Inserts event=0x17  01     unc_m_rdb_not_empty uncore memory Read Data Buffer Not Empty event=0x18  01     unc_m_rdb_occupancy uncore memory Read Data Buffer Occupancy event=0x1a  01     unc_m_rpq_cycles_full_pch0 uncore memory Read Pending Queue Full Cycles event=0x12  01    Read Pending Queue Full Cycles : Counts the number of cycles when the Read Pending Queue is full.  When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC.  This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead.  We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM.  This event only tracks non-ISOC queue entries unc_m_rpq_cycles_full_pch1 uncore memory Read Pending Queue Full Cycles event=0x15  01    Read Pending Queue Full Cycles : Counts the number of cycles when the Read Pending Queue is full.  When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC.  This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead.  We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM.  This event only tracks non-ISOC queue entries unc_m_rpq_cycles_ne.pch0 uncore memory Read Pending Queue Not Empty event=0x11,umask=1  01    Read Pending Queue Not Empty : Counts the number of cycles that the Read Pending Queue is not empty.  This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests unc_m_rpq_cycles_ne.pch1 uncore memory Read Pending Queue Not Empty event=0x11,umask=2  01    Read Pending Queue Not Empty : Counts the number of cycles that the Read Pending Queue is not empty.  This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests unc_m_sb_accesses.accepts uncore memory Scoreboard Accesses : Scoreboard Accesses Accepted event=0xd2,umask=5  01     unc_m_sb_accesses.fmrd_cmps uncore memory This event is deprecated event=0xd2,umask=0x40  11     unc_m_sb_accesses.fmwr_cmps uncore memory This event is deprecated event=0xd2,umask=0x80  11     unc_m_sb_accesses.nmrd_cmps uncore memory This event is deprecated event=0xd2,umask=0x10  11     unc_m_sb_accesses.nmwr_cmps uncore memory This event is deprecated event=0xd2,umask=0x20  11     unc_m_sb_accesses.rejects uncore memory Scoreboard Accesses : Scoreboard Accesses Rejected event=0xd2,umask=0xa  01     unc_m_sb_canary.fmrd_starved uncore memory This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_RD_STARVED event=0xd9,umask=0x20  11     unc_m_sb_canary.fmtgrwr_starved uncore memory This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_TGR_WR_STARVED event=0xd9,umask=0x80  11     unc_m_sb_canary.fmwr_starved uncore memory This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_WR_STARVED event=0xd9,umask=0x40  11     unc_m_sb_canary.nmrd_starved uncore memory This event is deprecated. Refer to new event UNC_M_SB_CANARY.NM_RD_STARVED event=0xd9,umask=8  11     unc_m_sb_canary.nmwr_starved uncore memory This event is deprecated. Refer to new event UNC_M_SB_CANARY.NM_WR_STARVED event=0xd9,umask=0x10  11     unc_m_sb_pref_inserts.pmm uncore memory Scoreboard Prefetch Inserts : Persistent Mem event=0xda,umask=4  01     unc_m_sb_pref_occupancy.pmem uncore memory This event is deprecated. Refer to new event UNC_M_SB_PREF_OCCUPANCY.PMM event=0xdb,umask=4  11     unc_m_sb_strv_alloc.fmrd uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_RD event=0xd7,umask=2  11     unc_m_sb_strv_alloc.fmtgr uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_TGR event=0xd7,umask=0x10  11     unc_m_sb_strv_alloc.fmwr uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_WR event=0xd7,umask=8  11     unc_m_sb_strv_alloc.nmrd uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.NM_RD event=0xd7,umask=1  11     unc_m_sb_strv_alloc.nmwr uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.NM_WR event=0xd7,umask=4  11     unc_m_sb_strv_dealloc.fmrd uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_RD event=0xde,umask=2  11     unc_m_sb_strv_dealloc.fmtgr uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_TGR event=0xde,umask=0x10  11     unc_m_sb_strv_dealloc.fmwr uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_WR event=0xde,umask=8  11     unc_m_sb_strv_dealloc.nmrd uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.NM_RD event=0xde,umask=1  11     unc_m_sb_strv_dealloc.nmwr uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.NM_WR event=0xde,umask=4  11     unc_m_sb_strv_occ.fmrd uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_RD event=0xd8,umask=2  11     unc_m_sb_strv_occ.fmtgr uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_TGR event=0xd8,umask=0x10  11     unc_m_sb_strv_occ.fmwr uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_WR event=0xd8,umask=8  11     unc_m_sb_strv_occ.nmrd uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.NM_RD event=0xd8,umask=1  11     unc_m_sb_strv_occ.nmwr uncore memory This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.NM_WR event=0xd8,umask=4  11     unc_m_tagchk.hit uncore memory 2LM Tag Check : Hit in Near Memory Cache event=0xd3,umask=1  01     unc_m_tagchk.miss_clean uncore memory 2LM Tag Check : Miss, no data in this line event=0xd3,umask=2  01     unc_m_tagchk.miss_dirty uncore memory 2LM Tag Check : Miss, existing data may be evicted to Far Memory event=0xd3,umask=4  01     unc_m_tagchk.nm_rd_hit uncore memory 2LM Tag Check : Read Hit in Near Memory Cache event=0xd3,umask=8  01     unc_m_tagchk.nm_wr_hit uncore memory 2LM Tag Check : Write Hit in Near Memory Cache event=0xd3,umask=0x10  01     unc_m_wpq_cycles_full_pch0 uncore memory Write Pending Queue Full Cycles event=0x22  01    Write Pending Queue Full Cycles : Counts the number of cycles when the Write Pending Queue is full.  When the WPQ is full, the HA will not be able to issue any additional write requests into the iMC.  This count should be similar count in the CHA which tracks the number of cycles that the CHA has no WPQ credits, just somewhat smaller to account for the credit return overhead unc_m_wpq_cycles_full_pch1 uncore memory Write Pending Queue Full Cycles event=0x16  01    Write Pending Queue Full Cycles : Counts the number of cycles when the Write Pending Queue is full.  When the WPQ is full, the HA will not be able to issue any additional write requests into the iMC.  This count should be similar count in the CHA which tracks the number of cycles that the CHA has no WPQ credits, just somewhat smaller to account for the credit return overhead unc_m_wpq_cycles_ne.pch0 uncore memory Write Pending Queue Not Empty event=0x21,umask=1  01    Write Pending Queue Not Empty : Counts the number of cycles that the Write Pending Queue is not empty.  This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies unc_m_wpq_cycles_ne.pch1 uncore memory Write Pending Queue Not Empty event=0x21,umask=2  01    Write Pending Queue Not Empty : Counts the number of cycles that the Write Pending Queue is not empty.  This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies unc_m_wpq_read_hit.pch0 uncore memory Write Pending Queue CAM Match event=0x23,umask=1  01    Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_m_wpq_read_hit.pch1 uncore memory Write Pending Queue CAM Match event=0x23,umask=2  01    Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_m_wpq_write_hit.pch0 uncore memory Write Pending Queue CAM Match event=0x24,umask=1  01    Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_m_wpq_write_hit.pch1 uncore memory Write Pending Queue CAM Match event=0x24,umask=2  01    Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections unc_p_clockticks uncore power Clockticks of the power control unit (PCU) event=0  01    Clockticks of the power control unit (PCU) : The PCU runs off a fixed 1 GHz clock.  This event counts the number of pclk cycles measured while the counter was enabled.  The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time unc_p_pkg_residency_c3_cycles uncore power Package C State Residency - C3 event=0x2c  01    Package C State Residency - C3 : Counts the number of cycles when the package was in C3.  This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert).  Residency events do not include transition times unc_p_power_state_occupancy.cores_c0 uncore power Number of cores in C-State : C0 and C1 event=0x80,umask=0x40  01    Number of cores in C-State : C0 and C1 : This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_power_state_occupancy.cores_c3 uncore power Number of cores in C-State : C3 event=0x80,umask=0x80  01    Number of cores in C-State : C3 : This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_power_state_occupancy.cores_c6 uncore power Number of cores in C-State : C6 and C7 event=0x80,umask=0xc0  01    Number of cores in C-State : C6 and C7 : This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details l1d.replacement cache L1D data line replacements event=0x51,period=2000003,umask=1  00    Counts the number of lines brought into the L1 data cache l2_l1d_wb_rqsts.all cache Not rejected writebacks from L1D to L2 cache lines in any state event=0x28,period=200003,umask=0xf  00     l2_l1d_wb_rqsts.hit_e cache Not rejected writebacks from L1D to L2 cache lines in E state event=0x28,period=200003,umask=4  00     l2_l1d_wb_rqsts.hit_m cache Not rejected writebacks from L1D to L2 cache lines in M state event=0x28,period=200003,umask=8  00     l2_l1d_wb_rqsts.miss cache Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.) event=0x28,period=200003,umask=1  00    Not rejected writebacks that missed LLC l2_lines_in.all cache L2 cache lines filling L2 event=0xf1,period=100003,umask=7  00     l2_lines_out.demand_clean cache Clean L2 cache lines evicted by demand event=0xf2,period=100003,umask=1  00     l2_lines_out.demand_dirty cache Dirty L2 cache lines evicted by demand event=0xf2,period=100003,umask=2  00     l2_lines_out.dirty_all cache Dirty L2 cache lines filling the L2 event=0xf2,period=100003,umask=0xa  00     l2_lines_out.pf_clean cache Clean L2 cache lines evicted by L2 prefetch event=0xf2,period=100003,umask=4  00    Clean L2 cache lines evicted by the MLC prefetcher l2_lines_out.pf_dirty cache Dirty L2 cache lines evicted by L2 prefetch event=0xf2,period=100003,umask=8  00    Dirty L2 cache lines evicted by the MLC prefetcher l2_rqsts.all_code_rd cache L2 code requests event=0x24,period=200003,umask=0x30  00    Counts all L2 code requests l2_rqsts.all_demand_data_rd cache Demand Data Read requests event=0x24,period=200003,umask=3  00    Counts any demand and L1 HW prefetch data load requests to L2 l2_rqsts.all_pf cache Requests from L2 hardware prefetchers event=0x24,period=200003,umask=0xc0  00    Counts all L2 HW prefetcher requests l2_rqsts.all_rfo cache RFO requests to L2 cache event=0x24,period=200003,umask=0xc  00    Counts all L2 store RFO requests l2_rqsts.code_rd_hit cache L2 cache hits when fetching instructions, code reads event=0x24,period=200003,umask=0x10  00    Number of instruction fetches that hit the L2 cache l2_rqsts.code_rd_miss cache L2 cache misses when fetching instructions event=0x24,period=200003,umask=0x20  00    Number of instruction fetches that missed the L2 cache l2_rqsts.demand_data_rd_hit cache Demand Data Read requests that hit L2 cache event=0x24,period=200003,umask=1  00     l2_rqsts.pf_hit cache Requests from the L2 hardware prefetchers that hit L2 cache event=0x24,period=200003,umask=0x40  00    Counts all L2 HW prefetcher requests that hit L2 l2_rqsts.pf_miss cache Requests from the L2 hardware prefetchers that miss L2 cache event=0x24,period=200003,umask=0x80  00    Counts all L2 HW prefetcher requests that missed L2 l2_rqsts.rfo_hit cache RFO requests that hit L2 cache event=0x24,period=200003,umask=4  00     l2_rqsts.rfo_miss cache RFO requests that miss L2 cache event=0x24,period=200003,umask=8  00    Counts the number of store RFO requests that miss the L2 cache l2_store_lock_rqsts.all cache RFOs that access cache lines in any state event=0x27,period=200003,umask=0xf  00     l2_store_lock_rqsts.hit_m cache RFOs that hit cache lines in M state event=0x27,period=200003,umask=8  00     l2_store_lock_rqsts.miss cache RFOs that miss cache lines event=0x27,period=200003,umask=1  00     l2_trans.all_pf cache L2 or LLC HW prefetches that access L2 cache event=0xf0,period=200003,umask=8  00    Any MLC or LLC HW prefetch accessing L2, including rejects l2_trans.demand_data_rd cache Demand Data Read requests that access L2 cache event=0xf0,period=200003,umask=1  00     longest_lat_cache.miss cache Core-originated cacheable demand requests missed LLC event=0x2e,period=100003,umask=0x41  00    This event counts each cache miss condition for references to the last level cache longest_lat_cache.reference cache Core-originated cacheable demand requests that refer to LLC event=0x2e,period=100003,umask=0x4f  00    This event counts requests originating from the core that reference a cache line in the last level cache mem_load_uops_llc_hit_retired.xsnp_hit cache Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache (Precise event) event=0xd2,period=20011,umask=2  00     mem_load_uops_llc_hit_retired.xsnp_hitm cache Retired load uops which data sources were HitM responses from shared LLC (Precise event) event=0xd2,period=20011,umask=4  00     mem_load_uops_llc_hit_retired.xsnp_miss cache Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache (Precise event) event=0xd2,period=20011,umask=1  00     mem_load_uops_llc_hit_retired.xsnp_none cache Retired load uops which data sources were hits in LLC without snoops required (Precise event) event=0xd2,period=100003,umask=8  00     mem_load_uops_llc_miss_retired.local_dram cache Retired load uops which data sources missed LLC but serviced from local dram event=0xd3,period=100007,umask=1  00    Retired load uops whose data source was local memory (cross-socket snoop not needed or missed) mem_load_uops_retired.hit_lfb cache Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready (Precise event) event=0xd1,period=100003,umask=0x40  00     mem_load_uops_retired.l1_hit cache Retired load uops with L1 cache hits as data sources (Precise event) event=0xd1,period=2000003,umask=1  00     mem_load_uops_retired.l1_miss cache Retired load uops which data sources following L1 data-cache miss (Precise event) event=0xd1,period=100003,umask=8  00     mem_load_uops_retired.l2_hit cache Retired load uops with L2 cache hits as data sources (Precise event) event=0xd1,period=100003,umask=2  00     mem_load_uops_retired.l2_miss cache Retired load uops with L2 cache misses as data sources (Precise event) event=0xd1,period=50021,umask=0x10  00     mem_load_uops_retired.llc_hit cache Retired load uops which data sources were data hits in LLC without snoops required (Precise event) event=0xd1,period=50021,umask=4  00     mem_load_uops_retired.llc_miss cache Miss in last-level (L3) cache. Excludes Unknown data-source (Precise event) event=0xd1,period=100007,umask=0x20  00     mem_uops_retired.all_loads cache All retired load uops. (Precise Event) event=0xd0,period=2000003,umask=0x81  00     mem_uops_retired.all_stores cache All retired store uops. (Precise Event) event=0xd0,period=2000003,umask=0x82  00     mem_uops_retired.lock_loads cache Retired load uops with locked access. (Precise Event) event=0xd0,period=100007,umask=0x21  00     mem_uops_retired.split_loads cache Retired load uops that split across a cacheline boundary. (Precise Event) event=0xd0,period=100003,umask=0x41  00     mem_uops_retired.split_stores cache Retired store uops that split across a cacheline boundary. (Precise Event) event=0xd0,period=100003,umask=0x42  00     mem_uops_retired.stlb_miss_loads cache Retired load uops that miss the STLB. (Precise Event) event=0xd0,period=100003,umask=0x11  00     mem_uops_retired.stlb_miss_stores cache Retired store uops that miss the STLB. (Precise Event) event=0xd0,period=100003,umask=0x12  00     offcore_requests.demand_data_rd cache Demand Data Read requests sent to uncore event=0xb0,period=100003,umask=1  00    Demand data read requests sent to uncore offcore_requests_buffer.sq_full cache Cases when offcore requests buffer cannot take more entries for core event=0xb2,period=2000003,umask=1  00     offcore_requests_outstanding.all_data_rd cache Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore event=0x60,period=2000003,umask=8  00    Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles offcore_requests_outstanding.cycles_with_data_rd cache Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore event=0x60,cmask=1,period=2000003,umask=8  00     offcore_requests_outstanding.cycles_with_demand_code_rd cache Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle event=0x60,cmask=1,period=2000003,umask=2  00     offcore_requests_outstanding.cycles_with_demand_data_rd cache Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore event=0x60,cmask=1,period=2000003,umask=1  00     offcore_requests_outstanding.cycles_with_demand_rfo cache Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle event=0x60,cmask=1,period=2000003,umask=4  00     offcore_requests_outstanding.demand_code_rd cache Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle event=0x60,period=2000003,umask=2  00    Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles offcore_requests_outstanding.demand_data_rd cache Offcore outstanding Demand Data Read transactions in uncore queue event=0x60,period=2000003,umask=1  00    Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles offcore_requests_outstanding.demand_rfo cache Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore event=0x60,period=2000003,umask=4  00    Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles offcore_response.all_code_rd.llc_hit.any_response cache Counts all demand & prefetch code reads that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0244  00     offcore_response.all_code_rd.llc_hit.no_snoop_needed cache Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c0244  00     offcore_response.all_data_rd.any_response cache Counts all demand & prefetch data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x000105B3  00     offcore_response.all_data_rd.llc_hit.any_response cache Counts all demand & prefetch data reads that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0091  00     offcore_response.all_data_rd.llc_hit.hitm_other_core cache Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c0091  00     offcore_response.all_data_rd.llc_hit.hit_other_core_no_fwd cache Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003c0091  00     offcore_response.all_data_rd.llc_hit.no_snoop_needed cache Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c0091  00     offcore_response.all_reads.any_response cache Counts all data/code/rfo references (demand & prefetch) event=0xb7,period=100003,umask=1,offcore_rsp=0x000107F7  00     offcore_response.all_rfo.any_response cache Counts all demand & prefetch prefetch RFOs event=0xb7,period=100003,umask=1,offcore_rsp=0x00010122  00     offcore_response.all_rfo.llc_hit.any_response cache Counts all demand & prefetch RFOs that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0122  00     offcore_response.all_rfo.llc_hit.no_snoop_needed cache Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c0122  00     offcore_response.corewb.any_response cache Counts all writebacks from the core to the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x10008  00     offcore_response.demand_code_rd.any_response cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x00010004  00     offcore_response.demand_code_rd.llc_hit.any_response cache Counts all demand code reads that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0004  00     offcore_response.demand_code_rd.llc_hit.no_snoop_needed cache Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c0004  00     offcore_response.demand_data_rd.any_response cache Counts all demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x00010001  00     offcore_response.demand_data_rd.llc_hit.any_response cache Counts all demand data reads that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0001  00     offcore_response.demand_data_rd.llc_hit.hitm_other_core cache Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c0001  00     offcore_response.demand_data_rd.llc_hit.hit_other_core_no_fwd cache Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003c0001  00     offcore_response.demand_data_rd.llc_hit.no_snoop_needed cache Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c0001  00     offcore_response.demand_rfo.any_response cache Counts all demand rfo's event=0xb7,period=100003,umask=1,offcore_rsp=0x00010002  00     offcore_response.demand_rfo.llc_hit.any_response cache Counts all demand data writes (RFOs) that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0002  00     offcore_response.demand_rfo.llc_hit.hitm_other_core cache Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c0002  00     offcore_response.demand_rfo.llc_hit.no_snoop_needed cache Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c0002  00     offcore_response.other.any_response cache Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches event=0xb7,period=100003,umask=1,offcore_rsp=0x18000  00     offcore_response.split_lock_uc_lock.any_response cache Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address event=0xb7,period=100003,umask=1,offcore_rsp=0x10400  00     offcore_response.streaming_stores.any_response cache Counts non-temporal stores event=0xb7,period=100003,umask=1,offcore_rsp=0x10800  00     fp_comp_ops_exe.sse_packed_double floating point Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle event=0x10,period=2000003,umask=0x10  00     fp_comp_ops_exe.sse_packed_single floating point Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle event=0x10,period=2000003,umask=0x40  00     fp_comp_ops_exe.sse_scalar_double floating point Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle event=0x10,period=2000003,umask=0x80  00    Counts number of SSE* or AVX-128 double precision FP scalar uops executed fp_comp_ops_exe.sse_scalar_single floating point Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle event=0x10,period=2000003,umask=0x20  00     fp_comp_ops_exe.x87 floating point Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULs and IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s event=0x10,period=2000003,umask=1  00    Counts number of X87 uops executed other_assists.avx_store floating point Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations event=0xc1,period=100003,umask=8  00    Number of assists associated with 256-bit AVX store operations other_assists.avx_to_sse floating point Number of transitions from AVX-256 to legacy SSE when penalty applicable event=0xc1,period=100003,umask=0x10  00     other_assists.sse_to_avx floating point Number of transitions from SSE to AVX-256 when penalty applicable event=0xc1,period=100003,umask=0x20  00     simd_fp_256.packed_double floating point number of AVX-256 Computational FP double precision uops issued this cycle event=0x11,period=2000003,umask=2  00    Counts 256-bit packed double-precision floating-point instructions simd_fp_256.packed_single floating point number of GSSE-256 Computational FP single precision uops issued this cycle event=0x11,period=2000003,umask=1  00    Counts 256-bit packed single-precision floating-point instructions dsb2mite_switches.count frontend Decode Stream Buffer (DSB)-to-MITE switches event=0xab,period=2000003,umask=1  00    Number of DSB to MITE switches dsb2mite_switches.penalty_cycles frontend Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles event=0xab,period=2000003,umask=2  00    Cycles DSB to MITE switches caused delay dsb_fill.exceed_dsb_lines frontend Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines event=0xac,period=2000003,umask=8  00    DSB Fill encountered > 3 DSB lines icache.ifetch_stall frontend Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss event=0x80,period=2000003,umask=4  00     icache.misses frontend Instruction cache, streaming buffer and victim cache misses event=0x80,period=200003,umask=2  00    Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses idq.all_mite_cycles_any_uops frontend Cycles MITE is delivering any Uop event=0x79,cmask=1,period=2000003,umask=0x24  00    Counts cycles MITE is delivered at least one uops. Set Cmask = 1 idq.empty frontend Instruction Decode Queue (IDQ) empty cycles event=0x79,period=2000003,umask=2  00    Counts cycles the IDQ is empty idq.ms_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,period=2000003,umask=0x30  00     idq.ms_uops frontend Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x30  00    Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles idq_uops_not_delivered.core frontend Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled event=0x9c,period=2000003,umask=1  00    Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall idq_uops_not_delivered.cycles_0_uops_deliv.core frontend Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled event=0x9c,cmask=4,period=2000003,umask=1  00     idq_uops_not_delivered.cycles_le_1_uop_deliv.core frontend Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled event=0x9c,cmask=3,period=2000003,umask=1  00     machine_clears.memory_ordering memory Counts the number of machine clears due to memory order conflicts event=0xc3,period=100003,umask=2  00     mem_trans_retired.load_latency_gt_128 memory Loads with latency value being above 128 (Must be precise) event=0xcd,period=1009,umask=1,ldlat=0x80  00     mem_trans_retired.load_latency_gt_16 memory Loads with latency value being above 16 (Must be precise) event=0xcd,period=20011,umask=1,ldlat=0x10  00     mem_trans_retired.load_latency_gt_256 memory Loads with latency value being above 256 (Must be precise) event=0xcd,period=503,umask=1,ldlat=0x100  00     mem_trans_retired.load_latency_gt_32 memory Loads with latency value being above 32 (Must be precise) event=0xcd,period=100007,umask=1,ldlat=0x20  00     mem_trans_retired.load_latency_gt_4 memory Loads with latency value being above 4 (Must be precise) event=0xcd,period=100003,umask=1,ldlat=0x4  00     mem_trans_retired.load_latency_gt_512 memory Loads with latency value being above 512 (Must be precise) event=0xcd,period=101,umask=1,ldlat=0x200  00     mem_trans_retired.load_latency_gt_64 memory Loads with latency value being above 64 (Must be precise) event=0xcd,period=2003,umask=1,ldlat=0x40  00     mem_trans_retired.load_latency_gt_8 memory Loads with latency value being above 8 (Must be precise) event=0xcd,period=50021,umask=1,ldlat=0x8  00     mem_trans_retired.precise_store memory Sample stores and collect precise store operation via PEBS record. PMC3 only (Must be precise) event=0xcd,period=2000003,umask=2  00     misalign_mem_ref.stores memory Speculative cache line split STA uops dispatched to L1 cache event=5,period=2000003,umask=2  00    Speculative cache-line split Store-address uops dispatched to L1D offcore_response.all_code_rd.llc_miss.dram memory Counts all demand & prefetch code reads that miss the LLC  and the data returned from dram event=0xb7,period=100003,umask=1,offcore_rsp=0x300400244  00     offcore_response.all_data_rd.llc_miss.dram memory Counts all demand & prefetch data reads that miss the LLC  and the data returned from dram event=0xb7,period=100003,umask=1,offcore_rsp=0x300400091  00     offcore_response.all_reads.llc_miss.dram memory Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data returned from dram event=0xb7,period=100003,umask=1,offcore_rsp=0x3004003f7  00     offcore_response.data_in_socket.llc_miss.local_dram memory Counts LLC replacements event=0xb7,period=100003,umask=1,offcore_rsp=0x6004001b3  00     offcore_response.demand_code_rd.llc_miss.dram memory Counts demand code reads that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=1,offcore_rsp=0x300400004  00     offcore_response.demand_data_rd.llc_miss.dram memory Counts demand data reads that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=1,offcore_rsp=0x300400001  00     page_walks.llc_miss memory Number of any page walk that had a miss in LLC event=0xbe,period=100003,umask=1  00     cpl_cycles.ring0_trans other Number of intervals between processor halts while thread is in ring 0 event=0x5c,cmask=1,edge=1,period=100007,umask=1  00     arith.fpu_div pipeline Divide operations executed event=0x14,cmask=1,edge=1,period=100003,umask=4  00     arith.fpu_div_active pipeline Cycles when divider is busy executing divide operations event=0x14,period=2000003,umask=1  00    Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides br_inst_retired.conditional pipeline Conditional branch instructions retired (Precise event) event=0xc4,period=400009,umask=1  00     br_inst_retired.far_branch pipeline Far branch instructions retired event=0xc4,period=100007,umask=0x40  00    Number of far branches retired br_inst_retired.near_call pipeline Direct and indirect near call instructions retired (Precise event) event=0xc4,period=100007,umask=2  00     br_inst_retired.near_call_r3 pipeline Direct and indirect macro near call instructions retired (captured in ring 3) (Precise event) event=0xc4,period=100007,umask=2  00     br_inst_retired.near_return pipeline Return instructions retired (Precise event) event=0xc4,period=100007,umask=8  00     br_inst_retired.near_taken pipeline Taken branch instructions retired (Precise event) event=0xc4,period=400009,umask=0x20  00     br_misp_retired.all_branches_pebs pipeline Mispredicted macro branch instructions retired (Must be precise) event=0xc5,period=400009,umask=4  00     br_misp_retired.near_taken pipeline number of near branch instructions retired that were mispredicted and taken (Precise event) event=0xc5,period=400009,umask=0x20  00     cpu_clk_thread_unhalted.one_thread_active pipeline Count XClk pulses when this thread is unhalted and the other is halted event=0x3c,period=2000003,umask=2  00     cpu_clk_thread_unhalted.ref_xclk pipeline Reference cycles when the thread is unhalted (counts at 100 MHz rate) event=0x3c,period=2000003,umask=1  00    Increments at the frequency of XCLK (100 MHz) when not halted cpu_clk_thread_unhalted.ref_xclk_any pipeline Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate) event=0x3c,any=1,period=2000003,umask=1  00     cpu_clk_unhalted.one_thread_active pipeline Count XClk pulses when this thread is unhalted and the other thread is halted event=0x3c,period=2000003,umask=2  00     cpu_clk_unhalted.ref_tsc pipeline Reference cycles when the core is not in halt state event=0,period=2000003,umask=3  00     cpu_clk_unhalted.ref_xclk pipeline Reference cycles when the thread is unhalted (counts at 100 MHz rate) event=0x3c,period=2000003,umask=1  00    Reference cycles when the thread is unhalted. (counts at 100 MHz rate) cpu_clk_unhalted.ref_xclk_any pipeline Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate) event=0x3c,any=1,period=2000003,umask=1  00     cpu_clk_unhalted.thread pipeline Core cycles when the thread is not in halt state event=0x3c,period=2000003  00     cycle_activity.cycles_l1d_pending pipeline Cycles with pending L1 cache miss loads event=0xa3,cmask=8,period=2000003,umask=8  00    Cycles with pending L1 cache miss loads. Set AnyThread to count per core cycle_activity.cycles_l2_miss pipeline Cycles while L2 cache miss load* is outstanding event=0xa3,cmask=1,period=2000003,umask=1  00     cycle_activity.cycles_l2_pending pipeline Cycles with pending L2 cache miss loads event=0xa3,cmask=1,period=2000003,umask=1  00    Cycles with pending L2 miss loads. Set AnyThread to count per core cycle_activity.cycles_ldm_pending pipeline Cycles with pending memory loads event=0xa3,cmask=2,period=2000003,umask=2  00    Cycles with pending memory loads. Set AnyThread to count per core cycle_activity.cycles_no_execute pipeline This event increments by 1 for every cycle where there was no execute for this thread event=0xa3,cmask=4,period=2000003,umask=4  00    Total execution stalls cycle_activity.stalls_l2_miss pipeline Execution stalls while L2 cache miss load* is outstanding event=0xa3,cmask=5,period=2000003,umask=5  00     cycle_activity.stalls_l2_pending pipeline Execution stalls due to L2 cache misses event=0xa3,cmask=5,period=2000003,umask=5  00    Number of loads missed L2 cycle_activity.stalls_ldm_pending pipeline Execution stalls due to memory subsystem event=0xa3,cmask=6,period=2000003,umask=6  00     ild_stall.lcp pipeline Stalls caused by changing prefix length of the instruction event=0x87,period=2000003,umask=1  00     inst_retired.any pipeline Instructions retired from execution event=0xc0,period=2000003  00     inst_retired.any_p pipeline Number of instructions retired. General Counter   - architectural event event=0xc0,period=2000003  00    Number of instructions at retirement inst_retired.prec_dist pipeline Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution (Must be precise) event=0xc0,period=2000003,umask=1  00     int_misc.recovery_cycles pipeline Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.) event=0xd,cmask=1,period=2000003,umask=3  00     int_misc.recovery_stalls_count pipeline Number of occurrences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.) event=0xd,cmask=1,edge=1,period=2000003,umask=3  00     ld_blocks.no_sr pipeline This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use event=3,period=100003,umask=8  00    The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use ld_blocks.store_forward pipeline Cases when loads get true Block-on-Store blocking code preventing store forwarding event=3,period=100003,umask=2  00    Loads blocked by overlapping with store buffer that cannot be forwarded ld_blocks_partial.address_alias pipeline False dependencies in MOB due to partial compare on address event=7,period=100003,umask=1  00     machine_clears.maskmov pipeline This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0 event=0xc3,period=100003,umask=0x20  00    Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0 machine_clears.smc pipeline Self-modifying code (SMC) detected event=0xc3,period=100003,umask=4  00    Number of self-modifying-code machine clears detected other_assists.any_wb_assist pipeline Number of times any microcode assist is invoked by HW upon uop writeback event=0xc1,period=100003,umask=0x80  00     resource_stalls.any pipeline Resource-related stall cycles event=0xa2,period=2000003,umask=1  00    Cycles Allocation is stalled due to Resource Related reason resource_stalls.sb pipeline Cycles stalled due to no store buffers available. (not including draining form sync) event=0xa2,period=2000003,umask=8  00    Cycles stalled due to no store buffers available (not including draining form sync) rs_events.empty_cycles pipeline Cycles when Reservation Station (RS) is empty for the thread event=0x5e,period=2000003,umask=1  00    Cycles the RS is empty for the thread uops_dispatched_port.port_0 pipeline Cycles per thread when uops are dispatched to port 0 event=0xa1,period=2000003,umask=1  00    Cycles which a Uop is dispatched on port 0 uops_dispatched_port.port_0_core pipeline Cycles per core when uops are dispatched to port 0 event=0xa1,any=1,period=2000003,umask=1  00     uops_dispatched_port.port_1 pipeline Cycles per thread when uops are dispatched to port 1 event=0xa1,period=2000003,umask=2  00    Cycles which a Uop is dispatched on port 1 uops_dispatched_port.port_1_core pipeline Cycles per core when uops are dispatched to port 1 event=0xa1,any=1,period=2000003,umask=2  00     uops_dispatched_port.port_2 pipeline Cycles per thread when load or STA uops are dispatched to port 2 event=0xa1,period=2000003,umask=0xc  00    Cycles which a Uop is dispatched on port 2 uops_dispatched_port.port_2_core pipeline Uops dispatched to port 2, loads and stores per core (speculative and retired) event=0xa1,any=1,period=2000003,umask=0xc  00     uops_dispatched_port.port_3 pipeline Cycles per thread when load or STA uops are dispatched to port 3 event=0xa1,period=2000003,umask=0x30  00    Cycles which a Uop is dispatched on port 3 uops_dispatched_port.port_3_core pipeline Cycles per core when load or STA uops are dispatched to port 3 event=0xa1,any=1,period=2000003,umask=0x30  00     uops_dispatched_port.port_4 pipeline Cycles per thread when uops are dispatched to port 4 event=0xa1,period=2000003,umask=0x40  00    Cycles which a Uop is dispatched on port 4 uops_dispatched_port.port_4_core pipeline Cycles per core when uops are dispatched to port 4 event=0xa1,any=1,period=2000003,umask=0x40  00     uops_dispatched_port.port_5 pipeline Cycles per thread when uops are dispatched to port 5 event=0xa1,period=2000003,umask=0x80  00    Cycles which a Uop is dispatched on port 5 uops_dispatched_port.port_5_core pipeline Cycles per core when uops are dispatched to port 5 event=0xa1,any=1,period=2000003,umask=0x80  00     uops_executed.core pipeline Number of uops executed on the core event=0xb1,period=2000003,umask=2  00    Counts total number of uops to be executed per-core each cycle uops_executed.stall_cycles pipeline Counts number of cycles no uops were dispatched to be executed on this thread event=0xb1,cmask=1,inv=1,period=2000003,umask=1  00     uops_executed.thread pipeline Counts the number of uops to be executed per-thread each cycle event=0xb1,period=2000003,umask=1  00    Counts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles uops_issued.any pipeline Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS) event=0xe,period=2000003,umask=1  00    Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core uops_issued.flags_merge pipeline Number of flags-merge uops being allocated event=0xe,period=2000003,umask=0x10  00    Number of flags-merge uops allocated. Such uops adds delay uops_issued.slow_lea pipeline Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not event=0xe,period=2000003,umask=0x20  00    Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not uops_retired.all pipeline Retired uops (Precise event) event=0xc2,period=2000003,umask=1  00     uops_retired.retire_slots pipeline Retirement slots used (Precise event) event=0xc2,period=2000003,umask=2  00     uops_retired.total_cycles pipeline Cycles with less than 10 actually retired uops event=0xc2,cmask=10,inv=1,period=2000003,umask=1  00     unc_arb_coh_trk_occupancy.all uncore interconnect Cycles weighted by number of requests pending in Coherency Tracker event=0x83,umask=1  01     unc_arb_trk_occupancy.all uncore interconnect Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC event=0x80,umask=1  01     unc_arb_trk_occupancy.cycles_over_half_full uncore interconnect Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC event=0x80,cmask=10,umask=1  01     unc_arb_trk_requests.evictions uncore interconnect Counts the number of LLC evictions allocated event=0x81,umask=0x80  01     unc_arb_trk_requests.writes uncore interconnect Counts the number of allocated write entries, include full, partial, and LLC evictions event=0x81,umask=0x20  01     unc_clock.socket uncore interconnect This 48-bit fixed counter counts the UCLK cycles event=0xff  01     dtlb_load_misses.large_page_walk_completed virtual memory Page walk for a large page completed for Demand load event=8,period=100003,umask=0x88  00     dtlb_load_misses.miss_causes_a_walk virtual memory Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size event=8,period=100003,umask=0x81  00    Misses in all TLB levels that cause a page walk of any page size from demand loads dtlb_load_misses.stlb_hit virtual memory Load operations that miss the first DTLB level but hit the second and do not cause page walks event=0x5f,period=100003,umask=4  00    Counts load operations that missed 1st level DTLB but hit the 2nd level dtlb_load_misses.walk_completed virtual memory Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size event=8,period=100003,umask=0x82  00    Misses in all TLB levels that caused page walk completed of any size by demand loads dtlb_load_misses.walk_duration virtual memory Demand load cycles page miss handler (PMH) is busy with this walk event=8,period=2000003,umask=0x84  00    Cycle PMH is busy with a walk due to demand loads dtlb_store_misses.stlb_hit virtual memory Store operations that miss the first TLB level but hit the second and do not cause page walks event=0x49,period=100003,umask=0x10  00     dtlb_store_misses.walk_completed virtual memory Store misses in all DTLB levels that cause completed page walks event=0x49,period=100003,umask=2  00    Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G) dtlb_store_misses.walk_duration virtual memory Cycles when PMH is busy with page walks event=0x49,period=2000003,umask=4  00    Cycles PMH is busy with this walk ept.walk_cycles virtual memory Cycle count for an Extended Page table walk.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches event=0x4f,period=2000003,umask=0x10  00     itlb.itlb_flush virtual memory Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages event=0xae,period=100007,umask=1  00    Counts the number of ITLB flushes, includes 4k/2M/4M pages itlb_misses.large_page_walk_completed virtual memory Completed page walks in ITLB due to STLB load misses for large pages event=0x85,period=100003,umask=0x80  00     itlb_misses.miss_causes_a_walk virtual memory Misses at all ITLB levels that cause page walks event=0x85,period=100003,umask=1  00    Misses in all ITLB levels that cause page walks itlb_misses.stlb_hit virtual memory Operations that miss the first ITLB level but hit the second and do not cause any page walks event=0x85,period=100003,umask=0x10  00    Number of cache load STLB hits. No page walk itlb_misses.walk_completed virtual memory Misses in all ITLB levels that cause completed page walks event=0x85,period=100003,umask=2  00     itlb_misses.walk_duration virtual memory Cycles when PMH is busy with page walks event=0x85,period=2000003,umask=4  00    Cycle PMH is busy with a walk tlb_flush.dtlb_thread virtual memory DTLB flush attempts of the thread-specific entries event=0xbd,period=100007,umask=1  00     tlb_flush.stlb_any virtual memory STLB flush attempts event=0xbd,period=100007,umask=0x20  00    Count number of STLB flush attempts mem_load_uops_llc_miss_retired.local_dram cache Retired load uops whose data source was local DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded) event=0xd3,period=100007,umask=3  00     mem_load_uops_llc_miss_retired.remote_dram cache Retired load uops whose data source was remote DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded) event=0xd3,period=100007,umask=0xc  00     mem_load_uops_llc_miss_retired.remote_fwd cache Data forwarded from remote cache event=0xd3,period=100007,umask=0x20  00     mem_load_uops_llc_miss_retired.remote_hitm cache Remote cache HITM event=0xd3,period=100007,umask=0x10  00     offcore_response.all_data_rd.llc_hit.snoop_miss cache Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0091  00     offcore_response.all_pf_data_rd.llc_hit.any_response cache Counts all prefetch data reads that hit the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0090  00     offcore_response.all_pf_data_rd.llc_hit.hitm_other_core cache Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c0090  00     offcore_response.all_pf_data_rd.llc_hit.hit_other_core_no_fwd cache Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003c0090  00     offcore_response.all_pf_data_rd.llc_hit.no_snoop_needed cache Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c0090  00     offcore_response.all_pf_data_rd.llc_hit.snoop_miss cache Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0090  00     offcore_response.all_reads.llc_hit.any_response cache Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c03f7  00     offcore_response.all_reads.llc_hit.hitm_other_core cache Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c03f7  00     offcore_response.all_reads.llc_hit.hit_other_core_no_fwd cache Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003c03f7  00     offcore_response.all_reads.llc_hit.no_snoop_needed cache Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c03f7  00     offcore_response.all_reads.llc_hit.snoop_miss cache Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c03f7  00     offcore_response.demand_data_rd.llc_hit.snoop_miss cache Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0001  00     offcore_response.other.lru_hints cache Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches event=0xb7,period=100003,umask=1,offcore_rsp=0x803c8000  00     offcore_response.other.portio_mmio_uc cache Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses event=0xb7,period=100003,umask=1,offcore_rsp=0x23ffc08000  00     offcore_response.pf_l2_code_rd.llc_hit.any_response cache Counts all prefetch (that bring data to L2) code reads that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0040  00     offcore_response.pf_l2_data_rd.llc_hit.any_response cache Counts prefetch (that bring data to L2) data reads that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0010  00     offcore_response.pf_l2_data_rd.llc_hit.hitm_other_core cache Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c0010  00     offcore_response.pf_l2_data_rd.llc_hit.hit_other_core_no_fwd cache Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003c0010  00     offcore_response.pf_l2_data_rd.llc_hit.no_snoop_needed cache Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c0010  00     offcore_response.pf_l2_data_rd.llc_hit.snoop_miss cache Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0010  00     offcore_response.pf_llc_code_rd.llc_hit.any_response cache Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0200  00     offcore_response.pf_llc_data_rd.llc_hit.any_response cache Counts prefetch (that bring data to LLC only) data reads that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0080  00     offcore_response.pf_llc_data_rd.llc_hit.hitm_other_core cache Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c0080  00     offcore_response.pf_llc_data_rd.llc_hit.hit_other_core_no_fwd cache Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003c0080  00     offcore_response.pf_llc_data_rd.llc_hit.no_snoop_needed cache Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c0080  00     offcore_response.pf_llc_data_rd.llc_hit.snoop_miss cache Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0080  00     offcore_response.all_code_rd.llc_miss.any_response memory Counts all demand & prefetch code reads that miss the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3fffc00244  00     offcore_response.all_code_rd.llc_miss.remote_dram memory Counts all demand & prefetch code reads that miss the LLC  and the data returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x67f800244  00     offcore_response.all_code_rd.llc_miss.remote_hit_forward memory Counts all demand & prefetch code reads that miss the LLC  and the data forwarded from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x87f800244  00     offcore_response.all_data_rd.llc_miss.any_response memory Counts all demand & prefetch data reads that hits the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3fffc20091  00     offcore_response.all_reads.llc_miss.any_response memory Counts all data/code/rfo reads (demand & prefetch) that hit the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3fffc203f7  00     offcore_response.all_reads.llc_miss.local_dram memory Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x6004003f7  00     offcore_response.all_reads.llc_miss.remote_hitm memory Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  the data is found in M state in remote cache and forwarded from there event=0xb7,period=100003,umask=1,offcore_rsp=0x107fc003f7  00     offcore_response.all_reads.llc_miss.remote_hit_forward memory Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data forwarded from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x87f8203f7  00     offcore_response.demand_code_rd.llc_miss.any_response memory Counts all demand code reads that miss the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3fffc20004  00     offcore_response.demand_code_rd.llc_miss.local_dram memory Counts all demand code reads that miss the LLC  and the data returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x600400004  00     offcore_response.demand_code_rd.llc_miss.remote_dram memory Counts all demand code reads that miss the LLC  and the data returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x67f800004  00     offcore_response.demand_code_rd.llc_miss.remote_hitm memory Counts all demand code reads that miss the LLC  the data is found in M state in remote cache and forwarded from there event=0xb7,period=100003,umask=1,offcore_rsp=0x107fc00004  00     offcore_response.demand_code_rd.llc_miss.remote_hit_forward memory Counts all demand code reads that miss the LLC  and the data forwarded from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x87f820004  00     offcore_response.demand_data_rd.llc_miss.any_dram memory Counts demand data reads that miss the LLC  and the data returned from remote & local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x67fc00001  00     offcore_response.demand_data_rd.llc_miss.any_response memory Counts demand data reads that miss in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3fffc20001  00     offcore_response.demand_data_rd.llc_miss.local_dram memory Counts demand data reads that miss the LLC  and the data returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x600400001  00     offcore_response.demand_data_rd.llc_miss.remote_dram memory Counts demand data reads that miss the LLC  and the data returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x67f800001  00     offcore_response.demand_data_rd.llc_miss.remote_hitm memory Counts demand data reads that miss the LLC  the data is found in M state in remote cache and forwarded from there event=0xb7,period=100003,umask=1,offcore_rsp=0x107fc00001  00     offcore_response.demand_data_rd.llc_miss.remote_hit_forward memory Counts demand data reads that miss the LLC  and the data forwarded from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x87f820001  00     offcore_response.demand_rfo.llc_miss.remote_hitm memory Counts all demand data writes (RFOs) that miss the LLC and the data is found in M state in remote cache and forwarded from there event=0xb7,period=100003,umask=1,offcore_rsp=0x107fc20002  00     offcore_response.pf_l2_code_rd.llc_miss.any_response memory Counts all prefetch (that bring data to L2) code reads that miss the LLC  and the data returned from remote & local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x3fffc20040  00     offcore_response.pf_l2_data_rd.llc_miss.any_dram memory Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from remote & local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x67fc00010  00     offcore_response.pf_l2_data_rd.llc_miss.any_response memory Counts prefetch (that bring data to L2) data reads that miss in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3fffc20010  00     offcore_response.pf_l2_data_rd.llc_miss.local_dram memory Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x600400010  00     offcore_response.pf_l2_data_rd.llc_miss.remote_dram memory Counts prefetch (that bring data to L2) data reads  that miss the LLC  and the data returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x67f800010  00     offcore_response.pf_l2_data_rd.llc_miss.remote_hitm memory Counts prefetch (that bring data to L2) data reads that miss the LLC  the data is found in M state in remote cache and forwarded from there event=0xb7,period=100003,umask=1,offcore_rsp=0x107fc00010  00     offcore_response.pf_l2_data_rd.llc_miss.remote_hit_forward memory Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data forwarded from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x87f820010  00     offcore_response.pf_llc_code_rd.llc_miss.any_response memory Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3fffc20200  00     offcore_response.pf_llc_data_rd.llc_miss.any_response memory Counts prefetch (that bring data to LLC only) data reads that miss in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3fffc20080  00     unc_c_llc_lookup.any uncore cache Cache Lookups; Any Request event=0x34,umask=0x11  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set filter mask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Filters for any transaction originating from the IPQ or IRQ.  This does not include lookups originating from the ISMQ unc_c_llc_lookup.data_read uncore cache Cache Lookups; Data Read Request event=0x34,umask=3  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set filter mask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Read transactions unc_c_llc_lookup.nid uncore cache Cache Lookups; Lookups that Match NID event=0x34,umask=0x41  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set filter mask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Qualify one of the other subevents by the Target NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.   In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system unc_c_llc_lookup.remote_snoop uncore cache Cache Lookups; External Snoop Request event=0x34,umask=9  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set filter mask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ unc_c_llc_lookup.write uncore cache Cache Lookups; Write Requests event=0x34,umask=5  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set filter mask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Writeback transactions from L2 to the LLC  This includes all write transactions -- both Cacheable and UC unc_c_llc_victims.miss uncore cache Lines Victimized event=0x37,umask=8  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_c_llc_victims.s_state uncore cache Lines Victimized; Lines in S State event=0x37,umask=4  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_c_ring_ad_used.ccw uncore cache AD Ring In Use; Counterclockwise event=0x1b,umask=0xc  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.cw uncore cache AD Ring In Use; Clockwise event=0x1b,umask=3  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.down uncore cache AD Ring In Use; Down event=0x1b,umask=0xcc  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.down_vr0_even uncore cache AD Ring In Use; Down and Even on Vring 0 event=0x1b,umask=4  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 0 unc_c_ring_ad_used.down_vr0_odd uncore cache AD Ring In Use; Down and Odd on Vring 0 event=0x1b,umask=8  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 0 unc_c_ring_ad_used.down_vr1_even uncore cache AD Ring In Use; Down and Even on VRing 1 event=0x1b,umask=0x40  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 1 unc_c_ring_ad_used.down_vr1_odd uncore cache AD Ring In Use; Down and Odd on VRing 1 event=0x1b,umask=0x80  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 1 unc_c_ring_ad_used.up uncore cache AD Ring In Use; Up event=0x1b,umask=0x33  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.up_vr0_even uncore cache AD Ring In Use; Up and Even on Vring 0 event=0x1b,umask=1  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 0 unc_c_ring_ad_used.up_vr0_odd uncore cache AD Ring In Use; Up and Odd on Vring 0 event=0x1b,umask=2  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 0 unc_c_ring_ad_used.up_vr1_even uncore cache AD Ring In Use; Up and Even on VRing 1 event=0x1b,umask=0x10  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 1 unc_c_ring_ad_used.up_vr1_odd uncore cache AD Ring In Use; Up and Odd on VRing 1 event=0x1b,umask=0x20  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 1 unc_c_ring_ak_used.ccw uncore cache AK Ring In Use; Counterclockwise event=0x1c,umask=0xc  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.cw uncore cache AK Ring In Use; Clockwise event=0x1c,umask=3  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.down uncore cache AK Ring In Use; Down event=0x1c,umask=0xcc  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.down_vr0_even uncore cache AK Ring In Use; Down and Even on Vring 0 event=0x1c,umask=4  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 0 unc_c_ring_ak_used.down_vr0_odd uncore cache AK Ring In Use; Down and Odd on Vring 0 event=0x1c,umask=8  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 0 unc_c_ring_ak_used.down_vr1_even uncore cache AK Ring In Use; Down and Even on VRing 1 event=0x1c,umask=0x40  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 1 unc_c_ring_ak_used.down_vr1_odd uncore cache AK Ring In Use; Down and Odd on VRing 1 event=0x1c,umask=0x80  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 1 unc_c_ring_ak_used.up uncore cache AK Ring In Use; Up event=0x1c,umask=0x33  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.up_vr0_even uncore cache AK Ring In Use; Up and Even on Vring 0 event=0x1c,umask=1  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 0 unc_c_ring_ak_used.up_vr0_odd uncore cache AK Ring In Use; Up and Odd on Vring 0 event=0x1c,umask=2  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 0 unc_c_ring_ak_used.up_vr1_even uncore cache AK Ring In Use; Up and Even on VRing 1 event=0x1c,umask=0x10  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 1 unc_c_ring_ak_used.up_vr1_odd uncore cache AK Ring In Use; Up and Odd on VRing 1 event=0x1c,umask=0x20  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 1 unc_c_ring_bl_used.ccw uncore cache BL Ring in Use; Counterclockwise event=0x1d,umask=0xc  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.cw uncore cache BL Ring in Use; Clockwise event=0x1d,umask=3  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.down uncore cache BL Ring in Use; Down event=0x1d,umask=0xcc  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.down_vr0_even uncore cache BL Ring in Use; Down and Even on Vring 0 event=0x1d,umask=4  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 0 unc_c_ring_bl_used.down_vr0_odd uncore cache BL Ring in Use; Down and Odd on Vring 0 event=0x1d,umask=8  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 0 unc_c_ring_bl_used.down_vr1_even uncore cache BL Ring in Use; Down and Even on VRing 1 event=0x1d,umask=0x40  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 1 unc_c_ring_bl_used.down_vr1_odd uncore cache BL Ring in Use; Down and Odd on VRing 1 event=0x1d,umask=0x80  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 1 unc_c_ring_bl_used.up uncore cache BL Ring in Use; Up event=0x1d,umask=0x33  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.up_vr0_even uncore cache BL Ring in Use; Up and Even on Vring 0 event=0x1d,umask=1  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 0 unc_c_ring_bl_used.up_vr0_odd uncore cache BL Ring in Use; Up and Odd on Vring 0 event=0x1d,umask=2  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 0 unc_c_ring_bl_used.up_vr1_even uncore cache BL Ring in Use; Up and Even on VRing 1 event=0x1d,umask=0x10  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 1 unc_c_ring_bl_used.up_vr1_odd uncore cache BL Ring in Use; Up and Odd on VRing 1 event=0x1d,umask=0x20  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 1 unc_c_ring_bounces.ad_irq uncore cache Number of LLC responses that bounced on the Ring event=5,umask=2  01     unc_c_ring_bounces.ak uncore cache Number of LLC responses that bounced on the Ring.; Acknowledgements to core event=5,umask=4  01     unc_c_ring_bounces.ak_core uncore cache Number of LLC responses that bounced on the Ring.: Acknowledgements to core event=5,umask=2  01     unc_c_ring_bounces.bl uncore cache Number of LLC responses that bounced on the Ring.; Data Responses to core event=5,umask=8  01     unc_c_ring_bounces.bl_core uncore cache Number of LLC responses that bounced on the Ring.: Data Responses to core event=5,umask=4  01     unc_c_ring_bounces.iv_core uncore cache Number of LLC responses that bounced on the Ring.: Snoops of processor's cache event=5,umask=8  01     unc_c_ring_iv_used.any uncore cache IV Ring in Use; Any event=0x1e,umask=0xf  01    Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters any polarity unc_c_ring_iv_used.down uncore cache IV Ring in Use; Down event=0x1e,umask=0xcc  01    Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for Down polarity unc_c_ring_iv_used.up uncore cache IV Ring in Use; Up event=0x1e,umask=0x33  01    Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for Up polarity unc_c_ring_sink_starved.ad_ipq uncore cache  event=6,umask=2  01     unc_c_ring_sink_starved.ad_irq uncore cache  event=6,umask=1  01     unc_c_ring_sink_starved.iv uncore cache  event=6,umask=0x10  01     unc_c_ring_src_thrtl uncore cache  event=7  01     unc_c_rxr_ext_starved.ipq uncore cache Ingress Arbiter Blocking Cycles; IRQ event=0x12,umask=2  01    Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.; IPQ is externally startved and therefore we are blocking the IRQ unc_c_rxr_ext_starved.prq uncore cache Ingress Arbiter Blocking Cycles event=0x12,umask=4  01    IRQ is blocking the ingress queue and causing the starvation unc_c_rxr_inserts.irq_rejected uncore cache Ingress Allocations: IRQ Rejected event=0x13,umask=2  01    Counts number of allocations per cycle into the specified Ingress queue unc_c_rxr_inserts.vfifo uncore cache Ingress Allocations; VFIFO event=0x13,umask=0x10  01    Counts number of allocations per cycle into the specified Ingress queue.; Counts the number of allocations into the IRQ Ordering FIFO.  In JKT, it is necessary to keep IO requests in order.  Therefore, they are allocated into an ordering FIFO that sits next to the IRQ, and must be satisfied from the FIFO in order (with respect to each other).  This event, in conjunction with the Occupancy Accumulator event, can be used to calculate average lifetime in the FIFO.  Transactions are allocated into the FIFO as soon as they enter the Cachebo (and the IRQ) and are deallocated from the FIFO as soon as they are deallocated from the IRQ unc_c_rxr_ismq_retry.wb_credits uncore cache ISMQ Retries; No WB Credits event=0x33,umask=0x80  01    Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Retries of writes to local memory due to lack of HT WB credits unc_c_rxr_occupancy.irq_rejected uncore cache IRQ Rejected event=0x11,umask=2  01    Counts number of entries in the specified Ingress queue in each cycle unc_c_rxr_occupancy.vfifo uncore cache Ingress Occupancy; VFIFO event=0x11,umask=0x10  01    Counts number of entries in the specified Ingress queue in each cycle.; Accumulates the number of used entries in the IRQ Ordering FIFO in each cycle.  In JKT, it is necessary to keep IO requests in order.  Therefore, they are allocated into an ordering FIFO that sits next to the IRQ, and must be satisfied from the FIFO in order (with respect to each other).  This event, in conjunction with the Allocations event, can be used to calculate average lifetime in the FIFO.  This event can be used in conjunction with the Not Empty event to calculate average queue occupancy. Transactions are allocated into the FIFO as soon as they enter the Cachebo (and the IRQ) and are deallocated from the FIFO as soon as they are deallocated from the IRQ unc_h_bt_bypass uncore cache BT Bypass event=0x52  01    Number of transactions that bypass the BT (fifo) to HT unc_h_bt_cycles_ne.local uncore cache BT Cycles Not Empty: Local event=0x42,umask=1  01    Cycles the Backup Tracker (BT) is not empty. The BT is the actual HOM tracker in IVT unc_h_bt_cycles_ne.remote uncore cache BT Cycles Not Empty: Remote event=0x42,umask=2  01    Cycles the Backup Tracker (BT) is not empty. The BT is the actual HOM tracker in IVT unc_h_bt_occupancy.local uncore cache BT Occupancy; Local event=0x43,umask=1  01    Accumulates the occupancy of the HA BT pool in every cycle.  This can be used with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_bt_occupancy.reads_local uncore cache BT Occupancy; Reads Local event=0x43,umask=4  01    Accumulates the occupancy of the HA BT pool in every cycle.  This can be used with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_bt_occupancy.reads_remote uncore cache BT Occupancy; Reads Remote event=0x43,umask=8  01    Accumulates the occupancy of the HA BT pool in every cycle.  This can be used with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_bt_occupancy.remote uncore cache BT Occupancy; Remote event=0x43,umask=2  01    Accumulates the occupancy of the HA BT pool in every cycle.  This can be used with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_bt_occupancy.writes_local uncore cache BT Occupancy; Writes Local event=0x43,umask=0x10  01    Accumulates the occupancy of the HA BT pool in every cycle.  This can be used with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_bt_occupancy.writes_remote uncore cache BT Occupancy; Writes Remote event=0x43,umask=0x20  01    Accumulates the occupancy of the HA BT pool in every cycle.  This can be used with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_bypass_imc.not_taken uncore cache HA to iMC Bypass; Not Taken event=0x14,umask=2  01    Counts the number of times when the HA was able to bypass was attempted.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filted by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass unc_h_bypass_imc.taken uncore cache HA to iMC Bypass; Taken event=0x14,umask=1  01    Counts the number of times when the HA was able to bypass was attempted.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filted by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the bypass unc_h_conflict_cycles.ackcnflts uncore cache Conflict Checks; Acknowledge Conflicts event=0xb,umask=8  01    Count the number of Ackcnflts unc_h_conflict_cycles.cmp_fwds uncore cache Conflict Checks; Cmp Fwds event=0xb,umask=0x10  01    Count the number of Cmp_Fwd. This will give the number of late conflicts unc_h_conflict_cycles.conflict uncore cache Conflict Checks; Conflict Detected event=0xb,umask=2  01    Counts the number of cycles that we are handling conflicts unc_h_conflict_cycles.last uncore cache Conflict Checks; Last in conflict chain event=0xb,umask=4  01    Count every last conflictor in conflict chain. Can be used to compute the average conflict chain length as (#Ackcnflts/#LastConflictor)+1. This can be used to give a feel for the conflict chain lengths while analyzing lock kernels unc_h_directory_lookup.any uncore cache Directory Lookups: Any state event=0xc,umask=0x10  01    Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to unc_h_directory_lookup.snoop_a uncore cache Directory Lookups: Snoop A event=0xc,umask=8  01    Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to unc_h_directory_lookup.snoop_s uncore cache Directory Lookups: Snoop S event=0xc,umask=2  01    Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to unc_h_directory_lookup.state_a uncore cache Directory Lookups: A State event=0xc,umask=0x80  01    Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to unc_h_directory_lookup.state_i uncore cache Directory Lookups: I State event=0xc,umask=0x20  01    Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to unc_h_directory_lookup.state_s uncore cache Directory Lookups: S State event=0xc,umask=0x40  01    Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to unc_h_directory_update.a2i uncore cache Directory Updates: A2I event=0xd,umask=0x20  01    Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears unc_h_directory_update.a2s uncore cache Directory Updates: A2S event=0xd,umask=0x40  01    Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears unc_h_directory_update.i2a uncore cache Directory Updates: I2A event=0xd,umask=4  01    Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears unc_h_directory_update.i2s uncore cache Directory Updates: I2S event=0xd,umask=2  01    Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears unc_h_directory_update.s2a uncore cache Directory Updates: S2A event=0xd,umask=0x10  01    Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears unc_h_directory_update.s2i uncore cache Directory Updates: S2I event=0xd,umask=8  01    Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears unc_h_igr_ad_qpi2_accumulator uncore cache AD QPI Link 2 Credit Accumulator event=0x59  01    Accumulates the number of credits available to the QPI Link 2 AD Ingress buffer unc_h_igr_bl_qpi2_accumulator uncore cache BL QPI Link 2 Credit Accumulator event=0x5a  01    Accumulates the number of credits available to the QPI Link 2 BL Ingress buffer unc_h_igr_credits_ad_qpi2 uncore cache AD QPI Link 2 Credit Accumulator event=0x59  01    Accumulates the number of credits available to the QPI Link 2 AD Ingress buffer unc_h_igr_credits_bl_qpi2 uncore cache BL QPI Link 2 Credit Accumulator event=0x5a  01    Accumulates the number of credits available to the QPI Link 2 BL Ingress buffer unc_h_iodc_conflicts.any uncore cache IODC Conflicts; Any Conflict event=0x57,umask=1  01     unc_h_iodc_conflicts.last uncore cache IODC Conflicts; Last Conflict event=0x57,umask=4  01     unc_h_iodc_conflicts.remote_invi2e_same_rtid uncore cache IODC Conflicts: Remote InvItoE - Same RTID event=0x57,umask=1  01     unc_h_iodc_conflicts.remote_other_same_addr uncore cache IODC Conflicts: Remote (Other) - Same Addr event=0x57,umask=4  01     unc_h_iodc_inserts uncore cache IODC Inserts event=0x56  01    IODC Allocations unc_h_iodc_olen_wbmtoi uncore cache Num IODC 0 Length Writes event=0x58  01    Num IODC 0 Length Writebacks M to I - All of which are dropped unc_h_ring_ad_used.ccw uncore cache HA AD Ring in Use; Counterclockwise event=0x3e,umask=0xcc  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ad_used.ccw_vr0_even uncore cache HA AD Ring in Use; Counterclockwise and Even on VRing 0 event=0x3e,umask=4  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0 unc_h_ring_ad_used.ccw_vr0_odd uncore cache HA AD Ring in Use; Counterclockwise and Odd on VRing 0 event=0x3e,umask=8  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0 unc_h_ring_ad_used.ccw_vr1_even uncore cache HA AD Ring in Use; Counterclockwise and Even on VRing 1 event=0x3e,umask=0x40  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1 unc_h_ring_ad_used.ccw_vr1_odd uncore cache HA AD Ring in Use; Counterclockwise and Odd on VRing 1 event=0x3e,umask=0x80  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1 unc_h_ring_ad_used.cw uncore cache HA AD Ring in Use; Clockwise event=0x3e,umask=0x33  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ad_used.cw_vr0_even uncore cache HA AD Ring in Use; Clockwise and Even on VRing 0 event=0x3e,umask=1  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0 unc_h_ring_ad_used.cw_vr0_odd uncore cache HA AD Ring in Use; Clockwise and Odd on VRing 0 event=0x3e,umask=2  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0 unc_h_ring_ad_used.cw_vr1_even uncore cache HA AD Ring in Use; Clockwise and Even on VRing 1 event=0x3e,umask=0x10  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1 unc_h_ring_ad_used.cw_vr1_odd uncore cache HA AD Ring in Use; Clockwise and Odd on VRing 1 event=0x3e,umask=0x20  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1 unc_h_ring_ak_used.ccw uncore cache HA AK Ring in Use; Counterclockwise event=0x3f,umask=0xcc  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ak_used.ccw_vr0_even uncore cache HA AK Ring in Use; Counterclockwise and Even on VRing 0 event=0x3f,umask=4  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0 unc_h_ring_ak_used.ccw_vr0_odd uncore cache HA AK Ring in Use; Counterclockwise and Odd on VRing 0 event=0x3f,umask=8  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0 unc_h_ring_ak_used.ccw_vr1_even uncore cache HA AK Ring in Use; Counterclockwise and Even on VRing 1 event=0x3f,umask=0x40  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1 unc_h_ring_ak_used.ccw_vr1_odd uncore cache HA AK Ring in Use; Counterclockwise and Odd on VRing 1 event=0x3f,umask=0x80  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1 unc_h_ring_ak_used.cw uncore cache HA AK Ring in Use; Clockwise event=0x3f,umask=0x33  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ak_used.cw_vr0_even uncore cache HA AK Ring in Use; Clockwise and Even on VRing 0 event=0x3f,umask=1  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0 unc_h_ring_ak_used.cw_vr0_odd uncore cache HA AK Ring in Use; Clockwise and Odd on VRing 0 event=0x3f,umask=2  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0 unc_h_ring_ak_used.cw_vr1_even uncore cache HA AK Ring in Use; Clockwise and Even on VRing 1 event=0x3f,umask=0x10  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1 unc_h_ring_ak_used.cw_vr1_odd uncore cache HA AK Ring in Use; Clockwise and Odd on VRing 1 event=0x3f,umask=0x20  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1 unc_h_ring_bl_used.ccw uncore cache HA BL Ring in Use; Counterclockwise event=0x40,umask=0xcc  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_bl_used.ccw_vr0_even uncore cache HA BL Ring in Use; Counterclockwise and Even on VRing 0 event=0x40,umask=4  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0 unc_h_ring_bl_used.ccw_vr0_odd uncore cache HA BL Ring in Use; Counterclockwise and Odd on VRing 0 event=0x40,umask=8  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0 unc_h_ring_bl_used.ccw_vr1_even uncore cache HA BL Ring in Use; Counterclockwise and Even on VRing 1 event=0x40,umask=0x40  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1 unc_h_ring_bl_used.ccw_vr1_odd uncore cache HA BL Ring in Use; Counterclockwise and Odd on VRing 1 event=0x40,umask=0x80  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1 unc_h_ring_bl_used.cw uncore cache HA BL Ring in Use; Clockwise event=0x40,umask=0x33  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_bl_used.cw_vr0_even uncore cache HA BL Ring in Use; Clockwise and Even on VRing 0 event=0x40,umask=1  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0 unc_h_ring_bl_used.cw_vr0_odd uncore cache HA BL Ring in Use; Clockwise and Odd on VRing 0 event=0x40,umask=2  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0 unc_h_ring_bl_used.cw_vr1_even uncore cache HA BL Ring in Use; Clockwise and Even on VRing 1 event=0x40,umask=0x10  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1 unc_h_ring_bl_used.cw_vr1_odd uncore cache HA BL Ring in Use; Clockwise and Odd on VRing 1 event=0x40,umask=0x20  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1 unc_h_rpq_cycles_no_reg_credits.chn0 uncore cache iMC RPQ Credits Empty - Regular; Channel 0 event=0x15,umask=1  01    Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only unc_h_rpq_cycles_no_reg_credits.chn1 uncore cache iMC RPQ Credits Empty - Regular; Channel 1 event=0x15,umask=2  01    Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only unc_h_rpq_cycles_no_reg_credits.chn2 uncore cache iMC RPQ Credits Empty - Regular; Channel 2 event=0x15,umask=4  01    Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only unc_h_rpq_cycles_no_reg_credits.chn3 uncore cache iMC RPQ Credits Empty - Regular; Channel 3 event=0x15,umask=8  01    Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only unc_h_snoop_resp.rspsfwd uncore cache Snoop Responses Received; RspSFwd event=0x21,umask=8  01    Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspSFwd.  This is returned when a remote caching agent forwards data but holds on to its currently copy.  This is common for data and code reads that hit in a remote socket in E or F state unc_h_tracker_cycles_ne uncore cache Tracker Cycles Not Empty event=3  01    Counts the number of cycles when the local HA tracker pool is not empty.  This can be used with edge detect to identify the number of situations when the pool became empty.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, this buffer could be completely empty, but there may still be credits in use by the CBos.  This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy.  HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_txr_ad_occupancy.sched0 uncore cache AD Egress Occupancy; Scheduler 0 event=0x28,umask=1  01    AD Egress Occupancy; Filter for occupancy from scheduler bank 0 unc_h_txr_ad_occupancy.sched1 uncore cache AD Egress Occupancy; Scheduler 1 event=0x28,umask=2  01    AD Egress Occupancy; Filter for occupancy from scheduler bank 1 unc_h_txr_ak.crd_cbo uncore cache Outbound Ring Transactions on AK: CRD Transactions to Cbo event=0xe,umask=2  01     unc_h_txr_ak_occupancy.sched0 uncore cache AK Egress Occupancy; Scheduler 0 event=0x30,umask=1  01    AK Egress Occupancy; Filter for occupancy from scheduler bank 0 unc_h_txr_ak_occupancy.sched1 uncore cache AK Egress Occupancy; Scheduler 1 event=0x30,umask=2  01    AK Egress Occupancy; Filter for occupancy from scheduler bank 1 unc_h_txr_bl_occupancy.all uncore cache BL Egress Occupancy: All event=0x34,umask=3  01     unc_h_txr_bl_occupancy.sched0 uncore cache BL Egress Occupancy; Scheduler 0 event=0x34,umask=1  01    BL Egress Occupancy; Filter for occupancy from scheduler bank 0 unc_h_txr_bl_occupancy.sched1 uncore cache BL Egress Occupancy; Scheduler 1 event=0x34,umask=2  01    BL Egress Occupancy; Filter for occupancy from scheduler bank 1 unc_h_wpq_cycles_no_reg_credits.chn0 uncore cache HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0 event=0x18,umask=1  01    Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only unc_h_wpq_cycles_no_reg_credits.chn1 uncore cache HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1 event=0x18,umask=2  01    Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only unc_h_wpq_cycles_no_reg_credits.chn2 uncore cache HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2 event=0x18,umask=4  01    Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only unc_h_wpq_cycles_no_reg_credits.chn3 uncore cache HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3 event=0x18,umask=8  01    Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only unc_i_address_match.merge_count uncore interconnect Address Match (Conflict) Count; Conflict Merges event=0x17,umask=2  01    Counts the number of times when an inbound write (from a device to memory or another device) had an address match with another request in the write cache.; When two requests to the same address from the same source are received back to back, it is possible to merge the two of them together unc_i_address_match.stall_count uncore interconnect Address Match (Conflict) Count; Conflict Stalls event=0x17,umask=1  01    Counts the number of times when an inbound write (from a device to memory or another device) had an address match with another request in the write cache.; When it is not possible to merge two conflicting requests, a stall event occurs.  This is bad for performance unc_i_cache_ack_pending_occupancy.any uncore interconnect Write Ack Pending Occupancy; Any Source event=0x14,umask=1  01    Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore.  These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data.  The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released.  Note that a single tickle can result in multiple decrements.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register.  This register allows one to select one specific queue.  It is not possible to monitor multiple queues at a time unc_i_cache_ack_pending_occupancy.source uncore interconnect Write Ack Pending Occupancy; Select Source event=0x14,umask=2  01    Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore.  These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data.  The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released.  Note that a single tickle can result in multiple decrements.; Tracks all requests from any source port unc_i_cache_own_occupancy.any uncore interconnect Outstanding Write Ownership Occupancy; Any Source event=0x13,umask=1  01    Accumulates the number of writes (and write prefetches) that are outstanding in the uncore trying to acquire ownership in each cycle.  This can be used with the write transaction count to calculate the average write latency in the uncore.  The occupancy increments when a write request is issued, and decrements when the data is returned.; Tracks all requests from any source port unc_i_cache_own_occupancy.source uncore interconnect Outstanding Write Ownership Occupancy; Select Source event=0x13,umask=2  01    Accumulates the number of writes (and write prefetches) that are outstanding in the uncore trying to acquire ownership in each cycle.  This can be used with the write transaction count to calculate the average write latency in the uncore.  The occupancy increments when a write request is issued, and decrements when the data is returned.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register.  This register allows one to select one specific queue.  It is not possible to monitor multiple queues at a time unc_i_cache_read_occupancy.any uncore interconnect Outstanding Read Occupancy; Any Source event=0x10,umask=1  01    Accumulates the number of reads that are outstanding in the uncore in each cycle.  This can be used with the read transaction count to calculate the average read latency in the uncore.  The occupancy increments when a read request is issued, and decrements when the data is returned.; Tracks all requests from any source port unc_i_cache_read_occupancy.source uncore interconnect Outstanding Read Occupancy; Select Source event=0x10,umask=2  01    Accumulates the number of reads that are outstanding in the uncore in each cycle.  This can be used with the read transaction count to calculate the average read latency in the uncore.  The occupancy increments when a read request is issued, and decrements when the data is returned.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register.  This register allows one to select one specific queue.  It is not possible to monitor multiple queues at a time unc_i_cache_write_occupancy.any uncore interconnect Outstanding Write Occupancy; Any Source event=0x11,umask=1  01    Accumulates the number of writes (and write prefetches)  that are outstanding in the uncore in each cycle.  This can be used with the transaction count event to calculate the average latency in the uncore.  The occupancy increments when the ownership fetch/prefetch is issued, and decrements the data is returned to the uncore.; Tracks all requests from any source port unc_i_cache_write_occupancy.source uncore interconnect Outstanding Write Occupancy; Select Source event=0x11,umask=2  01    Accumulates the number of writes (and write prefetches)  that are outstanding in the uncore in each cycle.  This can be used with the transaction count event to calculate the average latency in the uncore.  The occupancy increments when the ownership fetch/prefetch is issued, and decrements the data is returned to the uncore.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register.  This register allows one to select one specific queue.  It is not possible to monitor multiple queues at a time unc_i_rxr_ak_cycles_full uncore interconnect  event=0xb  01    Counts the number of cycles when the AK Ingress is full.  This queue is where the IRP receives responses from R2PCIe (the ring) unc_i_rxr_ak_occupancy uncore interconnect  event=0xc  01    Accumulates the occupancy of the AK Ingress in each cycles.  This queue is where the IRP receives responses from R2PCIe (the ring) unc_i_rxr_bl_drs_cycles_full uncore interconnect  event=4  01    Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_drs_occupancy uncore interconnect  event=7  01    Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_ncb_cycles_full uncore interconnect  event=5  01    Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_ncb_occupancy uncore interconnect  event=8  01    Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_ncs_cycles_full uncore interconnect  event=6  01    Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requests as well as outbound MMIO writes unc_i_rxr_bl_ncs_occupancy uncore interconnect  event=9  01    Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requests as well as outbound MMIO writes unc_i_tickles.lost_ownership uncore interconnect Tickle Count; Ownership Lost event=0x16,umask=1  01    Counts the number of tickles that are received.  This is for both explicit (from Cbo) and implicit (internal conflict) tickles.; Tracks the number of requests that lost ownership as a result of a tickle.  When a tickle comes in, if the request is not at the head of the queue in the switch, then that request as well as any requests behind it in the switch queue will lose ownership and have to re-acquire it later when they get to the head of the queue.  This will therefore track the number of requests that lost ownership and not just the number of tickles unc_i_tickles.top_of_queue uncore interconnect Tickle Count; Data Returned event=0x16,umask=2  01    Counts the number of tickles that are received.  This is for both explicit (from Cbo) and implicit (internal conflict) tickles.; Tracks the number of cases when a tickle was received but the requests was at the head of the queue in the switch.  In this case, data is returned rather than releasing ownership unc_i_transactions.pd_prefetches uncore interconnect Inbound Transaction Count: Read Prefetches event=0x15,umask=4  01    Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID unc_i_transactions.rd_prefetches uncore interconnect Inbound Transaction Count; Read Prefetches event=0x15,umask=4  01    Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches unc_i_transactions.reads uncore interconnect Inbound Transaction Count; Reads event=0x15,umask=1  01    Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches) unc_i_transactions.writes uncore interconnect Inbound Transaction Count; Writes event=0x15,umask=2  01    Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests.  Each write request should have a prefetch, so there is no need to explicitly track these requests.  For writes that are tickled and have to retry, the counter will be incremented for each retry unc_i_write_ordering_stall_cycles uncore interconnect Write Ordering Stalls event=0x1a  01    Counts the number of cycles when there are pending write ACK's in the switch but the switch->IRP pipeline is not utilized unc_q_clockticks uncore interconnect Number of qfclks event=0x14  01    Counts the number of clocks in the QPI LL.  This clock runs at 1/8th the GT/s speed of the QPI link.  For example, a 8GT/s link will have qfclk or 1GHz.  JKT does not support dynamic link speeds, so this frequency is fixed unc_q_match_mask uncore interconnect  event=0x38  01     unc_q_message.drs.anydatac uncore interconnect  event=0x38  01     unc_q_message.drs.anyresp uncore interconnect  event=0x38  01     unc_q_message.drs.anyresp11flits uncore interconnect  event=0x38  01     unc_q_message.drs.anyresp9flits uncore interconnect  event=0x38  01     unc_q_message.drs.datac_e uncore interconnect  event=0x38  01     unc_q_message.drs.datac_e_cmp uncore interconnect  event=0x38  01     unc_q_message.drs.datac_e_frcackcnflt uncore interconnect  event=0x38  01     unc_q_message.drs.datac_f uncore interconnect  event=0x38  01     unc_q_message.drs.datac_f_cmp uncore interconnect  event=0x38  01     unc_q_message.drs.datac_f_frcackcnflt uncore interconnect  event=0x38  01     unc_q_message.drs.datac_m uncore interconnect  event=0x38  01     unc_q_message.drs.wbedata uncore interconnect  event=0x38  01     unc_q_message.drs.wbidata uncore interconnect  event=0x38  01     unc_q_message.drs.wbsdata uncore interconnect  event=0x38  01     unc_q_message.hom.anyreq uncore interconnect  event=0x38  01     unc_q_message.hom.anyresp uncore interconnect  event=0x38  01     unc_q_message.hom.respfwd uncore interconnect  event=0x38  01     unc_q_message.hom.respfwdi uncore interconnect  event=0x38  01     unc_q_message.hom.respfwdiwb uncore interconnect  event=0x38  01     unc_q_message.hom.respfwds uncore interconnect  event=0x38  01     unc_q_message.hom.respfwdswb uncore interconnect  event=0x38  01     unc_q_message.hom.respiwb uncore interconnect  event=0x38  01     unc_q_message.hom.respswb uncore interconnect  event=0x38  01     unc_q_message.ncb.anyint uncore interconnect  event=0x38  01     unc_q_message.ncb.anymsg uncore interconnect  event=0x38  01     unc_q_message.ncb.anymsg11flits uncore interconnect  event=0x38  01     unc_q_message.ncb.anymsg9flits uncore interconnect  event=0x38  01     unc_q_message.ncs.anymsg1or2flits uncore interconnect  event=0x38  01     unc_q_message.ncs.anymsg3flits uncore interconnect  event=0x38  01     unc_q_message.ncs.ncrd uncore interconnect  event=0x38  01     unc_q_message.ndr.anycmp uncore interconnect  event=0x38  01     unc_q_message.snp.anysnp uncore interconnect  event=0x38  01     unc_q_rxl_flits_g0.data uncore interconnect Flits Received - Group 0; Data Tx Flits event=1,umask=2  01    Counts the number of flits received from the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits received over QPI.  Each flit contains 64b of data.  This includes both DRS and NCB data flits (coherent and non-coherent).  This can be used to calculate the data bandwidth of the QPI link.  One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits.  This does not include the header flits that go in data packets unc_q_rxl_flits_g0.non_data uncore interconnect Flits Received - Group 0; Non-Data protocol Tx Flits event=1,umask=4  01    Counts the number of flits received from the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits received across QPI.  This basically tracks the protocol overhead on the QPI link.  One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits.  This includes the header flits for data packets unc_q_rxl_inserts_drs uncore interconnect Rx Flit Buffer Allocations - DRS event=9  01    Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only DRS flits unc_q_rxl_inserts_hom uncore interconnect Rx Flit Buffer Allocations - HOM event=0xc  01    Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only HOM flits unc_q_rxl_inserts_ncb uncore interconnect Rx Flit Buffer Allocations - NCB event=0xa  01    Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCB flits unc_q_rxl_inserts_ncs uncore interconnect Rx Flit Buffer Allocations - NCS event=0xb  01    Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCS flits unc_q_rxl_inserts_ndr uncore interconnect Rx Flit Buffer Allocations - NDR event=0xe  01    Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NDR flits unc_q_rxl_inserts_snp uncore interconnect Rx Flit Buffer Allocations - SNP event=0xd  01    Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only SNP flits unc_q_rxl_occupancy_drs uncore interconnect RxQ Occupancy - DRS event=0x15  01    Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors DRS flits only unc_q_rxl_occupancy_hom uncore interconnect RxQ Occupancy - HOM event=0x18  01    Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors HOM flits only unc_q_rxl_occupancy_ncb uncore interconnect RxQ Occupancy - NCB event=0x16  01    Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCB flits only unc_q_rxl_occupancy_ncs uncore interconnect RxQ Occupancy - NCS event=0x17  01    Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCS flits only unc_q_rxl_occupancy_ndr uncore interconnect RxQ Occupancy - NDR event=0x1a  01    Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NDR flits only unc_q_rxl_occupancy_snp uncore interconnect RxQ Occupancy - SNP event=0x19  01    Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors SNP flits only unc_q_txr_ak_ndr_credit_acquired.vn0 uncore interconnect R3QPI Egress Credit Occupancy - AK NDR: for VN0 event=0x29,umask=1  01    Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress unc_q_txr_ak_ndr_credit_acquired.vn1 uncore interconnect R3QPI Egress Credit Occupancy - AK NDR: for VN1 event=0x29,umask=2  01    Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress unc_q_txr_ak_ndr_credit_occupancy.vn0 uncore interconnect R3QPI Egress Credit Occupancy - AK NDR: for VN0 event=0x25,umask=1  01    Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  Local NDR message class to AK Egress unc_q_txr_ak_ndr_credit_occupancy.vn1 uncore interconnect R3QPI Egress Credit Occupancy - AK NDR: for VN1 event=0x25,umask=2  01    Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  Local NDR message class to AK Egress unc_r3_c_hi_ad_credits_empty.cbo10 uncore interconnect CBox AD Credits Empty event=0x2c,umask=4  01    No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 10 unc_r3_c_hi_ad_credits_empty.cbo11 uncore interconnect CBox AD Credits Empty event=0x2c,umask=8  01    No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 11 unc_r3_c_hi_ad_credits_empty.cbo12 uncore interconnect CBox AD Credits Empty event=0x2c,umask=0x10  01    No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 12 unc_r3_c_hi_ad_credits_empty.cbo13 uncore interconnect CBox AD Credits Empty event=0x2c,umask=0x20  01    No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 13 unc_r3_c_hi_ad_credits_empty.cbo14 uncore interconnect CBox AD Credits Empty event=0x2c,umask=0x40  01    No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 14&16 unc_r3_c_hi_ad_credits_empty.cbo8 uncore interconnect CBox AD Credits Empty event=0x2c,umask=1  01    No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 8 unc_r3_c_hi_ad_credits_empty.cbo9 uncore interconnect CBox AD Credits Empty event=0x2c,umask=2  01    No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 9 unc_r3_c_lo_ad_credits_empty.cbo0 uncore interconnect CBox AD Credits Empty event=0x2b,umask=1  01    No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 0 unc_r3_c_lo_ad_credits_empty.cbo1 uncore interconnect CBox AD Credits Empty event=0x2b,umask=2  01    No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 1 unc_r3_c_lo_ad_credits_empty.cbo2 uncore interconnect CBox AD Credits Empty event=0x2b,umask=4  01    No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 2 unc_r3_c_lo_ad_credits_empty.cbo3 uncore interconnect CBox AD Credits Empty event=0x2b,umask=8  01    No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 3 unc_r3_c_lo_ad_credits_empty.cbo4 uncore interconnect CBox AD Credits Empty event=0x2b,umask=0x10  01    No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 4 unc_r3_c_lo_ad_credits_empty.cbo5 uncore interconnect CBox AD Credits Empty event=0x2b,umask=0x20  01    No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 5 unc_r3_c_lo_ad_credits_empty.cbo6 uncore interconnect CBox AD Credits Empty event=0x2b,umask=0x40  01    No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 6 unc_r3_c_lo_ad_credits_empty.cbo7 uncore interconnect CBox AD Credits Empty event=0x2b,umask=0x80  01    No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 7 unc_r3_ha_r2_bl_credits_empty.ha0 uncore interconnect HA/R2 AD Credits Empty event=0x2f,umask=1  01    No credits available to send to either HA or R2 on the BL Ring; HA0 unc_r3_ha_r2_bl_credits_empty.ha1 uncore interconnect HA/R2 AD Credits Empty event=0x2f,umask=2  01    No credits available to send to either HA or R2 on the BL Ring; HA1 unc_r3_ha_r2_bl_credits_empty.r2_ncb uncore interconnect HA/R2 AD Credits Empty event=0x2f,umask=4  01    No credits available to send to either HA or R2 on the BL Ring; R2 NCB Messages unc_r3_ha_r2_bl_credits_empty.r2_ncs uncore interconnect HA/R2 AD Credits Empty event=0x2f,umask=8  01    No credits available to send to either HA or R2 on the BL Ring; R2 NCS Messages unc_r3_qpi0_ad_credits_empty.vn0_hom uncore interconnect QPI0 AD Credits Empty event=0x29,umask=2  01    No credits available to send to QPI0 on the AD Ring; VN0 HOM Messages unc_r3_qpi0_ad_credits_empty.vn0_ndr uncore interconnect QPI0 AD Credits Empty event=0x29,umask=8  01    No credits available to send to QPI0 on the AD Ring; VN0 NDR Messages unc_r3_qpi0_ad_credits_empty.vn0_snp uncore interconnect QPI0 AD Credits Empty event=0x29,umask=4  01    No credits available to send to QPI0 on the AD Ring; VN0 SNP Messages unc_r3_qpi0_ad_credits_empty.vn1_hom uncore interconnect QPI0 AD Credits Empty event=0x29,umask=0x10  01    No credits available to send to QPI0 on the AD Ring; VN1 HOM Messages unc_r3_qpi0_ad_credits_empty.vn1_ndr uncore interconnect QPI0 AD Credits Empty event=0x29,umask=0x40  01    No credits available to send to QPI0 on the AD Ring; VN1 NDR Messages unc_r3_qpi0_ad_credits_empty.vn1_snp uncore interconnect QPI0 AD Credits Empty event=0x29,umask=0x20  01    No credits available to send to QPI0 on the AD Ring; VN1 SNP Messages unc_r3_qpi0_ad_credits_empty.vna uncore interconnect QPI0 AD Credits Empty event=0x29,umask=1  01    No credits available to send to QPI0 on the AD Ring; VNA unc_r3_qpi0_bl_credits_empty.vn0_hom uncore interconnect QPI0 BL Credits Empty event=0x2d,umask=2  01    No credits available to send to QPI0 on the BL Ring; VN0 HOM Messages unc_r3_qpi0_bl_credits_empty.vn0_ndr uncore interconnect QPI0 BL Credits Empty event=0x2d,umask=8  01    No credits available to send to QPI0 on the BL Ring; VN0 NDR Messages unc_r3_qpi0_bl_credits_empty.vn0_snp uncore interconnect QPI0 BL Credits Empty event=0x2d,umask=4  01    No credits available to send to QPI0 on the BL Ring; VN0 SNP Messages unc_r3_qpi0_bl_credits_empty.vn1_hom uncore interconnect QPI0 BL Credits Empty event=0x2d,umask=0x10  01    No credits available to send to QPI0 on the BL Ring; VN1 HOM Messages unc_r3_qpi0_bl_credits_empty.vn1_ndr uncore interconnect QPI0 BL Credits Empty event=0x2d,umask=0x40  01    No credits available to send to QPI0 on the BL Ring; VN1 NDR Messages unc_r3_qpi0_bl_credits_empty.vn1_snp uncore interconnect QPI0 BL Credits Empty event=0x2d,umask=0x20  01    No credits available to send to QPI0 on the BL Ring; VN1 SNP Messages unc_r3_qpi0_bl_credits_empty.vna uncore interconnect QPI0 BL Credits Empty event=0x2d,umask=1  01    No credits available to send to QPI0 on the BL Ring; VNA unc_r3_qpi1_ad_credits_empty.vn0_hom uncore interconnect QPI1 AD Credits Empty event=0x2a,umask=2  01    No credits available to send to QPI1 on the AD Ring; VN0 HOM Messages unc_r3_qpi1_ad_credits_empty.vn0_ndr uncore interconnect QPI1 AD Credits Empty event=0x2a,umask=8  01    No credits available to send to QPI1 on the AD Ring; VN0 NDR Messages unc_r3_qpi1_ad_credits_empty.vn0_snp uncore interconnect QPI1 AD Credits Empty event=0x2a,umask=4  01    No credits available to send to QPI1 on the AD Ring; VN0 SNP Messages unc_r3_qpi1_ad_credits_empty.vn1_hom uncore interconnect QPI1 AD Credits Empty event=0x2a,umask=0x10  01    No credits available to send to QPI1 on the AD Ring; VN1 HOM Messages unc_r3_qpi1_ad_credits_empty.vn1_ndr uncore interconnect QPI1 AD Credits Empty event=0x2a,umask=0x40  01    No credits available to send to QPI1 on the AD Ring; VN1 NDR Messages unc_r3_qpi1_ad_credits_empty.vn1_snp uncore interconnect QPI1 AD Credits Empty event=0x2a,umask=0x20  01    No credits available to send to QPI1 on the AD Ring; VN1 SNP Messages unc_r3_qpi1_ad_credits_empty.vna uncore interconnect QPI1 AD Credits Empty event=0x2a,umask=1  01    No credits available to send to QPI1 on the AD Ring; VNA unc_r3_qpi1_bl_credits_empty.vn0_hom uncore interconnect QPI1 BL Credits Empty event=0x2e,umask=2  01    No credits available to send to QPI1 on the BL Ring; VN0 HOM Messages unc_r3_qpi1_bl_credits_empty.vn0_ndr uncore interconnect QPI1 BL Credits Empty event=0x2e,umask=8  01    No credits available to send to QPI1 on the BL Ring; VN0 NDR Messages unc_r3_qpi1_bl_credits_empty.vn0_snp uncore interconnect QPI1 BL Credits Empty event=0x2e,umask=4  01    No credits available to send to QPI1 on the BL Ring; VN0 SNP Messages unc_r3_qpi1_bl_credits_empty.vn1_hom uncore interconnect QPI1 BL Credits Empty event=0x2e,umask=0x10  01    No credits available to send to QPI1 on the BL Ring; VN1 HOM Messages unc_r3_qpi1_bl_credits_empty.vn1_ndr uncore interconnect QPI1 BL Credits Empty event=0x2e,umask=0x40  01    No credits available to send to QPI1 on the BL Ring; VN1 NDR Messages unc_r3_qpi1_bl_credits_empty.vn1_snp uncore interconnect QPI1 BL Credits Empty event=0x2e,umask=0x20  01    No credits available to send to QPI1 on the BL Ring; VN1 SNP Messages unc_r3_qpi1_bl_credits_empty.vna uncore interconnect QPI1 BL Credits Empty event=0x2e,umask=1  01    No credits available to send to QPI1 on the BL Ring; VNA unc_r3_ring_ad_used.ccw uncore interconnect R3 AD Ring in Use; Counterclockwise event=7,umask=0xcc  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ad_used.ccw_vr0_even uncore interconnect R3 AD Ring in Use; Counterclockwise and Even on VRing 0 event=7,umask=4  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0 unc_r3_ring_ad_used.ccw_vr0_odd uncore interconnect R3 AD Ring in Use; Counterclockwise and Odd on VRing 0 event=7,umask=8  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0 unc_r3_ring_ad_used.cw uncore interconnect R3 AD Ring in Use; Clockwise event=7,umask=0x33  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ad_used.cw_vr0_even uncore interconnect R3 AD Ring in Use; Clockwise and Even on VRing 0 event=7,umask=1  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0 unc_r3_ring_ad_used.cw_vr0_odd uncore interconnect R3 AD Ring in Use; Clockwise and Odd on VRing 0 event=7,umask=2  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0 unc_r3_ring_ak_used.ccw uncore interconnect R3 AK Ring in Use; Counterclockwise event=8,umask=0xcc  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ak_used.ccw_vr0_even uncore interconnect R3 AK Ring in Use; Counterclockwise and Even on VRing 0 event=8,umask=4  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0 unc_r3_ring_ak_used.ccw_vr0_odd uncore interconnect R3 AK Ring in Use; Counterclockwise and Odd on VRing 0 event=8,umask=8  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0 unc_r3_ring_ak_used.cw uncore interconnect R3 AK Ring in Use; Clockwise event=8,umask=0x33  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ak_used.cw_vr0_even uncore interconnect R3 AK Ring in Use; Clockwise and Even on VRing 0 event=8,umask=1  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0 unc_r3_ring_ak_used.cw_vr0_odd uncore interconnect R3 AK Ring in Use; Clockwise and Odd on VRing 0 event=8,umask=2  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0 unc_r3_ring_bl_used.ccw uncore interconnect R3 BL Ring in Use; Counterclockwise event=9,umask=0xcc  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_bl_used.ccw_vr0_even uncore interconnect R3 BL Ring in Use; Counterclockwise and Even on VRing 0 event=9,umask=4  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0 unc_r3_ring_bl_used.ccw_vr0_odd uncore interconnect R3 BL Ring in Use; Counterclockwise and Odd on VRing 0 event=9,umask=8  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0 unc_r3_ring_bl_used.cw uncore interconnect R3 BL Ring in Use; Clockwise event=9,umask=0x33  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_bl_used.cw_vr0_even uncore interconnect R3 BL Ring in Use; Clockwise and Even on VRing 0 event=9,umask=1  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0 unc_r3_ring_bl_used.cw_vr0_odd uncore interconnect R3 BL Ring in Use; Clockwise and Odd on VRing 0 event=9,umask=2  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0 unc_r3_ring_iv_used.any uncore interconnect R2 IV Ring in Use; Any event=0xa,umask=0xff  01    Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  The IV ring is unidirectional.  Whether UP or DN is used is dependent on the system programming.  Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters any polarity unc_r3_ring_iv_used.ccw uncore interconnect R2 IV Ring in Use; Counterclockwise event=0xa,umask=0xcc  01    Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  The IV ring is unidirectional.  Whether UP or DN is used is dependent on the system programming.  Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Counterclockwise polarity unc_r3_ring_iv_used.cw uncore interconnect R2 IV Ring in Use; Clockwise event=0xa,umask=0x33  01    Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  The IV ring is unidirectional.  Whether UP or DN is used is dependent on the system programming.  Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Clockwise polarity unc_r3_rxr_ad_bypassed uncore interconnect AD Ingress Bypassed event=0x12  01    Counts the number of times when the AD Ingress was bypassed and an incoming transaction was bypassed directly across the BGF and into the qfclk domain unc_r3_rxr_bypassed.ad uncore interconnect Ingress Bypassed event=0x12,umask=1  01    Counts the number of times when the Ingress was bypassed and an incoming transaction was bypassed directly across the BGF and into the qfclk domain unc_r3_rxr_occupancy.drs uncore interconnect Ingress Occupancy Accumulator; DRS event=0x13,umask=8  01    Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue unc_r3_rxr_occupancy.hom uncore interconnect Ingress Occupancy Accumulator; HOM event=0x13,umask=1  01    Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; HOM Ingress Queue unc_r3_rxr_occupancy.ncb uncore interconnect Ingress Occupancy Accumulator; NCB event=0x13,umask=0x10  01    Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; NCB Ingress Queue unc_r3_rxr_occupancy.ncs uncore interconnect Ingress Occupancy Accumulator; NCS event=0x13,umask=0x20  01    Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; NCS Ingress Queue unc_r3_rxr_occupancy.ndr uncore interconnect Ingress Occupancy Accumulator; NDR event=0x13,umask=4  01    Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; NDR Ingress Queue unc_r3_rxr_occupancy.snp uncore interconnect Ingress Occupancy Accumulator; SNP event=0x13,umask=2  01    Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; SNP Ingress Queue unc_r3_txr_nack_ccw.ad uncore interconnect Egress NACK; AK CCW event=0x28,umask=1  01    BL CounterClockwise Egress Queue unc_r3_txr_nack_ccw.ak uncore interconnect Egress NACK; BL CW event=0x28,umask=2  01    AD Clockwise Egress Queue unc_r3_txr_nack_ccw.bl uncore interconnect Egress NACK; BL CCW event=0x28,umask=4  01    AD CounterClockwise Egress Queue unc_r3_txr_nack_cw.ad uncore interconnect Egress NACK; AD CW event=0x26,umask=1  01    AD Clockwise Egress Queue unc_r3_txr_nack_cw.ak uncore interconnect Egress NACK; AD CCW event=0x26,umask=2  01    AD CounterClockwise Egress Queue unc_r3_txr_nack_cw.bl uncore interconnect Egress NACK; AK CW event=0x26,umask=4  01    BL Clockwise Egress Queue unc_r3_vna_credits_acquired uncore interconnect VNA credit Acquisitions event=0x33  01    Number of QPI VNA Credit acquisitions.  This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder.  VNA credits are used by all message classes in order to communicate across QPI.  If a packet is unable to acquire credits, it will then attempt to use credits from the VN0 pool.  Note that a single packet may require multiple flit buffers (i.e. when data is being transferred).  Therefore, this event will increment by the number of credits acquired in each cycle.  Filtering based on message class is not provided.  One can count the number of packets transferred in a given message class using an qfclk event unc_r3_vna_credit_cycles_out uncore interconnect Cycles with no VNA credits available event=0x31  01    Number of QPI uclk cycles when the transmitted has no VNA credits available and therefore cannot send any requests on this channel.  Note that this does not mean that no flits can be transmitted, as those holding VN0 credits will still (potentially) be able to transmit.  Generally it is the goal of the uncore that VNA credits should not run out, as this can substantially throttle back useful QPI bandwidth unc_r3_vna_credit_cycles_used uncore interconnect Cycles with 1 or more VNA credits in use event=0x32  01    Number of QPI uclk cycles with one or more VNA credits in use.  This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average number of used VNA credits unc_u_clockticks uncore interconnect  event=0  01     unc_u_event_msg.int_prio uncore interconnect VLW Received event=0x42,umask=0x10  01    Virtual Logical Wire (legacy) message were received from Uncore.   Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID unc_u_event_msg.ipi_rcvd uncore interconnect VLW Received event=0x42,umask=4  01    Virtual Logical Wire (legacy) message were received from Uncore.   Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID unc_u_event_msg.msi_rcvd uncore interconnect VLW Received event=0x42,umask=2  01    Virtual Logical Wire (legacy) message were received from Uncore.   Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID unc_u_event_msg.vlw_rcvd uncore interconnect VLW Received event=0x42,umask=1  01    Virtual Logical Wire (legacy) message were received from Uncore.   Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID unc_u_racu_requests uncore interconnect RACU Request event=0x46  01     unc_r2_iio_credits_reject.drs uncore io R2PCIe IIO Failed to Acquire a Credit; DRS event=0x34,umask=8  01    Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class unc_r2_ring_ad_used.ccw uncore io R2 AD Ring in Use; Counterclockwise event=7,umask=0xcc  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ad_used.ccw_vr0_even uncore io R2 AD Ring in Use; Counterclockwise and Even on VRing 0 event=7,umask=4  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0 unc_r2_ring_ad_used.ccw_vr0_odd uncore io R2 AD Ring in Use; Counterclockwise and Odd on VRing 0 event=7,umask=8  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0 unc_r2_ring_ad_used.ccw_vr1_even uncore io R2 AD Ring in Use; Counterclockwise and Even on VRing 1 event=7,umask=0x40  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1 unc_r2_ring_ad_used.ccw_vr1_odd uncore io R2 AD Ring in Use; Counterclockwise and Odd on VRing 1 event=7,umask=0x80  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1 unc_r2_ring_ad_used.cw uncore io R2 AD Ring in Use; Clockwise event=7,umask=0x33  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ad_used.cw_vr0_even uncore io R2 AD Ring in Use; Clockwise and Even on VRing 0 event=7,umask=1  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0 unc_r2_ring_ad_used.cw_vr0_odd uncore io R2 AD Ring in Use; Clockwise and Odd on VRing 0 event=7,umask=2  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0 unc_r2_ring_ad_used.cw_vr1_even uncore io R2 AD Ring in Use; Clockwise and Even on VRing 1 event=7,umask=0x10  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1 unc_r2_ring_ad_used.cw_vr1_odd uncore io R2 AD Ring in Use; Clockwise and Odd on VRing 1 event=7,umask=0x20  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1 unc_r2_ring_ak_used.ccw uncore io R2 AK Ring in Use; Counterclockwise event=8,umask=0xcc  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ak_used.ccw_vr0_even uncore io R2 AK Ring in Use; Counterclockwise and Even on VRing 0 event=8,umask=4  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0 unc_r2_ring_ak_used.ccw_vr0_odd uncore io R2 AK Ring in Use; Counterclockwise and Odd on VRing 0 event=8,umask=8  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0 unc_r2_ring_ak_used.ccw_vr1_even uncore io R2 AK Ring in Use; Counterclockwise and Even on VRing 1 event=8,umask=0x40  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1 unc_r2_ring_ak_used.ccw_vr1_odd uncore io R2 AK Ring in Use; Counterclockwise and Odd on VRing 1 event=8,umask=0x80  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1 unc_r2_ring_ak_used.cw uncore io R2 AK Ring in Use; Clockwise event=8,umask=0x33  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ak_used.cw_vr0_even uncore io R2 AK Ring in Use; Clockwise and Even on VRing 0 event=8,umask=1  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0 unc_r2_ring_ak_used.cw_vr0_odd uncore io R2 AK Ring in Use; Clockwise and Odd on VRing 0 event=8,umask=2  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0 unc_r2_ring_ak_used.cw_vr1_even uncore io R2 AK Ring in Use; Clockwise and Even on VRing 1 event=8,umask=0x10  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1 unc_r2_ring_ak_used.cw_vr1_odd uncore io R2 AK Ring in Use; Clockwise and Odd on VRing 1 event=8,umask=0x20  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1 unc_r2_ring_bl_used.ccw uncore io R2 BL Ring in Use; Counterclockwise event=9,umask=0xcc  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_bl_used.ccw_vr0_even uncore io R2 BL Ring in Use; Counterclockwise and Even on VRing 0 event=9,umask=4  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0 unc_r2_ring_bl_used.ccw_vr0_odd uncore io R2 BL Ring in Use; Counterclockwise and Odd on VRing 0 event=9,umask=8  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0 unc_r2_ring_bl_used.ccw_vr1_even uncore io R2 BL Ring in Use; Counterclockwise and Even on VRing 1 event=9,umask=0x40  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1 unc_r2_ring_bl_used.ccw_vr1_odd uncore io R2 BL Ring in Use; Counterclockwise and Odd on VRing 1 event=9,umask=0x80  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1 unc_r2_ring_bl_used.cw uncore io R2 BL Ring in Use; Clockwise event=9,umask=0x33  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_bl_used.cw_vr0_even uncore io R2 BL Ring in Use; Clockwise and Even on VRing 0 event=9,umask=1  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0 unc_r2_ring_bl_used.cw_vr0_odd uncore io R2 BL Ring in Use; Clockwise and Odd on VRing 0 event=9,umask=2  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0 unc_r2_ring_bl_used.cw_vr1_even uncore io R2 BL Ring in Use; Clockwise and Even on VRing 1 event=9,umask=0x10  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1 unc_r2_ring_bl_used.cw_vr1_odd uncore io R2 BL Ring in Use; Clockwise and Odd on VRing 1 event=9,umask=0x20  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1 unc_r2_ring_iv_used.any uncore io R2 IV Ring in Use; Any event=0xa,umask=0xff  01    Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  The IV ring is unidirectional.  Whether UP or DN is used is dependent on the system programming.  Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters any polarity unc_r2_ring_iv_used.ccw uncore io R2 IV Ring in Use; Counterclockwise event=0xa,umask=0xcc  01    Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  The IV ring is unidirectional.  Whether UP or DN is used is dependent on the system programming.  Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Counterclockwise polarity unc_r2_ring_iv_used.cw uncore io R2 IV Ring in Use; Clockwise event=0xa,umask=0x33  01    Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  The IV ring is unidirectional.  Whether UP or DN is used is dependent on the system programming.  Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Clockwise polarity unc_r2_rxr_ak_bounces uncore io AK Ingress Bounced event=0x12  01    Counts the number of times when a request destined for the AK ingress bounced unc_r2_rxr_ak_bounces.ccw uncore io AK Ingress Bounced; Counterclockwise event=0x12,umask=2  01    Counts the number of times when a request destined for the AK ingress bounced unc_r2_rxr_ak_bounces.cw uncore io AK Ingress Bounced; Clockwise event=0x12,umask=1  01    Counts the number of times when a request destined for the AK ingress bounced unc_r2_txr_nack_ccw.ad uncore io Egress CCW NACK; AD CCW event=0x28,umask=1  01    AD CounterClockwise Egress Queue unc_r2_txr_nack_ccw.ak uncore io Egress CCW NACK; AK CCW event=0x28,umask=2  01    AK CounterClockwise Egress Queue unc_r2_txr_nack_ccw.bl uncore io Egress CCW NACK; BL CCW event=0x28,umask=4  01    BL CounterClockwise Egress Queue unc_r2_txr_nack_cw.ad uncore io Egress CW NACK; AD CW event=0x26,umask=1  01    AD Clockwise Egress Queue unc_r2_txr_nack_cw.ak uncore io Egress CW NACK; AK CW event=0x26,umask=2  01    AK Clockwise Egress Queue unc_r2_txr_nack_cw.bl uncore io Egress CW NACK; BL CW event=0x26,umask=4  01    BL Clockwise Egress Queue unc_m_power_pcu_throttling uncore memory  event=0x42  01     unc_m_rd_cas_rank0.bank0 uncore memory RD_CAS Access to Rank 0; Bank 0 event=0xb0,umask=1  01     unc_m_rd_cas_rank0.bank1 uncore memory RD_CAS Access to Rank 0; Bank 1 event=0xb0,umask=2  01     unc_m_rd_cas_rank0.bank2 uncore memory RD_CAS Access to Rank 0; Bank 2 event=0xb0,umask=4  01     unc_m_rd_cas_rank0.bank3 uncore memory RD_CAS Access to Rank 0; Bank 3 event=0xb0,umask=8  01     unc_m_rd_cas_rank0.bank4 uncore memory RD_CAS Access to Rank 0; Bank 4 event=0xb0,umask=0x10  01     unc_m_rd_cas_rank0.bank5 uncore memory RD_CAS Access to Rank 0; Bank 5 event=0xb0,umask=0x20  01     unc_m_rd_cas_rank0.bank6 uncore memory RD_CAS Access to Rank 0; Bank 6 event=0xb0,umask=0x40  01     unc_m_rd_cas_rank0.bank7 uncore memory RD_CAS Access to Rank 0; Bank 7 event=0xb0,umask=0x80  01     unc_m_rd_cas_rank1.bank0 uncore memory RD_CAS Access to Rank 1; Bank 0 event=0xb1,umask=1  01     unc_m_rd_cas_rank1.bank1 uncore memory RD_CAS Access to Rank 1; Bank 1 event=0xb1,umask=2  01     unc_m_rd_cas_rank1.bank2 uncore memory RD_CAS Access to Rank 1; Bank 2 event=0xb1,umask=4  01     unc_m_rd_cas_rank1.bank3 uncore memory RD_CAS Access to Rank 1; Bank 3 event=0xb1,umask=8  01     unc_m_rd_cas_rank1.bank4 uncore memory RD_CAS Access to Rank 1; Bank 4 event=0xb1,umask=0x10  01     unc_m_rd_cas_rank1.bank5 uncore memory RD_CAS Access to Rank 1; Bank 5 event=0xb1,umask=0x20  01     unc_m_rd_cas_rank1.bank6 uncore memory RD_CAS Access to Rank 1; Bank 6 event=0xb1,umask=0x40  01     unc_m_rd_cas_rank1.bank7 uncore memory RD_CAS Access to Rank 1; Bank 7 event=0xb1,umask=0x80  01     unc_m_rd_cas_rank2.bank0 uncore memory RD_CAS Access to Rank 2; Bank 0 event=0xb2,umask=1  01     unc_m_rd_cas_rank2.bank1 uncore memory RD_CAS Access to Rank 2; Bank 1 event=0xb2,umask=2  01     unc_m_rd_cas_rank2.bank2 uncore memory RD_CAS Access to Rank 2; Bank 2 event=0xb2,umask=4  01     unc_m_rd_cas_rank2.bank3 uncore memory RD_CAS Access to Rank 2; Bank 3 event=0xb2,umask=8  01     unc_m_rd_cas_rank2.bank4 uncore memory RD_CAS Access to Rank 2; Bank 4 event=0xb2,umask=0x10  01     unc_m_rd_cas_rank2.bank5 uncore memory RD_CAS Access to Rank 2; Bank 5 event=0xb2,umask=0x20  01     unc_m_rd_cas_rank2.bank6 uncore memory RD_CAS Access to Rank 2; Bank 6 event=0xb2,umask=0x40  01     unc_m_rd_cas_rank2.bank7 uncore memory RD_CAS Access to Rank 2; Bank 7 event=0xb2,umask=0x80  01     unc_m_rd_cas_rank3.bank0 uncore memory RD_CAS Access to Rank 3; Bank 0 event=0xb3,umask=1  01     unc_m_rd_cas_rank3.bank1 uncore memory RD_CAS Access to Rank 3; Bank 1 event=0xb3,umask=2  01     unc_m_rd_cas_rank3.bank2 uncore memory RD_CAS Access to Rank 3; Bank 2 event=0xb3,umask=4  01     unc_m_rd_cas_rank3.bank3 uncore memory RD_CAS Access to Rank 3; Bank 3 event=0xb3,umask=8  01     unc_m_rd_cas_rank3.bank4 uncore memory RD_CAS Access to Rank 3; Bank 4 event=0xb3,umask=0x10  01     unc_m_rd_cas_rank3.bank5 uncore memory RD_CAS Access to Rank 3; Bank 5 event=0xb3,umask=0x20  01     unc_m_rd_cas_rank3.bank6 uncore memory RD_CAS Access to Rank 3; Bank 6 event=0xb3,umask=0x40  01     unc_m_rd_cas_rank3.bank7 uncore memory RD_CAS Access to Rank 3; Bank 7 event=0xb3,umask=0x80  01     unc_m_rd_cas_rank4.bank0 uncore memory RD_CAS Access to Rank 4; Bank 0 event=0xb4,umask=1  01     unc_m_rd_cas_rank4.bank1 uncore memory RD_CAS Access to Rank 4; Bank 1 event=0xb4,umask=2  01     unc_m_rd_cas_rank4.bank2 uncore memory RD_CAS Access to Rank 4; Bank 2 event=0xb4,umask=4  01     unc_m_rd_cas_rank4.bank3 uncore memory RD_CAS Access to Rank 4; Bank 3 event=0xb4,umask=8  01     unc_m_rd_cas_rank4.bank4 uncore memory RD_CAS Access to Rank 4; Bank 4 event=0xb4,umask=0x10  01     unc_m_rd_cas_rank4.bank5 uncore memory RD_CAS Access to Rank 4; Bank 5 event=0xb4,umask=0x20  01     unc_m_rd_cas_rank4.bank6 uncore memory RD_CAS Access to Rank 4; Bank 6 event=0xb4,umask=0x40  01     unc_m_rd_cas_rank4.bank7 uncore memory RD_CAS Access to Rank 4; Bank 7 event=0xb4,umask=0x80  01     unc_m_rd_cas_rank5.bank0 uncore memory RD_CAS Access to Rank 5; Bank 0 event=0xb5,umask=1  01     unc_m_rd_cas_rank5.bank1 uncore memory RD_CAS Access to Rank 5; Bank 1 event=0xb5,umask=2  01     unc_m_rd_cas_rank5.bank2 uncore memory RD_CAS Access to Rank 5; Bank 2 event=0xb5,umask=4  01     unc_m_rd_cas_rank5.bank3 uncore memory RD_CAS Access to Rank 5; Bank 3 event=0xb5,umask=8  01     unc_m_rd_cas_rank5.bank4 uncore memory RD_CAS Access to Rank 5; Bank 4 event=0xb5,umask=0x10  01     unc_m_rd_cas_rank5.bank5 uncore memory RD_CAS Access to Rank 5; Bank 5 event=0xb5,umask=0x20  01     unc_m_rd_cas_rank5.bank6 uncore memory RD_CAS Access to Rank 5; Bank 6 event=0xb5,umask=0x40  01     unc_m_rd_cas_rank5.bank7 uncore memory RD_CAS Access to Rank 5; Bank 7 event=0xb5,umask=0x80  01     unc_m_rd_cas_rank6.bank0 uncore memory RD_CAS Access to Rank 6; Bank 0 event=0xb6,umask=1  01     unc_m_rd_cas_rank6.bank1 uncore memory RD_CAS Access to Rank 6; Bank 1 event=0xb6,umask=2  01     unc_m_rd_cas_rank6.bank2 uncore memory RD_CAS Access to Rank 6; Bank 2 event=0xb6,umask=4  01     unc_m_rd_cas_rank6.bank3 uncore memory RD_CAS Access to Rank 6; Bank 3 event=0xb6,umask=8  01     unc_m_rd_cas_rank6.bank4 uncore memory RD_CAS Access to Rank 6; Bank 4 event=0xb6,umask=0x10  01     unc_m_rd_cas_rank6.bank5 uncore memory RD_CAS Access to Rank 6; Bank 5 event=0xb6,umask=0x20  01     unc_m_rd_cas_rank6.bank6 uncore memory RD_CAS Access to Rank 6; Bank 6 event=0xb6,umask=0x40  01     unc_m_rd_cas_rank6.bank7 uncore memory RD_CAS Access to Rank 6; Bank 7 event=0xb6,umask=0x80  01     unc_m_rd_cas_rank7.bank0 uncore memory RD_CAS Access to Rank 7; Bank 0 event=0xb7,umask=1  01     unc_m_rd_cas_rank7.bank1 uncore memory RD_CAS Access to Rank 7; Bank 1 event=0xb7,umask=2  01     unc_m_rd_cas_rank7.bank2 uncore memory RD_CAS Access to Rank 7; Bank 2 event=0xb7,umask=4  01     unc_m_rd_cas_rank7.bank3 uncore memory RD_CAS Access to Rank 7; Bank 3 event=0xb7,umask=8  01     unc_m_rd_cas_rank7.bank4 uncore memory RD_CAS Access to Rank 7; Bank 4 event=0xb7,umask=0x10  01     unc_m_rd_cas_rank7.bank5 uncore memory RD_CAS Access to Rank 7; Bank 5 event=0xb7,umask=0x20  01     unc_m_rd_cas_rank7.bank6 uncore memory RD_CAS Access to Rank 7; Bank 6 event=0xb7,umask=0x40  01     unc_m_rd_cas_rank7.bank7 uncore memory RD_CAS Access to Rank 7; Bank 7 event=0xb7,umask=0x80  01     unc_m_wpq_inserts uncore memory Write Pending Queue Allocations event=0x20  01    Counts the number of allocations into the Write Pending Queue.  This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC unc_m_wr_cas_rank0.bank0 uncore memory WR_CAS Access to Rank 0; Bank 0 event=0xb8,umask=1  01     unc_m_wr_cas_rank0.bank1 uncore memory WR_CAS Access to Rank 0; Bank 1 event=0xb8,umask=2  01     unc_m_wr_cas_rank0.bank2 uncore memory WR_CAS Access to Rank 0; Bank 2 event=0xb8,umask=4  01     unc_m_wr_cas_rank0.bank3 uncore memory WR_CAS Access to Rank 0; Bank 3 event=0xb8,umask=8  01     unc_m_wr_cas_rank0.bank4 uncore memory WR_CAS Access to Rank 0; Bank 4 event=0xb8,umask=0x10  01     unc_m_wr_cas_rank0.bank5 uncore memory WR_CAS Access to Rank 0; Bank 5 event=0xb8,umask=0x20  01     unc_m_wr_cas_rank0.bank6 uncore memory WR_CAS Access to Rank 0; Bank 6 event=0xb8,umask=0x40  01     unc_m_wr_cas_rank0.bank7 uncore memory WR_CAS Access to Rank 0; Bank 7 event=0xb8,umask=0x80  01     unc_m_wr_cas_rank1.bank0 uncore memory WR_CAS Access to Rank 1; Bank 0 event=0xb9,umask=1  01     unc_m_wr_cas_rank1.bank1 uncore memory WR_CAS Access to Rank 1; Bank 1 event=0xb9,umask=2  01     unc_m_wr_cas_rank1.bank2 uncore memory WR_CAS Access to Rank 1; Bank 2 event=0xb9,umask=4  01     unc_m_wr_cas_rank1.bank3 uncore memory WR_CAS Access to Rank 1; Bank 3 event=0xb9,umask=8  01     unc_m_wr_cas_rank1.bank4 uncore memory WR_CAS Access to Rank 1; Bank 4 event=0xb9,umask=0x10  01     unc_m_wr_cas_rank1.bank5 uncore memory WR_CAS Access to Rank 1; Bank 5 event=0xb9,umask=0x20  01     unc_m_wr_cas_rank1.bank6 uncore memory WR_CAS Access to Rank 1; Bank 6 event=0xb9,umask=0x40  01     unc_m_wr_cas_rank1.bank7 uncore memory WR_CAS Access to Rank 1; Bank 7 event=0xb9,umask=0x80  01     unc_m_wr_cas_rank2.bank0 uncore memory WR_CAS Access to Rank 2; Bank 0 event=0xba,umask=1  01     unc_m_wr_cas_rank2.bank1 uncore memory WR_CAS Access to Rank 2; Bank 1 event=0xba,umask=2  01     unc_m_wr_cas_rank2.bank2 uncore memory WR_CAS Access to Rank 2; Bank 2 event=0xba,umask=4  01     unc_m_wr_cas_rank2.bank3 uncore memory WR_CAS Access to Rank 2; Bank 3 event=0xba,umask=8  01     unc_m_wr_cas_rank2.bank4 uncore memory WR_CAS Access to Rank 2; Bank 4 event=0xba,umask=0x10  01     unc_m_wr_cas_rank2.bank5 uncore memory WR_CAS Access to Rank 2; Bank 5 event=0xba,umask=0x20  01     unc_m_wr_cas_rank2.bank6 uncore memory WR_CAS Access to Rank 2; Bank 6 event=0xba,umask=0x40  01     unc_m_wr_cas_rank2.bank7 uncore memory WR_CAS Access to Rank 2; Bank 7 event=0xba,umask=0x80  01     unc_m_wr_cas_rank3.bank0 uncore memory WR_CAS Access to Rank 3; Bank 0 event=0xbb,umask=1  01     unc_m_wr_cas_rank3.bank1 uncore memory WR_CAS Access to Rank 3; Bank 1 event=0xbb,umask=2  01     unc_m_wr_cas_rank3.bank2 uncore memory WR_CAS Access to Rank 3; Bank 2 event=0xbb,umask=4  01     unc_m_wr_cas_rank3.bank3 uncore memory WR_CAS Access to Rank 3; Bank 3 event=0xbb,umask=8  01     unc_m_wr_cas_rank3.bank4 uncore memory WR_CAS Access to Rank 3; Bank 4 event=0xbb,umask=0x10  01     unc_m_wr_cas_rank3.bank5 uncore memory WR_CAS Access to Rank 3; Bank 5 event=0xbb,umask=0x20  01     unc_m_wr_cas_rank3.bank6 uncore memory WR_CAS Access to Rank 3; Bank 6 event=0xbb,umask=0x40  01     unc_m_wr_cas_rank3.bank7 uncore memory WR_CAS Access to Rank 3; Bank 7 event=0xbb,umask=0x80  01     unc_m_wr_cas_rank4.bank0 uncore memory WR_CAS Access to Rank 4; Bank 0 event=0xbc,umask=1  01     unc_m_wr_cas_rank4.bank1 uncore memory WR_CAS Access to Rank 4; Bank 1 event=0xbc,umask=2  01     unc_m_wr_cas_rank4.bank2 uncore memory WR_CAS Access to Rank 4; Bank 2 event=0xbc,umask=4  01     unc_m_wr_cas_rank4.bank3 uncore memory WR_CAS Access to Rank 4; Bank 3 event=0xbc,umask=8  01     unc_m_wr_cas_rank4.bank4 uncore memory WR_CAS Access to Rank 4; Bank 4 event=0xbc,umask=0x10  01     unc_m_wr_cas_rank4.bank5 uncore memory WR_CAS Access to Rank 4; Bank 5 event=0xbc,umask=0x20  01     unc_m_wr_cas_rank4.bank6 uncore memory WR_CAS Access to Rank 4; Bank 6 event=0xbc,umask=0x40  01     unc_m_wr_cas_rank4.bank7 uncore memory WR_CAS Access to Rank 4; Bank 7 event=0xbc,umask=0x80  01     unc_m_wr_cas_rank5.bank0 uncore memory WR_CAS Access to Rank 5; Bank 0 event=0xbd,umask=1  01     unc_m_wr_cas_rank5.bank1 uncore memory WR_CAS Access to Rank 5; Bank 1 event=0xbd,umask=2  01     unc_m_wr_cas_rank5.bank2 uncore memory WR_CAS Access to Rank 5; Bank 2 event=0xbd,umask=4  01     unc_m_wr_cas_rank5.bank3 uncore memory WR_CAS Access to Rank 5; Bank 3 event=0xbd,umask=8  01     unc_m_wr_cas_rank5.bank4 uncore memory WR_CAS Access to Rank 5; Bank 4 event=0xbd,umask=0x10  01     unc_m_wr_cas_rank5.bank5 uncore memory WR_CAS Access to Rank 5; Bank 5 event=0xbd,umask=0x20  01     unc_m_wr_cas_rank5.bank6 uncore memory WR_CAS Access to Rank 5; Bank 6 event=0xbd,umask=0x40  01     unc_m_wr_cas_rank5.bank7 uncore memory WR_CAS Access to Rank 5; Bank 7 event=0xbd,umask=0x80  01     unc_m_wr_cas_rank6.bank0 uncore memory WR_CAS Access to Rank 6; Bank 0 event=0xbe,umask=1  01     unc_m_wr_cas_rank6.bank1 uncore memory WR_CAS Access to Rank 6; Bank 1 event=0xbe,umask=2  01     unc_m_wr_cas_rank6.bank2 uncore memory WR_CAS Access to Rank 6; Bank 2 event=0xbe,umask=4  01     unc_m_wr_cas_rank6.bank3 uncore memory WR_CAS Access to Rank 6; Bank 3 event=0xbe,umask=8  01     unc_m_wr_cas_rank6.bank4 uncore memory WR_CAS Access to Rank 6; Bank 4 event=0xbe,umask=0x10  01     unc_m_wr_cas_rank6.bank5 uncore memory WR_CAS Access to Rank 6; Bank 5 event=0xbe,umask=0x20  01     unc_m_wr_cas_rank6.bank6 uncore memory WR_CAS Access to Rank 6; Bank 6 event=0xbe,umask=0x40  01     unc_m_wr_cas_rank6.bank7 uncore memory WR_CAS Access to Rank 6; Bank 7 event=0xbe,umask=0x80  01     unc_m_wr_cas_rank7.bank0 uncore memory WR_CAS Access to Rank 7; Bank 0 event=0xbf,umask=1  01     unc_m_wr_cas_rank7.bank1 uncore memory WR_CAS Access to Rank 7; Bank 1 event=0xbf,umask=2  01     unc_m_wr_cas_rank7.bank2 uncore memory WR_CAS Access to Rank 7; Bank 2 event=0xbf,umask=4  01     unc_m_wr_cas_rank7.bank3 uncore memory WR_CAS Access to Rank 7; Bank 3 event=0xbf,umask=8  01     unc_m_wr_cas_rank7.bank4 uncore memory WR_CAS Access to Rank 7; Bank 4 event=0xbf,umask=0x10  01     unc_m_wr_cas_rank7.bank5 uncore memory WR_CAS Access to Rank 7; Bank 5 event=0xbf,umask=0x20  01     unc_m_wr_cas_rank7.bank6 uncore memory WR_CAS Access to Rank 7; Bank 6 event=0xbf,umask=0x40  01     unc_m_wr_cas_rank7.bank7 uncore memory WR_CAS Access to Rank 7; Bank 7 event=0xbf,umask=0x80  01     unc_p_core0_transition_cycles uncore power Core 0 C State Transition Cycles event=0x70  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core10_transition_cycles uncore power Core 10 C State Transition Cycles event=0x7a  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core11_transition_cycles uncore power Core 11 C State Transition Cycles event=0x7b  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core12_transition_cycles uncore power Core 12 C State Transition Cycles event=0x7c  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core13_transition_cycles uncore power Core 13 C State Transition Cycles event=0x7d  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core14_transition_cycles uncore power Core 14 C State Transition Cycles event=0x7e  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core1_transition_cycles uncore power Core 1 C State Transition Cycles event=0x71  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core2_transition_cycles uncore power Core 2 C State Transition Cycles event=0x72  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core3_transition_cycles uncore power Core 3 C State Transition Cycles event=0x73  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core4_transition_cycles uncore power Core 4 C State Transition Cycles event=0x74  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core5_transition_cycles uncore power Core 5 C State Transition Cycles event=0x75  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core6_transition_cycles uncore power Core 6 C State Transition Cycles event=0x76  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core7_transition_cycles uncore power Core 7 C State Transition Cycles event=0x77  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core8_transition_cycles uncore power Core 8 C State Transition Cycles event=0x78  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core9_transition_cycles uncore power Core 9 C State Transition Cycles event=0x79  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_delayed_c_state_abort_core0 uncore power Deep C State Rejection - Core 0 event=0x17  01    Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core1 uncore power Deep C State Rejection - Core 1 event=0x18  01    Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core10 uncore power Deep C State Rejection - Core 10 event=0x21  01    Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core11 uncore power Deep C State Rejection - Core 11 event=0x22  01    Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core12 uncore power Deep C State Rejection - Core 12 event=0x23  01    Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core13 uncore power Deep C State Rejection - Core 13 event=0x24  01    Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core14 uncore power Deep C State Rejection - Core 14 event=0x25  01    Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core2 uncore power Deep C State Rejection - Core 2 event=0x19  01    Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core3 uncore power Deep C State Rejection - Core 3 event=0x1a  01    Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core4 uncore power Deep C State Rejection - Core 4 event=0x1b  01    Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core5 uncore power Deep C State Rejection - Core 5 event=0x1c  01    Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core6 uncore power Deep C State Rejection - Core 6 event=0x1d  01    Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core7 uncore power Deep C State Rejection - Core 7 event=0x1e  01    Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core8 uncore power Deep C State Rejection - Core 8 event=0x1f  01    Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_delayed_c_state_abort_core9 uncore power Deep C State Rejection - Core 9 event=0x20  01    Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state unc_p_demotions_core0 uncore power Core 0 C State Demotions event=0x1e  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core1 uncore power Core 1 C State Demotions event=0x1f  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core10 uncore power Core 10 C State Demotions event=0x42  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core11 uncore power Core 11 C State Demotions event=0x43  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core12 uncore power Core 12 C State Demotions event=0x44  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core13 uncore power Core 13 C State Demotions event=0x45  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core14 uncore power Core 14 C State Demotions event=0x46  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core2 uncore power Core 2 C State Demotions event=0x20  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core3 uncore power Core 3 C State Demotions event=0x21  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core4 uncore power Core 4 C State Demotions event=0x22  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core5 uncore power Core 5 C State Demotions event=0x23  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core6 uncore power Core 6 C State Demotions event=0x24  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core7 uncore power Core 7 C State Demotions event=0x25  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core8 uncore power Core 8 C State Demotions event=0x40  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core9 uncore power Core 9 C State Demotions event=0x41  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_freq_max_current_cycles uncore power Current Strongest Upper Limit Cycles event=7  01    Counts the number of cycles when current is the upper limit on frequency unc_p_freq_min_io_p_cycles uncore power IO P Limit Strongest Lower Limit Cycles event=0x61  01    Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower.  This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW.  This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth unc_p_freq_min_perf_p_cycles uncore power Perf P Limit Strongest Lower Limit Cycles event=0x62  01    Counts the number of cycles when Perf P Limit is preventing us from dropping the frequency lower.  Perf P Limit is an algorithm that takes input from remote sockets when determining if a socket should drop it's frequency down.  This is largely to minimize increases in snoop and remote read latencies unc_p_freq_trans_cycles uncore power Cycles spent changing Frequency event=0x60  01    Counts the number of cycles when the system is changing frequency.  This can not be filtered by thread ID.  One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system unc_p_pkg_c_exit_latency uncore power Package C State Exit Latency event=0x26  01    Counts the number of cycles that the package is transitioning from package C2 to C3 unc_p_pkg_c_exit_latency_sel uncore power Package C State Exit Latency event=0x26  01    Counts the number of cycles that the package is transitioning from package C2 to C3 unc_p_pkg_c_state_residency_c0_cycles uncore power Package C State Residency - C0 event=0x2a  01    Counts the number of cycles that the package is in C0 unc_p_pkg_c_state_residency_c2_cycles uncore power Package C State Residency - C2 event=0x2b  01    Counts the number of cycles that the package is in C2 unc_p_pkg_c_state_residency_c3_cycles uncore power Package C State Residency - C3 event=0x2c  01    Counts the number of cycles that the package is in C3 unc_p_pkg_c_state_residency_c6_cycles uncore power Package C State Residency - C6 event=0x2d  01    Counts the number of cycles that the package is in C6 unc_p_total_transition_cycles uncore power Total Core C State Transition Cycles event=0x63  01    Number of cycles spent performing core C state transitions across all cores unc_p_volt_trans_cycles_change uncore power Cycles Changing Voltage event=3  01    Counts the number of cycles when the system is changing voltage.  There is no filtering supported with this event.  One can use it as a simple event, or use it conjunction with the occupancy events to monitor the number of cores or threads that were impacted by the transition.  This event is calculated by or'ing together the increasing and decreasing events unc_p_volt_trans_cycles_decrease uncore power Cycles Decreasing Voltage event=2  01    Counts the number of cycles when the system is decreasing voltage.  There is no filtering supported with this event.  One can use it as a simple event, or use it conjunction with the occupancy events to monitor the number of cores or threads that were impacted by the transition unc_p_volt_trans_cycles_increase uncore power Cycles Increasing Voltage event=1  01    Counts the number of cycles when the system is increasing voltage.  There is no filtering supported with this event.  One can use it as a simple event, or use it conjunction with the occupancy events to monitor the number of cores or threads that were impacted by the transition unc_p_vr_hot_cycles uncore power VR Hot event=0x32  01     dtlb_load_misses.demand_ld_walk_completed virtual memory Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size event=8,period=100003,umask=0x82  00     dtlb_load_misses.demand_ld_walk_duration virtual memory Demand load cycles page miss handler (PMH) is busy with this walk event=8,period=2000003,umask=0x84  00     l1d.allocated_in_m cache Allocated L1D data cache lines in M state event=0x51,period=2000003,umask=2  00     l1d.all_m_replacement cache Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement event=0x51,period=2000003,umask=8  00     l1d.eviction cache L1D data cache lines in M state evicted due to replacement event=0x51,period=2000003,umask=4  00     l1d.replacement cache L1D data line replacements event=0x51,period=2000003,umask=1  00    This event counts L1D data line replacements.  Replacements occur when a new line is brought into the cache, causing eviction of a line loaded earlier l1d_blocks.bank_conflict_cycles cache Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports event=0xbf,cmask=1,period=100003,umask=5  00     l1d_pend_miss.pending cache L1D miss outstanding duration in cycles event=0x48,period=2000003,umask=1  00     l2_l1d_wb_rqsts.hit_s cache Not rejected writebacks from L1D to L2 cache lines in S state event=0x28,period=200003,umask=2  00     l2_l1d_wb_rqsts.miss cache Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.) event=0x28,period=200003,umask=1  00     l2_lines_out.pf_clean cache Clean L2 cache lines evicted by L2 prefetch event=0xf2,period=100003,umask=4  00     l2_lines_out.pf_dirty cache Dirty L2 cache lines evicted by L2 prefetch event=0xf2,period=100003,umask=8  00     l2_rqsts.all_code_rd cache L2 code requests event=0x24,period=200003,umask=0x30  00     l2_rqsts.all_demand_data_rd cache Demand Data Read requests event=0x24,period=200003,umask=3  00     l2_rqsts.all_pf cache Requests from L2 hardware prefetchers event=0x24,period=200003,umask=0xc0  00     l2_rqsts.all_rfo cache RFO requests to L2 cache event=0x24,period=200003,umask=0xc  00     l2_rqsts.code_rd_hit cache L2 cache hits when fetching instructions, code reads event=0x24,period=200003,umask=0x10  00     l2_rqsts.code_rd_miss cache L2 cache misses when fetching instructions event=0x24,period=200003,umask=0x20  00     l2_rqsts.pf_hit cache Requests from the L2 hardware prefetchers that hit L2 cache event=0x24,period=200003,umask=0x40  00     l2_rqsts.pf_miss cache Requests from the L2 hardware prefetchers that miss L2 cache event=0x24,period=200003,umask=0x80  00     l2_rqsts.rfo_miss cache RFO requests that miss L2 cache event=0x24,period=200003,umask=8  00     l2_store_lock_rqsts.hit_e cache RFOs that hit cache lines in E state event=0x27,period=200003,umask=4  00     l2_trans.all_pf cache L2 or LLC HW prefetches that access L2 cache event=0xf0,period=200003,umask=8  00     lock_cycles.cache_lock_duration cache Cycles when L1D is locked event=0x63,period=2000003,umask=2  00     longest_lat_cache.miss cache Core-originated cacheable demand requests missed LLC event=0x2e,period=100003,umask=0x41  00     longest_lat_cache.reference cache Core-originated cacheable demand requests that refer to LLC event=0x2e,period=100003,umask=0x4f  00     mem_load_uops_llc_hit_retired.xsnp_hit cache Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache event=0xd2,period=20011,umask=2  00    This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package).  Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line.  In this case, a snoop was required, and another L2 had the line in a non-modified state mem_load_uops_llc_hit_retired.xsnp_hitm cache Retired load uops which data sources were HitM responses from shared LLC event=0xd2,period=20011,umask=4  00    This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package).  Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line.  In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2 mem_load_uops_llc_hit_retired.xsnp_miss cache Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache event=0xd2,period=20011,umask=1  00     mem_load_uops_llc_hit_retired.xsnp_none cache Retired load uops which data sources were hits in LLC without snoops required event=0xd2,period=100003,umask=8  00     mem_load_uops_llc_miss_retired.local_dram cache Data from local DRAM either Snoop not needed or Snoop Miss (RspI) event=0xd3,period=100007,umask=1  00     mem_load_uops_llc_miss_retired.remote_dram cache Data from remote DRAM either Snoop not needed or Snoop Miss (RspI) event=0xd3,period=100007,umask=4  00     mem_load_uops_retired.llc_hit cache Retired load uops which data sources were data hits in LLC without snoops required event=0xd1,period=50021,umask=4  00    This event counts retired load uops that hit in the last-level (L3) cache without snoops required mem_load_uops_retired.llc_miss cache Miss in last-level (L3) cache. Excludes Unknown data-source event=0xd1,period=100007,umask=0x20  00     mem_uops_retired.all_loads cache All retired load uops (Precise event) event=0xd0,period=2000003,umask=0x81  00    This event counts the number of load uops retired (Precise event) mem_uops_retired.all_stores cache All retired store uops (Precise event) event=0xd0,period=2000003,umask=0x82  00    This event counts the number of store uops retired (Precise event) mem_uops_retired.lock_loads cache Retired load uops with locked access (Precise event) event=0xd0,period=100007,umask=0x21  00     mem_uops_retired.split_loads cache Retired load uops that split across a cacheline boundary (Precise event) event=0xd0,period=100003,umask=0x41  00    This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) (Precise event) mem_uops_retired.split_stores cache Retired store uops that split across a cacheline boundary (Precise event) event=0xd0,period=100003,umask=0x42  00    This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) (Precise event) mem_uops_retired.stlb_miss_loads cache Retired load uops that miss the STLB (Precise event) event=0xd0,period=100003,umask=0x11  00     mem_uops_retired.stlb_miss_stores cache Retired store uops that miss the STLB (Precise event) event=0xd0,period=100003,umask=0x12  00     offcore_requests.all_data_rd cache Demand and prefetch data reads event=0xb0,period=100003,umask=8  00     offcore_requests.demand_code_rd cache Cacheable and non-cacheable code read requests event=0xb0,period=100003,umask=2  00     offcore_requests.demand_data_rd cache Demand Data Read requests sent to uncore event=0xb0,period=100003,umask=1  00     offcore_requests.demand_rfo cache Demand RFO requests including regular RFOs, locks, ItoM event=0xb0,period=100003,umask=4  00     offcore_requests_outstanding.all_data_rd cache Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore event=0x60,period=2000003,umask=8  00     offcore_requests_outstanding.demand_data_rd cache Offcore outstanding Demand Data Read transactions in uncore queue event=0x60,period=2000003,umask=1  00     offcore_requests_outstanding.demand_data_rd_c6 cache Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue event=0x60,cmask=6,period=2000003,umask=1  00     offcore_requests_outstanding.demand_rfo cache Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore event=0x60,period=2000003,umask=4  00     fp_assist.any floating point Cycles with any input/output SSE or FP assist event=0xca,cmask=1,period=100003,umask=0x1e  00     fp_assist.simd_output floating point Number of SIMD FP assists due to Output values event=0xca,period=100003,umask=8  00     fp_assist.x87_input floating point Number of X87 assists due to input value event=0xca,period=100003,umask=4  00     fp_assist.x87_output floating point Number of X87 assists due to output value event=0xca,period=100003,umask=2  00     fp_comp_ops_exe.sse_scalar_double floating point Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle event=0x10,period=2000003,umask=0x80  00     fp_comp_ops_exe.x87 floating point Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULs and IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s event=0x10,period=2000003,umask=1  00     other_assists.avx_store floating point Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations event=0xc1,period=100003,umask=8  00     simd_fp_256.packed_double floating point Number of AVX-256 Computational FP double precision uops issued this cycle event=0x11,period=2000003,umask=2  00     simd_fp_256.packed_single floating point Number of GSSE-256 Computational FP single precision uops issued this cycle event=0x11,period=2000003,umask=1  00     dsb2mite_switches.count frontend Decode Stream Buffer (DSB)-to-MITE switches event=0xab,period=2000003,umask=1  00     dsb2mite_switches.penalty_cycles frontend Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles event=0xab,period=2000003,umask=2  00    This event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline.  It excludes cycles when the back-end cannot  accept new micro-ops.  The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-end dsb_fill.all_cancel frontend Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit event=0xac,period=2000003,umask=0xa  00     dsb_fill.exceed_dsb_lines frontend Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines event=0xac,period=2000003,umask=8  00     dsb_fill.other_cancel frontend Cases of cancelling valid DSB fill not because of exceeding way limit event=0xac,period=2000003,umask=2  00     icache.misses frontend Instruction cache, streaming buffer and victim cache misses event=0x80,period=200003,umask=2  00    This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses idq.all_dsb_cycles_4_uops frontend Cycles Decode Stream Buffer (DSB) is delivering 4 Uops event=0x79,cmask=4,period=2000003,umask=0x18  00     idq.all_dsb_cycles_any_uops frontend Cycles Decode Stream Buffer (DSB) is delivering any Uop event=0x79,cmask=1,period=2000003,umask=0x18  00     idq.all_mite_cycles_4_uops frontend Cycles MITE is delivering 4 Uops event=0x79,cmask=4,period=2000003,umask=0x24  00     idq.all_mite_cycles_any_uops frontend Cycles MITE is delivering any Uop event=0x79,cmask=1,period=2000003,umask=0x24  00     idq.dsb_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path event=0x79,period=2000003,umask=8  00     idq.empty frontend Instruction Decode Queue (IDQ) empty cycles event=0x79,period=2000003,umask=2  00     idq.mite_all_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,period=2000003,umask=0x3c  00     idq.mite_uops frontend Uops delivered to Instruction Decode Queue (IDQ) from MITE path event=0x79,period=2000003,umask=4  00     idq.ms_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,period=2000003,umask=0x30  00    This event counts cycles during which the microcode sequencer assisted the front-end in delivering uops.  Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder.  Using other instructions, if possible, will usually improve performance.  See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more information idq.ms_dsb_uops frontend Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x10  00     idq.ms_mite_uops frontend Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x20  00     idq.ms_uops frontend Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,period=2000003,umask=0x30  00     idq_uops_not_delivered.core frontend Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled  event=0x9c,period=2000003,umask=1  00    This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled.  In the ideal case 4 uops can be delivered each cycle.  The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them.  This event is used in determining the front-end bound category of the top-down pipeline slots characterization idq_uops_not_delivered.cycles_ge_1_uop_deliv.core frontend Cycles when 1 or more uops were delivered to the by the front end event=0x9c,cmask=4,inv=1,period=2000003,umask=1  00     insts_written_to_iq.insts frontend Valid instructions written to IQ per cycle event=0x17,period=2000003,umask=1  00     machine_clears.memory_ordering memory Counts the number of machine clears due to memory order conflicts event=0xc3,period=100003,umask=2  00    This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers.  Machine clears can have a significant performance impact if they are happening frequently mem_trans_retired.load_latency_gt_4 memory Loads with latency value being above 4  (Must be precise) event=0xcd,period=100003,umask=1,ldlat=0x4  00     mem_trans_retired.precise_store memory Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS) (Must be precise) event=0xcd,period=2000003,umask=2  00     misalign_mem_ref.loads memory Speculative cache line split load uops dispatched to L1 cache event=5,period=2000003,umask=1  00     misalign_mem_ref.stores memory Speculative cache line split STA uops dispatched to L1 cache event=5,period=2000003,umask=2  00     offcore_response.all_demand_mlc_pref_reads.llc_miss.any_response memory This event counts all LLC misses for all demand and L2 prefetches. LLC prefetches are excluded event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFFC20077  00     offcore_response.all_demand_mlc_pref_reads.llc_miss.local_dram memory Counts all local dram accesses for all demand and L2 prefetches. LLC prefetches are excluded event=0xb7,period=100003,umask=1,offcore_rsp=0x600400077  00     offcore_response.all_demand_mlc_pref_reads.llc_miss.remote_hitm_hit_forward memory This event counts all remote cache-to-cache transfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. LLC prefetches are excluded event=0xb7,period=100003,umask=1,offcore_rsp=0x187FC20077  00     offcore_response.pf_llc_data_rd.llc_miss.any_response memory Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x3fffc20080  00     cpl_cycles.ring123 other Unhalted core cycles when thread is in rings 1, 2, or 3 event=0x5c,period=2000003,umask=2  00     hw_pre_req.dl1_miss other Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for  event=0x4e,period=2000003,umask=2  00     lock_cycles.split_lock_uc_lock_duration other Cycles when L1 and L2 are locked due to UC or split lock event=0x63,period=2000003,umask=1  00     agu_bypass_cancel.count pipeline This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an event=0xb6,period=100003,umask=1  00     arith.fpu_div pipeline Divide operations executed event=0x14,cmask=1,edge=1,period=100003,umask=1  00    This event counts the number of the divide operations executed arith.fpu_div_active pipeline Cycles when divider is busy executing divide operations event=0x14,period=2000003,umask=1  00     br_inst_exec.all_branches pipeline Speculative and retired  branches event=0x88,period=200003,umask=0xff  00     br_inst_retired.all_branches pipeline All (macro) branch instructions retired event=0xc4,period=400009  00     br_inst_retired.all_branches_pebs pipeline All (macro) branch instructions retired. (Precise Event - PEBS) (Must be precise) event=0xc4,period=400009,umask=4  00     br_inst_retired.far_branch pipeline Far branch instructions retired event=0xc4,period=100007,umask=0x40  00     br_inst_retired.not_taken pipeline Not taken branch instructions retired event=0xc4,period=400009,umask=0x10  00     br_misp_exec.all_branches pipeline Speculative and retired mispredicted macro conditional branches event=0x89,period=200003,umask=0xff  00     br_misp_exec.all_direct_near_call pipeline Speculative and retired mispredicted direct near calls event=0x89,period=200003,umask=0xd0  00     br_misp_exec.taken_direct_near_call pipeline Taken speculative and retired mispredicted direct near calls event=0x89,period=200003,umask=0x90  00     br_misp_retired.all_branches pipeline All mispredicted macro branch instructions retired event=0xc5,period=400009  00     br_misp_retired.all_branches_pebs pipeline Mispredicted macro branch instructions retired. (Precise Event - PEBS) (Must be precise) event=0xc5,period=400009,umask=4  00     br_misp_retired.near_call pipeline Direct and indirect mispredicted near call instructions retired (Precise event) event=0xc5,period=100007,umask=2  00     br_misp_retired.not_taken pipeline Mispredicted not taken branch instructions retired (Precise event) event=0xc5,period=400009,umask=0x10  00     br_misp_retired.taken pipeline Mispredicted taken branch instructions retired (Precise event) event=0xc5,period=400009,umask=0x20  00     cpu_clk_thread_unhalted.ref_xclk pipeline Reference cycles when the thread is unhalted (counts at 100 MHz rate) event=0x3c,period=2000003,umask=1  00     cpu_clk_thread_unhalted.ref_xclk_any pipeline Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate) event=0x3c,any=1,period=2000003,umask=1  00     cpu_clk_unhalted.ref_tsc pipeline Reference cycles when the core is not in halt state event=0,period=2000003,umask=3  00    This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events cpu_clk_unhalted.ref_xclk pipeline Reference cycles when the thread is unhalted (counts at 100 MHz rate) event=0x3c,period=2000003,umask=1  00     cpu_clk_unhalted.ref_xclk_any pipeline Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate) event=0x3c,any=1,period=2000003,umask=1  00     cpu_clk_unhalted.thread_p pipeline Thread cycles when thread is not in halt state event=0x3c,period=2000003  00     cycle_activity.cycles_l1d_pending pipeline Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING event=0xa3,cmask=2,period=2000003,umask=2  00     cycle_activity.cycles_l2_pending pipeline Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 event=0xa3,cmask=1,period=2000003,umask=1  00     cycle_activity.cycles_no_dispatch pipeline Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event event=0xa3,cmask=4,period=2000003,umask=4  00     cycle_activity.stalls_l1d_pending pipeline Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING event=0xa3,cmask=6,period=2000003,umask=6  00     cycle_activity.stalls_l2_pending pipeline Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2 event=0xa3,cmask=5,period=2000003,umask=5  00     ild_stall.iq_full pipeline Stall cycles because IQ is full event=0x87,period=2000003,umask=4  00     inst_retired.any pipeline Instructions retired from execution event=0xc0,period=2000003  00    This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers inst_retired.any_p pipeline Number of instructions retired. General Counter   - architectural event event=0xc0,period=2000003  00     inst_retired.prec_dist pipeline Instructions retired. (Precise Event - PEBS) (Must be precise) event=0xc0,period=2000003,umask=1  00     int_misc.rat_stall_cycles pipeline Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread event=0xd,period=2000003,umask=0x40  00     int_misc.recovery_cycles pipeline Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...) event=0xd,cmask=1,period=2000003,umask=3  00     int_misc.recovery_stalls_count pipeline Number of occurrences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...) event=0xd,cmask=1,edge=1,period=2000003,umask=3  00     ld_blocks.all_block pipeline Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss) event=3,period=100003,umask=0x10  00     ld_blocks.data_unknown pipeline Loads delayed due to SB blocks, preceding store operations with known addresses but unknown data event=3,period=100003,umask=1  00     ld_blocks.store_forward pipeline Cases when loads get true Block-on-Store blocking code preventing store forwarding event=3,period=100003,umask=2  00    This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load.  The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store.  See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual.  The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued ld_blocks_partial.address_alias pipeline False dependencies in MOB due to partial compare event=7,period=100003,umask=1  00    Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K.  This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline.  The enhanced address check typically has a performance penalty of 5 cycles ld_blocks_partial.all_sta_block pipeline This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type event=7,period=100003,umask=8  00     load_hit_pre.hw_pf pipeline Not software-prefetch load dispatches that hit FB allocated for hardware prefetch event=0x4c,period=100003,umask=2  00     load_hit_pre.sw_pf pipeline Not software-prefetch load dispatches that hit FB allocated for software prefetch event=0x4c,period=100003,umask=1  00     other_assists.itlb_miss_retired pipeline Retired instructions experiencing ITLB misses event=0xc1,period=100003,umask=2  00     partial_rat_stalls.flags_merge_uop pipeline Increments the number of flags-merge uops in flight each cycle event=0x59,period=2000003,umask=0x20  00     partial_rat_stalls.flags_merge_uop_cycles pipeline Performance sensitive flags-merging uops added by Sandy Bridge u-arch event=0x59,cmask=1,period=2000003,umask=0x20  00    This event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel? 64 and IA-32 Architectures Optimization Reference Manual partial_rat_stalls.mul_single_uop pipeline Multiply packed/scalar single precision uops allocated event=0x59,period=2000003,umask=0x80  00     partial_rat_stalls.slow_lea_window pipeline Cycles with at least one slow LEA uop being allocated event=0x59,period=2000003,umask=0x40  00    This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions resource_stalls.any pipeline Resource-related stall cycles event=0xa2,period=2000003,umask=1  00     resource_stalls.lb pipeline Counts the cycles of stall due to lack of load buffers event=0xa2,period=2000003,umask=2  00     resource_stalls.lb_sb pipeline Resource stalls due to load or store buffers all being in use event=0xa2,period=2000003,umask=0xa  00     resource_stalls.mem_rs pipeline Resource stalls due to memory buffers or Reservation Station (RS) being fully utilized event=0xa2,period=2000003,umask=0xe  00     resource_stalls.ooo_rsrc pipeline Resource stalls due to Rob being full, FCSW, MXCSR and OTHER event=0xa2,period=2000003,umask=0xf0  00     resource_stalls.sb pipeline Cycles stalled due to no store buffers available. (not including draining form sync) event=0xa2,period=2000003,umask=8  00     resource_stalls2.all_fl_empty pipeline Cycles with either free list is empty event=0x5b,period=2000003,umask=0xc  00     resource_stalls2.all_prf_control pipeline Resource stalls2 control structures full for physical registers event=0x5b,period=2000003,umask=0xf  00     resource_stalls2.bob_full pipeline Cycles when Allocator is stalled if BOB is full and new branch needs it event=0x5b,period=2000003,umask=0x40  00     resource_stalls2.ooo_rsrc pipeline Resource stalls out of order resources full event=0x5b,period=2000003,umask=0x4f  00     rob_misc_events.lbr_inserts pipeline Count cases of saving new LBR event=0xcc,period=2000003,umask=0x20  00     rs_events.empty_cycles pipeline Cycles when Reservation Station (RS) is empty for the thread event=0x5e,period=2000003,umask=1  00     rs_events.empty_end pipeline Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues event=0x5e,cmask=1,edge=1,inv=1,period=2000003,umask=1  00     uops_dispatched.core pipeline Uops dispatched from any thread event=0xb1,period=2000003,umask=2  00     uops_dispatched.thread pipeline Uops dispatched per thread event=0xb1,period=2000003,umask=1  00     uops_dispatched_port.port_0 pipeline Cycles per thread when uops are dispatched to port 0 event=0xa1,period=2000003,umask=1  00     uops_dispatched_port.port_1 pipeline Cycles per thread when uops are dispatched to port 1 event=0xa1,period=2000003,umask=2  00     uops_dispatched_port.port_2 pipeline Cycles per thread when load or STA uops are dispatched to port 2 event=0xa1,period=2000003,umask=0xc  00     uops_dispatched_port.port_2_core pipeline Cycles per core when load or STA uops are dispatched to port 2 event=0xa1,any=1,period=2000003,umask=0xc  00     uops_dispatched_port.port_3 pipeline Cycles per thread when load or STA uops are dispatched to port 3 event=0xa1,period=2000003,umask=0x30  00     uops_dispatched_port.port_4 pipeline Cycles per thread when uops are dispatched to port 4 event=0xa1,period=2000003,umask=0x40  00     uops_dispatched_port.port_5 pipeline Cycles per thread when uops are dispatched to port 5 event=0xa1,period=2000003,umask=0x80  00     uops_issued.any pipeline Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS) event=0xe,period=2000003,umask=1  00    This event counts the number of Uops issued by the front-end of the pipeilne to the back-end uops_retired.all pipeline Actually retired uops (Precise event) event=0xc2,period=2000003,umask=1  00    This event counts the number of micro-ops retired (Precise event) uops_retired.core_stall_cycles pipeline Cycles without actually retired uops event=0xc2,cmask=1,inv=1,period=2000003,umask=1  00     uops_retired.retire_slots pipeline Retirement slots used (Precise event) event=0xc2,period=2000003,umask=2  00    This event counts the number of retirement slots used each cycle.  There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle.  This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization (Precise event) unc_c_ismq_drd_miss_occ uncore cache  event=0x21  01     unc_c_llc_lookup.data_read uncore cache Cache Lookups; Data Read Request event=0x34,umask=3  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set filter mask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state unc_c_llc_lookup.nid uncore cache Cache Lookups; RTID event=0x34,umask=0x41  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set filter mask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state unc_c_llc_lookup.remote_snoop uncore cache Cache Lookups; External Snoop Request event=0x34,umask=9  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set filter mask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state unc_c_llc_lookup.write uncore cache Cache Lookups; Write Requests event=0x34,umask=5  01    Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set filter mask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state unc_c_llc_victims.nid uncore cache Lines Victimized; Victimized Lines that Match NID event=0x37,umask=0x40  01    Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in unc_c_misc.rfo_hit_s uncore cache Cbo Misc; RFO HitS event=0x39,umask=8  01    Miscellaneous events in the Cbo unc_c_misc.rspi_was_fse uncore cache Cbo Misc; Silent Snoop Eviction event=0x39,umask=1  01    Miscellaneous events in the Cbo unc_c_misc.wc_aliasing uncore cache Cbo Misc; Write Combining Aliasing event=0x39,umask=2  01    Miscellaneous events in the Cbo unc_c_ring_ad_used.down_even uncore cache AD Ring In Use; Down and Even event=0x1b,umask=4  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.down_odd uncore cache AD Ring In Use; Down and Odd event=0x1b,umask=8  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.up_even uncore cache AD Ring In Use; Up and Even event=0x1b,umask=1  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ad_used.up_odd uncore cache AD Ring In Use; Up and Odd event=0x1b,umask=2  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.down_even uncore cache AK Ring In Use; Down and Even event=0x1c,umask=4  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.down_odd uncore cache AK Ring In Use; Down and Odd event=0x1c,umask=8  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.up_even uncore cache AK Ring In Use; Up and Even event=0x1c,umask=1  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_ak_used.up_odd uncore cache AK Ring In Use; Up and Odd event=0x1c,umask=2  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.down_even uncore cache BL Ring in Use; Down and Even event=0x1d,umask=4  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.down_odd uncore cache BL Ring in Use; Down and Odd event=0x1d,umask=8  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.up_even uncore cache BL Ring in Use; Up and Even event=0x1d,umask=1  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bl_used.up_odd uncore cache BL Ring in Use; Up and Odd event=0x1d,umask=2  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring unc_c_ring_bounces.ak_core uncore cache Number of LLC responses that bounced on the Ring.; Acknowledgements to core event=5,umask=2  01     unc_c_ring_bounces.bl_core uncore cache Number of LLC responses that bounced on the Ring.; Data Responses to core event=5,umask=4  01     unc_c_ring_bounces.iv_core uncore cache Number of LLC responses that bounced on the Ring.; Snoops of processor's cache event=5,umask=8  01     unc_c_ring_iv_used.any uncore cache BL Ring in Use; Any event=0x1e,umask=0xf  01    Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in JKT.  Therefore, if one wants to monitor the 'Even' ring, they should select both UP_EVEN and DN_EVEN.  To monitor the 'Odd' ring, they should select both UP_ODD and DN_ODD unc_c_ring_sink_starved.ad_cache uncore cache  event=6,umask=1  01     unc_c_ring_sink_starved.ak_core uncore cache  event=6,umask=2  01     unc_c_ring_sink_starved.bl_core uncore cache  event=6,umask=4  01     unc_c_ring_sink_starved.iv_core uncore cache  event=6,umask=8  01     unc_c_rxr_ext_starved.ipq uncore cache Ingress Arbiter Blocking Cycles; IRQ event=0x12,umask=2  01    Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues unc_c_rxr_ext_starved.irq uncore cache Ingress Arbiter Blocking Cycles; IPQ event=0x12,umask=1  01    Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues unc_c_rxr_ext_starved.ismq uncore cache Ingress Arbiter Blocking Cycles; ISMQ event=0x12,umask=4  01    Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues unc_c_rxr_ext_starved.ismq_bids uncore cache Ingress Arbiter Blocking Cycles; ISMQ_BID event=0x12,umask=8  01    Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues unc_c_rxr_inserts.irq_rejected uncore cache Ingress Allocations; IRQ Rejected event=0x13,umask=2  01    Counts number of allocations per cycle into the specified Ingress queue unc_c_rxr_inserts.vfifo uncore cache Ingress Allocations; VFIFO event=0x13,umask=0x10  01    Counts number of allocations per cycle into the specified Ingress queue unc_c_rxr_int_starved.ipq uncore cache Ingress Internal Starvation Cycles; IPQ event=0x14,umask=4  01    Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue unc_c_rxr_int_starved.irq uncore cache Ingress Internal Starvation Cycles; IRQ event=0x14,umask=1  01    Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue unc_c_rxr_int_starved.ismq uncore cache Ingress Internal Starvation Cycles; ISMQ event=0x14,umask=8  01    Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue unc_c_rxr_ipq_retry.addr_conflict uncore cache Probe Queue Retries; Address Conflict event=0x31,umask=4  01    Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries unc_c_rxr_ipq_retry.any uncore cache Probe Queue Retries; Any Reject event=0x31,umask=1  01    Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries unc_c_rxr_ipq_retry.full uncore cache Probe Queue Retries; No Egress Credits event=0x31,umask=2  01    Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries unc_c_rxr_irq_retry.addr_conflict uncore cache Ingress Request Queue Rejects; Address Conflict event=0x32,umask=4  01     unc_c_rxr_irq_retry.any uncore cache Ingress Request Queue Rejects; Any Reject event=0x32,umask=1  01     unc_c_rxr_irq_retry.full uncore cache Ingress Request Queue Rejects; No Egress Credits event=0x32,umask=2  01     unc_c_rxr_irq_retry.qpi_credits uncore cache Ingress Request Queue Rejects; No QPI Credits event=0x32,umask=0x10  01     unc_c_rxr_irq_retry.rtid uncore cache Ingress Request Queue Rejects; No RTIDs event=0x32,umask=8  01     unc_c_rxr_ismq_retry.any uncore cache ISMQ Retries; Any Reject event=0x33,umask=1  01    Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores unc_c_rxr_ismq_retry.full uncore cache ISMQ Retries; No Egress Credits event=0x33,umask=2  01    Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores unc_c_rxr_ismq_retry.iio_credits uncore cache ISMQ Retries; No IIO Credits event=0x33,umask=0x20  01    Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores unc_c_rxr_ismq_retry.rtid uncore cache ISMQ Retries; No RTIDs event=0x33,umask=8  01    Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores unc_c_rxr_occupancy.irq_rejected uncore cache Ingress Occupancy; IRQ Rejected event=0x11,umask=2  01    Counts number of entries in the specified Ingress queue in each cycle unc_c_rxr_occupancy.vfifo uncore cache Ingress Occupancy; VFIFO event=0x11,umask=0x10  01    Counts number of entries in the specified Ingress queue in each cycle unc_c_tor_inserts.eviction uncore cache TOR Inserts; Evictions event=0x35,umask=4  01    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182) unc_c_tor_inserts.miss_all uncore cache TOR Inserts; Miss All event=0x35,umask=0xa  01    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182) unc_c_tor_inserts.miss_opcode uncore cache TOR Inserts; Miss Opcode Match event=0x35,umask=3  01    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182) unc_c_tor_inserts.nid_all uncore cache TOR Inserts; NID Matched event=0x35,umask=0x48  01    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182) unc_c_tor_inserts.nid_eviction uncore cache TOR Inserts; NID Matched Evictions event=0x35,umask=0x44  01    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182) unc_c_tor_inserts.nid_miss_all uncore cache TOR Inserts; NID Matched Miss All event=0x35,umask=0x4a  01    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182) unc_c_tor_inserts.nid_miss_opcode uncore cache TOR Inserts; NID and Opcode Matched Miss event=0x35,umask=0x43  01    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182) unc_c_tor_inserts.nid_opcode uncore cache TOR Inserts; NID and Opcode Matched event=0x35,umask=0x41  01    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182) unc_c_tor_inserts.nid_wb uncore cache TOR Inserts; NID Matched Writebacks event=0x35,umask=0x50  01    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182) unc_c_tor_inserts.opcode uncore cache TOR Inserts; Opcode Match event=0x35,umask=1  01    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182) unc_c_tor_inserts.wb uncore cache TOR Inserts; Writebacks event=0x35,umask=0x10  01    Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182) unc_c_tor_occupancy.all uncore cache TOR Occupancy; Any event=0x36,umask=8  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.eviction uncore cache TOR Occupancy; Evictions event=0x36,umask=4  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.miss_all uncore cache TOR Occupancy; Miss All event=0x36,umask=0xa  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.miss_opcode uncore cache TOR Occupancy; Miss Opcode Match event=0x36,umask=3  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.nid_all uncore cache TOR Occupancy; NID Matched event=0x36,umask=0x48  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.nid_eviction uncore cache TOR Occupancy; NID Matched Evictions event=0x36,umask=0x44  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.nid_miss_all uncore cache TOR Occupancy; NID Matched event=0x36,umask=0x4a  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.nid_miss_opcode uncore cache TOR Occupancy; NID and Opcode Matched Miss event=0x36,umask=0x43  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.nid_opcode uncore cache TOR Occupancy; NID and Opcode Matched event=0x36,umask=0x41  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_tor_occupancy.opcode uncore cache TOR Occupancy; Opcode Match event=0x36,umask=1  01    For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) unc_c_txr_ads_used uncore cache  event=4  01     unc_c_txr_inserts.ad_cache uncore cache Egress Allocations; AD - Cachebo event=2,umask=1  01    Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring unc_c_txr_inserts.ad_core uncore cache Egress Allocations; AD - Corebo event=2,umask=0x10  01    Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring unc_c_txr_inserts.ak_cache uncore cache Egress Allocations; AK - Cachebo event=2,umask=2  01    Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring unc_c_txr_inserts.ak_core uncore cache Egress Allocations; AK - Corebo event=2,umask=0x20  01    Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring unc_c_txr_inserts.bl_cache uncore cache Egress Allocations; BL - Cacheno event=2,umask=4  01    Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring unc_c_txr_inserts.bl_core uncore cache Egress Allocations; BL - Corebo event=2,umask=0x40  01    Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring unc_c_txr_inserts.iv_cache uncore cache Egress Allocations; IV - Cachebo event=2,umask=8  01    Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring unc_c_txr_starved.ak uncore cache Injection Starvation; Onto AK Ring event=3,umask=2  01    Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time unc_c_txr_starved.bl uncore cache Injection Starvation; Onto BL Ring event=3,umask=4  01    Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time unc_h_bypass_imc.not_taken uncore cache HA to iMC Bypass; Not Taken event=0x14,umask=2  01    Counts the number of times when the HA was able to bypass was attempted.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filted by when the bypass was taken and when it was not unc_h_bypass_imc.taken uncore cache HA to iMC Bypass; Taken event=0x14,umask=1  01    Counts the number of times when the HA was able to bypass was attempted.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filted by when the bypass was taken and when it was not unc_h_conflict_cycles.conflict uncore cache Conflict Checks; Conflict Detected event=0xb,umask=2  01     unc_h_conflict_cycles.no_conflict uncore cache Conflict Checks; No Conflict event=0xb,umask=1  01     unc_h_directory_lookup.no_snp uncore cache Directory Lookups; Snoop Not Needed event=0xc,umask=2  01    Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to unc_h_directory_lookup.snp uncore cache Directory Lookups; Snoop Needed event=0xc,umask=1  01    Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to unc_h_directory_update.clear uncore cache Directory Updates; Directory Clear event=0xd,umask=2  01    Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears unc_h_directory_update.set uncore cache Directory Updates; Directory Set event=0xd,umask=1  01    Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears unc_h_requests.reads uncore cache Read and Write Requests; Reads event=1,umask=3  01    Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc) unc_h_requests.writes uncore cache Read and Write Requests; Writes event=1,umask=0xc  01    Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc) unc_h_ring_ad_used.ccw_even uncore cache HA AD Ring in Use; Counterclockwise and Even event=0x3e,umask=4  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ad_used.ccw_odd uncore cache HA AD Ring in Use; Counterclockwise and Odd event=0x3e,umask=8  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ad_used.cw_even uncore cache HA AD Ring in Use; Clockwise and Even event=0x3e,umask=1  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ad_used.cw_odd uncore cache HA AD Ring in Use; Clockwise and Odd event=0x3e,umask=2  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ak_used.ccw_even uncore cache HA AK Ring in Use; Counterclockwise and Even event=0x3f,umask=4  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ak_used.ccw_odd uncore cache HA AK Ring in Use; Counterclockwise and Odd event=0x3f,umask=8  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ak_used.cw_even uncore cache HA AK Ring in Use; Clockwise and Even event=0x3f,umask=1  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_ak_used.cw_odd uncore cache HA AK Ring in Use; Clockwise and Odd event=0x3f,umask=2  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_bl_used.ccw_even uncore cache HA BL Ring in Use; Counterclockwise and Even event=0x40,umask=4  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_bl_used.ccw_odd uncore cache HA BL Ring in Use; Counterclockwise and Odd event=0x40,umask=8  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_bl_used.cw_even uncore cache HA BL Ring in Use; Clockwise and Even event=0x40,umask=1  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_ring_bl_used.cw_odd uncore cache HA BL Ring in Use; Clockwise and Odd event=0x40,umask=2  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_h_rpq_cycles_no_reg_credits.chn0 uncore cache iMC RPQ Credits Empty - Regular; Channel 0 event=0x15,umask=1  01    Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time unc_h_rpq_cycles_no_reg_credits.chn1 uncore cache iMC RPQ Credits Empty - Regular; Channel 1 event=0x15,umask=2  01    Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time unc_h_rpq_cycles_no_reg_credits.chn2 uncore cache iMC RPQ Credits Empty - Regular; Channel 2 event=0x15,umask=4  01    Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time unc_h_rpq_cycles_no_reg_credits.chn3 uncore cache iMC RPQ Credits Empty - Regular; Channel 3 event=0x15,umask=8  01    Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time unc_h_rpq_cycles_no_spec_credits.chn0 uncore cache iMC RPQ Credits Empty - Special; Channel 0 event=0x16,umask=1  01    Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time unc_h_rpq_cycles_no_spec_credits.chn1 uncore cache iMC RPQ Credits Empty - Special; Channel 1 event=0x16,umask=2  01    Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time unc_h_rpq_cycles_no_spec_credits.chn2 uncore cache iMC RPQ Credits Empty - Special; Channel 2 event=0x16,umask=4  01    Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time unc_h_rpq_cycles_no_spec_credits.chn3 uncore cache iMC RPQ Credits Empty - Special; Channel 3 event=0x16,umask=8  01    Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time unc_h_tad_requests_g0.region0 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 0 event=0x1b,umask=1  01    Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g0.region1 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 1 event=0x1b,umask=2  01    Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g0.region2 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 2 event=0x1b,umask=4  01    Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g0.region3 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 3 event=0x1b,umask=8  01    Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g0.region4 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 4 event=0x1b,umask=0x10  01    Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g0.region5 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 5 event=0x1b,umask=0x20  01    Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g0.region6 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 6 event=0x1b,umask=0x40  01    Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g0.region7 uncore cache HA Requests to a TAD Region - Group 0; TAD Region 7 event=0x1b,umask=0x80  01    Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g1.region10 uncore cache HA Requests to a TAD Region - Group 1; TAD Region 10 event=0x1c,umask=4  01    Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g1.region11 uncore cache HA Requests to a TAD Region - Group 1; TAD Region 11 event=0x1c,umask=8  01    Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g1.region8 uncore cache HA Requests to a TAD Region - Group 1; TAD Region 8 event=0x1c,umask=1  01    Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tad_requests_g1.region9 uncore cache HA Requests to a TAD Region - Group 1; TAD Region 9 event=0x1c,umask=2  01    Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power unc_h_tracker_inserts.all uncore cache Tracker Allocations; All Requests event=6,umask=3  01    Counts the number of allocations into the local HA tracker pool.  This can be used in conjunction with the occupancy accumulation event in order to calculate average latency.  One cannot filter between reads and writes.  HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring unc_h_txr_ad.ndr uncore cache Outbound NDR Ring Transactions; Non-data Responses event=0xf,umask=1  01    Counts the number of outbound transactions on the AD ring.  This can be filtered by the NDR and SNP message classes.  See the filter descriptions for more details unc_h_txr_ad.snp uncore cache Outbound NDR Ring Transactions; Snoops event=0xf,umask=2  01    Counts the number of outbound transactions on the AD ring.  This can be filtered by the NDR and SNP message classes.  See the filter descriptions for more details unc_h_txr_ad_cycles_full.all uncore cache AD Egress Full; All event=0x2a,umask=3  01     unc_h_txr_ad_cycles_full.sched0 uncore cache AD Egress Full; Scheduler 0 event=0x2a,umask=1  01     unc_h_txr_ad_cycles_full.sched1 uncore cache AD Egress Full; Scheduler 1 event=0x2a,umask=2  01     unc_h_txr_ad_cycles_ne.all uncore cache AD Egress Not Empty; All event=0x29,umask=3  01     unc_h_txr_ad_cycles_ne.sched0 uncore cache AD Egress Not Empty; Scheduler 0 event=0x29,umask=1  01     unc_h_txr_ad_cycles_ne.sched1 uncore cache AD Egress Not Empty; Scheduler 1 event=0x29,umask=2  01     unc_h_txr_ad_inserts.all uncore cache AD Egress Allocations; All event=0x27,umask=3  01     unc_h_txr_ad_inserts.sched0 uncore cache AD Egress Allocations; Scheduler 0 event=0x27,umask=1  01     unc_h_txr_ad_inserts.sched1 uncore cache AD Egress Allocations; Scheduler 1 event=0x27,umask=2  01     unc_h_txr_ad_occupancy.all uncore cache AD Egress Occupancy; All event=0x28,umask=3  01     unc_h_txr_ad_occupancy.sched0 uncore cache AD Egress Occupancy; Scheduler 0 event=0x28,umask=1  01     unc_h_txr_ad_occupancy.sched1 uncore cache AD Egress Occupancy; Scheduler 1 event=0x28,umask=2  01     unc_h_txr_ak_cycles_full.all uncore cache AK Egress Full; All event=0x32,umask=3  01     unc_h_txr_ak_cycles_full.sched0 uncore cache AK Egress Full; Scheduler 0 event=0x32,umask=1  01     unc_h_txr_ak_cycles_full.sched1 uncore cache AK Egress Full; Scheduler 1 event=0x32,umask=2  01     unc_h_txr_ak_cycles_ne.all uncore cache AK Egress Not Empty; All event=0x31,umask=3  01     unc_h_txr_ak_cycles_ne.sched0 uncore cache AK Egress Not Empty; Scheduler 0 event=0x31,umask=1  01     unc_h_txr_ak_cycles_ne.sched1 uncore cache AK Egress Not Empty; Scheduler 1 event=0x31,umask=2  01     unc_h_txr_ak_inserts.all uncore cache AK Egress Allocations; All event=0x2f,umask=3  01     unc_h_txr_ak_inserts.sched0 uncore cache AK Egress Allocations; Scheduler 0 event=0x2f,umask=1  01     unc_h_txr_ak_inserts.sched1 uncore cache AK Egress Allocations; Scheduler 1 event=0x2f,umask=2  01     unc_h_txr_ak_ndr uncore cache Outbound NDR Ring Transactions event=0xe  01    Counts the number of outbound NDR transactions sent on the AK ring.  NDR stands for 'non-data response' and is generally used for completions that do not include data.  AK NDR is used for messages to the local socket unc_h_txr_ak_occupancy.all uncore cache AK Egress Occupancy; All event=0x30,umask=3  01     unc_h_txr_ak_occupancy.sched0 uncore cache AK Egress Occupancy; Scheduler 0 event=0x30,umask=1  01     unc_h_txr_ak_occupancy.sched1 uncore cache AK Egress Occupancy; Scheduler 1 event=0x30,umask=2  01     unc_h_txr_bl.drs_cache uncore cache Outbound DRS Ring Transactions to Cache; Data to Cache event=0x10,umask=1  01    Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination unc_h_txr_bl.drs_core uncore cache Outbound DRS Ring Transactions to Cache; Data to Core event=0x10,umask=2  01    Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination unc_h_txr_bl.drs_qpi uncore cache Outbound DRS Ring Transactions to Cache; Data to QPI event=0x10,umask=4  01    Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination unc_h_txr_bl_cycles_full.all uncore cache BL Egress Full; All event=0x36,umask=3  01     unc_h_txr_bl_cycles_full.sched0 uncore cache BL Egress Full; Scheduler 0 event=0x36,umask=1  01     unc_h_txr_bl_cycles_full.sched1 uncore cache BL Egress Full; Scheduler 1 event=0x36,umask=2  01     unc_h_txr_bl_cycles_ne.all uncore cache BL Egress Not Empty; All event=0x35,umask=3  01     unc_h_txr_bl_cycles_ne.sched0 uncore cache BL Egress Not Empty; Scheduler 0 event=0x35,umask=1  01     unc_h_txr_bl_cycles_ne.sched1 uncore cache BL Egress Not Empty; Scheduler 1 event=0x35,umask=2  01     unc_h_txr_bl_inserts.all uncore cache BL Egress Allocations; All event=0x33,umask=3  01     unc_h_txr_bl_inserts.sched0 uncore cache BL Egress Allocations; Scheduler 0 event=0x33,umask=1  01     unc_h_txr_bl_inserts.sched1 uncore cache BL Egress Allocations; Scheduler 1 event=0x33,umask=2  01     unc_h_txr_bl_occupancy.all uncore cache BL Egress Occupancy; All event=0x34,umask=3  01     unc_h_txr_bl_occupancy.sched0 uncore cache BL Egress Occupancy; Scheduler 0 event=0x34,umask=1  01     unc_h_txr_bl_occupancy.sched1 uncore cache BL Egress Occupancy; Scheduler 1 event=0x34,umask=2  01     unc_h_wpq_cycles_no_reg_credits.chn0 uncore cache HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0 event=0x18,umask=1  01    Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time unc_h_wpq_cycles_no_reg_credits.chn1 uncore cache HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1 event=0x18,umask=2  01    Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time unc_h_wpq_cycles_no_reg_credits.chn2 uncore cache HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2 event=0x18,umask=4  01    Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time unc_h_wpq_cycles_no_reg_credits.chn3 uncore cache HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3 event=0x18,umask=8  01    Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time unc_h_wpq_cycles_no_spec_credits.chn0 uncore cache HA iMC CHN0 WPQ Credits Empty - Special; Channel 0 event=0x19,umask=1  01    Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time unc_h_wpq_cycles_no_spec_credits.chn1 uncore cache HA iMC CHN0 WPQ Credits Empty - Special; Channel 1 event=0x19,umask=2  01    Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time unc_h_wpq_cycles_no_spec_credits.chn2 uncore cache HA iMC CHN0 WPQ Credits Empty - Special; Channel 2 event=0x19,umask=4  01    Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time unc_h_wpq_cycles_no_spec_credits.chn3 uncore cache HA iMC CHN0 WPQ Credits Empty - Special; Channel 3 event=0x19,umask=8  01    Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time unc_i_address_match.merge_count uncore interconnect Address Match (Conflict) Count; Conflict Merges event=0x17,umask=2  01    Counts the number of times when an inbound write (from a device to memory or another device) had an address match with another request in the write cache unc_i_address_match.stall_count uncore interconnect Address Match (Conflict) Count; Conflict Stalls event=0x17,umask=1  01    Counts the number of times when an inbound write (from a device to memory or another device) had an address match with another request in the write cache unc_i_cache_ack_pending_occupancy.any uncore interconnect Write Ack Pending Occupancy; Any Source event=0x14,umask=1  01    Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore.  These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data.  The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released.  Note that a single tickle can result in multiple decrements unc_i_cache_ack_pending_occupancy.source uncore interconnect Write Ack Pending Occupancy; Select Source event=0x14,umask=2  01    Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore.  These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data.  The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released.  Note that a single tickle can result in multiple decrements unc_i_cache_own_occupancy.any uncore interconnect Outstanding Write Ownership Occupancy; Any Source event=0x13,umask=1  01    Accumulates the number of writes (and write prefetches) that are outstanding in the uncore trying to acquire ownership in each cycle.  This can be used with the write transaction count to calculate the average write latency in the uncore.  The occupancy increments when a write request is issued, and decrements when the data is returned unc_i_cache_own_occupancy.source uncore interconnect Outstanding Write Ownership Occupancy; Select Source event=0x13,umask=2  01    Accumulates the number of writes (and write prefetches) that are outstanding in the uncore trying to acquire ownership in each cycle.  This can be used with the write transaction count to calculate the average write latency in the uncore.  The occupancy increments when a write request is issued, and decrements when the data is returned unc_i_cache_read_occupancy.any uncore interconnect Outstanding Read Occupancy; Any Source event=0x10,umask=1  01    Accumulates the number of reads that are outstanding in the uncore in each cycle.  This can be used with the read transaction count to calculate the average read latency in the uncore.  The occupancy increments when a read request is issued, and decrements when the data is returned unc_i_cache_read_occupancy.source uncore interconnect Outstanding Read Occupancy; Select Source event=0x10,umask=2  01    Accumulates the number of reads that are outstanding in the uncore in each cycle.  This can be used with the read transaction count to calculate the average read latency in the uncore.  The occupancy increments when a read request is issued, and decrements when the data is returned unc_i_cache_total_occupancy.any uncore interconnect Total Write Cache Occupancy; Any Source event=0x12,umask=1  01    Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events unc_i_cache_total_occupancy.source uncore interconnect Total Write Cache Occupancy; Select Source event=0x12,umask=2  01    Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events unc_i_cache_write_occupancy.any uncore interconnect Outstanding Write Occupancy; Any Source event=0x11,umask=1  01    Accumulates the number of writes (and write prefetches)  that are outstanding in the uncore in each cycle.  This can be used with the transaction count event to calculate the average latency in the uncore.  The occupancy increments when the ownership fetch/prefetch is issued, and decrements the data is returned to the uncore unc_i_cache_write_occupancy.source uncore interconnect Outstanding Write Occupancy; Select Source event=0x11,umask=2  01    Accumulates the number of writes (and write prefetches)  that are outstanding in the uncore in each cycle.  This can be used with the transaction count event to calculate the average latency in the uncore.  The occupancy increments when the ownership fetch/prefetch is issued, and decrements the data is returned to the uncore unc_i_tickles.lost_ownership uncore interconnect Tickle Count; Ownership Lost event=0x16,umask=1  01    Counts the number of tickles that are received.  This is for both explicit (from Cbo) and implicit (internal conflict) tickles unc_i_tickles.top_of_queue uncore interconnect Tickle Count; Data Returned event=0x16,umask=2  01    Counts the number of tickles that are received.  This is for both explicit (from Cbo) and implicit (internal conflict) tickles unc_i_transactions.pd_prefetches uncore interconnect Inbound Transaction Count; Read Prefetches event=0x15,umask=4  01    Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID unc_i_transactions.reads uncore interconnect Inbound Transaction Count; Reads event=0x15,umask=1  01    Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID unc_i_transactions.writes uncore interconnect Inbound Transaction Count; Writes event=0x15,umask=2  01    Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID unc_q_clockticks uncore interconnect Number of qfclks event=0x14  01    Counts the number of clocks in the QPI LL.  This clock runs at 1/8th the 'GT/s' speed of the QPI link.  For example, a 8GT/s link will have qfclk or 1GHz.  JKT does not support dynamic link speeds, so this frequency is fixed unc_q_direct2core.failure_credits uncore interconnect Direct 2 Core Spawning; Spawn Failure - Egress Credits event=0x13,umask=2  01    Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exclusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos unc_q_direct2core.failure_credits_rbt uncore interconnect Direct 2 Core Spawning; Spawn Failure - Egress and RBT event=0x13,umask=8  01    Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exclusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos unc_q_direct2core.failure_rbt uncore interconnect Direct 2 Core Spawning; Spawn Failure - RBT Not Set event=0x13,umask=4  01    Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exclusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos unc_q_direct2core.success uncore interconnect Direct 2 Core Spawning; Spawn Success event=0x13,umask=1  01    Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exclusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos unc_q_rxl_crc_errors.link_init uncore interconnect CRC Errors Detected; LinkInit event=3,umask=1  01    Number of CRC errors detected in the QPI Agent.  Each QPI flit incorporates 8 bits of CRC for error detection.  This counts the number of flits where the CRC was able to detect an error.  After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it) unc_q_rxl_crc_errors.normal_op uncore interconnect CRC Errors Detected; Normal Operations event=3,umask=2  01    Number of CRC errors detected in the QPI Agent.  Each QPI flit incorporates 8 bits of CRC for error detection.  This counts the number of flits where the CRC was able to detect an error.  After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it) unc_q_rxl_credits_consumed_vn0.drs uncore interconnect VN0 Credit Consumed; DRS event=0x1e,umask=1  01    Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed unc_q_rxl_credits_consumed_vn0.hom uncore interconnect VN0 Credit Consumed; HOM event=0x1e,umask=8  01    Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed unc_q_rxl_credits_consumed_vn0.ncb uncore interconnect VN0 Credit Consumed; NCB event=0x1e,umask=2  01    Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed unc_q_rxl_credits_consumed_vn0.ncs uncore interconnect VN0 Credit Consumed; NCS event=0x1e,umask=4  01    Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed unc_q_rxl_credits_consumed_vn0.ndr uncore interconnect VN0 Credit Consumed; NDR event=0x1e,umask=0x20  01    Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed unc_q_rxl_credits_consumed_vn0.snp uncore interconnect VN0 Credit Consumed; SNP event=0x1e,umask=0x10  01    Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed unc_q_rxl_flits_g0.data uncore interconnect Flits Received - Group 0; Data Tx Flits event=1,umask=2  01    Counts the number of flits received from the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p unc_q_rxl_flits_g0.idle uncore interconnect Flits Received - Group 0; Idle and Null Flits event=1,umask=1  01    Counts the number of flits received from the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p unc_q_rxl_flits_g0.non_data uncore interconnect Flits Received - Group 0; Non-Data protocol Tx Flits event=1,umask=4  01    Counts the number of flits received from the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p unc_q_rxl_flits_g1.drs uncore interconnect Flits Received - Group 1; DRS Flits (both Header and Data) event=2,umask=0x18  01    Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g1.drs_data uncore interconnect Flits Received - Group 1; DRS Data Flits event=2,umask=8  01    Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g1.drs_nondata uncore interconnect Flits Received - Group 1; DRS Header Flits event=2,umask=0x10  01    Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g1.hom uncore interconnect Flits Received - Group 1; HOM Flits event=2,umask=6  01    Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g1.hom_nonreq uncore interconnect Flits Received - Group 1; HOM Non-Request Flits event=2,umask=4  01    Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g1.hom_req uncore interconnect Flits Received - Group 1; HOM Request Flits event=2,umask=2  01    Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g1.snp uncore interconnect Flits Received - Group 1; SNP Flits event=2,umask=1  01    Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g2.ncb uncore interconnect Flits Received - Group 2; Non-Coherent Rx Flits event=3,umask=0xc  01    Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g2.ncb_data uncore interconnect Flits Received - Group 2; Non-Coherent data Rx Flits event=3,umask=4  01    Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g2.ncb_nondata uncore interconnect Flits Received - Group 2; Non-Coherent non-data Rx Flits event=3,umask=8  01    Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g2.ncs uncore interconnect Flits Received - Group 2; Non-Coherent standard Rx Flits event=3,umask=0x10  01    Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g2.ndr_ad uncore interconnect Flits Received - Group 2; Non-Data Response Rx Flits - AD event=3,umask=1  01    Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_flits_g2.ndr_ak uncore interconnect Flits Received - Group 2; Non-Data Response Rx Flits - AK event=3,umask=2  01    Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_rxl_stalls.bgf_drs uncore interconnect Stalls Sending to R3QPI; BGF Stall - HOM event=0x35,umask=1  01    Number of stalls trying to send to R3QPI unc_q_rxl_stalls.bgf_hom uncore interconnect Stalls Sending to R3QPI; BGF Stall - DRS event=0x35,umask=8  01    Number of stalls trying to send to R3QPI unc_q_rxl_stalls.bgf_ncb uncore interconnect Stalls Sending to R3QPI; BGF Stall - SNP event=0x35,umask=2  01    Number of stalls trying to send to R3QPI unc_q_rxl_stalls.bgf_ncs uncore interconnect Stalls Sending to R3QPI; BGF Stall - NDR event=0x35,umask=4  01    Number of stalls trying to send to R3QPI unc_q_rxl_stalls.bgf_ndr uncore interconnect Stalls Sending to R3QPI; BGF Stall - NCS event=0x35,umask=0x20  01    Number of stalls trying to send to R3QPI unc_q_rxl_stalls.bgf_snp uncore interconnect Stalls Sending to R3QPI; BGF Stall - NCB event=0x35,umask=0x10  01    Number of stalls trying to send to R3QPI unc_q_rxl_stalls.egress_credits uncore interconnect Stalls Sending to R3QPI; Egress Credits event=0x35,umask=0x40  01    Number of stalls trying to send to R3QPI unc_q_rxl_stalls.gv uncore interconnect Stalls Sending to R3QPI; GV event=0x35,umask=0x80  01    Number of stalls trying to send to R3QPI unc_q_txl_crc_no_credits.almost_full uncore interconnect Cycles Stalled with no LLR Credits; LLR is almost full event=2,umask=2  01    Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall unc_q_txl_crc_no_credits.full uncore interconnect Cycles Stalled with no LLR Credits; LLR is full event=2,umask=1  01    Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall unc_q_txl_flits_g0.data uncore interconnect Flits Transferred - Group 0; Data Tx Flits event=0,umask=2  01    Counts the number of flits transmitted across the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p unc_q_txl_flits_g0.idle uncore interconnect Flits Transferred - Group 0; Idle and Null Flits event=0,umask=1  01    Counts the number of flits transmitted across the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p unc_q_txl_flits_g0.non_data uncore interconnect Flits Transferred - Group 0; Non-Data protocol Tx Flits event=0,umask=4  01    Counts the number of flits transmitted across the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p unc_q_txl_flits_g1.drs uncore interconnect Flits Transferred - Group 1; DRS Flits (both Header and Data) event=0,umask=0x18  01    Counts the number of flits transmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g1.drs_data uncore interconnect Flits Transferred - Group 1; DRS Data Flits event=0,umask=8  01    Counts the number of flits transmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g1.drs_nondata uncore interconnect Flits Transferred - Group 1; DRS Header Flits event=0,umask=0x10  01    Counts the number of flits transmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g1.hom uncore interconnect Flits Transferred - Group 1; HOM Flits event=0,umask=6  01    Counts the number of flits transmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g1.hom_nonreq uncore interconnect Flits Transferred - Group 1; HOM Non-Request Flits event=0,umask=4  01    Counts the number of flits transmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g1.hom_req uncore interconnect Flits Transferred - Group 1; HOM Request Flits event=0,umask=2  01    Counts the number of flits transmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g1.snp uncore interconnect Flits Transferred - Group 1; SNP Flits event=0,umask=1  01    Counts the number of flits transmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g2.ncb uncore interconnect Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits event=1,umask=0xc  01    Counts the number of flits transmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g2.ncb_data uncore interconnect Flits Transferred - Group 2; Non-Coherent data Tx Flits event=1,umask=4  01    Counts the number of flits transmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g2.ncb_nondata uncore interconnect Flits Transferred - Group 2; Non-Coherent non-data Tx Flits event=1,umask=8  01    Counts the number of flits transmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g2.ncs uncore interconnect Flits Transferred - Group 2; Non-Coherent standard Tx Flits event=1,umask=0x10  01    Counts the number of flits transmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g2.ndr_ad uncore interconnect Flits Transferred - Group 2; Non-Data Response Tx Flits - AD event=1,umask=1  01    Counts the number of flits transmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_q_txl_flits_g2.ndr_ak uncore interconnect Flits Transferred - Group 2; Non-Data Response Tx Flits - AK event=1,umask=2  01    Counts the number of flits transmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time unc_r3_iio_credits_acquired.drs uncore interconnect to IIO BL Credit Acquired event=0x20,umask=8  01    Counts the number of times the NCS/NCB/DRS credit is acquired in the QPI for sending messages on BL to the IIO.  There is one credit for each of these three message classes (three credits total).  NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions).  This event can only track one message class at a time unc_r3_iio_credits_acquired.ncb uncore interconnect to IIO BL Credit Acquired event=0x20,umask=0x10  01    Counts the number of times the NCS/NCB/DRS credit is acquired in the QPI for sending messages on BL to the IIO.  There is one credit for each of these three message classes (three credits total).  NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions).  This event can only track one message class at a time unc_r3_iio_credits_acquired.ncs uncore interconnect to IIO BL Credit Acquired event=0x20,umask=0x20  01    Counts the number of times the NCS/NCB/DRS credit is acquired in the QPI for sending messages on BL to the IIO.  There is one credit for each of these three message classes (three credits total).  NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions).  This event can only track one message class at a time unc_r3_iio_credits_reject.drs uncore interconnect to IIO BL Credit Rejected event=0x21,umask=8  01    Counts the number of times that a request attempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on BL to the IIO but was rejected because no credit was available.  There is one credit for each of these three message classes (three credits total).  NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions).  This event can only track one message class at a time unc_r3_iio_credits_reject.ncb uncore interconnect to IIO BL Credit Rejected event=0x21,umask=0x10  01    Counts the number of times that a request attempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on BL to the IIO but was rejected because no credit was available.  There is one credit for each of these three message classes (three credits total).  NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions).  This event can only track one message class at a time unc_r3_iio_credits_reject.ncs uncore interconnect to IIO BL Credit Rejected event=0x21,umask=0x20  01    Counts the number of times that a request attempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on BL to the IIO but was rejected because no credit was available.  There is one credit for each of these three message classes (three credits total).  NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions).  This event can only track one message class at a time unc_r3_iio_credits_used.drs uncore interconnect to IIO BL Credit In Use event=0x22,umask=8  01    Counts the number of cycles when the NCS/NCB/DRS credit is in use in the QPI for sending messages on BL to the IIO.  There is one credit for each of these three message classes (three credits total).  NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions).  This event can only track one message class at a time unc_r3_iio_credits_used.ncb uncore interconnect to IIO BL Credit In Use event=0x22,umask=0x10  01    Counts the number of cycles when the NCS/NCB/DRS credit is in use in the QPI for sending messages on BL to the IIO.  There is one credit for each of these three message classes (three credits total).  NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions).  This event can only track one message class at a time unc_r3_iio_credits_used.ncs uncore interconnect to IIO BL Credit In Use event=0x22,umask=0x20  01    Counts the number of cycles when the NCS/NCB/DRS credit is in use in the QPI for sending messages on BL to the IIO.  There is one credit for each of these three message classes (three credits total).  NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions).  This event can only track one message class at a time unc_r3_ring_ad_used.ccw_even uncore interconnect R3 AD Ring in Use; Counterclockwise and Even event=7,umask=4  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ad_used.ccw_odd uncore interconnect R3 AD Ring in Use; Counterclockwise and Odd event=7,umask=8  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ad_used.cw_even uncore interconnect R3 AD Ring in Use; Clockwise and Even event=7,umask=1  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ad_used.cw_odd uncore interconnect R3 AD Ring in Use; Clockwise and Odd event=7,umask=2  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_ak_used.ccw_even uncore interconnect R3 AK Ring in Use; Counterclockwise and Even event=8,umask=4  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop unc_r3_ring_ak_used.ccw_odd uncore interconnect R3 AK Ring in Use; Counterclockwise and Odd event=8,umask=8  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop unc_r3_ring_ak_used.cw_even uncore interconnect R3 AK Ring in Use; Clockwise and Even event=8,umask=1  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop unc_r3_ring_ak_used.cw_odd uncore interconnect R3 AK Ring in Use; Clockwise and Odd event=8,umask=2  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop unc_r3_ring_bl_used.ccw_even uncore interconnect R3 BL Ring in Use; Counterclockwise and Even event=9,umask=4  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_bl_used.ccw_odd uncore interconnect R3 BL Ring in Use; Counterclockwise and Odd event=9,umask=8  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_bl_used.cw_even uncore interconnect R3 BL Ring in Use; Clockwise and Even event=9,umask=1  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_bl_used.cw_odd uncore interconnect R3 BL Ring in Use; Clockwise and Odd event=9,umask=2  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r3_ring_iv_used.any uncore interconnect R3 IV Ring in Use; Any event=0xa,umask=0xf  01    Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  The IV ring is unidirectional.  Whether UP or DN is used is dependent on the system programming.  Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time unc_r3_rxr_cycles_ne.drs uncore interconnect Ingress Cycles Not Empty; DRS event=0x10,umask=8  01    Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_cycles_ne.hom uncore interconnect Ingress Cycles Not Empty; HOM event=0x10,umask=1  01    Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_cycles_ne.ncb uncore interconnect Ingress Cycles Not Empty; NCB event=0x10,umask=0x10  01    Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_cycles_ne.ncs uncore interconnect Ingress Cycles Not Empty; NCS event=0x10,umask=0x20  01    Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_cycles_ne.ndr uncore interconnect Ingress Cycles Not Empty; NDR event=0x10,umask=4  01    Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_cycles_ne.snp uncore interconnect Ingress Cycles Not Empty; SNP event=0x10,umask=2  01    Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_inserts.drs uncore interconnect Ingress Allocations; DRS event=0x11,umask=8  01    Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_inserts.hom uncore interconnect Ingress Allocations; HOM event=0x11,umask=1  01    Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_inserts.ncb uncore interconnect Ingress Allocations; NCB event=0x11,umask=0x10  01    Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_inserts.ncs uncore interconnect Ingress Allocations; NCS event=0x11,umask=0x20  01    Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_inserts.ndr uncore interconnect Ingress Allocations; NDR event=0x11,umask=4  01    Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_inserts.snp uncore interconnect Ingress Allocations; SNP event=0x11,umask=2  01    Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters unc_r3_rxr_occupancy.drs uncore interconnect Ingress Occupancy Accumulator; DRS event=0x13,umask=8  01    Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency unc_r3_rxr_occupancy.hom uncore interconnect Ingress Occupancy Accumulator; HOM event=0x13,umask=1  01    Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency unc_r3_rxr_occupancy.ncb uncore interconnect Ingress Occupancy Accumulator; NCB event=0x13,umask=0x10  01    Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency unc_r3_rxr_occupancy.ncs uncore interconnect Ingress Occupancy Accumulator; NCS event=0x13,umask=0x20  01    Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency unc_r3_rxr_occupancy.ndr uncore interconnect Ingress Occupancy Accumulator; NDR event=0x13,umask=4  01    Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency unc_r3_rxr_occupancy.snp uncore interconnect Ingress Occupancy Accumulator; SNP event=0x13,umask=2  01    Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency unc_r3_vn0_credits_reject.drs uncore interconnect VN0 Credit Acquisition Failed on DRS; DRS Message Class event=0x37,umask=8  01    Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation unc_r3_vn0_credits_reject.hom uncore interconnect VN0 Credit Acquisition Failed on DRS; HOM Message Class event=0x37,umask=1  01    Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation unc_r3_vn0_credits_reject.ncb uncore interconnect VN0 Credit Acquisition Failed on DRS; NCB Message Class event=0x37,umask=0x10  01    Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation unc_r3_vn0_credits_reject.ncs uncore interconnect VN0 Credit Acquisition Failed on DRS; NCS Message Class event=0x37,umask=0x20  01    Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation unc_r3_vn0_credits_reject.ndr uncore interconnect VN0 Credit Acquisition Failed on DRS; NDR Message Class event=0x37,umask=4  01    Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation unc_r3_vn0_credits_reject.snp uncore interconnect VN0 Credit Acquisition Failed on DRS; SNP Message Class event=0x37,umask=2  01    Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation unc_r3_vn0_credits_used.drs uncore interconnect VN0 Credit Used; DRS Message Class event=0x36,umask=8  01    Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers unc_r3_vn0_credits_used.hom uncore interconnect VN0 Credit Used; HOM Message Class event=0x36,umask=1  01    Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers unc_r3_vn0_credits_used.ncb uncore interconnect VN0 Credit Used; NCB Message Class event=0x36,umask=0x10  01    Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers unc_r3_vn0_credits_used.ncs uncore interconnect VN0 Credit Used; NCS Message Class event=0x36,umask=0x20  01    Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers unc_r3_vn0_credits_used.ndr uncore interconnect VN0 Credit Used; NDR Message Class event=0x36,umask=4  01    Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers unc_r3_vn0_credits_used.snp uncore interconnect VN0 Credit Used; SNP Message Class event=0x36,umask=2  01    Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers unc_r3_vna_credits_reject.drs uncore interconnect VNA Credit Reject; DRS Message Class event=0x34,umask=8  01    Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough unc_r3_vna_credits_reject.hom uncore interconnect VNA Credit Reject; HOM Message Class event=0x34,umask=1  01    Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough unc_r3_vna_credits_reject.ncb uncore interconnect VNA Credit Reject; NCB Message Class event=0x34,umask=0x10  01    Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough unc_r3_vna_credits_reject.ncs uncore interconnect VNA Credit Reject; NCS Message Class event=0x34,umask=0x20  01    Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough unc_r3_vna_credits_reject.ndr uncore interconnect VNA Credit Reject; NDR Message Class event=0x34,umask=4  01    Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough unc_r3_vna_credits_reject.snp uncore interconnect VNA Credit Reject; SNP Message Class event=0x34,umask=2  01    Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough unc_u_msg_chnl_size_count.4b uncore interconnect MsgCh Requests by Size; 4B Requests event=0x47,umask=1  01    Number of transactions on the message channel filtered by request size.  This includes both reads and writes unc_u_msg_chnl_size_count.8b uncore interconnect MsgCh Requests by Size; 8B Requests event=0x47,umask=2  01    Number of transactions on the message channel filtered by request size.  This includes both reads and writes unc_u_phold_cycles.ack_to_deassert uncore interconnect Cycles PHOLD Assert to Ack; ACK to Deassert event=0x45,umask=2  01    PHOLD cycles.  Filter from source CoreID unc_u_racu_requests.count uncore interconnect RACU Request event=0x46,umask=1  01     unc_u_u2c_events.livelock uncore interconnect Monitor Sent to T0; Livelock event=0x43,umask=4  01    Events coming from Uncore can be sent to one or all cores unc_u_u2c_events.lterror uncore interconnect Monitor Sent to T0; LTError event=0x43,umask=8  01    Events coming from Uncore can be sent to one or all cores unc_u_u2c_events.monitor_t0 uncore interconnect Monitor Sent to T0; Monitor T0 event=0x43,umask=1  01    Events coming from Uncore can be sent to one or all cores unc_u_u2c_events.monitor_t1 uncore interconnect Monitor Sent to T0; Monitor T1 event=0x43,umask=2  01    Events coming from Uncore can be sent to one or all cores unc_u_u2c_events.other uncore interconnect Monitor Sent to T0; Other event=0x43,umask=0x80  01    Events coming from Uncore can be sent to one or all cores unc_r2_iio_credits_acquired.drs uncore io R2PCIe IIO Credit Acquired; DRS event=0x33,umask=8  01    Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly) unc_r2_iio_credits_acquired.ncb uncore io R2PCIe IIO Credit Acquired; NCB event=0x33,umask=0x10  01    Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly) unc_r2_iio_credits_acquired.ncs uncore io R2PCIe IIO Credit Acquired; NCS event=0x33,umask=0x20  01    Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly) unc_r2_iio_credits_reject.drs uncore io R2PCIe IIO Failed to Acquire a Credit; DRS event=0x34,umask=8  01    Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly) unc_r2_iio_credits_reject.ncb uncore io R2PCIe IIO Failed to Acquire a Credit; NCB event=0x34,umask=0x10  01    Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly) unc_r2_iio_credits_reject.ncs uncore io R2PCIe IIO Failed to Acquire a Credit; NCS event=0x34,umask=0x20  01    Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly) unc_r2_iio_credits_used.drs uncore io R2PCIe IIO Credits in Use; DRS event=0x32,umask=8  01    Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly) unc_r2_iio_credits_used.ncb uncore io R2PCIe IIO Credits in Use; NCB event=0x32,umask=0x10  01    Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly) unc_r2_iio_credits_used.ncs uncore io R2PCIe IIO Credits in Use; NCS event=0x32,umask=0x20  01    Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly) unc_r2_ring_ad_used.ccw_even uncore io R2 AD Ring in Use; Counterclockwise and Even event=7,umask=4  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ad_used.ccw_odd uncore io R2 AD Ring in Use; Counterclockwise and Odd event=7,umask=8  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ad_used.cw_even uncore io R2 AD Ring in Use; Clockwise and Even event=7,umask=1  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ad_used.cw_odd uncore io R2 AD Ring in Use; Clockwise and Odd event=7,umask=2  01    Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ak_used.ccw_even uncore io R2 AK Ring in Use; Counterclockwise and Even event=8,umask=4  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ak_used.ccw_odd uncore io R2 AK Ring in Use; Counterclockwise and Odd event=8,umask=8  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ak_used.cw_even uncore io R2 AK Ring in Use; Clockwise and Even event=8,umask=1  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_ak_used.cw_odd uncore io R2 AK Ring in Use; Clockwise and Odd event=8,umask=2  01    Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_bl_used.ccw_even uncore io R2 BL Ring in Use; Counterclockwise and Even event=9,umask=4  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_bl_used.ccw_odd uncore io R2 BL Ring in Use; Counterclockwise and Odd event=9,umask=8  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_bl_used.cw_even uncore io R2 BL Ring in Use; Clockwise and Even event=9,umask=1  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_bl_used.cw_odd uncore io R2 BL Ring in Use; Clockwise and Odd event=9,umask=2  01    Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop unc_r2_ring_iv_used.any uncore io R2 IV Ring in Use; Any event=0xa,umask=0xf  01    Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sunk into the ring stop.  The IV ring is unidirectional.  Whether UP or DN is used is dependent on the system programming.  Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time unc_r2_rxr_cycles_ne.drs uncore io Ingress Cycles Not Empty; DRS event=0x10,umask=8  01    Counts the number of cycles when the R2PCIe Ingress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters unc_r2_rxr_cycles_ne.ncb uncore io Ingress Cycles Not Empty; NCB event=0x10,umask=0x10  01    Counts the number of cycles when the R2PCIe Ingress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters unc_r2_rxr_cycles_ne.ncs uncore io Ingress Cycles Not Empty; NCS event=0x10,umask=0x20  01    Counts the number of cycles when the R2PCIe Ingress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters unc_r2_txr_cycles_full.ad uncore io Egress Cycles Full; AD event=0x25,umask=1  01    Counts the number of cycles when the R2PCIe Egress buffer is full unc_r2_txr_cycles_full.ak uncore io Egress Cycles Full; AK event=0x25,umask=2  01    Counts the number of cycles when the R2PCIe Egress buffer is full unc_r2_txr_cycles_full.bl uncore io Egress Cycles Full; BL event=0x25,umask=4  01    Counts the number of cycles when the R2PCIe Egress buffer is full unc_r2_txr_cycles_ne.ad uncore io Egress Cycles Not Empty; AD event=0x23,umask=1  01    Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_r2_txr_cycles_ne.ak uncore io Egress Cycles Not Empty; AK event=0x23,umask=2  01    Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_r2_txr_cycles_ne.bl uncore io Egress Cycles Not Empty; BL event=0x23,umask=4  01    Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity unc_r2_txr_nacks.ad uncore io Egress NACK; AD event=0x26,umask=1  01    Counts the number of times that the Egress received a NACK from the ring and could not issue a transaction unc_r2_txr_nacks.ak uncore io Egress NACK; AK event=0x26,umask=2  01    Counts the number of times that the Egress received a NACK from the ring and could not issue a transaction unc_r2_txr_nacks.bl uncore io Egress NACK; BL event=0x26,umask=4  01    Counts the number of times that the Egress received a NACK from the ring and could not issue a transaction unc_m_act_count uncore memory DRAM Activate Count event=1  01    Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates unc_m_cas_count.all uncore memory DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre) event=4,umask=0xf  01     unc_m_cas_count.rd uncore memory DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills) event=4,umask=3  01     unc_m_cas_count.rd_reg uncore memory DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre) event=4,umask=1  01     unc_m_cas_count.rd_underfill uncore memory DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued event=4,umask=2  01     unc_m_cas_count.wr uncore memory DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes) event=4,umask=0xc  01     unc_m_cas_count.wr_rmm uncore memory DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode event=4,umask=8  01     unc_m_cas_count.wr_wmm uncore memory DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode event=4,umask=4  01     unc_m_clockticks uncore memory uclks event=0  01    Uncore Fixed Counter - uclks unc_m_major_modes.isoch uncore memory Cycles in a Major Mode; Isoch Major Mode event=7,umask=8  01    Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode unc_m_major_modes.partial uncore memory Cycles in a Major Mode; Partial Major Mode event=7,umask=4  01    Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode unc_m_major_modes.read uncore memory Cycles in a Major Mode; Read Major Mode event=7,umask=1  01    Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode unc_m_major_modes.write uncore memory Cycles in a Major Mode; Write Major Mode event=7,umask=2  01    Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode unc_m_power_throttle_cycles.rank0 uncore memory Throttle Cycles for Rank 0; DIMM ID event=0x41,umask=1  01    Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1 unc_m_preemption.rd_preempt_rd uncore memory Read Preemption Count; Read over Read Preemption event=8,umask=1  01    Counts the number of times a read in the iMC preempts another read or write.  Generally reads to an open page are issued ahead of requests to closed pages.  This improves the page hit rate of the system.  However, high priority requests can cause pages of active requests to be closed in order to get them out.  This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency unc_m_preemption.rd_preempt_wr uncore memory Read Preemption Count; Read over Write Preemption event=8,umask=2  01    Counts the number of times a read in the iMC preempts another read or write.  Generally reads to an open page are issued ahead of requests to closed pages.  This improves the page hit rate of the system.  However, high priority requests can cause pages of active requests to be closed in order to get them out.  This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency unc_m_pre_count.page_close uncore memory DRAM Precharge commands.; Precharge due to timer expiration event=2,umask=2  01    Counts the number of DRAM Precharge commands sent on this channel unc_m_pre_count.page_miss uncore memory DRAM Precharge commands.; Precharges due to page miss event=2,umask=1  01    Counts the number of DRAM Precharge commands sent on this channel unc_m_rpq_occupancy uncore memory Read Pending Queue Occupancy event=0x80  01    Accumulates the occupancies of the Read Pending Queue each cycle.  This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory unc_m_wpq_cycles_ne uncore memory Write Pending Queue Not Empty event=0x21  01    Counts the number of cycles that the Write Pending Queue is not empty.  This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies unc_m_wpq_inserts uncore memory Write Pending Queue Allocations event=0x20  01    Counts the number of allocations into the Write Pending Queue.  This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC unc_m_wpq_occupancy uncore memory Write Pending Queue Occupancy event=0x81  01    Accumulates the occupancies of the Write Pending Queue each cycle.  This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.  So, we provide filtering based on if the request has posted or not.  By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA.  The 'posted' filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory.  High average occupancies will generally coincide with high write major mode counts unc_p_core0_transition_cycles uncore power Core C State Transition Cycles event=3  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core1_transition_cycles uncore power Core C State Transition Cycles event=4  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core2_transition_cycles uncore power Core C State Transition Cycles event=5  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core3_transition_cycles uncore power Core C State Transition Cycles event=6  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core4_transition_cycles uncore power Core C State Transition Cycles event=7  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core5_transition_cycles uncore power Core C State Transition Cycles event=8  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core6_transition_cycles uncore power Core C State Transition Cycles event=9  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_core7_transition_cycles uncore power Core C State Transition Cycles event=0xa  01    Number of cycles spent performing core C state transitions.  There is one event per core unc_p_demotions_core0 uncore power Core C State Demotions event=0x1e  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core1 uncore power Core C State Demotions event=0x1f  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core2 uncore power Core C State Demotions event=0x20  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core3 uncore power Core C State Demotions event=0x21  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core4 uncore power Core C State Demotions event=0x22  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core5 uncore power Core C State Demotions event=0x23  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core6 uncore power Core C State Demotions event=0x24  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_demotions_core7 uncore power Core C State Demotions event=0x25  01    Counts the number of times when a configurable cores had a C-state demotion unc_p_freq_min_io_p_cycles uncore power IO P Limit Strongest Lower Limit Cycles event=1  01    Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower.  This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW.  This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth unc_p_freq_min_perf_p_cycles uncore power Perf P Limit Strongest Lower Limit Cycles event=2  01    Counts the number of cycles when Perf P Limit is preventing us from dropping the frequency lower.  Perf P Limit is an algorithm that takes input from remote sockets when determining if a socket should drop it's frequency down.  This is largely to minimize increases in snoop and remote read latencies unc_p_freq_trans_cycles uncore power Cycles spent changing Frequency event=0  01    Counts the number of cycles when the system is changing frequency.  This can not be filtered by thread ID.  One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system unc_p_power_state_occupancy.cores_c0 uncore power Number of cores in C0 event=0x80,occ_sel=1  01    This is an occupancy event that tracks the number of cores that are in C0.  It can be used by itself to get the average number of cores in C0, with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_power_state_occupancy.cores_c3 uncore power Number of cores in C0 event=0x80,occ_sel=2  01    This is an occupancy event that tracks the number of cores that are in C0.  It can be used by itself to get the average number of cores in C0, with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_power_state_occupancy.cores_c6 uncore power Number of cores in C0 event=0x80,occ_sel=3  01    This is an occupancy event that tracks the number of cores that are in C0.  It can be used by itself to get the average number of cores in C0, with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details unc_p_total_transition_cycles uncore power Total Core C State Transition Cycles event=0xb  01    Number of cycles spent performing core C state transitions across all cores dtlb_load_misses.miss_causes_a_walk virtual memory Load misses in all DTLB levels that cause page walks event=8,period=100003,umask=1  00     dtlb_load_misses.stlb_hit virtual memory Load operations that miss the first DTLB level but hit the second and do not cause page walks event=8,period=100003,umask=0x10  00    This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles dtlb_load_misses.walk_completed virtual memory Load misses at all DTLB levels that cause completed page walks event=8,period=100003,umask=2  00     dtlb_load_misses.walk_duration virtual memory Cycles when PMH is busy with page walks event=8,period=2000003,umask=4  00    This event counts cycles when the  page miss handler (PMH) is servicing page walks caused by DTLB load misses dtlb_store_misses.miss_causes_a_walk virtual memory Store misses in all DTLB levels that cause page walks event=0x49,period=100003,umask=1  00     dtlb_store_misses.walk_completed virtual memory Store misses in all DTLB levels that cause completed page walks event=0x49,period=100003,umask=2  00     dtlb_store_misses.walk_duration virtual memory Cycles when PMH is busy with page walks event=0x49,period=2000003,umask=4  00     itlb.itlb_flush virtual memory Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages event=0xae,period=100007,umask=1  00     itlb_misses.miss_causes_a_walk virtual memory Misses at all ITLB levels that cause page walks event=0x85,period=100003,umask=1  00     itlb_misses.stlb_hit virtual memory Operations that miss the first ITLB level but hit the second and do not cause any page walks event=0x85,period=100003,umask=0x10  00     itlb_misses.walk_duration virtual memory Cycles when PMH is busy with page walks event=0x85,period=2000003,umask=4  00    This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses tlb_flush.stlb_any virtual memory STLB flush attempts event=0xbd,period=100007,umask=0x20  00     core_reject_l2q.all cache Counts the number of MEC requests that were not accepted into the L2Q because of any L2  queue reject condition. There is no concept of at-ret here. It might include requests due to instructions in the speculative path event=0x31,period=200003  00     fetch_stall.icache_fill_pending_cycles cache This event counts the number of core cycles the fetch stalls because of an icache miss. This is a cumulative count of cycles the NIP stalled for all icache misses event=0x86,period=200003,umask=4  00     l2_prefetcher.alloc_xq cache Counts the number of L2HWP allocated into XQ GP event=0x3e,period=100007,umask=4  00     l2_requests.miss cache Counts the number of L2 cache misses event=0x2e,period=200003,umask=0x41  00     l2_requests.reference cache Counts the total number of L2 cache references event=0x2e,period=200003,umask=0x4f  00     l2_requests_reject.all cache Counts the number of MEC requests from the L2Q that reference a cache line (cacheable requests) excluding SW prefetches filling only to L2 cache and L1 evictions (automatically excludes L2HWP, UC, WC) that were rejected - Multiple repeated rejects should be counted multiple times event=0x30,period=200003  00     mem_uops_retired.all_loads cache Counts all the load micro-ops retired event=4,period=200003,umask=0x40  00    This event counts the number of load micro-ops retired mem_uops_retired.all_stores cache Counts all the store micro-ops retired event=4,period=200003,umask=0x80  00    This event counts the number of store micro-ops retired mem_uops_retired.hitm cache Counts the loads retired that get the data from the other core in the same tile in M state (Precise Event)  Supports address when precise event=4,period=200003,umask=0x20  00    This event counts the number of load micro-ops retired that got data from another core's cache. (Precise Event)  Supports address when precise mem_uops_retired.l1_miss_loads cache Counts the number of load micro-ops retired that miss in L1 D cache event=4,period=200003,umask=1  00    This event counts the number of load micro-ops retired that miss in L1 Data cache. Note that prefetch misses will not be counted mem_uops_retired.l2_hit_loads cache Counts the number of load micro-ops retired that hit in the L2 (Precise Event)  Supports address when precise event=4,period=200003,umask=2  00    This event counts the number of load micro-uops retired that hit in the L2 (Precise Event)  Supports address when precise mem_uops_retired.l2_miss_loads cache Counts the number of load micro-ops retired that miss in the L2 (Precise Event)  Supports address when precise event=4,period=100007,umask=4  00    This event counts the number of load micro-ops retired that miss in the L2 (Precise Event)  Supports address when precise mem_uops_retired.utlb_miss_loads cache Counts the number of load micro-ops retired that caused micro TLB miss event=4,period=200003,umask=0x10  00     offcore_response cache Counts the matrix events specified by MSR_OFFCORE_RESPx event=0xb7,period=100007,umask=1  00     offcore_response.any_code_rd.any_response cache Counts Demand code reads and prefetch code read requests  that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010044  00     offcore_response.any_code_rd.l2_hit_far_tile cache Counts Demand code reads and prefetch code read requests  that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x1800400044  00     offcore_response.any_code_rd.l2_hit_far_tile_e_f cache Counts Demand code reads and prefetch code read requests  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x0800400044  00     offcore_response.any_code_rd.l2_hit_far_tile_m cache Counts Demand code reads and prefetch code read requests  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000400044  00     offcore_response.any_code_rd.l2_hit_near_tile cache Counts Demand code reads and prefetch code read requests  that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1800180044  00     offcore_response.any_code_rd.l2_hit_near_tile_e_f cache Counts Demand code reads and prefetch code read requests  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0800080044  00     offcore_response.any_code_rd.l2_hit_near_tile_m cache Counts Demand code reads and prefetch code read requests  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000080044  00     offcore_response.any_code_rd.l2_hit_this_tile_e cache Counts Demand code reads and prefetch code read requests  that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x0004000044  00     offcore_response.any_code_rd.l2_hit_this_tile_f cache Counts Demand code reads and prefetch code read requests  that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0010000044  00     offcore_response.any_code_rd.l2_hit_this_tile_m cache Counts Demand code reads and prefetch code read requests  that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x0002000044  00     offcore_response.any_code_rd.l2_hit_this_tile_s cache Counts Demand code reads and prefetch code read requests  that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=1,offcore_rsp=0x0008000044  00     offcore_response.any_code_rd.outstanding cache Counts Demand code reads and prefetch code read requests  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000044  00     offcore_response.any_data_rd.any_response cache Counts Demand cacheable data and L1 prefetch data read requests  that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000013091  00     offcore_response.any_data_rd.l2_hit_far_tile cache Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x1800403091  00     offcore_response.any_data_rd.l2_hit_far_tile_e_f cache Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x0800403091  00     offcore_response.any_data_rd.l2_hit_far_tile_m cache Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000403091  00     offcore_response.any_data_rd.l2_hit_near_tile cache Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1800183091  00     offcore_response.any_data_rd.l2_hit_near_tile_e_f cache Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0800083091  00     offcore_response.any_data_rd.l2_hit_near_tile_m cache Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000083091  00     offcore_response.any_data_rd.l2_hit_this_tile_e cache Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x0004003091  00     offcore_response.any_data_rd.l2_hit_this_tile_f cache Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0010003091  00     offcore_response.any_data_rd.l2_hit_this_tile_m cache Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x0002003091  00     offcore_response.any_data_rd.l2_hit_this_tile_s cache Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=1,offcore_rsp=0x0008003091  00     offcore_response.any_data_rd.outstanding cache Counts Demand cacheable data and L1 prefetch data read requests  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=1,offcore_rsp=0x4000003091  00     offcore_response.any_pf_l2.any_response cache Counts any Prefetch requests that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010070  00     offcore_response.any_pf_l2.l2_hit_far_tile cache Counts any Prefetch requests that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x1800400070  00     offcore_response.any_pf_l2.l2_hit_far_tile_e_f cache Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x0800400070  00     offcore_response.any_pf_l2.l2_hit_far_tile_m cache Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000400070  00     offcore_response.any_pf_l2.l2_hit_near_tile cache Counts any Prefetch requests that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1800180070  00     offcore_response.any_pf_l2.l2_hit_near_tile_e_f cache Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0800080070  00     offcore_response.any_pf_l2.l2_hit_near_tile_m cache Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000080070  00     offcore_response.any_pf_l2.l2_hit_this_tile_e cache Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x0004000070  00     offcore_response.any_pf_l2.l2_hit_this_tile_f cache Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0010000070  00     offcore_response.any_pf_l2.l2_hit_this_tile_m cache Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x0002000070  00     offcore_response.any_pf_l2.outstanding cache Counts any Prefetch requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000070  00     offcore_response.any_read.any_response cache Counts any Read request  that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x00000132f7  00     offcore_response.any_read.l2_hit_far_tile cache Counts any Read request  that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x18004032f7  00     offcore_response.any_read.l2_hit_far_tile_e_f cache Counts any Read request  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x08004032f7  00     offcore_response.any_read.l2_hit_far_tile_m cache Counts any Read request  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x10004032f7  00     offcore_response.any_read.l2_hit_near_tile cache Counts any Read request  that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=1,offcore_rsp=0x18001832f7  00     offcore_response.any_read.l2_hit_near_tile_e_f cache Counts any Read request  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x08000832f7  00     offcore_response.any_read.l2_hit_near_tile_m cache Counts any Read request  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x10000832f7  00     offcore_response.any_read.l2_hit_this_tile_e cache Counts any Read request  that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x00040032f7  00     offcore_response.any_read.l2_hit_this_tile_f cache Counts any Read request  that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x00100032f7  00     offcore_response.any_read.l2_hit_this_tile_m cache Counts any Read request  that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x00020032f7  00     offcore_response.any_read.l2_hit_this_tile_s cache Counts any Read request  that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=1,offcore_rsp=0x00080032f7  00     offcore_response.any_read.outstanding cache Counts any Read request  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=1,offcore_rsp=0x40000032f7  00     offcore_response.any_request.any_response cache Counts any request that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000018000  00     offcore_response.any_request.l2_hit_far_tile cache Counts any request that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x1800408000  00     offcore_response.any_request.l2_hit_far_tile_e_f cache Counts any request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x0800408000  00     offcore_response.any_request.l2_hit_far_tile_m cache Counts any request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000408000  00     offcore_response.any_request.l2_hit_near_tile cache Counts any request that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1800188000  00     offcore_response.any_request.l2_hit_near_tile_e_f cache Counts any request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0800088000  00     offcore_response.any_request.l2_hit_near_tile_m cache Counts any request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000088000  00     offcore_response.any_request.l2_hit_this_tile_e cache Counts any request that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x0004008000  00     offcore_response.any_request.l2_hit_this_tile_f cache Counts any request that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0010008000  00     offcore_response.any_request.l2_hit_this_tile_m cache Counts any request that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x0002008000  00     offcore_response.any_request.l2_hit_this_tile_s cache Counts any request that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=1,offcore_rsp=0x0008008000  00     offcore_response.any_request.l2_miss cache Accounts for responses which miss its own tile's L2 event=0xb7,period=100007,umask=1,offcore_rsp=0x18001981F8  00     offcore_response.any_request.outstanding cache Counts any request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=1,offcore_rsp=0x4000008000  00     offcore_response.any_rfo.any_response cache Counts Demand cacheable data write requests  that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010022  00     offcore_response.any_rfo.l2_hit_far_tile cache Counts Demand cacheable data write requests  that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x1800400022  00     offcore_response.any_rfo.l2_hit_far_tile_e_f cache Counts Demand cacheable data write requests  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x0800400022  00     offcore_response.any_rfo.l2_hit_far_tile_m cache Counts Demand cacheable data write requests  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000400022  00     offcore_response.any_rfo.l2_hit_near_tile cache Counts Demand cacheable data write requests  that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1800180022  00     offcore_response.any_rfo.l2_hit_near_tile_e_f cache Counts Demand cacheable data write requests  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0800080022  00     offcore_response.any_rfo.l2_hit_near_tile_m cache Counts Demand cacheable data write requests  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000080022  00     offcore_response.any_rfo.l2_hit_this_tile_e cache Counts Demand cacheable data write requests  that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x0004000022  00     offcore_response.any_rfo.l2_hit_this_tile_f cache Counts Demand cacheable data write requests  that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0010000022  00     offcore_response.any_rfo.l2_hit_this_tile_m cache Counts Demand cacheable data write requests  that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x0002000022  00     offcore_response.any_rfo.l2_hit_this_tile_s cache Counts Demand cacheable data write requests  that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=1,offcore_rsp=0x0008000022  00     offcore_response.any_rfo.outstanding cache Counts Demand cacheable data write requests  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000022  00     offcore_response.bus_locks.any_response cache Counts Bus locks and split lock requests that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010400  00     offcore_response.bus_locks.l2_hit_far_tile cache Counts Bus locks and split lock requests that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x1800400400  00     offcore_response.bus_locks.l2_hit_far_tile_e_f cache Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x0800400400  00     offcore_response.bus_locks.l2_hit_far_tile_m cache Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000400400  00     offcore_response.bus_locks.l2_hit_near_tile cache Counts Bus locks and split lock requests that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1800180400  00     offcore_response.bus_locks.l2_hit_near_tile_e_f cache Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0800080400  00     offcore_response.bus_locks.l2_hit_near_tile_m cache Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000080400  00     offcore_response.bus_locks.l2_hit_this_tile_e cache Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x0004000400  00     offcore_response.bus_locks.l2_hit_this_tile_f cache Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0010000400  00     offcore_response.bus_locks.l2_hit_this_tile_m cache Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x0002000400  00     offcore_response.bus_locks.l2_hit_this_tile_s cache Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=1,offcore_rsp=0x0008000400  00     offcore_response.bus_locks.outstanding cache Counts Bus locks and split lock requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000400  00     offcore_response.demand_code_rd.any_response cache Counts demand code reads and prefetch code reads that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010004  00     offcore_response.demand_code_rd.l2_hit_far_tile cache Counts demand code reads and prefetch code reads that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x1800400004  00     offcore_response.demand_code_rd.l2_hit_far_tile_e_f cache Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x0800400004  00     offcore_response.demand_code_rd.l2_hit_far_tile_m cache Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000400004  00     offcore_response.demand_code_rd.l2_hit_near_tile cache Counts demand code reads and prefetch code reads that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1800180004  00     offcore_response.demand_code_rd.l2_hit_near_tile_e_f cache Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0800080004  00     offcore_response.demand_code_rd.l2_hit_near_tile_m cache Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000080004  00     offcore_response.demand_code_rd.l2_hit_this_tile_e cache Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x0004000004  00     offcore_response.demand_code_rd.l2_hit_this_tile_f cache Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0010000004  00     offcore_response.demand_code_rd.l2_hit_this_tile_m cache Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x0002000004  00     offcore_response.demand_code_rd.l2_hit_this_tile_s cache Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=1,offcore_rsp=0x0008000004  00     offcore_response.demand_code_rd.outstanding cache Counts demand code reads and prefetch code reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000004  00     offcore_response.demand_data_rd.any_response cache Counts demand cacheable data and L1 prefetch data reads that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010001  00     offcore_response.demand_data_rd.l2_hit_far_tile_e_f cache Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x0800400001  00     offcore_response.demand_data_rd.l2_hit_far_tile_m cache Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000400001  00     offcore_response.demand_data_rd.l2_hit_near_tile_e_f cache Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0800080001  00     offcore_response.demand_data_rd.l2_hit_near_tile_m cache Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000080001  00     offcore_response.demand_data_rd.l2_hit_this_tile_e cache Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x0004000001  00     offcore_response.demand_data_rd.l2_hit_this_tile_f cache Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0010000001  00     offcore_response.demand_data_rd.l2_hit_this_tile_m cache Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x0002000001  00     offcore_response.demand_data_rd.l2_hit_this_tile_s cache Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=1,offcore_rsp=0x0008000001  00     offcore_response.demand_data_rd.outstanding cache Counts demand cacheable data and L1 prefetch data reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000001  00     offcore_response.demand_rfo.any_response cache Counts Demand cacheable data writes that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010002  00     offcore_response.demand_rfo.l2_hit_far_tile cache Counts Demand cacheable data writes that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x1800400002  00     offcore_response.demand_rfo.l2_hit_far_tile_e_f cache Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x0800400002  00     offcore_response.demand_rfo.l2_hit_far_tile_m cache Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000400002  00     offcore_response.demand_rfo.l2_hit_near_tile cache Counts Demand cacheable data writes that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1800180002  00     offcore_response.demand_rfo.l2_hit_near_tile_e_f cache Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0800080002  00     offcore_response.demand_rfo.l2_hit_near_tile_m cache Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000080002  00     offcore_response.demand_rfo.l2_hit_this_tile_e cache Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x0004000002  00     offcore_response.demand_rfo.l2_hit_this_tile_f cache Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0010000002  00     offcore_response.demand_rfo.l2_hit_this_tile_m cache Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x0002000002  00     offcore_response.demand_rfo.l2_hit_this_tile_s cache Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=1,offcore_rsp=0x0008000002  00     offcore_response.demand_rfo.outstanding cache Counts Demand cacheable data writes that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000002  00     offcore_response.full_streaming_stores.any_response cache Counts Full streaming stores (WC and should be programmed on PMC1) that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010800  00     offcore_response.partial_reads.any_response cache Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010080  00     offcore_response.partial_reads.l2_hit_far_tile cache Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x1800400080  00     offcore_response.partial_reads.l2_hit_far_tile_e_f cache Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x0800400080  00     offcore_response.partial_reads.l2_hit_far_tile_m cache Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000400080  00     offcore_response.partial_reads.l2_hit_near_tile cache Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1800180080  00     offcore_response.partial_reads.l2_hit_near_tile_e_f cache Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0800080080  00     offcore_response.partial_reads.l2_hit_near_tile_m cache Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000080080  00     offcore_response.partial_reads.l2_hit_this_tile_e cache Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x0004000080  00     offcore_response.partial_reads.l2_hit_this_tile_f cache Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0010000080  00     offcore_response.partial_reads.l2_hit_this_tile_m cache Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x0002000080  00     offcore_response.partial_reads.l2_hit_this_tile_s cache Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=1,offcore_rsp=0x0008000080  00     offcore_response.partial_reads.outstanding cache Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000080  00     offcore_response.partial_streaming_stores.any_response cache Counts Partial streaming stores (WC and should be programmed on PMC1) that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000014000  00     offcore_response.partial_writes.any_response cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010100  00     offcore_response.partial_writes.l2_hit_far_tile cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x1800400100  00     offcore_response.partial_writes.l2_hit_far_tile_e_f cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x0800400100  00     offcore_response.partial_writes.l2_hit_far_tile_m cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000400100  00     offcore_response.partial_writes.l2_hit_near_tile cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1800180100  00     offcore_response.partial_writes.l2_hit_near_tile_e_f cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0800080100  00     offcore_response.partial_writes.l2_hit_near_tile_m cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000080100  00     offcore_response.partial_writes.l2_hit_this_tile_e cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x0004000100  00     offcore_response.partial_writes.l2_hit_this_tile_f cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0010000100  00     offcore_response.partial_writes.l2_hit_this_tile_m cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x0002000100  00     offcore_response.partial_writes.l2_hit_this_tile_s cache Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=1,offcore_rsp=0x0008000100  00     offcore_response.pf_l1_data_rd.any_response cache Counts L1 data HW prefetches that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000012000  00     offcore_response.pf_l1_data_rd.l2_hit_far_tile cache Counts L1 data HW prefetches that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x1800402000  00     offcore_response.pf_l1_data_rd.l2_hit_far_tile_e_f cache Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x0800402000  00     offcore_response.pf_l1_data_rd.l2_hit_far_tile_m cache Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000402000  00     offcore_response.pf_l1_data_rd.l2_hit_near_tile cache Counts L1 data HW prefetches that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1800182000  00     offcore_response.pf_l1_data_rd.l2_hit_near_tile_e_f cache Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0800082000  00     offcore_response.pf_l1_data_rd.l2_hit_near_tile_m cache Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000082000  00     offcore_response.pf_l1_data_rd.l2_hit_this_tile_e cache Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x0004002000  00     offcore_response.pf_l1_data_rd.l2_hit_this_tile_f cache Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0010002000  00     offcore_response.pf_l1_data_rd.l2_hit_this_tile_m cache Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x0002002000  00     offcore_response.pf_l1_data_rd.l2_hit_this_tile_s cache Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=1,offcore_rsp=0x0008002000  00     offcore_response.pf_l1_data_rd.outstanding cache Counts L1 data HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=1,offcore_rsp=0x4000002000  00     offcore_response.pf_l2_code_rd.any_response cache Counts L2 code HW prefetches that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010040  00     offcore_response.pf_l2_code_rd.l2_hit_far_tile cache Counts L2 code HW prefetches that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x1800400040  00     offcore_response.pf_l2_code_rd.l2_hit_far_tile_e_f cache Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x0800400040  00     offcore_response.pf_l2_code_rd.l2_hit_far_tile_m cache Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000400040  00     offcore_response.pf_l2_code_rd.l2_hit_near_tile cache Counts L2 code HW prefetches that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1800180040  00     offcore_response.pf_l2_code_rd.l2_hit_near_tile_e_f cache Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0800080040  00     offcore_response.pf_l2_code_rd.l2_hit_near_tile_m cache Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000080040  00     offcore_response.pf_l2_code_rd.l2_hit_this_tile_e cache Counts L2 code HW prefetches that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x0004000040  00     offcore_response.pf_l2_code_rd.l2_hit_this_tile_f cache Counts L2 code HW prefetches that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0010000040  00     offcore_response.pf_l2_code_rd.outstanding cache Counts L2 code HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000040  00     offcore_response.pf_l2_rfo.any_response cache Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010020  00     offcore_response.pf_l2_rfo.l2_hit_far_tile_e_f cache Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x0800400020  00     offcore_response.pf_l2_rfo.l2_hit_far_tile_m cache Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000400020  00     offcore_response.pf_l2_rfo.l2_hit_near_tile cache Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1800180020  00     offcore_response.pf_l2_rfo.l2_hit_near_tile_e_f cache Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0800080020  00     offcore_response.pf_l2_rfo.l2_hit_near_tile_m cache Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000080020  00     offcore_response.pf_l2_rfo.l2_hit_this_tile_e cache Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x0004000020  00     offcore_response.pf_l2_rfo.l2_hit_this_tile_f cache Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0010000020  00     offcore_response.pf_l2_rfo.l2_hit_this_tile_m cache Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x0002000020  00     offcore_response.pf_l2_rfo.l2_hit_this_tile_s cache Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=1,offcore_rsp=0x0008000020  00     offcore_response.pf_software.any_response cache Counts Software Prefetches that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000011000  00     offcore_response.pf_software.l2_hit_far_tile cache Counts Software Prefetches that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x1800401000  00     offcore_response.pf_software.l2_hit_far_tile_e_f cache Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x0800401000  00     offcore_response.pf_software.l2_hit_far_tile_m cache Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000401000  00     offcore_response.pf_software.l2_hit_near_tile cache Counts Software Prefetches that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1800181000  00     offcore_response.pf_software.l2_hit_near_tile_e_f cache Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0800081000  00     offcore_response.pf_software.l2_hit_near_tile_m cache Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000081000  00     offcore_response.pf_software.l2_hit_this_tile_e cache Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x0004001000  00     offcore_response.pf_software.l2_hit_this_tile_f cache Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0010001000  00     offcore_response.pf_software.l2_hit_this_tile_m cache Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x0002001000  00     offcore_response.pf_software.l2_hit_this_tile_s cache Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=1,offcore_rsp=0x0008001000  00     offcore_response.pf_software.outstanding cache Counts Software Prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=1,offcore_rsp=0x4000001000  00     offcore_response.streaming_stores.any_response cache Counts all streaming stores (WC and should be programmed on PMC1) that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000014800  00     offcore_response.uc_code_reads.any_response cache Counts UC code reads (valid only for Outstanding response type)  that accounts for any response event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010200  00     offcore_response.uc_code_reads.l2_hit_far_tile_e_f cache Counts UC code reads (valid only for Outstanding response type)  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=1,offcore_rsp=0x0800400200  00     offcore_response.uc_code_reads.l2_hit_far_tile_m cache Counts UC code reads (valid only for Outstanding response type)  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000400200  00     offcore_response.uc_code_reads.l2_hit_near_tile cache Counts UC code reads (valid only for Outstanding response type)  that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1800180200  00     offcore_response.uc_code_reads.l2_hit_near_tile_e_f cache Counts UC code reads (valid only for Outstanding response type)  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0800080200  00     offcore_response.uc_code_reads.l2_hit_near_tile_m cache Counts UC code reads (valid only for Outstanding response type)  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x1000080200  00     offcore_response.uc_code_reads.l2_hit_this_tile_e cache Counts UC code reads (valid only for Outstanding response type)  that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=1,offcore_rsp=0x0004000200  00     offcore_response.uc_code_reads.l2_hit_this_tile_f cache Counts UC code reads (valid only for Outstanding response type)  that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=1,offcore_rsp=0x0010000200  00     offcore_response.uc_code_reads.l2_hit_this_tile_m cache Counts UC code reads (valid only for Outstanding response type)  that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=1,offcore_rsp=0x0002000200  00     offcore_response.uc_code_reads.l2_hit_this_tile_s cache Counts UC code reads (valid only for Outstanding response type)  that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=1,offcore_rsp=0x0008000200  00     offcore_response.uc_code_reads.outstanding cache Counts UC code reads (valid only for Outstanding response type)  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000200  00     machine_clears.fp_assist floating point Counts the number of floating operations retired that required microcode assists event=0xc3,period=200003,umask=4  00    This event counts the number of times that the pipeline stalled due to FP operations needing assists uops_retired.packed_simd floating point Counts the number of packed SSE, AVX, AVX2, AVX-512 micro-ops (both floating point and integer) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies event=0xc2,period=200003,umask=0x40  00    The length of the packed operation (128bits, 256bits or 512bits) is not taken into account when updating the counter; all count the same (+1). 
Mask (k) registers are ignored. For example: a micro-op operating with a mask that only enables one element or even zero elements will still trigger this counter (+1)
This event is defined at the micro-op level and not instruction level. Most instructions are implemented with one micro-op but not all uops_retired.scalar_simd floating point Counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops except for loads (memory-to-register mov-type micro ops), division, sqrt event=0xc2,period=200003,umask=0x20  00    This event is defined at the micro-op level and not instruction level. Most instructions are implemented with one micro-op but not all baclears.all frontend Counts the number of times the front end resteers for any branch as a result of another branch handling mechanism in the front end event=0xe6,period=200003,umask=1  00     baclears.cond frontend Counts the number of times the front end resteers for conditional branches as a result of another branch handling mechanism in the front end event=0xe6,period=200003,umask=0x10  00     baclears.return frontend Counts the number of times the front end resteers for RET branches as a result of another branch handling mechanism in the front end event=0xe6,period=200003,umask=8  00     icache.accesses frontend Counts all instruction fetches, including uncacheable fetches event=0x80,period=200003,umask=3  00     icache.hit frontend Counts all instruction fetches that hit the instruction cache event=0x80,period=200003,umask=1  00     icache.misses frontend Counts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstanding event=0x80,period=200003,umask=2  00     ms_decoded.ms_entry frontend Counts the number of times the MSROM starts a flow of uops event=0xe7,period=200003,umask=1  00     machine_clears.memory_ordering memory Counts the number of times the machine clears due to memory ordering hazards event=0xc3,period=200003,umask=2  00     offcore_response.any_code_rd.ddr memory Counts Demand code reads and prefetch code read requests  that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0181800044  00     offcore_response.any_code_rd.ddr_far memory Counts Demand code reads and prefetch code read requests  that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x0101000044  00     offcore_response.any_code_rd.ddr_near memory Counts Demand code reads and prefetch code read requests  that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080800044  00     offcore_response.any_code_rd.mcdram memory Counts Demand code reads and prefetch code read requests  that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0180600044  00     offcore_response.any_code_rd.mcdram_far memory Counts Demand code reads and prefetch code read requests  that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x0100400044  00     offcore_response.any_code_rd.mcdram_near memory Counts Demand code reads and prefetch code read requests  that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080200044  00     offcore_response.any_data_rd.ddr memory Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0181803091  00     offcore_response.any_data_rd.ddr_far memory Counts Demand cacheable data and L1 prefetch data read requests  that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x0101003091  00     offcore_response.any_data_rd.ddr_near memory Counts Demand cacheable data and L1 prefetch data read requests  that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080803091  00     offcore_response.any_data_rd.mcdram memory Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0180603091  00     offcore_response.any_data_rd.mcdram_far memory Counts Demand cacheable data and L1 prefetch data read requests  that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x0100403091  00     offcore_response.any_data_rd.mcdram_near memory Counts Demand cacheable data and L1 prefetch data read requests  that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080203091  00     offcore_response.any_pf_l2.ddr_far memory Counts any Prefetch requests that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x0101000070  00     offcore_response.any_pf_l2.ddr_near memory Counts any Prefetch requests that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080800070  00     offcore_response.any_pf_l2.mcdram memory Counts any Prefetch requests that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0180600070  00     offcore_response.any_pf_l2.mcdram_far memory Counts any Prefetch requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x0100400070  00     offcore_response.any_pf_l2.mcdram_near memory Counts any Prefetch requests that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080200070  00     offcore_response.any_read.ddr memory Counts any Read request  that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x01818032f7  00     offcore_response.any_read.ddr_far memory Counts any Read request  that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x01010032f7  00     offcore_response.any_read.ddr_near memory Counts any Read request  that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x00808032f7  00     offcore_response.any_read.mcdram memory Counts any Read request  that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x01806032f7  00     offcore_response.any_read.mcdram_far memory Counts any Read request  that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x01004032f7  00     offcore_response.any_read.mcdram_near memory Counts any Read request  that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x00802032f7  00     offcore_response.any_request.ddr memory Counts any request that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0181808000  00     offcore_response.any_request.ddr_far memory Counts any request that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x0101008000  00     offcore_response.any_request.ddr_near memory Counts any request that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080808000  00     offcore_response.any_request.mcdram memory Counts any request that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0180608000  00     offcore_response.any_request.mcdram_far memory Counts any request that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x0100408000  00     offcore_response.any_request.mcdram_near memory Counts any request that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080208000  00     offcore_response.any_rfo.ddr memory Counts Demand cacheable data write requests  that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0181800022  00     offcore_response.any_rfo.ddr_far memory Counts Demand cacheable data write requests  that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x0101000022  00     offcore_response.any_rfo.ddr_near memory Counts Demand cacheable data write requests  that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080800022  00     offcore_response.any_rfo.mcdram memory Counts Demand cacheable data write requests  that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0180600022  00     offcore_response.any_rfo.mcdram_far memory Counts Demand cacheable data write requests  that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x0100400022  00     offcore_response.any_rfo.mcdram_near memory Counts Demand cacheable data write requests  that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080200022  00     offcore_response.bus_locks.ddr memory Counts Bus locks and split lock requests that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0181800400  00     offcore_response.bus_locks.ddr_far memory Counts Bus locks and split lock requests that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x0101000400  00     offcore_response.bus_locks.ddr_near memory Counts Bus locks and split lock requests that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080800400  00     offcore_response.bus_locks.mcdram memory Counts Bus locks and split lock requests that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0180600400  00     offcore_response.bus_locks.mcdram_far memory Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x0100400400  00     offcore_response.bus_locks.mcdram_near memory Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080200400  00     offcore_response.demand_code_rd.ddr memory Counts demand code reads and prefetch code reads that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0181800004  00     offcore_response.demand_code_rd.ddr_far memory Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x0101000004  00     offcore_response.demand_code_rd.ddr_near memory Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080800004  00     offcore_response.demand_code_rd.mcdram memory Counts demand code reads and prefetch code reads that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0180600004  00     offcore_response.demand_code_rd.mcdram_far memory Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x0100400004  00     offcore_response.demand_code_rd.mcdram_near memory Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080200004  00     offcore_response.demand_data_rd.ddr memory Counts demand cacheable data and L1 prefetch data reads that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0181800001  00     offcore_response.demand_data_rd.ddr_far memory Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x0101000001  00     offcore_response.demand_data_rd.ddr_near memory Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080800001  00     offcore_response.demand_data_rd.mcdram memory Counts demand cacheable data and L1 prefetch data reads that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0180600001  00     offcore_response.demand_data_rd.mcdram_far memory Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x0100400001  00     offcore_response.demand_data_rd.mcdram_near memory Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080200001  00     offcore_response.demand_rfo.ddr memory Counts Demand cacheable data writes that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0181800002  00     offcore_response.demand_rfo.ddr_far memory Counts Demand cacheable data writes that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x0101000002  00     offcore_response.demand_rfo.ddr_near memory Counts Demand cacheable data writes that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080800002  00     offcore_response.demand_rfo.mcdram memory Counts Demand cacheable data writes that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0180600002  00     offcore_response.demand_rfo.mcdram_far memory Counts Demand cacheable data writes that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x0100400002  00     offcore_response.demand_rfo.mcdram_near memory Counts Demand cacheable data writes that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080200002  00     offcore_response.partial_reads.ddr memory Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0181800080  00     offcore_response.partial_reads.ddr_far memory Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x0101000080  00     offcore_response.partial_reads.ddr_near memory Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080800080  00     offcore_response.partial_reads.mcdram memory Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0180600080  00     offcore_response.partial_reads.mcdram_far memory Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x0100400080  00     offcore_response.partial_reads.mcdram_near memory Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080200080  00     offcore_response.partial_reads.non_dram memory Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from any NON_DRAM system address. This includes MMIO transactions event=0xb7,period=100007,umask=1,offcore_rsp=0x2000020080  00     offcore_response.partial_writes.ddr_far memory Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x0101000100  00     offcore_response.partial_writes.ddr_near memory Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080800100  00     offcore_response.partial_writes.mcdram memory Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0180600100  00     offcore_response.partial_writes.mcdram_far memory Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x0100400100  00     offcore_response.partial_writes.mcdram_near memory Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080200100  00     offcore_response.pf_l1_data_rd.ddr memory Counts L1 data HW prefetches that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0181802000  00     offcore_response.pf_l1_data_rd.ddr_far memory Counts L1 data HW prefetches that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x0101002000  00     offcore_response.pf_l1_data_rd.ddr_near memory Counts L1 data HW prefetches that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080802000  00     offcore_response.pf_l1_data_rd.mcdram_far memory Counts L1 data HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x0100402000  00     offcore_response.pf_l1_data_rd.mcdram_near memory Counts L1 data HW prefetches that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080202000  00     offcore_response.pf_l2_code_rd.ddr memory Counts L2 code HW prefetches that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0181800040  00     offcore_response.pf_l2_code_rd.ddr_far memory Counts L2 code HW prefetches that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x0101000040  00     offcore_response.pf_l2_code_rd.ddr_near memory Counts L2 code HW prefetches that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080800040  00     offcore_response.pf_l2_code_rd.mcdram_far memory Counts L2 code HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x0100400040  00     offcore_response.pf_l2_code_rd.mcdram_near memory Counts L2 code HW prefetches that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080200040  00     offcore_response.pf_l2_rfo.ddr memory Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0181800020  00     offcore_response.pf_l2_rfo.ddr_far memory Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x0101000020  00     offcore_response.pf_l2_rfo.ddr_near memory Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080800020  00     offcore_response.pf_l2_rfo.mcdram memory Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0180600020  00     offcore_response.pf_l2_rfo.mcdram_far memory Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x0100400020  00     offcore_response.pf_l2_rfo.mcdram_near memory Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080200020  00     offcore_response.pf_l2_rfo.non_dram memory Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from any NON_DRAM system address. This includes MMIO transactions event=0xb7,period=100007,umask=1,offcore_rsp=0x2000020020  00     offcore_response.pf_software.ddr memory Counts Software Prefetches that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0181801000  00     offcore_response.pf_software.ddr_far memory Counts Software Prefetches that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x0101001000  00     offcore_response.pf_software.ddr_near memory Counts Software Prefetches that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080801000  00     offcore_response.pf_software.mcdram memory Counts Software Prefetches that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0180601000  00     offcore_response.pf_software.mcdram_far memory Counts Software Prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x0100401000  00     offcore_response.pf_software.mcdram_near memory Counts Software Prefetches that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080201000  00     offcore_response.uc_code_reads.ddr memory Counts UC code reads (valid only for Outstanding response type)  that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0181800200  00     offcore_response.uc_code_reads.ddr_far memory Counts UC code reads (valid only for Outstanding response type)  that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=1,offcore_rsp=0x0101000200  00     offcore_response.uc_code_reads.ddr_near memory Counts UC code reads (valid only for Outstanding response type)  that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080800200  00     offcore_response.uc_code_reads.mcdram memory Counts UC code reads (valid only for Outstanding response type)  that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=1,offcore_rsp=0x0180600200  00     offcore_response.uc_code_reads.mcdram_far memory Counts UC code reads (valid only for Outstanding response type)  that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=1,offcore_rsp=0x0100400200  00     offcore_response.uc_code_reads.mcdram_near memory Counts UC code reads (valid only for Outstanding response type)  that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=1,offcore_rsp=0x0080200200  00     br_inst_retired.all_branches pipeline Counts the number of branch instructions retired (Precise Event) event=0xc4,period=200003  00     br_inst_retired.call pipeline Counts the number of near CALL branch instructions retired. (Precise Event) event=0xc4,period=200003,umask=0xf9  00     br_inst_retired.far_branch pipeline Counts the number of far branch instructions retired. (Precise Event) event=0xc4,period=200003,umask=0xbf  00     br_inst_retired.ind_call pipeline Counts the number of near indirect CALL branch instructions retired. (Precise Event) event=0xc4,period=200003,umask=0xfb  00     br_inst_retired.jcc pipeline Counts the number of branch instructions retired that were conditional jumps. (Precise Event) event=0xc4,period=200003,umask=0x7e  00     br_inst_retired.non_return_ind pipeline Counts the number of branch instructions retired that were near indirect CALL or near indirect JMP. (Precise Event) event=0xc4,period=200003,umask=0xeb  00     br_inst_retired.rel_call pipeline Counts the number of near relative CALL branch instructions retired. (Precise Event) event=0xc4,period=200003,umask=0xfd  00     br_inst_retired.return pipeline Counts the number of near RET branch instructions retired. (Precise Event) event=0xc4,period=200003,umask=0xf7  00     br_inst_retired.taken_jcc pipeline Counts the number of branch instructions retired that were conditional jumps and predicted taken. (Precise Event) event=0xc4,period=200003,umask=0xfe  00     br_misp_retired.all_branches pipeline Counts the number of mispredicted branch instructions retired (Precise Event) event=0xc5,period=200003  00     br_misp_retired.call pipeline Counts the number of mispredicted near CALL branch instructions retired. (Precise Event) event=0xc5,period=200003,umask=0xf9  00     br_misp_retired.far_branch pipeline Counts the number of mispredicted far branch instructions retired. (Precise Event) event=0xc5,period=200003,umask=0xbf  00     br_misp_retired.ind_call pipeline Counts the number of mispredicted near indirect CALL branch instructions retired. (Precise Event) event=0xc5,period=200003,umask=0xfb  00     br_misp_retired.jcc pipeline Counts the number of mispredicted branch instructions retired that were conditional jumps. (Precise Event) event=0xc5,period=200003,umask=0x7e  00     br_misp_retired.non_return_ind pipeline Counts the number of mispredicted branch instructions retired that were near indirect CALL or near indirect JMP. (Precise Event) event=0xc5,period=200003,umask=0xeb  00     br_misp_retired.rel_call pipeline Counts the number of mispredicted near relative CALL branch instructions retired. (Precise Event) event=0xc5,period=200003,umask=0xfd  00     br_misp_retired.return pipeline Counts the number of mispredicted near RET branch instructions retired. (Precise Event) event=0xc5,period=200003,umask=0xf7  00     br_misp_retired.taken_jcc pipeline Counts the number of mispredicted branch instructions retired that were conditional jumps and predicted taken. (Precise Event) event=0xc5,period=200003,umask=0xfe  00     cpu_clk_unhalted.ref pipeline Counts the number of unhalted reference clock cycles event=0x0,umask=0x03,period=2000003  00     cpu_clk_unhalted.thread pipeline Fixed Counter: Counts the number of unhalted core clock cycles event=0x3c,period=2000003  00    This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter cpu_clk_unhalted.thread_p pipeline Counts the number of unhalted core clock cycles event=0x3c,period=2000003  00     cycles_div_busy.all pipeline Cycles the number of core cycles when divider is busy.  Does not imply a stall waiting for the divider event=0xcd,period=2000003,umask=1  00    This event counts cycles when the divider is busy. More specifically cycles when the divide unit is unable to accept a new divide uop because it is busy processing a previously dispatched uop. The cycles will be counted irrespective of whether or not another divide uop is waiting to enter the divide unit (from the RS). This event counts integer divides, x87 divides, divss, divsd, sqrtss, sqrtsd event and does not count vector divides inst_retired.any pipeline Fixed Counter: Counts the number of instructions retired event=0xc0,period=2000003  00    This event counts the number of instructions that retire.  For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires.  The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps inst_retired.any_p pipeline Counts the total number of instructions retired event=0xc0,period=2000003  00     inst_retired.any_ps pipeline Counts the number of instructions retired (Precise Event) event=0xc0,period=2000003  00     machine_clears.all pipeline Counts all machine clears event=0xc3,period=200003,umask=8  00     machine_clears.smc pipeline Counts the number of times that the machine clears due to program modifying data within 1K of a recently fetched code page event=0xc3,period=200003,umask=1  00     no_alloc_cycles.all pipeline Counts the total number of core cycles when no micro-ops are allocated for any reason event=0xca,period=200003,umask=0x7f  00     no_alloc_cycles.mispredicts pipeline Counts the number of core cycles when no micro-ops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire event=0xca,period=200003,umask=4  00    This event counts the number of core cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire no_alloc_cycles.not_delivered pipeline Counts the number of core cycles when no micro-ops are allocated, the IQ is empty, and no other condition is blocking allocation event=0xca,period=200003,umask=0x90  00    This event counts the number of core cycles when no uops are allocated, the instruction queue is empty and the alloc pipe is stalled waiting for instructions to be fetched no_alloc_cycles.rat_stall pipeline Counts the number of core cycles when no micro-ops are allocated and a RATstall (caused by reservation station full) is asserted event=0xca,period=200003,umask=0x20  00     no_alloc_cycles.rob_full pipeline Counts the number of core cycles when no micro-ops are allocated and the ROB is full event=0xca,period=200003,umask=1  00     recycleq.any_ld pipeline Counts any retired load that was pushed into the recycle queue for any reason event=3,period=200003,umask=0x40  00     recycleq.any_st pipeline Counts any retired store that was pushed into the recycle queue for any reason event=3,period=200003,umask=0x80  00     recycleq.ld_block_std_notready pipeline Counts the number of occurrences a retired load gets blocked because its address overlaps with a store whose data is not ready event=3,period=200003,umask=2  00     recycleq.ld_block_st_forward pipeline Counts the number of occurrences a retired load gets blocked because its address partially overlaps with a store  (Precise Event)  Supports address when precise event=3,period=200003,umask=1  00    This event counts the number of retired loads that were prohibited from receiving forwarded data from a previous store because of address mismatch  Supports address when precise recycleq.ld_splits pipeline Counts the number of occurrences a retired load was pushed into the rehab queue because it sees a cache line split. Each split should be counted only once. (Precise Event)  Supports address when precise event=3,period=200003,umask=8  00    This event counts the number of retired loads which was pushed into the recycled queue that experienced cache line boundary splits (Precise event). Not that each split should be counted only once  Supports address when precise recycleq.lock pipeline Counts all the retired locked loads. It does not include stores because we would double count if we count stores event=3,period=200003,umask=0x10  00     recycleq.sta_full pipeline Counts the store micro-ops retired that were pushed in the rehab queue because the store address buffer is full event=3,period=200003,umask=0x20  00     recycleq.st_splits pipeline Counts the number of occurrences a retired store that is a cache line split. Each split should be counted only once event=3,period=200003,umask=4  00    This event counts the number of retired store that experienced a cache line boundary split(Precise Event). Note that each spilt should be counted only once rs_full_stall.all pipeline Counts the total number of core cycles allocation pipeline is stalled when any one of the reservation stations is full event=0xcb,period=200003,umask=0x1f  00     rs_full_stall.mec pipeline Counts the number of core cycles when allocation pipeline is stalled and is waiting for a free MEC reservation station entry event=0xcb,period=200003,umask=1  00     uops_retired.all pipeline Counts the number of micro-ops retired event=0xc2,period=2000003,umask=0x10  00    This event counts the number of micro-ops (uops) retired. The processor decodes complex macro instructions into a sequence of simpler uops. Most instructions are composed of one or two uops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists uops_retired.ms pipeline Counts the number of micro-ops retired that are from the complex flows issued by the micro-sequencer (MS) event=0xc2,period=2000003,umask=1  00    This event counts the number of micro-ops retired that were supplied from MSROM unc_c_tor_inserts.ipq_hit uncore cache Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent -IPQ event=0x35,umask=0x18  01     unc_c_tor_inserts.ipq_miss uncore cache Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent -IPQ event=0x35,umask=0x28  01     unc_c_tor_inserts.irq_hit uncore cache Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent -IRQ event=0x35,umask=0x11  01     unc_c_tor_inserts.irq_miss uncore cache Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent -IRQ event=0x35,umask=0x21  01     unc_c_tor_inserts.loc_all uncore cache Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent -IRQ or PRQ event=0x35,umask=0x37  01     unc_c_tor_inserts.prq_hit uncore cache Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent -PRQ event=0x35,umask=0x14  01     unc_c_tor_inserts.prq_miss uncore cache Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent -PRQ event=0x35,umask=0x24  01     unc_h_ag0_ad_crd_acquired.tgr0 uncore cache CMS Agent0 AD Credits Acquired For Transgress 0 event=0x80,umask=1  01     unc_h_ag0_ad_crd_acquired.tgr1 uncore cache CMS Agent0 AD Credits Acquired For Transgress 1 event=0x80,umask=2  01     unc_h_ag0_ad_crd_acquired.tgr2 uncore cache CMS Agent0 AD Credits Acquired For Transgress 2 event=0x80,umask=4  01     unc_h_ag0_ad_crd_acquired.tgr3 uncore cache CMS Agent0 AD Credits Acquired For Transgress 3 event=0x80,umask=8  01     unc_h_ag0_ad_crd_acquired.tgr4 uncore cache CMS Agent0 AD Credits Acquired For Transgress 4 event=0x80,umask=0x10  01     unc_h_ag0_ad_crd_acquired.tgr5 uncore cache CMS Agent0 AD Credits Acquired For Transgress 5 event=0x80,umask=0x20  01     unc_h_ag0_ad_crd_acquired.tgr6 uncore cache CMS Agent0 AD Credits Acquired For Transgress 6 event=0x80,umask=0x40  01     unc_h_ag0_ad_crd_acquired.tgr7 uncore cache CMS Agent0 AD Credits Acquired For Transgress 7 event=0x80,umask=0x80  01     unc_h_ag0_ad_crd_acquired_ext.any_of_tgr0_thru_tgr7 uncore cache CMS Agent0 AD Credits Acquired For Transgress 0-7 event=0x81,umask=2  01     unc_h_ag0_ad_crd_acquired_ext.tgr8 uncore cache CMS Agent0 AD Credits Acquired For Transgress 8 event=0x81,umask=1  01     unc_h_ag0_ad_crd_occupancy.tgr0 uncore cache CMS Agent0 AD Credits Occupancy For Transgress 0 event=0x82,umask=1  01     unc_h_ag0_ad_crd_occupancy.tgr1 uncore cache CMS Agent0 AD Credits Occupancy For Transgress 1 event=0x82,umask=2  01     unc_h_ag0_ad_crd_occupancy.tgr2 uncore cache CMS Agent0 AD Credits Occupancy For Transgress 2 event=0x82,umask=4  01     unc_h_ag0_ad_crd_occupancy.tgr3 uncore cache CMS Agent0 AD Credits Occupancy For Transgress 3 event=0x82,umask=8  01     unc_h_ag0_ad_crd_occupancy.tgr4 uncore cache CMS Agent0 AD Credits Occupancy For Transgress 4 event=0x82,umask=0x10  01     unc_h_ag0_ad_crd_occupancy.tgr5 uncore cache CMS Agent0 AD Credits Occupancy For Transgress 5 event=0x82,umask=0x20  01     unc_h_ag0_ad_crd_occupancy.tgr6 uncore cache CMS Agent0 AD Credits Occupancy For Transgress 6 event=0x82,umask=0x40  01     unc_h_ag0_ad_crd_occupancy.tgr7 uncore cache CMS Agent0 AD Credits Occupancy For Transgress 7 event=0x82,umask=0x80  01     unc_h_ag0_ad_crd_occupancy_ext.any_of_tgr0_thru_tgr7 uncore cache CMS Agent0 AD Credits Occupancy For Transgress 0-7 event=0x83,umask=2  01     unc_h_ag0_ad_crd_occupancy_ext.tgr8 uncore cache CMS Agent0 AD Credits Occupancy For Transgress 8 event=0x83,umask=1  01     unc_h_ag0_bl_crd_acquired.tgr0 uncore cache CMS Agent0 BL Credits Acquired For Transgress 0 event=0x88,umask=1  01     unc_h_ag0_bl_crd_acquired.tgr1 uncore cache CMS Agent0 BL Credits Acquired For Transgress 1 event=0x88,umask=2  01     unc_h_ag0_bl_crd_acquired.tgr2 uncore cache CMS Agent0 BL Credits Acquired For Transgress 2 event=0x88,umask=4  01     unc_h_ag0_bl_crd_acquired.tgr3 uncore cache CMS Agent0 BL Credits Acquired For Transgress 3 event=0x88,umask=8  01     unc_h_ag0_bl_crd_acquired.tgr4 uncore cache CMS Agent0 BL Credits Acquired For Transgress 4 event=0x88,umask=0x10  01     unc_h_ag0_bl_crd_acquired.tgr5 uncore cache CMS Agent0 BL Credits Acquired For Transgress 5 event=0x88,umask=0x20  01     unc_h_ag0_bl_crd_acquired.tgr6 uncore cache CMS Agent0 BL Credits Acquired For Transgress 6 event=0x88,umask=0x40  01     unc_h_ag0_bl_crd_acquired.tgr7 uncore cache CMS Agent0 BL Credits Acquired For Transgress 7 event=0x88,umask=0x80  01     unc_h_ag0_bl_crd_acquired_ext.any_of_tgr0_thru_tgr7 uncore cache CMS Agent0 BL Credits Acquired For Transgress 0-7 event=0x89,umask=2  01     unc_h_ag0_bl_crd_acquired_ext.tgr8 uncore cache CMS Agent0 BL Credits Acquired For Transgress 8 event=0x89,umask=1  01     unc_h_ag0_bl_crd_occupancy.tgr0 uncore cache CMS Agent0 BL Credits Occupancy For Transgress 0 event=0x8a,umask=1  01     unc_h_ag0_bl_crd_occupancy.tgr1 uncore cache CMS Agent0 BL Credits Occupancy For Transgress 1 event=0x8a,umask=2  01     unc_h_ag0_bl_crd_occupancy.tgr2 uncore cache CMS Agent0 BL Credits Occupancy For Transgress 2 event=0x8a,umask=4  01     unc_h_ag0_bl_crd_occupancy.tgr3 uncore cache CMS Agent0 BL Credits Occupancy For Transgress 3 event=0x8a,umask=8  01     unc_h_ag0_bl_crd_occupancy.tgr4 uncore cache CMS Agent0 BL Credits Occupancy For Transgress 4 event=0x8a,umask=0x10  01     unc_h_ag0_bl_crd_occupancy.tgr5 uncore cache CMS Agent0 BL Credits Occupancy For Transgress 5 event=0x8a,umask=0x20  01     unc_h_ag0_bl_crd_occupancy.tgr6 uncore cache CMS Agent0 BL Credits Occupancy For Transgress 6 event=0x8a,umask=0x40  01     unc_h_ag0_bl_crd_occupancy.tgr7 uncore cache CMS Agent0 BL Credits Occupancy For Transgress 7 event=0x8a,umask=0x80  01     unc_h_ag0_bl_crd_occupancy_ext.any_of_tgr0_thru_tgr7 uncore cache CMS Agent0 BL Credits Occupancy For Transgress 0-7 event=0x8b,umask=2  01     unc_h_ag0_bl_crd_occupancy_ext.tgr8 uncore cache CMS Agent0 BL Credits Occupancy For Transgress 8 event=0x8b,umask=1  01     unc_h_ag0_stall_no_crd_egress_horz_ad.tgr0 uncore cache Stall on No AD Transgress Credits For Transgress 0 event=0xd0,umask=1  01     unc_h_ag0_stall_no_crd_egress_horz_ad.tgr1 uncore cache Stall on No AD Transgress Credits For Transgress 1 event=0xd0,umask=2  01     unc_h_ag0_stall_no_crd_egress_horz_ad.tgr2 uncore cache Stall on No AD Transgress Credits For Transgress 2 event=0xd0,umask=4  01     unc_h_ag0_stall_no_crd_egress_horz_ad.tgr3 uncore cache Stall on No AD Transgress Credits For Transgress 3 event=0xd0,umask=8  01     unc_h_ag0_stall_no_crd_egress_horz_ad.tgr4 uncore cache Stall on No AD Transgress Credits For Transgress 4 event=0xd0,umask=0x10  01     unc_h_ag0_stall_no_crd_egress_horz_ad.tgr5 uncore cache Stall on No AD Transgress Credits For Transgress 5 event=0xd0,umask=0x20  01     unc_h_ag0_stall_no_crd_egress_horz_ad.tgr6 uncore cache Stall on No AD Transgress Credits For Transgress 6 event=0xd0,umask=0x40  01     unc_h_ag0_stall_no_crd_egress_horz_ad.tgr7 uncore cache Stall on No AD Transgress Credits For Transgress 7 event=0xd0,umask=0x80  01     unc_h_ag0_stall_no_crd_egress_horz_ad_ext.any_of_tgr0_thru_tgr7 uncore cache Stall on No AD Transgress Credits For Transgress 0-7 event=0xd1,umask=2  01     unc_h_ag0_stall_no_crd_egress_horz_ad_ext.tgr8 uncore cache Stall on No AD Transgress Credits For Transgress 8 event=0xd1,umask=1  01     unc_h_ag0_stall_no_crd_egress_horz_bl.tgr0 uncore cache Stall on No AD Transgress Credits For Transgress 0 event=0xd4,umask=1  01     unc_h_ag0_stall_no_crd_egress_horz_bl.tgr1 uncore cache Stall on No AD Transgress Credits For Transgress 1 event=0xd4,umask=2  01     unc_h_ag0_stall_no_crd_egress_horz_bl.tgr2 uncore cache Stall on No AD Transgress Credits For Transgress 2 event=0xd4,umask=4  01     unc_h_ag0_stall_no_crd_egress_horz_bl.tgr3 uncore cache Stall on No AD Transgress Credits For Transgress 3 event=0xd4,umask=8  01     unc_h_ag0_stall_no_crd_egress_horz_bl.tgr4 uncore cache Stall on No AD Transgress Credits For Transgress 4 event=0xd4,umask=0x10  01     unc_h_ag0_stall_no_crd_egress_horz_bl.tgr5 uncore cache Stall on No AD Transgress Credits For Transgress 5 event=0xd4,umask=0x20  01     unc_h_ag0_stall_no_crd_egress_horz_bl.tgr6 uncore cache Stall on No AD Transgress Credits For Transgress 6 event=0xd4,umask=0x40  01     unc_h_ag0_stall_no_crd_egress_horz_bl.tgr7 uncore cache Stall on No AD Transgress Credits For Transgress 7 event=0xd4,umask=0x80  01     unc_h_ag0_stall_no_crd_egress_horz_bl_ext.any_of_tgr0_thru_tgr7 uncore cache Stall on No AD Transgress Credits For Transgress 0-7 event=0xd5,umask=2  01     unc_h_ag0_stall_no_crd_egress_horz_bl_ext.tgr8 uncore cache Stall on No AD Transgress Credits For Transgress 8 event=0xd5,umask=1  01     unc_h_ag1_ad_crd_acquired.tgr0 uncore cache CMS Agent1 AD Credits Acquired For Transgress 0 event=0x84,umask=1  01     unc_h_ag1_ad_crd_acquired.tgr1 uncore cache CMS Agent1 AD Credits Acquired For Transgress 1 event=0x84,umask=2  01     unc_h_ag1_ad_crd_acquired.tgr2 uncore cache CMS Agent1 AD Credits Acquired For Transgress 2 event=0x84,umask=4  01     unc_h_ag1_ad_crd_acquired.tgr3 uncore cache CMS Agent1 AD Credits Acquired For Transgress 3 event=0x84,umask=8  01     unc_h_ag1_ad_crd_acquired.tgr4 uncore cache CMS Agent1 AD Credits Acquired For Transgress 4 event=0x84,umask=0x10  01     unc_h_ag1_ad_crd_acquired.tgr5 uncore cache CMS Agent1 AD Credits Acquired For Transgress 5 event=0x84,umask=0x20  01     unc_h_ag1_ad_crd_acquired.tgr6 uncore cache CMS Agent1 AD Credits Acquired For Transgress 6 event=0x84,umask=0x40  01     unc_h_ag1_ad_crd_acquired.tgr7 uncore cache CMS Agent1 AD Credits Acquired For Transgress 7 event=0x84,umask=0x80  01     unc_h_ag1_ad_crd_acquired_ext.any_of_tgr0_thru_tgr7 uncore cache CMS Agent1 AD Credits Acquired For Transgress 0-7 event=0x85,umask=2  01     unc_h_ag1_ad_crd_acquired_ext.tgr8 uncore cache CMS Agent1 AD Credits Acquired For Transgress 8 event=0x85,umask=1  01     unc_h_ag1_ad_crd_occupancy.tgr0 uncore cache CMS Agent1 AD Credits Occupancy For Transgress 0 event=0x86,umask=1  01     unc_h_ag1_ad_crd_occupancy.tgr1 uncore cache CMS Agent1 AD Credits Occupancy For Transgress 1 event=0x86,umask=2  01     unc_h_ag1_ad_crd_occupancy.tgr2 uncore cache CMS Agent1 AD Credits Occupancy For Transgress 2 event=0x86,umask=4  01     unc_h_ag1_ad_crd_occupancy.tgr3 uncore cache CMS Agent1 AD Credits Occupancy For Transgress 3 event=0x86,umask=8  01     unc_h_ag1_ad_crd_occupancy.tgr4 uncore cache CMS Agent1 AD Credits Occupancy For Transgress 4 event=0x86,umask=0x10  01     unc_h_ag1_ad_crd_occupancy.tgr5 uncore cache CMS Agent1 AD Credits Occupancy For Transgress 5 event=0x86,umask=0x20  01     unc_h_ag1_ad_crd_occupancy.tgr6 uncore cache CMS Agent1 AD Credits Occupancy For Transgress 6 event=0x86,umask=0x40  01     unc_h_ag1_ad_crd_occupancy.tgr7 uncore cache CMS Agent1 AD Credits Occupancy For Transgress 7 event=0x86,umask=0x80  01     unc_h_ag1_ad_crd_occupancy_ext.any_of_tgr0_thru_tgr7 uncore cache CMS Agent1 AD Credits Occupancy For Transgress 0-7 event=0x87,umask=2  01     unc_h_ag1_ad_crd_occupancy_ext.tgr8 uncore cache CMS Agent1 AD Credits Occupancy For Transgress 8 event=0x87,umask=1  01     unc_h_ag1_bl_crd_acquired.tgr0 uncore cache CMS Agent1 BL Credits Acquired For Transgress 0 event=0x8c,umask=1  01     unc_h_ag1_bl_crd_acquired.tgr1 uncore cache CMS Agent1 BL Credits Acquired For Transgress 1 event=0x8c,umask=2  01     unc_h_ag1_bl_crd_acquired.tgr2 uncore cache CMS Agent1 BL Credits Acquired For Transgress 2 event=0x8c,umask=4  01     unc_h_ag1_bl_crd_acquired.tgr3 uncore cache CMS Agent1 BL Credits Acquired For Transgress 3 event=0x8c,umask=8  01     unc_h_ag1_bl_crd_acquired.tgr4 uncore cache CMS Agent1 BL Credits Acquired For Transgress 4 event=0x8c,umask=0x10  01     unc_h_ag1_bl_crd_acquired.tgr5 uncore cache CMS Agent1 BL Credits Acquired For Transgress 5 event=0x8c,umask=0x20  01     unc_h_ag1_bl_crd_acquired.tgr6 uncore cache CMS Agent1 BL Credits Acquired For Transgress 6 event=0x8c,umask=0x40  01     unc_h_ag1_bl_crd_acquired.tgr7 uncore cache CMS Agent1 BL Credits Acquired For Transgress 7 event=0x8c,umask=0x80  01     unc_h_ag1_bl_crd_acquired_ext.any_of_tgr0_thru_tgr7 uncore cache CMS Agent1 BL Credits Acquired For Transgress 0-7 event=0x8d,umask=2  01     unc_h_ag1_bl_crd_acquired_ext.tgr8 uncore cache CMS Agent1 BL Credits Acquired For Transgress 8 event=0x8d,umask=1  01     unc_h_ag1_bl_crd_occupancy.tgr0 uncore cache CMS Agent1 BL Credits Occupancy For Transgress 0 event=0x8e,umask=1  01     unc_h_ag1_bl_crd_occupancy.tgr1 uncore cache CMS Agent1 BL Credits Occupancy For Transgress 1 event=0x8e,umask=2  01     unc_h_ag1_bl_crd_occupancy.tgr2 uncore cache CMS Agent1 BL Credits Occupancy For Transgress 2 event=0x8e,umask=4  01     unc_h_ag1_bl_crd_occupancy.tgr3 uncore cache CMS Agent1 BL Credits Occupancy For Transgress 3 event=0x8e,umask=8  01     unc_h_ag1_bl_crd_occupancy.tgr4 uncore cache CMS Agent1 BL Credits Occupancy For Transgress 4 event=0x8e,umask=0x10  01     unc_h_ag1_bl_crd_occupancy.tgr5 uncore cache CMS Agent1 BL Credits Occupancy For Transgress 5 event=0x8e,umask=0x20  01     unc_h_ag1_bl_crd_occupancy.tgr6 uncore cache CMS Agent1 BL Credits Occupancy For Transgress 6 event=0x8e,umask=0x40  01     unc_h_ag1_bl_crd_occupancy.tgr7 uncore cache CMS Agent1 BL Credits Occupancy For Transgress 7 event=0x8e,umask=0x80  01     unc_h_ag1_bl_crd_occupancy_ext.any_of_tgr0_thru_tgr7 uncore cache CMS Agent1 BL Credits Occupancy For Transgress 0-7 event=0x8f,umask=2  01     unc_h_ag1_bl_crd_occupancy_ext.tgr8 uncore cache CMS Agent1 BL Credits Occupancy For Transgress 8 event=0x8f,umask=1  01     unc_h_ag1_stall_no_crd_egress_horz_ad.tgr0 uncore cache Stall on No AD Transgress Credits For Transgress 0 event=0xd2,umask=1  01     unc_h_ag1_stall_no_crd_egress_horz_ad.tgr1 uncore cache Stall on No AD Transgress Credits For Transgress 1 event=0xd2,umask=2  01     unc_h_ag1_stall_no_crd_egress_horz_ad.tgr2 uncore cache Stall on No AD Transgress Credits For Transgress 2 event=0xd2,umask=4  01     unc_h_ag1_stall_no_crd_egress_horz_ad.tgr3 uncore cache Stall on No AD Transgress Credits For Transgress 3 event=0xd2,umask=8  01     unc_h_ag1_stall_no_crd_egress_horz_ad.tgr4 uncore cache Stall on No AD Transgress Credits For Transgress 4 event=0xd2,umask=0x10  01     unc_h_ag1_stall_no_crd_egress_horz_ad.tgr5 uncore cache Stall on No AD Transgress Credits For Transgress 5 event=0xd2,umask=0x20  01     unc_h_ag1_stall_no_crd_egress_horz_ad.tgr6 uncore cache Stall on No AD Transgress Credits For Transgress 6 event=0xd2,umask=0x40  01     unc_h_ag1_stall_no_crd_egress_horz_ad.tgr7 uncore cache Stall on No AD Transgress Credits For Transgress 7 event=0xd2,umask=0x80  01     unc_h_ag1_stall_no_crd_egress_horz_ad_ext.any_of_tgr0_thru_tgr7 uncore cache Stall on No AD Transgress Credits For Transgress 0-7 event=0xd3,umask=2  01     unc_h_ag1_stall_no_crd_egress_horz_ad_ext.tgr8 uncore cache Stall on No AD Transgress Credits For Transgress 8 event=0xd3,umask=1  01     unc_h_ag1_stall_no_crd_egress_horz_bl.tgr0 uncore cache Stall on No AD Transgress Credits For Transgress 0 event=0xd6,umask=1  01     unc_h_ag1_stall_no_crd_egress_horz_bl.tgr1 uncore cache Stall on No AD Transgress Credits For Transgress 1 event=0xd6,umask=2  01     unc_h_ag1_stall_no_crd_egress_horz_bl.tgr2 uncore cache Stall on No AD Transgress Credits For Transgress 2 event=0xd6,umask=4  01     unc_h_ag1_stall_no_crd_egress_horz_bl.tgr3 uncore cache Stall on No AD Transgress Credits For Transgress 3 event=0xd6,umask=8  01     unc_h_ag1_stall_no_crd_egress_horz_bl.tgr4 uncore cache Stall on No AD Transgress Credits For Transgress 4 event=0xd6,umask=0x10  01     unc_h_ag1_stall_no_crd_egress_horz_bl.tgr5 uncore cache Stall on No AD Transgress Credits For Transgress 5 event=0xd6,umask=0x20  01     unc_h_ag1_stall_no_crd_egress_horz_bl.tgr6 uncore cache Stall on No AD Transgress Credits For Transgress 6 event=0xd6,umask=0x40  01     unc_h_ag1_stall_no_crd_egress_horz_bl.tgr7 uncore cache Stall on No AD Transgress Credits For Transgress 7 event=0xd6,umask=0x80  01     unc_h_ag1_stall_no_crd_egress_horz_bl_ext.any_of_tgr0_thru_tgr7 uncore cache Stall on No AD Transgress Credits For Transgress 0-7 event=0xd7,umask=2  01     unc_h_ag1_stall_no_crd_egress_horz_bl_ext.tgr8 uncore cache Stall on No AD Transgress Credits For Transgress 8 event=0xd7,umask=1  01     unc_h_cache_lines_victimized.e_state uncore cache Cache Lookups. Counts the number of times the LLC was accessed. Writeback transactions from L2 to the LLC  This includes all write transactions -- both Cacheable and UC event=0x37,umask=2  01     unc_h_cache_lines_victimized.f_state uncore cache Cache Lookups. Counts the number of times the LLC was accessed. Filters for any transaction originating from the IPQ or IRQ.  This does not include lookups originating from the ISMQ event=0x37,umask=8  01     unc_h_cache_lines_victimized.local uncore cache Lines Victimized that Match NID event=0x37,umask=0x20  01     unc_h_cache_lines_victimized.m_state uncore cache Cache Lookups. Counts the number of times the LLC was accessed. Read transactions event=0x37,umask=1  01     unc_h_cache_lines_victimized.remote uncore cache Lines Victimized that Does Not Match NID event=0x37,umask=0x80  01     unc_h_cache_lines_victimized.s_state uncore cache Cache Lookups. Counts the number of times the LLC was accessed. Filters for only snoop requests coming from the remote socket(s) through the IPQ event=0x37,umask=4  01     unc_h_clock uncore cache Uncore Clocks event=0xc0  01     unc_h_egress_horz_ads_used.ad uncore cache CMS Horizontal ADS Used event=0x9d,umask=1  01     unc_h_egress_horz_ads_used.ak uncore cache CMS Horizontal ADS Used event=0x9d,umask=2  01     unc_h_egress_horz_ads_used.bl uncore cache CMS Horizontal ADS Used event=0x9d,umask=4  01     unc_h_egress_horz_bypass.ad uncore cache CMS Horizontal Egress Bypass. AD ring event=0x9f,umask=1  01     unc_h_egress_horz_bypass.ak uncore cache CMS Horizontal Egress Bypass. AK ring event=0x9f,umask=2  01     unc_h_egress_horz_bypass.bl uncore cache CMS Horizontal Egress Bypass. BL ring event=0x9f,umask=4  01     unc_h_egress_horz_bypass.iv uncore cache CMS Horizontal Egress Bypass. IV ring event=0x9f,umask=8  01     unc_h_egress_horz_cycles_full.ad uncore cache Cycles CMS Horizontal Egress Queue is Full AD event=0x96,umask=1  01     unc_h_egress_horz_cycles_full.ak uncore cache Cycles CMS Horizontal Egress Queue is Full AK event=0x96,umask=2  01     unc_h_egress_horz_cycles_full.bl uncore cache Cycles CMS Horizontal Egress Queue is Full BL event=0x96,umask=4  01     unc_h_egress_horz_cycles_full.iv uncore cache Cycles CMS Horizontal Egress Queue is Full IV event=0x96,umask=8  01     unc_h_egress_horz_cycles_ne.ad uncore cache Cycles CMS Horizontal Egress Queue is Not Empty AD event=0x97,umask=1  01     unc_h_egress_horz_cycles_ne.ak uncore cache Cycles CMS Horizontal Egress Queue is Not Empty AK event=0x97,umask=2  01     unc_h_egress_horz_cycles_ne.bl uncore cache Cycles CMS Horizontal Egress Queue is Not Empty BL event=0x97,umask=4  01     unc_h_egress_horz_cycles_ne.iv uncore cache Cycles CMS Horizontal Egress Queue is Not Empty IV event=0x97,umask=8  01     unc_h_egress_horz_inserts.ad uncore cache CMS Horizontal Egress Inserts AD event=0x95,umask=1  01     unc_h_egress_horz_inserts.ak uncore cache CMS Horizontal Egress Inserts AK event=0x95,umask=2  01     unc_h_egress_horz_inserts.bl uncore cache CMS Horizontal Egress Inserts BL event=0x95,umask=4  01     unc_h_egress_horz_inserts.iv uncore cache CMS Horizontal Egress Inserts IV event=0x95,umask=8  01     unc_h_egress_horz_nack.ad uncore cache CMS Horizontal Egress NACKs event=0x99,umask=1  01     unc_h_egress_horz_nack.ak uncore cache CMS Horizontal Egress NACKs event=0x99,umask=2  01     unc_h_egress_horz_nack.bl uncore cache CMS Horizontal Egress NACKs event=0x99,umask=4  01     unc_h_egress_horz_nack.iv uncore cache CMS Horizontal Egress NACKs event=0x99,umask=8  01     unc_h_egress_horz_occupancy.ad uncore cache CMS Horizontal Egress Occupancy AD event=0x94,umask=1  01     unc_h_egress_horz_occupancy.ak uncore cache CMS Horizontal Egress Occupancy AK event=0x94,umask=2  01     unc_h_egress_horz_occupancy.bl uncore cache CMS Horizontal Egress Occupancy BL event=0x94,umask=4  01     unc_h_egress_horz_occupancy.iv uncore cache CMS Horizontal Egress Occupancy IV event=0x94,umask=8  01     unc_h_egress_horz_starved.ad uncore cache CMS Horizontal Egress Injection Starvation event=0x9b,umask=1  01     unc_h_egress_horz_starved.ak uncore cache CMS Horizontal Egress Injection Starvation event=0x9b,umask=2  01     unc_h_egress_horz_starved.bl uncore cache CMS Horizontal Egress Injection Starvation event=0x9b,umask=4  01     unc_h_egress_horz_starved.iv uncore cache CMS Horizontal Egress Injection Starvation event=0x9b,umask=8  01     unc_h_egress_ordering.iv_snp_go_dn uncore cache Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements event=0xae,umask=4  01     unc_h_egress_ordering.iv_snp_go_up uncore cache Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements event=0xae,umask=1  01     unc_h_egress_vert_ads_used.ad_ag0 uncore cache CMS Vertical ADS Used event=0x9c,umask=1  01     unc_h_egress_vert_ads_used.ad_ag1 uncore cache CMS Vertical ADS Used event=0x9c,umask=0x10  01     unc_h_egress_vert_ads_used.ak_ag0 uncore cache CMS Vertical ADS Used event=0x9c,umask=2  01     unc_h_egress_vert_ads_used.ak_ag1 uncore cache CMS Vertical ADS Used event=0x9c,umask=0x20  01     unc_h_egress_vert_ads_used.bl_ag0 uncore cache CMS Vertical ADS Used event=0x9c,umask=4  01     unc_h_egress_vert_ads_used.bl_ag1 uncore cache CMS Vertical ADS Used event=0x9c,umask=0x40  01     unc_h_egress_vert_bypass.ad_ag0 uncore cache CMS Vertical Egress Bypass. AD ring agent 0 event=0x9e,umask=1  01     unc_h_egress_vert_bypass.ad_ag1 uncore cache CMS Vertical Egress Bypass. AD ring agent 1 event=0x9e,umask=0x10  01     unc_h_egress_vert_bypass.ak_ag0 uncore cache CMS Vertical Egress Bypass. AK ring agent 0 event=0x9e,umask=2  01     unc_h_egress_vert_bypass.ak_ag1 uncore cache CMS Vertical Egress Bypass. AK ring agent 1 event=0x9e,umask=0x20  01     unc_h_egress_vert_bypass.bl_ag0 uncore cache CMS Vertical Egress Bypass. BL ring agent 0 event=0x9e,umask=4  01     unc_h_egress_vert_bypass.bl_ag1 uncore cache CMS Vertical Egress Bypass. BL ring agent 1 event=0x9e,umask=0x40  01     unc_h_egress_vert_bypass.iv uncore cache CMS Vertical Egress Bypass. IV ring agent 0 event=0x9e,umask=8  01     unc_h_egress_vert_cycles_full.ad_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full AD - Agent 0 event=0x92,umask=1  01     unc_h_egress_vert_cycles_full.ad_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Full AD - Agent 1 event=0x92,umask=0x10  01     unc_h_egress_vert_cycles_full.ak_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full AK - Agent 0 event=0x92,umask=2  01     unc_h_egress_vert_cycles_full.ak_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Full AK - Agent 1 event=0x92,umask=0x20  01     unc_h_egress_vert_cycles_full.bl_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full BL - Agent 0 event=0x92,umask=4  01     unc_h_egress_vert_cycles_full.bl_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Full BL - Agent 1 event=0x92,umask=0x40  01     unc_h_egress_vert_cycles_full.iv_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Full IV - Agent 0 event=0x92,umask=8  01     unc_h_egress_vert_cycles_ne.ad_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty AD - Agent 0 event=0x93,umask=1  01     unc_h_egress_vert_cycles_ne.ad_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty AD - Agent 1 event=0x93,umask=0x10  01     unc_h_egress_vert_cycles_ne.ak_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty AK - Agent 0 event=0x93,umask=2  01     unc_h_egress_vert_cycles_ne.ak_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty AK - Agent 1 event=0x93,umask=0x20  01     unc_h_egress_vert_cycles_ne.bl_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty BL - Agent 0 event=0x93,umask=4  01     unc_h_egress_vert_cycles_ne.bl_ag1 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty BL - Agent 1 event=0x93,umask=0x40  01     unc_h_egress_vert_cycles_ne.iv_ag0 uncore cache Cycles CMS Vertical Egress Queue Is Not Empty IV - Agent 0 event=0x93,umask=8  01     unc_h_egress_vert_inserts.ad_ag0 uncore cache CMS Vert Egress Allocations AD - Agent 0 event=0x91,umask=1  01     unc_h_egress_vert_inserts.ad_ag1 uncore cache CMS Vert Egress Allocations AD - Agent 1 event=0x91,umask=0x10  01     unc_h_egress_vert_inserts.ak_ag0 uncore cache CMS Vert Egress Allocations AK - Agent 0 event=0x91,umask=2  01     unc_h_egress_vert_inserts.ak_ag1 uncore cache CMS Vert Egress Allocations AK - Agent 1 event=0x91,umask=0x20  01     unc_h_egress_vert_inserts.bl_ag0 uncore cache CMS Vert Egress Allocations BL - Agent 0 event=0x91,umask=4  01     unc_h_egress_vert_inserts.bl_ag1 uncore cache CMS Vert Egress Allocations BL - Agent 1 event=0x91,umask=0x40  01     unc_h_egress_vert_inserts.iv_ag0 uncore cache CMS Vert Egress Allocations IV - Agent 0 event=0x91,umask=8  01     unc_h_egress_vert_nack.ad_ag0 uncore cache CMS Vertical Egress NACKs event=0x98,umask=1  01     unc_h_egress_vert_nack.ad_ag1 uncore cache CMS Vertical Egress NACKs event=0x98,umask=0x10  01     unc_h_egress_vert_nack.ak_ag0 uncore cache CMS Vertical Egress NACKs Onto AK Ring event=0x98,umask=2  01     unc_h_egress_vert_nack.ak_ag1 uncore cache CMS Vertical Egress NACKs event=0x98,umask=0x20  01     unc_h_egress_vert_nack.bl_ag0 uncore cache CMS Vertical Egress NACKs Onto BL Ring event=0x98,umask=4  01     unc_h_egress_vert_nack.bl_ag1 uncore cache CMS Vertical Egress NACKs event=0x98,umask=0x40  01     unc_h_egress_vert_nack.iv_ag0 uncore cache CMS Vertical Egress NACKs event=0x98,umask=8  01     unc_h_egress_vert_occupancy.ad_ag0 uncore cache CMS Vert Egress Occupancy AD - Agent 0 event=0x90,umask=1  01     unc_h_egress_vert_occupancy.ad_ag1 uncore cache CMS Vert Egress Occupancy AD - Agent 1 event=0x90,umask=0x10  01     unc_h_egress_vert_occupancy.ak_ag0 uncore cache CMS Vert Egress Occupancy AK - Agent 0 event=0x90,umask=2  01     unc_h_egress_vert_occupancy.ak_ag1 uncore cache CMS Vert Egress Occupancy AK - Agent 1 event=0x90,umask=0x20  01     unc_h_egress_vert_occupancy.bl_ag0 uncore cache CMS Vert Egress Occupancy BL - Agent 0 event=0x90,umask=4  01     unc_h_egress_vert_occupancy.bl_ag1 uncore cache CMS Vert Egress Occupancy BL - Agent 1 event=0x90,umask=0x40  01     unc_h_egress_vert_occupancy.iv_ag0 uncore cache CMS Vert Egress Occupancy IV - Agent 0 event=0x90,umask=8  01     unc_h_egress_vert_starved.ad_ag0 uncore cache CMS Vertical Egress Injection Starvation event=0x9a,umask=1  01     unc_h_egress_vert_starved.ad_ag1 uncore cache CMS Vertical Egress Injection Starvation event=0x9a,umask=0x10  01     unc_h_egress_vert_starved.ak_ag0 uncore cache CMS Vertical Egress Injection Starvation Onto AK Ring event=0x9a,umask=2  01     unc_h_egress_vert_starved.ak_ag1 uncore cache CMS Vertical Egress Injection Starvation event=0x9a,umask=0x20  01     unc_h_egress_vert_starved.bl_ag0 uncore cache CMS Vertical Egress Injection Starvation Onto BL Ring event=0x9a,umask=4  01     unc_h_egress_vert_starved.bl_ag1 uncore cache CMS Vertical Egress Injection Starvation event=0x9a,umask=0x40  01     unc_h_egress_vert_starved.iv_ag0 uncore cache CMS Vertical Egress Injection Starvation event=0x9a,umask=8  01     unc_h_fast_asserted.horz uncore cache Counts cycles source throttling is asserted - horizontal event=0xa5,umask=1  01     unc_h_fast_asserted.vert uncore cache Counts cycles source throttling is asserted - vertical event=0xa5  01     unc_h_horz_ring_ad_in_use.left_even uncore cache Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Left and Even event=0xa7,umask=1  01     unc_h_horz_ring_ad_in_use.left_odd uncore cache Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Left and Odd event=0xa7,umask=2  01     unc_h_horz_ring_ad_in_use.right_even uncore cache Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Right and Even event=0xa7,umask=4  01     unc_h_horz_ring_ad_in_use.right_odd uncore cache Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Right and Odd event=0xa7,umask=8  01     unc_h_horz_ring_ak_in_use.left_even uncore cache Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Left and Even event=0xa9,umask=1  01     unc_h_horz_ring_ak_in_use.left_odd uncore cache Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Left and Odd event=0xa9,umask=2  01     unc_h_horz_ring_ak_in_use.right_even uncore cache Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Right and Even event=0xa9,umask=4  01     unc_h_horz_ring_ak_in_use.right_odd uncore cache Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Right and Odd event=0xa9,umask=8  01     unc_h_horz_ring_bl_in_use.left_even uncore cache Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Left and Even event=0xab,umask=1  01     unc_h_horz_ring_bl_in_use.left_odd uncore cache Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Left and Odd event=0xab,umask=2  01     unc_h_horz_ring_bl_in_use.right_even uncore cache Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Right and Even event=0xab,umask=4  01     unc_h_horz_ring_bl_in_use.right_odd uncore cache Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Right and Odd event=0xab,umask=8  01     unc_h_horz_ring_iv_in_use.left uncore cache Counts the number of cycles that the Horizontal IV ring is being used at this ring stop - Left event=0xad,umask=1  01     unc_h_horz_ring_iv_in_use.right uncore cache Counts the number of cycles that the Horizontal IV ring is being used at this ring stop - Right event=0xad,umask=4  01     unc_h_ingress_inserts.ipq uncore cache Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - IPQ event=0x13,umask=4  01     unc_h_ingress_inserts.irq uncore cache Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - IRQ event=0x13,umask=1  01     unc_h_ingress_inserts.irq_rej uncore cache Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - IRQ Rejected event=0x13,umask=2  01     unc_h_ingress_inserts.prq uncore cache Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - PRQ event=0x13,umask=0x10  01     unc_h_ingress_inserts.prq_rej uncore cache Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - PRQ Rejected event=0x13,umask=0x20  01     unc_h_ingress_int_starved.ipq uncore cache Cycles with the IPQ in Internal Starvation event=0x14,umask=4  01     unc_h_ingress_int_starved.irq uncore cache Cycles with the IRQ in Internal Starvation event=0x14,umask=1  01     unc_h_ingress_int_starved.ismq uncore cache Cycles with the ISMQ in Internal Starvation event=0x14,umask=8  01     unc_h_ingress_int_starved.prq uncore cache Ingress internal starvation cycles. Counts cycles in internal starvation. This occurs when one or more of the entries in the ingress queue are being starved out by other entries in the queue event=0x14,umask=0x10  01     unc_h_ingress_occupancy.ipq uncore cache Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycle. - IPQ event=0x11,umask=4  01     unc_h_ingress_occupancy.irq uncore cache Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycle. - IRQ event=0x11,umask=1  01     unc_h_ingress_occupancy.irq_rej uncore cache Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycle. - IRQ Rejected event=0x11,umask=2  01     unc_h_ingress_occupancy.prq uncore cache Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycle. - PRQ event=0x11,umask=0x10  01     unc_h_ingress_occupancy.prq_rej uncore cache Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycle. - PRQ Rejected event=0x11,umask=0x20  01     unc_h_ingress_retry_ipq0_reject.ad_req_vn0 uncore cache Ingress Probe Queue Rejects event=0x22,umask=1  01     unc_h_ingress_retry_ipq0_reject.ad_rsp_vn0 uncore cache Ingress Probe Queue Rejects event=0x22,umask=2  01     unc_h_ingress_retry_ipq0_reject.ak_non_upi uncore cache Ingress Probe Queue Rejects event=0x22,umask=0x40  01     unc_h_ingress_retry_ipq0_reject.bl_ncb_vn0 uncore cache Ingress Probe Queue Rejects event=0x22,umask=0x10  01     unc_h_ingress_retry_ipq0_reject.bl_ncs_vn0 uncore cache Ingress Probe Queue Rejects event=0x22,umask=0x20  01     unc_h_ingress_retry_ipq0_reject.bl_rsp_vn0 uncore cache Ingress Probe Queue Rejects event=0x22,umask=4  01     unc_h_ingress_retry_ipq0_reject.bl_wb_vn0 uncore cache Ingress Probe Queue Rejects event=0x22,umask=8  01     unc_h_ingress_retry_ipq0_reject.iv_non_upi uncore cache Ingress Probe Queue Rejects event=0x22,umask=0x80  01     unc_h_ingress_retry_ipq1_reject.allow_snp uncore cache Ingress Probe Queue Rejects event=0x23,umask=0x40  01     unc_h_ingress_retry_ipq1_reject.any_reject_ipq0 uncore cache Ingress Probe Queue Rejects event=0x23,umask=1  01     unc_h_ingress_retry_ipq1_reject.pa_match uncore cache Ingress Probe Queue Rejects event=0x23,umask=0x80  01     unc_h_ingress_retry_ipq1_reject.sf_victim uncore cache Ingress Probe Queue Rejects event=0x23,umask=8  01     unc_h_ingress_retry_ipq1_reject.sf_way uncore cache Ingress Probe Queue Rejects event=0x23,umask=0x20  01     unc_h_ingress_retry_irq0_reject.ad_req_vn0 uncore cache Ingress Request Queue Rejects event=0x18,umask=1  01     unc_h_ingress_retry_irq0_reject.ad_rsp_vn0 uncore cache Ingress Request Queue Rejects event=0x18,umask=2  01     unc_h_ingress_retry_irq0_reject.ak_non_upi uncore cache Ingress Request Queue Rejects event=0x18,umask=0x40  01     unc_h_ingress_retry_irq0_reject.bl_ncb_vn0 uncore cache Ingress Request Queue Rejects event=0x18,umask=0x10  01     unc_h_ingress_retry_irq0_reject.bl_ncs_vn0 uncore cache Ingress Request Queue Rejects event=0x18,umask=0x20  01     unc_h_ingress_retry_irq0_reject.bl_rsp_vn0 uncore cache Ingress Request Queue Rejects event=0x18,umask=4  01     unc_h_ingress_retry_irq0_reject.bl_wb_vn0 uncore cache Ingress Request Queue Rejects event=0x18,umask=8  01     unc_h_ingress_retry_irq0_reject.iv_non_upi uncore cache Ingress Request Queue Rejects event=0x18,umask=0x80  01     unc_h_ingress_retry_irq1_reject.allow_snp uncore cache Ingress Request Queue Rejects event=0x19,umask=0x40  01     unc_h_ingress_retry_irq1_reject.any_reject_irq0 uncore cache Ingress Request Queue Rejects event=0x19,umask=1  01     unc_h_ingress_retry_irq1_reject.pa_match uncore cache Ingress Request Queue Rejects event=0x19,umask=0x80  01     unc_h_ingress_retry_irq1_reject.sf_victim uncore cache Ingress Request Queue Rejects event=0x19,umask=8  01     unc_h_ingress_retry_irq1_reject.sf_way uncore cache Ingress Request Queue Rejects event=0x19,umask=0x20  01     unc_h_ingress_retry_ismq0_reject.ad_req_vn0 uncore cache ISMQ Rejects event=0x24,umask=1  01     unc_h_ingress_retry_ismq0_reject.ad_rsp_vn0 uncore cache ISMQ Rejects event=0x24,umask=2  01     unc_h_ingress_retry_ismq0_reject.ak_non_upi uncore cache ISMQ Rejects event=0x24,umask=0x40  01     unc_h_ingress_retry_ismq0_reject.bl_ncb_vn0 uncore cache ISMQ Rejects event=0x24,umask=0x10  01     unc_h_ingress_retry_ismq0_reject.bl_ncs_vn0 uncore cache ISMQ Rejects event=0x24,umask=0x20  01     unc_h_ingress_retry_ismq0_reject.bl_rsp_vn0 uncore cache ISMQ Rejects event=0x24,umask=4  01     unc_h_ingress_retry_ismq0_reject.bl_wb_vn0 uncore cache ISMQ Rejects event=0x24,umask=8  01     unc_h_ingress_retry_ismq0_reject.iv_non_upi uncore cache ISMQ Rejects event=0x24,umask=0x80  01     unc_h_ingress_retry_ismq0_retry.ad_req_vn0 uncore cache ISMQ Retries event=0x2c,umask=1  01     unc_h_ingress_retry_ismq0_retry.ad_rsp_vn0 uncore cache ISMQ Retries event=0x2c,umask=2  01     unc_h_ingress_retry_ismq0_retry.ak_non_upi uncore cache ISMQ Retries event=0x2c,umask=0x40  01     unc_h_ingress_retry_ismq0_retry.bl_ncb_vn0 uncore cache ISMQ Retries event=0x2c,umask=0x10  01     unc_h_ingress_retry_ismq0_retry.bl_ncs_vn0 uncore cache ISMQ Retries event=0x2c,umask=0x20  01     unc_h_ingress_retry_ismq0_retry.bl_rsp_vn0 uncore cache ISMQ Retries event=0x2c,umask=4  01     unc_h_ingress_retry_ismq0_retry.bl_wb_vn0 uncore cache ISMQ Retries event=0x2c,umask=8  01     unc_h_ingress_retry_ismq0_retry.iv_non_upi uncore cache ISMQ Retries event=0x2c,umask=0x80  01     unc_h_ingress_retry_other0_retry.ad_req_vn0 uncore cache Other Queue Retries event=0x2e,umask=1  01     unc_h_ingress_retry_other0_retry.ad_rsp_vn0 uncore cache Other Queue Retries event=0x2e,umask=2  01     unc_h_ingress_retry_other0_retry.ak_non_upi uncore cache Other Queue Retries event=0x2e,umask=0x40  01     unc_h_ingress_retry_other0_retry.bl_ncb_vn0 uncore cache Other Queue Retries event=0x2e,umask=0x10  01     unc_h_ingress_retry_other0_retry.bl_ncs_vn0 uncore cache Other Queue Retries event=0x2e,umask=0x20  01     unc_h_ingress_retry_other0_retry.bl_rsp_vn0 uncore cache Other Queue Retries event=0x2e,umask=4  01     unc_h_ingress_retry_other0_retry.bl_wb_vn0 uncore cache Other Queue Retries event=0x2e,umask=8  01     unc_h_ingress_retry_other0_retry.iv_non_upi uncore cache Other Queue Retries event=0x2e,umask=0x80  01     unc_h_ingress_retry_other1_retry.allow_snp uncore cache Other Queue Retries event=0x2f,umask=0x40  01     unc_h_ingress_retry_other1_retry.any_reject_irq0 uncore cache Other Queue Retries event=0x2f,umask=1  01     unc_h_ingress_retry_other1_retry.pa_match uncore cache Other Queue Retries event=0x2f,umask=0x80  01     unc_h_ingress_retry_other1_retry.sf_victim uncore cache Other Queue Retries event=0x2f,umask=8  01     unc_h_ingress_retry_other1_retry.sf_way uncore cache Other Queue Retries event=0x2f,umask=0x20  01     unc_h_ingress_retry_prq0_reject.ad_req_vn0 uncore cache Ingress Request Queue Rejects event=0x20,umask=1  01     unc_h_ingress_retry_prq0_reject.ad_rsp_vn0 uncore cache Ingress Request Queue Rejects event=0x20,umask=2  01     unc_h_ingress_retry_prq0_reject.ak_non_upi uncore cache Ingress Request Queue Rejects event=0x20,umask=0x40  01     unc_h_ingress_retry_prq0_reject.bl_ncb_vn0 uncore cache Ingress Request Queue Rejects event=0x20,umask=0x10  01     unc_h_ingress_retry_prq0_reject.bl_ncs_vn0 uncore cache Ingress Request Queue Rejects event=0x20,umask=0x20  01     unc_h_ingress_retry_prq0_reject.bl_rsp_vn0 uncore cache Ingress Request Queue Rejects event=0x20,umask=4  01     unc_h_ingress_retry_prq0_reject.bl_wb_vn0 uncore cache Ingress Request Queue Rejects event=0x20,umask=8  01     unc_h_ingress_retry_prq0_reject.iv_non_upi uncore cache Ingress Request Queue Rejects event=0x20,umask=0x80  01     unc_h_ingress_retry_prq1_reject.allow_snp uncore cache Ingress Request Queue Rejects event=0x21,umask=0x40  01     unc_h_ingress_retry_prq1_reject.any_reject_irq0 uncore cache Ingress Request Queue Rejects event=0x21,umask=1  01     unc_h_ingress_retry_prq1_reject.pa_match uncore cache Ingress Request Queue Rejects event=0x21,umask=0x80  01     unc_h_ingress_retry_prq1_reject.sf_victim uncore cache Ingress Request Queue Rejects event=0x21,umask=8  01     unc_h_ingress_retry_prq1_reject.sf_way uncore cache Ingress Request Queue Rejects event=0x21,umask=0x20  01     unc_h_ingress_retry_req_q0_retry.ad_req_vn0 uncore cache REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2a,umask=1  01     unc_h_ingress_retry_req_q0_retry.ad_rsp_vn0 uncore cache REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2a,umask=2  01     unc_h_ingress_retry_req_q0_retry.ak_non_upi uncore cache REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2a,umask=0x40  01     unc_h_ingress_retry_req_q0_retry.bl_ncb_vn0 uncore cache REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2a,umask=0x10  01     unc_h_ingress_retry_req_q0_retry.bl_ncs_vn0 uncore cache REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2a,umask=0x20  01     unc_h_ingress_retry_req_q0_retry.bl_rsp_vn0 uncore cache REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2a,umask=4  01     unc_h_ingress_retry_req_q0_retry.bl_wb_vn0 uncore cache REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2a,umask=8  01     unc_h_ingress_retry_req_q0_retry.iv_non_upi uncore cache REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2a,umask=0x80  01     unc_h_ingress_retry_req_q1_retry.allow_snp uncore cache REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2b,umask=0x40  01     unc_h_ingress_retry_req_q1_retry.any_reject_irq0 uncore cache REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2b,umask=1  01     unc_h_ingress_retry_req_q1_retry.pa_match uncore cache REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2b,umask=0x80  01     unc_h_ingress_retry_req_q1_retry.sf_victim uncore cache REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2b,umask=8  01     unc_h_ingress_retry_req_q1_retry.sf_way uncore cache REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) event=0x2b,umask=0x20  01     unc_h_misc.cv0_pref_miss uncore cache Miscellaneous events in the Cbo. CV0 Prefetch Miss event=0x39,umask=0x20  01     unc_h_misc.cv0_pref_vic uncore cache Miscellaneous events in the Cbo. CV0 Prefetch Victim event=0x39,umask=0x10  01     unc_h_misc.rfo_hit_s uncore cache Miscellaneous events in the Cbo. RFO HitS event=0x39,umask=8  01     unc_h_misc.rspi_was_fse uncore cache Miscellaneous events in the Cbo. Silent Snoop Eviction event=0x39,umask=1  01     unc_h_misc.wc_aliasing uncore cache Miscellaneous events in the Cbo. Write Combining Aliasing event=0x39,umask=2  01     unc_h_ring_bounces_horz.ad uncore cache Number of incoming messages from the Horizontal ring that were bounced, by ring type event=0xa1,umask=1  01     unc_h_ring_bounces_horz.ak uncore cache Number of incoming messages from the Horizontal ring that were bounced, by ring type - Acknowledgements to core event=0xa1,umask=2  01     unc_h_ring_bounces_horz.bl uncore cache Number of incoming messages from the Horizontal ring that were bounced, by ring type - Data Responses to core event=0xa1,umask=4  01     unc_h_ring_bounces_horz.iv uncore cache Number of incoming messages from the Horizontal ring that were bounced, by ring type - Snoops of processor's cache event=0xa1,umask=8  01     unc_h_ring_bounces_vert.ad uncore cache Number of incoming messages from the Vertical ring that were bounced, by ring type event=0xa0,umask=1  01     unc_h_ring_bounces_vert.ak uncore cache Number of incoming messages from the Vertical ring that were bounced, by ring type - Acknowledgements to core event=0xa0,umask=2  01     unc_h_ring_bounces_vert.bl uncore cache Number of incoming messages from the Vertical ring that were bounced, by ring type - Data Responses to core event=0xa0,umask=4  01     unc_h_ring_bounces_vert.iv uncore cache Number of incoming messages from the Vertical ring that were bounced, by ring type - Snoops of processor's cache event=0xa0,umask=8  01     unc_h_ring_sink_starved_horz.ad uncore cache Horizontal ring sink starvation count - AD ring event=0xa3,umask=1  01     unc_h_ring_sink_starved_horz.ak uncore cache Horizontal ring sink starvation count - AK ring event=0xa3,umask=2  01     unc_h_ring_sink_starved_horz.bl uncore cache Horizontal ring sink starvation count - BL ring event=0xa3,umask=4  01     unc_h_ring_sink_starved_horz.iv uncore cache Horizontal ring sink starvation count - IV ring event=0xa3,umask=8  01     unc_h_ring_sink_starved_vert.ad uncore cache Vertical ring sink starvation count - AD ring event=0xa2,umask=1  01     unc_h_ring_sink_starved_vert.ak uncore cache Vertical ring sink starvation count - AK ring event=0xa2,umask=2  01     unc_h_ring_sink_starved_vert.bl uncore cache Vertical ring sink starvation count - BL ring event=0xa2,umask=4  01     unc_h_ring_sink_starved_vert.iv uncore cache Vertical ring sink starvation count - IV ring event=0xa2,umask=8  01     unc_h_ring_src_thrtl uncore cache Counts cycles in throttle mode event=0xa4  01     unc_h_sf_lookup.any uncore cache Cache Lookups. Counts the number of times the LLC was accessed. Filters for any transaction originating from the IPQ or IRQ.  This does not include lookups originating from the ISMQ event=0x34,umask=0x11  01     unc_h_sf_lookup.data_read uncore cache Cache Lookups. Counts the number of times the LLC was accessed. Read transactions event=0x34,umask=3  01     unc_h_sf_lookup.remote_snoop uncore cache Cache Lookups. Counts the number of times the LLC was accessed. Filters for only snoop requests coming from the remote socket(s) through the IPQ event=0x34,umask=9  01     unc_h_sf_lookup.write uncore cache Cache Lookups. Counts the number of times the LLC was accessed. Writeback transactions from L2 to the LLC  This includes all write transactions -- both Cacheable and UC event=0x34,umask=5  01     unc_h_tg_ingress_busy_starved.ad_bnc uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority event=0xb4,umask=1  01     unc_h_tg_ingress_busy_starved.ad_crd uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority event=0xb4,umask=0x10  01     unc_h_tg_ingress_busy_starved.bl_bnc uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority event=0xb4,umask=4  01     unc_h_tg_ingress_busy_starved.bl_crd uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority event=0xb4,umask=0x40  01     unc_h_tg_ingress_bypass.ad_bnc uncore cache Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress  event=0xb2,umask=1  01     unc_h_tg_ingress_bypass.ad_crd uncore cache Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress  event=0xb2,umask=0x10  01     unc_h_tg_ingress_bypass.ak_bnc uncore cache Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress  event=0xb2,umask=2  01     unc_h_tg_ingress_bypass.bl_bnc uncore cache Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress  event=0xb2,umask=4  01     unc_h_tg_ingress_bypass.bl_crd uncore cache Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress  event=0xb2,umask=0x40  01     unc_h_tg_ingress_bypass.iv_bnc uncore cache Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress  event=0xb2,umask=8  01     unc_h_tg_ingress_crd_starved.ad_bnc uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit event=0xb3,umask=1  01     unc_h_tg_ingress_crd_starved.ad_crd uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit event=0xb3,umask=0x10  01     unc_h_tg_ingress_crd_starved.ak_bnc uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit event=0xb3,umask=2  01     unc_h_tg_ingress_crd_starved.bl_bnc uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit event=0xb3,umask=4  01     unc_h_tg_ingress_crd_starved.bl_crd uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit event=0xb3,umask=0x40  01     unc_h_tg_ingress_crd_starved.ifv uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit event=0xb3,umask=0x80  01     unc_h_tg_ingress_crd_starved.iv_bnc uncore cache Transgress Injection Starvation. Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit event=0xb3,umask=8  01     unc_h_tg_ingress_inserts.ad_bnc uncore cache Transgress Ingress Allocations. Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh event=0xb1,umask=1  01     unc_h_tg_ingress_inserts.ad_crd uncore cache Transgress Ingress Allocations. Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh event=0xb1,umask=0x10  01     unc_h_tg_ingress_inserts.ak_bnc uncore cache Transgress Ingress Allocations. Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh event=0xb1,umask=2  01     unc_h_tg_ingress_inserts.bl_bnc uncore cache Transgress Ingress Allocations. Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh event=0xb1,umask=4  01     unc_h_tg_ingress_inserts.bl_crd uncore cache Transgress Ingress Allocations. Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh event=0xb1,umask=0x40  01     unc_h_tg_ingress_inserts.iv_bnc uncore cache Transgress Ingress Allocations. Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh event=0xb1,umask=8  01     unc_h_tg_ingress_occupancy.ad_bnc uncore cache Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh event=0xb0,umask=1  01     unc_h_tg_ingress_occupancy.ad_crd uncore cache Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh event=0xb0,umask=0x10  01     unc_h_tg_ingress_occupancy.ak_bnc uncore cache Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh event=0xb0,umask=2  01     unc_h_tg_ingress_occupancy.bl_bnc uncore cache Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh event=0xb0,umask=4  01     unc_h_tg_ingress_occupancy.bl_crd uncore cache Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh event=0xb0,umask=0x40  01     unc_h_tg_ingress_occupancy.iv_bnc uncore cache Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh event=0xb0,umask=8  01     unc_h_tor_inserts.evict uncore cache Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent -SF/LLC Evictions event=0x35,umask=0x32  01     unc_h_tor_inserts.hit uncore cache Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent -Hit (Not a Miss) event=0x35,umask=0x1f  01     unc_h_tor_inserts.ipq uncore cache Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent -IPQ event=0x35,umask=0x38  01     unc_h_tor_inserts.irq uncore cache Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent -IRQ event=0x35,umask=0x31  01     unc_h_tor_inserts.miss uncore cache Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent -Miss event=0x35,umask=0x2f  01     unc_h_tor_inserts.prq uncore cache Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent -PRQ event=0x35,umask=0x34  01     unc_h_tor_occupancy.evict uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -SF/LLC Evictions event=0x36,umask=0x32  01     unc_h_tor_occupancy.hit uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -Hit (Not a Miss) event=0x36,umask=0x1f  01     unc_h_tor_occupancy.ipq uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IPQ event=0x36,umask=0x38  01     unc_h_tor_occupancy.ipq_hit uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IPQ hit event=0x36,umask=0x18  01     unc_h_tor_occupancy.ipq_miss uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IPQ miss event=0x36,umask=0x28  01     unc_h_tor_occupancy.irq uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IRQ or PRQ event=0x36,umask=0x31  01     unc_h_tor_occupancy.irq_hit uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IRQ or PRQ hit event=0x36,umask=0x11  01     unc_h_tor_occupancy.irq_miss uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IRQ or PRQ miss event=0x36,umask=0x21  01     unc_h_tor_occupancy.miss uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -Miss event=0x36,umask=0x2f  01     unc_h_tor_occupancy.prq uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -PRQ event=0x36,umask=0x34  01     unc_h_tor_occupancy.prq_hit uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -PRQ hit event=0x36,umask=0x14  01     unc_h_tor_occupancy.prq_miss uncore cache For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -PRQ miss event=0x36,umask=0x24  01     unc_h_u_clockticks uncore cache Uncore Clocks event=0  01     unc_h_vert_ring_ad_in_use.dn_even uncore cache Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Down and Even event=0xa6,umask=4  01     unc_h_vert_ring_ad_in_use.dn_odd uncore cache Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Down and Odd event=0xa6,umask=8  01     unc_h_vert_ring_ad_in_use.up_even uncore cache Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Up and Even event=0xa6,umask=1  01     unc_h_vert_ring_ad_in_use.up_odd uncore cache Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Up and Odd event=0xa6,umask=2  01     unc_h_vert_ring_ak_in_use.dn_even uncore cache Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Down and Even event=0xa8,umask=4  01     unc_h_vert_ring_ak_in_use.dn_odd uncore cache Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Down and Odd event=0xa8,umask=8  01     unc_h_vert_ring_ak_in_use.up_even uncore cache Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Up and Even event=0xa8,umask=1  01     unc_h_vert_ring_ak_in_use.up_odd uncore cache Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Up and Odd event=0xa8,umask=2  01     unc_h_vert_ring_bl_in_use.dn_even uncore cache Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Down and Even event=0xaa,umask=4  01     unc_h_vert_ring_bl_in_use.dn_odd uncore cache Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Down and Odd event=0xaa,umask=8  01     unc_h_vert_ring_bl_in_use.up_even uncore cache Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Up and Even event=0xaa,umask=1  01     unc_h_vert_ring_bl_in_use.up_odd uncore cache Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Up and Odd event=0xaa,umask=2  01     unc_h_vert_ring_iv_in_use.dn uncore cache Counts the number of cycles that the Vertical IV ring is being used at this ring stop - Down event=0xac,umask=4  01     unc_h_vert_ring_iv_in_use.up uncore cache Counts the number of cycles that the Vertical IV ring is being used at this ring stop - Up event=0xac,umask=1  01     unc_m2p_egress_cycles_full.ad_0 uncore io Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full.  AD_0 event=0x25,umask=1  01     unc_m2p_egress_cycles_full.ad_1 uncore io Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full.  AD_1 event=0x25,umask=8  01     unc_m2p_egress_cycles_full.ak_0 uncore io Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full.  AK_0 event=0x25,umask=2  01     unc_m2p_egress_cycles_full.ak_1 uncore io Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full.  AK_1 event=0x25,umask=0x10  01     unc_m2p_egress_cycles_full.bl_0 uncore io Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full.  BL_0 event=0x25,umask=4  01     unc_m2p_egress_cycles_full.bl_1 uncore io Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full.  BL_1 event=0x25,umask=0x20  01     unc_m2p_egress_cycles_ne.ad_0 uncore io Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty.  AD_0 event=0x23,umask=1  01     unc_m2p_egress_cycles_ne.ad_1 uncore io Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty.  AD_1 event=0x23,umask=8  01     unc_m2p_egress_cycles_ne.ak_0 uncore io Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty.  AK_0 event=0x23,umask=2  01     unc_m2p_egress_cycles_ne.ak_1 uncore io Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty.  AK_1 event=0x23,umask=0x10  01     unc_m2p_egress_cycles_ne.bl_0 uncore io Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty.  BL_0 event=0x23,umask=4  01     unc_m2p_egress_cycles_ne.bl_1 uncore io Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty.  BL_1 event=0x23,umask=0x20  01     unc_m2p_egress_inserts.ad_0 uncore io Egress (to CMS) Ingress. Counts the number of number of messages inserted into the  the M2PCIe Egress queue. AD_0 event=0x24,umask=1  01     unc_m2p_egress_inserts.ad_1 uncore io Egress (to CMS) Ingress. Counts the number of number of messages inserted into the  the M2PCIe Egress queue. AD_1 event=0x24,umask=0x10  01     unc_m2p_egress_inserts.ak_0 uncore io Egress (to CMS) Ingress. Counts the number of number of messages inserted into the  the M2PCIe Egress queue. AK_0 event=0x24,umask=2  01     unc_m2p_egress_inserts.ak_1 uncore io Egress (to CMS) Ingress. Counts the number of number of messages inserted into the  the M2PCIe Egress queue. AK_1 event=0x24,umask=0x20  01     unc_m2p_egress_inserts.ak_crd_0 uncore io Egress (to CMS) Ingress. Counts the number of number of messages inserted into the  the M2PCIe Egress queue. AK_CRD_0 event=0x24,umask=8  01     unc_m2p_egress_inserts.ak_crd_1 uncore io Egress (to CMS) Ingress. Counts the number of number of messages inserted into the  the M2PCIe Egress queue. AK_CRD_1 event=0x24,umask=0x80  01     unc_m2p_egress_inserts.bl_0 uncore io Egress (to CMS) Ingress. Counts the number of number of messages inserted into the  the M2PCIe Egress queue. BL_0 event=0x24,umask=4  01     unc_m2p_egress_inserts.bl_1 uncore io Egress (to CMS) Ingress. Counts the number of number of messages inserted into the  the M2PCIe Egress queue. BL_1 event=0x24,umask=0x40  01     unc_m2p_ingress_cycles_ne.all uncore io Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.ALL event=0x10,umask=0x80  01     unc_m2p_ingress_cycles_ne.cbo_idi uncore io Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_IDI event=0x10,umask=1  01     unc_m2p_ingress_cycles_ne.cbo_ncb uncore io Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_NCB event=0x10,umask=2  01     unc_m2p_ingress_cycles_ne.cbo_ncs uncore io Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_NCS event=0x10,umask=4  01     uncore_edc_uclk unc_e_edc_access.hit_clean uncore memory Counts the number of read requests and streaming stores that hit in MCDRAM cache and the data in MCDRAM is clean with respect to DDR. This event is only valid in cache and hybrid memory mode event=2,umask=1  01     unc_e_edc_access.hit_dirty uncore memory Counts the number of read requests and streaming stores that hit in MCDRAM cache and the data in MCDRAM is dirty with respect to DDR. This event is only valid in cache and hybrid memory mode event=2,umask=2  01     unc_e_edc_access.miss_clean uncore memory Counts the number of read requests and streaming stores that miss in MCDRAM cache and the data evicted from the MCDRAM is clean with respect to DDR. This event is only valid in cache and hybrid memory mode event=2,umask=4  01     unc_e_edc_access.miss_dirty uncore memory Counts the number of read requests and streaming stores that miss in MCDRAM cache and the data evicted from the MCDRAM is dirty with respect to DDR. This event is only valid in cache and hybrid memory mode event=2,umask=8  01     unc_e_edc_access.miss_invalid uncore memory Number of EDC Hits or Misses. Miss I event=2,umask=0x10  01     uncore_edc_eclk unc_e_e_clockticks uncore memory ECLK count event=0  01     unc_e_rpq_inserts uncore memory Counts the number of read requests received by the MCDRAM controller. This event is valid in all three memory modes: flat, cache and hybrid. In cache and hybrid memory mode, this event counts all read requests as well as streaming stores that hit or miss in the MCDRAM cache event=1,umask=1  01     unc_e_u_clockticks uncore memory UCLK count event=0  01     unc_e_wpq_inserts uncore memory Counts the number of write requests received by the MCDRAM controller. This event is valid in all three memory modes: flat, cache and hybrid. In cache and hybrid memory mode, this event counts all streaming stores, writebacks and, read requests that miss in MCDRAM cache event=2,umask=1  01     uncore_imc_dclk unc_m_cas_count.all uncore memory CAS All event=3,umask=3  01     unc_m_cas_count.rd uncore memory CAS Reads event=3,umask=1  01     unc_m_cas_count.wr uncore memory CAS Writes event=3,umask=2  01     unc_m_d_clockticks uncore memory DCLK count event=0  01     uncore_imc_uclk unc_m_u_clockticks uncore memory UCLK count event=0  01     mem_uops_retired.dtlb_miss_loads virtual memory Counts the number of load micro-ops retired that cause a DTLB miss (Precise Event)  Supports address when precise event=4,period=200003,umask=8  00     page_walks.cycles virtual memory Counts the total number of core cycles for all the page walks. The cycles for page walks started in speculative path will also be included event=5,period=200003,umask=3  00    This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress page_walks.d_side_cycles virtual memory Counts the total number of core cycles for all the D-side page walks. The cycles for page walks started in speculative path will also be included event=5,period=200003,umask=1  00     page_walks.d_side_walks virtual memory Counts the total D-side page walks that are completed or started. The page walks started in the speculative path will also be counted event=5,edge=1,period=100003,umask=1  00     page_walks.i_side_cycles virtual memory Counts the total number of core cycles for all the I-side page walks. The cycles for page walks started in speculative path will also be included event=5,period=200003,umask=2  00    This event counts every cycle when an I-side (walks due to an instruction fetch) page walk is in progress page_walks.i_side_walks virtual memory Counts the total I-side page walks that are completed event=5,edge=1,period=100003,umask=2  00     page_walks.walks virtual memory Counts the total page walks that are completed (I-side and D-side) event=5,edge=1,period=100003,umask=3  00     mem_load_l3_miss_retired.memside_cache cache Retired load instructions which data source is memory side cache  Supports address when precise event=0xd3,period=100007  00    Retired load instructions which data source is memory side cache. Available PDIST counters: 0,1  Supports address when precise mem_load_uops_l3_miss_retired.local_dram cache This event is deprecated. Refer to new event MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM event=0xd3,period=1000003,umask=1  10     mem_load_uops_l3_miss_retired.memside_cache cache This event is deprecated. Refer to new event MEM_LOAD_UOPS_LLC_MISS_RETIRED.MEMSIDE_CACHE event=0xd3,period=1000003,umask=0x40  10     mem_load_uops_llc_miss_retired.local_dram cache Counts the number of load ops retired that miss the L2 cache, missed the Memory Side Cache and hit in DRAM event=0xd3,period=1000003,umask=1  00     mem_load_uops_llc_miss_retired.memside_cache cache Counts the number of load ops retired that miss the LLC cache and hit in the Memory Side Cache event=0xd3,period=1000003,umask=0x40  00     mem_store_retired.memside_cache cache Number of cache-lines required by retired stores whose Data Source is: Memory Side Cache event=0x44,period=100021  00     ocr.corewb_m.any_response cache Counts writebacks of modified cachelines that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x10008  00    Counts writebacks of modified cachelines that have any type of response. Available PDIST counters: 0 ocr.corewb_m.l3_hit cache Counts writebacks of modified cachelines that were supplied by the L3 cache event=0x2a,period=100003,umask=1,offcore_rsp=0x7E001E00008  00    Counts writebacks of modified cachelines that were supplied by the L3 cache. Available PDIST counters: 0 ocr.corewb_nonm.any_response cache Counts writebacks of non-modified cachelines that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x11000  00    Counts writebacks of non-modified cachelines that have any type of response. Available PDIST counters: 0 ocr.corewb_nonm.l3_hit cache Counts writebacks of non-modified cachelines that were supplied by the L3 cache event=0x2a,period=100003,umask=1,offcore_rsp=0x7E001E01000  00    Counts writebacks of non-modified cachelines that were supplied by the L3 cache. Available PDIST counters: 0 ocr.demand_code_rd.memside_cache cache Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by mem side cache event=0xb7,period=100003,umask=1,offcore_rsp=0x11F80000004  00    Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by mem side cache. Available PDIST counters: 0 ocr.demand_data_rd.memside_cache cache Counts demand data reads that were supplied by mem side cache event=0xb7,period=100003,umask=1,offcore_rsp=0x11F80000001  00    Counts demand data reads that were supplied by mem side cache. Available PDIST counters: 0 ocr.reads_to_core.l3_hit cache Counts all data read, code read, RFO and ITOM requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache event=0x2a,period=100003,umask=1,offcore_rsp=0x7E001E04477  00    Counts all data read, code read, RFO and ITOM requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache. Available PDIST counters: 0 ocr.demand_code_rd.dram memory Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x1FBC000004  00    Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM. Available PDIST counters: 0 ocr.demand_code_rd.l3_miss memory Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache and were supplied by the system memory (DRAM, MSC, or MMIO) event=0xb7,period=100003,umask=1,offcore_rsp=0x13FBFC00004  00    Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache and were supplied by the system memory (DRAM, MSC, or MMIO). Available PDIST counters: 0 ocr.demand_data_rd.dram memory Counts demand data reads that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x1FBC000001  00    Counts demand data reads that were supplied by DRAM. Available PDIST counters: 0 ocr.demand_data_rd.l3_miss memory Counts demand data reads that were not supplied by the L3 cache and were supplied by the system memory (DRAM, MSC, or MMIO) event=0xb7,period=100003,umask=1,offcore_rsp=0x13FBFC00001  00    Counts demand data reads that were not supplied by the L3 cache and were supplied by the system memory (DRAM, MSC, or MMIO). Available PDIST counters: 0 ocr.demand_data_rd.l3_miss memory Counts demand data reads that were not supplied by the L3 cache and were supplied by the system memory (DRAM, MSC, or MMIO) event=0x2a,period=100003,umask=1,offcore_rsp=0x9E7FA000001  00    Counts demand data reads that were not supplied by the L3 cache and were supplied by the system memory (DRAM, MSC, or MMIO). Available PDIST counters: 0 ocr.demand_rfo.dram memory Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x1FBC000002  00    Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM. Available PDIST counters: 0 ocr.demand_rfo.l3_miss memory Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache and were supplied by the system memory (DRAM, MSC, or MMIO) event=0xb7,period=100003,umask=1,offcore_rsp=0x13FBFC00002  00    Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache and were supplied by the system memory (DRAM, MSC, or MMIO). Available PDIST counters: 0 ocr.demand_rfo.l3_miss memory Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache and were supplied by the system memory (DRAM, MSC, or MMIO) event=0x2a,period=100003,umask=1,offcore_rsp=0x9E7FA000002  00    Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache and were supplied by the system memory (DRAM, MSC, or MMIO). Available PDIST counters: 0 ocr.all_requests.any_response other Counts all requests that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0xFF0000001DFFF  00    Counts all requests that have any type of response. Available PDIST counters: 0 ocr.full_streaming_wr.any_response other Counts full streaming stores (64 bytes, WCiLF) that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x800000010000  00    Counts full streaming stores (64 bytes, WCiLF) that have any type of response. Available PDIST counters: 0 ocr.partial_streaming_wr.any_response other Counts partial streaming stores (less than 64 bytes, WCiL) that have any type of response event=0xb7,period=100003,umask=1,offcore_rsp=0x400000010000  00    Counts partial streaming stores (less than 64 bytes, WCiL) that have any type of response. Available PDIST counters: 0 misc_retired2.keylocker_access pipeline Counts the number of accesses to KeyLocker cache event=0xe1,period=1000003,umask=0x10  00     misc_retired2.keylocker_miss pipeline Counts the number of misses to KeyLocker cache event=0xe1,period=1000003,umask=0x11  00     uncore_santa unc_m_total_data uncore memory Total number of read and write byte transfers to/from DRAM, in 32B chunk, per DDR channel. Counter increments by 1 after sending  or receiving 32B chunk data event=0x3c  01     lock_cycles.cache_lock_duration cache Cycles when L1D is locked event=0x42,period=2000003,umask=2  00    This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION) mem_inst_retired.stlb_hit_loads cache Retired load instructions that hit the STLB  Supports address when precise event=0xd0,period=100003,umask=9  00    Number of retired load instructions with a clean hit in the 2nd-level TLB (STLB). Available PDIST counters: 0  Supports address when precise mem_inst_retired.stlb_hit_stores cache Retired store instructions that hit the STLB  Supports address when precise event=0xd0,period=100003,umask=0xa  00    Number of retired store instructions that hit in the 2nd-level TLB (STLB). Available PDIST counters: 0  Supports address when precise ocr.corewb_m.l3_hit cache Counts writebacks of modified cachelines that hit in the L3 or were snooped from another core's caches event=0x2a,period=100003,umask=1,offcore_rsp=0x3F803C0008  00    Counts writebacks of modified cachelines that hit in the L3 or were snooped from another core's caches. Available PDIST counters: 0 ocr.corewb_nonm.l3_hit cache Counts writebacks of non-modified cachelines that hit in the L3 or were snooped from another core's caches event=0x2a,period=100003,umask=1,offcore_rsp=0x3F803C1000  00    Counts writebacks of non-modified cachelines that hit in the L3 or were snooped from another core's caches. Available PDIST counters: 0 ocr.demand_code_rd.l3_hit cache Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0004  00    Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache. Available PDIST counters: 0 ocr.demand_data_rd.l3_hit cache Counts demand data reads that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0001  00    Counts demand data reads that were supplied by the L3 cache. Available PDIST counters: 0 ocr.demand_rfo.l3_hit cache Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0002  00    Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache. Available PDIST counters: 0 ocr.reads_to_core.l3_hit cache Counts all data read, code read, RFO and ITOM requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches event=0x2a,period=100003,umask=1,offcore_rsp=0x3F803C4477  00    Counts all data read, code read, RFO and ITOM requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches. Available PDIST counters: 0 frontend_retired.any_dsb_miss frontend Retired Instructions who experienced DSB miss event=0xc6,period=100007,umask=3,frontend=0x1  00    Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Available PDIST counters: 0 frontend_retired.itlb_miss frontend Retired Instructions who experienced iTLB true miss event=0xc6,period=100007,umask=3,frontend=0x14  00    Counts retired Instructions that experienced iTLB (Instruction TLB) true miss. Available PDIST counters: 0 frontend_retired.l1i_miss frontend Retired Instructions who experienced Instruction L1 Cache true miss event=0xc6,period=100007,umask=3,frontend=0x12  00    Counts retired Instructions who experienced Instruction L1 Cache true miss. Available PDIST counters: 0 frontend_retired.l2_miss frontend Retired Instructions who experienced Instruction L2 Cache true miss event=0xc6,period=100007,umask=3,frontend=0x13  00    Counts retired Instructions who experienced Instruction L2 Cache true miss. Available PDIST counters: 0 frontend_retired.ms_flows frontend FRONTEND_RETIRED.MS_FLOWS event=0xc6,period=100007,umask=3,frontend=0x8  00    FRONTEND_RETIRED.MS_FLOWS Available PDIST counters: 0 frontend_retired.stlb_miss frontend Retired Instructions who experienced STLB (2nd level TLB) true miss event=0xc6,period=100007,umask=3,frontend=0x15  00    Counts retired Instructions that experienced STLB (2nd level TLB) true miss. Available PDIST counters: 0 frontend_retired.unknown_branch frontend FRONTEND_RETIRED.UNKNOWN_BRANCH event=0xc6,period=100007,umask=3,frontend=0x17  00    FRONTEND_RETIRED.UNKNOWN_BRANCH Available PDIST counters: 0 ocr.demand_code_rd.l3_miss memory Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBFC00004  00    Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.demand_data_rd.dram memory Counts demand data reads that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x184000001  00    Counts demand data reads that were supplied by DRAM. Available PDIST counters: 0 br_inst_retired.all_branches pipeline Counts the total number of branch instructions retired for all branch types  Spec update: MTL012, MTL013 event=0xc4,period=200003  00    Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires.  All branch type instructions are accounted for  Spec update: MTL012, MTL013 br_inst_retired.cond pipeline Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches  Spec update: MTL013 event=0xc4,period=200003,umask=0x7e  00     br_inst_retired.far_branch pipeline Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return  Spec update: MTL013 event=0xc4,period=200003,umask=0xbf  00     br_inst_retired.indirect pipeline Counts the number of near indirect JMP and near indirect CALL branch instructions retired  Spec update: MTL013 event=0xc4,period=200003,umask=0xeb  00     br_inst_retired.indirect_call pipeline Counts the number of near indirect CALL branch instructions retired  Spec update: MTL013 event=0xc4,period=200003,umask=0xfb  00     br_inst_retired.ind_call pipeline This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT_CALL  Spec update: MTL013 event=0xc4,period=200003,umask=0xfb  10     br_inst_retired.near_call pipeline Counts the number of near CALL branch instructions retired  Spec update: MTL012, MTL013 event=0xc4,period=200003,umask=0xf9  00     br_inst_retired.near_taken pipeline Counts the number of near taken branch instructions retired  Spec update: MTL013 event=0xc4,period=200003,umask=0xc0  00     br_misp_retired.cond_ntaken_cost pipeline Mispredicted non-taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch event=0xc5,period=400009,umask=0x50  00    Mispredicted non-taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0 br_misp_retired.cond_taken_cost pipeline Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch event=0xc5,period=400009,umask=0x41  00    Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0 br_misp_retired.indirect_call_cost pipeline Mispredicted indirect CALL retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch event=0xc5,period=400009,umask=0x42  00    Mispredicted indirect CALL retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0 br_misp_retired.indirect_cost pipeline Mispredicted near indirect branch instructions retired (excluding returns). This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch event=0xc5,period=100003,umask=0xc0  00    Mispredicted near indirect branch instructions retired (excluding returns). This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0 br_misp_retired.ret_cost pipeline Mispredicted ret instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch event=0xc5,period=100007,umask=0x48  00    Mispredicted ret instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0 unc_hac_arb_coh_trk_requests.all uncore interconnect Number of entries allocated. Account for Any type: e.g. Snoop,  etc event=0x84,umask=1  01     cache_lock_cycles.l1d cache Cycles L1D locked event=0x63,period=2000000,umask=2  00     cache_lock_cycles.l1d_l2 cache Cycles L1D and L2 locked event=0x63,period=2000000,umask=1  00     l1d.m_evict cache L1D cache lines replaced in M state event=0x51,period=2000000,umask=4  00     l1d.m_repl cache L1D cache lines allocated in the M state event=0x51,period=2000000,umask=2  00     l1d.m_snoop_evict cache L1D snoop eviction of cache lines in M state event=0x51,period=2000000,umask=8  00     l1d.repl cache L1 data cache lines allocated event=0x51,period=2000000,umask=1  00     l1d_all_ref.any cache All references to the L1 data cache event=0x43,period=2000000,umask=1  00     l1d_all_ref.cacheable cache L1 data cacheable reads and writes event=0x43,period=2000000,umask=2  00     l1d_cache_ld.e_state cache L1 data cache read in E state event=0x40,period=2000000,umask=4  00     l1d_cache_ld.i_state cache L1 data cache read in I state (misses) event=0x40,period=2000000,umask=1  00     l1d_cache_ld.mesi cache L1 data cache reads event=0x40,period=2000000,umask=0xf  00     l1d_cache_ld.m_state cache L1 data cache read in M state event=0x40,period=2000000,umask=8  00     l1d_cache_ld.s_state cache L1 data cache read in S state event=0x40,period=2000000,umask=2  00     l1d_cache_lock.e_state cache L1 data cache load locks in E state event=0x42,period=2000000,umask=4  00     l1d_cache_lock.hit cache L1 data cache load lock hits event=0x42,period=2000000,umask=1  00     l1d_cache_lock.m_state cache L1 data cache load locks in M state event=0x42,period=2000000,umask=8  00     l1d_cache_lock.s_state cache L1 data cache load locks in S state event=0x42,period=2000000,umask=2  00     l1d_cache_lock_fb_hit cache L1D load lock accepted in fill buffer event=0x53,period=2000000,umask=1  00     l1d_cache_prefetch_lock_fb_hit cache L1D prefetch load lock accepted in fill buffer event=0x52,period=2000000,umask=1  00     l1d_cache_st.e_state cache L1 data cache stores in E state event=0x41,period=2000000,umask=4  00     l1d_cache_st.m_state cache L1 data cache stores in M state event=0x41,period=2000000,umask=8  00     l1d_cache_st.s_state cache L1 data cache stores in S state event=0x41,period=2000000,umask=2  00     l1d_prefetch.miss cache L1D hardware prefetch misses event=0x4e,period=200000,umask=2  00     l1d_prefetch.requests cache L1D hardware prefetch requests event=0x4e,period=200000,umask=1  00     l1d_prefetch.triggers cache L1D hardware prefetch requests triggered event=0x4e,period=200000,umask=4  00     l1d_wb_l2.e_state cache L1 writebacks to L2 in E state event=0x28,period=100000,umask=4  00     l1d_wb_l2.i_state cache L1 writebacks to L2 in I state (misses) event=0x28,period=100000,umask=1  00     l1d_wb_l2.mesi cache All L1 writebacks to L2 event=0x28,period=100000,umask=0xf  00     l1d_wb_l2.m_state cache L1 writebacks to L2 in M state event=0x28,period=100000,umask=8  00     l1d_wb_l2.s_state cache L1 writebacks to L2 in S state event=0x28,period=100000,umask=2  00     l1i.cycles_stalled cache L1I instruction fetch stall cycles event=0x80,period=2000000,umask=4  00     l1i.hits cache L1I instruction fetch hits event=0x80,period=2000000,umask=1  00     l1i.misses cache L1I instruction fetch misses event=0x80,period=2000000,umask=2  00     l1i.reads cache L1I Instruction fetches event=0x80,period=2000000,umask=3  00     l2_data_rqsts.any cache All L2 data requests event=0x26,period=200000,umask=0xff  00     l2_data_rqsts.demand.e_state cache L2 data demand loads in E state event=0x26,period=200000,umask=4  00     l2_data_rqsts.demand.i_state cache L2 data demand loads in I state (misses) event=0x26,period=200000,umask=1  00     l2_data_rqsts.demand.mesi cache L2 data demand requests event=0x26,period=200000,umask=0xf  00     l2_data_rqsts.demand.m_state cache L2 data demand loads in M state event=0x26,period=200000,umask=8  00     l2_data_rqsts.demand.s_state cache L2 data demand loads in S state event=0x26,period=200000,umask=2  00     l2_data_rqsts.prefetch.e_state cache L2 data prefetches in E state event=0x26,period=200000,umask=0x40  00     l2_data_rqsts.prefetch.i_state cache L2 data prefetches in the I state (misses) event=0x26,period=200000,umask=0x10  00     l2_data_rqsts.prefetch.mesi cache All L2 data prefetches event=0x26,period=200000,umask=0xf0  00     l2_data_rqsts.prefetch.m_state cache L2 data prefetches in M state event=0x26,period=200000,umask=0x80  00     l2_data_rqsts.prefetch.s_state cache L2 data prefetches in the S state event=0x26,period=200000,umask=0x20  00     l2_lines_in.any cache L2 lines allocated event=0xf1,period=100000,umask=7  00     l2_lines_in.e_state cache L2 lines allocated in the E state event=0xf1,period=100000,umask=4  00     l2_lines_in.s_state cache L2 lines allocated in the S state event=0xf1,period=100000,umask=2  00     l2_lines_out.any cache L2 lines evicted event=0xf2,period=100000,umask=0xf  00     l2_lines_out.demand_clean cache L2 lines evicted by a demand request event=0xf2,period=100000,umask=1  00     l2_lines_out.demand_dirty cache L2 modified lines evicted by a demand request event=0xf2,period=100000,umask=2  00     l2_lines_out.prefetch_clean cache L2 lines evicted by a prefetch request event=0xf2,period=100000,umask=4  00     l2_lines_out.prefetch_dirty cache L2 modified lines evicted by a prefetch request event=0xf2,period=100000,umask=8  00     l2_rqsts.ifetches cache L2 instruction fetches event=0x24,period=200000,umask=0x30  00     l2_rqsts.ifetch_hit cache L2 instruction fetch hits event=0x24,period=200000,umask=0x10  00     l2_rqsts.ifetch_miss cache L2 instruction fetch misses event=0x24,period=200000,umask=0x20  00     l2_rqsts.ld_hit cache L2 load hits event=0x24,period=200000,umask=1  00     l2_rqsts.ld_miss cache L2 load misses event=0x24,period=200000,umask=2  00     l2_rqsts.loads cache L2 requests event=0x24,period=200000,umask=3  00     l2_rqsts.miss cache All L2 misses event=0x24,period=200000,umask=0xaa  00     l2_rqsts.prefetches cache All L2 prefetches event=0x24,period=200000,umask=0xc0  00     l2_rqsts.prefetch_hit cache L2 prefetch hits event=0x24,period=200000,umask=0x40  00     l2_rqsts.prefetch_miss cache L2 prefetch misses event=0x24,period=200000,umask=0x80  00     l2_rqsts.references cache All L2 requests event=0x24,period=200000,umask=0xff  00     l2_rqsts.rfos cache L2 RFO requests event=0x24,period=200000,umask=0xc  00     l2_rqsts.rfo_hit cache L2 RFO hits event=0x24,period=200000,umask=4  00     l2_rqsts.rfo_miss cache L2 RFO misses event=0x24,period=200000,umask=8  00     l2_transactions.any cache All L2 transactions event=0xf0,period=200000,umask=0x80  00     l2_transactions.fill cache L2 fill transactions event=0xf0,period=200000,umask=0x20  00     l2_transactions.ifetch cache L2 instruction fetch transactions event=0xf0,period=200000,umask=4  00     l2_transactions.l1d_wb cache L1D writeback to L2 transactions event=0xf0,period=200000,umask=0x10  00     l2_transactions.load cache L2 Load transactions event=0xf0,period=200000,umask=1  00     l2_transactions.prefetch cache L2 prefetch transactions event=0xf0,period=200000,umask=8  00     l2_transactions.rfo cache L2 RFO transactions event=0xf0,period=200000,umask=2  00     l2_transactions.wb cache L2 writeback to LLC transactions event=0xf0,period=200000,umask=0x40  00     l2_write.lock.e_state cache L2 demand lock RFOs in E state event=0x27,period=100000,umask=0x40  00     l2_write.lock.hit cache All demand L2 lock RFOs that hit the cache event=0x27,period=100000,umask=0xe0  00     l2_write.lock.i_state cache L2 demand lock RFOs in I state (misses) event=0x27,period=100000,umask=0x10  00     l2_write.lock.mesi cache All demand L2 lock RFOs event=0x27,period=100000,umask=0xf0  00     l2_write.lock.m_state cache L2 demand lock RFOs in M state event=0x27,period=100000,umask=0x80  00     l2_write.lock.s_state cache L2 demand lock RFOs in S state event=0x27,period=100000,umask=0x20  00     l2_write.rfo.hit cache All L2 demand store RFOs that hit the cache event=0x27,period=100000,umask=0xe  00     l2_write.rfo.i_state cache L2 demand store RFOs in I state (misses) event=0x27,period=100000,umask=1  00     l2_write.rfo.mesi cache All L2 demand store RFOs event=0x27,period=100000,umask=0xf  00     l2_write.rfo.m_state cache L2 demand store RFOs in M state event=0x27,period=100000,umask=8  00     l2_write.rfo.s_state cache L2 demand store RFOs in S state event=0x27,period=100000,umask=2  00     longest_lat_cache.miss cache Longest latency cache miss event=0x2e,period=100000,umask=0x41  00     longest_lat_cache.reference cache Longest latency cache reference event=0x2e,period=200000,umask=0x4f  00     mem_inst_retired.latency_above_threshold_0 cache Memory instructions retired above 0 clocks (Precise Event) event=0xb,period=2000000,umask=0x10,ldlat=None  00     mem_inst_retired.latency_above_threshold_1024 cache Memory instructions retired above 1024 clocks (Precise Event) event=0xb,period=100,umask=0x10,ldlat=0x400  00     mem_inst_retired.latency_above_threshold_128 cache Memory instructions retired above 128 clocks (Precise Event) event=0xb,period=1000,umask=0x10,ldlat=0x80  00     mem_inst_retired.latency_above_threshold_16 cache Memory instructions retired above 16 clocks (Precise Event) event=0xb,period=10000,umask=0x10,ldlat=0x10  00     mem_inst_retired.latency_above_threshold_16384 cache Memory instructions retired above 16384 clocks (Precise Event) event=0xb,period=5,umask=0x10,ldlat=0x4000  00     mem_inst_retired.latency_above_threshold_2048 cache Memory instructions retired above 2048 clocks (Precise Event) event=0xb,period=50,umask=0x10,ldlat=0x800  00     mem_inst_retired.latency_above_threshold_256 cache Memory instructions retired above 256 clocks (Precise Event) event=0xb,period=500,umask=0x10,ldlat=0x100  00     mem_inst_retired.latency_above_threshold_32 cache Memory instructions retired above 32 clocks (Precise Event) event=0xb,period=5000,umask=0x10,ldlat=0x20  00     mem_inst_retired.latency_above_threshold_32768 cache Memory instructions retired above 32768 clocks (Precise Event) event=0xb,period=3,umask=0x10,ldlat=0x8000  00     mem_inst_retired.latency_above_threshold_4 cache Memory instructions retired above 4 clocks (Precise Event) event=0xb,period=50000,umask=0x10,ldlat=0x4  00     mem_inst_retired.latency_above_threshold_4096 cache Memory instructions retired above 4096 clocks (Precise Event) event=0xb,period=20,umask=0x10,ldlat=0x1000  00     mem_inst_retired.latency_above_threshold_512 cache Memory instructions retired above 512 clocks (Precise Event) event=0xb,period=200,umask=0x10,ldlat=0x200  00     mem_inst_retired.latency_above_threshold_64 cache Memory instructions retired above 64 clocks (Precise Event) event=0xb,period=2000,umask=0x10,ldlat=0x40  00     mem_inst_retired.latency_above_threshold_8 cache Memory instructions retired above 8 clocks (Precise Event) event=0xb,period=20000,umask=0x10,ldlat=0x8  00     mem_inst_retired.latency_above_threshold_8192 cache Memory instructions retired above 8192 clocks (Precise Event) event=0xb,period=10,umask=0x10,ldlat=0x2000  00     mem_inst_retired.loads cache Instructions retired which contains a load (Precise Event) event=0xb,period=2000000,umask=1  00     mem_inst_retired.stores cache Instructions retired which contains a store (Precise Event) event=0xb,period=2000000,umask=2  00     mem_load_retired.hit_lfb cache Retired loads that miss L1D and hit an previously allocated LFB (Precise Event) event=0xcb,period=200000,umask=0x40  00     mem_load_retired.l1d_hit cache Retired loads that hit the L1 data cache (Precise Event) event=0xcb,period=2000000,umask=1  00     mem_load_retired.l2_hit cache Retired loads that hit the L2 cache (Precise Event) event=0xcb,period=200000,umask=2  00     mem_load_retired.llc_miss cache Retired loads that miss the LLC cache (Precise Event) event=0xcb,period=10000,umask=0x10  00     mem_load_retired.llc_unshared_hit cache Retired loads that hit valid versions in the LLC cache (Precise Event) event=0xcb,period=40000,umask=4  00     mem_load_retired.other_core_l2_hit_hitm cache Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event) event=0xcb,period=40000,umask=8  00     mem_uncore_retired.local_dram cache Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event) event=0xf,period=10000,umask=0x20  00     mem_uncore_retired.other_core_l2_hitm cache Load instructions retired that HIT modified data in sibling core (Precise Event) event=0xf,period=40000,umask=2  00     mem_uncore_retired.remote_cache_local_home_hit cache Load instructions retired remote cache HIT data source (Precise Event) event=0xf,period=20000,umask=8  00     mem_uncore_retired.remote_dram cache Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event) event=0xf,period=10000,umask=0x10  00     mem_uncore_retired.uncacheable cache Load instructions retired IO (Precise Event) event=0xf,period=4000,umask=0x80  00     offcore_requests.l1d_writeback cache Offcore L1 data cache writebacks event=0xb0,period=100000,umask=0x40  00     offcore_requests_sq_full cache Offcore requests blocked due to Super Queue full event=0xb2,period=100000,umask=1  00     offcore_response.any_data.any_cache_dram cache Offcore data reads satisfied by any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7F11  00     offcore_response.any_data.any_location cache All offcore data reads event=0xb7,period=100000,umask=1,offcore_rsp=0xFF11  00     offcore_response.any_data.io_csr_mmio cache Offcore data reads satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8011  00     offcore_response.any_data.llc_hit_no_other_core cache Offcore data reads satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x111  00     offcore_response.any_data.llc_hit_other_core_hit cache Offcore data reads satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x211  00     offcore_response.any_data.llc_hit_other_core_hitm cache Offcore data reads satisfied by the LLC  and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x411  00     offcore_response.any_data.local_cache cache Offcore data reads satisfied by the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x711  00     offcore_response.any_data.local_cache_dram cache Offcore data reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4711  00     offcore_response.any_data.remote_cache cache Offcore data reads satisfied by a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1811  00     offcore_response.any_data.remote_cache_dram cache Offcore data reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x3811  00     offcore_response.any_data.remote_cache_hit cache Offcore data reads that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1011  00     offcore_response.any_data.remote_cache_hitm cache Offcore data reads that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x811  00     offcore_response.any_ifetch.any_cache_dram cache Offcore code reads satisfied by any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7F44  00     offcore_response.any_ifetch.any_location cache All offcore code reads event=0xb7,period=100000,umask=1,offcore_rsp=0xFF44  00     offcore_response.any_ifetch.io_csr_mmio cache Offcore code reads satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8044  00     offcore_response.any_ifetch.llc_hit_no_other_core cache Offcore code reads satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x144  00     offcore_response.any_ifetch.llc_hit_other_core_hit cache Offcore code reads satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x244  00     offcore_response.any_ifetch.llc_hit_other_core_hitm cache Offcore code reads satisfied by the LLC  and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x444  00     offcore_response.any_ifetch.local_cache cache Offcore code reads satisfied by the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x744  00     offcore_response.any_ifetch.local_cache_dram cache Offcore code reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4744  00     offcore_response.any_ifetch.remote_cache cache Offcore code reads satisfied by a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1844  00     offcore_response.any_ifetch.remote_cache_dram cache Offcore code reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x3844  00     offcore_response.any_ifetch.remote_cache_hit cache Offcore code reads that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1044  00     offcore_response.any_ifetch.remote_cache_hitm cache Offcore code reads that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x844  00     offcore_response.any_request.any_cache_dram cache Offcore requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7FFF  00     offcore_response.any_request.any_location cache All offcore requests event=0xb7,period=100000,umask=1,offcore_rsp=0xFFFF  00     offcore_response.any_request.io_csr_mmio cache Offcore requests satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x80FF  00     offcore_response.any_request.llc_hit_no_other_core cache Offcore requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x1FF  00     offcore_response.any_request.llc_hit_other_core_hit cache Offcore requests satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x2FF  00     offcore_response.any_request.llc_hit_other_core_hitm cache Offcore requests satisfied by the LLC  and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x4FF  00     offcore_response.any_request.local_cache cache Offcore requests satisfied by the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x7FF  00     offcore_response.any_request.local_cache_dram cache Offcore requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x47FF  00     offcore_response.any_request.remote_cache cache Offcore requests satisfied by a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x18FF  00     offcore_response.any_request.remote_cache_dram cache Offcore requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x38FF  00     offcore_response.any_request.remote_cache_hit cache Offcore requests that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x10FF  00     offcore_response.any_request.remote_cache_hitm cache Offcore requests that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x8FF  00     offcore_response.any_rfo.any_cache_dram cache Offcore RFO requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7F22  00     offcore_response.any_rfo.any_location cache All offcore RFO requests event=0xb7,period=100000,umask=1,offcore_rsp=0xFF22  00     offcore_response.any_rfo.io_csr_mmio cache Offcore RFO requests satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8022  00     offcore_response.any_rfo.llc_hit_no_other_core cache Offcore RFO requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x122  00     offcore_response.any_rfo.llc_hit_other_core_hit cache Offcore RFO requests satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x222  00     offcore_response.any_rfo.llc_hit_other_core_hitm cache Offcore RFO requests satisfied by the LLC  and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x422  00     offcore_response.any_rfo.local_cache cache Offcore RFO requests satisfied by the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x722  00     offcore_response.any_rfo.local_cache_dram cache Offcore RFO requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4722  00     offcore_response.any_rfo.remote_cache cache Offcore RFO requests satisfied by a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1822  00     offcore_response.any_rfo.remote_cache_dram cache Offcore RFO requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x3822  00     offcore_response.any_rfo.remote_cache_hit cache Offcore RFO requests that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1022  00     offcore_response.any_rfo.remote_cache_hitm cache Offcore RFO requests that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x822  00     offcore_response.corewb.any_cache_dram cache Offcore writebacks to any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7F08  00     offcore_response.corewb.any_location cache All offcore writebacks event=0xb7,period=100000,umask=1,offcore_rsp=0xFF08  00     offcore_response.corewb.io_csr_mmio cache Offcore writebacks to the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8008  00     offcore_response.corewb.llc_hit_no_other_core cache Offcore writebacks to the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x108  00     offcore_response.corewb.llc_hit_other_core_hitm cache Offcore writebacks to the LLC  and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x408  00     offcore_response.corewb.local_cache cache Offcore writebacks to the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x708  00     offcore_response.corewb.local_cache_dram cache Offcore writebacks to the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4708  00     offcore_response.corewb.remote_cache cache Offcore writebacks to a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1808  00     offcore_response.corewb.remote_cache_dram cache Offcore writebacks to a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x3808  00     offcore_response.corewb.remote_cache_hit cache Offcore writebacks that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1008  00     offcore_response.corewb.remote_cache_hitm cache Offcore writebacks that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x808  00     offcore_response.data_ifetch.any_cache_dram cache Offcore code or data read requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7F77  00     offcore_response.data_ifetch.any_location cache All offcore code or data read requests event=0xb7,period=100000,umask=1,offcore_rsp=0xFF77  00     offcore_response.data_ifetch.io_csr_mmio cache Offcore code or data read requests satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8077  00     offcore_response.data_ifetch.llc_hit_no_other_core cache Offcore code or data read requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x177  00     offcore_response.data_ifetch.llc_hit_other_core_hit cache Offcore code or data read requests satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x277  00     offcore_response.data_ifetch.llc_hit_other_core_hitm cache Offcore code or data read requests satisfied by the LLC  and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x477  00     offcore_response.data_ifetch.local_cache cache Offcore code or data read requests satisfied by the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x777  00     offcore_response.data_ifetch.local_cache_dram cache Offcore code or data read requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4777  00     offcore_response.data_ifetch.remote_cache cache Offcore code or data read requests satisfied by a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1877  00     offcore_response.data_ifetch.remote_cache_dram cache Offcore code or data read requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x3877  00     offcore_response.data_ifetch.remote_cache_hit cache Offcore code or data read requests that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1077  00     offcore_response.data_ifetch.remote_cache_hitm cache Offcore code or data read requests that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x877  00     offcore_response.data_in.any_cache_dram cache Offcore request = all data, response = any cache_dram event=0xb7,period=100000,umask=1,offcore_rsp=0x7F33  00     offcore_response.data_in.any_location cache Offcore request = all data, response = any location event=0xb7,period=100000,umask=1,offcore_rsp=0xFF33  00     offcore_response.data_in.io_csr_mmio cache Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8033  00     offcore_response.data_in.llc_hit_no_other_core cache Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x133  00     offcore_response.data_in.llc_hit_other_core_hit cache Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x233  00     offcore_response.data_in.llc_hit_other_core_hitm cache Offcore data reads, RFOs, and prefetches satisfied by the LLC  and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x433  00     offcore_response.data_in.local_cache cache Offcore request = all data, response = local cache event=0xb7,period=100000,umask=1,offcore_rsp=0x733  00     offcore_response.data_in.local_cache_dram cache Offcore request = all data, response = local cache or dram event=0xb7,period=100000,umask=1,offcore_rsp=0x4733  00     offcore_response.data_in.remote_cache cache Offcore request = all data, response = remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1833  00     offcore_response.data_in.remote_cache_dram cache Offcore request = all data, response = remote cache or dram event=0xb7,period=100000,umask=1,offcore_rsp=0x3833  00     offcore_response.data_in.remote_cache_hit cache Offcore data reads, RFOs, and prefetches that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1033  00     offcore_response.data_in.remote_cache_hitm cache Offcore data reads, RFOs, and prefetches that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x833  00     offcore_response.demand_data.any_cache_dram cache Offcore demand data requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7F03  00     offcore_response.demand_data.any_location cache All offcore demand data requests event=0xb7,period=100000,umask=1,offcore_rsp=0xFF03  00     offcore_response.demand_data.io_csr_mmio cache Offcore demand data requests satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8003  00     offcore_response.demand_data.llc_hit_no_other_core cache Offcore demand data requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x103  00     offcore_response.demand_data.llc_hit_other_core_hit cache Offcore demand data requests satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x203  00     offcore_response.demand_data.llc_hit_other_core_hitm cache Offcore demand data requests satisfied by the LLC  and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x403  00     offcore_response.demand_data.local_cache cache Offcore demand data requests satisfied by the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x703  00     offcore_response.demand_data.local_cache_dram cache Offcore demand data requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4703  00     offcore_response.demand_data.remote_cache cache Offcore demand data requests satisfied by a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1803  00     offcore_response.demand_data.remote_cache_dram cache Offcore demand data requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x3803  00     offcore_response.demand_data.remote_cache_hit cache Offcore demand data requests that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1003  00     offcore_response.demand_data.remote_cache_hitm cache Offcore demand data requests that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x803  00     offcore_response.demand_data_rd.any_cache_dram cache Offcore demand data reads satisfied by any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7F01  00     offcore_response.demand_data_rd.any_location cache All offcore demand data reads event=0xb7,period=100000,umask=1,offcore_rsp=0xFF01  00     offcore_response.demand_data_rd.io_csr_mmio cache Offcore demand data reads satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8001  00     offcore_response.demand_data_rd.llc_hit_no_other_core cache Offcore demand data reads satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x101  00     offcore_response.demand_data_rd.llc_hit_other_core_hit cache Offcore demand data reads satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x201  00     offcore_response.demand_data_rd.llc_hit_other_core_hitm cache Offcore demand data reads satisfied by the LLC  and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x401  00     offcore_response.demand_data_rd.local_cache cache Offcore demand data reads satisfied by the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x701  00     offcore_response.demand_data_rd.local_cache_dram cache Offcore demand data reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4701  00     offcore_response.demand_data_rd.remote_cache cache Offcore demand data reads satisfied by a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1801  00     offcore_response.demand_data_rd.remote_cache_dram cache Offcore demand data reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x3801  00     offcore_response.demand_data_rd.remote_cache_hit cache Offcore demand data reads that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1001  00     offcore_response.demand_data_rd.remote_cache_hitm cache Offcore demand data reads that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x801  00     offcore_response.demand_ifetch.any_cache_dram cache Offcore demand code reads satisfied by any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7F04  00     offcore_response.demand_ifetch.any_location cache All offcore demand code reads event=0xb7,period=100000,umask=1,offcore_rsp=0xFF04  00     offcore_response.demand_ifetch.io_csr_mmio cache Offcore demand code reads satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8004  00     offcore_response.demand_ifetch.llc_hit_no_other_core cache Offcore demand code reads satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x104  00     offcore_response.demand_ifetch.llc_hit_other_core_hit cache Offcore demand code reads satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x204  00     offcore_response.demand_ifetch.llc_hit_other_core_hitm cache Offcore demand code reads satisfied by the LLC  and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x404  00     offcore_response.demand_ifetch.local_cache cache Offcore demand code reads satisfied by the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x704  00     offcore_response.demand_ifetch.local_cache_dram cache Offcore demand code reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4704  00     offcore_response.demand_ifetch.remote_cache cache Offcore demand code reads satisfied by a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1804  00     offcore_response.demand_ifetch.remote_cache_dram cache Offcore demand code reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x3804  00     offcore_response.demand_ifetch.remote_cache_hit cache Offcore demand code reads that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1004  00     offcore_response.demand_ifetch.remote_cache_hitm cache Offcore demand code reads that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x804  00     offcore_response.demand_rfo.any_cache_dram cache Offcore demand RFO requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7F02  00     offcore_response.demand_rfo.any_location cache All offcore demand RFO requests event=0xb7,period=100000,umask=1,offcore_rsp=0xFF02  00     offcore_response.demand_rfo.io_csr_mmio cache Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8002  00     offcore_response.demand_rfo.llc_hit_no_other_core cache Offcore demand RFO requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x102  00     offcore_response.demand_rfo.llc_hit_other_core_hit cache Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x202  00     offcore_response.demand_rfo.llc_hit_other_core_hitm cache Offcore demand RFO requests satisfied by the LLC  and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x402  00     offcore_response.demand_rfo.local_cache cache Offcore demand RFO requests satisfied by the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x702  00     offcore_response.demand_rfo.local_cache_dram cache Offcore demand RFO requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4702  00     offcore_response.demand_rfo.remote_cache cache Offcore demand RFO requests satisfied by a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1802  00     offcore_response.demand_rfo.remote_cache_dram cache Offcore demand RFO requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x3802  00     offcore_response.demand_rfo.remote_cache_hit cache Offcore demand RFO requests that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1002  00     offcore_response.demand_rfo.remote_cache_hitm cache Offcore demand RFO requests that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x802  00     offcore_response.other.any_cache_dram cache Offcore other requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7F80  00     offcore_response.other.any_location cache All offcore other requests event=0xb7,period=100000,umask=1,offcore_rsp=0xFF80  00     offcore_response.other.io_csr_mmio cache Offcore other requests satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8080  00     offcore_response.other.llc_hit_no_other_core cache Offcore other requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x180  00     offcore_response.other.llc_hit_other_core_hit cache Offcore other requests satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x280  00     offcore_response.other.llc_hit_other_core_hitm cache Offcore other requests satisfied by the LLC  and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x480  00     offcore_response.other.local_cache cache Offcore other requests satisfied by the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x780  00     offcore_response.other.local_cache_dram cache Offcore other requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4780  00     offcore_response.other.remote_cache cache Offcore other requests satisfied by a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1880  00     offcore_response.other.remote_cache_dram cache Offcore other requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x3880  00     offcore_response.other.remote_cache_hit cache Offcore other requests that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1080  00     offcore_response.other.remote_cache_hitm cache Offcore other requests that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x880  00     offcore_response.pf_data.any_cache_dram cache Offcore prefetch data requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7F30  00     offcore_response.pf_data.any_location cache All offcore prefetch data requests event=0xb7,period=100000,umask=1,offcore_rsp=0xFF30  00     offcore_response.pf_data.io_csr_mmio cache Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8030  00     offcore_response.pf_data.llc_hit_no_other_core cache Offcore prefetch data requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x130  00     offcore_response.pf_data.llc_hit_other_core_hit cache Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x230  00     offcore_response.pf_data.llc_hit_other_core_hitm cache Offcore prefetch data requests satisfied by the LLC  and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x430  00     offcore_response.pf_data.local_cache cache Offcore prefetch data requests satisfied by the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x730  00     offcore_response.pf_data.local_cache_dram cache Offcore prefetch data requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4730  00     offcore_response.pf_data.remote_cache cache Offcore prefetch data requests satisfied by a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1830  00     offcore_response.pf_data.remote_cache_dram cache Offcore prefetch data requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x3830  00     offcore_response.pf_data.remote_cache_hit cache Offcore prefetch data requests that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1030  00     offcore_response.pf_data.remote_cache_hitm cache Offcore prefetch data requests that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x830  00     offcore_response.pf_data_rd.any_cache_dram cache Offcore prefetch data reads satisfied by any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7F10  00     offcore_response.pf_data_rd.any_location cache All offcore prefetch data reads event=0xb7,period=100000,umask=1,offcore_rsp=0xFF10  00     offcore_response.pf_data_rd.io_csr_mmio cache Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8010  00     offcore_response.pf_data_rd.llc_hit_no_other_core cache Offcore prefetch data reads satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x110  00     offcore_response.pf_data_rd.llc_hit_other_core_hit cache Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x210  00     offcore_response.pf_data_rd.llc_hit_other_core_hitm cache Offcore prefetch data reads satisfied by the LLC  and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x410  00     offcore_response.pf_data_rd.local_cache cache Offcore prefetch data reads satisfied by the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x710  00     offcore_response.pf_data_rd.local_cache_dram cache Offcore prefetch data reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4710  00     offcore_response.pf_data_rd.remote_cache cache Offcore prefetch data reads satisfied by a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1810  00     offcore_response.pf_data_rd.remote_cache_dram cache Offcore prefetch data reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x3810  00     offcore_response.pf_data_rd.remote_cache_hit cache Offcore prefetch data reads that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1010  00     offcore_response.pf_data_rd.remote_cache_hitm cache Offcore prefetch data reads that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x810  00     offcore_response.pf_ifetch.any_cache_dram cache Offcore prefetch code reads satisfied by any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7F40  00     offcore_response.pf_ifetch.any_location cache All offcore prefetch code reads event=0xb7,period=100000,umask=1,offcore_rsp=0xFF40  00     offcore_response.pf_ifetch.io_csr_mmio cache Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8040  00     offcore_response.pf_ifetch.llc_hit_no_other_core cache Offcore prefetch code reads satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x140  00     offcore_response.pf_ifetch.llc_hit_other_core_hit cache Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x240  00     offcore_response.pf_ifetch.llc_hit_other_core_hitm cache Offcore prefetch code reads satisfied by the LLC  and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x440  00     offcore_response.pf_ifetch.local_cache cache Offcore prefetch code reads satisfied by the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x740  00     offcore_response.pf_ifetch.local_cache_dram cache Offcore prefetch code reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4740  00     offcore_response.pf_ifetch.remote_cache cache Offcore prefetch code reads satisfied by a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1840  00     offcore_response.pf_ifetch.remote_cache_dram cache Offcore prefetch code reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x3840  00     offcore_response.pf_ifetch.remote_cache_hit cache Offcore prefetch code reads that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1040  00     offcore_response.pf_ifetch.remote_cache_hitm cache Offcore prefetch code reads that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x840  00     offcore_response.pf_rfo.any_cache_dram cache Offcore prefetch RFO requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7F20  00     offcore_response.pf_rfo.any_location cache All offcore prefetch RFO requests event=0xb7,period=100000,umask=1,offcore_rsp=0xFF20  00     offcore_response.pf_rfo.io_csr_mmio cache Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8020  00     offcore_response.pf_rfo.llc_hit_no_other_core cache Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x120  00     offcore_response.pf_rfo.llc_hit_other_core_hit cache Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x220  00     offcore_response.pf_rfo.llc_hit_other_core_hitm cache Offcore prefetch RFO requests satisfied by the LLC  and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x420  00     offcore_response.pf_rfo.local_cache cache Offcore prefetch RFO requests satisfied by the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x720  00     offcore_response.pf_rfo.local_cache_dram cache Offcore prefetch RFO requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4720  00     offcore_response.pf_rfo.remote_cache cache Offcore prefetch RFO requests satisfied by a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1820  00     offcore_response.pf_rfo.remote_cache_dram cache Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x3820  00     offcore_response.pf_rfo.remote_cache_hit cache Offcore prefetch RFO requests that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1020  00     offcore_response.pf_rfo.remote_cache_hitm cache Offcore prefetch RFO requests that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x820  00     offcore_response.prefetch.any_cache_dram cache Offcore prefetch requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7F70  00     offcore_response.prefetch.any_location cache All offcore prefetch requests event=0xb7,period=100000,umask=1,offcore_rsp=0xFF70  00     offcore_response.prefetch.io_csr_mmio cache Offcore prefetch requests satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8070  00     offcore_response.prefetch.llc_hit_no_other_core cache Offcore prefetch requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x170  00     offcore_response.prefetch.llc_hit_other_core_hit cache Offcore prefetch requests satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x270  00     offcore_response.prefetch.llc_hit_other_core_hitm cache Offcore prefetch requests satisfied by the LLC  and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x470  00     offcore_response.prefetch.local_cache cache Offcore prefetch requests satisfied by the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x770  00     offcore_response.prefetch.local_cache_dram cache Offcore prefetch requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4770  00     offcore_response.prefetch.remote_cache cache Offcore prefetch requests satisfied by a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1870  00     offcore_response.prefetch.remote_cache_dram cache Offcore prefetch requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x3870  00     offcore_response.prefetch.remote_cache_hit cache Offcore prefetch requests that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1070  00     offcore_response.prefetch.remote_cache_hitm cache Offcore prefetch requests that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x870  00     sq_misc.split_lock cache Super Queue lock splits across a cache line event=0xf4,period=2000000,umask=0x10  00     store_blocks.at_ret cache Loads delayed with at-Retirement block code event=6,period=200000,umask=4  00     store_blocks.l1d_block cache Cacheable loads delayed with L1D block code event=6,period=200000,umask=8  00     fp_assist.all floating point X87 Floating point assists (Precise Event) event=0xf7,period=20000,umask=1  00     fp_assist.input floating point X87 Floating point assists for invalid input value (Precise Event) event=0xf7,period=20000,umask=4  00     fp_assist.output floating point X87 Floating point assists for invalid output value (Precise Event) event=0xf7,period=20000,umask=2  00     fp_comp_ops_exe.mmx floating point MMX Uops event=0x10,period=2000000,umask=2  00     fp_comp_ops_exe.sse2_integer floating point SSE2 integer Uops event=0x10,period=2000000,umask=8  00     fp_comp_ops_exe.sse_double_precision floating point SSE* FP double precision Uops event=0x10,period=2000000,umask=0x80  00     fp_comp_ops_exe.sse_fp floating point SSE and SSE2 FP Uops event=0x10,period=2000000,umask=4  00     fp_comp_ops_exe.sse_fp_packed floating point SSE FP packed Uops event=0x10,period=2000000,umask=0x10  00     fp_comp_ops_exe.sse_fp_scalar floating point SSE FP scalar Uops event=0x10,period=2000000,umask=0x20  00     fp_comp_ops_exe.sse_single_precision floating point SSE* FP single precision Uops event=0x10,period=2000000,umask=0x40  00     fp_comp_ops_exe.x87 floating point Computational floating-point operations executed event=0x10,period=2000000,umask=1  00     fp_mmx_trans.any floating point All Floating Point to and from MMX transitions event=0xcc,period=2000000,umask=3  00     fp_mmx_trans.to_fp floating point Transitions from MMX to Floating Point instructions event=0xcc,period=2000000,umask=1  00     fp_mmx_trans.to_mmx floating point Transitions from Floating Point to MMX instructions event=0xcc,period=2000000,umask=2  00     simd_int_128.pack floating point 128 bit SIMD integer pack operations event=0x12,period=200000,umask=4  00     simd_int_128.packed_arith floating point 128 bit SIMD integer arithmetic operations event=0x12,period=200000,umask=0x20  00     simd_int_128.packed_logical floating point 128 bit SIMD integer logical operations event=0x12,period=200000,umask=0x10  00     simd_int_128.packed_mpy floating point 128 bit SIMD integer multiply operations event=0x12,period=200000,umask=1  00     simd_int_128.packed_shift floating point 128 bit SIMD integer shift operations event=0x12,period=200000,umask=2  00     simd_int_128.shuffle_move floating point 128 bit SIMD integer shuffle/move operations event=0x12,period=200000,umask=0x40  00     simd_int_128.unpack floating point 128 bit SIMD integer unpack operations event=0x12,period=200000,umask=8  00     simd_int_64.pack floating point SIMD integer 64 bit pack operations event=0xfd,period=200000,umask=4  00     simd_int_64.packed_arith floating point SIMD integer 64 bit arithmetic operations event=0xfd,period=200000,umask=0x20  00     simd_int_64.packed_logical floating point SIMD integer 64 bit logical operations event=0xfd,period=200000,umask=0x10  00     simd_int_64.packed_mpy floating point SIMD integer 64 bit packed multiply operations event=0xfd,period=200000,umask=1  00     simd_int_64.packed_shift floating point SIMD integer 64 bit shift operations event=0xfd,period=200000,umask=2  00     simd_int_64.shuffle_move floating point SIMD integer 64 bit shuffle/move operations event=0xfd,period=200000,umask=0x40  00     simd_int_64.unpack floating point SIMD integer 64 bit unpack operations event=0xfd,period=200000,umask=8  00     macro_insts.decoded frontend Instructions decoded event=0xd0,period=2000000,umask=1  00     macro_insts.fusions_decoded frontend Macro-fused instructions decoded event=0xa6,period=2000000,umask=1  00     two_uop_insts_decoded frontend Two Uop instructions decoded event=0x19,period=2000000,umask=1  00     offcore_response.any_data.any_dram memory Offcore data reads satisfied by any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6011  00     offcore_response.any_data.any_llc_miss memory Offcore data reads that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF811  00     offcore_response.any_data.local_dram memory Offcore data reads satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4011  00     offcore_response.any_data.remote_dram memory Offcore data reads satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2011  00     offcore_response.any_ifetch.any_dram memory Offcore code reads satisfied by any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6044  00     offcore_response.any_ifetch.any_llc_miss memory Offcore code reads that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF844  00     offcore_response.any_ifetch.local_dram memory Offcore code reads satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4044  00     offcore_response.any_ifetch.remote_dram memory Offcore code reads satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2044  00     offcore_response.any_request.any_dram memory Offcore requests satisfied by any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x60FF  00     offcore_response.any_request.any_llc_miss memory Offcore requests that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF8FF  00     offcore_response.any_request.local_dram memory Offcore requests satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x40FF  00     offcore_response.any_request.remote_dram memory Offcore requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x20FF  00     offcore_response.any_rfo.any_dram memory Offcore RFO requests satisfied by any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6022  00     offcore_response.any_rfo.any_llc_miss memory Offcore RFO requests that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF822  00     offcore_response.any_rfo.local_dram memory Offcore RFO requests satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4022  00     offcore_response.any_rfo.remote_dram memory Offcore RFO requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2022  00     offcore_response.corewb.any_dram memory Offcore writebacks to any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6008  00     offcore_response.corewb.any_llc_miss memory Offcore writebacks that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF808  00     offcore_response.corewb.local_dram memory Offcore writebacks to the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4008  00     offcore_response.corewb.remote_dram memory Offcore writebacks to a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2008  00     offcore_response.data_ifetch.any_dram memory Offcore code or data read requests satisfied by any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6077  00     offcore_response.data_ifetch.any_llc_miss memory Offcore code or data read requests that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF877  00     offcore_response.data_ifetch.local_dram memory Offcore code or data read requests satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4077  00     offcore_response.data_ifetch.remote_dram memory Offcore code or data read requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2077  00     offcore_response.data_in.any_dram memory Offcore request = all data, response = any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6033  00     offcore_response.data_in.any_llc_miss memory Offcore request = all data, response = any LLC miss event=0xb7,period=100000,umask=1,offcore_rsp=0xF833  00     offcore_response.data_in.local_dram memory Offcore data reads, RFOs, and prefetches satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4033  00     offcore_response.data_in.remote_dram memory Offcore data reads, RFOs, and prefetches satisfied by the remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2033  00     offcore_response.demand_data.any_dram memory Offcore demand data requests satisfied by any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6003  00     offcore_response.demand_data.any_llc_miss memory Offcore demand data requests that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF803  00     offcore_response.demand_data.local_dram memory Offcore demand data requests satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4003  00     offcore_response.demand_data.remote_dram memory Offcore demand data requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2003  00     offcore_response.demand_data_rd.any_dram memory Offcore demand data reads satisfied by any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6001  00     offcore_response.demand_data_rd.any_llc_miss memory Offcore demand data reads that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF801  00     offcore_response.demand_data_rd.local_dram memory Offcore demand data reads satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4001  00     offcore_response.demand_data_rd.remote_dram memory Offcore demand data reads satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2001  00     offcore_response.demand_ifetch.any_dram memory Offcore demand code reads satisfied by any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6004  00     offcore_response.demand_ifetch.any_llc_miss memory Offcore demand code reads that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF804  00     offcore_response.demand_ifetch.local_dram memory Offcore demand code reads satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4004  00     offcore_response.demand_ifetch.remote_dram memory Offcore demand code reads satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2004  00     offcore_response.demand_rfo.any_dram memory Offcore demand RFO requests satisfied by any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6002  00     offcore_response.demand_rfo.any_llc_miss memory Offcore demand RFO requests that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF802  00     offcore_response.demand_rfo.local_dram memory Offcore demand RFO requests satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4002  00     offcore_response.demand_rfo.remote_dram memory Offcore demand RFO requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2002  00     offcore_response.other.any_dram memory Offcore other requests satisfied by any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6080  00     offcore_response.other.any_llc_miss memory Offcore other requests that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF880  00     offcore_response.other.remote_dram memory Offcore other requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2080  00     offcore_response.pf_data.any_dram memory Offcore prefetch data requests satisfied by any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6030  00     offcore_response.pf_data.any_llc_miss memory Offcore prefetch data requests that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF830  00     offcore_response.pf_data.local_dram memory Offcore prefetch data requests satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4030  00     offcore_response.pf_data.remote_dram memory Offcore prefetch data requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2030  00     offcore_response.pf_data_rd.any_dram memory Offcore prefetch data reads satisfied by any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6010  00     offcore_response.pf_data_rd.any_llc_miss memory Offcore prefetch data reads that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF810  00     offcore_response.pf_data_rd.local_dram memory Offcore prefetch data reads satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4010  00     offcore_response.pf_data_rd.remote_dram memory Offcore prefetch data reads satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2010  00     offcore_response.pf_ifetch.any_dram memory Offcore prefetch code reads satisfied by any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6040  00     offcore_response.pf_ifetch.any_llc_miss memory Offcore prefetch code reads that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF840  00     offcore_response.pf_ifetch.local_dram memory Offcore prefetch code reads satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4040  00     offcore_response.pf_ifetch.remote_dram memory Offcore prefetch code reads satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2040  00     offcore_response.pf_rfo.any_dram memory Offcore prefetch RFO requests satisfied by any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6020  00     offcore_response.pf_rfo.any_llc_miss memory Offcore prefetch RFO requests that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF820  00     offcore_response.pf_rfo.local_dram memory Offcore prefetch RFO requests satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4020  00     offcore_response.pf_rfo.remote_dram memory Offcore prefetch RFO requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2020  00     offcore_response.prefetch.any_dram memory Offcore prefetch requests satisfied by any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6070  00     offcore_response.prefetch.any_llc_miss memory Offcore prefetch requests that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF870  00     offcore_response.prefetch.local_dram memory Offcore prefetch requests satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4070  00     offcore_response.prefetch.remote_dram memory Offcore prefetch requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2070  00     es_reg_renames other ES segment renames event=0xd5,period=2000000,umask=1  00     io_transactions other I/O transactions event=0x6c,period=2000000,umask=1  00     load_dispatch.any other All loads dispatched event=0x13,period=2000000,umask=7  00     load_dispatch.mob other Loads dispatched from the MOB event=0x13,period=2000000,umask=4  00     load_dispatch.rs other Loads dispatched that bypass the MOB event=0x13,period=2000000,umask=1  00     load_dispatch.rs_delayed other Loads dispatched from stage 305 event=0x13,period=2000000,umask=2  00     partial_address_alias other False dependencies due to partial address aliasing event=7,period=200000,umask=1  00     sb_drain.any other All Store buffer stall cycles event=4,period=200000,umask=7  00     seg_rename_stalls other Segment rename stall cycles event=0xd4,period=2000000,umask=1  00     snoop_response.hit other Thread responded HIT to snoop event=0xb8,period=100000,umask=1  00     snoop_response.hite other Thread responded HITE to snoop event=0xb8,period=100000,umask=2  00     snoop_response.hitm other Thread responded HITM to snoop event=0xb8,period=100000,umask=4  00     sq_full_stall_cycles other Super Queue full stall cycles event=0xf6,period=2000000,umask=1  00     arith.cycles_div_busy pipeline Cycles the divider is busy event=0x14,period=2000000,umask=1  00     arith.div pipeline Divide Operations executed event=0x14,cmask=1,edge=1,inv=1,period=2000000,umask=1  00     arith.mul pipeline Multiply operations executed event=0x14,period=2000000,umask=2  00     baclear.bad_target pipeline BACLEAR asserted with bad target address event=0xe6,period=2000000,umask=2  00     baclear.clear pipeline BACLEAR asserted, regardless of cause event=0xe6,period=2000000,umask=1  00     baclear_force_iq pipeline Instruction queue forced BACLEAR event=0xa7,period=2000000,umask=1  00     bpu_clears.early pipeline Early Branch Prediciton Unit clears event=0xe8,period=2000000,umask=1  00     bpu_clears.late pipeline Late Branch Prediction Unit clears event=0xe8,period=2000000,umask=2  00     bpu_missed_call_ret pipeline Branch prediction unit missed call or return event=0xe5,period=2000000,umask=1  00     br_inst_exec.any pipeline Branch instructions executed event=0x88,period=200000,umask=0x7f  00     br_inst_exec.cond pipeline Conditional branch instructions executed event=0x88,period=200000,umask=1  00     br_inst_exec.direct pipeline Unconditional branches executed event=0x88,period=200000,umask=2  00     br_inst_exec.direct_near_call pipeline Unconditional call branches executed event=0x88,period=20000,umask=0x10  00     br_inst_exec.indirect_near_call pipeline Indirect call branches executed event=0x88,period=20000,umask=0x20  00     br_inst_exec.indirect_non_call pipeline Indirect non call branches executed event=0x88,period=20000,umask=4  00     br_inst_exec.near_calls pipeline Call branches executed event=0x88,period=20000,umask=0x30  00     br_inst_exec.non_calls pipeline All non call branches executed event=0x88,period=200000,umask=7  00     br_inst_exec.return_near pipeline Indirect return branches executed event=0x88,period=20000,umask=8  00     br_inst_exec.taken pipeline Taken branches executed event=0x88,period=200000,umask=0x40  00     br_inst_retired.all_branches pipeline Retired branch instructions (Precise Event) event=0xc4,period=200000,umask=4  00     br_inst_retired.conditional pipeline Retired conditional branch instructions (Precise Event) event=0xc4,period=200000,umask=1  00     br_inst_retired.near_call pipeline Retired near call instructions (Precise Event) event=0xc4,period=20000,umask=2  00     br_misp_exec.any pipeline Mispredicted branches executed event=0x89,period=20000,umask=0x7f  00     br_misp_exec.cond pipeline Mispredicted conditional branches executed event=0x89,period=20000,umask=1  00     br_misp_exec.direct pipeline Mispredicted unconditional branches executed event=0x89,period=20000,umask=2  00     br_misp_exec.direct_near_call pipeline Mispredicted non call branches executed event=0x89,period=2000,umask=0x10  00     br_misp_exec.indirect_near_call pipeline Mispredicted indirect call branches executed event=0x89,period=2000,umask=0x20  00     br_misp_exec.indirect_non_call pipeline Mispredicted indirect non call branches executed event=0x89,period=2000,umask=4  00     br_misp_exec.near_calls pipeline Mispredicted call branches executed event=0x89,period=2000,umask=0x30  00     br_misp_exec.non_calls pipeline Mispredicted non call branches executed event=0x89,period=20000,umask=7  00     br_misp_exec.return_near pipeline Mispredicted return branches executed event=0x89,period=2000,umask=8  00     br_misp_exec.taken pipeline Mispredicted taken branches executed event=0x89,period=20000,umask=0x40  00     br_misp_retired.near_call pipeline Mispredicted near retired calls (Precise Event) event=0xc5,period=2000,umask=2  00     cpu_clk_unhalted.ref pipeline Reference cycles when thread is not halted (fixed counter) event=0x0,umask=0x03,period=2000003  00     cpu_clk_unhalted.ref_p pipeline Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter) event=0x3c,period=100000,umask=1  00     cpu_clk_unhalted.thread pipeline Cycles when thread is not halted (fixed counter) event=0x3c,period=2000003  00     cpu_clk_unhalted.thread_p pipeline Cycles when thread is not halted (programmable counter) event=0x3c,period=2000000  00     cpu_clk_unhalted.total_cycles pipeline Total CPU cycles event=0x3c,cmask=2,inv=1,period=2000000  00     ild_stall.any pipeline Any Instruction Length Decoder stall cycles event=0x87,period=2000000,umask=0xf  00     ild_stall.iq_full pipeline Instruction Queue full stall cycles event=0x87,period=2000000,umask=4  00     ild_stall.lcp pipeline Length Change Prefix stall cycles event=0x87,period=2000000,umask=1  00     ild_stall.mru pipeline Stall cycles due to BPU MRU bypass event=0x87,period=2000000,umask=2  00     ild_stall.regen pipeline Regen stall cycles event=0x87,period=2000000,umask=8  00     inst_decoded.dec0 pipeline Instructions that must be decoded by decoder 0 event=0x18,period=2000000,umask=1  00     inst_queue_writes pipeline Instructions written to instruction queue event=0x17,period=2000000,umask=1  00     inst_queue_write_cycles pipeline Cycles instructions are written to the instruction queue event=0x1e,period=2000000,umask=1  00     inst_retired.any pipeline Instructions retired (fixed counter) event=0xc0,period=2000003  00     inst_retired.any_p pipeline Instructions retired (Programmable counter and Precise Event) (Precise event) event=0xc0,period=2000003  00     inst_retired.mmx pipeline Retired MMX instructions (Precise Event) event=0xc0,period=2000000,umask=4  00     inst_retired.total_cycles pipeline Total cycles (Precise Event) event=0xc0,cmask=16,inv=1,period=2000000,umask=1  00     inst_retired.total_cycles_ps pipeline Total cycles (Precise Event) event=0xc0,cmask=16,inv=1,period=2000000,umask=1  00     inst_retired.x87 pipeline Retired floating-point operations (Precise Event) event=0xc0,period=2000000,umask=2  00     load_hit_pre pipeline Load operations conflicting with software prefetches event=0x4c,period=200000,umask=1  00     lsd.active pipeline Cycles when uops were delivered by the LSD event=0xa8,cmask=1,period=2000000,umask=1  00     lsd.inactive pipeline Cycles no uops were delivered by the LSD event=0xa8,cmask=1,inv=1,period=2000000,umask=1  00     lsd_overflow pipeline Loops that can't stream from the instruction queue event=0x20,period=2000000,umask=1  00     machine_clears.cycles pipeline Cycles machine clear asserted event=0xc3,period=20000,umask=1  00     machine_clears.mem_order pipeline Execution pipeline restart due to Memory ordering conflicts event=0xc3,period=20000,umask=2  00     machine_clears.smc pipeline Self-Modifying Code detected event=0xc3,period=20000,umask=4  00     rat_stalls.any pipeline All RAT stall cycles event=0xd2,period=2000000,umask=0xf  00     rat_stalls.flags pipeline Flag stall cycles event=0xd2,period=2000000,umask=1  00     rat_stalls.registers pipeline Partial register stall cycles event=0xd2,period=2000000,umask=2  00     rat_stalls.rob_read_port pipeline ROB read port stalls cycles event=0xd2,period=2000000,umask=4  00     rat_stalls.scoreboard pipeline Scoreboard stall cycles event=0xd2,period=2000000,umask=8  00     resource_stalls.any pipeline Resource related stall cycles event=0xa2,period=2000000,umask=1  00     resource_stalls.fpcw pipeline FPU control word write stall cycles event=0xa2,period=2000000,umask=0x20  00     resource_stalls.load pipeline Load buffer stall cycles event=0xa2,period=2000000,umask=2  00     resource_stalls.mxcsr pipeline MXCSR rename stall cycles event=0xa2,period=2000000,umask=0x40  00     resource_stalls.other pipeline Other Resource related stall cycles event=0xa2,period=2000000,umask=0x80  00     resource_stalls.rob_full pipeline ROB full stall cycles event=0xa2,period=2000000,umask=0x10  00     resource_stalls.rs_full pipeline Reservation Station full stall cycles event=0xa2,period=2000000,umask=4  00     resource_stalls.store pipeline Store buffer stall cycles event=0xa2,period=2000000,umask=8  00     ssex_uops_retired.packed_double pipeline SIMD Packed-Double Uops retired (Precise Event) event=0xc7,period=200000,umask=4  00     ssex_uops_retired.packed_single pipeline SIMD Packed-Single Uops retired (Precise Event) event=0xc7,period=200000,umask=1  00     ssex_uops_retired.scalar_double pipeline SIMD Scalar-Double Uops retired (Precise Event) event=0xc7,period=200000,umask=8  00     ssex_uops_retired.scalar_single pipeline SIMD Scalar-Single Uops retired (Precise Event) event=0xc7,period=200000,umask=2  00     ssex_uops_retired.vector_integer pipeline SIMD Vector Integer Uops retired (Precise Event) event=0xc7,period=200000,umask=0x10  00     uops_decoded.esp_folding pipeline Stack pointer instructions decoded event=0xd1,period=2000000,umask=4  00     uops_decoded.esp_sync pipeline Stack pointer sync operations event=0xd1,period=2000000,umask=8  00     uops_decoded.ms_cycles_active pipeline Uops decoded by Microcode Sequencer event=0xd1,cmask=1,period=2000000,umask=2  00     uops_decoded.stall_cycles pipeline Cycles no Uops are decoded event=0xd1,cmask=1,inv=1,period=2000000,umask=1  00     uops_executed.core_active_cycles pipeline Cycles Uops executed on any port (core count) event=0xb1,any=1,cmask=1,period=2000000,umask=0x3f  00     uops_executed.core_active_cycles_no_port5 pipeline Cycles Uops executed on ports 0-4 (core count) event=0xb1,any=1,cmask=1,period=2000000,umask=0x1f  00     uops_executed.core_stall_count pipeline Uops executed on any port (core count) event=0xb1,any=1,cmask=1,edge=1,inv=1,period=2000000,umask=0x3f  00     uops_executed.core_stall_count_no_port5 pipeline Uops executed on ports 0-4 (core count) event=0xb1,any=1,cmask=1,edge=1,inv=1,period=2000000,umask=0x1f  00     uops_executed.core_stall_cycles pipeline Cycles no Uops issued on any port (core count) event=0xb1,any=1,cmask=1,inv=1,period=2000000,umask=0x3f  00     uops_executed.core_stall_cycles_no_port5 pipeline Cycles no Uops issued on ports 0-4 (core count) event=0xb1,any=1,cmask=1,inv=1,period=2000000,umask=0x1f  00     uops_executed.port0 pipeline Uops executed on port 0 event=0xb1,period=2000000,umask=1  00     uops_executed.port015 pipeline Uops issued on ports 0, 1 or 5 event=0xb1,period=2000000,umask=0x40  00     uops_executed.port015_stall_cycles pipeline Cycles no Uops issued on ports 0, 1 or 5 event=0xb1,cmask=1,inv=1,period=2000000,umask=0x40  00     uops_executed.port1 pipeline Uops executed on port 1 event=0xb1,period=2000000,umask=2  00     uops_executed.port234_core pipeline Uops issued on ports 2, 3 or 4 event=0xb1,any=1,period=2000000,umask=0x80  00     uops_executed.port2_core pipeline Uops executed on port 2 (core count) event=0xb1,any=1,period=2000000,umask=4  00     uops_executed.port3_core pipeline Uops executed on port 3 (core count) event=0xb1,any=1,period=2000000,umask=8  00     uops_executed.port4_core pipeline Uops executed on port 4 (core count) event=0xb1,any=1,period=2000000,umask=0x10  00     uops_executed.port5 pipeline Uops executed on port 5 event=0xb1,period=2000000,umask=0x20  00     uops_issued.any pipeline Uops issued event=0xe,period=2000000,umask=1  00     uops_issued.core_stall_cycles pipeline Cycles no Uops were issued on any thread event=0xe,any=1,cmask=1,inv=1,period=2000000,umask=1  00     uops_issued.cycles_all_threads pipeline Cycles Uops were issued on either thread event=0xe,any=1,cmask=1,period=2000000,umask=1  00     uops_issued.fused pipeline Fused Uops issued event=0xe,period=2000000,umask=2  00     uops_issued.stall_cycles pipeline Cycles no Uops were issued event=0xe,cmask=1,inv=1,period=2000000,umask=1  00     uops_retired.active_cycles pipeline Cycles Uops are being retired (Precise event) event=0xc2,cmask=1,period=2000000,umask=1  00     uops_retired.any pipeline Uops retired (Precise Event) event=0xc2,period=2000000,umask=1  00     uops_retired.macro_fused pipeline Macro-fused Uops retired (Precise Event) event=0xc2,period=2000000,umask=4  00     uops_retired.retire_slots pipeline Retirement slots used (Precise Event) event=0xc2,period=2000000,umask=2  00     uops_retired.stall_cycles pipeline Cycles Uops are not retiring (Precise Event) event=0xc2,cmask=1,inv=1,period=2000000,umask=1  00     uops_retired.total_cycles pipeline Total cycles using precise uop retired event (Precise Event) event=0xc2,cmask=16,inv=1,period=2000000,umask=1  00     uop_unfusion pipeline Uop unfusions due to FP exceptions event=0xdb,period=2000000,umask=1  00     dtlb_load_misses.any virtual memory DTLB load misses event=8,period=200000,umask=1  00     dtlb_load_misses.pde_miss virtual memory DTLB load miss caused by low part of address event=8,period=200000,umask=0x20  00     dtlb_load_misses.stlb_hit virtual memory DTLB second level hit event=8,period=2000000,umask=0x10  00     dtlb_load_misses.walk_completed virtual memory DTLB load miss page walks complete event=8,period=200000,umask=2  00     dtlb_misses.any virtual memory DTLB misses event=0x49,period=200000,umask=1  00     dtlb_misses.stlb_hit virtual memory DTLB first level misses but second level hit event=0x49,period=200000,umask=0x10  00     dtlb_misses.walk_completed virtual memory DTLB miss page walks event=0x49,period=200000,umask=2  00     itlb_flush virtual memory ITLB flushes event=0xae,period=2000000,umask=1  00     itlb_misses.any virtual memory ITLB miss event=0x85,period=200000,umask=1  00     itlb_misses.walk_completed virtual memory ITLB miss page walks event=0x85,period=200000,umask=2  00     itlb_miss_retired virtual memory Retired instructions that missed the ITLB (Precise Event) event=0xc8,period=200000,umask=0x20  00     large_itlb.hit virtual memory Large ITLB hit event=0x82,period=200000,umask=1  00     mem_load_retired.dtlb_miss virtual memory Retired loads that miss the DTLB (Precise Event) event=0xcb,period=200000,umask=0x80  00     mem_store_retired.dtlb_miss virtual memory Retired stores that miss the DTLB (Precise Event) event=0xc,period=200000,umask=1  00     l2_request.all cache Counts the number of L2 cache accesses from front door requests for Code Read, Data Read, RFO, ITOM, and L2 Prefetches. Does not include rejects or recycles, per core event event=0x24,period=1000003,umask=0x1ff  00     l2_request.hit cache Counts the number of L2 cache accesses from front door requests that resulted in a Hit. Does not include rejects or recycles, per core event event=0x24,period=1000003,umask=0x1bf  00     mem_bound_stalls_load.l2_miss cache Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache event=0x34,period=1000003,umask=0x7e  00     mem_bound_stalls_load.llc_miss cache Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the local caches event=0x34,period=1000003,umask=0x38  00     mem_bound_stalls_load.llc_miss_localmem cache Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the caches.  DRAM, MMIO or other LOCAL memory type provides the data event=0x34,period=1000003,umask=0x10  00     mem_bound_stalls_load.llc_miss_othermod cache Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the caches, a snoop was required, and hits in other core or module on same die.  Another core provides the data with a fwd, no fwd, or hitM event=0x34,period=1000003,umask=8  00     mem_inst_retired.stlb_miss_any cache Retired instructions that miss the STLB  Supports address when precise event=0xd0,period=100003,umask=0x17  00    Number of retired instructions that (start a) miss in the 2nd-level TLB (STLB). Available PDIST counters: 0,1  Supports address when precise mem_load_uops_l3_miss_retired.local_dram cache Counts the number of load ops retired that miss the L3 cache and hit in DRAM event=0xd3,period=1000003,umask=1  00    Counts the number of load ops retired that miss the L3 cache and hit in DRAM Available PDIST counters: 0,1 mem_load_uops_l3_miss_retired.memside_cache cache Counts the number of load ops retired that miss the L3 cache and hit in memside cache event=0xd3,period=1000003,umask=0x40  00    Counts the number of load ops retired that miss the L3 cache and hit in memside cache. Available PDIST counters: 0,1 mem_load_uops_misc_retired.l3_hit_snoop_hitm cache Counts the number of load ops retired that hit in the L3 cache in which a snoop was required and modified data was forwarded event=0xd4,period=1000003,umask=8  00    Counts the number of load ops retired that hit in the L3 cache in which a snoop was required and modified data was forwarded. Available PDIST counters: 0,1 mem_load_uops_retired.l1_hit cache Counts the number of load ops retired that hit the L1 data cache event=0xd1,period=1000003,umask=1  00    Counts the number of load ops retired that hit the L1 data cache. Available PDIST counters: 0,1 mem_load_uops_retired.l1_miss cache Counts the number of load ops retired that miss in the L1 data cache event=0xd1,period=1000003,umask=0x40  00    Counts the number of load ops retired that miss in the L1 data cache. Available PDIST counters: 0,1 mem_load_uops_retired.l2_hit cache Counts the number of load ops retired that hit in the L2 cache event=0xd1,period=1000003,umask=2  00    Counts the number of load ops retired that hit in the L2 cache. Available PDIST counters: 0,1 mem_load_uops_retired.l2_miss cache Counts the number of load ops retired that miss in the L2 cache event=0xd1,period=1000003,umask=0x80  00    Counts the number of load ops retired that miss in the L2 cache. Available PDIST counters: 0,1 mem_load_uops_retired.l3_hit cache Counts the number of load ops retired that hit in the L3 cache event=0xd1,period=1000003,umask=0x1c  00    Counts the number of load ops retired that hit in the L3 cache. Available PDIST counters: 0,1 mem_scheduler_block.ld_buf cache Counts the number of cycles that uops are blocked due to a load buffer full condition event=4,period=1000003,umask=2  00     mem_scheduler_block.rsv cache Counts the number of cycles that uops are blocked due to an RSV full condition event=4,period=1000003,umask=4  00     mem_scheduler_block.st_buf cache Counts the number of cycles that uops are blocked due to a store buffer full condition event=4,period=1000003,umask=1  00     mem_uops_retired.all cache Counts the number of memory uops retired.  A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST) event=0xd0,period=1000003,umask=0x83  00    Counts the number of memory uops retired.  A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST). Available PDIST counters: 0,1 mem_uops_retired.lock_loads cache Counts the number of load uops retired that performed one or more locks event=0xd0,period=1000003,umask=0x21  00    Counts the number of load uops retired that performed one or more locks Available PDIST counters: 0,1 mem_uops_retired.split cache Counts the number of memory uops retired that were splits event=0xd0,period=1000003,umask=0x43  00    Counts the number of memory uops retired that were splits. Available PDIST counters: 0,1 mem_uops_retired.split_loads cache Counts the number of retired split load uops event=0xd0,period=1000003,umask=0x41  00    Counts the number of retired split load uops. Available PDIST counters: 0,1 mem_uops_retired.split_stores cache Counts the number of retired split store uops event=0xd0,period=1000003,umask=0x42  00    Counts the number of retired split store uops. Available PDIST counters: 0,1 mem_uops_retired.stlb_miss cache Counts the number of memory uops retired that missed in the second level TLB event=0xd0,period=1000003,umask=0x13  00    Counts the number of memory uops retired that missed in the second level TLB. Available PDIST counters: 0,1 mem_uops_retired.stlb_miss_loads cache Counts the number of load uops retired that miss in the second Level TLB event=0xd0,period=1000003,umask=0x11  00    Counts the number of load uops retired that miss in the second Level TLB. Available PDIST counters: 0,1 mem_uops_retired.stlb_miss_stores cache Counts the number of store uops retired that miss in the second level TLB event=0xd0,period=1000003,umask=0x12  00    Counts the number of store uops retired that miss in the second level TLB. Available PDIST counters: 0,1 fp_arith_ops_retired.vector_128b floating point FP_ARITH_OPS_RETIRED.VECTOR_128B event=0xc7,period=100003,umask=0xc  00     fp_arith_ops_retired.vector_256b floating point FP_ARITH_OPS_RETIRED.VECTOR_256B event=0xc7,period=100003,umask=0x30  00     fp_flops_retired.all floating point Counts the number of all types of floating point operations per uop with all default weighting event=0xc8,period=1000003,umask=3  00    Counts the number of all types of floating point operations per uop with all default weighting Available PDIST counters: 0,1 fp_flops_retired.fp32 floating point Counts the number of floating point operations that produce 32 bit single precision results event=0xc8,period=1000003,umask=2  00    Counts the number of floating point operations that produce 32 bit single precision results Available PDIST counters: 0,1 fp_flops_retired.fp64 floating point Counts the number of floating point operations that produce 64 bit double precision results event=0xc8,period=1000003,umask=1  00    Counts the number of floating point operations that produce 64 bit double precision results Available PDIST counters: 0,1 fp_inst_retired.128b_dp floating point Counts the number of retired instructions whose sources are a packed 128 bit double precision floating point. This may be SSE or AVX.128 operations event=0xc7,period=1000003,umask=8  00    Counts the number of retired instructions whose sources are a packed 128 bit double precision floating point. This may be SSE or AVX.128 operations. Available PDIST counters: 0,1 fp_inst_retired.128b_sp floating point Counts the number of retired instructions whose sources are a packed 128 bit single precision floating point. This may be SSE or AVX.128 operations event=0xc7,period=1000003,umask=4  00    Counts the number of retired instructions whose sources are a packed 128 bit single precision floating point. This may be SSE or AVX.128 operations. Available PDIST counters: 0,1 fp_inst_retired.256b_dp floating point Counts the number of retired instructions whose sources are a packed 256 bit double precision floating point event=0xc7,period=1000003,umask=0x20  00    Counts the number of retired instructions whose sources are a packed 256 bit double precision floating point. Available PDIST counters: 0,1 fp_inst_retired.256b_sp floating point Counts the number of retired instructions whose sources are a packed 256 bit single precision floating point event=0xc7,period=1000003,umask=0x10  00    Counts the number of retired instructions whose sources are a packed 256 bit single precision floating point. Available PDIST counters: 0,1 fp_inst_retired.32b_sp floating point Counts the number of retired instructions whose sources are a scalar 32bit single precision floating point event=0xc7,period=1000003,umask=1  00    Counts the number of retired instructions whose sources are a scalar 32bit single precision floating point. Available PDIST counters: 0,1 fp_inst_retired.64b_dp floating point Counts the number of retired instructions whose sources are a scalar 64 bit double precision floating point event=0xc7,period=1000003,umask=2  00    Counts the number of retired instructions whose sources are a scalar 64 bit double precision floating point. Available PDIST counters: 0,1 fp_inst_retired.all floating point Counts the total number of  floating point retired instructions event=0xc7,period=1000003,umask=0x3f  00    Counts the total number of  floating point retired instructions. Available PDIST counters: 0,1 machine_clears.fp_assist floating point Counts the number of floating point operations retired that required microcode assist event=0xc3,period=1000003,umask=4  00    Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops uops_retired.fpdiv floating point Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt) event=0xc2,period=1000003,umask=0x40  00    Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt). Available PDIST counters: 0,1 baclears.any frontend Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches event=0xe6,period=1000003,umask=1  00    Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend.  Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches baclears.cond frontend Counts the number of BACLEARS due to a conditional jump event=0xe6,period=1000003,umask=0x10  00     baclears.indirect frontend Counts the number of BACLEARS due to an indirect branch event=0xe6,period=1000003,umask=2  00     baclears.return frontend Counts the number of BACLEARS due to a return branch event=0xe6,period=1000003,umask=8  00     baclears.uncond frontend Counts the number of BACLEARS due to a direct, unconditional jump event=0xe6,period=1000003,umask=4  00     frontend_retired.itlb_miss frontend Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss event=0xc6,period=1000003,umask=0x10  00    Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss Available PDIST counters: 0,1 frontend_retired_source.icache_l2_hit frontend Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that hit in the L2 cache event=0xc9,period=1000003,umask=1  00    Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that hit in the L2 cache. Available PDIST counters: 0,1 frontend_retired_source.itlb_stlb_hit frontend Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss that hit in the second level TLB event=0xc9,period=1000003,umask=0x10  00    Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss that hit in the second level TLB. Available PDIST counters: 0,1 frontend_retired_source.itlb_stlb_miss frontend Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss that also missed the second level TLB event=0xc9,period=1000003,umask=0x20  00    Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss that also missed the second level TLB. Available PDIST counters: 0,1 icache.hit frontend Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are present event=0x80,period=1000003,umask=1  00     idq_bubbles.starvation_cycles frontend Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled event=0x9c,cmask=8,period=1000003,umask=1  00    Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls machine_clears.memory_ordering memory Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation event=0xc3,period=1000003,umask=2  00     mem_trans_retired.load_latency_gt_1024 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles  Supports address when precise event=0xcd,period=53,umask=1,ldlat=0x400  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.  Reported latency may be longer than just the memory latency. Available PDIST counters: 0,1  Supports address when precise mem_trans_retired.load_latency_gt_128 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles  Supports address when precise event=0xcd,period=1009,umask=1,ldlat=0x80  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency. Available PDIST counters: 0,1  Supports address when precise mem_trans_retired.load_latency_gt_16 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles  Supports address when precise event=0xcd,period=20011,umask=1,ldlat=0x10  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency. Available PDIST counters: 0,1  Supports address when precise mem_trans_retired.load_latency_gt_2048 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles  Supports address when precise event=0xcd,period=23,umask=1,ldlat=0x800  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles.  Reported latency may be longer than just the memory latency. Available PDIST counters: 0,1  Supports address when precise mem_trans_retired.load_latency_gt_256 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles  Supports address when precise event=0xcd,period=503,umask=1,ldlat=0x100  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency. Available PDIST counters: 0,1  Supports address when precise mem_trans_retired.load_latency_gt_32 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles  Supports address when precise event=0xcd,period=100007,umask=1,ldlat=0x20  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency. Available PDIST counters: 0,1  Supports address when precise mem_trans_retired.load_latency_gt_4 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles  Supports address when precise event=0xcd,period=100003,umask=1,ldlat=0x4  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency. Available PDIST counters: 0,1  Supports address when precise mem_trans_retired.load_latency_gt_512 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles  Supports address when precise event=0xcd,period=101,umask=1,ldlat=0x200  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency. Available PDIST counters: 0,1  Supports address when precise mem_trans_retired.load_latency_gt_64 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles  Supports address when precise event=0xcd,period=2003,umask=1,ldlat=0x40  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency. Available PDIST counters: 0,1  Supports address when precise mem_trans_retired.load_latency_gt_8 memory Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles  Supports address when precise event=0xcd,period=50021,umask=1,ldlat=0x8  00    Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency. Available PDIST counters: 0,1  Supports address when precise misalign_mem_ref.load_page_split memory Counts misaligned loads that are 4K page splits event=0x13,period=1000003,umask=2  00    Counts misaligned loads that are 4K page splits. Available PDIST counters: 0,1 misalign_mem_ref.store_page_split memory Counts misaligned stores that are 4K page splits event=0x13,period=1000003,umask=4  00    Counts misaligned stores that are 4K page splits. Available PDIST counters: 0,1 ocr.demand_data_rd.dram memory Counts demand data reads that were supplied by DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x7BC000001  00    Counts demand data reads that were supplied by DRAM. Available PDIST counters: 0 ocr.demand_data_rd.l3_miss memory Counts demand data reads that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x13FBFC00001  00    Counts demand data reads that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.demand_data_rd.l3_miss memory Counts demand data reads that were not supplied by the L3 cache event=0x2a,period=100003,umask=1,offcore_rsp=0x9E7FA000001  00    Counts demand data reads that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.demand_rfo.l3_miss memory Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache event=0xb7,period=100003,umask=1,offcore_rsp=0x13FBFC00002  00    Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. Available PDIST counters: 0 ocr.demand_rfo.l3_miss memory Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache event=0x2a,period=100003,umask=1,offcore_rsp=0x9E7FA000002  00    Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. Available PDIST counters: 0 br_inst_retired.cond pipeline Conditional branch instructions retired event=0xc4,period=400009,umask=7  00    Counts conditional branch instructions retired. Available PDIST counters: 0,1 br_inst_retired.cond_ntaken pipeline Counts the number of not taken conditional branch instructions retired event=0xc4,period=1000003,umask=4  00    Counts the number of not taken conditional branch instructions retired. Available PDIST counters: 0,1 br_inst_retired.cond_ntaken pipeline Not taken branch instructions retired event=0xc4,period=400009,umask=4  00    Counts not taken branch instructions retired. Available PDIST counters: 0,1 br_inst_retired.cond_taken pipeline Taken conditional branch instructions retired event=0xc4,period=400009,umask=3  00    Counts taken conditional branch instructions retired. Available PDIST counters: 0,1 br_inst_retired.cond_taken_fwd pipeline Taken forward conditional branch instructions retired event=0xc4,period=400009,umask=2  00    Counts taken forward conditional branch instructions retired. Available PDIST counters: 0,1 br_inst_retired.far_branch pipeline Far branch instructions retired event=0xc4,period=100007  00    Counts far branch instructions retired. Available PDIST counters: 0,1 br_inst_retired.indirect pipeline This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT] event=0xc4,period=100003,umask=0x50  10    This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT] Available PDIST counters: 0,1 br_inst_retired.near_call pipeline Counts the number of near CALL branch instructions retired event=0xc4,period=1000003,umask=0x30  00    Counts the number of near CALL branch instructions retired. Available PDIST counters: 0,1 br_inst_retired.near_call pipeline Direct and indirect near call instructions retired event=0xc4,period=100007,umask=0x30  00    Counts both direct and indirect near call instructions retired. Available PDIST counters: 0,1 br_inst_retired.near_direct_call pipeline near relative call instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_REL_CALL] event=0xc4,period=100007,umask=0x20  00    Counts near relative call instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_REL_CALL] Available PDIST counters: 0,1 br_inst_retired.near_direct_jmp pipeline near relative jump instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_REL_JMP] event=0xc4,period=100007,umask=0x80  00    Counts near relative jump instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_REL_JMP] Available PDIST counters: 0,1 br_inst_retired.near_indirect pipeline Indirect near branch instructions retired (excluding returns) [This event is alias to BR_INST_RETIRED.INDIRECT] event=0xc4,period=100003,umask=0x50  00    Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch. [This event is alias to BR_INST_RETIRED.INDIRECT] Available PDIST counters: 0,1 br_inst_retired.near_indirect_call pipeline Indirect near call instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_IND_CALL] event=0xc4,period=100007,umask=0x10  00    Counts indirect near call instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_IND_CALL] Available PDIST counters: 0,1 br_inst_retired.near_indirect_jmp pipeline Indirect near jump instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_IND_JMP] event=0xc4,period=100007,umask=0x40  00    Counts indirect near jump instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_IND_JMP] Available PDIST counters: 0,1 br_inst_retired.near_ind_call pipeline This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT_CALL] event=0xc4,period=100007,umask=0x10  10    This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT_CALL] Available PDIST counters: 0,1 br_inst_retired.near_ind_jmp pipeline This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT_JMP] event=0xc4,period=100007,umask=0x40  10    This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT_JMP] Available PDIST counters: 0,1 br_inst_retired.near_jmp pipeline Indirect and Direct Relative near jump instructions retired event=0xc4,period=100007,umask=0xc0  00    Counts near jump instructions retired. Available PDIST counters: 0,1 br_inst_retired.near_rel_call pipeline This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_DIRECT_CALL] event=0xc4,period=100007,umask=0x20  10    This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_DIRECT_CALL] Available PDIST counters: 0,1 br_inst_retired.near_rel_jmp pipeline This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_DIRECT_JMP] event=0xc4,period=100007,umask=0x80  10    This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_DIRECT_JMP] Available PDIST counters: 0,1 br_inst_retired.near_taken pipeline Counts the number of near taken branch instructions retired event=0xc4,period=1000003,umask=0xfb  00    Counts the number of near taken branch instructions retired. Available PDIST counters: 0,1 br_inst_retired.near_taken pipeline Taken branch instructions retired event=0xc4,period=400009,umask=0xfb  00    Counts taken branch instructions retired. Available PDIST counters: 0,1 br_misp_retired.all_branches_cost pipeline This event is deprecated. [This event is alias to BR_MISP_RETIRED.ALL_BRANCHES_TPEBS] event=0xc5,period=400009  10    This event is deprecated. [This event is alias to BR_MISP_RETIRED.ALL_BRANCHES_TPEBS] Available PDIST counters: 0,1 br_misp_retired.all_branches_tpebs pipeline All mispredicted branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. [This event is alias to BR_MISP_RETIRED.ALL_BRANCHES_COST] event=0xc5,period=400009  00    All mispredicted branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. [This event is alias to BR_MISP_RETIRED.ALL_BRANCHES_COST] Available PDIST counters: 0,1 br_misp_retired.all_near_ind pipeline This event is deprecated. [This event is alias to BR_MISP_RETIRED.NEAR_INDIRECT] event=0xc5,period=1000003,umask=0x50  10    This event is deprecated. [This event is alias to BR_MISP_RETIRED.NEAR_INDIRECT] Available PDIST counters: 0,1 br_misp_retired.cond pipeline Mispredicted conditional branch instructions retired event=0xc5,period=400009,umask=7  00    Counts mispredicted conditional branch instructions retired. Available PDIST counters: 0,1 br_misp_retired.cond_cost pipeline This event is deprecated. [This event is alias to BR_MISP_RETIRED.COND_TPEBS] event=0xc5,period=400009,umask=0x8007  10    This event is deprecated. [This event is alias to BR_MISP_RETIRED.COND_TPEBS] Available PDIST counters: 0,1 br_misp_retired.cond_ntaken pipeline Counts the number of mispredicted not taken conditional branch instructions retired event=0xc5,period=1000003,umask=4  00    Counts the number of mispredicted not taken conditional branch instructions retired. Available PDIST counters: 0,1 br_misp_retired.cond_ntaken pipeline Mispredicted non-taken conditional branch instructions retired event=0xc5,period=400009,umask=4  00    Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken. Available PDIST counters: 0,1 br_misp_retired.cond_ntaken_cost pipeline This event is deprecated. [This event is alias to BR_MISP_RETIRED.COND_NTAKEN_TPEBS] event=0xc5,period=400009,umask=0x8004  10    This event is deprecated. [This event is alias to BR_MISP_RETIRED.COND_NTAKEN_TPEBS] Available PDIST counters: 0,1 br_misp_retired.cond_ntaken_tpebs pipeline Mispredicted non-taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. [This event is alias to BR_MISP_RETIRED.COND_NTAKEN_COST] event=0xc5,period=400009,umask=0x8004  00    Mispredicted non-taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. [This event is alias to BR_MISP_RETIRED.COND_NTAKEN_COST] Available PDIST counters: 0,1 br_misp_retired.cond_taken pipeline Counts the number of mispredicted taken conditional branch instructions retired event=0xc5,period=1000003,umask=3  00    Counts the number of mispredicted taken conditional branch instructions retired. Available PDIST counters: 0,1 br_misp_retired.cond_taken pipeline number of branch instructions retired that were mispredicted and taken event=0xc5,period=400009,umask=3  00    Counts taken conditional mispredicted branch instructions retired. Available PDIST counters: 0,1 br_misp_retired.cond_taken_bwd_cost pipeline This event is deprecated. [This event is alias to BR_MISP_RETIRED.COND_TAKEN_BWD_TPEBS] event=0xc5,period=400009,umask=0x8001  10    This event is deprecated. [This event is alias to BR_MISP_RETIRED.COND_TAKEN_BWD_TPEBS] Available PDIST counters: 0,1 br_misp_retired.cond_taken_bwd_tpebs pipeline number of branch instructions retired that were mispredicted and taken backward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. [This event is alias to BR_MISP_RETIRED.COND_TAKEN_BWD_COST] event=0xc5,period=400009,umask=0x8001  00    number of branch instructions retired that were mispredicted and taken backward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. [This event is alias to BR_MISP_RETIRED.COND_TAKEN_BWD_COST] Available PDIST counters: 0,1 br_misp_retired.cond_taken_cost pipeline This event is deprecated. [This event is alias to BR_MISP_RETIRED.COND_TAKEN_TPEBS] event=0xc5,period=400009,umask=0x8003  10    This event is deprecated. [This event is alias to BR_MISP_RETIRED.COND_TAKEN_TPEBS] Available PDIST counters: 0,1 br_misp_retired.cond_taken_fwd pipeline number of branch instructions retired that were mispredicted and taken forward event=0xc5,period=400009,umask=2  00    Counts taken forward conditional mispredicted branch instructions retired. Available PDIST counters: 0,1 br_misp_retired.cond_taken_fwd_cost pipeline This event is deprecated. [This event is alias to BR_MISP_RETIRED.COND_TAKEN_FWD_TPEBS] event=0xc5,period=400009,umask=0x8002  10    This event is deprecated. [This event is alias to BR_MISP_RETIRED.COND_TAKEN_FWD_TPEBS] Available PDIST counters: 0,1 br_misp_retired.cond_taken_fwd_tpebs pipeline number of branch instructions retired that were mispredicted and taken forward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. [This event is alias to BR_MISP_RETIRED.COND_TAKEN_FWD_COST] event=0xc5,period=400009,umask=0x8002  00    number of branch instructions retired that were mispredicted and taken forward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. [This event is alias to BR_MISP_RETIRED.COND_TAKEN_FWD_COST] Available PDIST counters: 0,1 br_misp_retired.cond_taken_tpebs pipeline Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. [This event is alias to BR_MISP_RETIRED.COND_TAKEN_COST] event=0xc5,period=400009,umask=0x8003  00    Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. [This event is alias to BR_MISP_RETIRED.COND_TAKEN_COST] Available PDIST counters: 0,1 br_misp_retired.cond_tpebs pipeline Mispredicted conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. [This event is alias to BR_MISP_RETIRED.COND_COST] event=0xc5,period=400009,umask=0x8007  00    Mispredicted conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. [This event is alias to BR_MISP_RETIRED.COND_COST] Available PDIST counters: 0,1 br_misp_retired.indirect pipeline This event is deprecated. [This event is alias to BR_MISP_RETIRED.NEAR_INDIRECT] event=0xc5,period=100003,umask=0x50  10    This event is deprecated. [This event is alias to BR_MISP_RETIRED.NEAR_INDIRECT] Available PDIST counters: 0,1 br_misp_retired.indirect_call pipeline This event is deprecated. [This event is alias to BR_MISP_RETIRED.NEAR_INDIRECT_CALL] event=0xc5,period=400009,umask=0x10  10    This event is deprecated. [This event is alias to BR_MISP_RETIRED.NEAR_INDIRECT_CALL] Available PDIST counters: 0,1 br_misp_retired.indirect_call_cost pipeline This event is deprecated. [This event is alias to BR_MISP_RETIRED.NEAR_INDIRECT_CALL_TPEBS] event=0xc5,period=400009,umask=0x8010  10    This event is deprecated. [This event is alias to BR_MISP_RETIRED.NEAR_INDIRECT_CALL_TPEBS] Available PDIST counters: 0,1 br_misp_retired.indirect_cost pipeline This event is deprecated. [This event is alias to BR_MISP_RETIRED.NEAR_INDIRECT_TPEBS] event=0xc5,period=100003,umask=0x8050  10    This event is deprecated. [This event is alias to BR_MISP_RETIRED.NEAR_INDIRECT_TPEBS] Available PDIST counters: 0,1 br_misp_retired.indirect_jmp pipeline This event is deprecated. [This event is alias to BR_MISP_RETIRED.NEAR_INDIRECT_JMP] event=0xc5,period=100003,umask=0x40  10    This event is deprecated. [This event is alias to BR_MISP_RETIRED.NEAR_INDIRECT_JMP] Available PDIST counters: 0,1 br_misp_retired.indirect_jmp_cost pipeline This event is deprecated. [This event is alias to BR_MISP_RETIRED.NEAR_INDIRECT_JMP_TPEBS] event=0xc5,period=100003,umask=0x8040  10    This event is deprecated. [This event is alias to BR_MISP_RETIRED.NEAR_INDIRECT_JMP_TPEBS] Available PDIST counters: 0,1 br_misp_retired.near_indirect pipeline Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired. [This event is alias to BR_MISP_RETIRED.ALL_NEAR_IND] event=0xc5,period=1000003,umask=0x50  00    Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired. [This event is alias to BR_MISP_RETIRED.ALL_NEAR_IND] Available PDIST counters: 0,1 br_misp_retired.near_indirect pipeline Miss-predicted near indirect branch instructions retired (excluding returns) [This event is alias to BR_MISP_RETIRED.INDIRECT] event=0xc5,period=100003,umask=0x50  00    Counts miss-predicted near indirect branch instructions retired excluding returns. TSX abort is an indirect branch. [This event is alias to BR_MISP_RETIRED.INDIRECT] Available PDIST counters: 0,1 br_misp_retired.near_indirect_call pipeline Mispredicted indirect CALL retired. [This event is alias to BR_MISP_RETIRED.INDIRECT_CALL] event=0xc5,period=400009,umask=0x10  00    Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect. [This event is alias to BR_MISP_RETIRED.INDIRECT_CALL] Available PDIST counters: 0,1 br_misp_retired.near_indirect_call_tpebs pipeline Mispredicted indirect CALL retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. [This event is alias to BR_MISP_RETIRED.INDIRECT_CALL_COST] event=0xc5,period=400009,umask=0x8010  00    Mispredicted indirect CALL retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. [This event is alias to BR_MISP_RETIRED.INDIRECT_CALL_COST] Available PDIST counters: 0,1 br_misp_retired.near_indirect_jmp pipeline Miss-predicted near indirect jump instructions retired. [This event is alias to BR_MISP_RETIRED.INDIRECT_JMP] event=0xc5,period=100003,umask=0x40  00    Miss-predicted near indirect jump instructions retired. [This event is alias to BR_MISP_RETIRED.INDIRECT_JMP] Available PDIST counters: 0,1 br_misp_retired.near_indirect_jmp_tpebs pipeline Miss-predicted near indirect jump instructions retired. Precise cost. [This event is alias to BR_MISP_RETIRED.INDIRECT_JMP_COST] event=0xc5,period=100003,umask=0x8040  00    Miss-predicted near indirect jump instructions retired. Precise cost. [This event is alias to BR_MISP_RETIRED.INDIRECT_JMP_COST] Available PDIST counters: 0,1 br_misp_retired.near_indirect_tpebs pipeline Mispredicted near indirect branch instructions retired (excluding returns). This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. [This event is alias to BR_MISP_RETIRED.INDIRECT_COST] event=0xc5,period=100003,umask=0x8050  00    Mispredicted near indirect branch instructions retired (excluding returns). This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. [This event is alias to BR_MISP_RETIRED.INDIRECT_COST] Available PDIST counters: 0,1 br_misp_retired.near_return pipeline This event counts the number of mispredicted ret instructions retired. Non PEBS [This event is alias to BR_MISP_RETIRED.RET] event=0xc5,period=100007,umask=8  00    This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired. [This event is alias to BR_MISP_RETIRED.RET] Available PDIST counters: 0,1 br_misp_retired.near_return_tpebs pipeline Mispredicted ret instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. [This event is alias to BR_MISP_RETIRED.RET_COST] event=0xc5,period=100007,umask=0x8008  00    Mispredicted ret instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. [This event is alias to BR_MISP_RETIRED.RET_COST] Available PDIST counters: 0,1 br_misp_retired.near_taken pipeline Number of near branch instructions retired that were mispredicted and taken event=0xc5,period=400009,umask=0xfb  00    Counts number of near branch instructions retired that were mispredicted and taken. Available PDIST counters: 0,1 br_misp_retired.near_taken_cost pipeline This event is deprecated. [This event is alias to BR_MISP_RETIRED.NEAR_TAKEN_TPEBS] event=0xc5,period=400009,umask=0x80fb  10    This event is deprecated. [This event is alias to BR_MISP_RETIRED.NEAR_TAKEN_TPEBS] Available PDIST counters: 0,1 br_misp_retired.near_taken_tpebs pipeline Mispredicted taken near branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. [This event is alias to BR_MISP_RETIRED.NEAR_TAKEN_COST] event=0xc5,period=400009,umask=0x80fb  00    Mispredicted taken near branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. [This event is alias to BR_MISP_RETIRED.NEAR_TAKEN_COST] Available PDIST counters: 0,1 br_misp_retired.ret pipeline This event is deprecated. [This event is alias to BR_MISP_RETIRED.NEAR_RETURN] event=0xc5,period=100007,umask=8  10    This event is deprecated. [This event is alias to BR_MISP_RETIRED.NEAR_RETURN] Available PDIST counters: 0,1 br_misp_retired.ret_cost pipeline This event is deprecated. [This event is alias to BR_MISP_RETIRED.NEAR_RETURN_TPEBS] event=0xc5,period=100007,umask=0x8008  10    This event is deprecated. [This event is alias to BR_MISP_RETIRED.NEAR_RETURN_TPEBS] Available PDIST counters: 0,1 cpu_clk_unhalted.core_p pipeline Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD_P] event=0x3c,period=2000003  00     cpu_clk_unhalted.thread_p pipeline Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE_P] event=0x3c,period=2000003  00     ld_blocks.address_alias pipeline Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check event=3,period=1000003,umask=4  00    Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check. Available PDIST counters: 0,1 ld_blocks.all pipeline Counts the number of retired loads that are blocked for any of the following reasons:  DTLB miss, address alias, store forward or data unknown (includes memory disambiguation blocks and ESP consuming load blocks) event=3,period=1000003,umask=0x1f  00    Counts the number of retired loads that are blocked for any of the following reasons:  DTLB miss, address alias, store forward or data unknown (includes memory disambiguation blocks and ESP consuming load blocks). Available PDIST counters: 0,1 ld_blocks.bank_conflict pipeline Bank conflicts in DCU due to limited lookup ports event=3,period=100003,umask=0x40  00    Counts the number of times a load got blocked due to bank conflicts in DCU ld_blocks.data_unknown pipeline Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready event=3,period=1000003,umask=1  00    Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready. Available PDIST counters: 0,1 ld_blocks.store_forward pipeline Counts the number of retired loads that are blocked because its address partially overlapped with an older store event=3,period=1000003,umask=2  00    Counts the number of retired loads that are blocked because its address partially overlapped with an older store. Available PDIST counters: 0,1 machine_clears.disambiguation pipeline Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU event=0xc3,period=1000003,umask=8  00     machine_clears.page_fault pipeline Counts the number of machine clears due to a page fault.  Counts both I-Side and D-Side (Loads/Stores) page faults.  A page fault occurs when either the page is not present, or an access violation occurs event=0xc3,period=1000003,umask=0x20  00     machine_clears.smc pipeline Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page event=0xc3,period=1000003,umask=1  00     misc_retired.lbr_inserts pipeline Counts the number of LBR entries recorded. Requires LBRs to be enabled in IA32_LBR_CTL event=0xe4,period=1000003,umask=1  00    Counts the number of LBR entries recorded. Requires LBRs to be enabled in IA32_LBR_CTL. Available PDIST counters: 0,1 misc_retired1.lfence pipeline Counts the number of LFENCE instructions retired event=0xe0,period=1000003,umask=2  00    Counts the number of LFENCE instructions retired. Available PDIST counters: 0,1 misc_retired2.keylocker_access pipeline Counts the number of accesses to KeyLocker cache event=0xe1,period=1000003,umask=0x10  00    Counts the number of accesses to KeyLocker cache. Available PDIST counters: 0,1 misc_retired2.keylocker_miss pipeline Counts the number of misses to KeyLocker cache event=0xe1,period=1000003,umask=0x11  00    Counts the number of misses to KeyLocker cache. Available PDIST counters: 0,1 serialization.c01_ms_scb pipeline Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state. For Tremont, UMWAIT and TPAUSE will only put the CPU into C0.1 activity state (not C0.2 activity state) event=0x75,period=1000003,umask=4  00     topdown_bad_speculation.lsd_mispredict pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to a branch mispredict that resulted in LSD exit event=0x73,period=1000003,umask=8  00     topdown_be_bound.lsd pipeline Counts the number of issue slots every cycle that were not consumed by the backend due to LSD entry event=0x74,period=1000003,umask=0x80  00     topdown_retiring.all_p pipeline Counts the number of consumed retirement slots event=0xc2,period=1000003,umask=2  00    Counts the number of consumed retirement slots. Available PDIST counters: 0,1 uops_retired.idiv pipeline Counts the number of integer divide uops retired event=0xc2,period=1000003,umask=0x80  00    Counts the number of integer divide uops retired. Available PDIST counters: 0,1 uops_retired.ms pipeline Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS).  This includes uops from flows due to complex instructions, faults, assists, and inserted flows event=0xc2,period=1000003,umask=4  00     uops_retired.x87 pipeline Counts the number of x87 uops retired, includes those in ms flows event=0xc2,period=1000003  00     dtlb_load_misses.miss_caused_walk virtual memory Counts the number of page walks initiated by a demand load that missed the first and second level TLBs event=8,period=1000003,umask=1  00     dtlb_load_misses.stlb_hit virtual memory Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB event=8,period=1000003,umask=0x20  00     dtlb_store_misses.miss_caused_walk virtual memory Counts the number of page walks initiated by a store that missed the first and second level TLBs event=0x49,period=1000003,umask=1  00     dtlb_store_misses.stlb_hit virtual memory Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB event=0x49,period=1000003,umask=0x20  00    Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB itlb_misses.stlb_hit virtual memory Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will result in an ITLB write from STLB event=0x85,period=1000003,umask=0x20  00     itlb_misses.walk_pending virtual memory Counts the number of page walks outstanding for iside in PMH every cycle event=0x85,period=1000003,umask=0x10  00    Counts the number of page walks outstanding for iside in PMH every cycle.  A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.  Walks could be counted by edge detecting on this event, but would count restarted suspended walks ld_blocks.dtlb_miss virtual memory Counts the number of retired loads that are blocked due to a first level TLB miss event=3,period=1000003,umask=8  00    Counts the number of retired loads that are blocked due to a first level TLB miss. Available PDIST counters: 0,1 l2_rqsts.miss cache All requests that miss L2 cache event=0x24,period=200003,umask=0x3f  00    Counts all requests that miss L2 cache l2_rqsts.references cache All L2 requests event=0x24,period=200003,umask=0xff  00    Counts all L2 requests unc_arb_dat_occupancy.all uncore interconnect Each cycle counts number of any coherent requests at memory controller that were issued by any core event=0x85,umask=1  01     unc_arb_req_trk_occupancy.drd uncore interconnect Each cycle counts number of valid coherent Data Read entries. Such entry is defined as valid when it is allocated until deallocation. Does not include prefetches event=0x80,umask=2  01     unc_arb_trk_occupancy.all uncore interconnect Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk until deallocation. Accounts for Coherent and non-coherent traffic event=0x80,umask=1  01     unc_arb_trk_occupancy.rd uncore interconnect Each cycle counts number of valid coherent Data Read entries. Such entry is defined as valid when it is allocated until deallocation. Does not include prefetches event=0x80,umask=2  01     unc_arb_trk_requests.rd uncore interconnect Counts number of all coherent Data Read entries. Does not include prefetches event=0x81,umask=2  01     mem_load_uops_llc_hit_retired.xsnp_hit cache Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS) (Precise event) event=0xd2,period=20011,umask=2  00    This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package).  Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line.  In this case, a snoop was required, and another L2 had the line in a non-modified state. (Precise Event - PEBS) (Precise event) mem_load_uops_llc_hit_retired.xsnp_hitm cache Retired load uops which data sources were HitM responses from shared LLC. (Precise Event - PEBS) (Precise event) event=0xd2,period=20011,umask=4  00    This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package).  Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line.  In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2. (Precise Event - PEBS) (Precise event) mem_load_uops_llc_hit_retired.xsnp_miss cache Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS) (Precise event) event=0xd2,period=20011,umask=1  00     mem_load_uops_llc_hit_retired.xsnp_none cache Retired load uops which data sources were hits in LLC without snoops required. (Precise Event - PEBS) (Precise event) event=0xd2,period=100003,umask=8  00     mem_load_uops_misc_retired.llc_miss cache Retired load uops with unknown information as data source in cache serviced the load. (Precise Event - PEBS) (Precise event) event=0xd4,period=100007,umask=2  00    This event counts retired demand loads that missed the  last-level (L3) cache. This means that the load is usually satisfied from memory in a client system or possibly from the remote socket in a server. Demand loads are non speculative load uops. (Precise Event - PEBS) (Precise event) mem_load_uops_retired.hit_lfb cache Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS) (Precise event) event=0xd1,period=100003,umask=0x40  00     mem_load_uops_retired.l1_hit cache Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS) (Precise event) event=0xd1,period=2000003,umask=1  00     mem_load_uops_retired.l2_hit cache Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS) (Precise event) event=0xd1,period=100003,umask=2  00     mem_load_uops_retired.llc_hit cache Retired load uops which data sources were data hits in LLC without snoops required. (Precise Event - PEBS) (Precise event) event=0xd1,period=50021,umask=4  00    This event counts retired load uops that hit in the last-level (L3) cache without snoops required. (Precise Event - PEBS) (Precise event) mem_uops_retired.all_loads cache All retired load uops. (Precise Event - PEBS) (Precise event) event=0xd0,period=2000003,umask=0x81  00    This event counts the number of load uops retired (Precise Event) (Precise event) mem_uops_retired.all_stores cache All retired store uops. (Precise Event - PEBS) (Precise event) event=0xd0,period=2000003,umask=0x82  00    This event counts the number of store uops retired. (Precise Event - PEBS) (Precise event) mem_uops_retired.lock_loads cache Retired load uops with locked access. (Precise Event - PEBS) (Precise event) event=0xd0,period=100007,umask=0x21  00     mem_uops_retired.split_loads cache Retired load uops that split across a cacheline boundary. (Precise Event - PEBS) (Precise event) event=0xd0,period=100003,umask=0x41  00    This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). (Precise Event - PEBS) (Precise event) mem_uops_retired.split_stores cache Retired store uops that split across a cacheline boundary. (Precise Event - PEBS) (Precise event) event=0xd0,period=100003,umask=0x42  00    This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). (Precise Event - PEBS) (Precise event) mem_uops_retired.stlb_miss_loads cache Retired load uops that miss the STLB. (Precise Event - PEBS) (Precise event) event=0xd0,period=100003,umask=0x11  00     mem_uops_retired.stlb_miss_stores cache Retired store uops that miss the STLB. (Precise Event - PEBS) (Precise event) event=0xd0,period=100003,umask=0x12  00     offcore_requests.demand_code_rd cache Cacheable and noncacheable code read requests event=0xb0,period=100003,umask=2  00     offcore_response.all_code_rd.llc_hit.hitm_other_core cache Counts demand & prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c0244  00     offcore_response.all_code_rd.llc_hit.snoop_miss cache Counts demand & prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0244  00     offcore_response.all_data_rd.llc_hit.snoop_miss cache Counts demand & prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0091  00     offcore_response.all_pf_code_rd.llc_hit.any_response cache Counts all prefetch code reads that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0240  00     offcore_response.all_pf_code_rd.llc_hit.hitm_other_core cache Counts prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c0240  00     offcore_response.all_pf_code_rd.llc_hit.hit_other_core_no_fwd cache Counts prefetch code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003c0240  00     offcore_response.all_pf_code_rd.llc_hit.no_snoop_needed cache Counts prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c0240  00     offcore_response.all_pf_code_rd.llc_hit.snoop_miss cache Counts prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0240  00     offcore_response.all_pf_data_rd.llc_hit.any_response cache Counts all prefetch data reads that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0090  00     offcore_response.all_pf_data_rd.llc_hit.snoop_miss cache Counts prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0090  00     offcore_response.all_pf_rfo.llc_hit.any_response cache Counts all prefetch RFOs that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0120  00     offcore_response.all_pf_rfo.llc_hit.hitm_other_core cache Counts prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c0120  00     offcore_response.all_pf_rfo.llc_hit.hit_other_core_no_fwd cache Counts prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003c0120  00     offcore_response.all_pf_rfo.llc_hit.no_snoop_needed cache Counts prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c0120  00     offcore_response.all_pf_rfo.llc_hit.snoop_miss cache Counts prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0120  00     offcore_response.all_reads.any_response cache Counts all data/code/rfo references (demand & prefetch)  event=0xb7,period=100003,umask=1,offcore_rsp=0x000107F7  00     offcore_response.all_reads.llc_hit.hitm_other_core cache Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c03f7  00     offcore_response.all_reads.llc_hit.hit_other_core_no_fwd cache Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003c03f7  00     offcore_response.all_reads.llc_hit.no_snoop_needed cache Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c03f7  00     offcore_response.all_reads.llc_hit.snoop_miss cache Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c03f7  00     offcore_response.all_rfo.any_response cache Counts all demand & prefetch prefetch RFOs  event=0xb7,period=100003,umask=1,offcore_rsp=0x00010122  00     offcore_response.all_rfo.llc_hit.hitm_other_core cache Counts demand & prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c0122  00     offcore_response.all_rfo.llc_hit.hit_other_core_no_fwd cache Counts demand & prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003c0122  00     offcore_response.all_rfo.llc_hit.snoop_miss cache Counts demand & prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0122  00     offcore_response.corewb.any_response cache OFFCORE_RESPONSE.COREWB.ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10008  00     offcore_response.data_in.any_response cache REQUEST = DATA_INTO_CORE and RESPONSE = ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10433  00     offcore_response.demand_code_rd.llc_hit.hitm_other_core cache Counts demand code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c0004  00     offcore_response.demand_code_rd.llc_hit.hit_other_core_no_fwd cache Counts demand code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003c0004  00     offcore_response.demand_code_rd.llc_hit.snoop_miss cache Counts demand code reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0004  00     offcore_response.demand_data_rd.any_response cache Counts all demand data reads  event=0xb7,period=100003,umask=1,offcore_rsp=0x00010001  00     offcore_response.demand_data_rd.llc_hit.snoop_miss cache Counts demand data reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0001  00     offcore_response.demand_rfo.any_response cache Counts all demand rfo's  event=0xb7,period=100003,umask=1,offcore_rsp=0x00010002  00     offcore_response.demand_rfo.llc_hit.hit_other_core_no_fwd cache Counts demand data writes (RFOs) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003c0002  00     offcore_response.demand_rfo.llc_hit.snoop_miss cache Counts demand data writes (RFOs) that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0002  00     offcore_response.demand_rfo.llc_hit_m.hitm cache REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_M and SNOOP = HITM event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040002  00     offcore_response.other.portio_mmio_uc cache Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses event=0xb7,period=100003,umask=1,offcore_rsp=0x2380408000  00     offcore_response.pf_ifetch.any_response cache REQUEST = PF_RFO and RESPONSE = ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10040  00     offcore_response.pf_l2_code_rd.llc_hit.hitm_other_core cache Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c0040  00     offcore_response.pf_l2_code_rd.llc_hit.hit_other_core_no_fwd cache Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003c0040  00     offcore_response.pf_l2_code_rd.llc_hit.no_snoop_needed cache Counts prefetch (that bring data to L2) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c0040  00     offcore_response.pf_l2_code_rd.llc_hit.snoop_miss cache Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0040  00     offcore_response.pf_l2_data_rd.llc_hit.any_response cache Counts all prefetch (that bring data to L2) data reads that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0010  00     offcore_response.pf_l2_rfo.llc_hit.any_response cache Counts all prefetch (that bring data to L2) RFOs that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0020  00     offcore_response.pf_l2_rfo.llc_hit.hitm_other_core cache Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c0020  00     offcore_response.pf_l2_rfo.llc_hit.hit_other_core_no_fwd cache Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003c0020  00     offcore_response.pf_l2_rfo.llc_hit.no_snoop_needed cache Counts prefetch (that bring data to L2) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c0020  00     offcore_response.pf_l2_rfo.llc_hit.snoop_miss cache Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0020  00     offcore_response.pf_llc_code_rd.llc_hit.hitm_other_core cache Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c0200  00     offcore_response.pf_llc_code_rd.llc_hit.hit_other_core_no_fwd cache Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003c0200  00     offcore_response.pf_llc_code_rd.llc_hit.no_snoop_needed cache Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c0200  00     offcore_response.pf_llc_code_rd.llc_hit.snoop_miss cache Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0200  00     offcore_response.pf_llc_data_rd.llc_hit.any_response cache Counts all prefetch (that bring data to LLC only) data reads that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0080  00     offcore_response.pf_llc_rfo.llc_hit.any_response cache Counts all prefetch (that bring data to LLC only) RFOs that hit in the LLC event=0xb7,period=100003,umask=1,offcore_rsp=0x3f803c0100  00     offcore_response.pf_llc_rfo.llc_hit.hitm_other_core cache Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003c0100  00     offcore_response.pf_llc_rfo.llc_hit.hit_other_core_no_fwd cache Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003c0100  00     offcore_response.pf_llc_rfo.llc_hit.no_snoop_needed cache Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003c0100  00     offcore_response.pf_llc_rfo.llc_hit.snoop_miss cache Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=1,offcore_rsp=0x2003c0100  00     offcore_response.pf_l_data_rd.any_response cache REQUEST = PF_LLC_DATA_RD and RESPONSE = ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10080  00     offcore_response.pf_l_ifetch.any_response cache REQUEST = PF_LLC_IFETCH and RESPONSE = ANY_RESPONSE event=0xb7,period=100003,umask=1,offcore_rsp=0x10200  00     idq.ms_cycles frontend Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy event=0x79,cmask=1,period=2000003,umask=0x30  00    This event counts cycles during which the microcode sequencer assisted the front-end in delivering uops.  Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder.  Using other instructions, if possible, will usually improve performance.  See the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual for more information offcore_response.all_pf_code_rd.llc_miss.dram memory Counts all prefetch code reads that miss the LLC  and the data returned from dram event=0xb7,period=100003,umask=1,offcore_rsp=0x300400240  00     offcore_response.all_pf_data_rd.llc_miss.dram memory Counts all prefetch data reads that miss the LLC  and the data returned from dram event=0xb7,period=100003,umask=1,offcore_rsp=0x300400090  00     offcore_response.all_pf_rfo.llc_miss.dram memory Counts all prefetch RFOs that miss the LLC  and the data returned from dram event=0xb7,period=100003,umask=1,offcore_rsp=0x300400120  00     offcore_response.all_rfo.llc_miss.dram memory Counts all demand & prefetch RFOs that miss the LLC  and the data returned from dram event=0xb7,period=100003,umask=1,offcore_rsp=0x300400122  00     offcore_response.any_request.llc_miss_local.dram memory REQUEST = ANY_REQUEST and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x1f80408fff  00    This event counts any requests that miss the LLC where the data was returned from local DRAM offcore_response.data_in_socket.llc_miss.local_dram memory Counts LLC replacements event=0xb7,period=100003,umask=1,offcore_rsp=0x6004001b3  00    This event counts all data requests (demand/prefetch data reads and demand data writes (RFOs) that miss the LLC  where the data is returned from local DRAM offcore_response.data_in_socket.llc_miss_local.any_llc_hit memory REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIT event=0xb7,period=100003,umask=1,offcore_rsp=0x17004001b3  00     offcore_response.demand_ifetch.llc_miss_local.dram memory REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x1f80400004  00     offcore_response.demand_rfo.llc_miss.dram memory Counts demand data writes (RFOs) that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=1,offcore_rsp=0x300400002  00     offcore_response.pf_data_rd.llc_miss_local.dram memory REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x1f80400010  00     offcore_response.pf_ifetch.llc_miss_local.dram memory REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x1f80400040  00     offcore_response.pf_l2_code_rd.llc_miss.dram memory Counts all prefetch (that bring data to L2) code reads that miss the LLC  and the data returned from dram event=0xb7,period=100003,umask=1,offcore_rsp=0x300400040  00     offcore_response.pf_l2_data_rd.llc_miss.dram memory Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=1,offcore_rsp=0x300400010  00     offcore_response.pf_l2_rfo.llc_miss.dram memory Counts all prefetch (that bring data to L2) RFOs that miss the LLC  and the data returned from dram event=0xb7,period=100003,umask=1,offcore_rsp=0x300400020  00     offcore_response.pf_llc_code_rd.llc_miss.dram memory Counts all prefetch (that bring data to LLC only) code reads that miss the LLC  and the data returned from dram event=0xb7,period=100003,umask=1,offcore_rsp=0x300400200  00     offcore_response.pf_llc_data_rd.llc_miss.dram memory Counts all prefetch (that bring data to LLC only) data reads that miss the LLC  and the data returned from dram event=0xb7,period=100003,umask=1,offcore_rsp=0x300400080  00     offcore_response.pf_llc_rfo.llc_miss.dram memory Counts all prefetch (that bring data to LLC only) RFOs that miss the LLC  and the data returned from dram event=0xb7,period=100003,umask=1,offcore_rsp=0x300400100  00     offcore_response.pf_l_data_rd.llc_miss_local.dram memory REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x1f80400080  00     offcore_response.pf_l_ifetch.llc_miss_local.dram memory REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM event=0xb7,period=100003,umask=1,offcore_rsp=0x1f80400200  00     page_walks.llc_miss memory Number of any page walk that had a miss in LLC. Does not necessary cause a SUSPEND event=0xbe,period=100003,umask=1  00     br_inst_retired.conditional pipeline Conditional branch instructions retired. (Precise Event - PEBS) (Precise event) event=0xc4,period=400009,umask=1  00     br_inst_retired.near_call pipeline Direct and indirect near call instructions retired. (Precise Event - PEBS) (Precise event) event=0xc4,period=100007,umask=2  00     br_inst_retired.near_call_r3 pipeline Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS) (Precise event) event=0xc4,period=100007,umask=2  00     br_inst_retired.near_return pipeline Return instructions retired. (Precise Event - PEBS) (Precise event) event=0xc4,period=100007,umask=8  00     br_inst_retired.near_taken pipeline Taken branch instructions retired. (Precise Event - PEBS) (Precise event) event=0xc4,period=400009,umask=0x20  00     br_misp_retired.conditional pipeline Mispredicted conditional branch instructions retired. (Precise Event - PEBS) (Precise event) event=0xc5,period=400009,umask=1  00     br_misp_retired.near_call pipeline Direct and indirect mispredicted near call instructions retired. (Precise Event - PEBS) (Precise event) event=0xc5,period=100007,umask=2  00     br_misp_retired.not_taken pipeline Mispredicted not taken branch instructions retired.(Precise Event - PEBS) (Precise event) event=0xc5,period=400009,umask=0x10  00     br_misp_retired.taken pipeline Mispredicted taken branch instructions retired. (Precise Event - PEBS) (Precise event) event=0xc5,period=400009,umask=0x20  00     ld_blocks.store_forward pipeline Cases when loads get true Block-on-Store blocking code preventing store forwarding event=3,period=100003,umask=2  00    This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load.  The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store.  See the table of not supported store forwards in the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual.  The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued partial_rat_stalls.flags_merge_uop_cycles pipeline Performance sensitive flags-merging uops added by Sandy Bridge u-arch event=0x59,cmask=1,period=2000003,umask=0x20  00    This event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual partial_rat_stalls.slow_lea_window pipeline Cycles with at least one slow LEA uop being allocated event=0x59,period=2000003,umask=0x40  00    This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions uops_retired.all pipeline Actually retired uops. (Precise Event - PEBS) (Precise event) event=0xc2,period=2000003,umask=1  00    This event counts the number of micro-ops retired. (Precise Event) (Precise event) uops_retired.retire_slots pipeline Retirement slots used. (Precise Event - PEBS) (Precise event) event=0xc2,period=2000003,umask=2  00    This event counts the number of retirement slots used each cycle.  There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle.  This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization. (Precise Event - PEBS) (Precise event) mem_load_l3_miss_retired.remote_pmm cache Retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches event=0xd3,period=100007,umask=0x10  00    Counts retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3. Available PDIST counters: 0 mem_load_retired.local_pmm cache Retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches  Supports address when precise event=0xd1,period=1000003,umask=0x80  00    Counts retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3. Available PDIST counters: 0  Supports address when precise ocr.demand_data_rd.local_socket_pmm cache Counts demand data reads that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster event=0x2a,period=100003,umask=1,offcore_rsp=0x700C00001  00    Counts demand data reads that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster. Available PDIST counters: 0 ocr.demand_data_rd.pmm cache Counts demand data reads that were supplied by PMM event=0x2a,period=100003,umask=1,offcore_rsp=0x703C00001  00    Counts demand data reads that were supplied by PMM. Available PDIST counters: 0 ocr.demand_data_rd.remote_pmm cache Counts demand data reads that were supplied by PMM attached to another socket event=0x2a,period=100003,umask=1,offcore_rsp=0x703000001  00    Counts demand data reads that were supplied by PMM attached to another socket. Available PDIST counters: 0 ocr.reads_to_core.local_socket_pmm cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster event=0x2a,period=100003,umask=1,offcore_rsp=0x700C04477  00    Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster. Available PDIST counters: 0 ocr.reads_to_core.remote_pmm cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to another socket event=0x2a,period=100003,umask=1,offcore_rsp=0x703004477  00    Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to another socket. Available PDIST counters: 0 unc_iio_bandwidth_out.part0_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x30  01     unc_iio_bandwidth_out.part1_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x31  01     unc_iio_bandwidth_out.part2_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x32  01     unc_iio_bandwidth_out.part3_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x33  01     unc_iio_bandwidth_out.part4_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x34  01     unc_iio_bandwidth_out.part5_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x35  01     unc_iio_bandwidth_out.part6_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x36  01     unc_iio_bandwidth_out.part7_freerun uncore io Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC event=0xff,umask=0x37  01     mem_bound_stalls_load.llc_hit_nosnoop cache Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC, no snoop was required. LLC provides the data. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros event=0x34,period=1000003,umask=2  00     mem_load_uops_l3_miss_retired.all cache Counts the total number of load ops retired that miss the L3 cache event=0xd3,period=1000003,umask=0xff  00     mem_load_uops_l3_miss_retired.remote_dram_or_nofwd cache Counts the number of load ops retired that miss the L3 cache and hit in a Remote DRAM event=0xd3,period=1000003,umask=2  00    Counts the number of load ops retired that miss the L3 cache and hit in a Remote DRAM, OR had a Remote snoop miss/no fwd and hit in the Local Dram mem_load_uops_l3_miss_retired.remote_fwd_hitm cache Counts the number of load ops retired that miss the L3 cache and hit in a Remote Cache and modified data was forwarded event=0xd3,period=1000003,umask=8  00     mem_load_uops_l3_miss_retired.remote_fwd_nonm cache Counts the number of load ops retired that miss the L3 cache and hit in a Remote Cache and non-modified data was forwarded event=0xd3,period=1000003,umask=4  00     ocr.demand_data_rd.local_dram memory Counts demand data reads that were supplied by DRAM attached to this socket event=0xb7,period=100003,umask=1,offcore_rsp=0x184000001  00    Counts demand data reads that were supplied by DRAM attached to this socket. Available PDIST counters: 0 ocr.demand_data_rd.remote_dram memory Counts demand data reads that were supplied by DRAM attached to another socket event=0xb7,period=100003,umask=1,offcore_rsp=0x730000001  00    Counts demand data reads that were supplied by DRAM attached to another socket. Available PDIST counters: 0 br_inst_retired.all_branches pipeline Counts the total number of branch instructions retired for all branch types  Spec update: SRF6, SRF7 event=0xc4,period=200003  00    Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires.  All branch type instructions are accounted for  Spec update: SRF6, SRF7 br_inst_retired.cond pipeline Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches  Spec update: SRF7 event=0xc4,period=200003,umask=0x7e  00     br_inst_retired.far_branch pipeline Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return  Spec update: SRF7 event=0xc4,period=200003,umask=0xbf  00     br_inst_retired.indirect pipeline Counts the number of near indirect JMP and near indirect CALL branch instructions retired  Spec update: SRF7 event=0xc4,period=200003,umask=0xeb  00     br_inst_retired.indirect_call pipeline Counts the number of near indirect CALL branch instructions retired  Spec update: SRF7 event=0xc4,period=200003,umask=0xfb  00     br_inst_retired.ind_call pipeline This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT_CALL  Spec update: SRF7 event=0xc4,period=200003,umask=0xfb  10     br_inst_retired.near_call pipeline Counts the number of near CALL branch instructions retired  Spec update: SRF6, SRF7 event=0xc4,period=200003,umask=0xf9  00     br_inst_retired.near_taken pipeline Counts the number of near taken branch instructions retired  Spec update: SRF7 event=0xc4,period=200003,umask=0xc0  00     unc_cha_tor_inserts.ia_miss_drd_opt_pref_remote uncore cache Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF_OPT, and target remote memory event=0x35,umask=0xc8a77e01  01    TOR Inserts : Data read opt prefetch from local iA that missed the LLC targeting remote memory unc_cha_tor_inserts.ia_miss_drd_opt_remote uncore cache Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd_Opt, and target remote memory event=0x35,umask=0xc8277e01  01    TOR Inserts : Data read opt from local iA that missed the LLC targeting remote memory unc_b2hot_clockticks uncore interconnect UNC_B2HOT_CLOCKTICKS event=1,umask=1  01     core_reject_l2q.all cache Counts the number of request that were not accepted into the L2Q because the L2Q is FULL event=0x31,period=200003  00    Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q.  It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link.  The L2Q may also reject transactions  from a core to insure fairness between cores, or to delay a core?s dirty eviction when the address conflicts incoming external snoops.  (Note that L2 prefetcher requests that are dropped are not counted by this event.) fetch_stall.icache_fill_pending_cycles cache Cycles code-fetch stalled due to an outstanding ICache miss event=0x86,period=200003,umask=4  00    Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss.  Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy.
Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes.  This will include cycles due to an ITLB miss, ICache miss and other events l2_reject_xq.all cache Counts the number of request from the L2 that were not accepted into the XQ event=0x30,period=200003  00    This event counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBS (L2 misses) and WOB (L2 write-back victims) longest_lat_cache.miss cache L2 cache request misses event=0x2e,period=200003,umask=0x41  00    This event counts the total number of L2 cache references and the number of L2 cache misses respectively longest_lat_cache.reference cache L2 cache requests from this core event=0x2e,period=200003,umask=0x4f  00    This event counts requests originating from the core that references a cache line in the L2 cache mem_uops_retired.all_loads cache All Loads event=4,period=200003,umask=0x40  00    This event counts the number of load ops retired mem_uops_retired.all_stores cache All Stores event=4,period=200003,umask=0x80  00    This event counts the number of store ops retired mem_uops_retired.hitm cache Cross core or cross module hitm (Precise event) event=4,period=200003,umask=0x20  00    This event counts the number of load ops retired that got data from the other core or from the other module (Precise event) mem_uops_retired.l1_miss_loads cache Loads missed L1 event=4,period=200003,umask=1  00    This event counts the number of load ops retired that miss in L1 Data cache. Note that prefetch misses will not be counted mem_uops_retired.l2_hit_loads cache Loads hit L2 (Precise event) event=4,period=200003,umask=2  00    This event counts the number of load ops retired that hit in the L2 (Precise event) mem_uops_retired.l2_miss_loads cache Loads missed L2 (Precise event) event=4,period=100007,umask=4  00    This event counts the number of load ops retired that miss in the L2 (Precise event) mem_uops_retired.utlb_miss cache Loads missed UTLB event=4,period=200003,umask=0x10  00    This event counts the number of load ops retired that had UTLB miss offcore_response cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction event=0xb7,period=100007,umask=1  00     offcore_response.any_code_rd.any_response cache Counts any code reads (demand & prefetch) that have any response type event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010044  00     offcore_response.any_code_rd.l2_miss.any cache Counts any code reads (demand & prefetch) that miss L2 event=0xb7,period=100007,umask=1,offcore_rsp=0x1680000044  00     offcore_response.any_code_rd.l2_miss.hitm_other_core cache Counts any code reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000044  00     offcore_response.any_code_rd.l2_miss.hit_other_core_no_fwd cache Counts any code reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=1,offcore_rsp=0x0400000044  00     offcore_response.any_code_rd.l2_miss.snoop_miss cache Counts any code reads (demand & prefetch) that miss L2 with a snoop miss response event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000044  00     offcore_response.any_data_rd.any_response cache Counts any data read (demand & prefetch) that have any response type event=0xb7,period=100007,umask=1,offcore_rsp=0x0000013091  00     offcore_response.any_data_rd.l2_miss.any cache Counts any data read (demand & prefetch) that miss L2 event=0xb7,period=100007,umask=1,offcore_rsp=0x1680003091  00     offcore_response.any_data_rd.l2_miss.hitm_other_core cache Counts any data read (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x1000003091  00     offcore_response.any_data_rd.l2_miss.hit_other_core_no_fwd cache Counts any data read (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=1,offcore_rsp=0x0400003091  00     offcore_response.any_data_rd.l2_miss.snoop_miss cache Counts any data read (demand & prefetch) that miss L2 with a snoop miss response event=0xb7,period=100007,umask=1,offcore_rsp=0x0200003091  00     offcore_response.any_request.any_response cache Counts any request that have any response type event=0xb7,period=100007,umask=1,offcore_rsp=0x0000018008  00     offcore_response.any_request.l2_miss.hitm_other_core cache Counts any request that hit in the other module where modified copies were found in other core's L1 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x1000008008  00     offcore_response.any_request.l2_miss.hit_other_core_no_fwd cache Counts any request that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=1,offcore_rsp=0x0400008008  00     offcore_response.any_request.l2_miss.snoop_miss cache Counts any request that miss L2 with a snoop miss response event=0xb7,period=100007,umask=1,offcore_rsp=0x0200008008  00     offcore_response.any_rfo.any_response cache Counts any rfo reads (demand & prefetch) that have any response type event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010022  00     offcore_response.any_rfo.l2_miss.any cache Counts any rfo reads (demand & prefetch) that miss L2 event=0xb7,period=100007,umask=1,offcore_rsp=0x1680000022  00     offcore_response.any_rfo.l2_miss.hitm_other_core cache Counts any rfo reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000022  00     offcore_response.any_rfo.l2_miss.hit_other_core_no_fwd cache Counts any rfo reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=1,offcore_rsp=0x0400000022  00     offcore_response.any_rfo.l2_miss.snoop_miss cache Counts any rfo reads (demand & prefetch) that miss L2 with a snoop miss response event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000022  00     offcore_response.corewb.l2_miss.any cache Counts writeback (modified to exclusive) that miss L2 event=0xb7,period=100007,umask=1,offcore_rsp=0x1680000008  00     offcore_response.corewb.l2_miss.no_snoop_needed cache Counts writeback (modified to exclusive) that miss L2 with no details on snoop-related information event=0xb7,period=100007,umask=1,offcore_rsp=0x0080000008  00     offcore_response.demand_code_rd.any_response cache Counts demand and DCU prefetch instruction cacheline that have any response type event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010004  00     offcore_response.demand_code_rd.l2_miss.any cache Counts demand and DCU prefetch instruction cacheline that miss L2 event=0xb7,period=100007,umask=1,offcore_rsp=0x1680000004  00     offcore_response.demand_code_rd.l2_miss.hit_other_core_no_fwd cache Counts demand and DCU prefetch instruction cacheline that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=1,offcore_rsp=0x0400000004  00     offcore_response.demand_code_rd.l2_miss.snoop_miss cache Counts demand and DCU prefetch instruction cacheline that miss L2 with a snoop miss response event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000004  00     offcore_response.demand_code_rd.outstanding cache Counts demand and DCU prefetch instruction cacheline that are are outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000004  00     offcore_response.demand_data_rd.any_response cache Counts demand and DCU prefetch data read that have any response type event=0xb7,period=100007,umask=1,offcore_rsp=0x0000010001  00     offcore_response.demand_data_rd.l2_miss.any cache Counts demand and DCU prefetch data read that miss L2 event=0xb7,period=100007,umask=1,offcore_rsp=0x1680000001  00     offcore_response.demand_data_rd.l2_miss.hitm_other_core cache Counts demand and DCU prefetch data read that hit in the other module where modified copies were found in other core's L1 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000001  00     offcore_response.demand_data_rd.l2_miss.hit_other_core_no_fwd cache Counts demand and DCU prefetch data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=1,offcore_rsp=0x0400000001  00     offcore_response.demand_data_rd.l2_miss.snoop_miss cache Counts demand and DCU prefetch data read that miss L2 with a snoop miss response event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000001  00     offcore_response.demand_data_rd.outstanding cache Counts demand and DCU prefetch data read that are are outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000001  00     offcore_response.demand_rfo.l2_miss.any cache Counts demand and DCU prefetch RFOs that miss L2 event=0xb7,period=100007,umask=1,offcore_rsp=0x1680000002  00     offcore_response.demand_rfo.l2_miss.hitm_other_core cache Counts demand and DCU prefetch RFOs that hit in the other module where modified copies were found in other core's L1 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000002  00     offcore_response.demand_rfo.l2_miss.hit_other_core_no_fwd cache Counts demand and DCU prefetch RFOs that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=1,offcore_rsp=0x0400000002  00     offcore_response.demand_rfo.l2_miss.snoop_miss cache Counts demand and DCU prefetch RFOs that miss L2 with a snoop miss response event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000002  00     offcore_response.demand_rfo.outstanding cache Counts demand and DCU prefetch RFOs that are are outstanding, per cycle, from the time of the L2 miss to when any response is received event=0xb7,period=100007,umask=1,offcore_rsp=0x4000000002  00     offcore_response.partial_reads.l2_miss.any cache Counts demand reads of partial cache lines (including UC and WC) that miss L2 event=0xb7,period=100007,umask=1,offcore_rsp=0x1680000080  00     offcore_response.partial_writes.l2_miss.any cache Countsof demand RFO requests to write to partial cache lines that miss L2 event=0xb7,period=100007,umask=1,offcore_rsp=0x1680000100  00     offcore_response.pf_l1_data_rd.any_response cache Counts DCU hardware prefetcher data read that have any response type event=0xb7,period=100007,umask=1,offcore_rsp=0x0000012000  00     offcore_response.pf_l1_data_rd.l2_miss.any cache Counts DCU hardware prefetcher data read that miss L2 event=0xb7,period=100007,umask=1,offcore_rsp=0x1680002000  00     offcore_response.pf_l1_data_rd.l2_miss.hitm_other_core cache Counts DCU hardware prefetcher data read that hit in the other module where modified copies were found in other core's L1 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x1000002000  00     offcore_response.pf_l1_data_rd.l2_miss.hit_other_core_no_fwd cache Counts DCU hardware prefetcher data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=1,offcore_rsp=0x0400002000  00     offcore_response.pf_l1_data_rd.l2_miss.snoop_miss cache Counts DCU hardware prefetcher data read that miss L2 with a snoop miss response event=0xb7,period=100007,umask=1,offcore_rsp=0x0200002000  00     offcore_response.pf_l2_code_rd.l2_miss.any cache Counts code reads generated by L2 prefetchers that miss L2 event=0xb7,period=100007,umask=1,offcore_rsp=0x1680000040  00     offcore_response.pf_l2_code_rd.l2_miss.hit_other_core_no_fwd cache Counts code reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=1,offcore_rsp=0x0400000040  00     offcore_response.pf_l2_code_rd.l2_miss.snoop_miss cache Counts code reads generated by L2 prefetchers that miss L2 with a snoop miss response event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000040  00     offcore_response.pf_l2_data_rd.l2_miss.any cache Counts data cacheline reads generated by L2 prefetchers that miss L2 event=0xb7,period=100007,umask=1,offcore_rsp=0x1680000010  00     offcore_response.pf_l2_data_rd.l2_miss.hitm_other_core cache Counts data cacheline reads generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000010  00     offcore_response.pf_l2_data_rd.l2_miss.hit_other_core_no_fwd cache Counts data cacheline reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=1,offcore_rsp=0x0400000010  00     offcore_response.pf_l2_data_rd.l2_miss.snoop_miss cache Counts data cacheline reads generated by L2 prefetchers that miss L2 with a snoop miss response event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000010  00     offcore_response.pf_l2_rfo.l2_miss.any cache Counts RFO requests generated by L2 prefetchers that miss L2 event=0xb7,period=100007,umask=1,offcore_rsp=0x1680000020  00     offcore_response.pf_l2_rfo.l2_miss.hitm_other_core cache Counts RFO requests generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache event=0xb7,period=100007,umask=1,offcore_rsp=0x1000000020  00     offcore_response.pf_l2_rfo.l2_miss.hit_other_core_no_fwd cache Counts RFO requests generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=1,offcore_rsp=0x0400000020  00     offcore_response.pf_l2_rfo.l2_miss.snoop_miss cache Counts RFO requests generated by L2 prefetchers that miss L2 with a snoop miss response event=0xb7,period=100007,umask=1,offcore_rsp=0x0200000020  00     offcore_response.streaming_stores.l2_miss.any cache Counts streaming store that miss L2 event=0xb7,period=100007,umask=1,offcore_rsp=0x1680004800  00     rehabq.any_ld cache Any reissued load uops event=3,period=200003,umask=0x40  00    This event counts the number of load uops reissued from Rehabq rehabq.any_st cache Any reissued store uops event=3,period=200003,umask=0x80  00    This event counts the number of store uops reissued from Rehabq rehabq.ld_block_std_notready cache Loads blocked due to store data not ready event=3,period=200003,umask=2  00    This event counts the cases where a forward was technically possible, but did not occur because the store data was not available at the right time rehabq.ld_block_st_forward cache Loads blocked due to store forward restriction (Precise event) event=3,period=200003,umask=1  00    This event counts the number of retired loads that were prohibited from receiving forwarded data from the store because of address mismatch (Precise event) rehabq.ld_splits cache Load uops that split cache line boundary (Precise event) event=3,period=200003,umask=8  00    This event counts the number of retire loads that experienced cache line boundary splits (Precise event) rehabq.lock cache Uops with lock semantics event=3,period=200003,umask=0x10  00    This event counts the number of retired memory operations with lock semantics. These are either implicit locked instructions such as the XCHG instruction or instructions with an explicit LOCK prefix (0xF0) rehabq.sta_full cache Store address buffer full event=3,period=200003,umask=0x20  00    This event counts the number of retired stores that are delayed because there is not a store address buffer available rehabq.st_splits cache Store uops that split cache line boundary event=3,period=200003,umask=4  00    This event counts the number of retire stores that experienced cache line boundary splits machine_clears.fp_assist floating point Stalls due to FP assists event=0xc3,period=200003,umask=4  00    This event counts the number of times that pipeline stalled due to FP operations needing assists baclears.all frontend Counts the number of baclears event=0xe6,period=200003,umask=1  00    The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end.  The BACLEARS.ANY event counts the number of baclears for any type of branch baclears.cond frontend Counts the number of JCC baclears event=0xe6,period=200003,umask=0x10  00    The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end.  The BACLEARS.COND event counts the number of JCC (Jump on Conditional Code) baclears baclears.return frontend Counts the number of RETURN baclears event=0xe6,period=200003,umask=8  00    The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end.  The BACLEARS.RETURN event counts the number of RETURN baclears decode_restriction.predecode_wrong frontend Counts the number of times a decode restriction reduced the decode throughput due to wrong instruction length prediction event=0xe9,period=200003,umask=1  00     icache.accesses frontend Instruction fetches event=0x80,period=200003,umask=3  00    This event counts all instruction fetches, not including most uncacheable
fetches icache.hit frontend Instruction fetches from Icache event=0x80,period=200003,umask=1  00    This event counts all instruction fetches from the instruction cache icache.misses frontend Icache miss event=0x80,period=200003,umask=2  00    This event counts all instruction fetches that miss the Instruction cache or produce memory requests. This includes uncacheable fetches. An instruction fetch miss is counted only once and not once for every cycle it is outstanding ms_decoded.ms_entry frontend Counts the number of times entered into a ucode flow in the FEC.  Includes inserted flows due to front-end detected faults or assists.  Speculative count event=0xe7,period=200003,umask=1  00    Counts the number of times the MSROM starts a flow of UOPS. It does not count every time a UOP is read from the microcode ROM.  The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine.  Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort.  The event will count MSROM startups for UOPS that are speculative, and subsequently cleared by branch mispredict or machine clear.  Background: UOPS are produced by two mechanisms.  Either they are generated by hardware that decodes instructions into UOPS, or they are delivered by a ROM (called the MSROM) that holds UOPS associated with a specific instruction.  MSROM UOPS might also be delivered in response to some condition such as a fault or other exceptional condition.  This event is an excellent mechanism for detecting instructions that require the use of MSROM instructions machine_clears.memory_ordering memory Stalls due to Memory ordering event=0xc3,period=200003,umask=2  00    This event counts the number of times that pipeline was cleared due to memory ordering issues fetch_stall.all other Cycles code-fetch stalled due to any reason event=0x86,period=200003,umask=0x3f  00    Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes.  This will include cycles due to an ITLB miss, ICache miss and other events fetch_stall.itlb_fill_pending_cycles other Cycles code-fetch stalled due to an outstanding ITLB miss event=0x86,period=200003,umask=2  00    Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss.  Note: this event is not the same as page walk cycles to retrieve an instruction translation br_inst_retired.all_branches pipeline Counts the number of branch instructions retired.. (Precise event) event=0xc4,period=200003  00    ALL_BRANCHES counts the number of any branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) br_inst_retired.all_taken_branches pipeline Counts the number of taken branch instructions retired (Must be precise) event=0xc4,period=200003,umask=0x80  00    ALL_TAKEN_BRANCHES counts the number of all taken branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Must be precise) br_inst_retired.call pipeline Counts the number of near CALL branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xf9  00    CALL counts the number of near CALL branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) br_inst_retired.far_branch pipeline Counts the number of far branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xbf  00    FAR counts the number of far branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) br_inst_retired.ind_call pipeline Counts the number of near indirect CALL branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xfb  00    IND_CALL counts the number of near indirect CALL branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) br_inst_retired.jcc pipeline Counts the number of JCC branch instructions retired (Precise event) event=0xc4,period=200003,umask=0x7e  00    JCC counts the number of conditional branch (JCC) instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) br_inst_retired.non_return_ind pipeline Counts the number of near indirect JMP and near indirect CALL branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xeb  00    NON_RETURN_IND counts the number of near indirect JMP and near indirect CALL branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) br_inst_retired.rel_call pipeline Counts the number of near relative CALL branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xfd  00    REL_CALL counts the number of near relative CALL branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) br_inst_retired.return pipeline Counts the number of near RET branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xf7  00    RETURN counts the number of near RET branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) br_inst_retired.taken_jcc pipeline Counts the number of taken JCC branch instructions retired (Precise event) event=0xc4,period=200003,umask=0xfe  00    TAKEN_JCC counts the number of taken conditional branch (JCC) instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) br_misp_retired.all_branches pipeline Counts the number of mispredicted branch instructions retired (Precise event) event=0xc5,period=200003  00    ALL_BRANCHES counts the number of any mispredicted branch instructions retired. This umask is an architecturally defined event. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) br_misp_retired.ind_call pipeline Counts the number of mispredicted near indirect CALL branch instructions retired (Precise event) event=0xc5,period=200003,umask=0xfb  00    IND_CALL counts the number of mispredicted near indirect CALL branch instructions retired.  This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) br_misp_retired.jcc pipeline Counts the number of mispredicted JCC branch instructions retired (Precise event) event=0xc5,period=200003,umask=0x7e  00    JCC counts the number of mispredicted conditional branches (JCC) instructions retired.  This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) br_misp_retired.non_return_ind pipeline Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired (Precise event) event=0xc5,period=200003,umask=0xeb  00    NON_RETURN_IND counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired.  This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) br_misp_retired.return pipeline Counts the number of mispredicted near RET branch instructions retired (Precise event) event=0xc5,period=200003,umask=0xf7  00    RETURN counts the number of mispredicted near RET branch instructions retired.  This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) br_misp_retired.taken_jcc pipeline Counts the number of mispredicted taken JCC branch instructions retired (Precise event) event=0xc5,period=200003,umask=0xfe  00    TAKEN_JCC counts the number of mispredicted taken conditional branch (JCC) instructions retired.  This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) cpu_clk_unhalted.core pipeline Fixed Counter: Counts the number of unhalted core clock cycles event=0x3c,period=2000003  00    Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios.  The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. In systems with a constant core frequency, this event can give you a measurement of the elapsed time while the core was not in halt state by dividing the event count by the core frequency. This event is architecturally defined and is a designated fixed counter.  CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the core frequency which may change from time to time.  CPU_CLK_UNHALTE.REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time.  The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REF cpu_clk_unhalted.core_p pipeline Core cycles when core is not halted event=0x3c,period=2000003  00    This event counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time cpu_clk_unhalted.ref pipeline Reference cycles when core is not halted event=0x0,umask=0x03,period=2000003  00    This event counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time cpu_clk_unhalted.ref_tsc pipeline Fixed Counter: Counts the number of unhalted reference clock cycles event=0,period=2000003,umask=3  00    Counts the number of reference cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios.  The core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time.  Divide this event count by core frequency to determine the elapsed time while the core was not in halt state.  Divide this event count by core frequency to determine the elapsed time while the core was not in halt state.  This event is architecturally defined and is a designated fixed counter.  CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the core frequency which may change from time to time.  CPU_CLK_UNHALTE.REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time.  The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REF cycles_div_busy.all pipeline Cycles the divider is busy.  Does not imply a stall waiting for the divider event=0xcd,period=2000003,umask=1  00    Cycles the divider is busy.This event counts the cycles when the divide unit is unable to accept a new divide UOP because it is busy processing a previously dispatched UOP. The cycles will be counted irrespective of whether or not another divide UOP is waiting to enter the divide unit (from the RS). This event might count cycles while a divide is in progress even if the RS is empty.  The divide instruction is one of the longest latency instructions in the machine.  Hence, it has a special event associated with it to help determine if divides are delaying the retirement of instructions inst_retired.any pipeline Fixed Counter: Counts the number of instructions retired event=0xc0,period=2000003  00    This event counts the number of instructions that retire.  For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires.  The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps.  Background: Modern microprocessors employ extensive pipelining and speculative techniques.  Since sometimes an instruction is started but never completed, the notion of "retirement" is introduced.  A retired instruction is one that commits its states. Or stated differently, an instruction might be abandoned at some point. No instruction is truly finished until it retires.  This counter measures the number of completed instructions.  The fixed event is INST_RETIRED.ANY and the programmable event is INST_RETIRED.ANY_P inst_retired.any_p pipeline Instructions retired event=0xc0,period=2000003  00    This event counts the number of instructions that retire execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers machine_clears.all pipeline Counts all machine clears event=0xc3,period=200003,umask=8  00    Machine clears happen when something happens in the machine that causes the hardware to need to take special care to get the right answer. When such a condition is signaled on an instruction, the front end of the machine is notified that it must restart, so no more instructions will be decoded from the current path.  All instructions "older" than this one will be allowed to finish.  This instruction and all "younger" instructions must be cleared, since they must not be allowed to complete.  Essentially, the hardware waits until the problematic instruction is the oldest instruction in the machine.  This means all older instructions are retired, and all pending stores (from older instructions) are completed.  Then the new path of instructions from the front end are allowed to start into the machine.  There are many conditions that might cause a machine clear (including the receipt of an interrupt, or a trap or a fault).  All those conditions (including but not limited to MACHINE_CLEARS.MEMORY_ORDERING, MACHINE_CLEARS.SMC, and MACHINE_CLEARS.FP_ASSIST) are captured in the ANY event. In addition, some conditions can be specifically counted (i.e. SMC, MEMORY_ORDERING, FP_ASSIST).  However, the sum of SMC, MEMORY_ORDERING, and FP_ASSIST machine clears will not necessarily equal the number of ANY machine_clears.smc pipeline Self-Modifying Code detected event=0xc3,period=200003,umask=1  00    This event counts the number of times that a program writes to a code section. Self-modifying code causes a severe penalty in all Intel? architecture processors no_alloc_cycles.all pipeline Counts the number of cycles when no uops are allocated for any reason event=0xca,period=200003,umask=0x3f  00    The NO_ALLOC_CYCLES.ALL event counts the number of cycles when the front-end does not provide any instructions to be allocated for any reason. This event indicates the cycles where an allocation stalls occurs, and no UOPS are allocated in that cycle no_alloc_cycles.mispredicts pipeline Counts the number of cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted jump to retire.  After the misprediction is detected, the front end will start immediately but the allocate pipe stalls until the mispredicted event=0xca,period=200003,umask=4  00     no_alloc_cycles.not_delivered pipeline Counts the number of cycles when no uops are allocated, the IQ is empty, and no other condition is blocking allocation event=0xca,period=200003,umask=0x50  00    The NO_ALLOC_CYCLES.NOT_DELIVERED event is used to measure front-end inefficiencies, i.e. when front-end of the machine is not delivering micro-ops to the back-end and the back-end is not stalled. This event can be used to identify if the machine is truly front-end bound.  When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance.  Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into micro-ops (uops) in machine understandable format and putting them into a micro-op queue to be consumed by back end. The back-end then takes these micro-ops, allocates the required resources.  When all resources are ready, micro-ops are executed. If the back-end is not ready to accept micro-ops from the front-end, then we do not want to count these as front-end bottlenecks.  However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more UOPS. This event counts the cycles only when back-end is requesting more uops and front-end is not able to provide them. Some examples of conditions that cause front-end efficiencies are: Icache misses, ITLB misses, and decoder restrictions that limit the front-end bandwidth no_alloc_cycles.rat_stall pipeline Counts the number of cycles when no uops are allocated and a RATstall is asserted event=0xca,period=200003,umask=0x20  00     no_alloc_cycles.rob_full pipeline Counts the number of cycles when no uops are allocated and the ROB is full (less than 2 entries available) event=0xca,period=200003,umask=1  00     rs_full_stall.all pipeline Counts the number of cycles the Alloc pipeline is stalled when any one of the RSs (IEC, FPC and MEC) is full. This event is a superset of all the individual RS stall event counts event=0xcb,period=200003,umask=0x1f  00     rs_full_stall.mec pipeline Counts the number of cycles and allocation pipeline is stalled and is waiting for a free MEC reservation station entry.  The cycles should be appropriately counted in case of the cracked ops e.g. In case of a cracked load-op, the load portion is sent to M event=0xcb,period=200003,umask=1  00     uops_retired.all pipeline Micro-ops retired event=0xc2,period=2000003,umask=0x10  00    This event counts the number of micro-ops retired. The processor decodes complex macro instructions into a sequence of simpler micro-ops. Most instructions are composed of one or two micro-ops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists. In some cases micro-op sequences are fused or whole instructions are fused into one micro-op. See other UOPS_RETIRED events for differentiating retired fused and non-fused micro-ops uops_retired.ms pipeline MSROM micro-ops retired event=0xc2,period=2000003,umask=1  00    This event counts the number of micro-ops retired that were supplied from MSROM mem_uops_retired.dtlb_miss_loads virtual memory Loads missed DTLB (Precise event) event=4,period=200003,umask=8  00    This event counts the number of load ops retired that had DTLB miss (Precise event) page_walks.cycles virtual memory Total cycles for all the page walks. (I-side and D-side) event=5,period=200003,umask=3  00    This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress.  Since a pagewalk implies a TLB miss, the approximate cost of a TLB miss can be determined from this event page_walks.d_side_cycles virtual memory Duration of D-side page-walks in core cycles event=5,period=200003,umask=1  00    This event counts every cycle when a D-side (walks due to a load) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks page_walks.d_side_walks virtual memory D-side page-walks event=5,edge=1,period=100003,umask=1  00    This event counts when a data (D) page walk is completed or started.  Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks page_walks.i_side_cycles virtual memory Duration of I-side page-walks in core cycles event=5,period=200003,umask=2  00    This event counts every cycle when a I-side (walks due to an instruction fetch) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks page_walks.i_side_walks virtual memory I-side page-walks event=5,edge=1,period=100003,umask=2  00    This event counts when an instruction (I) page walk is completed or started.  Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks page_walks.walks virtual memory Total page walks that are completed (I-side and D-side) event=5,edge=1,period=100003,umask=3  00    This event counts when a data (D) page walk or an instruction (I) page walk is completed or started.  Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks l2_lines_out.non_silent cache Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3 event=0xf2,period=200003,umask=2  00     l2_lines_out.silent cache Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event event=0xf2,period=200003,umask=1  00     offcore_response.demand_code_rd.l3_hit.any_snoop cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC01C0004  00     offcore_response.demand_code_rd.l3_hit.snoop_hitm cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x10001C0004  00     offcore_response.demand_code_rd.l3_hit.snoop_hit_no_fwd cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x4001C0004  00     offcore_response.demand_code_rd.l3_hit.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2001C0004  00     offcore_response.demand_code_rd.l3_hit.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x801C0004  00     offcore_response.demand_code_rd.l3_hit.snoop_not_needed cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1001C0004  00     offcore_response.demand_code_rd.l3_hit.spl_hit cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x401C0004  00     offcore_response.demand_code_rd.l3_hit_e.any_snoop cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0080004  00     offcore_response.demand_code_rd.l3_hit_e.snoop_hitm cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080004  00     offcore_response.demand_code_rd.l3_hit_e.snoop_hit_no_fwd cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400080004  00     offcore_response.demand_code_rd.l3_hit_e.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200080004  00     offcore_response.demand_code_rd.l3_hit_e.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80080004  00     offcore_response.demand_code_rd.l3_hit_e.snoop_not_needed cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100080004  00     offcore_response.demand_code_rd.l3_hit_e.spl_hit cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x40080004  00     offcore_response.demand_code_rd.l3_hit_m.any_snoop cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0040004  00     offcore_response.demand_code_rd.l3_hit_m.snoop_hitm cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040004  00     offcore_response.demand_code_rd.l3_hit_m.snoop_hit_no_fwd cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400040004  00     offcore_response.demand_code_rd.l3_hit_m.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200040004  00     offcore_response.demand_code_rd.l3_hit_m.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80040004  00     offcore_response.demand_code_rd.l3_hit_m.snoop_not_needed cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100040004  00     offcore_response.demand_code_rd.l3_hit_m.spl_hit cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x40040004  00     offcore_response.demand_code_rd.l3_hit_s.any_snoop cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0100004  00     offcore_response.demand_code_rd.l3_hit_s.snoop_hitm cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100004  00     offcore_response.demand_code_rd.l3_hit_s.snoop_hit_no_fwd cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400100004  00     offcore_response.demand_code_rd.l3_hit_s.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200100004  00     offcore_response.demand_code_rd.l3_hit_s.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80100004  00     offcore_response.demand_code_rd.l3_hit_s.snoop_not_needed cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100100004  00     offcore_response.demand_code_rd.l3_hit_s.spl_hit cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x40100004  00     offcore_response.demand_code_rd.l4_hit_local_l4.any_snoop cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0400004  00     offcore_response.demand_code_rd.l4_hit_local_l4.snoop_hitm cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000400004  00     offcore_response.demand_code_rd.l4_hit_local_l4.snoop_hit_no_fwd cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400400004  00     offcore_response.demand_code_rd.l4_hit_local_l4.snoop_miss cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200400004  00     offcore_response.demand_code_rd.l4_hit_local_l4.snoop_none cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80400004  00     offcore_response.demand_code_rd.l4_hit_local_l4.snoop_not_needed cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100400004  00     offcore_response.demand_code_rd.l4_hit_local_l4.spl_hit cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x40400004  00     offcore_response.demand_code_rd.supplier_none.any_snoop cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0020004  00     offcore_response.demand_code_rd.supplier_none.spl_hit cache Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x40020004  00     offcore_response.demand_data_rd.l3_hit.any_snoop cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC01C0001  00     offcore_response.demand_data_rd.l3_hit.snoop_hitm cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x10001C0001  00     offcore_response.demand_data_rd.l3_hit.snoop_hit_no_fwd cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x4001C0001  00     offcore_response.demand_data_rd.l3_hit.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2001C0001  00     offcore_response.demand_data_rd.l3_hit.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x801C0001  00     offcore_response.demand_data_rd.l3_hit.snoop_not_needed cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1001C0001  00     offcore_response.demand_data_rd.l3_hit.spl_hit cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x401C0001  00     offcore_response.demand_data_rd.l3_hit_e.any_snoop cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0080001  00     offcore_response.demand_data_rd.l3_hit_e.snoop_hitm cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080001  00     offcore_response.demand_data_rd.l3_hit_e.snoop_hit_no_fwd cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400080001  00     offcore_response.demand_data_rd.l3_hit_e.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200080001  00     offcore_response.demand_data_rd.l3_hit_e.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80080001  00     offcore_response.demand_data_rd.l3_hit_e.snoop_not_needed cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100080001  00     offcore_response.demand_data_rd.l3_hit_e.spl_hit cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x40080001  00     offcore_response.demand_data_rd.l3_hit_m.any_snoop cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0040001  00     offcore_response.demand_data_rd.l3_hit_m.snoop_hitm cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040001  00     offcore_response.demand_data_rd.l3_hit_m.snoop_hit_no_fwd cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400040001  00     offcore_response.demand_data_rd.l3_hit_m.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200040001  00     offcore_response.demand_data_rd.l3_hit_m.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80040001  00     offcore_response.demand_data_rd.l3_hit_m.snoop_not_needed cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100040001  00     offcore_response.demand_data_rd.l3_hit_m.spl_hit cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x40040001  00     offcore_response.demand_data_rd.l3_hit_s.any_snoop cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0100001  00     offcore_response.demand_data_rd.l3_hit_s.snoop_hitm cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100001  00     offcore_response.demand_data_rd.l3_hit_s.snoop_hit_no_fwd cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400100001  00     offcore_response.demand_data_rd.l3_hit_s.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200100001  00     offcore_response.demand_data_rd.l3_hit_s.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80100001  00     offcore_response.demand_data_rd.l3_hit_s.snoop_not_needed cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100100001  00     offcore_response.demand_data_rd.l3_hit_s.spl_hit cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x40100001  00     offcore_response.demand_data_rd.l4_hit_local_l4.any_snoop cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0400001  00     offcore_response.demand_data_rd.l4_hit_local_l4.snoop_hitm cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x1000400001  00     offcore_response.demand_data_rd.l4_hit_local_l4.snoop_hit_no_fwd cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x400400001  00     offcore_response.demand_data_rd.l4_hit_local_l4.snoop_miss cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x200400001  00     offcore_response.demand_data_rd.l4_hit_local_l4.snoop_none cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x80400001  00     offcore_response.demand_data_rd.l4_hit_local_l4.snoop_not_needed cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x100400001  00     offcore_response.demand_data_rd.l4_hit_local_l4.spl_hit cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x40400001  00     offcore_response.demand_data_rd.supplier_none.any_snoop cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0020001  00     offcore_response.demand_data_rd.supplier_none.spl_hit cache Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x40020001  00     offcore_response.demand_rfo.l3_hit.any_snoop cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC01C0002  00     offcore_response.demand_rfo.l3_hit.snoop_hitm cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x10001C0002  00     offcore_response.demand_rfo.l3_hit.snoop_hit_no_fwd cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x4001C0002  00     offcore_response.demand_rfo.l3_hit.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x2001C0002  00     offcore_response.demand_rfo.l3_hit.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x801C0002  00     offcore_response.demand_rfo.l3_hit.snoop_not_needed cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x1001C0002  00     offcore_response.demand_rfo.l3_hit.spl_hit cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x401C0002  00     offcore_response.demand_rfo.l3_hit_e.any_snoop cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0080002  00     offcore_response.demand_rfo.l3_hit_e.snoop_hitm cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x1000080002  00     offcore_response.demand_rfo.l3_hit_e.snoop_hit_no_fwd cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x400080002  00     offcore_response.demand_rfo.l3_hit_e.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x200080002  00     offcore_response.demand_rfo.l3_hit_e.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x80080002  00     offcore_response.demand_rfo.l3_hit_e.snoop_not_needed cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x100080002  00     offcore_response.demand_rfo.l3_hit_e.spl_hit cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x40080002  00     offcore_response.demand_rfo.l3_hit_m.any_snoop cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0040002  00     offcore_response.demand_rfo.l3_hit_m.snoop_hitm cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x1000040002  00     offcore_response.demand_rfo.l3_hit_m.snoop_hit_no_fwd cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x400040002  00     offcore_response.demand_rfo.l3_hit_m.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x200040002  00     offcore_response.demand_rfo.l3_hit_m.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x80040002  00     offcore_response.demand_rfo.l3_hit_m.snoop_not_needed cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x100040002  00     offcore_response.demand_rfo.l3_hit_m.spl_hit cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x40040002  00     offcore_response.demand_rfo.l3_hit_s.any_snoop cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0100002  00     offcore_response.demand_rfo.l3_hit_s.snoop_hitm cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x1000100002  00     offcore_response.demand_rfo.l3_hit_s.snoop_hit_no_fwd cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x400100002  00     offcore_response.demand_rfo.l3_hit_s.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x200100002  00     offcore_response.demand_rfo.l3_hit_s.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x80100002  00     offcore_response.demand_rfo.l3_hit_s.snoop_not_needed cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x100100002  00     offcore_response.demand_rfo.l3_hit_s.spl_hit cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x40100002  00     offcore_response.demand_rfo.l4_hit_local_l4.any_snoop cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0400002  00     offcore_response.demand_rfo.l4_hit_local_l4.snoop_hitm cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x1000400002  00     offcore_response.demand_rfo.l4_hit_local_l4.snoop_hit_no_fwd cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x400400002  00     offcore_response.demand_rfo.l4_hit_local_l4.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x200400002  00     offcore_response.demand_rfo.l4_hit_local_l4.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x80400002  00     offcore_response.demand_rfo.l4_hit_local_l4.snoop_not_needed cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x100400002  00     offcore_response.demand_rfo.l4_hit_local_l4.spl_hit cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x40400002  00     offcore_response.demand_rfo.supplier_none.any_snoop cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0020002  00     offcore_response.demand_rfo.supplier_none.snoop_hitm cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x1000020002  00     offcore_response.demand_rfo.supplier_none.snoop_hit_no_fwd cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x400020002  00     offcore_response.demand_rfo.supplier_none.snoop_miss cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x200020002  00     offcore_response.demand_rfo.supplier_none.snoop_none cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x80020002  00     offcore_response.demand_rfo.supplier_none.snoop_not_needed cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x100020002  00     offcore_response.demand_rfo.supplier_none.spl_hit cache Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x40020002  00     offcore_response.other.l3_hit.any_snoop cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC01C8000  00     offcore_response.other.l3_hit.snoop_hitm cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x10001C8000  00     offcore_response.other.l3_hit.snoop_hit_no_fwd cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x4001C8000  00     offcore_response.other.l3_hit.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x2001C8000  00     offcore_response.other.l3_hit.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x801C8000  00     offcore_response.other.l3_hit.snoop_not_needed cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x1001C8000  00     offcore_response.other.l3_hit.spl_hit cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x401C8000  00     offcore_response.other.l3_hit_e.any_snoop cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0088000  00     offcore_response.other.l3_hit_e.snoop_hitm cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x1000088000  00     offcore_response.other.l3_hit_e.snoop_hit_no_fwd cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x400088000  00     offcore_response.other.l3_hit_e.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x200088000  00     offcore_response.other.l3_hit_e.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x80088000  00     offcore_response.other.l3_hit_e.snoop_not_needed cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x100088000  00     offcore_response.other.l3_hit_e.spl_hit cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x40088000  00     offcore_response.other.l3_hit_m.any_snoop cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0048000  00     offcore_response.other.l3_hit_m.snoop_hitm cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x1000048000  00     offcore_response.other.l3_hit_m.snoop_hit_no_fwd cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x400048000  00     offcore_response.other.l3_hit_m.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x200048000  00     offcore_response.other.l3_hit_m.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x80048000  00     offcore_response.other.l3_hit_m.snoop_not_needed cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x100048000  00     offcore_response.other.l3_hit_m.spl_hit cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x40048000  00     offcore_response.other.l3_hit_s.any_snoop cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0108000  00     offcore_response.other.l3_hit_s.snoop_hitm cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x1000108000  00     offcore_response.other.l3_hit_s.snoop_hit_no_fwd cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x400108000  00     offcore_response.other.l3_hit_s.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x200108000  00     offcore_response.other.l3_hit_s.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x80108000  00     offcore_response.other.l3_hit_s.snoop_not_needed cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x100108000  00     offcore_response.other.l3_hit_s.spl_hit cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x40108000  00     offcore_response.other.l4_hit_local_l4.any_snoop cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0408000  00     offcore_response.other.l4_hit_local_l4.snoop_hitm cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x1000408000  00     offcore_response.other.l4_hit_local_l4.snoop_hit_no_fwd cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x400408000  00     offcore_response.other.l4_hit_local_l4.snoop_miss cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x200408000  00     offcore_response.other.l4_hit_local_l4.snoop_none cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x80408000  00     offcore_response.other.l4_hit_local_l4.snoop_not_needed cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x100408000  00     offcore_response.other.l4_hit_local_l4.spl_hit cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x40408000  00     offcore_response.other.supplier_none.any_snoop cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC0028000  00     offcore_response.other.supplier_none.spl_hit cache Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x40028000  00     offcore_response.demand_code_rd.l3_hit.snoop_non_dram memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x20001C0004  00     offcore_response.demand_code_rd.l3_hit_e.snoop_non_dram memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000080004  00     offcore_response.demand_code_rd.l3_hit_m.snoop_non_dram memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000040004  00     offcore_response.demand_code_rd.l3_hit_s.snoop_non_dram memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000100004  00     offcore_response.demand_code_rd.l3_miss.any_snoop memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFC400004  00     offcore_response.demand_code_rd.l3_miss.snoop_hitm memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x103C400004  00     offcore_response.demand_code_rd.l3_miss.snoop_hit_no_fwd memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x43C400004  00     offcore_response.demand_code_rd.l3_miss.snoop_miss memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x23C400004  00     offcore_response.demand_code_rd.l3_miss.snoop_none memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0xBC400004  00     offcore_response.demand_code_rd.l3_miss.snoop_non_dram memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x203C400004  00     offcore_response.demand_code_rd.l3_miss.snoop_not_needed memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x13C400004  00     offcore_response.demand_code_rd.l3_miss.spl_hit memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x7C400004  00     offcore_response.demand_code_rd.l3_miss_local_dram.any_snoop memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC4000004  00     offcore_response.demand_code_rd.l3_miss_local_dram.spl_hit memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x44000004  00     offcore_response.demand_code_rd.l4_hit_local_l4.snoop_non_dram memory Counts all demand code reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000400004  00     offcore_response.demand_data_rd.l3_hit.snoop_non_dram memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x20001C0001  00     offcore_response.demand_data_rd.l3_hit_e.snoop_non_dram memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000080001  00     offcore_response.demand_data_rd.l3_hit_m.snoop_non_dram memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000040001  00     offcore_response.demand_data_rd.l3_hit_s.snoop_non_dram memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000100001  00     offcore_response.demand_data_rd.l3_miss.any_snoop memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFC400001  00     offcore_response.demand_data_rd.l3_miss.snoop_hitm memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x103C400001  00     offcore_response.demand_data_rd.l3_miss.snoop_hit_no_fwd memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x43C400001  00     offcore_response.demand_data_rd.l3_miss.snoop_miss memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x23C400001  00     offcore_response.demand_data_rd.l3_miss.snoop_none memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0xBC400001  00     offcore_response.demand_data_rd.l3_miss.snoop_non_dram memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x203C400001  00     offcore_response.demand_data_rd.l3_miss.snoop_not_needed memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x13C400001  00     offcore_response.demand_data_rd.l3_miss.spl_hit memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x7C400001  00     offcore_response.demand_data_rd.l3_miss_local_dram.any_snoop memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC4000001  00     offcore_response.demand_data_rd.l3_miss_local_dram.spl_hit memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x44000001  00     offcore_response.demand_data_rd.l4_hit_local_l4.snoop_non_dram memory Counts demand data reads event=0xb7,period=100003,umask=1,offcore_rsp=0x2000400001  00     offcore_response.demand_rfo.l3_hit.snoop_non_dram memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x20001C0002  00     offcore_response.demand_rfo.l3_hit_e.snoop_non_dram memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x2000080002  00     offcore_response.demand_rfo.l3_hit_m.snoop_non_dram memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x2000040002  00     offcore_response.demand_rfo.l3_hit_s.snoop_non_dram memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x2000100002  00     offcore_response.demand_rfo.l3_miss.any_snoop memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFC400002  00     offcore_response.demand_rfo.l3_miss.snoop_hitm memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x103C400002  00     offcore_response.demand_rfo.l3_miss.snoop_hit_no_fwd memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x43C400002  00     offcore_response.demand_rfo.l3_miss.snoop_miss memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x23C400002  00     offcore_response.demand_rfo.l3_miss.snoop_none memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0xBC400002  00     offcore_response.demand_rfo.l3_miss.snoop_non_dram memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x203C400002  00     offcore_response.demand_rfo.l3_miss.snoop_not_needed memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x13C400002  00     offcore_response.demand_rfo.l3_miss.spl_hit memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x7C400002  00     offcore_response.demand_rfo.l3_miss_local_dram.any_snoop memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC4000002  00     offcore_response.demand_rfo.l3_miss_local_dram.snoop_hitm memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x1004000002  00     offcore_response.demand_rfo.l3_miss_local_dram.snoop_hit_no_fwd memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x404000002  00     offcore_response.demand_rfo.l3_miss_local_dram.snoop_miss memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x204000002  00     offcore_response.demand_rfo.l3_miss_local_dram.snoop_none memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x84000002  00     offcore_response.demand_rfo.l3_miss_local_dram.snoop_non_dram memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x2004000002  00     offcore_response.demand_rfo.l3_miss_local_dram.snoop_not_needed memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x104000002  00     offcore_response.demand_rfo.l3_miss_local_dram.spl_hit memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x44000002  00     offcore_response.demand_rfo.l4_hit_local_l4.snoop_non_dram memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x2000400002  00     offcore_response.demand_rfo.supplier_none.snoop_non_dram memory Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=1,offcore_rsp=0x2000020002  00     offcore_response.other.l3_hit.snoop_non_dram memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x20001C8000  00     offcore_response.other.l3_hit_e.snoop_non_dram memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x2000088000  00     offcore_response.other.l3_hit_m.snoop_non_dram memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x2000048000  00     offcore_response.other.l3_hit_s.snoop_non_dram memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x2000108000  00     offcore_response.other.l3_miss.any_snoop memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x3FFC408000  00     offcore_response.other.l3_miss.snoop_hitm memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x103C408000  00     offcore_response.other.l3_miss.snoop_hit_no_fwd memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x43C408000  00     offcore_response.other.l3_miss.snoop_miss memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x23C408000  00     offcore_response.other.l3_miss.snoop_none memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0xBC408000  00     offcore_response.other.l3_miss.snoop_non_dram memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x203C408000  00     offcore_response.other.l3_miss.snoop_not_needed memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x13C408000  00     offcore_response.other.l3_miss.spl_hit memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x7C408000  00     offcore_response.other.l3_miss_local_dram.any_snoop memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x3FC4008000  00     offcore_response.other.l3_miss_local_dram.spl_hit memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x44008000  00     offcore_response.other.l4_hit_local_l4.snoop_non_dram memory Counts any other requests event=0xb7,period=100003,umask=1,offcore_rsp=0x2000408000  00     memory_disambiguation.history_reset other MEMORY_DISAMBIGUATION.HISTORY_RESET event=9,period=2000003,umask=1  00     load_hit_pre.sw_pf pipeline Demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch event=0x4c,period=100003,umask=1  00    Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions unc_arb_trk_occupancy.all uncore interconnect Number of all Core entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk. Accounts for Coherent and non-coherent traffic event=0x80,umask=1  01     unc_arb_trk_occupancy.data_read uncore interconnect Number of Core Data Read entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk event=0x80,umask=2  01     unc_arb_trk_requests.all uncore interconnect UNC_ARB_TRK_REQUESTS.ALL event=0x81,umask=1  01     unc_arb_trk_requests.data_read uncore interconnect Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent event=0x81,umask=2  01     unc_arb_trk_requests.drd_direct uncore interconnect Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent event=0x81,umask=2  01     mem_load_l3_miss_retired.remote_fwd cache Retired load instructions whose data sources was forwarded from a remote cache  Supports address when precise (Precise event) event=0xd3,period=100007,umask=8  00     offcore_response.all_data_rd.any_response cache Counts all demand & prefetch data reads that have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10491  00     offcore_response.all_data_rd.l3_hit.any_snoop cache Counts all demand & prefetch data reads that hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0491  00     offcore_response.all_data_rd.l3_hit.hitm_other_core cache Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0491  00     offcore_response.all_data_rd.l3_hit.hit_other_core_no_fwd cache Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0491  00     offcore_response.all_data_rd.l3_hit.no_snoop_needed cache Counts all demand & prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0491  00     offcore_response.all_data_rd.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0491  00     offcore_response.all_pf_data_rd.any_response cache Counts all prefetch data reads that have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10490  00     offcore_response.all_pf_data_rd.l3_hit.any_snoop cache Counts all prefetch data reads that hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0490  00     offcore_response.all_pf_data_rd.l3_hit.hitm_other_core cache Counts all prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0490  00     offcore_response.all_pf_data_rd.l3_hit.hit_other_core_no_fwd cache Counts all prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0490  00     offcore_response.all_pf_data_rd.l3_hit.no_snoop_needed cache Counts all prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0490  00     offcore_response.all_pf_data_rd.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0490  00     offcore_response.all_pf_rfo.any_response cache Counts prefetch RFOs that have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10120  00     offcore_response.all_pf_rfo.l3_hit.any_snoop cache Counts prefetch RFOs that hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0120  00     offcore_response.all_pf_rfo.l3_hit.hitm_other_core cache Counts prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0120  00     offcore_response.all_pf_rfo.l3_hit.hit_other_core_no_fwd cache Counts prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0120  00     offcore_response.all_pf_rfo.l3_hit.no_snoop_needed cache Counts prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0120  00     offcore_response.all_pf_rfo.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0120  00     offcore_response.all_reads.l3_hit.hit_other_core_fwd cache OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD hit in the L3 and the snoop to one of the sibling cores hits the line in E/S/F state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C07F7  00     offcore_response.all_rfo.any_response cache Counts all demand & prefetch RFOs that have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10122  00     offcore_response.all_rfo.l3_hit.any_snoop cache Counts all demand & prefetch RFOs that hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0122  00     offcore_response.all_rfo.l3_hit.hitm_other_core cache Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0122  00     offcore_response.all_rfo.l3_hit.hit_other_core_no_fwd cache Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0122  00     offcore_response.all_rfo.l3_hit.no_snoop_needed cache Counts all demand & prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0122  00     offcore_response.all_rfo.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0122  00     offcore_response.demand_code_rd.any_response cache Counts all demand code reads that have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10004  00     offcore_response.demand_code_rd.l3_hit.any_snoop cache Counts all demand code reads that hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0004  00     offcore_response.demand_code_rd.l3_hit.hitm_other_core cache Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0004  00     offcore_response.demand_code_rd.l3_hit.hit_other_core_no_fwd cache Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0004  00     offcore_response.demand_code_rd.l3_hit.no_snoop_needed cache Counts all demand code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0004  00     offcore_response.demand_code_rd.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0004  00     offcore_response.demand_data_rd.any_response cache Counts demand data reads that have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10001  00     offcore_response.demand_data_rd.l3_hit.any_snoop cache Counts demand data reads that hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0001  00     offcore_response.demand_data_rd.l3_hit.hitm_other_core cache Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0001  00     offcore_response.demand_data_rd.l3_hit.hit_other_core_no_fwd cache Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0001  00     offcore_response.demand_data_rd.l3_hit.no_snoop_needed cache Counts demand data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0001  00     offcore_response.demand_data_rd.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0001  00     offcore_response.demand_rfo.any_response cache Counts all demand data writes (RFOs) that have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10002  00     offcore_response.demand_rfo.l3_hit.any_snoop cache Counts all demand data writes (RFOs) that hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0002  00     offcore_response.demand_rfo.l3_hit.hitm_other_core cache Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0002  00     offcore_response.demand_rfo.l3_hit.hit_other_core_no_fwd cache Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0002  00     offcore_response.demand_rfo.l3_hit.no_snoop_needed cache Counts all demand data writes (RFOs) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0002  00     offcore_response.demand_rfo.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0002  00     offcore_response.pf_l1d_and_sw.any_response cache Counts L1 data cache hardware prefetch requests and software prefetch requests that have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10400  00     offcore_response.pf_l1d_and_sw.l3_hit.any_snoop cache Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0400  00     offcore_response.pf_l1d_and_sw.l3_hit.hitm_other_core cache Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0400  00     offcore_response.pf_l1d_and_sw.l3_hit.hit_other_core_no_fwd cache Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0400  00     offcore_response.pf_l1d_and_sw.l3_hit.no_snoop_needed cache Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0400  00     offcore_response.pf_l1d_and_sw.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0400  00     offcore_response.pf_l2_data_rd.any_response cache Counts prefetch (that bring data to L2) data reads that have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10010  00     offcore_response.pf_l2_data_rd.l3_hit.any_snoop cache Counts prefetch (that bring data to L2) data reads that hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0010  00     offcore_response.pf_l2_data_rd.l3_hit.hitm_other_core cache Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0010  00     offcore_response.pf_l2_data_rd.l3_hit.hit_other_core_no_fwd cache Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0010  00     offcore_response.pf_l2_data_rd.l3_hit.no_snoop_needed cache Counts prefetch (that bring data to L2) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0010  00     offcore_response.pf_l2_data_rd.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0010  00     offcore_response.pf_l2_rfo.any_response cache Counts all prefetch (that bring data to L2) RFOs that have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10020  00     offcore_response.pf_l2_rfo.l3_hit.any_snoop cache Counts all prefetch (that bring data to L2) RFOs that hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0020  00     offcore_response.pf_l2_rfo.l3_hit.hitm_other_core cache Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0020  00     offcore_response.pf_l2_rfo.l3_hit.hit_other_core_no_fwd cache Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0020  00     offcore_response.pf_l2_rfo.l3_hit.no_snoop_needed cache Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0020  00     offcore_response.pf_l2_rfo.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0020  00     offcore_response.pf_l3_data_rd.any_response cache Counts all prefetch (that bring data to LLC only) data reads that have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10080  00     offcore_response.pf_l3_data_rd.l3_hit.any_snoop cache Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0080  00     offcore_response.pf_l3_data_rd.l3_hit.hitm_other_core cache Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0080  00     offcore_response.pf_l3_data_rd.l3_hit.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0080  00     offcore_response.pf_l3_data_rd.l3_hit.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0080  00     offcore_response.pf_l3_data_rd.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0080  00     offcore_response.pf_l3_rfo.any_response cache Counts all prefetch (that bring data to LLC only) RFOs that have any response type event=0xb7,period=100003,umask=1,offcore_rsp=0x10100  00     offcore_response.pf_l3_rfo.l3_hit.any_snoop cache Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3F803C0100  00     offcore_response.pf_l3_rfo.l3_hit.hitm_other_core cache Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x10003C0100  00     offcore_response.pf_l3_rfo.l3_hit.hit_other_core_no_fwd cache Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=1,offcore_rsp=0x4003C0100  00     offcore_response.pf_l3_rfo.l3_hit.no_snoop_needed cache Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=1,offcore_rsp=0x1003C0100  00     offcore_response.pf_l3_rfo.l3_hit.snoop_hit_with_fwd cache OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0100  00     fp_arith_inst_retired.512b_packed_double floating point Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=2000003,umask=0x40  00    Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired.512b_packed_single floating point Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc7,period=2000003,umask=0x80  00    Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events offcore_response.all_data_rd.l3_miss.any_snoop memory Counts all demand & prefetch data reads that miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000491  00     offcore_response.all_data_rd.l3_miss.remote_hitm memory Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00491  00     offcore_response.all_data_rd.l3_miss.remote_hit_forward memory Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00491  00     offcore_response.all_data_rd.l3_miss.snoop_miss_or_no_fwd memory Counts all demand & prefetch data reads that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63FC00491  00     offcore_response.all_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x604000491  00     offcore_response.all_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800491  00     offcore_response.all_pf_data_rd.l3_miss.any_snoop memory Counts all prefetch data reads that miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000490  00     offcore_response.all_pf_data_rd.l3_miss.remote_hitm memory Counts all prefetch data reads that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00490  00     offcore_response.all_pf_data_rd.l3_miss.remote_hit_forward memory Counts all prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00490  00     offcore_response.all_pf_data_rd.l3_miss.snoop_miss_or_no_fwd memory Counts all prefetch data reads that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63FC00490  00     offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all prefetch data reads that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x604000490  00     offcore_response.all_pf_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all prefetch data reads that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800490  00     offcore_response.all_pf_rfo.l3_miss.any_snoop memory Counts prefetch RFOs that miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000120  00     offcore_response.all_pf_rfo.l3_miss.remote_hitm memory Counts prefetch RFOs that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00120  00     offcore_response.all_pf_rfo.l3_miss.remote_hit_forward memory Counts prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00120  00     offcore_response.all_pf_rfo.l3_miss.snoop_miss_or_no_fwd memory Counts prefetch RFOs that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63FC00120  00     offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts prefetch RFOs that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x604000120  00     offcore_response.all_pf_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts prefetch RFOs that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800120  00     offcore_response.all_rfo.l3_miss.any_snoop memory Counts all demand & prefetch RFOs that miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000122  00     offcore_response.all_rfo.l3_miss.remote_hitm memory Counts all demand & prefetch RFOs that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00122  00     offcore_response.all_rfo.l3_miss.remote_hit_forward memory Counts all demand & prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00122  00     offcore_response.all_rfo.l3_miss.snoop_miss_or_no_fwd memory Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63FC00122  00     offcore_response.all_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x604000122  00     offcore_response.all_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all demand & prefetch RFOs that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800122  00     offcore_response.demand_code_rd.l3_miss.any_snoop memory Counts all demand code reads that miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000004  00     offcore_response.demand_code_rd.l3_miss.remote_hitm memory Counts all demand code reads that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00004  00     offcore_response.demand_code_rd.l3_miss.remote_hit_forward memory Counts all demand code reads that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00004  00     offcore_response.demand_code_rd.l3_miss.snoop_miss_or_no_fwd memory Counts all demand code reads that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63FC00004  00     offcore_response.demand_code_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all demand code reads that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x604000004  00     offcore_response.demand_code_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all demand code reads that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800004  00     offcore_response.demand_data_rd.l3_miss.any_snoop memory Counts demand data reads that miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000001  00     offcore_response.demand_data_rd.l3_miss.remote_hitm memory Counts demand data reads that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00001  00     offcore_response.demand_data_rd.l3_miss.remote_hit_forward memory Counts demand data reads that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00001  00     offcore_response.demand_data_rd.l3_miss.snoop_miss_or_no_fwd memory Counts demand data reads that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63FC00001  00     offcore_response.demand_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts demand data reads that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x604000001  00     offcore_response.demand_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts demand data reads that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800001  00     offcore_response.demand_rfo.l3_miss.any_snoop memory Counts all demand data writes (RFOs) that miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000002  00     offcore_response.demand_rfo.l3_miss.remote_hitm memory Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00002  00     offcore_response.demand_rfo.l3_miss.remote_hit_forward memory Counts all demand data writes (RFOs) that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00002  00     offcore_response.demand_rfo.l3_miss.snoop_miss_or_no_fwd memory Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63FC00002  00     offcore_response.demand_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x604000002  00     offcore_response.demand_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all demand data writes (RFOs) that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800002  00     offcore_response.pf_l1d_and_sw.l3_miss.any_snoop memory Counts L1 data cache hardware prefetch requests and software prefetch requests that miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000400  00     offcore_response.pf_l1d_and_sw.l3_miss.remote_hitm memory Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00400  00     offcore_response.pf_l1d_and_sw.l3_miss.remote_hit_forward memory Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00400  00     offcore_response.pf_l1d_and_sw.l3_miss.snoop_miss_or_no_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63FC00400  00     offcore_response.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x604000400  00     offcore_response.pf_l1d_and_sw.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800400  00     offcore_response.pf_l2_data_rd.l3_miss.any_snoop memory Counts prefetch (that bring data to L2) data reads that miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000010  00     offcore_response.pf_l2_data_rd.l3_miss.remote_hitm memory Counts prefetch (that bring data to L2) data reads that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00010  00     offcore_response.pf_l2_data_rd.l3_miss.remote_hit_forward memory Counts prefetch (that bring data to L2) data reads that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00010  00     offcore_response.pf_l2_data_rd.l3_miss.snoop_miss_or_no_fwd memory Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63FC00010  00     offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x604000010  00     offcore_response.pf_l2_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800010  00     offcore_response.pf_l2_rfo.l3_miss.any_snoop memory Counts all prefetch (that bring data to L2) RFOs that miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000020  00     offcore_response.pf_l2_rfo.l3_miss.remote_hitm memory Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00020  00     offcore_response.pf_l2_rfo.l3_miss.remote_hit_forward memory Counts all prefetch (that bring data to L2) RFOs that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00020  00     offcore_response.pf_l2_rfo.l3_miss.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63FC00020  00     offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x604000020  00     offcore_response.pf_l2_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800020  00     offcore_response.pf_l3_data_rd.l3_miss.any_snoop memory Counts all prefetch (that bring data to LLC only) data reads that miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000080  00     offcore_response.pf_l3_data_rd.l3_miss.remote_hitm memory Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00080  00     offcore_response.pf_l3_data_rd.l3_miss.remote_hit_forward memory Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00080  00     offcore_response.pf_l3_data_rd.l3_miss.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63FC00080  00     offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x604000080  00     offcore_response.pf_l3_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800080  00     offcore_response.pf_l3_rfo.l3_miss.any_snoop memory Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3 event=0xb7,period=100003,umask=1,offcore_rsp=0x3FBC000100  00     offcore_response.pf_l3_rfo.l3_miss.remote_hitm memory Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x103FC00100  00     offcore_response.pf_l3_rfo.l3_miss.remote_hit_forward memory Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=1,offcore_rsp=0x83FC00100  00     offcore_response.pf_l3_rfo.l3_miss.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63FC00100  00     offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=1,offcore_rsp=0x604000100  00     offcore_response.pf_l3_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd memory Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from remote dram event=0xb7,period=100003,umask=1,offcore_rsp=0x63B800100  00     unc_cha_clockticks uncore cache Clockticks of the uncore caching & home agent (CHA) event=0  01    Counts clockticks of the clock controlling the uncore caching and home agent (CHA) unc_upi_rxl_crc_errors uncore interconnect CRC Errors Detected event=0xb  01    Number of CRC errors detected in the UPI Agent.  Each UPI flit incorporates 8 bits of CRC for error detection.  This counts the number of flits where the CRC was able to detect an error.  After an error has been detected, the UPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it) unc_upi_rxl_crc_llr_req_transmit uncore interconnect LLR Requests Sent event=8  01    Number of LLR Requests were transmitted.  This should generally be <= the number of CRC errors detected.  If multiple errors are detected before the Rx side receives a LLC_REQ_ACK from the Tx side, there is no need to send more LLR_REQ_NACKs unc_m_power_channel_ppd uncore memory Cycles where DRAM ranks are in power down (CKE) mode event=0x85  01    Counts cycles when all the ranks in the channel are in PPD (PreCharge Power Down) mode. If IBT (Input Buffer Terminators)=off is enabled, then this event counts the cycles in PPD mode. If IBT=off is not enabled, then this event counts the number of cycles when being in PPD mode could have been taken advantage of unc_cha_clockticks uncore cache Uncore cache clock ticks event=0  01     unc_cha_llc_lookup.code uncore cache This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ event=0x34,umask=0x1bd0ff  11     unc_cha_llc_lookup.dmnd_read_local uncore cache This event is deprecated event=0x34,umask=0x841ff  11     unc_cha_llc_lookup.rfo_pref_local uncore cache This event is deprecated event=0x34,umask=0x888ff  11     unc_cha_llc_lookup.write_local uncore cache This event is deprecated event=0x34,umask=0x842ff  11     unc_m2m_prefcam_demand_merge.ch0_xpt uncore interconnect Demands Merged with CAMed Prefetches : XPT - Ch 0 event=0x74,umask=1  01     unc_m2m_prefcam_demand_merge.ch1_xpt uncore interconnect Demands Merged with CAMed Prefetches : XPT - Ch 1 event=0x74,umask=4  01     unc_m2m_prefcam_demand_merge.xpt_allch uncore interconnect Demands Merged with CAMed Prefetches : XPT - All Channels event=0x74,umask=0x15  01     unc_m2m_prefcam_demand_no_merge.ch0_xpt uncore interconnect Demands Not Merged with CAMed Prefetches : XPT - Ch 0 event=0x75,umask=1  01     unc_m2m_prefcam_demand_no_merge.ch1_xpt uncore interconnect Demands Not Merged with CAMed Prefetches : XPT - Ch 1 event=0x75,umask=4  01     unc_m2m_prefcam_demand_no_merge.xpt_allch uncore interconnect Demands Not Merged with CAMed Prefetches : XPT - All Channels event=0x75,umask=0x15  01     llc_misses.pcie_read uncore io PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0 event=0x83,ch_mask=1,fc_mask=7,umask=4,ch_mask=0x1f  014Bytes    Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 llc_misses.pcie_write uncore io PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0 event=0x83,ch_mask=1,fc_mask=7,umask=1,ch_mask=0x1f  014Bytes    Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_clockticks uncore io Clockticks of the integrated IO (IIO) traffic controller event=1  01     unc_iio_data_req_of_cpu.mem_read.part0 uncore io PCI Express bandwidth reading at IIO, part 0 event=0x83,ch_mask=1,fc_mask=7,umask=4  01    Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.mem_read.part1 uncore io PCI Express bandwidth reading at IIO, part 1 event=0x83,ch_mask=2,fc_mask=7,umask=4  01    Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_read.part2 uncore io PCI Express bandwidth reading at IIO, part 2 event=0x83,ch_mask=4,fc_mask=7,umask=4  01    Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.mem_read.part3 uncore io PCI Express bandwidth reading at IIO, part 3 event=0x83,ch_mask=8,fc_mask=7,umask=4  01    Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.mem_write.part0 uncore io PCI Express bandwidth writing at IIO, part 0 event=0x83,ch_mask=1,fc_mask=7,umask=1  01    Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.mem_write.part1 uncore io PCI Express bandwidth writing at IIO, part 1 event=0x83,ch_mask=2,fc_mask=7,umask=1  01    Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_write.part2 uncore io PCI Express bandwidth writing at IIO, part 2 event=0x83,ch_mask=4,fc_mask=7,umask=1  01    Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 unc_iio_data_req_of_cpu.mem_write.part3 uncore io PCI Express bandwidth writing at IIO, part 3 event=0x83,ch_mask=8,fc_mask=7,umask=1  01    Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_m2p_clockticks uncore io Clockticks of the mesh to PCI (M2P) event=1  01     llc_misses.mem_read uncore memory read requests to memory controller. Derived from unc_m_cas_count.rd event=4,umask=0xf  0164Bytes    Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issued on this channel.  This includes underfills llc_misses.mem_write uncore memory write requests to memory controller. Derived from unc_m_cas_count.wr event=4,umask=0x30  0164Bytes    Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-pre, on this channel unc_m_clockticks uncore memory Memory controller clock ticks event=0  01    Clockticks of the integrated memory controller (IMC) unc_m_power_channel_ppd uncore memory Cycles where DRAM ranks are in power down (CKE) mode event=0x85  01    Channel PPD Cycles : Number of cycles when all the ranks in the channel are in PPD mode.  If IBT=off is enabled, then this can be used to count those cycles.  If it is not enabled, then this can count the number of cycles when that could have been taken advantage of unc_m_power_self_refresh uncore memory Cycles Memory is in self refresh power mode event=0x43  01    Clock-Enabled Self-Refresh : Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock.  This happens in some package C-states.  For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing.  One use of this is for Monroe technology.  Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases unc_m_pre_count.page_miss uncore memory Pre-charges due to page misses event=2,umask=0xc  01    DRAM Precharge commands. : Precharge due to page miss : Counts the number of DRAM Precharge commands sent on this channel. : Pages Misses are due to precharges from bank scheduler (rd/wr requests) unc_m_pre_count.rd uncore memory Pre-charge for reads event=2,umask=4  01    DRAM Precharge commands. : Precharge due to read : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from read bank scheduler unc_m_pre_count.wr uncore memory Pre-charge for writes event=2,umask=8  01    DRAM Precharge commands. : Precharge due to write : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from write bank scheduler unc_p_clockticks uncore power Clockticks of the power control unit (PCU) event=0  01     l2_rqsts.miss cache Read requests with true-miss in L2 cache event=0x24,period=200003,umask=0x3f  00    Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses l2_rqsts.references cache All accesses to L2 cache event=0x24,period=200003,umask=0xff  00    Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses mem_load_l3_hit_retired.xsnp_fwd cache Snoop hit a modified(HITM) or clean line(HIT_W_FWD) in another on-pkg core which forwarded the data back due to a retired load instruction  Supports address when precise event=0xd2,period=20011,umask=4  00    Counts retired load instructions where a cross-core snoop hit in another cores caches on this socket, the data was forwarded back to the requesting core as the data was modified (SNOOP_HITM) or the L3 did not have the data(SNOOP_HIT_WITH_FWD)  Supports address when precise mem_load_l3_hit_retired.xsnp_no_fwd cache Snoop hit without forwarding in another on-pkg core due to a retired load instruction, data was supplied by the L3  Supports address when precise event=0xd2,period=20011,umask=2  00    Counts retired load instructions in which the L3 supplied the data and a cross-core snoop hit in another cores caches on this socket but that other core did not forward the data back (SNOOP_HIT_NO_FWD)  Supports address when precise mem_load_misc_retired.uc cache Retired instructions with at least 1 uncacheable load or lock  Supports address when precise event=0xd4,period=100007,umask=4  00    Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access  Supports address when precise ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd cache Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches which forwarded the data to the requesting core event=0xb7,period=100003,umask=1,offcore_rsp=0x8003C0001  00     offcore_requests_outstanding.all_data_rd cache Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore event=0x60,period=1000003,umask=8  00    Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.cycles_with_data_rd cache Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore event=0x60,cmask=1,period=1000003,umask=8  00    Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.cycles_with_demand_code_rd cache Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore event=0x60,cmask=1,period=1000003,umask=2  00    Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.cycles_with_demand_rfo cache Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore event=0x60,cmask=1,period=1000003,umask=4  00    Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS offcore_requests_outstanding.demand_data_rd cache Demand Data Read transactions pending for off-core. Highly correlated event=0x60,period=1000003,umask=1  00    Counts the number of off-core outstanding Demand Data Read transactions every cycle. A transaction is considered to be in the Off-core outstanding state between L2 cache miss and data-return to the core sq_misc.sq_full cache Cycles the superQ cannot take any more entries event=0xf4,period=100003,umask=4  00    Counts the cycles for which the thread is active and the superQ cannot take any more entries exe_activity.bound_on_loads pipeline Cycles when the memory subsystem has an outstanding load. Increments by 4 for every such cycle event=0xa6,cmask=5,period=2000003,umask=0x21  00    Counts cycles when the memory subsystem has an outstanding load. Increments by 4 for every such cycle inst_retired.any pipeline Number of instructions retired. Fixed Counter - architectural event event=0xc0,period=2000003  00    Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter ld_blocks_partial.address_alias pipeline False dependencies in MOB due to partial compare on address event=7,period=100003,umask=1  00    Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on address uops_issued.vector_width_mismatch pipeline Uops inserted at issue-stage in order to preserve upper bits of vector registers event=0xe,period=100003,umask=2  00    Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide unc_arb_trk_occupancy.all uncore interconnect Each cycle count number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from it's allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic event=0x80,umask=1  01     unc_mc0_rdcas_count_freerun uncore memory Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM event=0xff,umask=0x20  01     unc_mc0_total_reqcount_freerun uncore memory Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM event=0xff,umask=0x10  01     unc_mc0_wrcas_count_freerun uncore memory Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM event=0xff,umask=0x30  01     unc_mc1_rdcas_count_freerun uncore memory Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM event=0xff,umask=0x20  01     unc_mc1_total_reqcount_freerun uncore memory Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM event=0xff,umask=0x10  01     unc_mc1_wrcas_count_freerun uncore memory Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM event=0xff,umask=0x30  01     dtlb_store_misses.walk_completed_1g virtual memory Page walks completed due to a demand data store to a 1G page event=0x49,period=100003,umask=8  00    Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 1G pages.  The page walks can end with or without a page fault dtlb_store_misses.walk_completed_2m_4m virtual memory Page walks completed due to a demand data store to a 2M/4M page event=0x49,period=100003,umask=4  00    Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M/4M pages.  The page walks can end with or without a page fault dtlb_store_misses.walk_completed_4k virtual memory Page walks completed due to a demand data store to a 4K page event=0x49,period=100003,umask=2  00    Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages.  The page walks can end with or without a page fault offcore_requests.any cache All offcore requests event=0xb0,period=100000,umask=0x80  00     offcore_requests.any.read cache Offcore read requests event=0xb0,period=100000,umask=8  00     offcore_requests.any.rfo cache Offcore RFO requests event=0xb0,period=100000,umask=0x10  00     offcore_requests.demand.read_code cache Offcore demand code read requests event=0xb0,period=100000,umask=2  00     offcore_requests.demand.read_data cache Offcore demand data read requests event=0xb0,period=100000,umask=1  00     offcore_requests.demand.rfo cache Offcore demand RFO requests event=0xb0,period=100000,umask=4  00     offcore_requests_outstanding.any.read cache Outstanding offcore reads event=0x60,period=2000000,umask=8  00     offcore_requests_outstanding.any.read_not_empty cache Cycles offcore reads busy event=0x60,cmask=1,period=2000000,umask=8  00     offcore_requests_outstanding.demand.read_code cache Outstanding offcore demand code reads event=0x60,period=2000000,umask=2  00     offcore_requests_outstanding.demand.read_code_not_empty cache Cycles offcore demand code read busy event=0x60,cmask=1,period=2000000,umask=2  00     offcore_requests_outstanding.demand.read_data cache Outstanding offcore demand data reads event=0x60,period=2000000,umask=1  00     offcore_requests_outstanding.demand.read_data_not_empty cache Cycles offcore demand data read busy event=0x60,cmask=1,period=2000000,umask=1  00     offcore_requests_outstanding.demand.rfo cache Outstanding offcore demand RFOs event=0x60,period=2000000,umask=4  00     offcore_requests_outstanding.demand.rfo_not_empty cache Cycles offcore demand RFOs busy event=0x60,cmask=1,period=2000000,umask=4  00     offcore_response.any_data.all_local_dram_and_remote_cache_hit cache REQUEST = ANY_DATA read and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x5011  00     offcore_response.any_data.any_cache_dram cache REQUEST = ANY_DATA read and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7f11  00     offcore_response.any_data.any_location cache REQUEST = ANY_DATA read and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xff11  00     offcore_response.any_data.io_csr_mmio cache REQUEST = ANY_DATA read and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x8011  00     offcore_response.any_data.llc_hit_no_other_core cache REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x111  00     offcore_response.any_data.llc_hit_other_core_hit cache REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x211  00     offcore_response.any_data.llc_hit_other_core_hitm cache REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x411  00     offcore_response.any_data.local_cache cache REQUEST = ANY_DATA read and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x711  00     offcore_response.any_data.local_dram_and_remote_cache_hit cache REQUEST = ANY_DATA read and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x1011  00     offcore_response.any_data.remote_cache_hitm cache REQUEST = ANY_DATA read and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x811  00     offcore_response.any_ifetch.all_local_dram_and_remote_cache_hit cache REQUEST = ANY IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x5044  00     offcore_response.any_ifetch.any_cache_dram cache REQUEST = ANY IFETCH and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7f44  00     offcore_response.any_ifetch.any_location cache REQUEST = ANY IFETCH and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xff44  00     offcore_response.any_ifetch.io_csr_mmio cache REQUEST = ANY IFETCH and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x8044  00     offcore_response.any_ifetch.llc_hit_no_other_core cache REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x144  00     offcore_response.any_ifetch.llc_hit_other_core_hit cache REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x244  00     offcore_response.any_ifetch.llc_hit_other_core_hitm cache REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x444  00     offcore_response.any_ifetch.local_cache cache REQUEST = ANY IFETCH and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x744  00     offcore_response.any_ifetch.local_dram_and_remote_cache_hit cache REQUEST = ANY IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x1044  00     offcore_response.any_ifetch.remote_cache_hitm cache REQUEST = ANY IFETCH and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x844  00     offcore_response.any_request.all_local_dram_and_remote_cache_hit cache REQUEST = ANY_REQUEST and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x50ff  00     offcore_response.any_request.any_cache_dram cache REQUEST = ANY_REQUEST and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7fff  00     offcore_response.any_request.any_location cache REQUEST = ANY_REQUEST and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xffff  00     offcore_response.any_request.io_csr_mmio cache REQUEST = ANY_REQUEST and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x80ff  00     offcore_response.any_request.llc_hit_no_other_core cache REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x1ff  00     offcore_response.any_request.llc_hit_other_core_hit cache REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x2ff  00     offcore_response.any_request.llc_hit_other_core_hitm cache REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x4ff  00     offcore_response.any_request.local_cache cache REQUEST = ANY_REQUEST and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x7ff  00     offcore_response.any_request.local_dram_and_remote_cache_hit cache REQUEST = ANY_REQUEST and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x10ff  00     offcore_response.any_request.remote_cache_hitm cache REQUEST = ANY_REQUEST and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x8ff  00     offcore_response.any_rfo.all_local_dram_and_remote_cache_hit cache REQUEST = ANY RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x5022  00     offcore_response.any_rfo.any_cache_dram cache REQUEST = ANY RFO and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7f22  00     offcore_response.any_rfo.any_location cache REQUEST = ANY RFO and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xff22  00     offcore_response.any_rfo.io_csr_mmio cache REQUEST = ANY RFO and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x8022  00     offcore_response.any_rfo.llc_hit_no_other_core cache REQUEST = ANY RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x122  00     offcore_response.any_rfo.llc_hit_other_core_hit cache REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x222  00     offcore_response.any_rfo.llc_hit_other_core_hitm cache REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x422  00     offcore_response.any_rfo.local_cache cache REQUEST = ANY RFO and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x722  00     offcore_response.any_rfo.local_dram_and_remote_cache_hit cache REQUEST = ANY RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x1022  00     offcore_response.any_rfo.remote_cache_hitm cache REQUEST = ANY RFO and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x822  00     offcore_response.corewb.all_local_dram_and_remote_cache_hit cache REQUEST = CORE_WB and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x5008  00     offcore_response.corewb.any_cache_dram cache REQUEST = CORE_WB and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7f08  00     offcore_response.corewb.any_location cache REQUEST = CORE_WB and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xff08  00     offcore_response.corewb.io_csr_mmio cache REQUEST = CORE_WB and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x8008  00     offcore_response.corewb.llc_hit_no_other_core cache REQUEST = CORE_WB and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x108  00     offcore_response.corewb.llc_hit_other_core_hit cache REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x208  00     offcore_response.corewb.llc_hit_other_core_hitm cache REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x408  00     offcore_response.corewb.local_cache cache REQUEST = CORE_WB and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x708  00     offcore_response.corewb.local_dram_and_remote_cache_hit cache REQUEST = CORE_WB and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x1008  00     offcore_response.corewb.remote_cache_hitm cache REQUEST = CORE_WB and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x808  00     offcore_response.data_ifetch.all_local_dram_and_remote_cache_hit cache REQUEST = DATA_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x5077  00     offcore_response.data_ifetch.any_cache_dram cache REQUEST = DATA_IFETCH and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7f77  00     offcore_response.data_ifetch.any_location cache REQUEST = DATA_IFETCH and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xff77  00     offcore_response.data_ifetch.io_csr_mmio cache REQUEST = DATA_IFETCH and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x8077  00     offcore_response.data_ifetch.llc_hit_no_other_core cache REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x177  00     offcore_response.data_ifetch.llc_hit_other_core_hit cache REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x277  00     offcore_response.data_ifetch.llc_hit_other_core_hitm cache REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x477  00     offcore_response.data_ifetch.local_cache cache REQUEST = DATA_IFETCH and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x777  00     offcore_response.data_ifetch.local_dram_and_remote_cache_hit cache REQUEST = DATA_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x1077  00     offcore_response.data_ifetch.remote_cache_hitm cache REQUEST = DATA_IFETCH and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x877  00     offcore_response.data_in.all_local_dram_and_remote_cache_hit cache REQUEST = DATA_IN and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x5033  00     offcore_response.data_in.any_cache_dram cache REQUEST = DATA_IN and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7f33  00     offcore_response.data_in.any_location cache REQUEST = DATA_IN and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xff33  00     offcore_response.data_in.io_csr_mmio cache REQUEST = DATA_IN and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x8033  00     offcore_response.data_in.llc_hit_no_other_core cache REQUEST = DATA_IN and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x133  00     offcore_response.data_in.llc_hit_other_core_hit cache REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x233  00     offcore_response.data_in.llc_hit_other_core_hitm cache REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x433  00     offcore_response.data_in.local_cache cache REQUEST = DATA_IN and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x733  00     offcore_response.data_in.local_dram_and_remote_cache_hit cache REQUEST = DATA_IN and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x1033  00     offcore_response.data_in.remote_cache_hitm cache REQUEST = DATA_IN and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x833  00     offcore_response.demand_data.all_local_dram_and_remote_cache_hit cache REQUEST = DEMAND_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x5003  00     offcore_response.demand_data.any_cache_dram cache REQUEST = DEMAND_DATA and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7f03  00     offcore_response.demand_data.any_location cache REQUEST = DEMAND_DATA and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xff03  00     offcore_response.demand_data.io_csr_mmio cache REQUEST = DEMAND_DATA and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x8003  00     offcore_response.demand_data.llc_hit_no_other_core cache REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x103  00     offcore_response.demand_data.llc_hit_other_core_hit cache REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x203  00     offcore_response.demand_data.llc_hit_other_core_hitm cache REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x403  00     offcore_response.demand_data.local_cache cache REQUEST = DEMAND_DATA and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x703  00     offcore_response.demand_data.local_dram_and_remote_cache_hit cache REQUEST = DEMAND_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x1003  00     offcore_response.demand_data.remote_cache_hitm cache REQUEST = DEMAND_DATA and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x803  00     offcore_response.demand_data_rd.all_local_dram_and_remote_cache_hit cache REQUEST = DEMAND_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x5001  00     offcore_response.demand_data_rd.any_cache_dram cache REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7f01  00     offcore_response.demand_data_rd.any_location cache REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xff01  00     offcore_response.demand_data_rd.io_csr_mmio cache REQUEST = DEMAND_DATA_RD and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x8001  00     offcore_response.demand_data_rd.llc_hit_no_other_core cache REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x101  00     offcore_response.demand_data_rd.llc_hit_other_core_hit cache REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x201  00     offcore_response.demand_data_rd.llc_hit_other_core_hitm cache REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x401  00     offcore_response.demand_data_rd.local_cache cache REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x701  00     offcore_response.demand_data_rd.local_dram_and_remote_cache_hit cache REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x1001  00     offcore_response.demand_data_rd.remote_cache_hitm cache REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x801  00     offcore_response.demand_ifetch.all_local_dram_and_remote_cache_hit cache REQUEST = DEMAND_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x5004  00     offcore_response.demand_ifetch.any_cache_dram cache REQUEST = DEMAND_IFETCH and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7f04  00     offcore_response.demand_ifetch.any_location cache REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xff04  00     offcore_response.demand_ifetch.io_csr_mmio cache REQUEST = DEMAND_IFETCH and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x8004  00     offcore_response.demand_ifetch.llc_hit_no_other_core cache REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x104  00     offcore_response.demand_ifetch.llc_hit_other_core_hit cache REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x204  00     offcore_response.demand_ifetch.llc_hit_other_core_hitm cache REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x404  00     offcore_response.demand_ifetch.local_cache cache REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x704  00     offcore_response.demand_ifetch.local_dram_and_remote_cache_hit cache REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x1004  00     offcore_response.demand_ifetch.remote_cache_hitm cache REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x804  00     offcore_response.demand_rfo.all_local_dram_and_remote_cache_hit cache REQUEST = DEMAND_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x5002  00     offcore_response.demand_rfo.any_cache_dram cache REQUEST = DEMAND_RFO and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7f02  00     offcore_response.demand_rfo.any_location cache REQUEST = DEMAND_RFO and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xff02  00     offcore_response.demand_rfo.io_csr_mmio cache REQUEST = DEMAND_RFO and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x8002  00     offcore_response.demand_rfo.llc_hit_no_other_core cache REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x102  00     offcore_response.demand_rfo.llc_hit_other_core_hit cache REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x202  00     offcore_response.demand_rfo.llc_hit_other_core_hitm cache REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x402  00     offcore_response.demand_rfo.local_cache cache REQUEST = DEMAND_RFO and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x702  00     offcore_response.demand_rfo.local_dram_and_remote_cache_hit cache REQUEST = DEMAND_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x1002  00     offcore_response.demand_rfo.remote_cache_hitm cache REQUEST = DEMAND_RFO and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x802  00     offcore_response.other.all_local_dram_and_remote_cache_hit cache REQUEST = OTHER and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x5080  00     offcore_response.other.any_cache_dram cache REQUEST = OTHER and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7f80  00     offcore_response.other.any_location cache REQUEST = OTHER and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xff80  00     offcore_response.other.io_csr_mmio cache REQUEST = OTHER and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x8080  00     offcore_response.other.llc_hit_no_other_core cache REQUEST = OTHER and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x180  00     offcore_response.other.llc_hit_other_core_hit cache REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x280  00     offcore_response.other.llc_hit_other_core_hitm cache REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x480  00     offcore_response.other.local_cache cache REQUEST = OTHER and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x780  00     offcore_response.other.local_dram_and_remote_cache_hit cache REQUEST = OTHER and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x1080  00     offcore_response.other.remote_cache_hitm cache REQUEST = OTHER and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x880  00     offcore_response.pf_data.all_local_dram_and_remote_cache_hit cache REQUEST = PF_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x5050  00     offcore_response.pf_data.any_cache_dram cache REQUEST = PF_DATA and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7f50  00     offcore_response.pf_data.any_location cache REQUEST = PF_DATA and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xff50  00     offcore_response.pf_data.io_csr_mmio cache REQUEST = PF_DATA and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x8050  00     offcore_response.pf_data.llc_hit_no_other_core cache REQUEST = PF_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x150  00     offcore_response.pf_data.llc_hit_other_core_hit cache REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x250  00     offcore_response.pf_data.llc_hit_other_core_hitm cache REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x450  00     offcore_response.pf_data.local_cache cache REQUEST = PF_DATA and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x750  00     offcore_response.pf_data.local_dram_and_remote_cache_hit cache REQUEST = PF_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x1050  00     offcore_response.pf_data.remote_cache_hitm cache REQUEST = PF_DATA and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x850  00     offcore_response.pf_data_rd.all_local_dram_and_remote_cache_hit cache REQUEST = PF_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x5010  00     offcore_response.pf_data_rd.any_cache_dram cache REQUEST = PF_DATA_RD and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7f10  00     offcore_response.pf_data_rd.any_location cache REQUEST = PF_DATA_RD and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xff10  00     offcore_response.pf_data_rd.io_csr_mmio cache REQUEST = PF_DATA_RD and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x8010  00     offcore_response.pf_data_rd.llc_hit_no_other_core cache REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x110  00     offcore_response.pf_data_rd.llc_hit_other_core_hit cache REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x210  00     offcore_response.pf_data_rd.llc_hit_other_core_hitm cache REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x410  00     offcore_response.pf_data_rd.local_cache cache REQUEST = PF_DATA_RD and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x710  00     offcore_response.pf_data_rd.local_dram_and_remote_cache_hit cache REQUEST = PF_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x1010  00     offcore_response.pf_data_rd.remote_cache_hitm cache REQUEST = PF_DATA_RD and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x810  00     offcore_response.pf_ifetch.all_local_dram_and_remote_cache_hit cache REQUEST = PF_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x5040  00     offcore_response.pf_ifetch.any_cache_dram cache REQUEST = PF_RFO and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7f40  00     offcore_response.pf_ifetch.any_location cache REQUEST = PF_RFO and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xff40  00     offcore_response.pf_ifetch.io_csr_mmio cache REQUEST = PF_RFO and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x8040  00     offcore_response.pf_ifetch.llc_hit_no_other_core cache REQUEST = PF_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x140  00     offcore_response.pf_ifetch.llc_hit_other_core_hit cache REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x240  00     offcore_response.pf_ifetch.llc_hit_other_core_hitm cache REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x440  00     offcore_response.pf_ifetch.local_cache cache REQUEST = PF_RFO and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x740  00     offcore_response.pf_ifetch.local_dram_and_remote_cache_hit cache REQUEST = PF_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x1040  00     offcore_response.pf_ifetch.remote_cache_hitm cache REQUEST = PF_RFO and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x840  00     offcore_response.pf_rfo.all_local_dram_and_remote_cache_hit cache REQUEST = PF_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x5020  00     offcore_response.pf_rfo.any_cache_dram cache REQUEST = PF_IFETCH and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7f20  00     offcore_response.pf_rfo.any_location cache REQUEST = PF_IFETCH and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xff20  00     offcore_response.pf_rfo.io_csr_mmio cache REQUEST = PF_IFETCH and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x8020  00     offcore_response.pf_rfo.llc_hit_no_other_core cache REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x120  00     offcore_response.pf_rfo.llc_hit_other_core_hit cache REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x220  00     offcore_response.pf_rfo.llc_hit_other_core_hitm cache REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x420  00     offcore_response.pf_rfo.local_cache cache REQUEST = PF_IFETCH and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x720  00     offcore_response.pf_rfo.local_dram_and_remote_cache_hit cache REQUEST = PF_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x1020  00     offcore_response.pf_rfo.remote_cache_hitm cache REQUEST = PF_IFETCH and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x820  00     offcore_response.prefetch.all_local_dram_and_remote_cache_hit cache REQUEST = PREFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x5070  00     offcore_response.prefetch.any_cache_dram cache REQUEST = PREFETCH and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7f70  00     offcore_response.prefetch.any_location cache REQUEST = PREFETCH and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=1,offcore_rsp=0xff70  00     offcore_response.prefetch.io_csr_mmio cache REQUEST = PREFETCH and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=1,offcore_rsp=0x8070  00     offcore_response.prefetch.llc_hit_no_other_core cache REQUEST = PREFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=1,offcore_rsp=0x170  00     offcore_response.prefetch.llc_hit_other_core_hit cache REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x270  00     offcore_response.prefetch.llc_hit_other_core_hitm cache REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x470  00     offcore_response.prefetch.local_cache cache REQUEST = PREFETCH and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=1,offcore_rsp=0x770  00     offcore_response.prefetch.local_dram_and_remote_cache_hit cache REQUEST = PREFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=1,offcore_rsp=0x1070  00     offcore_response.prefetch.remote_cache_hitm cache REQUEST = PREFETCH and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=1,offcore_rsp=0x870  00     sq_misc.lru_hints cache Super Queue LRU hints sent to LLC event=0xf4,period=2000000,umask=4  00     misalign_mem_ref.store memory Misaligned store references event=5,period=200000,umask=2  00     offcore_response.any_data.any_dram_and_remote_fwd memory REQUEST = ANY_DATA read and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x3011  00     offcore_response.any_data.any_llc_miss memory REQUEST = ANY_DATA read and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf811  00     offcore_response.any_data.other_local_dram memory REQUEST = ANY_DATA read and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4011  00     offcore_response.any_data.remote_dram memory REQUEST = ANY_DATA read and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2011  00     offcore_response.any_ifetch.any_dram_and_remote_fwd memory REQUEST = ANY IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x3044  00     offcore_response.any_ifetch.any_llc_miss memory REQUEST = ANY IFETCH and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf844  00     offcore_response.any_ifetch.other_local_dram memory REQUEST = ANY IFETCH and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4044  00     offcore_response.any_ifetch.remote_dram memory REQUEST = ANY IFETCH and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2044  00     offcore_response.any_request.any_dram_and_remote_fwd memory REQUEST = ANY_REQUEST and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x30ff  00     offcore_response.any_request.any_llc_miss memory REQUEST = ANY_REQUEST and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf8ff  00     offcore_response.any_request.other_local_dram memory REQUEST = ANY_REQUEST and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x40ff  00     offcore_response.any_request.remote_dram memory REQUEST = ANY_REQUEST and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x20ff  00     offcore_response.any_rfo.any_dram_and_remote_fwd memory REQUEST = ANY RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x3022  00     offcore_response.any_rfo.any_llc_miss memory REQUEST = ANY RFO and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf822  00     offcore_response.any_rfo.other_local_dram memory REQUEST = ANY RFO and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4022  00     offcore_response.any_rfo.remote_dram memory REQUEST = ANY RFO and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2022  00     offcore_response.corewb.any_dram_and_remote_fwd memory REQUEST = CORE_WB and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x3008  00     offcore_response.corewb.any_llc_miss memory REQUEST = CORE_WB and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf808  00     offcore_response.corewb.other_local_dram memory REQUEST = CORE_WB and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4008  00     offcore_response.corewb.remote_dram memory REQUEST = CORE_WB and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2008  00     offcore_response.data_ifetch.any_dram_and_remote_fwd memory REQUEST = DATA_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x3077  00     offcore_response.data_ifetch.any_llc_miss memory REQUEST = DATA_IFETCH and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf877  00     offcore_response.data_ifetch.other_local_dram memory REQUEST = DATA_IFETCH and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4077  00     offcore_response.data_ifetch.remote_dram memory REQUEST = DATA_IFETCH and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2077  00     offcore_response.data_in.any_dram_and_remote_fwd memory REQUEST = DATA_IN and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x3033  00     offcore_response.data_in.any_llc_miss memory REQUEST = DATA_IN and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf833  00     offcore_response.data_in.other_local_dram memory REQUEST = DATA_IN and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4033  00     offcore_response.data_in.remote_dram memory REQUEST = DATA_IN and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2033  00     offcore_response.demand_data.any_dram_and_remote_fwd memory REQUEST = DEMAND_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x3003  00     offcore_response.demand_data.any_llc_miss memory REQUEST = DEMAND_DATA and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf803  00     offcore_response.demand_data.other_local_dram memory REQUEST = DEMAND_DATA and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4003  00     offcore_response.demand_data.remote_dram memory REQUEST = DEMAND_DATA and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2003  00     offcore_response.demand_data_rd.any_dram_and_remote_fwd memory REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x3001  00     offcore_response.demand_data_rd.any_llc_miss memory REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf801  00     offcore_response.demand_data_rd.other_local_dram memory REQUEST = DEMAND_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4001  00     offcore_response.demand_data_rd.remote_dram memory REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2001  00     offcore_response.demand_ifetch.any_dram_and_remote_fwd memory REQUEST = DEMAND_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x3004  00     offcore_response.demand_ifetch.any_llc_miss memory REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf804  00     offcore_response.demand_ifetch.other_local_dram memory REQUEST = DEMAND_IFETCH and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4004  00     offcore_response.demand_ifetch.remote_dram memory REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2004  00     offcore_response.demand_rfo.any_dram_and_remote_fwd memory REQUEST = DEMAND_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x3002  00     offcore_response.demand_rfo.any_llc_miss memory REQUEST = DEMAND_RFO and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf802  00     offcore_response.demand_rfo.other_local_dram memory REQUEST = DEMAND_RFO and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4002  00     offcore_response.demand_rfo.remote_dram memory REQUEST = DEMAND_RFO and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2002  00     offcore_response.other.any_dram_and_remote_fwd memory REQUEST = OTHER and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x3080  00     offcore_response.other.any_llc_miss memory REQUEST = OTHER and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf880  00     offcore_response.other.other_local_dram memory REQUEST = OTHER and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4080  00     offcore_response.other.remote_dram memory REQUEST = OTHER and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2080  00     offcore_response.pf_data.any_dram_and_remote_fwd memory REQUEST = PF_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x3050  00     offcore_response.pf_data.any_llc_miss memory REQUEST = PF_DATA and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf850  00     offcore_response.pf_data.other_local_dram memory REQUEST = PF_DATA and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4050  00     offcore_response.pf_data.remote_dram memory REQUEST = PF_DATA and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2050  00     offcore_response.pf_data_rd.any_dram_and_remote_fwd memory REQUEST = PF_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x3010  00     offcore_response.pf_data_rd.any_llc_miss memory REQUEST = PF_DATA_RD and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf810  00     offcore_response.pf_data_rd.other_local_dram memory REQUEST = PF_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4010  00     offcore_response.pf_data_rd.remote_dram memory REQUEST = PF_DATA_RD and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2010  00     offcore_response.pf_ifetch.any_dram_and_remote_fwd memory REQUEST = PF_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x3040  00     offcore_response.pf_ifetch.any_llc_miss memory REQUEST = PF_RFO and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf840  00     offcore_response.pf_ifetch.other_local_dram memory REQUEST = PF_RFO and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4040  00     offcore_response.pf_ifetch.remote_dram memory REQUEST = PF_RFO and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2040  00     offcore_response.pf_rfo.any_dram_and_remote_fwd memory REQUEST = PF_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x3020  00     offcore_response.pf_rfo.any_llc_miss memory REQUEST = PF_IFETCH and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf820  00     offcore_response.pf_rfo.other_local_dram memory REQUEST = PF_IFETCH and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4020  00     offcore_response.pf_rfo.remote_dram memory REQUEST = PF_IFETCH and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2020  00     offcore_response.prefetch.any_dram_and_remote_fwd memory REQUEST = PREFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=1,offcore_rsp=0x3070  00     offcore_response.prefetch.any_llc_miss memory REQUEST = PREFETCH and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=1,offcore_rsp=0xf870  00     offcore_response.prefetch.other_local_dram memory REQUEST = PREFETCH and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4070  00     offcore_response.prefetch.remote_dram memory REQUEST = PREFETCH and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2070  00     load_block.overlap_store other Loads that partially overlap an earlier store event=3,period=200000,umask=2  00     snoopq_requests.code other Snoop code requests event=0xb4,period=100000,umask=4  00     snoopq_requests.data other Snoop data requests event=0xb4,period=100000,umask=1  00     snoopq_requests.invalidate other Snoop invalidate requests event=0xb4,period=100000,umask=2  00     snoopq_requests_outstanding.code other Outstanding snoop code requests event=0xb3,period=2000000,umask=4  00     snoopq_requests_outstanding.code_not_empty other Cycles snoop code requests queued event=0xb3,cmask=1,period=2000000,umask=4  00     snoopq_requests_outstanding.data other Outstanding snoop data requests event=0xb3,period=2000000,umask=1  00     snoopq_requests_outstanding.data_not_empty other Cycles snoop data requests queued event=0xb3,cmask=1,period=2000000,umask=1  00     snoopq_requests_outstanding.invalidate other Outstanding snoop invalidate requests event=0xb3,period=2000000,umask=2  00     snoopq_requests_outstanding.invalidate_not_empty other Cycles snoop invalidate requests queued event=0xb3,cmask=1,period=2000000,umask=2  00     br_misp_retired.all_branches pipeline Mispredicted retired branch instructions (Precise Event) event=0xc5,period=20000,umask=4  00     br_misp_retired.conditional pipeline Mispredicted conditional retired branches (Precise Event) event=0xc5,period=20000,umask=1  00     dtlb_load_misses.large_walk_completed virtual memory DTLB load miss large page walks event=8,period=200000,umask=0x80  00     dtlb_load_misses.walk_cycles virtual memory DTLB load miss page walk cycles event=8,period=200000,umask=4  00     dtlb_misses.large_walk_completed virtual memory DTLB miss large page walks event=0x49,period=200000,umask=0x80  00     dtlb_misses.pde_miss virtual memory DTLB misses caused by low part of address event=0x49,period=200000,umask=0x20  00     dtlb_misses.walk_cycles virtual memory DTLB miss page walk cycles event=0x49,period=2000000,umask=4  00     ept.walk_cycles virtual memory Extended Page Table walk cycles event=0x4f,period=2000000,umask=0x10  00     itlb_misses.large_walk_completed virtual memory ITLB miss large page walks event=0x85,period=200000,umask=0x80  00     itlb_misses.walk_cycles virtual memory ITLB miss page walk cycles event=0x85,period=2000000,umask=4  00     mem_uncore_retired.local_dram cache Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event) event=0xf,period=10000,umask=0x10  00     mem_uncore_retired.remote_dram cache Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event) event=0xf,period=10000,umask=0x20  00     offcore_requests.uncached_mem cache Offcore uncached memory accesses event=0xb0,period=100000,umask=0x20  00     offcore_response.any_data.local_cache_dram cache Offcore data reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2711  00     offcore_response.any_data.remote_cache_dram cache Offcore data reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x5811  00     offcore_response.any_ifetch.local_cache_dram cache Offcore code reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2744  00     offcore_response.any_ifetch.remote_cache_dram cache Offcore code reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x5844  00     offcore_response.any_request.local_cache_dram cache Offcore requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x27FF  00     offcore_response.any_request.remote_cache_dram cache Offcore requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x58FF  00     offcore_response.any_rfo.local_cache_dram cache Offcore RFO requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2722  00     offcore_response.any_rfo.remote_cache_dram cache Offcore RFO requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x5822  00     offcore_response.corewb.local_cache_dram cache Offcore writebacks to the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2708  00     offcore_response.corewb.remote_cache_dram cache Offcore writebacks to a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x5808  00     offcore_response.data_ifetch.local_cache_dram cache Offcore code or data read requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2777  00     offcore_response.data_ifetch.remote_cache_dram cache Offcore code or data read requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x5877  00     offcore_response.data_in.local_cache_dram cache Offcore request = all data, response = local cache or dram event=0xb7,period=100000,umask=1,offcore_rsp=0x2733  00     offcore_response.data_in.remote_cache_dram cache Offcore request = all data, response = remote cache or dram event=0xb7,period=100000,umask=1,offcore_rsp=0x5833  00     offcore_response.demand_data.local_cache_dram cache Offcore demand data requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2703  00     offcore_response.demand_data.remote_cache_dram cache Offcore demand data requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x5803  00     offcore_response.demand_data_rd.local_cache_dram cache Offcore demand data reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2701  00     offcore_response.demand_data_rd.remote_cache_dram cache Offcore demand data reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x5801  00     offcore_response.demand_ifetch.local_cache_dram cache Offcore demand code reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2704  00     offcore_response.demand_ifetch.remote_cache_dram cache Offcore demand code reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x5804  00     offcore_response.demand_rfo.local_cache_dram cache Offcore demand RFO requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2702  00     offcore_response.demand_rfo.remote_cache_dram cache Offcore demand RFO requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x5802  00     offcore_response.other.local_cache_dram cache Offcore other requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2780  00     offcore_response.other.remote_cache_dram cache Offcore other requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x5880  00     offcore_response.pf_data.any_cache_dram cache Offcore prefetch data requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x7F50  00     offcore_response.pf_data.any_location cache All offcore prefetch data requests event=0xb7,period=100000,umask=1,offcore_rsp=0xFF50  00     offcore_response.pf_data.io_csr_mmio cache Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=1,offcore_rsp=0x8050  00     offcore_response.pf_data.llc_hit_no_other_core cache Offcore prefetch data requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x150  00     offcore_response.pf_data.llc_hit_other_core_hit cache Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x250  00     offcore_response.pf_data.llc_hit_other_core_hitm cache Offcore prefetch data requests satisfied by the LLC  and HITM in a sibling core event=0xb7,period=100000,umask=1,offcore_rsp=0x450  00     offcore_response.pf_data.local_cache cache Offcore prefetch data requests satisfied by the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0x750  00     offcore_response.pf_data.local_cache_dram cache Offcore prefetch data requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2750  00     offcore_response.pf_data.remote_cache cache Offcore prefetch data requests satisfied by a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1850  00     offcore_response.pf_data.remote_cache_dram cache Offcore prefetch data requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x5850  00     offcore_response.pf_data.remote_cache_hit cache Offcore prefetch data requests that HIT in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x1050  00     offcore_response.pf_data.remote_cache_hitm cache Offcore prefetch data requests that HITM in a remote cache event=0xb7,period=100000,umask=1,offcore_rsp=0x850  00     offcore_response.pf_data_rd.local_cache_dram cache Offcore prefetch data reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2710  00     offcore_response.pf_data_rd.remote_cache_dram cache Offcore prefetch data reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x5810  00     offcore_response.pf_ifetch.local_cache_dram cache Offcore prefetch code reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2740  00     offcore_response.pf_ifetch.remote_cache_dram cache Offcore prefetch code reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x5840  00     offcore_response.pf_rfo.local_cache_dram cache Offcore prefetch RFO requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2720  00     offcore_response.pf_rfo.remote_cache_dram cache Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x5820  00     offcore_response.prefetch.local_cache_dram cache Offcore prefetch requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2770  00     offcore_response.prefetch.remote_cache_dram cache Offcore prefetch requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x5870  00     offcore_response.any_data.local_dram memory Offcore data reads satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2011  00     offcore_response.any_data.remote_dram memory Offcore data reads satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4011  00     offcore_response.any_ifetch.local_dram memory Offcore code reads satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2044  00     offcore_response.any_ifetch.remote_dram memory Offcore code reads satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4044  00     offcore_response.any_request.local_dram memory Offcore requests satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x20FF  00     offcore_response.any_request.remote_dram memory Offcore requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x40FF  00     offcore_response.any_rfo.local_dram memory Offcore RFO requests satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2022  00     offcore_response.any_rfo.remote_dram memory Offcore RFO requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4022  00     offcore_response.corewb.local_dram memory Offcore writebacks to the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2008  00     offcore_response.corewb.remote_dram memory Offcore writebacks to a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4008  00     offcore_response.data_ifetch.local_dram memory Offcore code or data read requests satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2077  00     offcore_response.data_ifetch.remote_dram memory Offcore code or data read requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4077  00     offcore_response.data_in.local_dram memory Offcore data reads, RFOs, and prefetches satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2033  00     offcore_response.data_in.remote_dram memory Offcore data reads, RFOs, and prefetches satisfied by the remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4033  00     offcore_response.demand_data.local_dram memory Offcore demand data requests satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2003  00     offcore_response.demand_data.remote_dram memory Offcore demand data requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4003  00     offcore_response.demand_data_rd.local_dram memory Offcore demand data reads satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2001  00     offcore_response.demand_data_rd.remote_dram memory Offcore demand data reads satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4001  00     offcore_response.demand_ifetch.local_dram memory Offcore demand code reads satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2004  00     offcore_response.demand_ifetch.remote_dram memory Offcore demand code reads satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4004  00     offcore_response.demand_rfo.local_dram memory Offcore demand RFO requests satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2002  00     offcore_response.demand_rfo.remote_dram memory Offcore demand RFO requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4002  00     offcore_response.other.remote_dram memory Offcore other requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4080  00     offcore_response.pf_data.any_dram memory Offcore prefetch data requests satisfied by any DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x6050  00     offcore_response.pf_data.any_llc_miss memory Offcore prefetch data requests that missed the LLC event=0xb7,period=100000,umask=1,offcore_rsp=0xF850  00     offcore_response.pf_data.local_dram memory Offcore prefetch data requests satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2050  00     offcore_response.pf_data.remote_dram memory Offcore prefetch data requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4050  00     offcore_response.pf_data_rd.local_dram memory Offcore prefetch data reads satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2010  00     offcore_response.pf_data_rd.remote_dram memory Offcore prefetch data reads satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4010  00     offcore_response.pf_ifetch.local_dram memory Offcore prefetch code reads satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2040  00     offcore_response.pf_ifetch.remote_dram memory Offcore prefetch code reads satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4040  00     offcore_response.pf_rfo.local_dram memory Offcore prefetch RFO requests satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2020  00     offcore_response.pf_rfo.remote_dram memory Offcore prefetch RFO requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4020  00     offcore_response.prefetch.local_dram memory Offcore prefetch requests satisfied by the local DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x2070  00     offcore_response.prefetch.remote_dram memory Offcore prefetch requests satisfied by a remote DRAM event=0xb7,period=100000,umask=1,offcore_rsp=0x4070  00     mem_uncore_retired.local_dram_and_remote_cache_hit cache Load instructions retired local dram and remote cache HIT data sources (Precise Event) event=0xf,period=20000,umask=8  00     mem_uncore_retired.local_hitm cache Load instructions retired that HIT modified data in sibling core (Precise Event) event=0xf,period=40000,umask=2  00     mem_uncore_retired.remote_hitm cache Retired loads that hit remote socket in modified state (Precise Event) event=0xf,period=40000,umask=4  00     bpu_clears.early pipeline Early Branch Prediction Unit clears event=0xe8,period=2000000,umask=1  00     uops_executed.core_stall_count pipeline Uops executed on any port (core count) event=0xb1,cmask=1,edge=1,inv=1,period=2000000,umask=0x3f  00     uops_executed.core_stall_count_no_port5 pipeline Uops executed on ports 0-4 (core count) event=0xb1,cmask=1,edge=1,inv=1,period=2000000,umask=0x1f  00     dtlb_misses.pde_miss virtual memory DTLB misses caused by low part of address. Count also includes 2M page references because 2M pages do not use the PDE event=0x49,period=200000,umask=0x20  00     CPUs_utilized Default (software@cpu\-clock\,name\=cpu\-clock@ if #target_cpu else software@task\-clock\,name\=task\-clock@) / (duration_time * 1e9)  Average CPU utilization  1CPUs    011cs_per_second Default software@context\-switches\,name\=context\-switches@ * 1e9 / (software@cpu\-clock\,name\=cpu\-clock@ if #target_cpu else software@task\-clock\,name\=task\-clock@)  Context switches per CPU second  1cs/sec    011migrations_per_second Default software@cpu\-migrations\,name\=cpu\-migrations@ * 1e9 / (software@cpu\-clock\,name\=cpu\-clock@ if #target_cpu else software@task\-clock\,name\=task\-clock@)  Process migrations to a new CPU per CPU second  1migrations/sec    011page_faults_per_second Default software@page\-faults\,name\=page\-faults@ * 1e9 / (software@cpu\-clock\,name\=cpu\-clock@ if #target_cpu else software@task\-clock\,name\=task\-clock@)  Page faults per CPU second  1faults/sec    011insn_per_cycle Default instructions / cpu\-cycles insn_per_cycle < 1 Instructions Per Cycle  1instructions    001stalled_cycles_per_instruction Default (max(stalled\-cycles\-frontend, stalled\-cycles\-backend) / instructions if has_event(stalled\-cycles\-frontend) & has_event(stalled\-cycles\-backend) else (stalled\-cycles\-frontend / instructions if has_event(stalled\-cycles\-frontend) else (stalled\-cycles\-backend / instructions if has_event(stalled\-cycles\-backend) else 0)))  Max front or backend stalls per instruction      001frontend_cycles_idle Default (stalled\-cycles\-frontend / cpu\-cycles if has_event(stalled\-cycles\-frontend) else 0) frontend_cycles_idle > 0.1 Frontend stalls per cycle      001backend_cycles_idle Default (stalled\-cycles\-backend / cpu\-cycles if has_event(stalled\-cycles\-backend) else 0) backend_cycles_idle > 0.2 Backend stalls per cycle      001cycles_frequency Default cpu\-cycles / (software@cpu\-clock\,name\=cpu\-clock@ if #target_cpu else software@task\-clock\,name\=task\-clock@)  Cycles per CPU second  1GHz    011branch_frequency Default branches / (software@cpu\-clock\,name\=cpu\-clock@ if #target_cpu else software@task\-clock\,name\=task\-clock@)  Branches per CPU second  1000M/sec    011branch_miss_rate Default branch\-misses / branches branch_miss_rate > 0.05 Branch miss rate  100%    001l1d_miss_rate Default2 L1\-dcache\-load\-misses / L1\-dcache\-loads l1d_miss_rate > 0.05 L1D  miss rate  100%    001llc_miss_rate Default2 LLC\-load\-misses / LLC\-loads llc_miss_rate > 0.05 LLC miss rate  100%    001l1i_miss_rate Default3 L1\-icache\-load\-misses / L1\-icache\-loads l1i_miss_rate > 0.05 L1I miss rate  100%    001dtlb_miss_rate Default3 dTLB\-load\-misses / dTLB\-loads dtlb_miss_rate > 0.05 dTLB miss rate  100%    001itlb_miss_rate Default3 iTLB\-load\-misses / iTLB\-loads itlb_miss_rate > 0.05 iTLB miss rate  100%    001l1_prefetch_miss_rate Default4 L1\-dcache\-prefetch\-misses / L1\-dcache\-prefetches l1_prefetch_miss_rate > 0.05 L1 prefetch miss rate  100%    001CPI  1 / IPC        000IPC group1 inst_retired.any / cpu_clk_unhalted.thread        000Frontend_Bound_SMT  idq_uops_not_delivered.core / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk)))        000dcache_miss_cpi  l1d\-loads\-misses / inst_retired.any        000icache_miss_cycles  l1i\-loads\-misses / inst_retired.any        000cache_miss_cycles group1 dcache_miss_cpi + icache_miss_cycles        000DCache_L2_All_Hits  l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + l2_rqsts.rfo_hit        000DCache_L2_All_Miss  max(l2_rqsts.all_demand_data_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss        000DCache_L2_All  DCache_L2_All_Hits + DCache_L2_All_Miss        000DCache_L2_Hits  d_ratio(DCache_L2_All_Hits, DCache_L2_All)        000DCache_L2_Misses  d_ratio(DCache_L2_All_Miss, DCache_L2_All)        000M1  ipc + M2        000M2  ipc + M1        000M3  1 / M3        000L1D_Cache_Fill_BW  64 * l1d.replacement / 1e9 / duration_time        000C10_Pkg_Residency Power cstate_pkg@c10\-residency@ / msr@tsc@  C10 residency percent per package  100%    000C1_Core_Residency Power cstate_core@c1\-residency@ / msr@tsc@  C1 residency percent per core  100%    000C2_Pkg_Residency Power cstate_pkg@c2\-residency@ / msr@tsc@  C2 residency percent per package  100%    000C3_Pkg_Residency Power cstate_pkg@c3\-residency@ / msr@tsc@  C3 residency percent per package  100%    000C6_Core_Residency Power cstate_core@c6\-residency@ / msr@tsc@  C6 residency percent per core  100%    000C6_Pkg_Residency Power cstate_pkg@c6\-residency@ / msr@tsc@  C6 residency percent per package  100%    000C7_Core_Residency Power cstate_core@c7\-residency@ / msr@tsc@  C7 residency percent per core  100%    000C8_Pkg_Residency Power cstate_pkg@c8\-residency@ / msr@tsc@  C8 residency percent per package  100%    000smi_cycles smi ((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0) smi_cycles > 0.1 Percentage of cycles spent in System Management Interrupts  100%    000smi_num smi msr@smi@  Number of SMI interrupts  1SMI#    000tsx_aborted_cycles transaction (max(cycles\-t - cycles\-ct, 0) / cycles if has_event(cycles\-t) else 0)  Percentage of cycles in aborted transactions  100%    000tsx_cycles_per_elision transaction (cycles\-t / el\-start if has_event(el\-start) else 0)  Number of cycles within a transaction divided by the number of elisions  1cycles / elision    000tsx_cycles_per_transaction transaction (cycles\-t / tx\-start if has_event(cycles\-t) else 0)  Number of cycles within a transaction divided by the number of transactions  1cycles / transaction    000tsx_transactional_cycles transaction (cycles\-t / cycles if has_event(cycles\-t) else 0)  Percentage of cycles within a transaction region  100%    000cpu_atom tma_allocation_restriction TopdownL3;tma_L3_group;tma_core_bound_group tma_core_bound tma_allocation_restriction > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to certain allocation restrictions  100%    000tma_backend_bound Default;TopdownL1;tma_L1_group cpu_atom@TOPDOWN_BE_BOUND.ALL@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_backend_bound > 0.1 Counts the total number of issue slots that were not consumed by the backend due to backend stalls Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count 100%  TopdownL1;Default TopdownL1 000tma_bad_speculation Default;TopdownL1;tma_L1_group (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@ - (cpu_atom@TOPDOWN_FE_BOUND.ALL@ + cpu_atom@TOPDOWN_BE_BOUND.ALL@ + cpu_atom@TOPDOWN_RETIRING.ALL@)) / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_bad_speculation > 0.15 Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear 100%  TopdownL1;Default TopdownL1 000tma_branch_detect TopdownL3;tma_L3_group;tma_ifetch_latency_group cpu_atom@TOPDOWN_FE_BOUND.BRANCH_DETECT@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_branch_detect > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches 100%    000tma_branch_mispredicts TopdownL2;tma_L2_group;tma_bad_speculation_group cpu_atom@TOPDOWN_BAD_SPECULATION.MISPREDICT@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_branch_mispredicts > 0.05 & tma_bad_speculation > 0.15 Counts the number of issue slots that were not consumed by the backend due to branch mispredicts  100%  TopdownL2  000tma_branch_resteer TopdownL3;tma_L3_group;tma_ifetch_latency_group cpu_atom@TOPDOWN_FE_BOUND.BRANCH_RESTEER@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_branch_resteer > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch  100%    000tma_cisc TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group cpu_atom@TOPDOWN_FE_BOUND.CISC@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_cisc > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to the microcode sequencer (MS)  100%    000tma_core_bound TopdownL2;tma_L2_group;tma_backend_bound_group cpu_atom@TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_core_bound > 0.1 & tma_backend_bound > 0.1 Counts the number of cycles due to backend bound stalls that are bounded by core restrictions and not attributed to an outstanding load or stores, or resource limitation  100%  TopdownL2  000tma_decode TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group cpu_atom@TOPDOWN_FE_BOUND.DECODE@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_decode > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to decode stalls  100%    000tma_fast_nuke TopdownL3;tma_L3_group;tma_machine_clears_group cpu_atom@TOPDOWN_BAD_SPECULATION.FASTNUKE@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_fast_nuke > 0.05 & (tma_machine_clears > 0.05 & tma_bad_speculation > 0.15) Counts the number of issue slots that were not consumed by the backend due to a machine clear that does not require the use of microcode, classified as a fast nuke, due to memory ordering, memory disambiguation and memory renaming  100%    000tma_frontend_bound Default;TopdownL1;tma_L1_group cpu_atom@TOPDOWN_FE_BOUND.ALL@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_frontend_bound > 0.2 Counts the number of issue slots that were not consumed by the backend due to frontend stalls  100%  TopdownL1;Default TopdownL1 000tma_icache_misses TopdownL3;tma_L3_group;tma_ifetch_latency_group cpu_atom@TOPDOWN_FE_BOUND.ICACHE@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_icache_misses > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to instruction cache misses  100%    000tma_ifetch_bandwidth TopdownL2;tma_L2_group;tma_frontend_bound_group cpu_atom@TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2 Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations  100%  TopdownL2  000tma_ifetch_latency TopdownL2;tma_L2_group;tma_frontend_bound_group cpu_atom@TOPDOWN_FE_BOUND.FRONTEND_LATENCY@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2 Counts the number of issue slots that were not delivered by the frontend due to frontend latency restrictions due to icache misses, itlb misses, branch detection, and resteer limitations  100%  TopdownL2  000tma_info_bottleneck_%_dtlb_miss_bound_cycles  100 * (cpu_atom@LD_HEAD.DTLB_MISS_AT_RET@ + cpu_atom@LD_HEAD.PGWALK_AT_RET@) / cpu_atom@CPU_CLK_UNHALTED.CORE@  Percentage of time that retirement is stalled due to a first level data TLB miss      000tma_info_bottleneck_%_ifetch_miss_bound_cycles Ifetch 100 * cpu_atom@MEM_BOUND_STALLS.IFETCH@ / cpu_atom@CPU_CLK_UNHALTED.CORE@  Percentage of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icache or ITLB Miss Percentage of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icache or ITLB Miss. See Info.Ifetch_Bound     000tma_info_bottleneck_%_load_miss_bound_cycles Load_Store_Miss 100 * cpu_atom@MEM_BOUND_STALLS.LOAD@ / cpu_atom@CPU_CLK_UNHALTED.CORE@  Percentage of time that retirement is stalled due to an L1 miss Percentage of time that retirement is stalled due to an L1 miss. See Info.Load_Miss_Bound     000tma_info_bottleneck_%_mem_exec_bound_cycles Mem_Exec 100 * cpu_atom@LD_HEAD.ANY_AT_RET@ / cpu_atom@CPU_CLK_UNHALTED.CORE@  Percentage of time that retirement is stalled by the Memory Cluster due to a pipeline stall Percentage of time that retirement is stalled by the Memory Cluster due to a pipeline stall. See Info.Mem_Exec_Bound     000tma_info_br_inst_mix_ipbranch  cpu_atom@INST_RETIRED.ANY@ / cpu_atom@BR_INST_RETIRED.ALL_BRANCHES@  Instructions per Branch (lower number means higher occurrence rate)      000tma_info_br_inst_mix_ipcall  cpu_atom@INST_RETIRED.ANY@ / cpu_atom@BR_INST_RETIRED.CALL@  Instruction per (near) call (lower number means higher occurrence rate)      000tma_info_br_inst_mix_ipfarbranch  cpu_atom@INST_RETIRED.ANY@ / cpu_atom@BR_INST_RETIRED.FAR_BRANCH@u  Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]      000tma_info_br_inst_mix_ipmisp_cond_ntaken  cpu_atom@INST_RETIRED.ANY@ / (cpu_atom@BR_MISP_RETIRED.COND@ - cpu_atom@BR_MISP_RETIRED.COND_TAKEN@)  Instructions per retired conditional Branch Misprediction where the branch was not taken      000tma_info_br_inst_mix_ipmisp_cond_taken  cpu_atom@INST_RETIRED.ANY@ / cpu_atom@BR_MISP_RETIRED.COND_TAKEN@  Instructions per retired conditional Branch Misprediction where the branch was taken      000tma_info_br_inst_mix_ipmisp_indirect  cpu_atom@INST_RETIRED.ANY@ / cpu_atom@BR_MISP_RETIRED.INDIRECT@  Instructions per retired indirect call or jump Branch Misprediction      000tma_info_br_inst_mix_ipmisp_ret  cpu_atom@INST_RETIRED.ANY@ / cpu_atom@BR_MISP_RETIRED.RETURN@  Instructions per retired return Branch Misprediction      000tma_info_br_inst_mix_ipmispredict  cpu_atom@INST_RETIRED.ANY@ / cpu_atom@BR_MISP_RETIRED.ALL_BRANCHES@  Instructions per retired Branch Misprediction      000tma_info_br_mispredict_bound_branch_mispredict_ratio  cpu_atom@BR_MISP_RETIRED.ALL_BRANCHES@ / cpu_atom@BR_INST_RETIRED.ALL_BRANCHES@  Ratio of all branches which mispredict      000tma_info_br_mispredict_bound_branch_mispredict_to_unknown_branch_ratio  cpu_atom@BR_MISP_RETIRED.ALL_BRANCHES@ / cpu_atom@BACLEARS.ANY@  Ratio between Mispredicted branches and unknown branches      000tma_info_buffer_stalls_%_load_buffer_stall_cycles  100 * cpu_atom@MEM_SCHEDULER_BLOCK.LD_BUF@ / cpu_atom@CPU_CLK_UNHALTED.CORE@  Percentage of time that allocation is stalled due to load buffer full      000tma_info_buffer_stalls_%_mem_rsv_stall_cycles  100 * cpu_atom@MEM_SCHEDULER_BLOCK.RSV@ / cpu_atom@CPU_CLK_UNHALTED.CORE@  Percentage of time that allocation is stalled due to memory reservation stations full      000tma_info_buffer_stalls_%_store_buffer_stall_cycles  100 * cpu_atom@MEM_SCHEDULER_BLOCK.ST_BUF@ / cpu_atom@CPU_CLK_UNHALTED.CORE@  Percentage of time that allocation is stalled due to store buffer full      000tma_info_core_cpi  cpu_atom@CPU_CLK_UNHALTED.CORE@ / cpu_atom@INST_RETIRED.ANY@  Cycles Per Instruction      000tma_info_core_ipc  cpu_atom@INST_RETIRED.ANY@ / cpu_atom@CPU_CLK_UNHALTED.CORE@  Instructions Per Cycle      000tma_info_core_upi  cpu_atom@UOPS_RETIRED.ALL@ / cpu_atom@INST_RETIRED.ANY@  Uops Per Instruction      000tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l2hit  100 * cpu_atom@MEM_BOUND_STALLS.IFETCH_L2_HIT@ / cpu_atom@MEM_BOUND_STALLS.IFETCH@  Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L2      000tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l2miss  100 * (cpu_atom@MEM_BOUND_STALLS.IFETCH_LLC_HIT@ + cpu_atom@MEM_BOUND_STALLS.IFETCH_DRAM_HIT@) / cpu_atom@MEM_BOUND_STALLS.IFETCH@  Percentage of ifetch miss bound stalls, where the ifetch miss doesn't hit in the L2      000tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l3hit  100 * cpu_atom@MEM_BOUND_STALLS.IFETCH_LLC_HIT@ / cpu_atom@MEM_BOUND_STALLS.IFETCH@  Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L3      000tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l3miss  100 * cpu_atom@MEM_BOUND_STALLS.IFETCH_DRAM_HIT@ / cpu_atom@MEM_BOUND_STALLS.IFETCH@  Percentage of ifetch miss bound stalls, where the ifetch miss subsequently misses in the L3      000tma_info_load_miss_bound_%_loadmissbound_with_l2hit load_store_bound 100 * cpu_atom@MEM_BOUND_STALLS.LOAD_L2_HIT@ / cpu_atom@MEM_BOUND_STALLS.LOAD@  Percentage of memory bound stalls where retirement is stalled due to an L1 miss that hit the L2      000tma_info_load_miss_bound_%_loadmissbound_with_l2miss load_store_bound 100 * (cpu_atom@MEM_BOUND_STALLS.LOAD_LLC_HIT@ + cpu_atom@MEM_BOUND_STALLS.LOAD_DRAM_HIT@) / cpu_atom@MEM_BOUND_STALLS.LOAD@  Percentage of memory bound stalls where retirement is stalled due to an L1 miss that subsequently misses in the L2      000tma_info_load_miss_bound_%_loadmissbound_with_l3hit load_store_bound 100 * cpu_atom@MEM_BOUND_STALLS.LOAD_LLC_HIT@ / cpu_atom@MEM_BOUND_STALLS.LOAD@  Percentage of memory bound stalls where retirement is stalled due to an L1 miss that hit the L3      000tma_info_load_miss_bound_%_loadmissbound_with_l3miss load_store_bound 100 * cpu_atom@MEM_BOUND_STALLS.LOAD_DRAM_HIT@ / cpu_atom@MEM_BOUND_STALLS.LOAD@  Percentage of memory bound stalls where retirement is stalled due to an L1 miss that subsequently misses the L3      000tma_info_load_store_bound_l1_bound load_store_bound 100 * cpu_atom@LD_HEAD.L1_BOUND_AT_RET@ / cpu_atom@CPU_CLK_UNHALTED.CORE@  Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a pipeline block      000tma_info_load_store_bound_load_bound load_store_bound 100 * (cpu_atom@LD_HEAD.L1_BOUND_AT_RET@ + cpu_atom@MEM_BOUND_STALLS.LOAD@) / cpu_atom@CPU_CLK_UNHALTED.CORE@  Counts the number of cycles that the oldest load of the load buffer is stalled at retirement      000tma_info_load_store_bound_store_bound load_store_bound 100 * (cpu_atom@MEM_SCHEDULER_BLOCK.ST_BUF@ / cpu_atom@MEM_SCHEDULER_BLOCK.ALL@) * tma_mem_scheduler  Counts the number of cycles the core is stalled due to store buffer full      000tma_info_machine_clear_bound_machine_clears_disamb_pki  1e3 * cpu_atom@MACHINE_CLEARS.DISAMBIGUATION@ / cpu_atom@INST_RETIRED.ANY@  Counts the number of machine clears relative to thousands of instructions retired, due to memory disambiguation      000tma_info_machine_clear_bound_machine_clears_fp_assist_pki  1e3 * cpu_atom@MACHINE_CLEARS.FP_ASSIST@ / cpu_atom@INST_RETIRED.ANY@  Counts the number of machine clears relative to thousands of instructions retired, due to floating point assists      000tma_info_machine_clear_bound_machine_clears_monuke_pki  1e3 * cpu_atom@MACHINE_CLEARS.MEMORY_ORDERING@ / cpu_atom@INST_RETIRED.ANY@  Counts the number of machine clears relative to thousands of instructions retired, due to memory ordering      000tma_info_machine_clear_bound_machine_clears_mrn_pki  1e3 * cpu_atom@MACHINE_CLEARS.MRN_NUKE@ / cpu_atom@INST_RETIRED.ANY@  Counts the number of machine clears relative to thousands of instructions retired, due to memory renaming      000tma_info_machine_clear_bound_machine_clears_page_fault_pki  1e3 * cpu_atom@MACHINE_CLEARS.PAGE_FAULT@ / cpu_atom@INST_RETIRED.ANY@  Counts the number of machine clears relative to thousands of instructions retired, due to page faults      000tma_info_machine_clear_bound_machine_clears_smc_pki  1e3 * cpu_atom@MACHINE_CLEARS.SMC@ / cpu_atom@INST_RETIRED.ANY@  Counts the number of machine clears relative to thousands of instructions retired, due to self-modifying code      000tma_info_mem_exec_blocks_%_loads_with_adressaliasing  100 * cpu_atom@LD_BLOCKS.4K_ALIAS@ / cpu_atom@MEM_UOPS_RETIRED.ALL_LOADS@  Percentage of total non-speculative loads with an address aliasing block      000tma_info_mem_exec_blocks_%_loads_with_storefwdblk  100 * cpu_atom@LD_BLOCKS.DATA_UNKNOWN@ / cpu_atom@MEM_UOPS_RETIRED.ALL_LOADS@  Percentage of total non-speculative loads with a store forward or unknown store address block      000tma_info_mem_exec_bound_%_loadhead_with_l1miss  100 * cpu_atom@LD_HEAD.L1_MISS_AT_RET@ / cpu_atom@LD_HEAD.ANY_AT_RET@  Percentage of Memory Execution Bound due to a first level data cache miss      000tma_info_mem_exec_bound_%_loadhead_with_otherpipelineblks  100 * cpu_atom@LD_HEAD.OTHER_AT_RET@ / cpu_atom@LD_HEAD.ANY_AT_RET@  Percentage of Memory Execution Bound due to other block cases, such as pipeline conflicts, fences, etc      000tma_info_mem_exec_bound_%_loadhead_with_pagewalk  100 * cpu_atom@LD_HEAD.PGWALK_AT_RET@ / cpu_atom@LD_HEAD.ANY_AT_RET@  Percentage of Memory Execution Bound due to a pagewalk      000tma_info_mem_exec_bound_%_loadhead_with_stlbhit  100 * cpu_atom@LD_HEAD.DTLB_MISS_AT_RET@ / cpu_atom@LD_HEAD.ANY_AT_RET@  Percentage of Memory Execution Bound due to a second level TLB miss      000tma_info_mem_exec_bound_%_loadhead_with_storefwding  100 * cpu_atom@LD_HEAD.ST_ADDR_AT_RET@ / cpu_atom@LD_HEAD.ANY_AT_RET@  Percentage of Memory Execution Bound due to a store forward address match      000tma_info_mem_mix_ipload  cpu_atom@INST_RETIRED.ANY@ / cpu_atom@MEM_UOPS_RETIRED.ALL_LOADS@  Instructions per Load      000tma_info_mem_mix_ipstore  cpu_atom@INST_RETIRED.ANY@ / cpu_atom@MEM_UOPS_RETIRED.ALL_STORES@  Instructions per Store      000tma_info_mem_mix_load_locks_ratio  100 * cpu_atom@MEM_UOPS_RETIRED.LOCK_LOADS@ / cpu_atom@MEM_UOPS_RETIRED.ALL_LOADS@  Percentage of total non-speculative loads that perform one or more locks      000tma_info_mem_mix_load_splits_ratio  100 * cpu_atom@MEM_UOPS_RETIRED.SPLIT_LOADS@ / cpu_atom@MEM_UOPS_RETIRED.ALL_LOADS@  Percentage of total non-speculative loads that are splits      000tma_info_mem_mix_memload_ratio  1e3 * cpu_atom@MEM_UOPS_RETIRED.ALL_LOADS@ / cpu_atom@UOPS_RETIRED.ALL@  Ratio of mem load uops to all uops      000tma_info_serialization_%_tpause_cycles  100 * cpu_atom@SERIALIZATION.C01_MS_SCB@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@)  Percentage of time that the core is stalled due to a TPAUSE or UMWAIT instruction      000tma_info_system_cpu_utilization  cpu_atom@CPU_CLK_UNHALTED.REF_TSC@ / msr@tsc\,cpu\=cpu_atom@  Average CPU Utilization      000tma_info_system_kernel_utilization Summary cpu_atom@CPU_CLK_UNHALTED.CORE_P@k / cpu_atom@CPU_CLK_UNHALTED.CORE@  Fraction of cycles spent in Kernel mode      000tma_info_system_mux  cpu_atom@CPU_CLK_UNHALTED.CORE_P@ / cpu_atom@CPU_CLK_UNHALTED.CORE@ tma_info_system_mux > 1.1 | tma_info_system_mux < 0.9 PerfMon Event Multiplexing accuracy indicator      000tma_info_system_turbo_utilization Power cpu_atom@CPU_CLK_UNHALTED.CORE@ / cpu_atom@CPU_CLK_UNHALTED.REF_TSC@  Average Frequency Utilization relative nominal frequency      000tma_info_uop_mix_fpdiv_uop_ratio  100 * cpu_atom@UOPS_RETIRED.FPDIV@ / cpu_atom@UOPS_RETIRED.ALL@  Percentage of all uops which are FPDiv uops      000tma_info_uop_mix_idiv_uop_ratio  100 * cpu_atom@UOPS_RETIRED.IDIV@ / cpu_atom@UOPS_RETIRED.ALL@  Percentage of all uops which are IDiv uops      000tma_info_uop_mix_microcode_uop_ratio  100 * cpu_atom@UOPS_RETIRED.MS@ / cpu_atom@UOPS_RETIRED.ALL@  Percentage of all uops which are microcode ops      000tma_info_uop_mix_x87_uop_ratio  100 * cpu_atom@UOPS_RETIRED.X87@ / cpu_atom@UOPS_RETIRED.ALL@  Percentage of all uops which are x87 uops      000tma_itlb_misses TopdownL3;tma_L3_group;tma_ifetch_latency_group cpu_atom@TOPDOWN_FE_BOUND.ITLB@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_itlb_misses > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses  100%    000tma_machine_clears TopdownL2;tma_L2_group;tma_bad_speculation_group cpu_atom@TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_machine_clears > 0.05 & tma_bad_speculation > 0.15 Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation  100%  TopdownL2  000tma_mem_scheduler TopdownL3;tma_L3_group;tma_resource_bound_group cpu_atom@TOPDOWN_BE_BOUND.MEM_SCHEDULER@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_mem_scheduler > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops  100%    000tma_non_mem_scheduler TopdownL3;tma_L3_group;tma_resource_bound_group cpu_atom@TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_non_mem_scheduler > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops  100%    000tma_nuke TopdownL3;tma_L3_group;tma_machine_clears_group cpu_atom@TOPDOWN_BAD_SPECULATION.NUKE@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_nuke > 0.05 & (tma_machine_clears > 0.05 & tma_bad_speculation > 0.15) Counts the number of issue slots that were not consumed by the backend due to a machine clear that requires the use of microcode (slow nuke)  100%    000tma_other_fb TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group cpu_atom@TOPDOWN_FE_BOUND.OTHER@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_other_fb > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to other common frontend stalls not categorized  100%    000tma_predecode TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group cpu_atom@TOPDOWN_FE_BOUND.PREDECODE@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_predecode > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to wrong predecodes  100%    000tma_register TopdownL3;tma_L3_group;tma_resource_bound_group cpu_atom@TOPDOWN_BE_BOUND.REGISTER@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_register > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls)  100%    000tma_reorder_buffer TopdownL3;tma_L3_group;tma_resource_bound_group cpu_atom@TOPDOWN_BE_BOUND.REORDER_BUFFER@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_reorder_buffer > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to the reorder buffer being full (ROB stalls)  100%    000tma_resource_bound TopdownL2;tma_L2_group;tma_backend_bound_group tma_backend_bound - tma_core_bound tma_resource_bound > 0.2 & tma_backend_bound > 0.1 Counts the number of cycles the core is stalled due to a resource limitation  100%  TopdownL2  000tma_retiring Default;TopdownL1;tma_L1_group cpu_atom@TOPDOWN_RETIRING.ALL@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_retiring > 0.75 Counts the number of issue slots that result in retirement slots  100%  TopdownL1;Default TopdownL1 000tma_serialization TopdownL3;tma_L3_group;tma_resource_bound_group cpu_atom@TOPDOWN_BE_BOUND.SERIALIZATION@ / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_serialization > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS)  100%    000cpu_core UNCORE_FREQ SoC tma_info_system_socket_clks / #num_dies / duration_time / 1e9  Uncore frequency per die [GHZ]      000tma_alu_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (cpu_core@UOPS_DISPATCHED.PORT_0@ + cpu_core@UOPS_DISPATCHED.PORT_1@ + cpu_core@UOPS_DISPATCHED.PORT_5_11@ + cpu_core@UOPS_DISPATCHED.PORT_6@) / (5 * tma_info_core_core_clks) tma_alu_op_utilization > 0.4 This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations  100%    000tma_assists BvIO;TopdownL4;tma_L4_group;tma_microcode_sequencer_group 78 * cpu_core@ASSISTS.ANY@ / tma_info_thread_slots tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1) This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY 100%    000tma_avx_assists HPC;TopdownL5;tma_L5_group;tma_assists_group 63 * cpu_core@ASSISTS.SSE_AVX_MIX@ / tma_info_thread_slots tma_avx_assists > 0.1 This metric estimates fraction of slots the CPU retired uops as a result of handing SSE to AVX* or AVX* to SSE transition Assists  100%    000tma_backend_bound BvOB;Default;TmaL1;TopdownL1;tma_L1_group cpu_core@topdown\-be\-bound@ / (cpu_core@topdown\-fe\-bound@ + cpu_core@topdown\-bad\-spec@ + cpu_core@topdown\-retiring@ + cpu_core@topdown\-be\-bound@) tma_backend_bound > 0.2 This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS 100%  TopdownL1;Default TopdownL1 000tma_bad_speculation Default;TmaL1;TopdownL1;tma_L1_group max(1 - (tma_frontend_bound + tma_backend_bound + tma_retiring), 0) tma_bad_speculation > 0.15 This category represents fraction of slots wasted due to incorrect speculations This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example 100%  TopdownL1;Default TopdownL1 000tma_bottleneck_big_code BigFootprint;BvBC;Fed;Frontend;IcMiss;MemoryTLB 100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) tma_bottleneck_big_code > 20 Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)      000tma_bottleneck_branching_overhead BvBO;Ret 100 * ((cpu_core@BR_INST_RETIRED.ALL_BRANCHES@ + 2 * cpu_core@BR_INST_RETIRED.NEAR_CALL@ + cpu_core@INST_RETIRED.NOP@) / tma_info_thread_slots) tma_bottleneck_branching_overhead > 5 Total pipeline cost of instructions used for program control-flow - a subset of the Retiring category in TMA Total pipeline cost of instructions used for program control-flow - a subset of the Retiring category in TMA. Examples include function calls; loops and alignments. (A lower bound)     000tma_bottleneck_compute_bound_est BvCB;Cor;tma_issueComp 100 * (tma_core_bound * tma_divider / (tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_core_bound * (tma_ports_utilization / (tma_divider + tma_ports_utilization + tma_serializing_operation)) * (tma_ports_utilized_3m / (tma_ports_utilized_0 + tma_ports_utilized_1 + tma_ports_utilized_2 + tma_ports_utilized_3m))) tma_bottleneck_compute_bound_est > 20 Total pipeline cost when the execution is compute-bound - an estimation Total pipeline cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as well as when long-latency execution units are busy. Related metrics:      000tma_bottleneck_data_cache_memory_bandwidth BvMB;Mem;MemoryBW;Offcore;tma_issueBW 100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_fb_full / (tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))) tma_bottleneck_data_cache_memory_bandwidth > 20 Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full     000tma_bottleneck_data_cache_memory_latency BvML;Mem;MemoryLat;Offcore;tma_issueLat 100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l1_latency_dependency / (tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_lock_latency / (tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_split_loads / (tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_split_stores / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) tma_bottleneck_data_cache_memory_latency > 20 Total pipeline cost of external Memory- or Cache-Latency related bottlenecks Total pipeline cost of external Memory- or Cache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_mem_latency     000tma_bottleneck_instruction_fetch_bw BvFB;Fed;FetchBW;Frontend 100 * (tma_frontend_bound - (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) - (1 - cpu_core@INST_RETIRED.REP_ITERATION@ / cpu_core@UOPS_RETIRED.MS\,cmask\=1@) * (tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_ms)) - tma_bottleneck_big_code tma_bottleneck_instruction_fetch_bw > 20 Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)      000tma_bottleneck_irregular_overhead Bad;BvIO;Cor;Ret;tma_issueMS 100 * ((1 - cpu_core@INST_RETIRED.REP_ITERATION@ / cpu_core@UOPS_RETIRED.MS\,cmask\=1@) * (tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_ms) + 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts * tma_branch_mispredicts + tma_machine_clears * tma_other_nukes / tma_other_nukes + tma_core_bound * (tma_serializing_operation + cpu_core@RS.EMPTY_RESOURCE@ / tma_info_thread_clks * tma_ports_utilized_0) / (tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations) tma_bottleneck_irregular_overhead > 10 Total pipeline cost of irregular execution (e.g Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloads, overhead in system services or virtualized environments). Related metrics: tma_microcode_sequencer, tma_ms_switches     000tma_bottleneck_memory_data_tlbs BvMT;Mem;MemoryTLB;Offcore;tma_issueTLB 100 * (tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) tma_bottleneck_memory_data_tlbs > 20 Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs) Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store     000tma_bottleneck_memory_synchronization BvMS;LockCont;Mem;Offcore;tma_issueSyncxn 100 * (tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_contested_accesses + tma_data_sharing) / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * tma_false_sharing / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores - tma_store_latency)) + tma_machine_clears * (1 - tma_other_nukes / tma_other_nukes)) tma_bottleneck_memory_synchronization > 10 Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors) Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors). Related metrics: tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache     000tma_bottleneck_mispredictions Bad;BadSpec;BrMispredicts;BvMP;tma_issueBM 100 * (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) tma_bottleneck_mispredictions > 20 Total pipeline cost of Branch Misprediction related bottlenecks Total pipeline cost of Branch Misprediction related bottlenecks. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost, tma_mispredicts_resteers     000tma_bottleneck_other_bottlenecks BvOB;Cor;Offcore 100 - (tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_data_cache_memory_bandwidth + tma_bottleneck_data_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work) tma_bottleneck_other_bottlenecks > 20 Total pipeline cost of remaining bottlenecks in the back-end Total pipeline cost of remaining bottlenecks in the back-end. Examples include data-dependencies (Core Bound when Low ILP) and other unlisted memory-related stalls     000tma_bottleneck_useful_work BvUW;Ret 100 * (tma_retiring - (cpu_core@BR_INST_RETIRED.ALL_BRANCHES@ + 2 * cpu_core@BR_INST_RETIRED.NEAR_CALL@ + cpu_core@INST_RETIRED.NOP@) / tma_info_thread_slots - tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations) tma_bottleneck_useful_work > 20 Total pipeline cost of "useful operations" - the portion of Retiring category not covered by Branching_Overhead nor Irregular_Overhead      000tma_branch_mispredicts BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM cpu_core@topdown\-br\-mispredict@ / (cpu_core@topdown\-fe\-bound@ + cpu_core@topdown\-bad\-spec@ + cpu_core@topdown\-retiring@ + cpu_core@topdown\-be\-bound@) tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15 This metric represents fraction of slots the CPU has wasted due to Branch Misprediction This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS. Related metrics: tma_bottleneck_mispredictions, tma_info_bad_spec_branch_misprediction_cost, tma_mispredicts_resteers 100%  TopdownL2  000tma_branch_resteers FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group cpu_core@INT_MISC.CLEAR_RESTEER_CYCLES@ / tma_info_thread_clks + tma_unknown_branches tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES 100%    000tma_c01_wait C0Wait;TopdownL4;tma_L4_group;tma_serializing_operation_group cpu_core@CPU_CLK_UNHALTED.C01@ / tma_info_thread_clks tma_c01_wait > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU was stalled due staying in C0.1 power-performance optimized state (Faster wakeup time; Smaller power savings)  100%    000tma_c02_wait C0Wait;TopdownL4;tma_L4_group;tma_serializing_operation_group cpu_core@CPU_CLK_UNHALTED.C02@ / tma_info_thread_clks tma_c02_wait > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU was stalled due staying in C0.2 power-performance optimized state (Slower wakeup time; Larger power savings)  100%    000tma_cisc TopdownL4;tma_L4_group;tma_microcode_sequencer_group max(0, tma_microcode_sequencer - tma_assists) tma_cisc > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1) This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources. Sample with: FRONTEND_RETIRED.MS_FLOWS 100%    000tma_clears_resteers BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueMC (1 - tma_branch_mispredicts / tma_bad_speculation) * cpu_core@INT_MISC.CLEAR_RESTEER_CYCLES@ / tma_info_thread_clks tma_clears_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches 100%    000tma_code_l2_hit FetchLat;IcMiss;Offcore;TopdownL4;tma_L4_group;tma_icache_misses_group max(0, tma_icache_misses - tma_code_l2_miss) tma_code_l2_hit > 0.05 & (tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric estimates fraction of cycles the CPU was stalled due to instruction cache misses that hit in the L2 cache  100%    000tma_code_l2_miss FetchLat;IcMiss;Offcore;TopdownL4;tma_L4_group;tma_icache_misses_group cpu_core@OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD@ / tma_info_thread_clks tma_code_l2_miss > 0.05 & (tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric estimates fraction of cycles the CPU was stalled due to instruction cache misses that miss in the L2 cache  100%    000tma_code_stlb_hit FetchLat;MemoryTLB;TopdownL4;tma_L4_group;tma_itlb_misses_group max(0, tma_itlb_misses - tma_code_stlb_miss) tma_code_stlb_hit > 0.05 & (tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric roughly estimates the fraction of cycles where the (first level) ITLB was missed by instructions fetches, that later on hit in second-level TLB (STLB)  100%    000tma_code_stlb_miss FetchLat;MemoryTLB;TopdownL4;tma_L4_group;tma_itlb_misses_group cpu_core@ITLB_MISSES.WALK_ACTIVE@ / tma_info_thread_clks tma_code_stlb_miss > 0.05 & (tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by instruction fetches, performing a hardware page walk  100%    000tma_code_stlb_miss_2m FetchLat;MemoryTLB;TopdownL5;tma_L5_group;tma_code_stlb_miss_group tma_code_stlb_miss * cpu_core@ITLB_MISSES.WALK_COMPLETED_2M_4M@ / (cpu_core@ITLB_MISSES.WALK_COMPLETED_4K@ + cpu_core@ITLB_MISSES.WALK_COMPLETED_2M_4M@) tma_code_stlb_miss_2m > 0.05 & (tma_code_stlb_miss > 0.05 & (tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))) This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 2 or 4 MB pages for (instruction) code accesses  100%    000tma_code_stlb_miss_4k FetchLat;MemoryTLB;TopdownL5;tma_L5_group;tma_code_stlb_miss_group tma_code_stlb_miss * cpu_core@ITLB_MISSES.WALK_COMPLETED_4K@ / (cpu_core@ITLB_MISSES.WALK_COMPLETED_4K@ + cpu_core@ITLB_MISSES.WALK_COMPLETED_2M_4M@) tma_code_stlb_miss_4k > 0.05 & (tma_code_stlb_miss > 0.05 & (tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))) This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 4 KB pages for (instruction) code accesses  100%    000tma_contested_accesses BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (25 * tma_info_system_core_frequency * (cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD@ * (cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM@ / (cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM@ + cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD@))) + 24 * tma_info_system_core_frequency * cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS@) * (1 + cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / 2) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS. Related metrics: tma_bottleneck_memory_synchronization, tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100%    000tma_core_bound Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group max(0, tma_backend_bound - tma_memory_bound) tma_core_bound > 0.1 & tma_backend_bound > 0.2 This metric represents fraction of slots where Core non-memory issues were of a bottleneck This metric represents fraction of slots where Core non-memory issues were of a bottleneck.  Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations) 100%  TopdownL2  000tma_data_sharing BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 24 * tma_info_system_core_frequency * (cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD@ + cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD@ * (1 - cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM@ / (cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM@ + cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD@))) * (1 + cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / 2) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD. Related metrics: tma_bottleneck_memory_synchronization, tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100%    010tma_decoder0_alone DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_issueD0;tma_mite_group (cpu_core@INST_DECODED.DECODERS\,cmask\=1@ - cpu_core@INST_DECODED.DECODERS\,cmask\=2@) / tma_info_core_core_clks / 2 tma_decoder0_alone > 0.1 & (tma_mite > 0.1 & tma_fetch_bandwidth > 0.2) This metric represents fraction of cycles where decoder-0 was the only active decoder This metric represents fraction of cycles where decoder-0 was the only active decoder. Related metrics: tma_few_uops_instructions 100%    000tma_divider BvCB;TopdownL3;tma_L3_group;tma_core_bound_group cpu_core@ARITH.DIV_ACTIVE@ / tma_info_thread_clks tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric represents fraction of cycles where the Divider unit was active This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE 100%    000tma_dram_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group cpu_core@MEMORY_ACTIVITY.STALLS_L3_MISS@ / tma_info_thread_clks tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS 100%    000tma_dsb DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group (cpu_core@IDQ.DSB_CYCLES_ANY@ - cpu_core@IDQ.DSB_CYCLES_OK@) / tma_info_core_core_clks / 2 tma_dsb > 0.15 & tma_fetch_bandwidth > 0.2 This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline.  For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here 100%    000tma_dsb_switches DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB cpu_core@DSB2MITE_SWITCHES.PENALTY_CYCLES@ / tma_info_thread_clks tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 100%    000tma_dtlb_load BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group min(7 * cpu_core@DTLB_LOAD_MISSES.STLB_HIT\,cmask\=1@ + cpu_core@DTLB_LOAD_MISSES.WALK_ACTIVE@, max(cpu_core@CYCLE_ACTIVITY.CYCLES_MEM_ANY@ - cpu_core@MEMORY_ACTIVITY.CYCLES_L1D_MISS@, 0)) / tma_info_thread_clks tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_bottleneck_memory_data_tlbs, tma_dtlb_store 100%    000tma_dtlb_store BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group (7 * cpu_core@DTLB_STORE_MISSES.STLB_HIT\,cmask\=1@ + cpu_core@DTLB_STORE_MISSES.WALK_ACTIVE@) / tma_info_core_core_clks tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses.  As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead.  Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page.  Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_bottleneck_memory_data_tlbs, tma_dtlb_load 100%    000tma_false_sharing BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group 28 * tma_info_system_core_frequency * cpu_core@OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM@ / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_bottleneck_memory_synchronization, tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100%    000tma_fb_full BvMB;MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group cpu_core@L1D_PEND_MISS.FB_FULL@ / tma_info_thread_clks tma_fb_full > 0.3 This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_bottleneck_data_cache_memory_bandwidth, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores 100%    000tma_fetch_bandwidth FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB max(0, tma_frontend_bound - tma_fetch_latency) tma_fetch_bandwidth > 0.2 This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues.  For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1;FRONTEND_RETIRED.LATENCY_GE_1;FRONTEND_RETIRED.LATENCY_GE_2. Related metrics: tma_dsb_switches, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 100%  TopdownL2  000tma_fetch_latency Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group cpu_core@topdown\-fetch\-lat@ / (cpu_core@topdown\-fe\-bound@ + cpu_core@topdown\-bad\-spec@ + cpu_core@topdown\-retiring@ + cpu_core@topdown\-be\-bound@) - cpu_core@INT_MISC.UOP_DROPPING@ / tma_info_thread_slots tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15 This metric represents fraction of slots the CPU was stalled due to Frontend latency issues This metric represents fraction of slots the CPU was stalled due to Frontend latency issues.  For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS 100%  TopdownL2  000tma_few_uops_instructions TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueD0 max(0, tma_heavy_operations - tma_microcode_sequencer) tma_few_uops_instructions > 0.05 & tma_heavy_operations > 0.1 This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or more uops This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or more uops. This highly-correlates with the number of uops in such instructions. Related metrics: tma_decoder0_alone 100%    000tma_fp_arith HPC;TopdownL3;tma_L3_group;tma_light_operations_group tma_x87_use + tma_fp_scalar + tma_fp_vector tma_fp_arith > 0.2 & tma_light_operations > 0.6 This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired) This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of "Uops" CountDomain and FMA double-counting 100%    000tma_fp_assists HPC;TopdownL5;tma_L5_group;tma_assists_group 30 * cpu_core@ASSISTS.FP@ / tma_info_thread_slots tma_fp_assists > 0.1 This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called Denormals) 100%    000tma_fp_divider TopdownL4;tma_L4_group;tma_divider_group cpu_core@ARITH.FPDIV_ACTIVE@ / tma_info_thread_clks tma_fp_divider > 0.2 & (tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles where the Floating-Point Divider unit was active  100%    000tma_fp_scalar Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P cpu_core@FP_ARITH_INST_RETIRED.SCALAR@ / (tma_retiring * tma_info_thread_slots) tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_fp_vector Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P cpu_core@FP_ARITH_INST_RETIRED.VECTOR@ / (tma_retiring * tma_info_thread_slots) tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_fp_vector_128b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE@ + cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE@) / (tma_retiring * tma_info_thread_slots) tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting prior to LNL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_fp_vector_256b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE@ + cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE@) / (tma_retiring * tma_info_thread_slots) tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting prior to LNL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_frontend_bound BvFB;BvIO;Default;PGO;TmaL1;TopdownL1;tma_L1_group cpu_core@topdown\-fe\-bound@ / (cpu_core@topdown\-fe\-bound@ + cpu_core@topdown\-bad\-spec@ + cpu_core@topdown\-retiring@ + cpu_core@topdown\-be\-bound@) - cpu_core@INT_MISC.UOP_DROPPING@ / tma_info_thread_slots tma_frontend_bound > 0.15 This category represents fraction of slots where the processor's Frontend undersupplies its Backend This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS 100%  TopdownL1;Default TopdownL1 000tma_fused_instructions Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * cpu_core@INST_RETIRED.MACRO_FUSED@ / (tma_retiring * tma_info_thread_slots) tma_fused_instructions > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Other_Light_Ops in MTL!)} 100%    000tma_heavy_operations Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group cpu_core@topdown\-heavy\-ops@ / (cpu_core@topdown\-fe\-bound@ + cpu_core@topdown\-bad\-spec@ + cpu_core@topdown\-retiring@ + cpu_core@topdown\-be\-bound@) tma_heavy_operations > 0.1 This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.([ICL+] Note this may overcount due to approximation using indirect events; [ADL+]). Sample with: UOPS_RETIRED.HEAVY 100%  TopdownL2  000tma_icache_misses BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group cpu_core@ICACHE_DATA.STALLS@ / tma_info_thread_clks tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to instruction cache misses This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS 100%    000tma_info_bad_spec_branch_misprediction_cost Bad;BrMispredicts;tma_issueBM tma_bottleneck_mispredictions * tma_info_thread_slots / 6 / cpu_core@BR_MISP_RETIRED.ALL_BRANCHES@ / 100  Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear) Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_bottleneck_mispredictions, tma_branch_mispredicts, tma_mispredicts_resteers     000tma_info_bad_spec_ipmisp_cond_ntaken Bad;BrMispredicts cpu_core@INST_RETIRED.ANY@ / cpu_core@BR_MISP_RETIRED.COND_NTAKEN@ tma_info_bad_spec_ipmisp_cond_ntaken < 200 Instructions per retired Mispredicts for conditional non-taken branches (lower number means higher occurrence rate)      000tma_info_bad_spec_ipmisp_cond_taken Bad;BrMispredicts cpu_core@INST_RETIRED.ANY@ / cpu_core@BR_MISP_RETIRED.COND_TAKEN@ tma_info_bad_spec_ipmisp_cond_taken < 200 Instructions per retired Mispredicts for conditional taken branches (lower number means higher occurrence rate)      000tma_info_bad_spec_ipmisp_indirect Bad;BrMispredicts cpu_core@INST_RETIRED.ANY@ / cpu_core@BR_MISP_RETIRED.INDIRECT@ tma_info_bad_spec_ipmisp_indirect < 1e3 Instructions per retired Mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate)      000tma_info_bad_spec_ipmisp_ret Bad;BrMispredicts cpu_core@INST_RETIRED.ANY@ / cpu_core@BR_MISP_RETIRED.RET@ tma_info_bad_spec_ipmisp_ret < 500 Instructions per retired Mispredicts for return branches (lower number means higher occurrence rate)      000tma_info_bad_spec_ipmispredict Bad;BadSpec;BrMispredicts cpu_core@INST_RETIRED.ANY@ / cpu_core@BR_MISP_RETIRED.ALL_BRANCHES@ tma_info_bad_spec_ipmispredict < 200 Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)      000tma_info_bad_spec_spec_clears_ratio BrMispredicts cpu_core@INT_MISC.CLEARS_COUNT@ / (cpu_core@BR_MISP_RETIRED.ALL_BRANCHES@ + cpu_core@MACHINE_CLEARS.COUNT@)  Speculative to Retired ratio of all clears (covering Mispredicts and nukes)      000tma_info_botlnk_l0_core_bound_likely Cor;SMT (100 * (1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if tma_info_system_smt_2t_utilization > 0.5 else 0) tma_info_botlnk_l0_core_bound_likely > 0.5 Probability of Core Bound bottleneck hidden by SMT-profiling artifacts      000tma_info_botlnk_l2_dsb_bandwidth DSB;Fed;FetchBW;tma_issueFB 100 * (tma_frontend_bound * (tma_fetch_bandwidth / (tma_fetch_bandwidth + tma_fetch_latency)) * (tma_dsb / (tma_dsb + tma_lsd + tma_mite + tma_ms))) tma_info_botlnk_l2_dsb_bandwidth > 10 Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp     000tma_info_botlnk_l2_dsb_misses DSBmiss;Fed;tma_issueFB 100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_lsd + tma_mite + tma_ms)) tma_info_botlnk_l2_dsb_misses > 10 Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp     000tma_info_botlnk_l2_ic_misses Fed;FetchLat;IcMiss;tma_issueFL 100 * (tma_fetch_latency * tma_icache_misses / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) tma_info_botlnk_l2_ic_misses > 5 Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck. Related metrics:      000tma_info_branches_callret Bad;Branches (cpu_core@BR_INST_RETIRED.NEAR_CALL@ + cpu_core@BR_INST_RETIRED.NEAR_RETURN@) / cpu_core@BR_INST_RETIRED.ALL_BRANCHES@  Fraction of branches that are CALL or RET      000tma_info_branches_cond_nt Bad;Branches;CodeGen;PGO cpu_core@BR_INST_RETIRED.COND_NTAKEN@ / cpu_core@BR_INST_RETIRED.ALL_BRANCHES@  Fraction of branches that are non-taken conditionals      000tma_info_branches_cond_tk Bad;Branches;CodeGen;PGO cpu_core@BR_INST_RETIRED.COND_TAKEN@ / cpu_core@BR_INST_RETIRED.ALL_BRANCHES@  Fraction of branches that are taken conditionals      000tma_info_branches_jump Bad;Branches (cpu_core@BR_INST_RETIRED.NEAR_TAKEN@ - cpu_core@BR_INST_RETIRED.COND_TAKEN@ - 2 * cpu_core@BR_INST_RETIRED.NEAR_CALL@) / cpu_core@BR_INST_RETIRED.ALL_BRANCHES@  Fraction of branches that are unconditional (direct or indirect) jumps      000tma_info_branches_other_branches Bad;Branches 1 - (tma_info_branches_cond_nt + tma_info_branches_cond_tk + tma_info_branches_callret + tma_info_branches_jump)  Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)      000tma_info_core_core_clks SMT (cpu_core@CPU_CLK_UNHALTED.DISTRIBUTED@ if #SMT_on else tma_info_thread_clks)  Core actual clocks when any Logical Processor is active on the Physical Core      000tma_info_core_coreipc Ret;SMT;TmaL1;tma_L1_group cpu_core@INST_RETIRED.ANY@ / tma_info_core_core_clks  Instructions Per Cycle across hyper-threads (per physical core)      000tma_info_core_epc Power cpu_core@UOPS_EXECUTED.THREAD@ / tma_info_thread_clks  uops Executed per Cycle      000tma_info_core_flopc Flops;Ret (cpu_core@FP_ARITH_INST_RETIRED.SCALAR@ + 2 * cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE@ + 4 * cpu_core@FP_ARITH_INST_RETIRED.4_FLOPS@ + 8 * cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE@) / tma_info_core_core_clks  Floating Point Operations Per Cycle      000tma_info_core_fp_arith_utilization Cor;Flops;HPC (cpu_core@FP_ARITH_DISPATCHED.PORT_0@ + cpu_core@FP_ARITH_DISPATCHED.PORT_1@ + cpu_core@FP_ARITH_DISPATCHED.PORT_5@) / (2 * tma_info_core_core_clks)  Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width) Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)     000tma_info_core_ilp Backend;Cor;Pipeline;PortsUtil cpu_core@UOPS_EXECUTED.THREAD@ / cpu_core@UOPS_EXECUTED.THREAD\,cmask\=1@  Instruction-Level-Parallelism (average number of uops executed when there is execution) per thread (logical-processor)      000tma_info_frontend_dsb_coverage DSB;Fed;FetchBW;tma_issueFB cpu_core@IDQ.DSB_UOPS@ / cpu_core@UOPS_ISSUED.ANY@ tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 6 > 0.35 Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache) Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp     000tma_info_frontend_dsb_switch_cost DSBmiss cpu_core@DSB2MITE_SWITCHES.PENALTY_CYCLES@ / cpu_core@DSB2MITE_SWITCHES.PENALTY_CYCLES\,cmask\=1\,edge@  Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details      000tma_info_frontend_fetch_upc Fed;FetchBW cpu_core@UOPS_ISSUED.ANY@ / cpu_core@UOPS_ISSUED.ANY\,cmask\=1@  Average number of Uops issued by front-end when it issued something      000tma_info_frontend_icache_miss_latency Fed;FetchLat;IcMiss cpu_core@ICACHE_DATA.STALLS@ / cpu_core@ICACHE_DATA.STALLS\,cmask\=1\,edge@  Average Latency for L1 instruction cache misses      000tma_info_frontend_ipdsb_miss_ret DSBmiss;Fed cpu_core@INST_RETIRED.ANY@ / cpu_core@FRONTEND_RETIRED.ANY_DSB_MISS@ tma_info_frontend_ipdsb_miss_ret < 50 Instructions per non-speculative DSB miss (lower number means higher occurrence rate)      000tma_info_frontend_ipunknown_branch Fed tma_info_inst_mix_instructions / cpu_core@BACLEARS.ANY@  Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)      000tma_info_frontend_l2mpki_code IcMiss 1e3 * cpu_core@FRONTEND_RETIRED.L2_MISS@ / cpu_core@INST_RETIRED.ANY@  L2 cache true code cacheline misses per kilo instruction      000tma_info_frontend_l2mpki_code_all IcMiss 1e3 * cpu_core@L2_RQSTS.CODE_RD_MISS@ / cpu_core@INST_RETIRED.ANY@  L2 cache speculative code cacheline misses per kilo instruction      000tma_info_frontend_lsd_coverage Fed;LSD cpu_core@LSD.UOPS@ / cpu_core@UOPS_ISSUED.ANY@  Fraction of Uops delivered by the LSD (Loop Stream Detector; aka Loop Cache)      000tma_info_frontend_tbpc Branches;FetchBW cpu_core@BR_INST_RETIRED.NEAR_TAKEN@ / tma_info_thread_clks  Taken Branches retired Per Cycle      000tma_info_frontend_unknown_branch_cost Fed cpu_core@INT_MISC.UNKNOWN_BRANCH_CYCLES@ / cpu_core@INT_MISC.UNKNOWN_BRANCH_CYCLES\,cmask\=1\,edge@  Average number of cycles the front-end was delayed due to an Unknown Branch detection Average number of cycles the front-end was delayed due to an Unknown Branch detection. See Unknown_Branches node     000tma_info_inst_mix_bptkbranch Branches;Fed;PGO cpu_core@BR_INST_RETIRED.ALL_BRANCHES@ / cpu_core@BR_INST_RETIRED.NEAR_TAKEN@  Branch instructions per taken branch      000tma_info_inst_mix_instructions Summary;TmaL1;tma_L1_group cpu_core@INST_RETIRED.ANY@  Total number of retired Instructions Total number of retired Instructions. Sample with: INST_RETIRED.PREC_DIST     000tma_info_inst_mix_iparith Flops;InsType cpu_core@INST_RETIRED.ANY@ / (cpu_core@FP_ARITH_INST_RETIRED.SCALAR@ + cpu_core@FP_ARITH_INST_RETIRED.VECTOR@) tma_info_inst_mix_iparith < 10 Instructions per FP Arithmetic instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW     000tma_info_inst_mix_iparith_avx128 Flops;FpVector;InsType cpu_core@INST_RETIRED.ANY@ / (cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE@ + cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE@) tma_info_inst_mix_iparith_avx128 < 10 Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting     000tma_info_inst_mix_iparith_avx256 Flops;FpVector;InsType cpu_core@INST_RETIRED.ANY@ / (cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE@ + cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE@) tma_info_inst_mix_iparith_avx256 < 10 Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting     000tma_info_inst_mix_iparith_scalar_dp Flops;FpScalar;InsType cpu_core@INST_RETIRED.ANY@ / cpu_core@FP_ARITH_INST_RETIRED.SCALAR_DOUBLE@ tma_info_inst_mix_iparith_scalar_dp < 10 Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting     000tma_info_inst_mix_iparith_scalar_sp Flops;FpScalar;InsType cpu_core@INST_RETIRED.ANY@ / cpu_core@FP_ARITH_INST_RETIRED.SCALAR_SINGLE@ tma_info_inst_mix_iparith_scalar_sp < 10 Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting     000tma_info_inst_mix_ipbranch Branches;Fed;InsType cpu_core@INST_RETIRED.ANY@ / cpu_core@BR_INST_RETIRED.ALL_BRANCHES@ tma_info_inst_mix_ipbranch < 8 Instructions per Branch (lower number means higher occurrence rate)      000tma_info_inst_mix_ipcall Branches;Fed;PGO cpu_core@INST_RETIRED.ANY@ / cpu_core@BR_INST_RETIRED.NEAR_CALL@ tma_info_inst_mix_ipcall < 200 Instructions per (near) call (lower number means higher occurrence rate)      000tma_info_inst_mix_ipflop Flops;InsType cpu_core@INST_RETIRED.ANY@ / (cpu_core@FP_ARITH_INST_RETIRED.SCALAR@ + 2 * cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE@ + 4 * cpu_core@FP_ARITH_INST_RETIRED.4_FLOPS@ + 8 * cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE@) tma_info_inst_mix_ipflop < 10 Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)      000tma_info_inst_mix_ipload InsType cpu_core@INST_RETIRED.ANY@ / cpu_core@MEM_INST_RETIRED.ALL_LOADS@ tma_info_inst_mix_ipload < 3 Instructions per Load (lower number means higher occurrence rate)      000tma_info_inst_mix_ippause Flops;FpVector;InsType tma_info_inst_mix_instructions / cpu_core@CPU_CLK_UNHALTED.PAUSE_INST@  Instructions per PAUSE (lower number means higher occurrence rate)      000tma_info_inst_mix_ipstore InsType cpu_core@INST_RETIRED.ANY@ / cpu_core@MEM_INST_RETIRED.ALL_STORES@ tma_info_inst_mix_ipstore < 8 Instructions per Store (lower number means higher occurrence rate)      000tma_info_inst_mix_ipswpf Prefetches cpu_core@INST_RETIRED.ANY@ / cpu_core@SW_PREFETCH_ACCESS.ANY@ tma_info_inst_mix_ipswpf < 100 Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)      000tma_info_inst_mix_iptb Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB cpu_core@INST_RETIRED.ANY@ / cpu_core@BR_INST_RETIRED.NEAR_TAKEN@ tma_info_inst_mix_iptb < 13 Instructions per taken branch Instructions per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_lcp     000tma_info_memory_core_l1d_cache_fill_bw_2t Mem;MemoryBW tma_info_memory_l1d_cache_fill_bw  Average per-core data fill bandwidth to the L1 data cache [GB / sec]      000tma_info_memory_core_l2_cache_fill_bw_2t Mem;MemoryBW tma_info_memory_l2_cache_fill_bw  Average per-core data fill bandwidth to the L2 cache [GB / sec]      000tma_info_memory_core_l3_cache_access_bw_2t Mem;MemoryBW;Offcore tma_info_memory_l3_cache_access_bw  Average per-core data access bandwidth to the L3 cache [GB / sec]      000tma_info_memory_core_l3_cache_fill_bw_2t Mem;MemoryBW tma_info_memory_l3_cache_fill_bw  Average per-core data fill bandwidth to the L3 cache [GB / sec]      000tma_info_memory_fb_hpki CacheHits;Mem 1e3 * cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / cpu_core@INST_RETIRED.ANY@  Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)      000tma_info_memory_l1d_cache_fill_bw Mem;MemoryBW 64 * cpu_core@L1D.REPLACEMENT@ / 1e9 / tma_info_system_time  Average per-thread data fill bandwidth to the L1 data cache [GB / sec]      000tma_info_memory_l1mpki CacheHits;Mem 1e3 * cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / cpu_core@INST_RETIRED.ANY@  L1 cache true misses per kilo instruction for retired demand loads      000tma_info_memory_l1mpki_load CacheHits;Mem 1e3 * cpu_core@L2_RQSTS.ALL_DEMAND_DATA_RD@ / cpu_core@INST_RETIRED.ANY@  L1 cache true misses per kilo instruction for all demand loads (including speculative)      000tma_info_memory_l2_cache_fill_bw Mem;MemoryBW 64 * cpu_core@L2_LINES_IN.ALL@ / 1e9 / tma_info_system_time  Average per-thread data fill bandwidth to the L2 cache [GB / sec]      000tma_info_memory_l2hpki_all CacheHits;Mem 1e3 * (cpu_core@L2_RQSTS.REFERENCES@ - cpu_core@L2_RQSTS.MISS@) / cpu_core@INST_RETIRED.ANY@  L2 cache hits per kilo instruction for all request types (including speculative)      000tma_info_memory_l2hpki_load CacheHits;Mem 1e3 * cpu_core@L2_RQSTS.DEMAND_DATA_RD_HIT@ / cpu_core@INST_RETIRED.ANY@  L2 cache hits per kilo instruction for all demand loads  (including speculative)      000tma_info_memory_l2mpki Backend;CacheHits;Mem 1e3 * cpu_core@MEM_LOAD_RETIRED.L2_MISS@ / cpu_core@INST_RETIRED.ANY@  L2 cache true misses per kilo instruction for retired demand loads      000tma_info_memory_l2mpki_all CacheHits;Mem;Offcore 1e3 * cpu_core@L2_RQSTS.MISS@ / cpu_core@INST_RETIRED.ANY@  L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)      000tma_info_memory_l2mpki_load CacheHits;Mem 1e3 * cpu_core@L2_RQSTS.DEMAND_DATA_RD_MISS@ / cpu_core@INST_RETIRED.ANY@  L2 cache ([RKL+] true) misses per kilo instruction for all demand loads  (including speculative)      000tma_info_memory_l2mpki_rfo CacheMisses;Offcore 1e3 * cpu_core@L2_RQSTS.RFO_MISS@ / cpu_core@INST_RETIRED.ANY@  Offcore requests (L2 cache miss) per kilo instruction for demand RFOs      000tma_info_memory_l3_cache_access_bw Mem;MemoryBW;Offcore 64 * cpu_core@OFFCORE_REQUESTS.ALL_REQUESTS@ / 1e9 / tma_info_system_time  Average per-thread data access bandwidth to the L3 cache [GB / sec]      000tma_info_memory_l3_cache_fill_bw Mem;MemoryBW 64 * cpu_core@LONGEST_LAT_CACHE.MISS@ / 1e9 / tma_info_system_time  Average per-thread data fill bandwidth to the L3 cache [GB / sec]      000tma_info_memory_l3mpki Mem 1e3 * cpu_core@MEM_LOAD_RETIRED.L3_MISS@ / cpu_core@INST_RETIRED.ANY@  L3 cache true misses per kilo instruction for retired demand loads      000tma_info_memory_latency_data_l2_mlp Memory_BW;Offcore cpu_core@OFFCORE_REQUESTS_OUTSTANDING.DATA_RD@ / cpu_core@OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD@  Average Parallel L2 cache miss data reads      000tma_info_memory_latency_load_l2_miss_latency LockCont;Memory_Lat;Offcore cpu_core@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD@ / cpu_core@OFFCORE_REQUESTS.DEMAND_DATA_RD@  Average Latency for L2 cache miss demand Loads      000tma_info_memory_latency_load_l2_mlp Memory_BW;Offcore cpu_core@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD@ / cpu_core@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\,cmask\=1@  Average Parallel L2 cache miss demand Loads      000tma_info_memory_latency_load_l3_miss_latency Memory_Lat;Offcore cpu_core@OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD@ / cpu_core@OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD@  Average Latency for L3 cache miss demand Loads      000tma_info_memory_load_miss_real_latency Mem;MemoryBound;MemoryLat cpu_core@L1D_PEND_MISS.PENDING@ / cpu_core@MEM_LOAD_COMPLETED.L1_MISS_ANY@  Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)      000tma_info_memory_mix_bus_lock_pki Mem 1e3 * cpu_core@SQ_MISC.BUS_LOCK@ / cpu_core@INST_RETIRED.ANY@  "Bus lock" per kilo instruction      000tma_info_memory_mix_uc_load_pki Mem 1e3 * cpu_core@MEM_LOAD_MISC_RETIRED.UC@ / cpu_core@INST_RETIRED.ANY@  Un-cacheable retired load per kilo instruction      000tma_info_memory_mlp Mem;MemoryBW;MemoryBound cpu_core@L1D_PEND_MISS.PENDING@ / cpu_core@L1D_PEND_MISS.PENDING_CYCLES@  Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)     000tma_info_memory_prefetches_useless_hwpf Prefetches cpu_core@L2_LINES_OUT.USELESS_HWPF@ / (cpu_core@L2_LINES_OUT.SILENT@ + cpu_core@L2_LINES_OUT.NON_SILENT@) tma_info_memory_prefetches_useless_hwpf > 0.15 Rate of L2 HW prefetched lines that were not used by demand accesses      000tma_info_memory_tlb_code_stlb_mpki Fed;MemoryTLB 1e3 * cpu_core@ITLB_MISSES.WALK_COMPLETED@ / cpu_core@INST_RETIRED.ANY@  STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)      000tma_info_memory_tlb_load_stlb_mpki Mem;MemoryTLB 1e3 * cpu_core@DTLB_LOAD_MISSES.WALK_COMPLETED@ / cpu_core@INST_RETIRED.ANY@  STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)      000tma_info_memory_tlb_page_walks_utilization Mem;MemoryTLB (cpu_core@ITLB_MISSES.WALK_PENDING@ + cpu_core@DTLB_LOAD_MISSES.WALK_PENDING@ + cpu_core@DTLB_STORE_MISSES.WALK_PENDING@) / (4 * tma_info_core_core_clks) tma_info_memory_tlb_page_walks_utilization > 0.5 Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses      000tma_info_memory_tlb_store_stlb_mpki Mem;MemoryTLB 1e3 * cpu_core@DTLB_STORE_MISSES.WALK_COMPLETED@ / cpu_core@INST_RETIRED.ANY@  STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)      000tma_info_pipeline_execute Cor;Pipeline;PortsUtil;SMT cpu_core@UOPS_EXECUTED.THREAD@ / (cpu_core@UOPS_EXECUTED.CORE_CYCLES_GE_1@ / 2 if #SMT_on else cpu_core@UOPS_EXECUTED.THREAD\,cmask\=1@)  Mem;Backend;CacheHits      000tma_info_pipeline_fetch_dsb Fed;FetchBW cpu_core@IDQ.DSB_UOPS@ / cpu_core@IDQ.DSB_CYCLES_ANY@  Average number of uops fetched from DSB per cycle      000tma_info_pipeline_fetch_lsd Fed;FetchBW cpu_core@LSD.UOPS@ / cpu_core@LSD.CYCLES_ACTIVE@  Average number of uops fetched from LSD per cycle      000tma_info_pipeline_fetch_mite Fed;FetchBW cpu_core@IDQ.MITE_UOPS@ / cpu_core@IDQ.MITE_CYCLES_ANY@  Average number of uops fetched from MITE per cycle      000tma_info_pipeline_ipassist MicroSeq;Pipeline;Ret;Retire cpu_core@INST_RETIRED.ANY@ / cpu_core@ASSISTS.ANY@ tma_info_pipeline_ipassist < 100e3 Instructions per a microcode Assist invocation Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate)     000tma_info_pipeline_retire Pipeline;Ret tma_retiring * tma_info_thread_slots / cpu_core@UOPS_RETIRED.SLOTS\,cmask\=1@  Average number of Uops retired in cycles where at least one uop has retired      000tma_info_pipeline_strings_cycles MicroSeq;Pipeline;Ret cpu_core@INST_RETIRED.REP_ITERATION@ / cpu_core@UOPS_RETIRED.SLOTS\,cmask\=1@ tma_info_pipeline_strings_cycles > 0.1 Estimated fraction of retirement-cycles dealing with repeat instructions      000tma_info_system_c0_wait C0Wait cpu_core@CPU_CLK_UNHALTED.C0_WAIT@ / tma_info_thread_clks tma_info_system_c0_wait > 0.05 Fraction of cycles the processor is waiting yet unhalted; covering legacy PAUSE instruction, as well as C0.1 / C0.2 power-performance optimized states      000tma_info_system_core_frequency Power;Summary tma_info_system_turbo_utilization * msr@tsc\,cpu\=cpu_core@ / 1e9 / tma_info_system_time  Measured Average Core Frequency for unhalted processors [GHz]      000tma_info_system_cpu_utilization HPC;Summary tma_info_system_cpus_utilized / #num_cpus_online  Average CPU Utilization (percentage)      000tma_info_system_cpus_utilized Summary cpu_core@CPU_CLK_UNHALTED.REF_TSC@ / msr@tsc\,cpu\=cpu_core@  Average number of utilized CPUs      000tma_info_system_dram_bw_use HPC;MemOffcore;MemoryBW;SoC;tma_issueBW 64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / tma_info_system_time / 1e3  Average external Memory Bandwidth Use for reads and writes [GB / sec] Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_bottleneck_data_cache_memory_bandwidth, tma_fb_full, tma_mem_bandwidth, tma_sq_full     000tma_info_system_gflops Cor;Flops;HPC (cpu_core@FP_ARITH_INST_RETIRED.SCALAR@ + 2 * cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE@ + 4 * cpu_core@FP_ARITH_INST_RETIRED.4_FLOPS@ + 8 * cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE@) / 1e9 / tma_info_system_time  Giga Floating Point Operations Per Second Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width     000tma_info_system_ipfarbranch Branches;OS cpu_core@INST_RETIRED.ANY@ / cpu_core@BR_INST_RETIRED.FAR_BRANCH@u tma_info_system_ipfarbranch < 1e6 Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]      000tma_info_system_kernel_cpi OS cpu_core@CPU_CLK_UNHALTED.THREAD_P@k / cpu_core@INST_RETIRED.ANY_P@k  Cycles Per Instruction for the Operating System (OS) Kernel mode      000tma_info_system_kernel_utilization OS cpu_core@CPU_CLK_UNHALTED.THREAD_P@k / cpu_core@CPU_CLK_UNHALTED.THREAD@ tma_info_system_kernel_utilization > 0.05 Fraction of cycles spent in the Operating System (OS) Kernel mode      000tma_info_system_mem_parallel_reads Mem;MemoryBW;SoC UNC_ARB_DAT_OCCUPANCY.RD / UNC_ARB_DAT_OCCUPANCY.RD@cmask\=1@  Average number of parallel data read requests to external memory Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches     000tma_info_system_mem_read_latency Mem;MemoryLat;SoC (UNC_ARB_TRK_OCCUPANCY.RD + UNC_ARB_DAT_OCCUPANCY.RD) / UNC_ARB_TRK_REQUESTS.RD  Average latency of data read request to external memory (in nanoseconds) Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)     000tma_info_system_mux Summary cpu_core@CPU_CLK_UNHALTED.THREAD_P@ / cpu_core@CPU_CLK_UNHALTED.THREAD@ tma_info_system_mux > 1.1 | tma_info_system_mux < 0.9 PerfMon Event Multiplexing accuracy indicator      000tma_info_system_power Power;SoC power@energy\-pkg@ * 61 / (tma_info_system_time * 1e6)  Total package Power in Watts      000tma_info_system_smt_2t_utilization SMT (1 - cpu_core@CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE@ / cpu_core@CPU_CLK_UNHALTED.REF_DISTRIBUTED@ if #SMT_on else 0)  Fraction of cycles where both hardware Logical Processors were active      000tma_info_system_socket_clks SoC UNC_CLOCK.SOCKET  Socket actual clocks when any core is active on that socket      000tma_info_system_time Summary duration_time tma_info_system_time < 1 Run duration time in seconds      000tma_info_system_turbo_utilization Power tma_info_thread_clks / cpu_core@CPU_CLK_UNHALTED.REF_TSC@  Average Frequency Utilization relative nominal frequency      000tma_info_system_uncore_frequency SoC tma_info_system_socket_clks / 1e9 / tma_info_system_time  Measured Average Uncore Frequency for the SoC [GHz]      000tma_info_thread_clks Pipeline cpu_core@CPU_CLK_UNHALTED.THREAD@  Per-Logical Processor actual clocks when the Logical Processor is active      000tma_info_thread_cpi Mem;Pipeline 1 / tma_info_thread_ipc  Cycles Per Instruction (per Logical Processor)      000tma_info_thread_execute_per_issue Cor;Pipeline cpu_core@UOPS_EXECUTED.THREAD@ / cpu_core@UOPS_ISSUED.ANY@  The ratio of Executed- by Issued-Uops The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of "execute" at rename stage     000tma_info_thread_ipc Ret;Summary cpu_core@INST_RETIRED.ANY@ / tma_info_thread_clks  Instructions Per Cycle (per Logical Processor)      000tma_info_thread_slots TmaL1;tma_L1_group cpu_core@TOPDOWN.SLOTS@  Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)      000tma_info_thread_slots_utilization SMT;TmaL1;tma_L1_group (tma_info_thread_slots / (cpu_core@TOPDOWN.SLOTS@ / 2) if #SMT_on else 1)  Fraction of Physical Core issue-slots utilized by this Logical Processor      000tma_info_thread_uoppi Pipeline;Ret;Retire tma_retiring * tma_info_thread_slots / cpu_core@INST_RETIRED.ANY@ tma_info_thread_uoppi > 1.05 Uops Per Instruction      000tma_info_thread_uptb Branches;Fed;FetchBW tma_retiring * tma_info_thread_slots / cpu_core@BR_INST_RETIRED.NEAR_TAKEN@ tma_info_thread_uptb < 9 Uops per taken branch      000tma_int_divider TopdownL4;tma_L4_group;tma_divider_group tma_divider - tma_fp_divider tma_int_divider > 0.2 & (tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles where the Integer Divider unit was active  100%    000tma_int_operations Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_int_vector_128b + tma_int_vector_256b tma_int_operations > 0.1 & tma_light_operations > 0.6 This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired) This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired). Vector/Matrix Int operations and shuffles are counted. Note this metric's value may exceed its parent due to use of "Uops" CountDomain 100%    000tma_int_vector_128b Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group;tma_issue2P (cpu_core@INT_VEC_RETIRED.ADD_128@ + cpu_core@INT_VEC_RETIRED.VNNI_128@) / (tma_retiring * tma_info_thread_slots) tma_int_vector_128b > 0.1 & (tma_int_operations > 0.1 & tma_light_operations > 0.6) This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_int_vector_256b Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group;tma_issue2P (cpu_core@INT_VEC_RETIRED.ADD_256@ + cpu_core@INT_VEC_RETIRED.MUL_256@ + cpu_core@INT_VEC_RETIRED.VNNI_256@) / (tma_retiring * tma_info_thread_slots) tma_int_vector_256b > 0.1 & (tma_int_operations > 0.1 & tma_light_operations > 0.6) This metric represents 256-bit vector Integer ADD/SUB/SAD/MUL or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired This metric represents 256-bit vector Integer ADD/SUB/SAD/MUL or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_itlb_misses BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group cpu_core@ICACHE_TAG.STALLS@ / tma_info_thread_clks tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS 100%    000tma_l1_bound CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group max((cpu_core@EXE_ACTIVITY.BOUND_ON_LOADS@ - cpu_core@MEMORY_ACTIVITY.STALLS_L1D_MISS@) / tma_info_thread_clks, 0) tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled without loads missing the L1 Data (L1D) cache This metric estimates how often the CPU was stalled without loads missing the L1 Data (L1D) cache.  The L1D cache typically has the shortest latency.  However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1D. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1 100%    000tma_l1_latency_dependency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_l1_bound_group min(2 * (cpu_core@MEM_INST_RETIRED.ALL_LOADS@ - cpu_core@MEM_LOAD_RETIRED.FB_HIT@ - cpu_core@MEM_LOAD_RETIRED.L1_MISS@) * 20 / 100, max(cpu_core@CYCLE_ACTIVITY.CYCLES_MEM_ANY@ - cpu_core@MEMORY_ACTIVITY.CYCLES_L1D_MISS@, 0)) / tma_info_thread_clks tma_l1_latency_dependency > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric ([SKL+] roughly; [LNL]) estimates fraction of cycles with demand load accesses that hit the L1D cache This metric ([SKL+] roughly; [LNL]) estimates fraction of cycles with demand load accesses that hit the L1D cache. The short latency of the L1D cache may be exposed in pointer-chasing memory access patterns as an example. Sample with: MEM_LOAD_RETIRED.L1_HIT 100%    000tma_l2_bound BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (cpu_core@MEMORY_ACTIVITY.STALLS_L1D_MISS@ - cpu_core@MEMORY_ACTIVITY.STALLS_L2_MISS@) / tma_info_thread_clks tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to L2 cache accesses by loads This metric estimates how often the CPU was stalled due to L2 cache accesses by loads.  Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT 100%    000tma_l2_hit_latency MemoryLat;TopdownL4;tma_L4_group;tma_l2_bound_group 3 * tma_info_system_core_frequency * cpu_core@MEM_LOAD_RETIRED.L2_HIT@ * (1 + cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / 2) / tma_info_thread_clks tma_l2_hit_latency > 0.05 & (tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles with demand load accesses that hit the L2 cache under unloaded scenarios (possibly L2 latency limited) This metric represents fraction of cycles with demand load accesses that hit the L2 cache under unloaded scenarios (possibly L2 latency limited).  Avoiding L1 cache misses (i.e. L1 misses/L2 hits) will improve the latency. Sample with: MEM_LOAD_RETIRED.L2_HIT 100%    000tma_l3_bound CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (cpu_core@MEMORY_ACTIVITY.STALLS_L2_MISS@ - cpu_core@MEMORY_ACTIVITY.STALLS_L3_MISS@) / tma_info_thread_clks tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core.  Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS 100%    000tma_l3_hit_latency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 9 * tma_info_system_core_frequency * (cpu_core@MEM_LOAD_RETIRED.L3_HIT@ * (1 + cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / 2)) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_bottleneck_data_cache_memory_latency, tma_mem_latency 100%    000tma_lcp FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB cpu_core@DECODE.LCP@ / tma_info_thread_clks tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs) This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb 100%    000tma_light_operations Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group max(0, tma_retiring - tma_heavy_operations) tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation) This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .). Sample with: INST_RETIRED.PREC_DIST 100%  TopdownL2  000tma_load_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group cpu_core@UOPS_DISPATCHED.PORT_2_3_10@ / (3 * tma_info_core_core_clks) tma_load_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3_10 100%    000tma_load_stlb_hit MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group tma_dtlb_load - tma_load_stlb_miss tma_load_stlb_hit > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)  100%    000tma_load_stlb_miss MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group cpu_core@DTLB_LOAD_MISSES.WALK_ACTIVE@ / tma_info_thread_clks tma_load_stlb_miss > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk  100%    000tma_load_stlb_miss_1g MemoryTLB;TopdownL6;tma_L6_group;tma_load_stlb_miss_group tma_load_stlb_miss * cpu_core@DTLB_LOAD_MISSES.WALK_COMPLETED_1G@ / (cpu_core@DTLB_LOAD_MISSES.WALK_COMPLETED_4K@ + cpu_core@DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M@ + cpu_core@DTLB_LOAD_MISSES.WALK_COMPLETED_1G@) tma_load_stlb_miss_1g > 0.05 & (tma_load_stlb_miss > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))) This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 1 GB pages for data load accesses  100%    000tma_load_stlb_miss_2m MemoryTLB;TopdownL6;tma_L6_group;tma_load_stlb_miss_group tma_load_stlb_miss * cpu_core@DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M@ / (cpu_core@DTLB_LOAD_MISSES.WALK_COMPLETED_4K@ + cpu_core@DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M@ + cpu_core@DTLB_LOAD_MISSES.WALK_COMPLETED_1G@) tma_load_stlb_miss_2m > 0.05 & (tma_load_stlb_miss > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))) This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 2 or 4 MB pages for data load accesses  100%    000tma_load_stlb_miss_4k MemoryTLB;TopdownL6;tma_L6_group;tma_load_stlb_miss_group tma_load_stlb_miss * cpu_core@DTLB_LOAD_MISSES.WALK_COMPLETED_4K@ / (cpu_core@DTLB_LOAD_MISSES.WALK_COMPLETED_4K@ + cpu_core@DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M@ + cpu_core@DTLB_LOAD_MISSES.WALK_COMPLETED_1G@) tma_load_stlb_miss_4k > 0.05 & (tma_load_stlb_miss > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))) This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 4 KB pages for data load accesses  100%    000tma_lock_latency LockCont;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group (16 * max(0, cpu_core@MEM_INST_RETIRED.LOCK_LOADS@ - cpu_core@L2_RQSTS.ALL_RFO@) + cpu_core@MEM_INST_RETIRED.LOCK_LOADS@ / cpu_core@MEM_INST_RETIRED.ALL_STORES@ * (10 * cpu_core@L2_RQSTS.RFO_HIT@ + min(cpu_core@CPU_CLK_UNHALTED.THREAD@, cpu_core@OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO@))) / tma_info_thread_clks tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS. Related metrics: tma_store_latency 100%    010tma_lsd FetchBW;LSD;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group (cpu_core@LSD.CYCLES_ACTIVE@ - cpu_core@LSD.CYCLES_OK@) / tma_info_core_core_clks / 2 tma_lsd > 0.15 & tma_fetch_bandwidth > 0.2 This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit.  LSD typically does well sustaining Uop supply. However; in some rare cases; optimal uop-delivery could not be reached for small loops whose size (in terms of number of uops) does not suit well the LSD structure 100%    000tma_machine_clears BadSpec;BvMS;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn max(0, tma_bad_speculation - tma_branch_mispredicts) tma_machine_clears > 0.1 & tma_bad_speculation > 0.15 This metric represents fraction of slots the CPU has wasted due to Machine Clears This metric represents fraction of slots the CPU has wasted due to Machine Clears.  These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_bottleneck_memory_synchronization, tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache 100%  TopdownL2  000tma_mem_bandwidth BvMB;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW min(cpu_core@CPU_CLK_UNHALTED.THREAD@, cpu_core@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=4@) / tma_info_thread_clks tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM).  The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_bottleneck_data_cache_memory_bandwidth, tma_fb_full, tma_info_system_dram_bw_use, tma_sq_full 100%    000tma_mem_latency BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat min(cpu_core@CPU_CLK_UNHALTED.THREAD@, cpu_core@OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD@) / tma_info_thread_clks - tma_mem_bandwidth tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM) This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM).  This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: tma_bottleneck_data_cache_memory_latency, tma_l3_hit_latency 100%    000tma_memory_bound Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group cpu_core@topdown\-mem\-bound@ / (cpu_core@topdown\-fe\-bound@ + cpu_core@topdown\-bad\-spec@ + cpu_core@topdown\-retiring@ + cpu_core@topdown\-be\-bound@) tma_memory_bound > 0.2 & tma_backend_bound > 0.2 This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two) 100%  TopdownL2  000tma_memory_fence TopdownL4;tma_L4_group;tma_serializing_operation_group 13 * cpu_core@MISC2_RETIRED.LFENCE@ / tma_info_thread_clks tma_memory_fence > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU was stalled due to LFENCE Instructions  100%    000tma_memory_operations Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * cpu_core@MEM_UOP_RETIRED.ANY@ / (tma_retiring * tma_info_thread_slots) tma_memory_operations > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses  100%    000tma_microcode_sequencer MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS cpu_core@UOPS_RETIRED.MS@ / tma_info_thread_slots tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1 This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: UOPS_RETIRED.MS. Related metrics: tma_bottleneck_irregular_overhead, tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_ms_switches 100%    000tma_mispredicts_resteers BadSpec;BrMispredicts;BvMP;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM tma_branch_mispredicts / tma_bad_speculation * cpu_core@INT_MISC.CLEAR_RESTEER_CYCLES@ / tma_info_thread_clks tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_bottleneck_mispredictions, tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost 100%    000tma_mite DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group (cpu_core@IDQ.MITE_CYCLES_ANY@ - cpu_core@IDQ.MITE_CYCLES_OK@) / tma_info_core_core_clks / 2 tma_mite > 0.1 & tma_fetch_bandwidth > 0.2 This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline) This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS 100%    000tma_mixing_vectors TopdownL5;tma_L5_group;tma_issueMV;tma_ports_utilized_0_group 160 * cpu_core@ASSISTS.SSE_AVX_MIX@ / tma_info_thread_clks tma_mixing_vectors > 0.05 This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [ADL+] cycles) This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [ADL+] cycles). Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic. Related metrics: tma_ms_switches 100%    000tma_ms MicroSeq;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group max(cpu_core@IDQ.MS_CYCLES_ANY@, cpu_core@UOPS_RETIRED.MS\,cmask\=1@ / (cpu_core@UOPS_RETIRED.SLOTS@ / cpu_core@UOPS_ISSUED.ANY@)) / tma_info_core_core_clks / 2.4 tma_ms > 0.05 & tma_fetch_bandwidth > 0.2 This metric represents Core fraction of cycles in which CPU was likely limited due to the Microcode Sequencer (MS) unit - see Microcode_Sequencer node for details  100%    000tma_ms_switches FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO 3 * cpu_core@UOPS_RETIRED.MS\,cmask\=1\,edge@ / (cpu_core@UOPS_RETIRED.SLOTS@ / cpu_core@UOPS_ISSUED.ANY@) / tma_info_thread_clks tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: FRONTEND_RETIRED.MS_FLOWS. Related metrics: tma_bottleneck_irregular_overhead, tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation 100%    000tma_non_fused_branches Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * (cpu_core@BR_INST_RETIRED.ALL_BRANCHES@ - cpu_core@INST_RETIRED.MACRO_FUSED@) / (tma_retiring * tma_info_thread_slots) tma_non_fused_branches > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused 100%    000tma_nop_instructions BvBO;Pipeline;TopdownL4;tma_L4_group;tma_other_light_ops_group tma_light_operations * cpu_core@INST_RETIRED.NOP@ / (tma_retiring * tma_info_thread_slots) tma_nop_instructions > 0.1 & (tma_other_light_ops > 0.3 & tma_light_operations > 0.6) This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP 100%    000tma_other_light_ops Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group max(0, tma_light_operations - (tma_fp_arith + tma_int_operations + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches)) tma_other_light_ops > 0.3 & tma_light_operations > 0.6 This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting 100%    010tma_other_mispredicts BrMispredicts;BvIO;TopdownL3;tma_L3_group;tma_branch_mispredicts_group max(tma_branch_mispredicts * (1 - cpu_core@BR_MISP_RETIRED.ALL_BRANCHES@ / (cpu_core@INT_MISC.CLEARS_COUNT@ - cpu_core@MACHINE_CLEARS.COUNT@)), 0.0001) tma_other_mispredicts > 0.05 & (tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15) This metric estimates fraction of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches or other types)  100%    000tma_other_nukes BvIO;Machine_Clears;TopdownL3;tma_L3_group;tma_machine_clears_group max(tma_machine_clears * (1 - cpu_core@MACHINE_CLEARS.MEMORY_ORDERING@ / cpu_core@MACHINE_CLEARS.COUNT@), 0.0001) tma_other_nukes > 0.05 & (tma_machine_clears > 0.1 & tma_bad_speculation > 0.15) This metric represents fraction of slots the CPU has wasted due to Nukes (Machine Clears) not related to memory ordering  100%    000tma_page_faults TopdownL5;tma_L5_group;tma_assists_group 99 * cpu_core@ASSISTS.PAGE_FAULT@ / tma_info_thread_slots tma_page_faults > 0.05 This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults. A Page Fault may apply on first application access to a memory page. Note operating system handling of page faults accounts for the majority of its cost 100%    000tma_port_0 Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P cpu_core@UOPS_DISPATCHED.PORT_0@ / tma_info_core_core_clks tma_port_0 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_port_1 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P cpu_core@UOPS_DISPATCHED.PORT_1@ / tma_info_core_core_clks tma_port_1 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_port_6 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P cpu_core@UOPS_DISPATCHED.PORT_6@ / tma_info_core_core_clks tma_port_6 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2 100%    000tma_ports_utilization PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group ((tma_ports_utilized_0 * tma_info_thread_clks + (cpu_core@EXE_ACTIVITY.1_PORTS_UTIL@ + tma_retiring * cpu_core@EXE_ACTIVITY.2_3_PORTS_UTIL@)) / tma_info_thread_clks if cpu_core@ARITH.DIV_ACTIVE@ < cpu_core@CYCLE_ACTIVITY.STALLS_TOTAL@ - cpu_core@EXE_ACTIVITY.BOUND_ON_LOADS@ else (cpu_core@EXE_ACTIVITY.1_PORTS_UTIL@ + tma_retiring * cpu_core@EXE_ACTIVITY.2_3_PORTS_UTIL@) / tma_info_thread_clks) tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations 100%    020tma_ports_utilized_0 PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group (cpu_core@EXE_ACTIVITY.EXE_BOUND_0_PORTS@ + max(cpu_core@RS.EMPTY_RESOURCE@ - cpu_core@RESOURCE_STALLS.SCOREBOARD@, 0)) / tma_info_thread_clks * (cpu_core@CYCLE_ACTIVITY.STALLS_TOTAL@ - cpu_core@EXE_ACTIVITY.BOUND_ON_LOADS@) / tma_info_thread_clks tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric 100%    040tma_ports_utilized_1 PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group cpu_core@EXE_ACTIVITY.1_PORTS_UTIL@ / tma_info_thread_clks tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL. Related metrics: tma_l1_bound 100%    040tma_ports_utilized_2 PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group cpu_core@EXE_ACTIVITY.2_PORTS_UTIL@ / tma_info_thread_clks tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).  Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6 100%    000tma_ports_utilized_3m BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group cpu_core@UOPS_EXECUTED.CYCLES_GE_3@ / tma_info_thread_clks tma_ports_utilized_3m > 0.4 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3 100%    000tma_retiring BvUW;Default;TmaL1;TopdownL1;tma_L1_group cpu_core@topdown\-retiring@ / (cpu_core@topdown\-fe\-bound@ + cpu_core@topdown\-bad\-spec@ + cpu_core@topdown\-retiring@ + cpu_core@topdown\-be\-bound@) tma_retiring > 0.7 | tma_heavy_operations > 0.1 This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category.  Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved.  Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance.  For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS 100%  TopdownL1;Default TopdownL1 000tma_serializing_operation BvIO;PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group;tma_issueSO cpu_core@RESOURCE_STALLS.SCOREBOARD@ / tma_info_thread_clks + tma_c02_wait tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: RESOURCE_STALLS.SCOREBOARD. Related metrics: tma_ms_switches 100%    000tma_shuffles_256b HPC;Pipeline;TopdownL4;tma_L4_group;tma_other_light_ops_group tma_light_operations * cpu_core@INT_VEC_RETIRED.SHUFFLES@ / (tma_retiring * tma_info_thread_slots) tma_shuffles_256b > 0.1 & (tma_other_light_ops > 0.3 & tma_light_operations > 0.6) This metric represents fraction of slots where the CPU was retiring Shuffle operations of 256-bit vector size (FP or Integer) This metric represents fraction of slots where the CPU was retiring Shuffle operations of 256-bit vector size (FP or Integer). Shuffles may incur slow cross "vector lane" data transfers 100%    000tma_slow_pause TopdownL4;tma_L4_group;tma_serializing_operation_group cpu_core@CPU_CLK_UNHALTED.PAUSE@ / tma_info_thread_clks tma_slow_pause > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: CPU_CLK_UNHALTED.PAUSE_INST 100%    000tma_split_loads TopdownL4;tma_L4_group;tma_l1_bound_group tma_info_memory_load_miss_real_latency * cpu_core@LD_BLOCKS.NO_SR@ / tma_info_thread_clks tma_split_loads > 0.3 This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS 100%    000tma_split_stores TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group cpu_core@MEM_INST_RETIRED.SPLIT_STORES@ / tma_info_core_core_clks tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents rate of split store accesses This metric represents rate of split store accesses.  Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4 100%    000tma_sq_full BvMB;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group (cpu_core@XQ.FULL_CYCLES@ + cpu_core@L1D_PEND_MISS.L2_STALLS@) / tma_info_thread_clks tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors) This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_bottleneck_data_cache_memory_bandwidth, tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth 100%    000tma_store_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group cpu_core@EXE_ACTIVITY.BOUND_ON_STORES@ / tma_info_thread_clks tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS 100%    000tma_store_fwd_blk TopdownL4;tma_L4_group;tma_l1_bound_group 13 * cpu_core@LD_BLOCKS.STORE_FORWARD@ / tma_info_thread_clks tma_store_fwd_blk > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading 100%    000tma_store_latency BvML;LockCont;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group (cpu_core@MEM_STORE_RETIRED.L2_HIT@ * 10 * (1 - cpu_core@MEM_INST_RETIRED.LOCK_LOADS@ / cpu_core@MEM_INST_RETIRED.ALL_STORES@) + (1 - cpu_core@MEM_INST_RETIRED.LOCK_LOADS@ / cpu_core@MEM_INST_RETIRED.ALL_STORES@) * min(cpu_core@CPU_CLK_UNHALTED.THREAD@, cpu_core@OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO@)) / tma_info_thread_clks tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles the CPU spent handling L1D store misses This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency 100%    000tma_store_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (cpu_core@UOPS_DISPATCHED.PORT_4_9@ + cpu_core@UOPS_DISPATCHED.PORT_7_8@) / (4 * tma_info_core_core_clks) tma_store_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations. Sample with: UOPS_DISPATCHED.PORT_7_8 100%    000tma_store_stlb_hit MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group tma_dtlb_store - tma_store_stlb_miss tma_store_stlb_hit > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)  100%    000tma_store_stlb_miss MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group cpu_core@DTLB_STORE_MISSES.WALK_ACTIVE@ / tma_info_core_core_clks tma_store_stlb_miss > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk  100%    000tma_store_stlb_miss_1g MemoryTLB;TopdownL6;tma_L6_group;tma_store_stlb_miss_group tma_store_stlb_miss * cpu_core@DTLB_STORE_MISSES.WALK_COMPLETED_1G@ / (cpu_core@DTLB_STORE_MISSES.WALK_COMPLETED_4K@ + cpu_core@DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M@ + cpu_core@DTLB_STORE_MISSES.WALK_COMPLETED_1G@) tma_store_stlb_miss_1g > 0.05 & (tma_store_stlb_miss > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))) This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 1 GB pages for data store accesses  100%    000tma_store_stlb_miss_2m MemoryTLB;TopdownL6;tma_L6_group;tma_store_stlb_miss_group tma_store_stlb_miss * cpu_core@DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M@ / (cpu_core@DTLB_STORE_MISSES.WALK_COMPLETED_4K@ + cpu_core@DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M@ + cpu_core@DTLB_STORE_MISSES.WALK_COMPLETED_1G@) tma_store_stlb_miss_2m > 0.05 & (tma_store_stlb_miss > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))) This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 2 or 4 MB pages for data store accesses  100%    000tma_store_stlb_miss_4k MemoryTLB;TopdownL6;tma_L6_group;tma_store_stlb_miss_group tma_store_stlb_miss * cpu_core@DTLB_STORE_MISSES.WALK_COMPLETED_4K@ / (cpu_core@DTLB_STORE_MISSES.WALK_COMPLETED_4K@ + cpu_core@DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M@ + cpu_core@DTLB_STORE_MISSES.WALK_COMPLETED_1G@) tma_store_stlb_miss_4k > 0.05 & (tma_store_stlb_miss > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))) This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 4 KB pages for data store accesses  100%    000tma_streaming_stores MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueSmSt;tma_store_bound_group 9 * cpu_core@OCR.STREAMING_WR.ANY_RESPONSE@ / tma_info_thread_clks tma_streaming_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates how often CPU was stalled  due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores This metric estimates how often CPU was stalled  due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck. Sample with: OCR.STREAMING_WR.ANY_RESPONSE. Related metrics: tma_fb_full 100%    000tma_unknown_branches BigFootprint;BvBC;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group cpu_core@INT_MISC.UNKNOWN_BRANCH_CYCLES@ / tma_info_thread_clks tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to new branch address clears This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches. Sample with: FRONTEND_RETIRED.UNKNOWN_BRANCH 100%    000tma_x87_use Compute;TopdownL4;tma_L4_group;tma_fp_arith_group tma_retiring * cpu_core@UOPS_EXECUTED.X87@ / cpu_core@UOPS_EXECUTED.THREAD@ tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric serves as an approximation of legacy x87 usage This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint 100%    000lpm_cycles cycles breakdown per privilege level (users, kernel, guest) lpm_cpu_power Running Average Power Limit (RAPL) power consumption estimates smi System Management Interrupt metrics lpm_br breakdown of retired branch instructions lpm_cs Number of context switches per second, instructions retired & core cycles between context switches lpm_l2 L2 data cache analysis lpm_ldst Breakdown of load/store instructions lpm_ports functional unit (port) utilization -- fraction of cycles each port is utilized (higher is better) lpm_swpf Software prefetch instruction breakdown lpm_br_cond_insn_between_branches lpm_br;lpm_br_cond;lpm_br_cond_tkn d_ratio(instructions, BR_INST_RETIRED.COND)  The number of instructions divided by the number of conditional branches  1insn    000lpm_br_cond_insn_between_branches lpm_br;lpm_br_cond;lpm_br_cond_nt d_ratio(instructions, BR_INST_RETIRED.COND_NTAKEN)  The number of instructions divided by the number of not taken conditional branches  1insn    000lpm_br_cond_mispred lpm_br;lpm_br_cond;lpm_br_cond_nt d_ratio(BR_MISP_RETIRED.COND_NTAKEN, BR_INST_RETIRED.COND_NTAKEN)  Retired not taken conditional branch instructions mispredicted as a percentage of all not taken conditional branches  100%    000lpm_br_cond_mispred lpm_br;lpm_br_cond;lpm_br_cond_tkn d_ratio(BR_MISP_RETIRED.COND, BR_INST_RETIRED.COND)  Retired conditional branch instructions mispredicted as a percentage of all conditional branches  100%    000lpm_br_cond_retired lpm_br;lpm_br_cond;lpm_br_cond_tkn d_ratio(BR_INST_RETIRED.COND, duration_time)  Retired conditional branch instructions  1insn/s    000lpm_br_cond_retired lpm_br;lpm_br_cond;lpm_br_cond_nt d_ratio(BR_INST_RETIRED.COND_NTAKEN, duration_time)  Retired conditional not taken branch instructions  1insn/s    000lpm_br_far_insn_between_branches lpm_br;lpm_br_far d_ratio(instructions, BR_INST_RETIRED.FAR_BRANCH)  The number of instructions divided by the number of far branches  1insn    000lpm_br_far_retired lpm_br;lpm_br_far d_ratio(BR_INST_RETIRED.FAR_BRANCH, duration_time)  Retired far control transfers per second  1insn/s    000lpm_br_taken_insn_between_branches lpm_br;lpm_br_taken d_ratio(instructions, BR_INST_RETIRED.ALL_BRANCHES)  The number of instructions divided by the number of taken branches  1insn    000lpm_br_taken_mispred lpm_br;lpm_br_taken d_ratio(BR_MISP_RETIRED.NEAR_TAKEN, BR_INST_RETIRED.ALL_BRANCHES)  The number of retired taken branch instructions that were mispredicted as a percentage of all taken branches  100%    000lpm_br_taken_retired lpm_br;lpm_br_taken d_ratio(BR_INST_RETIRED.ALL_BRANCHES, duration_time)  The number of taken branches that were retired per second  1insn/s    000lpm_br_total_insn_between_branches lpm_br;lpm_br_total d_ratio(instructions, BR_INST_RETIRED.ALL_BRANCHES)  The number of instructions divided by the number of branches  1insn    000lpm_br_total_insn_fe_resteers lpm_br;lpm_br_total d_ratio(BACLEARS.ANY, duration_time)  The number of resync branches per second  1req/s    000lpm_br_total_mispred lpm_br;lpm_br_total d_ratio(BR_MISP_RETIRED.ALL_BRANCHES, BR_INST_RETIRED.ALL_BRANCHES)  The number of branch instructions retired, of any type, that were not correctly predicted as a percentage of all branch instrucions  100%    000lpm_br_total_retired lpm_br;lpm_br_total d_ratio(BR_INST_RETIRED.ALL_BRANCHES, duration_time)  The number of branch instructions retired per second  1insn/s    000lpm_cpu_power_cores lpm_cpu_power d_ratio((power@energy\-cores@ if has_event(power@energy\-cores@) else NaN) * 232.83064365386963e-12, duration_time)    1Watts    000lpm_cpu_power_gpu lpm_cpu_power d_ratio((power@energy\-gpu@ if has_event(power@energy\-gpu@) else NaN) * 232.83064365386963e-12, duration_time)    1Watts    000lpm_cpu_power_pkg lpm_cpu_power d_ratio((power@energy\-pkg@ if has_event(power@energy\-pkg@) else NaN) * 232.83064365386963e-12, duration_time)    1Watts    000lpm_cpu_power_psys lpm_cpu_power d_ratio((power@energy\-psys@ if has_event(power@energy\-psys@) else NaN) * 232.83064365386963e-12, duration_time)    1Watts    000lpm_cpu_power_ram lpm_cpu_power d_ratio((power@energy\-ram@ if has_event(power@energy\-ram@) else NaN) * 232.83064365386963e-12, duration_time)    1Watts    000lpm_cs_br_taken lpm_cs d_ratio(BR_INST_RETIRED.NEAR_TAKEN, context\-switches)  Branches taken per context switch  1br_taken/cs    000lpm_cs_cycles lpm_cs d_ratio(cycles, context\-switches)  Cycles per context switch  1cycles/cs    000lpm_cs_instr lpm_cs d_ratio(instructions, context\-switches)  Instructions per context switch  1instr/cs    000lpm_cs_l2_misses lpm_cs d_ratio(L2_RQSTS.DEMAND_DATA_RD_MISS + L2_RQSTS.RFO_MISS + L2_RQSTS.CODE_RD_MISS + L2_RQSTS.HWPF_MISS, context\-switches)  L2 misses per context switch  1l2_misses/cs    000lpm_cs_loads lpm_cs d_ratio(MEM_INST_RETIRED.ALL_LOADS, context\-switches)  Loads per context switch  1loads/cs    000lpm_cs_rate lpm_cs d_ratio(context\-switches, duration_time)  Context switches per second  1ctxsw/s    000lpm_cs_stores lpm_cs d_ratio(MEM_INST_RETIRED.ALL_STORES, context\-switches)  Stores per context switch  1stores/cs    000lpm_cycles_guest lpm_cycles d_ratio(cpu\-cycles:G, cpu\-cycles:kHh + cpu\-cycles:G + cpu\-cycles:uH)  Hypervisor guest cycles as a percentage of all cycles  100%    000lpm_cycles_kernel lpm_cycles d_ratio(cpu\-cycles:kHh, cpu\-cycles:kHh + cpu\-cycles:G + cpu\-cycles:uH)  Kernel cycles as a percentage of all cycles  100%    000lpm_cycles_total lpm_cycles cpu\-cycles:kHh + cpu\-cycles:G + cpu\-cycles:uH  Total number of cycles  1cycles    000lpm_cycles_user lpm_cycles d_ratio(cpu\-cycles:uH, cpu\-cycles:kHh + cpu\-cycles:G + cpu\-cycles:uH)  User cycles as a percentage of all cycles  100%    000lpm_fpu_128_double_flops lpm_fpu;lpm_fpu_128;lpm_fpu_128_double d_ratio(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE * 2, duration_time)  128-bit packed double floating point operations per second  1flops/s    000lpm_fpu_128_double_of_total lpm_fpu;lpm_fpu_128;lpm_fpu_128_double d_ratio(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE * 2, FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 4 * FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + 4 * FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE)  128-bit packed double floating point operations per second  100%    000lpm_fpu_128_double_ops lpm_fpu;lpm_fpu_128;lpm_fpu_128_double d_ratio(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE, duration_time)  128-bit packed double operations per second  1ops/s    000lpm_fpu_128_single_flops lpm_fpu;lpm_fpu_128;lpm_fpu_128_single d_ratio(FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE * 4, duration_time)  128-bit packed single floating point operations per second  1flops/s    000lpm_fpu_128_single_of_total lpm_fpu;lpm_fpu_128;lpm_fpu_128_single d_ratio(FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE * 4, FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 4 * FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + 4 * FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE)  128-bit packed single floating point operations per second  100%    000lpm_fpu_128_single_ops lpm_fpu;lpm_fpu_128;lpm_fpu_128_single d_ratio(FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE, duration_time)  128-bit packed single operations per second  1ops/s    000lpm_fpu_256_double_flops lpm_fpu;lpm_fpu_256;lpm_fpu_256_double d_ratio(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE * 4, duration_time)  128-bit packed double floating point operations per second  1flops/s    000lpm_fpu_256_double_of_total lpm_fpu;lpm_fpu_256;lpm_fpu_256_double d_ratio(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE * 4, FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 4 * FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + 4 * FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE)  128-bit packed double floating point operations per second  100%    000lpm_fpu_256_double_ops lpm_fpu;lpm_fpu_256;lpm_fpu_256_double d_ratio(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE, duration_time)  128-bit packed double operations per second  1ops/s    000lpm_fpu_256_single_flops lpm_fpu;lpm_fpu_256;lpm_fpu_256_single d_ratio(FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE * 8, duration_time)  128-bit packed single floating point operations per second  1flops/s    000lpm_fpu_256_single_of_total lpm_fpu;lpm_fpu_256;lpm_fpu_256_single d_ratio(FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE * 8, FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 4 * FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + 4 * FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE)  128-bit packed single floating point operations per second  100%    000lpm_fpu_256_single_ops lpm_fpu;lpm_fpu_256;lpm_fpu_256_single d_ratio(FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE, duration_time)  128-bit packed single operations per second  1ops/s    000lpm_fpu_64_double_flops lpm_fpu;lpm_fpu_64;lpm_fpu_64_double d_ratio(FP_ARITH_INST_RETIRED.SCALAR_DOUBLE, duration_time)  64-bit double floating point operations per second  1flops/s    000lpm_fpu_64_double_of_total lpm_fpu;lpm_fpu_64;lpm_fpu_64_double d_ratio(FP_ARITH_INST_RETIRED.SCALAR_DOUBLE, FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 4 * FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + 4 * FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE)  64-bit double floating point operations per second  100%    000lpm_fpu_64_double_ops lpm_fpu;lpm_fpu_64;lpm_fpu_64_double d_ratio(FP_ARITH_INST_RETIRED.SCALAR_DOUBLE, duration_time)  64-bit double operations per second  1ops/s    000lpm_fpu_64_single_flops lpm_fpu;lpm_fpu_64;lpm_fpu_64_single d_ratio(FP_ARITH_INST_RETIRED.SCALAR_SINGLE, duration_time)  64-bit single floating point operations per second  1flops/s    000lpm_fpu_64_single_of_total lpm_fpu;lpm_fpu_64;lpm_fpu_64_single d_ratio(FP_ARITH_INST_RETIRED.SCALAR_SINGLE, FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 4 * FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + 4 * FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE)  64-bit single floating point operations per second  100%    000lpm_fpu_64_single_ops lpm_fpu;lpm_fpu_64;lpm_fpu_64_single d_ratio(FP_ARITH_INST_RETIRED.SCALAR_SINGLE, duration_time)  64-bit single operations per second  1ops/s    000lpm_fpu_assists lpm_fpu d_ratio(ASSISTS.FP, cycles)  FP assists as a percentage of cycles  100%    000lpm_fpu_total_flopc lpm_fpu;lpm_fpu_total d_ratio(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 4 * FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + 4 * FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE, cycles)  Floating point operations per cycle  1flops/cycle    020lpm_fpu_total_flops lpm_fpu;lpm_fpu_total d_ratio(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 4 * FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + 4 * FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE, duration_time)  Floating point operations per second  1flops/s    000lpm_idle  d_ratio(max(msr@tsc@ - msr@mperf@, 0), msr@tsc@)  Percentage of total wallclock cycles where CPUs are in low power state (C1 or deeper sleep state)  100%    000lpm_ilp_idle lpm_ilp d_ratio(msr@tsc@ - msr@mperf@, msr@tsc@)  Lower power cycles as a percentage of all cycles  100%    000lpm_ilp_inst_ret_0 lpm_ilp 1 - d_ratio(max(INST_RETIRED.ANY_P@cmask\=1@ - INST_RETIRED.ANY_P@cmask\=2@, 0), CPU_CLK_UNHALTED.DISTRIBUTED) - d_ratio(max(INST_RETIRED.ANY_P@cmask\=2@ - INST_RETIRED.ANY_P@cmask\=3@, 0), CPU_CLK_UNHALTED.DISTRIBUTED) - d_ratio(max(INST_RETIRED.ANY_P@cmask\=3@ - INST_RETIRED.ANY_P@cmask\=4@, 0), CPU_CLK_UNHALTED.DISTRIBUTED) - d_ratio(max(INST_RETIRED.ANY_P@cmask\=4@ - INST_RETIRED.ANY_P@cmask\=5@, 0), CPU_CLK_UNHALTED.DISTRIBUTED) - d_ratio(INST_RETIRED.ANY_P@cmask\=5@, CPU_CLK_UNHALTED.DISTRIBUTED)  Instructions retired in 0 cycles as a percentage of all cycles  100%    000lpm_ilp_inst_ret_1 lpm_ilp d_ratio(max(INST_RETIRED.ANY_P@cmask\=1@ - INST_RETIRED.ANY_P@cmask\=2@, 0), CPU_CLK_UNHALTED.DISTRIBUTED)  Instructions retired in 1 cycles as a percentage of all cycles  100%    000lpm_ilp_inst_ret_2 lpm_ilp d_ratio(max(INST_RETIRED.ANY_P@cmask\=2@ - INST_RETIRED.ANY_P@cmask\=3@, 0), CPU_CLK_UNHALTED.DISTRIBUTED)  Instructions retired in 2 cycles as a percentage of all cycles  100%    000lpm_ilp_inst_ret_3 lpm_ilp d_ratio(max(INST_RETIRED.ANY_P@cmask\=3@ - INST_RETIRED.ANY_P@cmask\=4@, 0), CPU_CLK_UNHALTED.DISTRIBUTED)  Instructions retired in 3 cycles as a percentage of all cycles  100%    000lpm_ilp_inst_ret_4 lpm_ilp d_ratio(max(INST_RETIRED.ANY_P@cmask\=4@ - INST_RETIRED.ANY_P@cmask\=5@, 0), CPU_CLK_UNHALTED.DISTRIBUTED)  Instructions retired in 4 cycles as a percentage of all cycles  100%    000lpm_ilp_inst_ret_5 lpm_ilp d_ratio(INST_RETIRED.ANY_P@cmask\=5@, CPU_CLK_UNHALTED.DISTRIBUTED)  Instructions retired in 5 or more cycles as a percentage of all cycles  100%    000lpm_l2_code_hits lpm_l2;lpm_l2_code d_ratio(L2_RQSTS.CODE_RD_HIT, L2_RQSTS.CODE_RD_HIT + L2_RQSTS.CODE_RD_MISS)  L2 cache code hits  100%    000lpm_l2_code_misses lpm_l2;lpm_l2_code d_ratio(L2_RQSTS.CODE_RD_MISS, duration_time)  L2 cache code misses per second  1misses/s    000lpm_l2_code_misses lpm_l2;lpm_l2_code d_ratio(L2_RQSTS.CODE_RD_MISS, L2_RQSTS.CODE_RD_HIT + L2_RQSTS.CODE_RD_MISS)  L2 cache code misses  100%    000lpm_l2_code_requests lpm_l2;lpm_l2_code d_ratio(L2_RQSTS.CODE_RD_HIT + L2_RQSTS.CODE_RD_MISS, duration_time)  L2 cache code requests per second  1requests/s    000lpm_l2_rd_hits lpm_l2;lpm_l2_rd d_ratio(L2_RQSTS.DEMAND_DATA_RD_MISS, L2_RQSTS.DEMAND_DATA_RD_MISS + L2_RQSTS.DEMAND_DATA_RD_HIT)  L2 cache data read hits  100%    000lpm_l2_rd_hits lpm_l2;lpm_l2_rd d_ratio(L2_RQSTS.DEMAND_DATA_RD_HIT, L2_RQSTS.DEMAND_DATA_RD_MISS + L2_RQSTS.DEMAND_DATA_RD_HIT)  L2 cache data read hits  100%    000lpm_l2_rd_misses lpm_l2;lpm_l2_rd d_ratio(L2_RQSTS.DEMAND_DATA_RD_MISS, duration_time)  L2 cache data read misses per second  1misses/s    000lpm_l2_rd_requests lpm_l2;lpm_l2_rd d_ratio(L2_RQSTS.DEMAND_DATA_RD_MISS + L2_RQSTS.DEMAND_DATA_RD_HIT, duration_time)  L2 cache data read requests per second  1requests/s    000lpm_l2_rfo_hits lpm_l2;lpm_l2_rfo d_ratio(L2_RQSTS.RFO_HIT, L2_RQSTS.RFO_HIT + L2_RQSTS.RFO_MISS)  L2 cache request for ownership (RFO) hits  100%    000lpm_l2_rfo_misses lpm_l2;lpm_l2_rfo d_ratio(L2_RQSTS.RFO_MISS, duration_time)  L2 cache request for ownership (RFO) misses per second  1misses/s    000lpm_l2_rfo_misses lpm_l2;lpm_l2_rfo d_ratio(L2_RQSTS.RFO_MISS, L2_RQSTS.RFO_HIT + L2_RQSTS.RFO_MISS)  L2 cache request for ownership (RFO) misses  100%    000lpm_l2_rfo_requests lpm_l2;lpm_l2_rfo d_ratio(L2_RQSTS.RFO_HIT + L2_RQSTS.RFO_MISS, duration_time)  L2 cache request for ownership (RFO) requests per second  1requests/s    000lpm_l2_totals_in lpm_l2;lpm_l2_totals d_ratio(L2_LINES_IN.ALL, duration_time)  L2 cache total in per second  1In/s    000lpm_ldst_atomic_lds lpm_ldst d_ratio(MEM_INST_RETIRED.LOCK_LOADS, duration_time)  Atomic loads per second  1loads/s    000lpm_ldst_ld_hit_swpf lpm_ldst d_ratio(LOAD_HIT_PREFETCH.SWPF, duration_time)  Load hit software prefetches per second  1swpf/s    000lpm_ldst_prcnt_loads lpm_ldst;lpm_ldst_prcnt d_ratio(MEM_INST_RETIRED.ALL_LOADS, instructions)  Percent of all instructions that are loads  100%    000lpm_ldst_prcnt_stores lpm_ldst;lpm_ldst_prcnt d_ratio(MEM_INST_RETIRED.ALL_STORES, instructions)  Percent of all instructions that are stores  100%    000lpm_ldst_ret_lds_1 lpm_ldst;lpm_ldst_ret_lds d_ratio(max(MEM_INST_RETIRED.ALL_LOADS@cmask\=1@ - MEM_INST_RETIRED.ALL_LOADS@cmask\=2@, 0), CPU_CLK_UNHALTED.THREAD)  Retired loads in 1 cycle  100%    000lpm_ldst_ret_lds_2 lpm_ldst;lpm_ldst_ret_lds d_ratio(max(MEM_INST_RETIRED.ALL_LOADS@cmask\=2@ - MEM_INST_RETIRED.ALL_LOADS@cmask\=3@, 0), CPU_CLK_UNHALTED.THREAD)  Retired loads in 2 cycles  100%    000lpm_ldst_ret_lds_3 lpm_ldst;lpm_ldst_ret_lds d_ratio(MEM_INST_RETIRED.ALL_LOADS@cmask\=3@, CPU_CLK_UNHALTED.THREAD)  Retired loads in 3 or more cycles  100%    000lpm_ldst_ret_sts_1 lpm_ldst;lpm_ldst_ret_sts d_ratio(max(MEM_INST_RETIRED.ALL_STORES@cmask\=1@ - MEM_INST_RETIRED.ALL_STORES@cmask\=2@, 0), CPU_CLK_UNHALTED.THREAD)  Retired stores in 1 cycle  100%    000lpm_ldst_ret_sts_2 lpm_ldst;lpm_ldst_ret_sts d_ratio(max(MEM_INST_RETIRED.ALL_STORES@cmask\=2@ - MEM_INST_RETIRED.ALL_STORES@cmask\=3@, 0), CPU_CLK_UNHALTED.THREAD)  Retired stores in 2 cycles  100%    000lpm_ldst_ret_sts_3 lpm_ldst;lpm_ldst_ret_sts d_ratio(MEM_INST_RETIRED.ALL_STORES@cmask\=3@, CPU_CLK_UNHALTED.THREAD)  Retired stores in 3 more cycles  100%    000lpm_ldst_total_loads lpm_ldst;lpm_ldst_total d_ratio(MEM_INST_RETIRED.ALL_LOADS, duration_time)  Load/store instructions total loads  1loads    000lpm_ldst_total_stores lpm_ldst;lpm_ldst_total d_ratio(MEM_INST_RETIRED.ALL_STORES, duration_time)  Load/store instructions total stores  1stores    000lpm_mlp  d_ratio(L1D_PEND_MISS.PENDING, (L1D_PEND_MISS.PENDING_CYCLES / 2 if #smt_on else L1D_PEND_MISS.PENDING_CYCLES))  Miss level parallelism - number of outstanding load misses per cycle (higher is better)  1load_miss_pending/cycle    000lpm_port_0 lpm_ports d_ratio(UOPS_DISPATCHED.PORT_0, (CPU_CLK_UNHALTED.DISTRIBUTED / 2 if #smt_on else CPU_CLK_UNHALTED.DISTRIBUTED))  port_0 utilization (higher is better)  100%    000lpm_port_1 lpm_ports d_ratio(UOPS_DISPATCHED.PORT_1, (CPU_CLK_UNHALTED.DISTRIBUTED / 2 if #smt_on else CPU_CLK_UNHALTED.DISTRIBUTED))  port_1 utilization (higher is better)  100%    000lpm_port_2_3_10 lpm_ports d_ratio(UOPS_DISPATCHED.PORT_2_3_10, (CPU_CLK_UNHALTED.DISTRIBUTED / 2 if #smt_on else CPU_CLK_UNHALTED.DISTRIBUTED))  port_2_3_10 utilization (higher is better)  100%    000lpm_port_4_9 lpm_ports d_ratio(UOPS_DISPATCHED.PORT_4_9, (CPU_CLK_UNHALTED.DISTRIBUTED / 2 if #smt_on else CPU_CLK_UNHALTED.DISTRIBUTED))  port_4_9 utilization (higher is better)  100%    000lpm_port_5_11 lpm_ports d_ratio(UOPS_DISPATCHED.PORT_5_11, (CPU_CLK_UNHALTED.DISTRIBUTED / 2 if #smt_on else CPU_CLK_UNHALTED.DISTRIBUTED))  port_5_11 utilization (higher is better)  100%    000lpm_port_6 lpm_ports d_ratio(UOPS_DISPATCHED.PORT_6, (CPU_CLK_UNHALTED.DISTRIBUTED / 2 if #smt_on else CPU_CLK_UNHALTED.DISTRIBUTED))  port_6 utilization (higher is better)  100%    000lpm_port_7_8 lpm_ports d_ratio(UOPS_DISPATCHED.PORT_7_8, (CPU_CLK_UNHALTED.DISTRIBUTED / 2 if #smt_on else CPU_CLK_UNHALTED.DISTRIBUTED))  port_7_8 utilization (higher is better)  100%    000lpm_swpf_bkdwn_nta_per_swpf lpm_swpf;lpm_swpf_bkdwn;lpm_swpf_bkdwn_nta d_ratio(SW_PREFETCH_ACCESS.NTA, SW_PREFETCH_ACCESS.NTA + SW_PREFETCH_ACCESS.T0 + SW_PREFETCH_ACCESS.T1_T2 + SW_PREFETCH_ACCESS.PREFETCHW)  Software prefetch NTA instructions as a percent of all prefetch instructions  100%    000lpm_swpf_bkdwn_nta_rate lpm_swpf;lpm_swpf_bkdwn;lpm_swpf_bkdwn_nta d_ratio(SW_PREFETCH_ACCESS.NTA, duration_time)  Software prefetch NTA instructions per second  1insn/s    000lpm_swpf_bkdwn_t0_per_swpf lpm_swpf;lpm_swpf_bkdwn;lpm_swpf_bkdwn_t0 d_ratio(SW_PREFETCH_ACCESS.T0, SW_PREFETCH_ACCESS.NTA + SW_PREFETCH_ACCESS.T0 + SW_PREFETCH_ACCESS.T1_T2 + SW_PREFETCH_ACCESS.PREFETCHW)  Software prefetch T0 instructions as a percent of all prefetch instructions  100%    000lpm_swpf_bkdwn_t0_rate lpm_swpf;lpm_swpf_bkdwn;lpm_swpf_bkdwn_t0 d_ratio(SW_PREFETCH_ACCESS.T0, duration_time)  Software prefetch T0 instructions per second  1insn/s    000lpm_swpf_bkdwn_t1_t2_per_swpf lpm_swpf;lpm_swpf_bkdwn;lpm_swpf_bkdwn_t1_t2 d_ratio(SW_PREFETCH_ACCESS.T1_T2, SW_PREFETCH_ACCESS.NTA + SW_PREFETCH_ACCESS.T0 + SW_PREFETCH_ACCESS.T1_T2 + SW_PREFETCH_ACCESS.PREFETCHW)  Software prefetch T1 or T2 instructions as a percent of all prefetch instructions  100%    000lpm_swpf_bkdwn_t1_t2_rate lpm_swpf;lpm_swpf_bkdwn;lpm_swpf_bkdwn_t1_t2 d_ratio(SW_PREFETCH_ACCESS.T1_T2, duration_time)  Software prefetch T1 or T2 instructions per second  1insn/s    000lpm_swpf_bkdwn_w_per_swpf lpm_swpf;lpm_swpf_bkdwn;lpm_swpf_bkdwn_w d_ratio(SW_PREFETCH_ACCESS.PREFETCHW, SW_PREFETCH_ACCESS.NTA + SW_PREFETCH_ACCESS.T0 + SW_PREFETCH_ACCESS.T1_T2 + SW_PREFETCH_ACCESS.PREFETCHW)  Software prefetch W instructions as a percent of all prefetch instructions  100%    000lpm_swpf_bkdwn_w_rate lpm_swpf;lpm_swpf_bkdwn;lpm_swpf_bkdwn_w d_ratio(SW_PREFETCH_ACCESS.PREFETCHW, duration_time)  Software prefetch W instructions per second  1insn/s    000lpm_swpf_totals_exec lpm_swpf;lpm_swpf_totals d_ratio(SW_PREFETCH_ACCESS.NTA + SW_PREFETCH_ACCESS.T0 + SW_PREFETCH_ACCESS.T1_T2 + SW_PREFETCH_ACCESS.PREFETCHW, duration_time)  Software prefetch instructions per second  1swpf/s    000lpm_swpf_totals_insn_per_pf lpm_swpf;lpm_swpf_totals d_ratio(instructions, SW_PREFETCH_ACCESS.NTA + SW_PREFETCH_ACCESS.T0 + SW_PREFETCH_ACCESS.T1_T2 + SW_PREFETCH_ACCESS.PREFETCHW)  Average number of instructions between software prefetches  1insn/swpf    000lpm_swpf_totals_loads_per_pf lpm_swpf;lpm_swpf_totals d_ratio(MEM_INST_RETIRED.ALL_LOADS, SW_PREFETCH_ACCESS.NTA + SW_PREFETCH_ACCESS.T0 + SW_PREFETCH_ACCESS.T1_T2 + SW_PREFETCH_ACCESS.PREFETCHW)  Average number of loads between software prefetches  1loads/swpf    000smi_cycles smi (((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0) if has_event(msr@aperf@) else 0) smi_cycles > 0.1 Percentage of cycles spent in System Management Interrupts. Requires /sys/bus/event_source/devices/<cpu_core or cpu_atom>/freeze_on_smi to be 1  100%    000smi_num smi (msr@smi@ if has_event(msr@smi@) else 0)  Number of SMI interrupts  1SMI#    000Backend Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet Bad BadSpec BigFootprint BrMispredicts Branches BvBC BvBO BvCB BvFB BvIO BvMB BvML BvMP BvMS BvMT BvOB BvUW C0Wait CacheHits CacheMisses CodeGen Compute Cor DSB DSBmiss DataSharing Fed FetchBW FetchLat Flops FpScalar FpVector Frontend HPC IcMiss Ifetch InsType IntVector L2Evicts Load_Store_Miss LockCont MachineClears Machine_Clears Mem MemOffcore Mem_Exec MemoryBW MemoryBound MemoryLat MemoryTLB Memory_BW Memory_Lat MicroSeq OS PGO Pipeline PortsUtil Power Ret Retire SMT Server Snoop SoC Summary TmaL1 TmaL2 TmaL3mem TopdownL1 Metrics for top-down breakdown at level 1 TopdownL2 Metrics for top-down breakdown at level 2 TopdownL3 Metrics for top-down breakdown at level 3 TopdownL4 Metrics for top-down breakdown at level 4 TopdownL5 Metrics for top-down breakdown at level 5 TopdownL6 Metrics for top-down breakdown at level 6 load_store_bound tma_L1_group tma_L2_group tma_L3_group tma_L4_group tma_L5_group tma_L6_group tma_alu_op_utilization_group Metrics contributing to tma_alu_op_utilization category tma_assists_group Metrics contributing to tma_assists category tma_backend_bound_group Metrics contributing to tma_backend_bound category tma_bad_speculation_group Metrics contributing to tma_bad_speculation category tma_branch_mispredicts_group Metrics contributing to tma_branch_mispredicts category tma_branch_resteers_group Metrics contributing to tma_branch_resteers category tma_code_stlb_miss_group Metrics contributing to tma_code_stlb_miss category tma_core_bound_group Metrics contributing to tma_core_bound category tma_divider_group Metrics contributing to tma_divider category tma_dram_bound_group Metrics contributing to tma_dram_bound category tma_dtlb_load_group Metrics contributing to tma_dtlb_load category tma_dtlb_store_group Metrics contributing to tma_dtlb_store category tma_fetch_bandwidth_group Metrics contributing to tma_fetch_bandwidth category tma_fetch_latency_group Metrics contributing to tma_fetch_latency category tma_fp_arith_group Metrics contributing to tma_fp_arith category tma_fp_vector_group Metrics contributing to tma_fp_vector category tma_frontend_bound_group Metrics contributing to tma_frontend_bound category tma_heavy_operations_group Metrics contributing to tma_heavy_operations category tma_icache_misses_group Metrics contributing to tma_icache_misses category tma_ifetch_bandwidth_group Metrics contributing to tma_ifetch_bandwidth category tma_ifetch_latency_group Metrics contributing to tma_ifetch_latency category tma_int_operations_group Metrics contributing to tma_int_operations category tma_issue2P Metrics related by the issue $issue2P tma_issueBM Metrics related by the issue $issueBM tma_issueBW Metrics related by the issue $issueBW tma_issueComp Metrics related by the issue $issueComp tma_issueD0 Metrics related by the issue $issueD0 tma_issueFB Metrics related by the issue $issueFB tma_issueFL Metrics related by the issue $issueFL tma_issueL1 Metrics related by the issue $issueL1 tma_issueLat Metrics related by the issue $issueLat tma_issueMC Metrics related by the issue $issueMC tma_issueMS Metrics related by the issue $issueMS tma_issueMV Metrics related by the issue $issueMV tma_issueRFO Metrics related by the issue $issueRFO tma_issueSL Metrics related by the issue $issueSL tma_issueSO Metrics related by the issue $issueSO tma_issueSmSt Metrics related by the issue $issueSmSt tma_issueSpSt Metrics related by the issue $issueSpSt tma_issueSyncxn Metrics related by the issue $issueSyncxn tma_issueTLB Metrics related by the issue $issueTLB tma_itlb_misses_group Metrics contributing to tma_itlb_misses category tma_l1_bound_group Metrics contributing to tma_l1_bound category tma_l2_bound_group Metrics contributing to tma_l2_bound category tma_l3_bound_group Metrics contributing to tma_l3_bound category tma_light_operations_group Metrics contributing to tma_light_operations category tma_load_op_utilization_group Metrics contributing to tma_load_op_utilization category tma_load_stlb_miss_group Metrics contributing to tma_load_stlb_miss category tma_machine_clears_group Metrics contributing to tma_machine_clears category tma_mem_latency_group Metrics contributing to tma_mem_latency category tma_memory_bound_group Metrics contributing to tma_memory_bound category tma_microcode_sequencer_group Metrics contributing to tma_microcode_sequencer category tma_mite_group Metrics contributing to tma_mite category tma_other_light_ops_group Metrics contributing to tma_other_light_ops category tma_ports_utilization_group Metrics contributing to tma_ports_utilization category tma_ports_utilized_0_group Metrics contributing to tma_ports_utilized_0 category tma_ports_utilized_3m_group Metrics contributing to tma_ports_utilized_3m category tma_resource_bound_group Metrics contributing to tma_resource_bound category tma_retiring_group Metrics contributing to tma_retiring category tma_serializing_operation_group Metrics contributing to tma_serializing_operation category tma_store_bound_group Metrics contributing to tma_store_bound category tma_store_op_utilization_group Metrics contributing to tma_store_op_utilization category tma_store_stlb_miss_group Metrics contributing to tma_store_stlb_miss category tma_backend_bound Default;TopdownL1;tma_L1_group TOPDOWN_BE_BOUND.ALL / (5 * CPU_CLK_UNHALTED.CORE) tma_backend_bound > 0.1 Counts the total number of issue slots that were not consumed by the backend due to backend stalls Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count 100%  TopdownL1;Default TopdownL1 000tma_bad_speculation Default;TopdownL1;tma_L1_group (5 * CPU_CLK_UNHALTED.CORE - (TOPDOWN_FE_BOUND.ALL + TOPDOWN_BE_BOUND.ALL + TOPDOWN_RETIRING.ALL)) / (5 * CPU_CLK_UNHALTED.CORE) tma_bad_speculation > 0.15 Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear 100%  TopdownL1;Default TopdownL1 000tma_branch_detect TopdownL3;tma_L3_group;tma_ifetch_latency_group TOPDOWN_FE_BOUND.BRANCH_DETECT / (5 * CPU_CLK_UNHALTED.CORE) tma_branch_detect > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches 100%    000tma_branch_mispredicts TopdownL2;tma_L2_group;tma_bad_speculation_group TOPDOWN_BAD_SPECULATION.MISPREDICT / (5 * CPU_CLK_UNHALTED.CORE) tma_branch_mispredicts > 0.05 & tma_bad_speculation > 0.15 Counts the number of issue slots that were not consumed by the backend due to branch mispredicts  100%  TopdownL2  000tma_branch_resteer TopdownL3;tma_L3_group;tma_ifetch_latency_group TOPDOWN_FE_BOUND.BRANCH_RESTEER / (5 * CPU_CLK_UNHALTED.CORE) tma_branch_resteer > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch  100%    000tma_cisc TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group TOPDOWN_FE_BOUND.CISC / (5 * CPU_CLK_UNHALTED.CORE) tma_cisc > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to the microcode sequencer (MS)  100%    000tma_core_bound TopdownL2;tma_L2_group;tma_backend_bound_group TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS / (5 * CPU_CLK_UNHALTED.CORE) tma_core_bound > 0.1 & tma_backend_bound > 0.1 Counts the number of cycles due to backend bound stalls that are bounded by core restrictions and not attributed to an outstanding load or stores, or resource limitation  100%  TopdownL2  000tma_decode TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group TOPDOWN_FE_BOUND.DECODE / (5 * CPU_CLK_UNHALTED.CORE) tma_decode > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to decode stalls  100%    000tma_fast_nuke TopdownL3;tma_L3_group;tma_machine_clears_group TOPDOWN_BAD_SPECULATION.FASTNUKE / (5 * CPU_CLK_UNHALTED.CORE) tma_fast_nuke > 0.05 & (tma_machine_clears > 0.05 & tma_bad_speculation > 0.15) Counts the number of issue slots that were not consumed by the backend due to a machine clear that does not require the use of microcode, classified as a fast nuke, due to memory ordering, memory disambiguation and memory renaming  100%    000tma_frontend_bound Default;TopdownL1;tma_L1_group TOPDOWN_FE_BOUND.ALL / (5 * CPU_CLK_UNHALTED.CORE) tma_frontend_bound > 0.2 Counts the number of issue slots that were not consumed by the backend due to frontend stalls  100%  TopdownL1;Default TopdownL1 000tma_icache_misses TopdownL3;tma_L3_group;tma_ifetch_latency_group TOPDOWN_FE_BOUND.ICACHE / (5 * CPU_CLK_UNHALTED.CORE) tma_icache_misses > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to instruction cache misses  100%    000tma_ifetch_bandwidth TopdownL2;tma_L2_group;tma_frontend_bound_group TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH / (5 * CPU_CLK_UNHALTED.CORE) tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2 Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations  100%  TopdownL2  000tma_ifetch_latency TopdownL2;tma_L2_group;tma_frontend_bound_group TOPDOWN_FE_BOUND.FRONTEND_LATENCY / (5 * CPU_CLK_UNHALTED.CORE) tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2 Counts the number of issue slots that were not delivered by the frontend due to frontend latency restrictions due to icache misses, itlb misses, branch detection, and resteer limitations  100%  TopdownL2  000tma_info_bottleneck_%_dtlb_miss_bound_cycles  100 * (LD_HEAD.DTLB_MISS_AT_RET + LD_HEAD.PGWALK_AT_RET) / CPU_CLK_UNHALTED.CORE  Percentage of time that retirement is stalled due to a first level data TLB miss      000tma_info_bottleneck_%_ifetch_miss_bound_cycles Ifetch 100 * MEM_BOUND_STALLS.IFETCH / CPU_CLK_UNHALTED.CORE  Percentage of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icache or ITLB Miss Percentage of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icache or ITLB Miss. See Info.Ifetch_Bound     000tma_info_bottleneck_%_load_miss_bound_cycles Load_Store_Miss 100 * MEM_BOUND_STALLS.LOAD / CPU_CLK_UNHALTED.CORE  Percentage of time that retirement is stalled due to an L1 miss Percentage of time that retirement is stalled due to an L1 miss. See Info.Load_Miss_Bound     000tma_info_bottleneck_%_mem_exec_bound_cycles Mem_Exec 100 * LD_HEAD.ANY_AT_RET / CPU_CLK_UNHALTED.CORE  Percentage of time that retirement is stalled by the Memory Cluster due to a pipeline stall Percentage of time that retirement is stalled by the Memory Cluster due to a pipeline stall. See Info.Mem_Exec_Bound     000tma_info_br_inst_mix_ipbranch  INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES  Instructions per Branch (lower number means higher occurrence rate)      000tma_info_br_inst_mix_ipcall  INST_RETIRED.ANY / BR_INST_RETIRED.CALL  Instruction per (near) call (lower number means higher occurrence rate)      000tma_info_br_inst_mix_ipfarbranch  INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u  Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]      000tma_info_br_inst_mix_ipmisp_cond_ntaken  INST_RETIRED.ANY / (BR_MISP_RETIRED.COND - BR_MISP_RETIRED.COND_TAKEN)  Instructions per retired conditional Branch Misprediction where the branch was not taken      000tma_info_br_inst_mix_ipmisp_cond_taken  INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN  Instructions per retired conditional Branch Misprediction where the branch was taken      000tma_info_br_inst_mix_ipmisp_indirect  INST_RETIRED.ANY / BR_MISP_RETIRED.INDIRECT  Instructions per retired indirect call or jump Branch Misprediction      000tma_info_br_inst_mix_ipmisp_ret  INST_RETIRED.ANY / BR_MISP_RETIRED.RETURN  Instructions per retired return Branch Misprediction      000tma_info_br_inst_mix_ipmispredict  INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES  Instructions per retired Branch Misprediction      000tma_info_br_mispredict_bound_branch_mispredict_ratio  BR_MISP_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.ALL_BRANCHES  Ratio of all branches which mispredict      000tma_info_br_mispredict_bound_branch_mispredict_to_unknown_branch_ratio  BR_MISP_RETIRED.ALL_BRANCHES / BACLEARS.ANY  Ratio between Mispredicted branches and unknown branches      000tma_info_buffer_stalls_%_load_buffer_stall_cycles  100 * MEM_SCHEDULER_BLOCK.LD_BUF / CPU_CLK_UNHALTED.CORE  Percentage of time that allocation is stalled due to load buffer full      000tma_info_buffer_stalls_%_mem_rsv_stall_cycles  100 * MEM_SCHEDULER_BLOCK.RSV / CPU_CLK_UNHALTED.CORE  Percentage of time that allocation is stalled due to memory reservation stations full      000tma_info_buffer_stalls_%_store_buffer_stall_cycles  100 * MEM_SCHEDULER_BLOCK.ST_BUF / CPU_CLK_UNHALTED.CORE  Percentage of time that allocation is stalled due to store buffer full      000tma_info_core_cpi  CPU_CLK_UNHALTED.CORE / INST_RETIRED.ANY  Cycles Per Instruction      000tma_info_core_ipc  INST_RETIRED.ANY / CPU_CLK_UNHALTED.CORE  Instructions Per Cycle      000tma_info_core_upi  UOPS_RETIRED.ALL / INST_RETIRED.ANY  Uops Per Instruction      000tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l2hit  100 * MEM_BOUND_STALLS.IFETCH_L2_HIT / MEM_BOUND_STALLS.IFETCH  Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L2      000tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l2miss  100 * (MEM_BOUND_STALLS.IFETCH_LLC_HIT + MEM_BOUND_STALLS.IFETCH_DRAM_HIT) / MEM_BOUND_STALLS.IFETCH  Percentage of ifetch miss bound stalls, where the ifetch miss doesn't hit in the L2      000tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l3hit  100 * MEM_BOUND_STALLS.IFETCH_LLC_HIT / MEM_BOUND_STALLS.IFETCH  Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L3      000tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l3miss  100 * MEM_BOUND_STALLS.IFETCH_DRAM_HIT / MEM_BOUND_STALLS.IFETCH  Percentage of ifetch miss bound stalls, where the ifetch miss subsequently misses in the L3      000tma_info_load_miss_bound_%_loadmissbound_with_l2hit load_store_bound 100 * MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_STALLS.LOAD  Percentage of memory bound stalls where retirement is stalled due to an L1 miss that hit the L2      000tma_info_load_miss_bound_%_loadmissbound_with_l2miss load_store_bound 100 * (MEM_BOUND_STALLS.LOAD_LLC_HIT + MEM_BOUND_STALLS.LOAD_DRAM_HIT) / MEM_BOUND_STALLS.LOAD  Percentage of memory bound stalls where retirement is stalled due to an L1 miss that subsequently misses in the L2      000tma_info_load_miss_bound_%_loadmissbound_with_l3hit load_store_bound 100 * MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND_STALLS.LOAD  Percentage of memory bound stalls where retirement is stalled due to an L1 miss that hit the L3      000tma_info_load_miss_bound_%_loadmissbound_with_l3miss load_store_bound 100 * MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOUND_STALLS.LOAD  Percentage of memory bound stalls where retirement is stalled due to an L1 miss that subsequently misses the L3      000tma_info_load_store_bound_l1_bound load_store_bound 100 * LD_HEAD.L1_BOUND_AT_RET / CPU_CLK_UNHALTED.CORE  Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a pipeline block      000tma_info_load_store_bound_load_bound load_store_bound 100 * (LD_HEAD.L1_BOUND_AT_RET + MEM_BOUND_STALLS.LOAD) / CPU_CLK_UNHALTED.CORE  Counts the number of cycles that the oldest load of the load buffer is stalled at retirement      000tma_info_load_store_bound_store_bound load_store_bound 100 * (MEM_SCHEDULER_BLOCK.ST_BUF / MEM_SCHEDULER_BLOCK.ALL) * tma_mem_scheduler  Counts the number of cycles the core is stalled due to store buffer full      000tma_info_machine_clear_bound_machine_clears_disamb_pki  1e3 * MACHINE_CLEARS.DISAMBIGUATION / INST_RETIRED.ANY  Counts the number of machine clears relative to thousands of instructions retired, due to memory disambiguation      000tma_info_machine_clear_bound_machine_clears_fp_assist_pki  1e3 * MACHINE_CLEARS.FP_ASSIST / INST_RETIRED.ANY  Counts the number of machine clears relative to thousands of instructions retired, due to floating point assists      000tma_info_machine_clear_bound_machine_clears_monuke_pki  1e3 * MACHINE_CLEARS.MEMORY_ORDERING / INST_RETIRED.ANY  Counts the number of machine clears relative to thousands of instructions retired, due to memory ordering      000tma_info_machine_clear_bound_machine_clears_mrn_pki  1e3 * MACHINE_CLEARS.MRN_NUKE / INST_RETIRED.ANY  Counts the number of machine clears relative to thousands of instructions retired, due to memory renaming      000tma_info_machine_clear_bound_machine_clears_page_fault_pki  1e3 * MACHINE_CLEARS.PAGE_FAULT / INST_RETIRED.ANY  Counts the number of machine clears relative to thousands of instructions retired, due to page faults      000tma_info_machine_clear_bound_machine_clears_smc_pki  1e3 * MACHINE_CLEARS.SMC / INST_RETIRED.ANY  Counts the number of machine clears relative to thousands of instructions retired, due to self-modifying code      000tma_info_mem_exec_blocks_%_loads_with_adressaliasing  100 * LD_BLOCKS.4K_ALIAS / MEM_UOPS_RETIRED.ALL_LOADS  Percentage of total non-speculative loads with an address aliasing block      000tma_info_mem_exec_blocks_%_loads_with_storefwdblk  100 * LD_BLOCKS.DATA_UNKNOWN / MEM_UOPS_RETIRED.ALL_LOADS  Percentage of total non-speculative loads with a store forward or unknown store address block      000tma_info_mem_exec_bound_%_loadhead_with_l1miss  100 * LD_HEAD.L1_MISS_AT_RET / LD_HEAD.ANY_AT_RET  Percentage of Memory Execution Bound due to a first level data cache miss      000tma_info_mem_exec_bound_%_loadhead_with_otherpipelineblks  100 * LD_HEAD.OTHER_AT_RET / LD_HEAD.ANY_AT_RET  Percentage of Memory Execution Bound due to other block cases, such as pipeline conflicts, fences, etc      000tma_info_mem_exec_bound_%_loadhead_with_pagewalk  100 * LD_HEAD.PGWALK_AT_RET / LD_HEAD.ANY_AT_RET  Percentage of Memory Execution Bound due to a pagewalk      000tma_info_mem_exec_bound_%_loadhead_with_stlbhit  100 * LD_HEAD.DTLB_MISS_AT_RET / LD_HEAD.ANY_AT_RET  Percentage of Memory Execution Bound due to a second level TLB miss      000tma_info_mem_exec_bound_%_loadhead_with_storefwding  100 * LD_HEAD.ST_ADDR_AT_RET / LD_HEAD.ANY_AT_RET  Percentage of Memory Execution Bound due to a store forward address match      000tma_info_mem_mix_ipload  INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS  Instructions per Load      000tma_info_mem_mix_ipstore  INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES  Instructions per Store      000tma_info_mem_mix_load_locks_ratio  100 * MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_LOADS  Percentage of total non-speculative loads that perform one or more locks      000tma_info_mem_mix_load_splits_ratio  100 * MEM_UOPS_RETIRED.SPLIT_LOADS / MEM_UOPS_RETIRED.ALL_LOADS  Percentage of total non-speculative loads that are splits      000tma_info_mem_mix_memload_ratio  1e3 * MEM_UOPS_RETIRED.ALL_LOADS / UOPS_RETIRED.ALL  Ratio of mem load uops to all uops      000tma_info_serialization_%_tpause_cycles  100 * SERIALIZATION.C01_MS_SCB / (5 * CPU_CLK_UNHALTED.CORE)  Percentage of time that the core is stalled due to a TPAUSE or UMWAIT instruction      000tma_info_system_cpu_utilization  CPU_CLK_UNHALTED.REF_TSC / msr@tsc@  Average CPU Utilization      000tma_info_system_kernel_utilization Summary CPU_CLK_UNHALTED.CORE_P:k / CPU_CLK_UNHALTED.CORE  Fraction of cycles spent in Kernel mode      000tma_info_system_mux  CPU_CLK_UNHALTED.CORE_P / CPU_CLK_UNHALTED.CORE tma_info_system_mux > 1.1 | tma_info_system_mux < 0.9 PerfMon Event Multiplexing accuracy indicator      000tma_info_system_turbo_utilization Power CPU_CLK_UNHALTED.CORE / CPU_CLK_UNHALTED.REF_TSC  Average Frequency Utilization relative nominal frequency      000tma_info_uop_mix_fpdiv_uop_ratio  100 * UOPS_RETIRED.FPDIV / UOPS_RETIRED.ALL  Percentage of all uops which are FPDiv uops      000tma_info_uop_mix_idiv_uop_ratio  100 * UOPS_RETIRED.IDIV / UOPS_RETIRED.ALL  Percentage of all uops which are IDiv uops      000tma_info_uop_mix_microcode_uop_ratio  100 * UOPS_RETIRED.MS / UOPS_RETIRED.ALL  Percentage of all uops which are microcode ops      000tma_info_uop_mix_x87_uop_ratio  100 * UOPS_RETIRED.X87 / UOPS_RETIRED.ALL  Percentage of all uops which are x87 uops      000tma_itlb_misses TopdownL3;tma_L3_group;tma_ifetch_latency_group TOPDOWN_FE_BOUND.ITLB / (5 * CPU_CLK_UNHALTED.CORE) tma_itlb_misses > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses  100%    000tma_machine_clears TopdownL2;tma_L2_group;tma_bad_speculation_group TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS / (5 * CPU_CLK_UNHALTED.CORE) tma_machine_clears > 0.05 & tma_bad_speculation > 0.15 Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation  100%  TopdownL2  000tma_mem_scheduler TopdownL3;tma_L3_group;tma_resource_bound_group TOPDOWN_BE_BOUND.MEM_SCHEDULER / (5 * CPU_CLK_UNHALTED.CORE) tma_mem_scheduler > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops  100%    000tma_non_mem_scheduler TopdownL3;tma_L3_group;tma_resource_bound_group TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER / (5 * CPU_CLK_UNHALTED.CORE) tma_non_mem_scheduler > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops  100%    000tma_nuke TopdownL3;tma_L3_group;tma_machine_clears_group TOPDOWN_BAD_SPECULATION.NUKE / (5 * CPU_CLK_UNHALTED.CORE) tma_nuke > 0.05 & (tma_machine_clears > 0.05 & tma_bad_speculation > 0.15) Counts the number of issue slots that were not consumed by the backend due to a machine clear that requires the use of microcode (slow nuke)  100%    000tma_other_fb TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group TOPDOWN_FE_BOUND.OTHER / (5 * CPU_CLK_UNHALTED.CORE) tma_other_fb > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to other common frontend stalls not categorized  100%    000tma_predecode TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group TOPDOWN_FE_BOUND.PREDECODE / (5 * CPU_CLK_UNHALTED.CORE) tma_predecode > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to wrong predecodes  100%    000tma_register TopdownL3;tma_L3_group;tma_resource_bound_group TOPDOWN_BE_BOUND.REGISTER / (5 * CPU_CLK_UNHALTED.CORE) tma_register > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls)  100%    000tma_reorder_buffer TopdownL3;tma_L3_group;tma_resource_bound_group TOPDOWN_BE_BOUND.REORDER_BUFFER / (5 * CPU_CLK_UNHALTED.CORE) tma_reorder_buffer > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to the reorder buffer being full (ROB stalls)  100%    000tma_retiring Default;TopdownL1;tma_L1_group TOPDOWN_RETIRING.ALL / (5 * CPU_CLK_UNHALTED.CORE) tma_retiring > 0.75 Counts the number of issue slots that result in retirement slots  100%  TopdownL1;Default TopdownL1 000tma_serialization TopdownL3;tma_L3_group;tma_resource_bound_group TOPDOWN_BE_BOUND.SERIALIZATION / (5 * CPU_CLK_UNHALTED.CORE) tma_serialization > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS)  100%    000lpm_br_cond_insn_between_branches lpm_br;lpm_br_cond d_ratio(instructions, BR_INST_RETIRED.COND)  The number of instructions divided by the number of conditional branches  1insn    000lpm_br_cond_mispred lpm_br;lpm_br_cond d_ratio(BR_MISP_RETIRED.COND, BR_INST_RETIRED.COND)  Retired conditional branch instructions mispredicted as a percentage of all conditional branches  100%    000lpm_br_cond_retired lpm_br;lpm_br_cond d_ratio(BR_INST_RETIRED.COND, duration_time)  Retired conditional branch instructions  1insn/s    000lpm_cs_loads lpm_cs d_ratio(MEM_UOPS_RETIRED.ALL_LOADS, context\-switches)  Loads per context switch  1loads/cs    000lpm_cs_stores lpm_cs d_ratio(MEM_UOPS_RETIRED.ALL_STORES, context\-switches)  Stores per context switch  1stores/cs    000lpm_ilp_inst_ret_0 lpm_ilp 1 - d_ratio(max(INST_RETIRED.ANY_P@cmask\=1@ - INST_RETIRED.ANY_P@cmask\=2@, 0), cycles) - d_ratio(max(INST_RETIRED.ANY_P@cmask\=2@ - INST_RETIRED.ANY_P@cmask\=3@, 0), cycles) - d_ratio(max(INST_RETIRED.ANY_P@cmask\=3@ - INST_RETIRED.ANY_P@cmask\=4@, 0), cycles) - d_ratio(max(INST_RETIRED.ANY_P@cmask\=4@ - INST_RETIRED.ANY_P@cmask\=5@, 0), cycles) - d_ratio(INST_RETIRED.ANY_P@cmask\=5@, cycles)  Instructions retired in 0 cycles as a percentage of all cycles  100%    000lpm_ilp_inst_ret_1 lpm_ilp d_ratio(max(INST_RETIRED.ANY_P@cmask\=1@ - INST_RETIRED.ANY_P@cmask\=2@, 0), cycles)  Instructions retired in 1 cycles as a percentage of all cycles  100%    000lpm_ilp_inst_ret_2 lpm_ilp d_ratio(max(INST_RETIRED.ANY_P@cmask\=2@ - INST_RETIRED.ANY_P@cmask\=3@, 0), cycles)  Instructions retired in 2 cycles as a percentage of all cycles  100%    000lpm_ilp_inst_ret_3 lpm_ilp d_ratio(max(INST_RETIRED.ANY_P@cmask\=3@ - INST_RETIRED.ANY_P@cmask\=4@, 0), cycles)  Instructions retired in 3 cycles as a percentage of all cycles  100%    000lpm_ilp_inst_ret_4 lpm_ilp d_ratio(max(INST_RETIRED.ANY_P@cmask\=4@ - INST_RETIRED.ANY_P@cmask\=5@, 0), cycles)  Instructions retired in 4 cycles as a percentage of all cycles  100%    000lpm_ilp_inst_ret_5 lpm_ilp d_ratio(INST_RETIRED.ANY_P@cmask\=5@, cycles)  Instructions retired in 5 or more cycles as a percentage of all cycles  100%    000lpm_ldst_prcnt_loads lpm_ldst;lpm_ldst_prcnt d_ratio(MEM_UOPS_RETIRED.ALL_LOADS, instructions)  Percent of all instructions that are loads  100%    000lpm_ldst_prcnt_stores lpm_ldst;lpm_ldst_prcnt d_ratio(MEM_UOPS_RETIRED.ALL_STORES, instructions)  Percent of all instructions that are stores  100%    000lpm_ldst_ret_lds_1 lpm_ldst;lpm_ldst_ret_lds d_ratio(max(MEM_UOPS_RETIRED.ALL_LOADS@cmask\=1@ - MEM_UOPS_RETIRED.ALL_LOADS@cmask\=2@, 0), CPU_CLK_UNHALTED.THREAD)  Retired loads in 1 cycle  100%    020lpm_ldst_ret_lds_2 lpm_ldst;lpm_ldst_ret_lds d_ratio(max(MEM_UOPS_RETIRED.ALL_LOADS@cmask\=2@ - MEM_UOPS_RETIRED.ALL_LOADS@cmask\=3@, 0), CPU_CLK_UNHALTED.THREAD)  Retired loads in 2 cycles  100%    020lpm_ldst_ret_lds_3 lpm_ldst;lpm_ldst_ret_lds d_ratio(MEM_UOPS_RETIRED.ALL_LOADS@cmask\=3@, CPU_CLK_UNHALTED.THREAD)  Retired loads in 3 or more cycles  100%    000lpm_ldst_ret_sts_1 lpm_ldst;lpm_ldst_ret_sts d_ratio(max(MEM_UOPS_RETIRED.ALL_STORES@cmask\=1@ - MEM_UOPS_RETIRED.ALL_STORES@cmask\=2@, 0), CPU_CLK_UNHALTED.THREAD)  Retired stores in 1 cycle  100%    020lpm_ldst_ret_sts_2 lpm_ldst;lpm_ldst_ret_sts d_ratio(max(MEM_UOPS_RETIRED.ALL_STORES@cmask\=2@ - MEM_UOPS_RETIRED.ALL_STORES@cmask\=3@, 0), CPU_CLK_UNHALTED.THREAD)  Retired stores in 2 cycles  100%    020lpm_ldst_ret_sts_3 lpm_ldst;lpm_ldst_ret_sts d_ratio(MEM_UOPS_RETIRED.ALL_STORES@cmask\=3@, CPU_CLK_UNHALTED.THREAD)  Retired stores in 3 more cycles  100%    000lpm_ldst_total_loads lpm_ldst;lpm_ldst_total d_ratio(MEM_UOPS_RETIRED.ALL_LOADS, duration_time)  Load/store instructions total loads  1loads    000lpm_ldst_total_stores lpm_ldst;lpm_ldst_total d_ratio(MEM_UOPS_RETIRED.ALL_STORES, duration_time)  Load/store instructions total stores  1stores    000smi_cycles smi (((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0) if has_event(msr@aperf@) else 0) smi_cycles > 0.1 Percentage of cycles spent in System Management Interrupts. Requires /sys/bus/event_source/devices/cpu/freeze_on_smi to be 1  100%    000lpm_dtlb Data TLB metrics lpm_itlb Instruction TLB breakdown Processor socket power consumption estimates lpm_l3 L3 cache breakdown per CCX lpm_br_cond_insn_between_branches lpm_br;lpm_br_cond d_ratio(instructions, ex_ret_cond)  The number of instructions divided by the number of conditional branches  1insn    000lpm_br_cond_retired lpm_br;lpm_br_cond d_ratio(ex_ret_cond, duration_time)  Retired conditional branch instructions  1insn/s    000lpm_br_far_insn_between_branches lpm_br;lpm_br_far d_ratio(instructions, ex_ret_brn_far)  The number of instructions divided by the number of far branches  1insn    000lpm_br_far_retired lpm_br;lpm_br_far d_ratio(ex_ret_brn_far, duration_time)  Retired far control transfers per second  1insn/s    000lpm_br_fused_insn_between_branches lpm_br;lpm_br_cond d_ratio(instructions, ex_ret_fus_brnch_inst)  The number of instructions divided by the number of fused branches  1insn    000lpm_br_fused_retired lpm_br;lpm_br_cond d_ratio(ex_ret_fus_brnch_inst, duration_time)  Retired fused branch instructions per second  1insn/s    000lpm_br_taken_insn_between_branches lpm_br;lpm_br_taken d_ratio(instructions, ex_ret_brn_tkn)  The number of instructions divided by the number of taken branches  1insn    000lpm_br_taken_mispred lpm_br;lpm_br_taken d_ratio(ex_ret_brn_tkn_misp, ex_ret_brn_tkn)  The number of retired taken branch instructions that were mispredicted as a percentage of all taken branches  100%    000lpm_br_taken_retired lpm_br;lpm_br_taken d_ratio(ex_ret_brn_tkn, duration_time)  The number of taken branches that were retired per second  1insn/s    000lpm_br_total_insn_between_branches lpm_br;lpm_br_total d_ratio(instructions, ex_ret_brn)  The number of instructions divided by the number of branches  1insn    000lpm_br_total_insn_fe_resteers lpm_br;lpm_br_total d_ratio(ex_ret_brn_resync, duration_time)  The number of resync branches per second  1req/s    000lpm_br_total_mispred lpm_br;lpm_br_total d_ratio(ex_ret_brn_misp, ex_ret_brn)  The number of branch instructions retired, of any type, that were not correctly predicted as a percentage of all branch instrucions  100%    000lpm_br_total_retired lpm_br;lpm_br_total d_ratio(ex_ret_brn, duration_time)  The number of branch instructions retired per second  1insn/s    000lpm_cs_br_taken lpm_cs d_ratio(ex_ret_brn_tkn, context\-switches)  Branches taken per context switch  1br_taken/cs    000lpm_cs_loads lpm_cs d_ratio(ls_dispatch.ld_dispatch, context\-switches)  Loads per context switch  1loads/cs    000lpm_cs_stores lpm_cs d_ratio(ls_dispatch.store_dispatch, context\-switches)  Stores per context switch  1stores/cs    000lpm_dtlb_l1_hits lpm_dtlb;lpm_dtlb_l1 d_ratio(max(ls_dc_accesses - (ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit + ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit + ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit + (ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss + ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss + ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss) + (ls_tablewalker.dc_type0 + ls_tablewalker.dc_type1)), 0), ls_dc_accesses)  DTLB L1 hits as percentage of all DTLB L1 accesses  100%    000lpm_dtlb_l1_miss lpm_dtlb;lpm_dtlb_l1 d_ratio(ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit + ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit + ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit + (ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss + ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss + ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss) + (ls_tablewalker.dc_type0 + ls_tablewalker.dc_type1), ls_dc_accesses)  DTLB L1 misses as percentage of all DTLB L1 accesses  100%    000lpm_dtlb_l1_reqs lpm_dtlb;lpm_dtlb_l1 d_ratio(ls_dc_accesses, duration_time)  DTLB L1 accesses per second  1insns/s    000lpm_dtlb_l2_1g_hits lpm_dtlb;lpm_dtlb_l2;lpm_dtlb_l2_1g d_ratio(ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit, ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit + ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss)  DTLB L2 1gb page size hits as percentage of all DTLB L2 1gb accesses  100%    000lpm_dtlb_l2_1g_miss lpm_dtlb;lpm_dtlb_l2;lpm_dtlb_l2_1g d_ratio(ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss, ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit + ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss)  DTLB L2 1gb page size misses as percentage of all DTLB L2 1gb accesses  100%    000lpm_dtlb_l2_2mb_hits lpm_dtlb;lpm_dtlb_l2;lpm_dtlb_l2_2mb d_ratio(ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit, ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit + ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss)  DTLB L2 2mb page size hits as percentage of all DTLB L2 2mb accesses  100%    000lpm_dtlb_l2_2mb_miss lpm_dtlb;lpm_dtlb_l2;lpm_dtlb_l2_2mb d_ratio(ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss, ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit + ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss)  DTLB L2 2mb page size misses as percentage of all DTLB L2 accesses  100%    000lpm_dtlb_l2_4kb_hits lpm_dtlb;lpm_dtlb_l2;lpm_dtlb_l2_4kb d_ratio(ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit, ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit + ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss)  DTLB L2 4kb page size hits as percentage of all DTLB L2 4kb accesses  100%    000lpm_dtlb_l2_4kb_miss lpm_dtlb;lpm_dtlb_l2;lpm_dtlb_l2_4kb d_ratio(ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss, ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit + ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss)  DTLB L2 4kb page size misses as percentage of all DTLB L2 4kbaccesses  100%    000lpm_dtlb_l2_coal_hits lpm_dtlb;lpm_dtlb_l2;lpm_dtlb_l2_coalesced 0  DTLB L2 coalesced page (16kb) hits as percentage of all DTLB L2 coalesced accesses  100%    000lpm_dtlb_l2_coal_miss lpm_dtlb;lpm_dtlb_l2;lpm_dtlb_l2_coalesced 0  DTLB L2 coalesced page (16kb) misses as percentage of all DTLB L2 coalesced accesses  100%    000lpm_dtlb_l2_hits lpm_dtlb;lpm_dtlb_l2 d_ratio(ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit + ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit + ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit, ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit + ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit + ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit + (ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss + ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss + ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss))  DTLB L2 hits as percentage of all DTLB L2 accesses  100%    000lpm_dtlb_l2_miss lpm_dtlb;lpm_dtlb_l2 d_ratio(ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss + ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss + ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss, ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit + ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit + ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit + (ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss + ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss + ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss))  DTLB L2 misses as percentage of all DTLB L2 accesses  100%    000lpm_dtlb_l2_reqs lpm_dtlb;lpm_dtlb_l2 d_ratio(ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit + ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit + ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit + (ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss + ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss + ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss), duration_time)  DTLB L2 accesses per second  1insns/s    000lpm_dtlb_ov_insn_bt_l1_miss lpm_dtlb;lpm_dtlb_ov d_ratio(instructions, ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit + ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit + ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit + (ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss + ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss + ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss) + (ls_tablewalker.dc_type0 + ls_tablewalker.dc_type1))  DTLB overview: instructions between l1 misses  1insns    000lpm_dtlb_ov_insn_bt_walks lpm_dtlb;lpm_dtlb_ov d_ratio(instructions, ls_tablewalker.dc_type0 + ls_tablewalker.dc_type1)  DTLB overview: instructions between dtlb page table walks  1insns    000lpm_dtlb_walks_reqs lpm_dtlb;lpm_dtlb_walks d_ratio(ls_tablewalker.dc_type0 + ls_tablewalker.dc_type1, duration_time)  DTLB page table walks per second  1walks/s    000lpm_itlb_l1_hits lpm_itlb;lpm_itlb_l1 d_ratio(max(ic_fw32 - (bp_l1_tlb_miss_l2_hit + l2_itlb_misses), 0), max(ic_fw32 - (bp_l1_tlb_miss_l2_hit + l2_itlb_misses), 0) + (bp_l1_tlb_miss_l2_hit + l2_itlb_misses))  L1 ITLB hits as a perecentage of L1 ITLB accesses  100%    000lpm_itlb_l1_miss lpm_itlb;lpm_itlb_l1 d_ratio(bp_l1_tlb_miss_l2_hit + l2_itlb_misses, max(ic_fw32 - (bp_l1_tlb_miss_l2_hit + l2_itlb_misses), 0) + (bp_l1_tlb_miss_l2_hit + l2_itlb_misses))  L1 ITLB misses as a perecentage of L1 ITLB accesses  100%    000lpm_itlb_l1_reqs lpm_itlb;lpm_itlb_l1 d_ratio(ic_fw32, duration_time)  The number of 32B fetch windows transferred from IC pipe to DE instruction decoder per second  1windows per sec    000lpm_itlb_l2_hits lpm_itlb;lpm_itlb_l2 d_ratio(bp_l1_tlb_miss_l2_hit, bp_l1_tlb_miss_l2_hit + l2_itlb_misses)  L2 ITLB hits as a percentage of all L2 ITLB accesses  100%    000lpm_itlb_l2_miss lpm_itlb;lpm_itlb_l2 d_ratio(l2_itlb_misses, bp_l1_tlb_miss_l2_hit + l2_itlb_misses)  L2 ITLB misses as a percentage of all L2 ITLB accesses  100%    000lpm_itlb_l2_reqs lpm_itlb;lpm_itlb_l2 d_ratio(bp_l1_tlb_miss_l2_hit + l2_itlb_misses, duration_time)  ITLB accesses per second  1accesses per sec    000lpm_itlb_ov_insn_bt_l1_miss lpm_itlb;lpm_itlb_ov d_ratio(instructions, bp_l1_tlb_miss_l2_hit + l2_itlb_misses)  Number of instructions between l1 misses  1insns    000lpm_itlb_ov_insn_bt_l2_miss lpm_itlb;lpm_itlb_ov d_ratio(instructions, l2_itlb_misses)  Number of instructions between l2 misses  1insns    000lpm_l3_accesses lpm_l3 d_ratio(max(l3_lookup_state.all_l3_req_typs, l3_comb_clstr_state.request_miss), duration_time)  L3 victim cache accesses  1accesses per sec    000lpm_l3_hits lpm_l3 d_ratio(max(l3_lookup_state.all_l3_req_typs, l3_comb_clstr_state.request_miss) - l3_comb_clstr_state.request_miss, max(l3_lookup_state.all_l3_req_typs, l3_comb_clstr_state.request_miss))  L3 victim cache hit rate  100%    000lpm_l3_miss lpm_l3 d_ratio(l3_comb_clstr_state.request_miss, max(l3_lookup_state.all_l3_req_typs, l3_comb_clstr_state.request_miss))  L3 victim cache miss rate  100%    000lpm_ldst_insn_bt_ld lpm_ldst;lpm_ldst_insn_bt d_ratio(instructions, ls_dispatch.ld_dispatch)  Number of instructions between loads  1insns    000lpm_ldst_insn_bt_st lpm_ldst;lpm_ldst_insn_bt d_ratio(instructions, ls_dispatch.store_dispatch)  Number of instructions between stores  1insns    000lpm_ldst_percent_insn_ld lpm_ldst;lpm_ldst_percent_insn d_ratio(ls_dispatch.ld_dispatch, instructions)  Load instructions as a percentage of all instructions  100%    000lpm_ldst_percent_insn_st lpm_ldst;lpm_ldst_percent_insn d_ratio(ls_dispatch.store_dispatch, instructions)  Store instructions as a percentage of all instructions  100%    000lpm_ldst_ret_loads_per_cycle_1 lpm_ldst;lpm_ldst_ret_loads_per_cycle d_ratio(max(ls_dispatch.ld_dispatch@cmask\=1@ - ls_dispatch.ld_dispatch@cmask\=2@, 0), ls_not_halted_cyc)  Load instructions retiring in 1 cycle as a percentage of all unhalted cycles  100%    000lpm_ldst_ret_loads_per_cycle_2 lpm_ldst;lpm_ldst_ret_loads_per_cycle d_ratio(max(ls_dispatch.ld_dispatch@cmask\=2@ - ls_dispatch.ld_dispatch@cmask\=3@, 0), ls_not_halted_cyc)  Load instructions retiring in 2 cycles as a percentage of all unhalted cycles  100%    000lpm_ldst_ret_loads_per_cycle_3 lpm_ldst;lpm_ldst_ret_loads_per_cycle d_ratio(ls_dispatch.ld_dispatch@cmask\=3@, ls_not_halted_cyc)  Load instructions retiring in 3 or more cycles as a percentageof all unhalted cycles  100%    000lpm_ldst_ret_stores_per_cycle_1 lpm_ldst;lpm_ldst_ret_stores_per_cycle d_ratio(max(ls_dispatch.store_dispatch@cmask\=1@ - ls_dispatch.store_dispatch@cmask\=2@, 0), ls_not_halted_cyc)  Store instructions retiring in 1 cycle as a percentage of all unhalted cycles  100%    000lpm_ldst_ret_stores_per_cycle_2 lpm_ldst;lpm_ldst_ret_stores_per_cycle d_ratio(max(ls_dispatch.store_dispatch@cmask\=2@ - ls_dispatch.store_dispatch@cmask\=3@, 0), ls_not_halted_cyc)  Store instructions retiring in 2 cycles as a percentage of all unhalted cycles  100%    000lpm_ldst_ret_stores_per_cycle_3 lpm_ldst;lpm_ldst_ret_stores_per_cycle d_ratio(ls_dispatch.store_dispatch@cmask\=3@, ls_not_halted_cyc)  Store instructions retiring in 3 or more cycles as a percentageof all unhalted cycles  100%    000lpm_ldst_total_ld lpm_ldst;lpm_ldst_total d_ratio(ls_dispatch.ld_dispatch, duration_time)  Number of loads dispatched per second  1insns per sec    000lpm_ldst_total_st lpm_ldst;lpm_ldst_total d_ratio(ls_dispatch.store_dispatch, duration_time)  Number of stores dispatched per second  1insns per sec    000lpm_upc  d_ratio(ex_ret_cops, (cycles / 2 if #smt_on else cycles))  Micro-ops retired per core cycle (higher is better)  1uops/cycle    000branch_misprediction_ratio branch_prediction d_ratio(ex_ret_brn_misp, ex_ret_brn)  Execution-Time Branch Misprediction Ratio (Non-Speculative)  100%    000all_l2_cache_accesses l2_cache l2_request_g1.all_no_prefetch + l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3  All L2 Cache Accesses      000l2_cache_accesses_from_l2_hwpf l2_cache l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3  L2 Cache Accesses from L2 HWPF      000all_l2_cache_misses l2_cache l2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3  All L2 Cache Misses      000l2_cache_misses_from_l2_hwpf l2_cache l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3  L2 Cache Misses from L2 HWPF      000all_l2_cache_hits l2_cache l2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2  All L2 Cache Hits      000l3_read_miss_latency l3_cache xi_sys_fill_latency * 16 / xi_ccx_sdp_req1.all_l3_miss_req_typs  Average L3 Read Miss Latency (in core clocks)  1core clocks    000ic_fetch_miss_ratio l2_cache d_ratio(l2_cache_req_stat.ic_access_in_l2, bp_l1_tlb_fetch_hit + bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_miss)  L1 Instruction Cache (32B) Fetch Miss Ratio  100%    000l1_itlb_misses tlb bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_miss  L1 ITLB Misses      000all_remote_links_outbound data_fabric remote_outbound_data_controller_0 + remote_outbound_data_controller_1 + remote_outbound_data_controller_2 + remote_outbound_data_controller_3  Approximate: Outbound data bytes for all Remote Links for a node (die)  3e-5MiB    000nps1_die_to_dram data_fabric dram_channel_data_controller_0 + dram_channel_data_controller_1 + dram_channel_data_controller_2 + dram_channel_data_controller_3 + dram_channel_data_controller_4 + dram_channel_data_controller_5 + dram_channel_data_controller_6 + dram_channel_data_controller_7  Approximate: Combined DRAM B/bytes of all channels on a NPS1 node (die)  6.1e-5MiB    010lpm_br_cond_mispred lpm_br;lpm_br_cond d_ratio(ex_ret_cond_misp, ex_ret_cond)  Retired conditional branch instructions mispredicted as a percentage of all conditional branches  100%    000lpm_dtlb_l1_hits lpm_dtlb;lpm_dtlb_l1 d_ratio(max(ls_dc_accesses - (ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit + ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit + ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit + ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit + (ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss + ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss + ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss + ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss) + (ls_tablewalker.dc_type0 + ls_tablewalker.dc_type1)), 0), ls_dc_accesses)  DTLB L1 hits as percentage of all DTLB L1 accesses  100%    000lpm_dtlb_l1_miss lpm_dtlb;lpm_dtlb_l1 d_ratio(ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit + ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit + ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit + ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit + (ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss + ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss + ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss + ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss) + (ls_tablewalker.dc_type0 + ls_tablewalker.dc_type1), ls_dc_accesses)  DTLB L1 misses as percentage of all DTLB L1 accesses  100%    000lpm_dtlb_l2_coal_hits lpm_dtlb;lpm_dtlb_l2;lpm_dtlb_l2_coalesced d_ratio(ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit, ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit + ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss)  DTLB L2 coalesced page (16kb) hits as percentage of all DTLB L2 coalesced accesses  100%    000lpm_dtlb_l2_coal_miss lpm_dtlb;lpm_dtlb_l2;lpm_dtlb_l2_coalesced d_ratio(ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss, ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit + ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss)  DTLB L2 coalesced page (16kb) misses as percentage of all DTLB L2 coalesced accesses  100%    000lpm_dtlb_l2_hits lpm_dtlb;lpm_dtlb_l2 d_ratio(ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit + ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit + ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit + ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit, ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit + ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit + ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit + ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit + (ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss + ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss + ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss + ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss))  DTLB L2 hits as percentage of all DTLB L2 accesses  100%    000lpm_dtlb_l2_miss lpm_dtlb;lpm_dtlb_l2 d_ratio(ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss + ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss + ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss + ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss, ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit + ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit + ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit + ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit + (ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss + ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss + ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss + ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss))  DTLB L2 misses as percentage of all DTLB L2 accesses  100%    000lpm_dtlb_l2_reqs lpm_dtlb;lpm_dtlb_l2 d_ratio(ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit + ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit + ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit + ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit + (ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss + ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss + ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss + ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss), duration_time)  DTLB L2 accesses per second  1insns/s    000lpm_dtlb_ov_insn_bt_l1_miss lpm_dtlb;lpm_dtlb_ov d_ratio(instructions, ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit + ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit + ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit + ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit + (ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss + ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss + ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss + ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss) + (ls_tablewalker.dc_type0 + ls_tablewalker.dc_type1))  DTLB overview: instructions between l1 misses  1insns    000ic_fetch_miss_ratio l2_cache d_ratio(l2_cache_req_stat.ic_access_in_l2, bp_l1_tlb_fetch_hit + bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_tlb_miss)  L1 Instruction Cache (32B) Fetch Miss Ratio  100%    000l1_itlb_misses tlb bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_tlb_miss  L1 ITLB Misses      000lpm_br_fused_insn_between_branches lpm_br;lpm_br_cond d_ratio(instructions, ex_ret_fused_instr)  The number of instructions divided by the number of fused branches  1insn    000lpm_br_fused_retired lpm_br;lpm_br_cond d_ratio(ex_ret_fused_instr, duration_time)  Retired fused branch instructions per second  1insn/s    000lpm_br_total_insn_fe_resteers lpm_br;lpm_br_total d_ratio(ex_ret_msprd_brnch_instr_dir_msmtch, duration_time)  The number of resync branches per second  1req/s    000lpm_itlb_l1_hits lpm_itlb;lpm_itlb_l1 d_ratio(max(ic_fw32 - (bp_l1_tlb_miss_l2_tlb_hit + l2_itlb_misses), 0), max(ic_fw32 - (bp_l1_tlb_miss_l2_tlb_hit + l2_itlb_misses), 0) + (bp_l1_tlb_miss_l2_tlb_hit + l2_itlb_misses))  L1 ITLB hits as a perecentage of L1 ITLB accesses  100%    000lpm_itlb_l1_miss lpm_itlb;lpm_itlb_l1 d_ratio(bp_l1_tlb_miss_l2_tlb_hit + l2_itlb_misses, max(ic_fw32 - (bp_l1_tlb_miss_l2_tlb_hit + l2_itlb_misses), 0) + (bp_l1_tlb_miss_l2_tlb_hit + l2_itlb_misses))  L1 ITLB misses as a perecentage of L1 ITLB accesses  100%    000lpm_itlb_l2_hits lpm_itlb;lpm_itlb_l2 d_ratio(bp_l1_tlb_miss_l2_tlb_hit, bp_l1_tlb_miss_l2_tlb_hit + l2_itlb_misses)  L2 ITLB hits as a percentage of all L2 ITLB accesses  100%    000lpm_itlb_l2_miss lpm_itlb;lpm_itlb_l2 d_ratio(l2_itlb_misses, bp_l1_tlb_miss_l2_tlb_hit + l2_itlb_misses)  L2 ITLB misses as a percentage of all L2 ITLB accesses  100%    000lpm_itlb_l2_reqs lpm_itlb;lpm_itlb_l2 d_ratio(bp_l1_tlb_miss_l2_tlb_hit + l2_itlb_misses, duration_time)  ITLB accesses per second  1accesses per sec    000lpm_itlb_ov_insn_bt_l1_miss lpm_itlb;lpm_itlb_ov d_ratio(instructions, bp_l1_tlb_miss_l2_tlb_hit + l2_itlb_misses)  Number of instructions between l1 misses  1insns    000lpm_upc  d_ratio(ex_ret_ops, (cycles / 2 if #smt_on else cycles))  Micro-ops retired per core cycle (higher is better)  1uops/cycle    000l2_cache_misses_from_l2_hwpf l2_cache l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3  L2 Cache Misses from L2 Cache HWPF      000l3_read_miss_latency l3_cache xi_sys_fill_latency * 16 / xi_ccx_sdp_req1  Average L3 Read Miss Latency (in core clocks)  1core clocks    000op_cache_fetch_miss_ratio l2_cache d_ratio(op_cache_hit_miss.op_cache_miss, op_cache_hit_miss.all_op_cache_accesses)  Op Cache (64B) Fetch Miss Ratio      000ic_fetch_miss_ratio l2_cache d_ratio(ic_tag_hit_miss.instruction_cache_miss, ic_tag_hit_miss.all_instruction_cache_accesses)  Instruction Cache (32B) Fetch Miss Ratio  100%    000l1_itlb_misses tlb bp_l1_tlb_miss_l2_tlb_hit + bp_l1_tlb_miss_l2_tlb_miss  L1 ITLB Misses      000macro_ops_dispatched decoder de_dis_cops_from_decoder.disp_op_type.any_integer_dispatch + de_dis_cops_from_decoder.disp_op_type.any_fp_dispatch  Macro-ops Dispatched      000lpm_l3_accesses lpm_l3 d_ratio(max(l3_lookup_state.all_coherent_accesses_to_l3, l3_lookup_state.l3_miss), duration_time)  L3 victim cache accesses  1accesses per sec    000lpm_l3_hits lpm_l3 d_ratio(max(l3_lookup_state.all_coherent_accesses_to_l3, l3_lookup_state.l3_miss) - l3_lookup_state.l3_miss, max(l3_lookup_state.all_coherent_accesses_to_l3, l3_lookup_state.l3_miss))  L3 victim cache hit rate  100%    000lpm_l3_miss lpm_l3 d_ratio(l3_lookup_state.l3_miss, max(l3_lookup_state.all_coherent_accesses_to_l3, l3_lookup_state.l3_miss))  L3 victim cache miss rate  100%    000total_dispatch_slots  6 * ls_not_halted_cyc  Total dispatch slots (upto 6 instructions can be dispatched in each cycle)      000frontend_bound PipelineL1 d_ratio(de_no_dispatch_per_slot.no_ops_from_frontend, total_dispatch_slots)  Fraction of dispatch slots that remained unused because the frontend did not supply enough instructions/ops  100%    000bad_speculation PipelineL1 d_ratio(de_src_op_disp.all - ex_ret_ops, total_dispatch_slots)  Fraction of dispatched ops that did not retire  100%    000backend_bound PipelineL1 d_ratio(de_no_dispatch_per_slot.backend_stalls, total_dispatch_slots)  Fraction of dispatch slots that remained unused because of backend stalls  100%    000smt_contention PipelineL1 d_ratio(de_no_dispatch_per_slot.smt_contention, total_dispatch_slots)  Fraction of dispatch slots that remained unused because the other thread was selected  100%    000retiring PipelineL1 d_ratio(ex_ret_ops, total_dispatch_slots)  Fraction of dispatch slots used by ops that retired  100%    000frontend_bound_latency PipelineL2;frontend_bound_group d_ratio(6 * cpu@de_no_dispatch_per_slot.no_ops_from_frontend\,cmask\=0x6@, total_dispatch_slots)  Fraction of dispatch slots that remained unused because of a latency bottleneck in the frontend (such as instruction cache or TLB misses)  100%    000frontend_bound_bandwidth PipelineL2;frontend_bound_group d_ratio(de_no_dispatch_per_slot.no_ops_from_frontend - 6 * cpu@de_no_dispatch_per_slot.no_ops_from_frontend\,cmask\=0x6@, total_dispatch_slots)  Fraction of dispatch slots that remained unused because of a bandwidth bottleneck in the frontend (such as decode or op cache fetch bandwidth)  100%    000bad_speculation_mispredicts PipelineL2;bad_speculation_group d_ratio(bad_speculation * ex_ret_brn_misp, ex_ret_brn_misp + resyncs_or_nc_redirects)  Fraction of dispatched ops that were flushed due to branch mispredicts  100%    000bad_speculation_pipeline_restarts PipelineL2;bad_speculation_group d_ratio(bad_speculation * resyncs_or_nc_redirects, ex_ret_brn_misp + resyncs_or_nc_redirects)  Fraction of dispatched ops that were flushed due to pipeline restarts (resyncs)  100%    000backend_bound_memory PipelineL2;backend_bound_group backend_bound * d_ratio(ex_no_retire.load_not_complete, ex_no_retire.not_complete)  Fraction of dispatch slots that remained unused because of stalls due to the memory subsystem  100%    000backend_bound_cpu PipelineL2;backend_bound_group backend_bound * (1 - d_ratio(ex_no_retire.load_not_complete, ex_no_retire.not_complete))  Fraction of dispatch slots that remained unused because of stalls not related to the memory subsystem  100%    000retiring_fastpath PipelineL2;retiring_group retiring * (1 - d_ratio(ex_ret_ucode_ops, ex_ret_ops))  Fraction of dispatch slots used by fastpath ops that retired  100%    000retiring_microcode PipelineL2;retiring_group retiring * d_ratio(ex_ret_ucode_ops, ex_ret_ops)  Fraction of dispatch slots used by microcode ops that retired  100%    000branch_misprediction_ratio branch_prediction d_ratio(ex_ret_brn_misp, ex_ret_brn)  Execution-time branch misprediction ratio (non-speculative)  100%    000all_l2_cache_accesses l2_cache l2_request_g1.all_no_prefetch + l2_pf_hit_l2.all + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all  All L2 cache accesses      000l2_cache_accesses_from_l1_ic_misses l2_cache l2_request_g1.cacheable_ic_read  L2 cache accesses from L1 instruction cache misses (including prefetch)      000l2_cache_accesses_from_l1_dc_misses l2_cache l2_request_g1.all_dc  L2 cache accesses from L1 data cache misses (including prefetch)      000l2_cache_accesses_from_l2_hwpf l2_cache l2_pf_hit_l2.all + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all  L2 cache accesses from L2 cache hardware prefetcher      000all_l2_cache_misses l2_cache l2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all  All L2 cache misses      000l2_cache_misses_from_l1_ic_miss l2_cache l2_cache_req_stat.ic_fill_miss  L2 cache misses from L1 instruction cache misses      000l2_cache_misses_from_l1_dc_miss l2_cache l2_cache_req_stat.ls_rd_blk_c  L2 cache misses from L1 data cache misses      000l2_cache_misses_from_l2_hwpf l2_cache l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all  L2 cache misses from L2 cache hardware prefetcher      000all_l2_cache_hits l2_cache l2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2.all  All L2 cache hits      000l2_cache_hits_from_l1_ic_miss l2_cache l2_cache_req_stat.ic_hit_in_l2  L2 cache hits from L1 instruction cache misses      000l2_cache_hits_from_l1_dc_miss l2_cache l2_cache_req_stat.dc_hit_in_l2  L2 cache hits from L1 data cache misses      000l2_cache_hits_from_l2_hwpf l2_cache l2_pf_hit_l2.all  L2 cache hits from L2 cache hardware prefetcher      000l3_cache_accesses l3_cache l3_lookup_state.all_coherent_accesses_to_l3  L3 cache accesses      000l3_misses l3_cache l3_lookup_state.l3_miss  L3 misses (including cacheline state change requests)      000l3_read_miss_latency l3_cache l3_xi_sampled_latency.all * 10 / l3_xi_sampled_latency_requests.all  Average L3 read miss latency (in core clocks)  1core clocks    000op_cache_fetch_miss_ratio  d_ratio(op_cache_hit_miss.op_cache_miss, op_cache_hit_miss.all_op_cache_accesses)  Op cache miss ratio for all fetches  100%    000ic_fetch_miss_ratio  d_ratio(ic_tag_hit_miss.instruction_cache_miss, ic_tag_hit_miss.all_instruction_cache_accesses)  Instruction cache miss ratio for all fetches. An instruction cache miss will not be counted by this metric if it is an OC hit  100%    000l1_data_cache_fills_from_memory l1_dcache ls_any_fills_from_sys.dram_io_all  L1 data cache fills from DRAM or MMIO in any NUMA node      000l1_data_cache_fills_from_remote_node l1_dcache ls_any_fills_from_sys.far_all  L1 data cache fills from a different NUMA node      000l1_data_cache_fills_from_same_ccx l1_dcache ls_any_fills_from_sys.local_all  L1 data cache fills from within the same CCX      000l1_data_cache_fills_from_different_ccx l1_dcache ls_any_fills_from_sys.remote_cache  L1 data cache fills from another CCX cache in any NUMA node      000all_l1_data_cache_fills l1_dcache ls_any_fills_from_sys.all  All L1 data cache fills      000l1_demand_data_cache_fills_from_local_l2 l1_dcache ls_dmnd_fills_from_sys.local_l2  L1 demand data cache fills from local L2 cache      000l1_demand_data_cache_fills_from_same_ccx l1_dcache ls_dmnd_fills_from_sys.local_ccx  L1 demand data cache fills from within the same CCX      000l1_demand_data_cache_fills_from_near_cache l1_dcache ls_dmnd_fills_from_sys.near_cache  L1 demand data cache fills from another CCX cache in the same NUMA node      000l1_demand_data_cache_fills_from_near_memory l1_dcache ls_dmnd_fills_from_sys.dram_io_near  L1 demand data cache fills from DRAM or MMIO in the same NUMA node      000l1_demand_data_cache_fills_from_far_cache l1_dcache ls_dmnd_fills_from_sys.far_cache  L1 demand data cache fills from another CCX cache in a different NUMA node      000l1_demand_data_cache_fills_from_far_memory l1_dcache ls_dmnd_fills_from_sys.dram_io_far  L1 demand data cache fills from DRAM or MMIO in a different NUMA node      000l1_itlb_misses tlb bp_l1_tlb_miss_l2_tlb_hit + bp_l1_tlb_miss_l2_tlb_miss.all  L1 instruction TLB misses      000l2_itlb_misses tlb bp_l1_tlb_miss_l2_tlb_miss.all  L2 instruction TLB misses and instruction page walks      000l1_dtlb_misses tlb ls_l1_d_tlb_miss.all  L1 data TLB misses      000l2_dtlb_misses tlb ls_l1_d_tlb_miss.all_l2_miss  L2 data TLB misses and data page walks      000all_tlbs_flushed tlb ls_tlb_flush.all  All TLBs flushed      000macro_ops_dispatched decoder de_src_op_disp.all  Macro-ops dispatched      000sse_avx_stalls  fp_disp_faults.sse_avx_all  Mixed SSE/AVX stalls      000macro_ops_retired  ex_ret_ops  Macro-ops retired      000dram_read_data_for_local_processor data_fabric local_processor_read_data_beats_cs0 + local_processor_read_data_beats_cs1 + local_processor_read_data_beats_cs2 + local_processor_read_data_beats_cs3 + local_processor_read_data_beats_cs4 + local_processor_read_data_beats_cs5 + local_processor_read_data_beats_cs6 + local_processor_read_data_beats_cs7 + local_processor_read_data_beats_cs8 + local_processor_read_data_beats_cs9 + local_processor_read_data_beats_cs10 + local_processor_read_data_beats_cs11  DRAM read data for local processor  6.103515625e-5MiB    000dram_write_data_for_local_processor data_fabric local_processor_write_data_beats_cs0 + local_processor_write_data_beats_cs1 + local_processor_write_data_beats_cs2 + local_processor_write_data_beats_cs3 + local_processor_write_data_beats_cs4 + local_processor_write_data_beats_cs5 + local_processor_write_data_beats_cs6 + local_processor_write_data_beats_cs7 + local_processor_write_data_beats_cs8 + local_processor_write_data_beats_cs9 + local_processor_write_data_beats_cs10 + local_processor_write_data_beats_cs11  DRAM write data for local processor  6.103515625e-5MiB    000dram_read_data_for_remote_processor data_fabric remote_processor_read_data_beats_cs0 + remote_processor_read_data_beats_cs1 + remote_processor_read_data_beats_cs2 + remote_processor_read_data_beats_cs3 + remote_processor_read_data_beats_cs4 + remote_processor_read_data_beats_cs5 + remote_processor_read_data_beats_cs6 + remote_processor_read_data_beats_cs7 + remote_processor_read_data_beats_cs8 + remote_processor_read_data_beats_cs9 + remote_processor_read_data_beats_cs10 + remote_processor_read_data_beats_cs11  DRAM read data for remote processor  6.103515625e-5MiB    000dram_write_data_for_remote_processor data_fabric remote_processor_write_data_beats_cs0 + remote_processor_write_data_beats_cs1 + remote_processor_write_data_beats_cs2 + remote_processor_write_data_beats_cs3 + remote_processor_write_data_beats_cs4 + remote_processor_write_data_beats_cs5 + remote_processor_write_data_beats_cs6 + remote_processor_write_data_beats_cs7 + remote_processor_write_data_beats_cs8 + remote_processor_write_data_beats_cs9 + remote_processor_write_data_beats_cs10 + remote_processor_write_data_beats_cs11  DRAM write data for remote processor  6.103515625e-5MiB    000local_socket_upstream_dma_read_data data_fabric local_socket_upstream_read_beats_iom0 + local_socket_upstream_read_beats_iom1 + local_socket_upstream_read_beats_iom2 + local_socket_upstream_read_beats_iom3  Local socket upstream DMA read data  6.103515625e-5MiB    000local_socket_upstream_dma_write_data data_fabric local_socket_upstream_write_beats_iom0 + local_socket_upstream_write_beats_iom1 + local_socket_upstream_write_beats_iom2 + local_socket_upstream_write_beats_iom3  Local socket upstream DMA write data  6.103515625e-5MiB    000remote_socket_upstream_dma_read_data data_fabric remote_socket_upstream_read_beats_iom0 + remote_socket_upstream_read_beats_iom1 + remote_socket_upstream_read_beats_iom2 + remote_socket_upstream_read_beats_iom3  Remote socket upstream DMA read data  6.103515625e-5MiB    000remote_socket_upstream_dma_write_data data_fabric remote_socket_upstream_write_beats_iom0 + remote_socket_upstream_write_beats_iom1 + remote_socket_upstream_write_beats_iom2 + remote_socket_upstream_write_beats_iom3  Remote socket upstream DMA write data  6.103515625e-5MiB    000local_socket_inbound_data_to_cpu data_fabric local_socket_inf0_inbound_data_beats_ccm0 + local_socket_inf1_inbound_data_beats_ccm0 + local_socket_inf0_inbound_data_beats_ccm1 + local_socket_inf1_inbound_data_beats_ccm1 + local_socket_inf0_inbound_data_beats_ccm2 + local_socket_inf1_inbound_data_beats_ccm2 + local_socket_inf0_inbound_data_beats_ccm3 + local_socket_inf1_inbound_data_beats_ccm3 + local_socket_inf0_inbound_data_beats_ccm4 + local_socket_inf1_inbound_data_beats_ccm4 + local_socket_inf0_inbound_data_beats_ccm5 + local_socket_inf1_inbound_data_beats_ccm5 + local_socket_inf0_inbound_data_beats_ccm6 + local_socket_inf1_inbound_data_beats_ccm6 + local_socket_inf0_inbound_data_beats_ccm7 + local_socket_inf1_inbound_data_beats_ccm7  Local socket inbound data to the CPU (e.g. read data)  3.0517578125e-5MiB    000local_socket_outbound_data_from_cpu data_fabric local_socket_inf0_outbound_data_beats_ccm0 + local_socket_inf1_outbound_data_beats_ccm0 + local_socket_inf0_outbound_data_beats_ccm1 + local_socket_inf1_outbound_data_beats_ccm1 + local_socket_inf0_outbound_data_beats_ccm2 + local_socket_inf1_outbound_data_beats_ccm2 + local_socket_inf0_outbound_data_beats_ccm3 + local_socket_inf1_outbound_data_beats_ccm3 + local_socket_inf0_outbound_data_beats_ccm4 + local_socket_inf1_outbound_data_beats_ccm4 + local_socket_inf0_outbound_data_beats_ccm5 + local_socket_inf1_outbound_data_beats_ccm5 + local_socket_inf0_outbound_data_beats_ccm6 + local_socket_inf1_outbound_data_beats_ccm6 + local_socket_inf0_outbound_data_beats_ccm7 + local_socket_inf1_outbound_data_beats_ccm7  Local socket outbound data from the CPU (e.g. write data)  6.103515625e-5MiB    000remote_socket_inbound_data_to_cpu data_fabric remote_socket_inf0_inbound_data_beats_ccm0 + remote_socket_inf1_inbound_data_beats_ccm0 + remote_socket_inf0_inbound_data_beats_ccm1 + remote_socket_inf1_inbound_data_beats_ccm1 + remote_socket_inf0_inbound_data_beats_ccm2 + remote_socket_inf1_inbound_data_beats_ccm2 + remote_socket_inf0_inbound_data_beats_ccm3 + remote_socket_inf1_inbound_data_beats_ccm3 + remote_socket_inf0_inbound_data_beats_ccm4 + remote_socket_inf1_inbound_data_beats_ccm4 + remote_socket_inf0_inbound_data_beats_ccm5 + remote_socket_inf1_inbound_data_beats_ccm5 + remote_socket_inf0_inbound_data_beats_ccm6 + remote_socket_inf1_inbound_data_beats_ccm6 + remote_socket_inf0_inbound_data_beats_ccm7 + remote_socket_inf1_inbound_data_beats_ccm7  Remote socket inbound data to the CPU (e.g. read data)  3.0517578125e-5MiB    000remote_socket_outbound_data_from_cpu data_fabric remote_socket_inf0_outbound_data_beats_ccm0 + remote_socket_inf1_outbound_data_beats_ccm0 + remote_socket_inf0_outbound_data_beats_ccm1 + remote_socket_inf1_outbound_data_beats_ccm1 + remote_socket_inf0_outbound_data_beats_ccm2 + remote_socket_inf1_outbound_data_beats_ccm2 + remote_socket_inf0_outbound_data_beats_ccm3 + remote_socket_inf1_outbound_data_beats_ccm3 + remote_socket_inf0_outbound_data_beats_ccm4 + remote_socket_inf1_outbound_data_beats_ccm4 + remote_socket_inf0_outbound_data_beats_ccm5 + remote_socket_inf1_outbound_data_beats_ccm5 + remote_socket_inf0_outbound_data_beats_ccm6 + remote_socket_inf1_outbound_data_beats_ccm6 + remote_socket_inf0_outbound_data_beats_ccm7 + remote_socket_inf1_outbound_data_beats_ccm7  Remote socket outbound data from the CPU (e.g. write data)  6.103515625e-5MiB    000local_socket_outbound_data_from_all_links data_fabric local_socket_outbound_data_beats_link0 + local_socket_outbound_data_beats_link1 + local_socket_outbound_data_beats_link2 + local_socket_outbound_data_beats_link3 + local_socket_outbound_data_beats_link4 + local_socket_outbound_data_beats_link5 + local_socket_outbound_data_beats_link6 + local_socket_outbound_data_beats_link7  Outbound data from all links (local socket)  6.103515625e-5MiB    000umc_data_bus_utilization memory_controller d_ratio(umc_data_slot_clks.all / 2, umc_mem_clk)  Memory controller data bus utilization  100%    000umc_cas_cmd_rate memory_controller d_ratio(umc_cas_cmd.all * 1e3, umc_mem_clk)  Memory controller CAS command rate      000umc_cas_cmd_read_ratio memory_controller d_ratio(umc_cas_cmd.rd, umc_cas_cmd.all)  Ratio of memory controller CAS commands for reads  100%    000umc_cas_cmd_write_ratio memory_controller d_ratio(umc_cas_cmd.wr, umc_cas_cmd.all)  Ratio of memory controller CAS commands for writes  100%    000umc_mem_read_bandwidth memory_controller umc_cas_cmd.rd * 64 / 1e6 / duration_time  Estimated memory read bandwidth  1MB/s    000umc_mem_write_bandwidth memory_controller umc_cas_cmd.wr * 64 / 1e6 / duration_time  Estimated memory write bandwidth  1MB/s    000umc_mem_bandwidth memory_controller umc_cas_cmd.all * 64 / 1e6 / duration_time  Estimated combined memory bandwidth  1MB/s    000umc_activate_cmd_rate memory_controller d_ratio(umc_act_cmd.all * 1e3, umc_mem_clk)  Memory controller ACTIVATE command rate      000umc_precharge_cmd_rate memory_controller d_ratio(umc_pchg_cmd.all * 1e3, umc_mem_clk)  Memory controller PRECHARGE command rate      000total_dispatch_slots  8 * ls_not_halted_cyc  Total dispatch slots (up to 8 instructions can be dispatched in each cycle)  1slots    000frontend_bound PipelineL1 d_ratio(de_no_dispatch_per_slot.no_ops_from_frontend, total_dispatch_slots)  Percentage of dispatch slots that remained unused because the frontend did not supply enough instructions/ops  100%slots    000bad_speculation PipelineL1 d_ratio(de_src_op_disp.all - ex_ret_ops, total_dispatch_slots)  Percentage of dispatched ops that did not retire  100%ops    000backend_bound PipelineL1 d_ratio(de_no_dispatch_per_slot.backend_stalls, total_dispatch_slots)  Percentage of dispatch slots that remained unused because of backend stalls  100%slots    000smt_contention PipelineL1 d_ratio(de_no_dispatch_per_slot.smt_contention, total_dispatch_slots)  Percentage of dispatch slots that remained unused because the other thread was selected  100%slots    000retiring PipelineL1 d_ratio(ex_ret_ops, total_dispatch_slots)  Percentage of dispatch slots used by ops that retired  100%slots    000frontend_bound_by_latency PipelineL2;frontend_bound_group d_ratio(8 * cpu@de_no_dispatch_per_slot.no_ops_from_frontend\,cmask\=0x8@, total_dispatch_slots)  Percentage of dispatch slots that remained unused because of a latency bottleneck in the frontend (such as instruction cache or TLB misses)  100%slots    000frontend_bound_by_bandwidth PipelineL2;frontend_bound_group d_ratio(de_no_dispatch_per_slot.no_ops_from_frontend - 8 * cpu@de_no_dispatch_per_slot.no_ops_from_frontend\,cmask\=0x8@, total_dispatch_slots)  Percentage of dispatch slots that remained unused because of a bandwidth bottleneck in the frontend (such as decode or op cache fetch bandwidth)  100%slots    000bad_speculation_from_mispredicts PipelineL2;bad_speculation_group d_ratio(bad_speculation * ex_ret_brn_misp, ex_ret_brn_misp + bp_redirects.resync)  Percentage of dispatched ops that were flushed due to branch mispredicts  100%ops    000bad_speculation_from_pipeline_restarts PipelineL2;bad_speculation_group d_ratio(bad_speculation * bp_redirects.resync, ex_ret_brn_misp + bp_redirects.resync)  Percentage of dispatched ops that were flushed due to pipeline restarts (resyncs)  100%ops    000backend_bound_by_memory PipelineL2;backend_bound_group backend_bound * d_ratio(ex_no_retire.load_not_complete, ex_no_retire.not_complete)  Percentage of dispatch slots that remained unused because of stalls due to the memory subsystem  100%slots    000backend_bound_by_cpu PipelineL2;backend_bound_group backend_bound * (1 - d_ratio(ex_no_retire.load_not_complete, ex_no_retire.not_complete))  Percentage of dispatch slots that remained unused because of stalls not related to the memory subsystem  100%slots    000retiring_from_fastpath PipelineL2;retiring_group retiring * (1 - d_ratio(ex_ret_ucode_ops, ex_ret_ops))  Percentage of dispatch slots used by fastpath ops that retired  100%slots    000retiring_from_microcode PipelineL2;retiring_group retiring * d_ratio(ex_ret_ucode_ops, ex_ret_ops)  Percentage of dispatch slots used by microcode ops that retired  100%slots    000branch_misprediction_rate branch_prediction d_ratio(ex_ret_brn_misp, ex_ret_brn)  Execution-time branch misprediction rate (non-speculative)  1per_branch    000all_data_cache_accesses_pti l1_dcache ls_dispatch.all / instructions  All data cache accesses per thousand instructions  1e3per_1k_instr    000all_l2_cache_accesses_pti l2_cache (l2_request_g1.all_no_prefetch + l2_pf_hit_l2.l2_hwpf + l2_pf_miss_l2_hit_l3.l2_hwpf + l2_pf_miss_l2_l3.l2_hwpf) / instructions  All L2 cache accesses per thousand instructions  1e3per_1k_instr    000l2_cache_accesses_from_l1_ic_misses_pti l2_cache l2_request_g1.cacheable_ic_read / instructions  L2 cache accesses from L1 instruction cache misses (including prefetch) per thousand instructions  1e3per_1k_instr    000l2_cache_accesses_from_l1_dc_misses_pti l2_cache l2_request_g1.all_dc / instructions  L2 cache accesses from L1 data cache misses (including prefetch) per thousand instructions  1e3per_1k_instr    000l2_cache_accesses_from_l2_hwpf_pti l2_cache (l2_pf_hit_l2.l1_dc_l2_hwpf + l2_pf_miss_l2_hit_l3.l1_dc_l2_hwpf + l2_pf_miss_l2_l3.l1_dc_l2_hwpf) / instructions  L2 cache accesses from L2 cache hardware prefetcher per thousand instructions  1e3per_1k_instr    000all_l2_cache_misses_pti l2_cache (l2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3.l2_hwpf + l2_pf_miss_l2_l3.l2_hwpf) / instructions  All L2 cache misses per thousand instructions  1e3per_1k_instr    000l2_cache_misses_from_l1_ic_miss_pti l2_cache l2_cache_req_stat.ic_fill_miss / instructions  L2 cache misses from L1 instruction cache misses per thousand instructions  1e3per_1k_instr    000l2_cache_misses_from_l1_dc_miss_pti l2_cache l2_cache_req_stat.ls_rd_blk_c / instructions  L2 cache misses from L1 data cache misses per thousand instructions  1e3per_1k_instr    000l2_cache_misses_from_l2_hwpf_pti l2_cache (l2_pf_miss_l2_hit_l3.l1_dc_l2_hwpf + l2_pf_miss_l2_l3.l1_dc_l2_hwpf) / instructions  L2 cache misses from L2 cache hardware prefetcher per thousand instructions  1e3per_1k_instr    000all_l2_cache_hits_pti l2_cache (l2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2.l2_hwpf) / instructions  All L2 cache hits per thousand instructions  1e3per_1k_instr    000l2_cache_hits_from_l1_ic_miss_pti l2_cache l2_cache_req_stat.ic_hit_in_l2 / instructions  L2 cache hits from L1 instruction cache misses per thousand instructions  1e3per_1k_instr    000l2_cache_hits_from_l1_dc_miss_pti l2_cache l2_cache_req_stat.dc_hit_in_l2 / instructions  L2 cache hits from L1 data cache misses per thousand instructions  1e3per_1k_instr    000l2_cache_hits_from_l2_hwpf_pti l2_cache l2_pf_hit_l2.l1_dc_l2_hwpf / instructions  L2 cache hits from L2 cache hardware prefetcher per thousand instructions  1e3per_1k_instr    000l3_read_miss_latency l3_cache l3_xi_sampled_latency.all * 10 / l3_xi_sampled_latency_requests.all  Average L3 read miss latency (in core clocks)  1ns    000l3_read_miss_latency_for_local_dram l3_cache l3_xi_sampled_latency.dram_near * 10 / l3_xi_sampled_latency_requests.dram_near  Average L3 read miss latency (in core clocks) for local DRAM  1ns    000l3_read_miss_latency_for_remote_dram l3_cache l3_xi_sampled_latency.dram_far * 10 / l3_xi_sampled_latency_requests.dram_far  Average L3 read miss latency (in core clocks) for remote DRAM  1ns    000l1_data_cache_fills_from_memory_pti l1_dcache ls_any_fills_from_sys.dram_io_all / instructions  L1 data cache fills from DRAM or MMIO in any NUMA node per thousand instructions  1e3per_1k_instr    000l1_data_cache_fills_from_remote_node_pti l1_dcache ls_any_fills_from_sys.far_all / instructions  L1 data cache fills from a different NUMA node per thousand instructions  1e3per_1k_instr    000l1_data_cache_fills_from_same_ccx_pti l1_dcache ls_any_fills_from_sys.local_all / instructions  L1 data cache fills from within the same CCX per thousand instructions  1e3per_1k_instr    000l1_data_cache_fills_from_different_ccx_pti l1_dcache ls_any_fills_from_sys.remote_cache / instructions  L1 data cache fills from another CCX cache in any NUMA node per thousand instructions  1e3per_1k_instr    000all_l1_data_cache_fills_pti l1_dcache ls_any_fills_from_sys.all / instructions  All L1 data cache fills per thousand instructions  1e3per_1k_instr    000l1_demand_data_cache_fills_from_local_l2_pti l1_dcache ls_dmnd_fills_from_sys.local_l2 / instructions  L1 demand data cache fills from local L2 cache per thousand instructions  1e3per_1k_instr    000l1_demand_data_cache_fills_from_same_ccx_pti l1_dcache ls_dmnd_fills_from_sys.local_ccx / instructions  L1 demand data cache fills from within the same CCX per thousand instructions  1e3per_1k_instr    000l1_demand_data_cache_fills_from_near_cache_pti l1_dcache ls_dmnd_fills_from_sys.near_cache / instructions  L1 demand data cache fills from another CCX cache in the same NUMA node per thousand instructions  1e3per_1k_instr    000l1_demand_data_cache_fills_from_near_memory_pti l1_dcache ls_dmnd_fills_from_sys.dram_io_near / instructions  L1 demand data cache fills from DRAM or MMIO in the same NUMA node per thousand instructions  1e3per_1k_instr    000l1_demand_data_cache_fills_from_far_cache_pti l1_dcache ls_dmnd_fills_from_sys.far_cache / instructions  L1 demand data cache fills from another CCX cache in a different NUMA node per thousand instructions  1e3per_1k_instr    000l1_demand_data_cache_fills_from_far_memory_pti l1_dcache ls_dmnd_fills_from_sys.dram_io_far / instructions  L1 demand data cache fills from DRAM or MMIO in a different NUMA node per thousand instructions  1e3per_1k_instr    000l1_itlb_misses_pti tlb (bp_l1_tlb_miss_l2_tlb_hit + bp_l1_tlb_miss_l2_tlb_miss.all) / instructions  L1 instruction TLB misses per thousand instructions  1e3per_1k_instr    000l2_itlb_misses_pti tlb bp_l1_tlb_miss_l2_tlb_miss.all / instructions  L2 instruction TLB misses and instruction page walks per thousand instructions  1e3per_1k_instr    000l1_dtlb_misses_pti tlb ls_l1_d_tlb_miss.all / instructions  L1 data TLB misses per thousand instructions  1e3per_1k_instr    000l2_dtlb_misses_pti tlb ls_l1_d_tlb_miss.all_l2_miss / instructions  L2 data TLB misses and data page walks per thousand instructions  1e3per_1k_instr    000all_tlbs_flushed_pti tlb ls_tlb_flush.all / instructions  All TLBs flushed per thousand instructions  1e3per_1k_instr    000umc_cas_cmd_rate memory_controller d_ratio(umc_cas_cmd.all * 1e3, umc_mem_clk)  Memory controller CAS command rate  1per_memclk    000umc_activate_cmd_rate memory_controller d_ratio(umc_act_cmd.all * 1e3, umc_mem_clk)  Memory controller ACTIVATE command rate  1per_memclk    000umc_precharge_cmd_rate memory_controller d_ratio(umc_pchg_cmd.all * 1e3, umc_mem_clk)  Memory controller PRECHARGE command rate  1per_memclk    000dram_read_bandwidth_for_local_or_remote_socket data_fabric (local_or_remote_socket_read_data_beats_dram_0 + local_or_remote_socket_read_data_beats_dram_1 + local_or_remote_socket_read_data_beats_dram_2 + local_or_remote_socket_read_data_beats_dram_3 + local_or_remote_socket_read_data_beats_dram_4 + local_or_remote_socket_read_data_beats_dram_5 + local_or_remote_socket_read_data_beats_dram_6 + local_or_remote_socket_read_data_beats_dram_7 + local_or_remote_socket_read_data_beats_dram_8 + local_or_remote_socket_read_data_beats_dram_9 + local_or_remote_socket_read_data_beats_dram_10 + local_or_remote_socket_read_data_beats_dram_11) / duration_time  DRAM read data bandwidth for accesses in local or remote socket  6.4e-5MB/s    000dram_write_bandwidth_for_local_socket data_fabric (local_socket_write_data_beats_dram_0 + local_socket_write_data_beats_dram_1 + local_socket_write_data_beats_dram_2 + local_socket_write_data_beats_dram_3 + local_socket_write_data_beats_dram_4 + local_socket_write_data_beats_dram_5 + local_socket_write_data_beats_dram_6 + local_socket_write_data_beats_dram_7 + local_socket_write_data_beats_dram_8 + local_socket_write_data_beats_dram_9 + local_socket_write_data_beats_dram_10 + local_socket_write_data_beats_dram_11) / duration_time  DRAM write data bandwidth for accesses in local socket  6.4e-5MB/s    000dram_write_bandwidth_for_remote_socket data_fabric (remote_socket_write_data_beats_dram_0 + remote_socket_write_data_beats_dram_1 + remote_socket_write_data_beats_dram_2 + remote_socket_write_data_beats_dram_3 + remote_socket_write_data_beats_dram_4 + remote_socket_write_data_beats_dram_5 + remote_socket_write_data_beats_dram_6 + remote_socket_write_data_beats_dram_7 + remote_socket_write_data_beats_dram_8 + remote_socket_write_data_beats_dram_9 + remote_socket_write_data_beats_dram_10 + remote_socket_write_data_beats_dram_11) / duration_time  DRAM write data bandwidth for accesses in remote socket  6.4e-5MB/s    000dram_write_bandwidth_for_local_or_remote_socket data_fabric (local_or_remote_socket_write_data_beats_dram_0 + local_or_remote_socket_write_data_beats_dram_1 + local_or_remote_socket_write_data_beats_dram_2 + local_or_remote_socket_write_data_beats_dram_3 + local_or_remote_socket_write_data_beats_dram_4 + local_or_remote_socket_write_data_beats_dram_5 + local_or_remote_socket_write_data_beats_dram_6 + local_or_remote_socket_write_data_beats_dram_7 + local_or_remote_socket_write_data_beats_dram_8 + local_or_remote_socket_write_data_beats_dram_9 + local_or_remote_socket_write_data_beats_dram_10 + local_or_remote_socket_write_data_beats_dram_11) / duration_time  DRAM write data bandwidth for accesses in local or remote socket  6.4e-5MB/s    000upstream_dma_read_bandwidth_for_local_socket data_fabric (local_socket_upstream_read_data_beats_io_0 + local_socket_upstream_read_data_beats_io_1 + local_socket_upstream_read_data_beats_io_2 + local_socket_upstream_read_data_beats_io_3 + local_socket_upstream_read_data_beats_io_4 + local_socket_upstream_read_data_beats_io_5 + local_socket_upstream_read_data_beats_io_6 + local_socket_upstream_read_data_beats_io_7) / duration_time  Upstream DMA read data bandwidth for accesses in local socket  6.4e-5MB/s    000upstream_dma_write_bandwidth_for_local_socket data_fabric (local_socket_upstream_write_data_beats_io_0 + local_socket_upstream_write_data_beats_io_1 + local_socket_upstream_write_data_beats_io_2 + local_socket_upstream_write_data_beats_io_3 + local_socket_upstream_write_data_beats_io_4 + local_socket_upstream_write_data_beats_io_5 + local_socket_upstream_write_data_beats_io_6 + local_socket_upstream_write_data_beats_io_7) / duration_time  Upstream DMA write data bandwidth for accesses in local socket  6.4e-5MB/s    000upstream_dma_read_bandwidth_for_remote_socket data_fabric (remote_socket_upstream_read_data_beats_io_0 + remote_socket_upstream_read_data_beats_io_1 + remote_socket_upstream_read_data_beats_io_2 + remote_socket_upstream_read_data_beats_io_3 + remote_socket_upstream_read_data_beats_io_4 + remote_socket_upstream_read_data_beats_io_5 + remote_socket_upstream_read_data_beats_io_6 + remote_socket_upstream_read_data_beats_io_7) / duration_time  Upstream DMA read data bandwidth for accesses in remote socket  6.4e-5MB/s    000upstream_dma_write_bandwidth_for_remote_socket data_fabric (remote_socket_upstream_write_data_beats_io_0 + remote_socket_upstream_write_data_beats_io_1 + remote_socket_upstream_write_data_beats_io_2 + remote_socket_upstream_write_data_beats_io_3 + remote_socket_upstream_write_data_beats_io_4 + remote_socket_upstream_write_data_beats_io_5 + remote_socket_upstream_write_data_beats_io_6 + remote_socket_upstream_write_data_beats_io_7) / duration_time  Upstream DMA write data bandwidth for accesses in remote socket  6.4e-5MB/s    000core_inbound_data_bandwidth_for_local_socket data_fabric (local_socket_inbound_data_beats_cfi_0 + local_socket_inbound_data_beats_cfi_1 + local_socket_inbound_data_beats_cfi_2 + local_socket_inbound_data_beats_cfi_3 + local_socket_inbound_data_beats_cfi_4 + local_socket_inbound_data_beats_cfi_5 + local_socket_inbound_data_beats_cfi_6 + local_socket_inbound_data_beats_cfi_7 + local_socket_inbound_data_beats_cfi_8 + local_socket_inbound_data_beats_cfi_9 + local_socket_inbound_data_beats_cfi_10 + local_socket_inbound_data_beats_cfi_11 + local_socket_inbound_data_beats_cfi_12 + local_socket_inbound_data_beats_cfi_13 + local_socket_inbound_data_beats_cfi_14 + local_socket_inbound_data_beats_cfi_15) / duration_time  Core inbound data bandwidth for accesses in local socket  3.2e-5MB/s    000core_outbound_data_bandwidth_for_local_socket data_fabric (local_socket_outbound_data_beats_cfi_0 + local_socket_outbound_data_beats_cfi_1 + local_socket_outbound_data_beats_cfi_2 + local_socket_outbound_data_beats_cfi_3 + local_socket_outbound_data_beats_cfi_4 + local_socket_outbound_data_beats_cfi_5 + local_socket_outbound_data_beats_cfi_6 + local_socket_outbound_data_beats_cfi_7 + local_socket_outbound_data_beats_cfi_8 + local_socket_outbound_data_beats_cfi_9 + local_socket_outbound_data_beats_cfi_10 + local_socket_outbound_data_beats_cfi_11 + local_socket_outbound_data_beats_cfi_12 + local_socket_outbound_data_beats_cfi_13 + local_socket_outbound_data_beats_cfi_14 + local_socket_outbound_data_beats_cfi_15) / duration_time  Core outbound data bandwidth for accesses in local socket  6.4e-5MB/s    000core_inbound_data_bandwidth_for_remote_socket data_fabric (remote_socket_inbound_data_beats_cfi_0 + remote_socket_inbound_data_beats_cfi_1 + remote_socket_inbound_data_beats_cfi_2 + remote_socket_inbound_data_beats_cfi_3 + remote_socket_inbound_data_beats_cfi_4 + remote_socket_inbound_data_beats_cfi_5 + remote_socket_inbound_data_beats_cfi_6 + remote_socket_inbound_data_beats_cfi_7 + remote_socket_inbound_data_beats_cfi_8 + remote_socket_inbound_data_beats_cfi_9 + remote_socket_inbound_data_beats_cfi_10 + remote_socket_inbound_data_beats_cfi_11 + remote_socket_inbound_data_beats_cfi_12 + remote_socket_inbound_data_beats_cfi_13 + remote_socket_inbound_data_beats_cfi_14 + remote_socket_inbound_data_beats_cfi_15) / duration_time  Core inbound data bandwidth for accesses in remote socket  3.2e-5MB/s    000core_outbound_data_bandwidth_for_remote_socket data_fabric (remote_socket_outbound_data_beats_cfi_0 + remote_socket_outbound_data_beats_cfi_1 + remote_socket_outbound_data_beats_cfi_2 + remote_socket_outbound_data_beats_cfi_3 + remote_socket_outbound_data_beats_cfi_4 + remote_socket_outbound_data_beats_cfi_5 + remote_socket_outbound_data_beats_cfi_6 + remote_socket_outbound_data_beats_cfi_7 + remote_socket_outbound_data_beats_cfi_8 + remote_socket_outbound_data_beats_cfi_9 + remote_socket_outbound_data_beats_cfi_10 + remote_socket_outbound_data_beats_cfi_11 + remote_socket_outbound_data_beats_cfi_12 + remote_socket_outbound_data_beats_cfi_13 + remote_socket_outbound_data_beats_cfi_14 + remote_socket_outbound_data_beats_cfi_15) / duration_time  Core outbound data bandwidth for accesses in remote socket  6.4e-5MB/s    000cross_socket_inbound_data_bandwidth_for_local_socket data_fabric (local_socket_inbound_data_beats_link_0 + local_socket_inbound_data_beats_link_1 + local_socket_inbound_data_beats_link_2 + local_socket_inbound_data_beats_link_3 + local_socket_inbound_data_beats_link_4 + local_socket_inbound_data_beats_link_5) / duration_time  Inbound data bandwidth for accesses between local socket and remote socket  6.4e-5MB/s    000cross_socket_outbound_data_bandwidth_for_local_socket data_fabric (local_socket_outbound_data_beats_link_0 + local_socket_outbound_data_beats_link_1 + local_socket_outbound_data_beats_link_2 + local_socket_outbound_data_beats_link_3 + local_socket_outbound_data_beats_link_4 + local_socket_outbound_data_beats_link_5) / duration_time  Outbound data bandwidth for accesses between local socket and remote socket  6.4e-5MB/s    000lpm_br_cond_insn_between_branches lpm_br;lpm_br_cond d_ratio(instructions, ex_ret_brn_cond)  The number of instructions divided by the number of conditional branches  1insn    000lpm_br_cond_retired lpm_br;lpm_br_cond d_ratio(ex_ret_brn_cond, duration_time)  Retired conditional branch instructions  1insn/s    000lpm_br_total_insn_fe_resteers lpm_br;lpm_br_total d_ratio(ex_ret_brn_cond_misp, duration_time)  The number of resync branches per second  1req/s    000lpm_cs_loads lpm_cs d_ratio(ls_dispatch.pure_ld, context\-switches)  Loads per context switch  1loads/cs    000lpm_cs_stores lpm_cs d_ratio(ls_dispatch.pure_st, context\-switches)  Stores per context switch  1stores/cs    000lpm_ldst_insn_bt_ld lpm_ldst;lpm_ldst_insn_bt d_ratio(instructions, ls_dispatch.pure_ld)  Number of instructions between loads  1insns    000lpm_ldst_insn_bt_st lpm_ldst;lpm_ldst_insn_bt d_ratio(instructions, ls_dispatch.pure_st)  Number of instructions between stores  1insns    000lpm_ldst_percent_insn_ld lpm_ldst;lpm_ldst_percent_insn d_ratio(ls_dispatch.pure_ld, instructions)  Load instructions as a percentage of all instructions  100%    000lpm_ldst_percent_insn_st lpm_ldst;lpm_ldst_percent_insn d_ratio(ls_dispatch.pure_st, instructions)  Store instructions as a percentage of all instructions  100%    000lpm_ldst_ret_loads_per_cycle_1 lpm_ldst;lpm_ldst_ret_loads_per_cycle d_ratio(max(ls_dispatch.pure_ld@cmask\=1@ - ls_dispatch.pure_ld@cmask\=2@, 0), ls_not_halted_cyc)  Load instructions retiring in 1 cycle as a percentage of all unhalted cycles  100%    000lpm_ldst_ret_loads_per_cycle_2 lpm_ldst;lpm_ldst_ret_loads_per_cycle d_ratio(max(ls_dispatch.pure_ld@cmask\=2@ - ls_dispatch.pure_ld@cmask\=3@, 0), ls_not_halted_cyc)  Load instructions retiring in 2 cycles as a percentage of all unhalted cycles  100%    000lpm_ldst_ret_loads_per_cycle_3 lpm_ldst;lpm_ldst_ret_loads_per_cycle d_ratio(ls_dispatch.pure_ld@cmask\=3@, ls_not_halted_cyc)  Load instructions retiring in 3 or more cycles as a percentageof all unhalted cycles  100%    000lpm_ldst_ret_stores_per_cycle_1 lpm_ldst;lpm_ldst_ret_stores_per_cycle d_ratio(max(ls_dispatch.pure_st@cmask\=1@ - ls_dispatch.pure_st@cmask\=2@, 0), ls_not_halted_cyc)  Store instructions retiring in 1 cycle as a percentage of all unhalted cycles  100%    000lpm_ldst_ret_stores_per_cycle_2 lpm_ldst;lpm_ldst_ret_stores_per_cycle d_ratio(max(ls_dispatch.pure_st@cmask\=2@ - ls_dispatch.pure_st@cmask\=3@, 0), ls_not_halted_cyc)  Store instructions retiring in 2 cycles as a percentage of all unhalted cycles  100%    000lpm_ldst_ret_stores_per_cycle_3 lpm_ldst;lpm_ldst_ret_stores_per_cycle d_ratio(ls_dispatch.pure_st@cmask\=3@, ls_not_halted_cyc)  Store instructions retiring in 3 or more cycles as a percentageof all unhalted cycles  100%    000lpm_ldst_total_ld lpm_ldst;lpm_ldst_total d_ratio(ls_dispatch.pure_ld, duration_time)  Number of loads dispatched per second  1insns per sec    000lpm_ldst_total_st lpm_ldst;lpm_ldst_total d_ratio(ls_dispatch.pure_st, duration_time)  Number of stores dispatched per second  1insns per sec    000bad_speculation_from_mispredicts PipelineL2;bad_speculation_group d_ratio(bad_speculation * ex_ret_brn_misp, ex_ret_brn_misp + bp_fe_redir.resync)  Percentage of dispatched ops that were flushed due to branch mispredicts  100%ops    000bad_speculation_from_pipeline_restarts PipelineL2;bad_speculation_group d_ratio(bad_speculation * bp_fe_redir.resync, ex_ret_brn_misp + bp_fe_redir.resync)  Percentage of dispatched ops that were flushed due to pipeline restarts (resyncs)  100%ops    000all_l2_cache_accesses_pti l2_cache (l2_request_g1.no_pf_all + l2_pf_hit_l2.l2_hwpf + l2_pf_miss_l2_hit_l3.l2_hwpf + l2_pf_miss_l2_l3.l2_hwpf) / instructions  All L2 cache accesses per thousand instructions  1e3per_1k_instr    000l2_cache_accesses_from_l1_dc_misses_pti l2_cache l2_request_g1.dc_all / instructions  L2 cache accesses from L1 data cache misses (including prefetch) per thousand instructions  1e3per_1k_instr    000op_cache_fetch_miss_ratio  d_ratio(op_cache_hit_miss.miss, op_cache_hit_miss.all)  Op cache miss ratio for all fetches  100%    000l2_dtlb_misses_pti tlb ls_l1_d_tlb_miss.l2_miss_all / instructions  L2 data TLB misses and data page walks per thousand instructions  1e3per_1k_instr    000tma_backend_bound Default;TopdownL1;tma_L1_group cpu_atom@TOPDOWN_BE_BOUND.ALL_P@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_backend_bound > 0.1 Counts the total number of issue slots that were not consumed by the backend due to backend stalls Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count 100%  TopdownL1;Default TopdownL1 000tma_bad_speculation Default;TopdownL1;tma_L1_group cpu_atom@TOPDOWN_BAD_SPECULATION.ALL_P@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_bad_speculation > 0.15 Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear 100%  TopdownL1;Default TopdownL1 000tma_branch_detect TopdownL3;tma_L3_group;tma_ifetch_latency_group cpu_atom@TOPDOWN_FE_BOUND.BRANCH_DETECT@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_branch_detect > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches 100%    000tma_branch_mispredicts TopdownL2;tma_L2_group;tma_bad_speculation_group cpu_atom@TOPDOWN_BAD_SPECULATION.MISPREDICT@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_branch_mispredicts > 0.05 & tma_bad_speculation > 0.15 Counts the number of issue slots that were not consumed by the backend due to branch mispredicts  100%  TopdownL2  000tma_branch_resteer TopdownL3;tma_L3_group;tma_ifetch_latency_group cpu_atom@TOPDOWN_FE_BOUND.BRANCH_RESTEER@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_branch_resteer > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch  100%    000tma_cisc TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group cpu_atom@TOPDOWN_FE_BOUND.CISC@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_cisc > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to the microcode sequencer (MS)  100%    000tma_core_bound TopdownL2;tma_L2_group;tma_backend_bound_group cpu_atom@TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_core_bound > 0.1 & tma_backend_bound > 0.1 Counts the number of cycles due to backend bound stalls that are bounded by core restrictions and not attributed to an outstanding load or stores, or resource limitation  100%  TopdownL2  000tma_decode TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group cpu_atom@TOPDOWN_FE_BOUND.DECODE@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_decode > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to decode stalls  100%    000tma_fast_nuke TopdownL3;tma_L3_group;tma_machine_clears_group cpu_atom@TOPDOWN_BAD_SPECULATION.FASTNUKE@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_fast_nuke > 0.05 & (tma_machine_clears > 0.05 & tma_bad_speculation > 0.15) Counts the number of issue slots that were not consumed by the backend due to a machine clear that does not require the use of microcode, classified as a fast nuke, due to memory ordering, memory disambiguation and memory renaming  100%    000tma_frontend_bound Default;TopdownL1;tma_L1_group cpu_atom@TOPDOWN_FE_BOUND.ALL@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_frontend_bound > 0.2 Counts the number of issue slots that were not consumed by the backend due to frontend stalls  100%  TopdownL1;Default TopdownL1 000tma_icache_misses TopdownL3;tma_L3_group;tma_ifetch_latency_group cpu_atom@TOPDOWN_FE_BOUND.ICACHE@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_icache_misses > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to instruction cache misses  100%    000tma_ifetch_bandwidth TopdownL2;tma_L2_group;tma_frontend_bound_group cpu_atom@TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2 Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations  100%  TopdownL2  000tma_ifetch_latency TopdownL2;tma_L2_group;tma_frontend_bound_group cpu_atom@TOPDOWN_FE_BOUND.FRONTEND_LATENCY@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2 Counts the number of issue slots that were not delivered by the frontend due to frontend latency restrictions due to icache misses, itlb misses, branch detection, and resteer limitations  100%  TopdownL2  000tma_info_arith_inst_mix_ipflop Flops cpu_atom@INST_RETIRED.ANY@ / cpu_atom@FP_FLOPS_RETIRED.ALL@  Instructions per Floating Point (FP) Operation      000tma_info_arith_inst_mix_ipfparith Flops cpu_atom@INST_RETIRED.ANY@ / cpu_atom@FP_INST_RETIRED.ALL@  Instructions per FP Arithmetic instruction      000tma_info_arith_inst_mix_ipfparith_avx128 Flops cpu_atom@INST_RETIRED.ANY@ / (cpu_atom@FP_INST_RETIRED.128B_DP@ + cpu_atom@FP_INST_RETIRED.128B_SP@)  Instructions per FP Arithmetic AVX/SSE 128-bit instruction      000tma_info_arith_inst_mix_ipfparith_avx256 Flops cpu_atom@INST_RETIRED.ANY@ / (cpu_atom@FP_INST_RETIRED.256B_DP@ + cpu_atom@FP_INST_RETIRED.256B_SP@)  Instructions per FP Arithmetic AVX 256-bit instruction      000tma_info_arith_inst_mix_ipfparith_scalar_dp Flops cpu_atom@INST_RETIRED.ANY@ / cpu_atom@FP_INST_RETIRED.64B_DP@  Instructions per FP Arithmetic Scalar Double-Precision instruction      000tma_info_arith_inst_mix_ipfparith_scalar_sp Flops cpu_atom@INST_RETIRED.ANY@ / cpu_atom@FP_INST_RETIRED.32B_SP@  Instructions per FP Arithmetic Scalar Single-Precision instruction      000tma_info_bottleneck_%_ifetch_miss_bound_cycles Ifetch 100 * cpu_atom@MEM_BOUND_STALLS_IFETCH.ALL@ / cpu_atom@CPU_CLK_UNHALTED.CORE@  Percentage of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icache or ITLB Miss Percentage of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icache or ITLB Miss. See Info.Ifetch_Bound     000tma_info_bottleneck_%_load_miss_bound_cycles Load_Store_Miss 100 * cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@ / cpu_atom@CPU_CLK_UNHALTED.CORE@  Percentage of time that retirement is stalled due to an L1 miss Percentage of time that retirement is stalled due to an L1 miss. See Info.Load_Miss_Bound     000tma_info_br_inst_mix_ipcall  cpu_atom@INST_RETIRED.ANY@ / cpu_atom@BR_INST_RETIRED.NEAR_CALL@  Instruction per (near) call (lower number means higher occurrence rate)      000tma_info_core_flopc Flops cpu_atom@FP_FLOPS_RETIRED.ALL@ / cpu_atom@CPU_CLK_UNHALTED.CORE@  Floating Point Operations Per Cycle      000tma_info_core_upi  cpu_atom@TOPDOWN_RETIRING.ALL@ / cpu_atom@INST_RETIRED.ANY@  Uops Per Instruction      000tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l2hit  100 * cpu_atom@MEM_BOUND_STALLS_IFETCH.L2_HIT@ / cpu_atom@MEM_BOUND_STALLS_IFETCH.ALL@  Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L2      000tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l2miss  100 * cpu_atom@MEM_BOUND_STALLS_IFETCH.L2_MISS@ / cpu_atom@MEM_BOUND_STALLS_IFETCH.ALL@  Percentage of ifetch miss bound stalls, where the ifetch miss doesn't hit in the L2      000tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l3hit  100 * cpu_atom@MEM_BOUND_STALLS_IFETCH.LLC_HIT@ / cpu_atom@MEM_BOUND_STALLS_IFETCH.ALL@  Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L3      000tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l3miss  100 * (cpu_atom@MEM_BOUND_STALLS_IFETCH.L2_MISS@ - cpu_atom@MEM_BOUND_STALLS_IFETCH.LLC_HIT@) / cpu_atom@MEM_BOUND_STALLS_IFETCH.ALL@  Percentage of ifetch miss bound stalls, where the ifetch miss subsequently misses in the L3      000tma_info_load_miss_bound_%_loadmissbound_with_l2hit load_store_bound 100 * cpu_atom@MEM_BOUND_STALLS_LOAD.L2_HIT@ / cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@  Percentage of memory bound stalls where retirement is stalled due to an L1 miss that hit the L2      000tma_info_load_miss_bound_%_loadmissbound_with_l2miss load_store_bound 100 * cpu_atom@MEM_BOUND_STALLS_LOAD.L2_MISS@ / cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@  Percentage of memory bound stalls where retirement is stalled due to an L1 miss that subsequently misses in the L2      000tma_info_load_miss_bound_%_loadmissbound_with_l3hit load_store_bound 100 * cpu_atom@MEM_BOUND_STALLS_LOAD.LLC_HIT@ / cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@  Percentage of memory bound stalls where retirement is stalled due to an L1 miss that hit the L3      000tma_info_load_miss_bound_%_loadmissbound_with_l3miss load_store_bound 100 * (cpu_atom@MEM_BOUND_STALLS_LOAD.L2_MISS@ - cpu_atom@MEM_BOUND_STALLS_LOAD.LLC_HIT@) / cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@  Percentage of memory bound stalls where retirement is stalled due to an L1 miss that subsequently misses the L3      000tma_info_load_store_bound_load_bound load_store_bound 100 * (cpu_atom@LD_HEAD.L1_BOUND_AT_RET@ + cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@) / cpu_atom@CPU_CLK_UNHALTED.CORE@  Counts the number of cycles that the oldest load of the load buffer is stalled at retirement      000tma_info_mem_exec_blocks_%_loads_with_adressaliasing  100 * cpu_atom@LD_BLOCKS.ADDRESS_ALIAS@ / cpu_atom@MEM_UOPS_RETIRED.ALL_LOADS@  Percentage of total non-speculative loads with an address aliasing block      000tma_info_mem_mix_memload_ratio  1e3 * cpu_atom@MEM_UOPS_RETIRED.ALL_LOADS@ / cpu_atom@TOPDOWN_RETIRING.ALL@  Ratio of mem load uops to all uops      000tma_info_serialization_%_tpause_cycles  100 * cpu_atom@SERIALIZATION.C01_MS_SCB@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@)  Percentage of time that the core is stalled due to a TPAUSE or UMWAIT instruction      000tma_info_system_gflops Flops cpu_atom@FP_FLOPS_RETIRED.ALL@ / (duration_time * 1e9)  Giga Floating Point Operations Per Second Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width     000tma_info_uop_mix_fpdiv_uop_ratio  100 * cpu_atom@UOPS_RETIRED.FPDIV@ / cpu_atom@TOPDOWN_RETIRING.ALL@  Percentage of all uops which are FPDiv uops      000tma_info_uop_mix_idiv_uop_ratio  100 * cpu_atom@UOPS_RETIRED.IDIV@ / cpu_atom@TOPDOWN_RETIRING.ALL@  Percentage of all uops which are IDiv uops      000tma_info_uop_mix_microcode_uop_ratio  100 * cpu_atom@UOPS_RETIRED.MS@ / cpu_atom@TOPDOWN_RETIRING.ALL@  Percentage of all uops which are microcode ops      000tma_info_uop_mix_x87_uop_ratio  100 * cpu_atom@UOPS_RETIRED.X87@ / cpu_atom@TOPDOWN_RETIRING.ALL@  Percentage of all uops which are x87 uops      000tma_itlb_misses TopdownL3;tma_L3_group;tma_ifetch_latency_group cpu_atom@TOPDOWN_FE_BOUND.ITLB_MISS@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_itlb_misses > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses  100%    000tma_machine_clears TopdownL2;tma_L2_group;tma_bad_speculation_group cpu_atom@TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_machine_clears > 0.05 & tma_bad_speculation > 0.15 Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation  100%  TopdownL2  000tma_mem_scheduler TopdownL3;tma_L3_group;tma_resource_bound_group cpu_atom@TOPDOWN_BE_BOUND.MEM_SCHEDULER@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_mem_scheduler > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops  100%    000tma_non_mem_scheduler TopdownL3;tma_L3_group;tma_resource_bound_group cpu_atom@TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_non_mem_scheduler > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops  100%    000tma_nuke TopdownL3;tma_L3_group;tma_machine_clears_group cpu_atom@TOPDOWN_BAD_SPECULATION.NUKE@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_nuke > 0.05 & (tma_machine_clears > 0.05 & tma_bad_speculation > 0.15) Counts the number of issue slots that were not consumed by the backend due to a machine clear that requires the use of microcode (slow nuke)  100%    000tma_other_fb TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group cpu_atom@TOPDOWN_FE_BOUND.OTHER@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_other_fb > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to other common frontend stalls not categorized  100%    000tma_predecode TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group cpu_atom@TOPDOWN_FE_BOUND.PREDECODE@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_predecode > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to wrong predecodes  100%    000tma_register TopdownL3;tma_L3_group;tma_resource_bound_group cpu_atom@TOPDOWN_BE_BOUND.REGISTER@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_register > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls)  100%    000tma_reorder_buffer TopdownL3;tma_L3_group;tma_resource_bound_group cpu_atom@TOPDOWN_BE_BOUND.REORDER_BUFFER@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_reorder_buffer > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to the reorder buffer being full (ROB stalls)  100%    000tma_retiring Default;TopdownL1;tma_L1_group cpu_atom@TOPDOWN_RETIRING.ALL@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_retiring > 0.75 Counts the number of issue slots that result in retirement slots  100%  TopdownL1;Default TopdownL1 000tma_serialization TopdownL3;tma_L3_group;tma_resource_bound_group cpu_atom@TOPDOWN_BE_BOUND.SERIALIZATION@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_serialization > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS)  100%    000tma_alu_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group cpu_core@UOPS_DISPATCHED.ALU@ / (6 * tma_info_thread_clks) tma_alu_op_utilization > 0.4 This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations  100%    000tma_bad_speculation Default;TmaL1;TopdownL1;tma_L1_group cpu_core@topdown\-bad\-spec@ / (cpu_core@topdown\-fe\-bound@ + cpu_core@topdown\-bad\-spec@ + cpu_core@topdown\-retiring@ + cpu_core@topdown\-be\-bound@) tma_bad_speculation > 0.15 This category represents fraction of slots wasted due to incorrect speculations This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example 100%  TopdownL1;Default TopdownL1 000tma_bottleneck_data_cache_memory_bandwidth BvMB;Mem;MemoryBW;Offcore;tma_issueBW 100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_fb_full / (tma_dtlb_load + tma_fb_full + tma_l1_latency_capacity + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_early_blk + tma_store_fwd_blk))) tma_bottleneck_data_cache_memory_bandwidth > 20 Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full     000tma_bottleneck_data_cache_memory_latency BvML;Mem;MemoryLat;Offcore;tma_issueLat 100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l1_latency_dependency / (tma_dtlb_load + tma_fb_full + tma_l1_latency_capacity + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_early_blk + tma_store_fwd_blk)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l1_latency_capacity / (tma_dtlb_load + tma_fb_full + tma_l1_latency_capacity + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_early_blk + tma_store_fwd_blk)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_lock_latency / (tma_dtlb_load + tma_fb_full + tma_l1_latency_capacity + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_early_blk + tma_store_fwd_blk)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_split_loads / (tma_dtlb_load + tma_fb_full + tma_l1_latency_capacity + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_early_blk + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_split_stores / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) tma_bottleneck_data_cache_memory_latency > 20 Total pipeline cost of external Memory- or Cache-Latency related bottlenecks Total pipeline cost of external Memory- or Cache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_mem_latency     000tma_bottleneck_irregular_overhead Bad;BvIO;Cor;Ret;tma_issueMS 100 * ((1 - cpu_core@INST_RETIRED.REP_ITERATION@ / cpu_core@UOPS_RETIRED.MS\,cmask\=1@) * (tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_ms) + 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts * tma_branch_mispredicts + tma_machine_clears * tma_other_nukes / tma_other_nukes + tma_core_bound * (tma_serializing_operation + cpu_core@RS.EMPTY_RESOURCE@ / tma_info_thread_clks * tma_ports_utilized_0) / (tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_microcode_sequencer / (tma_microcode_sequencer + tma_few_uops_instructions) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations) tma_bottleneck_irregular_overhead > 10 Total pipeline cost of irregular execution (e.g Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloads, overhead in system services or virtualized environments). Related metrics: tma_microcode_sequencer, tma_ms_switches     000tma_bottleneck_memory_data_tlbs BvMT;Mem;MemoryTLB;Offcore;tma_issueTLB 100 * (tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_load / (tma_dtlb_load + tma_fb_full + tma_l1_latency_capacity + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_early_blk + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) tma_bottleneck_memory_data_tlbs > 20 Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs) Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store     000tma_bottleneck_useful_work BvUW;Ret 100 * (tma_retiring - (cpu_core@BR_INST_RETIRED.ALL_BRANCHES@ + 2 * cpu_core@BR_INST_RETIRED.NEAR_CALL@ + cpu_core@INST_RETIRED.NOP@) / tma_info_thread_slots - tma_microcode_sequencer / (tma_microcode_sequencer + tma_few_uops_instructions) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations) tma_bottleneck_useful_work > 20 Total pipeline cost of "useful operations" - the portion of Retiring category not covered by Branching_Overhead nor Irregular_Overhead      000tma_cisc TopdownL4;tma_L4_group;tma_microcode_sequencer_group max(0, tma_microcode_sequencer - tma_assists) tma_cisc > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1) This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources 100%    000tma_code_l2_hit FetchLat;IcMiss;Offcore;TopdownL4;tma_L4_group;tma_icache_misses_group max(0, cpu_core@FRONTEND_RETIRED.L1I_MISS@ * cpu_core@FRONTEND_RETIRED.L1I_MISS@R / tma_info_thread_clks - tma_code_l2_miss) tma_code_l2_hit > 0.05 & (tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric estimates fraction of cycles the CPU was stalled due to instruction cache misses that hit in the L2 cache  100%    000tma_code_l2_miss FetchLat;IcMiss;Offcore;TopdownL4;tma_L4_group;tma_icache_misses_group cpu_core@FRONTEND_RETIRED.L2_MISS@ * cpu_core@FRONTEND_RETIRED.L2_MISS@R / tma_info_thread_clks tma_code_l2_miss > 0.05 & (tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric estimates fraction of cycles the CPU was stalled due to instruction cache misses that miss in the L2 cache  100%    000tma_code_stlb_hit FetchLat;MemoryTLB;TopdownL4;tma_L4_group;tma_itlb_misses_group max(0, cpu_core@FRONTEND_RETIRED.ITLB_MISS@ * cpu_core@FRONTEND_RETIRED.ITLB_MISS@R / tma_info_thread_clks - tma_code_stlb_miss) tma_code_stlb_hit > 0.05 & (tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric roughly estimates the fraction of cycles where the (first level) ITLB was missed by instructions fetches, that later on hit in second-level TLB (STLB)  100%    000tma_code_stlb_miss FetchLat;MemoryTLB;TopdownL4;tma_L4_group;tma_itlb_misses_group cpu_core@FRONTEND_RETIRED.STLB_MISS@ * cpu_core@FRONTEND_RETIRED.STLB_MISS@R / tma_info_thread_clks tma_code_stlb_miss > 0.05 & (tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by instruction fetches, performing a hardware page walk  100%    000tma_code_stlb_miss_2m FetchLat;MemoryTLB;TopdownL5;tma_L5_group;tma_code_stlb_miss_group cpu_core@ITLB_MISSES.WALK_ACTIVE@ / tma_info_thread_clks * cpu_core@ITLB_MISSES.WALK_COMPLETED_2M_4M@ / (cpu_core@ITLB_MISSES.WALK_COMPLETED_4K@ + cpu_core@ITLB_MISSES.WALK_COMPLETED_2M_4M@) tma_code_stlb_miss_2m > 0.05 & (tma_code_stlb_miss > 0.05 & (tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))) This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 2 or 4 MB pages for (instruction) code accesses  100%    000tma_code_stlb_miss_4k FetchLat;MemoryTLB;TopdownL5;tma_L5_group;tma_code_stlb_miss_group cpu_core@ITLB_MISSES.WALK_ACTIVE@ / tma_info_thread_clks * cpu_core@ITLB_MISSES.WALK_COMPLETED_4K@ / (cpu_core@ITLB_MISSES.WALK_COMPLETED_4K@ + cpu_core@ITLB_MISSES.WALK_COMPLETED_2M_4M@) tma_code_stlb_miss_4k > 0.05 & (tma_code_stlb_miss > 0.05 & (tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))) This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 4 KB pages for (instruction) code accesses  100%    000tma_cond_nt_mispredicts BrMispredicts;TopdownL3;tma_L3_group;tma_branch_mispredicts_group cpu_core@BR_MISP_RETIRED.COND_NTAKEN_COST@ * cpu_core@BR_MISP_RETIRED.COND_NTAKEN_COST@R / tma_info_thread_clks tma_cond_nt_mispredicts > 0.05 & (tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15) This metric represents fraction of cycles the CPU was stalled due to retired misprediction by non-taken conditional branches  100%    000tma_cond_tk_bwd_mispredicts BrMispredicts;TopdownL3;tma_L3_group;tma_branch_mispredicts_group cpu_core@BR_MISP_RETIRED.COND_TAKEN_BWD_COST@ * cpu_core@BR_MISP_RETIRED.COND_TAKEN_BWD_COST@R / tma_info_thread_clks tma_cond_tk_bwd_mispredicts > 0.05 & (tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15) This metric represents fraction of cycles the CPU was stalled due to misprediction by backward-taken conditional branches  100%    000tma_cond_tk_fwd_mispredicts BrMispredicts;TopdownL3;tma_L3_group;tma_branch_mispredicts_group cpu_core@BR_MISP_RETIRED.COND_TAKEN_FWD_COST@ * cpu_core@BR_MISP_RETIRED.COND_TAKEN_FWD_COST@R / tma_info_thread_clks tma_cond_tk_fwd_mispredicts > 0.05 & (tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15) This metric represents fraction of cycles the CPU was stalled due to misprediction by forward-taken conditional branches  100%    000tma_contested_accesses BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS@ * min(cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS@R, 24 * tma_info_system_core_frequency) + cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM@ * min(cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM@R, 25 * tma_info_system_core_frequency)) * (1 + cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / 2) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS. Related metrics: tma_bottleneck_memory_synchronization, tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100%    000tma_data_sharing BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD@ * min(cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD@R, 24 * tma_info_system_core_frequency) + cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD@ * min(cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD@R, 25 * tma_info_system_core_frequency)) * (1 + cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / 2) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD. Related metrics: tma_bottleneck_memory_synchronization, tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100%    010tma_divider BvCB;TopdownL3;tma_L3_group;tma_core_bound_group cpu_core@ARITH.DIV_ACTIVE@ / tma_info_thread_clks tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric represents fraction of cycles where the Divider unit was active This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIV_ACTIVE 100%    000tma_dram_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group cpu_core@MEMORY_STALLS.MEM@ / tma_info_thread_clks tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS 100%    000tma_dsb DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group (cpu_core@IDQ.DSB_UOPS\,cmask\=0x8\,inv\=0x1@ / 2 + cpu_core@IDQ.DSB_UOPS@ / (cpu_core@IDQ.DSB_UOPS@ + cpu_core@IDQ.MITE_UOPS@) * (cpu_core@IDQ_BUBBLES.STARVATION_CYCLES@ - cpu_core@IDQ_BUBBLES.FETCH_LATENCY@)) / tma_info_thread_clks tma_dsb > 0.15 & tma_fetch_bandwidth > 0.2 This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline.  For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here 100%    000tma_dtlb_load BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group cpu_core@MEM_INST_RETIRED.STLB_HIT_LOADS@ * min(cpu_core@MEM_INST_RETIRED.STLB_HIT_LOADS@R, 7) / tma_info_thread_clks + tma_load_stlb_miss tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_bottleneck_memory_data_tlbs, tma_dtlb_store 100%    000tma_dtlb_store BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group cpu_core@MEM_INST_RETIRED.STLB_HIT_STORES@ * min(cpu_core@MEM_INST_RETIRED.STLB_HIT_STORES@R, 7) / tma_info_thread_clks + tma_store_stlb_miss tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses.  As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead.  Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page.  Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_bottleneck_memory_data_tlbs, tma_dtlb_load 100%    000tma_fb_full BvMB;MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group cpu_core@L1D_MISS.FB_FULL@ / tma_info_thread_clks tma_fb_full > 0.3 This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_bottleneck_data_cache_memory_bandwidth, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores 100%    000tma_fetch_latency Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group cpu_core@topdown\-fetch\-lat@ / (cpu_core@topdown\-fe\-bound@ + cpu_core@topdown\-bad\-spec@ + cpu_core@topdown\-retiring@ + cpu_core@topdown\-be\-bound@) tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15 This metric represents fraction of slots the CPU was stalled due to Frontend latency issues This metric represents fraction of slots the CPU was stalled due to Frontend latency issues.  For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS 100%  TopdownL2  000tma_fp_scalar Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P cpu_core@FP_ARITH_OPS_RETIRED.SCALAR@ / (tma_retiring * tma_info_thread_slots) tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_fp_vector Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P cpu_core@FP_ARITH_OPS_RETIRED.VECTOR@ / (tma_retiring * tma_info_thread_slots) tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_fp_vector_128b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (cpu_core@FP_ARITH_OPS_RETIRED.128B_PACKED_DOUBLE@ + cpu_core@FP_ARITH_OPS_RETIRED.128B_PACKED_SINGLE@) / (tma_retiring * tma_info_thread_slots) tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting prior to LNL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_fp_vector_256b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P cpu_core@FP_ARITH_OPS_RETIRED.VECTOR\,umask\=0x30@ / (tma_retiring * tma_info_thread_slots) tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting prior to LNL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_frontend_bound BvFB;BvIO;Default;PGO;TmaL1;TopdownL1;tma_L1_group cpu_core@topdown\-fe\-bound@ / (cpu_core@topdown\-fe\-bound@ + cpu_core@topdown\-bad\-spec@ + cpu_core@topdown\-retiring@ + cpu_core@topdown\-be\-bound@) tma_frontend_bound > 0.15 This category represents fraction of slots where the processor's Frontend undersupplies its Backend This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS 100%  TopdownL1;Default TopdownL1 000tma_ind_call_mispredicts BrMispredicts;TopdownL3;tma_L3_group;tma_branch_mispredicts_group cpu_core@BR_MISP_RETIRED.INDIRECT_CALL_COST@ * cpu_core@BR_MISP_RETIRED.INDIRECT_CALL_COST@R / tma_info_thread_clks tma_ind_call_mispredicts > 0.05 & (tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15) This metric represents fraction of cycles the CPU was stalled due to retired misprediction by indirect CALL instructions  100%    000tma_ind_jump_mispredicts BrMispredicts;TopdownL3;tma_L3_group;tma_branch_mispredicts_group max((cpu_core@BR_MISP_RETIRED.INDIRECT_COST@ * cpu_core@BR_MISP_RETIRED.INDIRECT_COST@R - cpu_core@BR_MISP_RETIRED.INDIRECT_CALL_COST@ * cpu_core@BR_MISP_RETIRED.INDIRECT_CALL_COST@R) / tma_info_thread_clks, 0) tma_ind_jump_mispredicts > 0.05 & (tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15) This metric represents fraction of cycles the CPU was stalled due to retired misprediction by indirect JMP instructions  100%    000tma_info_bad_spec_branch_misprediction_cost Bad;BrMispredicts;tma_issueBM tma_bottleneck_mispredictions * tma_info_thread_slots / 8 / cpu_core@BR_MISP_RETIRED.ALL_BRANCHES@ / 100  Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear) Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_bottleneck_mispredictions, tma_branch_mispredicts, tma_mispredicts_resteers     000tma_info_bad_spec_ipmisp_cond_taken_bwd Bad;BrMispredicts cpu_core@INST_RETIRED.ANY@ / cpu_core@BR_MISP_RETIRED.COND_TAKEN_BWD@  Instructions per retired Mispredicts for conditional backward-taken branches (lower number means higher occurrence rate)      000tma_info_bad_spec_ipmisp_cond_taken_fwd Bad;BrMispredicts cpu_core@INST_RETIRED.ANY@ / cpu_core@BR_MISP_RETIRED.COND_TAKEN_FWD@  Instructions per retired Mispredicts for conditional forward-taken branches (lower number means higher occurrence rate)      000tma_info_branches_cond_tk_bwd Bad;Branches;CodeGen;PGO cpu_core@BR_INST_RETIRED.COND_TAKEN_BWD@ / cpu_core@BR_INST_RETIRED.ALL_BRANCHES@ tma_info_branches_cond_tk_bwd > 0.3 Fraction of branches that are forward taken conditionals      000tma_info_branches_cond_tk_fwd Bad;Branches;CodeGen;PGO cpu_core@BR_INST_RETIRED.COND_TAKEN_FWD@ / cpu_core@BR_INST_RETIRED.ALL_BRANCHES@ tma_info_branches_cond_tk_fwd > 0.2 Fraction of branches that are forward taken conditionals      000tma_info_branches_jump Bad;Branches (cpu_core@BR_INST_RETIRED.NEAR_TAKEN@ - cpu_core@BR_INST_RETIRED.COND_TAKEN_BWD@ - cpu_core@BR_INST_RETIRED.COND_TAKEN_FWD@ - 2 * cpu_core@BR_INST_RETIRED.NEAR_CALL@) / cpu_core@BR_INST_RETIRED.ALL_BRANCHES@  Fraction of branches that are unconditional (direct or indirect) jumps      000tma_info_branches_other_branches Bad;Branches 1 - (tma_info_branches_cond_nt + tma_info_branches_cond_tk_bwd + tma_info_branches_cond_tk_fwd + tma_info_branches_callret + tma_info_branches_jump)  Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)      000tma_info_core_flopc Flops;Ret (cpu_core@FP_ARITH_OPS_RETIRED.SCALAR@ + 2 * cpu_core@FP_ARITH_OPS_RETIRED.128B_PACKED_DOUBLE@ + 4 * cpu_core@FP_ARITH_OPS_RETIRED.4_FLOPS@ + 8 * cpu_core@FP_ARITH_OPS_RETIRED.256B_PACKED_SINGLE@) / tma_info_thread_clks  Floating Point Operations Per Cycle      000tma_info_core_fp_arith_utilization Cor;Flops;HPC (cpu_core@FP_ARITH_DISPATCHED.V0@ + cpu_core@FP_ARITH_DISPATCHED.V1@ + cpu_core@FP_ARITH_DISPATCHED.V2@ + cpu_core@FP_ARITH_DISPATCHED.V3@) / (4 * tma_info_thread_clks)  Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width) Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)     000tma_info_frontend_dsb_coverage DSB;Fed;FetchBW;tma_issueFB cpu_core@IDQ.DSB_UOPS@ / cpu_core@UOPS_ISSUED.ANY@ tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 8 > 0.35 Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache) Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp     000tma_info_frontend_dsb_switches_ret DSBmiss;Fed;FetchLat cpu_core@FRONTEND_RETIRED.ANY_DSB_MISS@ * cpu_core@FRONTEND_RETIRED.ANY_DSB_MISS@R / tma_info_thread_clks tma_info_frontend_dsb_switches_ret > 0.05 This metric represents fraction of cycles the CPU retirement was stalled likely due to retired DSB misses      000tma_info_frontend_icache_miss_latency Fed;FetchLat;IcMiss cpu_core@ICACHE_DATA.STALLS@ / cpu_core@ICACHE_DATA.STALL_PERIODS@  Average Latency for L1 instruction cache misses      000tma_info_frontend_ms_latency_ret Fed;FetchLat;MicroSeq cpu_core@FRONTEND_RETIRED.MS_FLOWS@ * cpu_core@FRONTEND_RETIRED.MS_FLOWS@R / tma_info_thread_clks tma_info_frontend_ms_latency_ret > 0.05 This metric represents fraction of cycles the CPU retirement was stalled likely due to retired operations that invoke the Microcode Sequencer      000tma_info_frontend_unknown_branches_ret Fed;FetchLat cpu_core@FRONTEND_RETIRED.UNKNOWN_BRANCH@ * cpu_core@FRONTEND_RETIRED.UNKNOWN_BRANCH@R / tma_info_thread_clks  This metric represents fraction of cycles the CPU retirement was stalled likely due to retired branches who got branch address clears      000tma_info_inst_mix_iparith Flops;InsType cpu_core@INST_RETIRED.ANY@ / (cpu_core@FP_ARITH_OPS_RETIRED.SCALAR@ + cpu_core@FP_ARITH_OPS_RETIRED.VECTOR@) tma_info_inst_mix_iparith < 10 Instructions per FP Arithmetic instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW     000tma_info_inst_mix_iparith_avx128 Flops;FpVector;InsType cpu_core@INST_RETIRED.ANY@ / (cpu_core@FP_ARITH_OPS_RETIRED.128B_PACKED_DOUBLE@ + cpu_core@FP_ARITH_OPS_RETIRED.128B_PACKED_SINGLE@) tma_info_inst_mix_iparith_avx128 < 10 Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting     000tma_info_inst_mix_iparith_avx256 Flops;FpVector;InsType cpu_core@INST_RETIRED.ANY@ / (cpu_core@FP_ARITH_OPS_RETIRED.256B_PACKED_DOUBLE@ + cpu_core@FP_ARITH_OPS_RETIRED.256B_PACKED_SINGLE@) tma_info_inst_mix_iparith_avx256 < 10 Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting     000tma_info_inst_mix_iparith_scalar_dp Flops;FpScalar;InsType cpu_core@INST_RETIRED.ANY@ / cpu_core@FP_ARITH_OPS_RETIRED.SCALAR_DOUBLE@ tma_info_inst_mix_iparith_scalar_dp < 10 Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting     000tma_info_inst_mix_iparith_scalar_sp Flops;FpScalar;InsType cpu_core@INST_RETIRED.ANY@ / cpu_core@FP_ARITH_OPS_RETIRED.SCALAR_SINGLE@ tma_info_inst_mix_iparith_scalar_sp < 10 Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting     000tma_info_inst_mix_ipflop Flops;InsType cpu_core@INST_RETIRED.ANY@ / (cpu_core@FP_ARITH_OPS_RETIRED.SCALAR@ + 2 * cpu_core@FP_ARITH_OPS_RETIRED.128B_PACKED_DOUBLE@ + 4 * cpu_core@FP_ARITH_OPS_RETIRED.4_FLOPS@ + 8 * cpu_core@FP_ARITH_OPS_RETIRED.256B_PACKED_SINGLE@) tma_info_inst_mix_ipflop < 10 Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)      000tma_info_inst_mix_ipswpf Prefetches cpu_core@INST_RETIRED.ANY@ / cpu_core@MEM_INST_RETIRED.ALL_SWPF@ tma_info_inst_mix_ipswpf < 100 Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)      000tma_info_inst_mix_iptb Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB cpu_core@INST_RETIRED.ANY@ / cpu_core@BR_INST_RETIRED.NEAR_TAKEN@ tma_info_inst_mix_iptb < 17 Instructions per taken branch Instructions per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_lcp     000tma_info_memory_l1d_cache_fill_bw Mem;MemoryBW 64 * cpu_core@L1D.L1_REPLACEMENT@ / 1e9 / tma_info_system_time  Average per-thread data fill bandwidth to the L1 data cache [GB / sec]      000tma_info_memory_l1dl0_cache_fill_bw Mem;MemoryBW 64 * cpu_core@L1D.L0_REPLACEMENT@ / 1e9 / tma_info_system_time  Average per-thread data fill bandwidth to the Level 0 within L1D cache [GB / sec]      000tma_info_memory_l1dl0_mpki CacheHits;Mem 1e3 * (cpu_core@MEM_LOAD_RETIRED.L1_MISS@ + cpu_core@MEM_LOAD_RETIRED.L1_HIT_L1@) / cpu_core@INST_RETIRED.ANY@  L0 cache true misses per kilo instruction for retired demand loads      000tma_info_memory_load_miss_real_latency Mem;MemoryBound;MemoryLat cpu_core@L1D_PENDING.LOAD@ / cpu_core@L1D_MISS.LOAD@  Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)      000tma_info_memory_mlp Mem;MemoryBW;MemoryBound cpu_core@L1D_PENDING.LOAD@ / cpu_core@L1D_PENDING.LOAD_CYCLES@  Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)     000tma_info_memory_tlb_load_stlb_miss_ret Mem;MemoryTLB cpu_core@MEM_INST_RETIRED.STLB_MISS_LOADS@ * cpu_core@MEM_INST_RETIRED.STLB_MISS_LOADS@R / tma_info_thread_clks tma_info_memory_tlb_load_stlb_miss_ret > 0.05 This metric represents fraction of cycles the CPU retirement was stalled likely due to STLB misses by demand loads      000tma_info_memory_tlb_page_walks_utilization Mem;MemoryTLB (cpu_core@ITLB_MISSES.WALK_PENDING@ + cpu_core@DTLB_LOAD_MISSES.WALK_PENDING@ + cpu_core@DTLB_STORE_MISSES.WALK_PENDING@) / (4 * tma_info_thread_clks) tma_info_memory_tlb_page_walks_utilization > 0.5 Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses      000tma_info_memory_tlb_store_stlb_miss_ret Mem;MemoryTLB cpu_core@MEM_INST_RETIRED.STLB_MISS_STORES@ * cpu_core@MEM_INST_RETIRED.STLB_MISS_STORES@R / tma_info_thread_clks tma_info_memory_tlb_store_stlb_miss_ret > 0.05 This metric represents fraction of cycles the CPU retirement was stalled likely due to STLB misses by demand stores      000tma_info_pipeline_fetch_ms Fed;FetchLat;MicroSeq cpu_core@IDQ.MS_UOPS@ / cpu_core@IDQ.MS_UOPS\,cmask\=1@  Average number of uops fetched from MS per cycle      000tma_info_system_dram_bw_use HPC;MemOffcore;MemoryBW;SoC;tma_issueBW 32 * UNC_M_TOTAL_DATA / 1e9 / tma_info_system_time  Average external Memory Bandwidth Use for reads and writes [GB / sec] Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_bottleneck_data_cache_memory_bandwidth, tma_fb_full, tma_mem_bandwidth, tma_sq_full     000tma_info_system_gflops Cor;Flops;HPC (cpu_core@FP_ARITH_OPS_RETIRED.SCALAR@ + 2 * cpu_core@FP_ARITH_OPS_RETIRED.128B_PACKED_DOUBLE@ + 4 * cpu_core@FP_ARITH_OPS_RETIRED.4_FLOPS@ + 8 * cpu_core@FP_ARITH_OPS_RETIRED.256B_PACKED_SINGLE@) / 1e9 / tma_info_system_time  Giga Floating Point Operations Per Second Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width     000tma_info_thread_uptb Branches;Fed;FetchBW tma_retiring * tma_info_thread_slots / cpu_core@BR_INST_RETIRED.NEAR_TAKEN@ tma_info_thread_uptb < 12 Uops per taken branch      000tma_int_vector_128b Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group;tma_issue2P cpu_core@INT_VEC_RETIRED.128BIT@ / (tma_retiring * tma_info_thread_slots) tma_int_vector_128b > 0.1 & (tma_int_operations > 0.1 & tma_light_operations > 0.6) This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_int_vector_256b Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group;tma_issue2P cpu_core@INT_VEC_RETIRED.256BIT@ / (tma_retiring * tma_info_thread_slots) tma_int_vector_256b > 0.1 & (tma_int_operations > 0.1 & tma_light_operations > 0.6) This metric represents 256-bit vector Integer ADD/SUB/SAD/MUL or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired This metric represents 256-bit vector Integer ADD/SUB/SAD/MUL or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_l1_bound CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group cpu_core@MEMORY_STALLS.L1@ / tma_info_thread_clks tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled without loads missing the L1 Data (L1D) cache This metric estimates how often the CPU was stalled without loads missing the L1 Data (L1D) cache.  The L1D cache typically has the shortest latency.  However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1D. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1 100%    000tma_l1_latency_capacity BvML;MemoryLat;TopdownL4;tma_L4_group;tma_l1_bound_group cpu_core@MEM_LOAD_RETIRED.L1_HIT_L1@ * min(cpu_core@MEM_LOAD_RETIRED.L1_HIT_L1@R, 9) / tma_info_thread_clks tma_l1_latency_capacity > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles with demand load accesses that hit Level 1 after missing Level 0 within the L1D cache  100%    000tma_l1_latency_dependency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_l1_bound_group 4 * cpu_core@DEPENDENT_LOADS.ANY\,cmask\=1@ / tma_info_thread_clks tma_l1_latency_dependency > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric ([SKL+] roughly; [LNL]) estimates fraction of cycles with demand load accesses that hit the L1D cache This metric ([SKL+] roughly; [LNL]) estimates fraction of cycles with demand load accesses that hit the L1D cache. The short latency of the L1D cache may be exposed in pointer-chasing memory access patterns as an example. Sample with: MEM_LOAD_RETIRED.L1_HIT 100%    000tma_l2_bound BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group cpu_core@MEMORY_STALLS.L2@ / tma_info_thread_clks tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to L2 cache accesses by loads This metric estimates how often the CPU was stalled due to L2 cache accesses by loads.  Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT 100%    000tma_l2_hit_latency MemoryLat;TopdownL4;tma_L4_group;tma_l2_bound_group cpu_core@MEM_LOAD_RETIRED.L2_HIT@ * min(cpu_core@MEM_LOAD_RETIRED.L2_HIT@R, 3 * tma_info_system_core_frequency) * (1 + cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / 2) / tma_info_thread_clks tma_l2_hit_latency > 0.05 & (tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles with demand load accesses that hit the L2 cache under unloaded scenarios (possibly L2 latency limited) This metric represents fraction of cycles with demand load accesses that hit the L2 cache under unloaded scenarios (possibly L2 latency limited).  Avoiding L1 cache misses (i.e. L1 misses/L2 hits) will improve the latency. Sample with: MEM_LOAD_RETIRED.L2_HIT 100%    000tma_l3_bound CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group cpu_core@MEMORY_STALLS.L3@ / tma_info_thread_clks tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core.  Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS 100%    000tma_l3_hit_latency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group cpu_core@MEM_LOAD_RETIRED.L3_HIT@ * min(cpu_core@MEM_LOAD_RETIRED.L3_HIT@R, 9 * tma_info_system_core_frequency) * (1 + cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / 2) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_bottleneck_data_cache_memory_latency, tma_mem_latency 100%    000tma_load_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group cpu_core@UOPS_DISPATCHED.LOAD@ / (3 * tma_info_thread_clks) tma_load_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3_10 100%    000tma_load_stlb_hit MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group max(0, tma_dtlb_load - tma_load_stlb_miss) tma_load_stlb_hit > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)  100%    000tma_lock_latency LockCont;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group cpu_core@MEM_INST_RETIRED.LOCK_LOADS@ * cpu_core@MEM_INST_RETIRED.LOCK_LOADS@R / tma_info_thread_clks tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS. Related metrics: tma_store_latency 100%    010tma_lsd FetchBW;LSD;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group cpu_core@LSD.UOPS\,cmask\=0x8\,inv\=0x1@ / tma_info_thread_clks / 2 tma_lsd > 0.15 & tma_fetch_bandwidth > 0.2 This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit.  LSD typically does well sustaining Uop supply. However; in some rare cases; optimal uop-delivery could not be reached for small loops whose size (in terms of number of uops) does not suit well the LSD structure 100%    000tma_mem_bandwidth BvMB;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW min(cpu_core@CPU_CLK_UNHALTED.THREAD@, cpu_core@OFFCORE_REQUESTS_OUTSTANDING.DATA_RD\,cmask\=4@) / tma_info_thread_clks tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM).  The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_bottleneck_data_cache_memory_bandwidth, tma_fb_full, tma_info_system_dram_bw_use, tma_sq_full 100%    000tma_mite DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group (cpu_core@IDQ.MITE_UOPS\,cmask\=0x8\,inv\=0x1@ / 2 + cpu_core@IDQ.MITE_UOPS@ / (cpu_core@IDQ.DSB_UOPS@ + cpu_core@IDQ.MITE_UOPS@) * (cpu_core@IDQ_BUBBLES.STARVATION_CYCLES@ - cpu_core@IDQ_BUBBLES.FETCH_LATENCY@)) / tma_info_thread_clks tma_mite > 0.1 & tma_fetch_bandwidth > 0.2 This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline) This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS 100%    000tma_ms MicroSeq;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group cpu_core@IDQ.MS_CYCLES_ANY@ / tma_info_thread_clks / 1.8 tma_ms > 0.05 & tma_fetch_bandwidth > 0.2 This metric represents Core fraction of cycles in which CPU was likely limited due to the Microcode Sequencer (MS) unit - see Microcode_Sequencer node for details  100%    000tma_ms_switches FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO 3 * cpu_core@IDQ.MS_SWITCHES@ / tma_info_thread_clks tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_bottleneck_irregular_overhead, tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation 100%    000tma_non_fused_branches Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * (cpu_core@BR_INST_RETIRED.ALL_BRANCHES@ - cpu_core@INST_RETIRED.BR_FUSED@) / (tma_retiring * tma_info_thread_slots) tma_non_fused_branches > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused 100%    000tma_other_light_ops Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group max(0, tma_light_operations - (tma_x87_use + (cpu_core@FP_ARITH_OPS_RETIRED.SCALAR@ + cpu_core@FP_ARITH_OPS_RETIRED.VECTOR@) / (tma_retiring * tma_info_thread_slots) + (cpu_core@INT_VEC_RETIRED.ADD_128@ + cpu_core@INT_VEC_RETIRED.VNNI_128@ + cpu_core@INT_VEC_RETIRED.ADD_256@ + cpu_core@INT_VEC_RETIRED.MUL_256@ + cpu_core@INT_VEC_RETIRED.VNNI_256@) / (tma_retiring * tma_info_thread_slots) + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches)) tma_other_light_ops > 0.3 & tma_light_operations > 0.6 This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting 100%    010tma_ports_utilization PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group ((cpu_core@EXE_ACTIVITY.EXE_BOUND_0_PORTS@ + (cpu_core@EXE_ACTIVITY.1_PORTS_UTIL@ + tma_retiring * cpu_core@EXE_ACTIVITY.2_3_PORTS_UTIL@)) / tma_info_thread_clks if cpu_core@ARITH.DIV_ACTIVE@ < cpu_core@CYCLE_ACTIVITY.STALLS_TOTAL@ - cpu_core@EXE_ACTIVITY.BOUND_ON_LOADS@ else (cpu_core@EXE_ACTIVITY.1_PORTS_UTIL@ + tma_retiring * cpu_core@EXE_ACTIVITY.2_3_PORTS_UTIL@) / tma_info_thread_clks) tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations 100%    020tma_ports_utilized_0 PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group cpu_core@EXE_ACTIVITY.EXE_BOUND_0_PORTS@ / tma_info_thread_clks tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric 100%    040tma_ret_mispredicts BrMispredicts;TopdownL3;tma_L3_group;tma_branch_mispredicts_group cpu_core@BR_MISP_RETIRED.RET_COST@ * cpu_core@BR_MISP_RETIRED.RET_COST@R / tma_info_thread_clks tma_ret_mispredicts > 0.05 & (tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15) This metric represents fraction of cycles the CPU was stalled due to retired misprediction by (indirect) RET instructions  100%    000tma_serializing_operation BvIO;PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group;tma_issueSO (cpu_core@BE_STALLS.SCOREBOARD@ + cpu_core@CPU_CLK_UNHALTED.C02@) / tma_info_thread_clks tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: PARTIAL_RAT_STALLS.SCOREBOARD. Related metrics: tma_ms_switches 100%    000tma_split_loads TopdownL4;tma_L4_group;tma_l1_bound_group cpu_core@MEM_INST_RETIRED.SPLIT_LOADS@ * min(cpu_core@MEM_INST_RETIRED.SPLIT_LOADS@R, tma_info_memory_load_miss_real_latency) / tma_info_thread_clks tma_split_loads > 0.3 This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS 100%    000tma_split_stores TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group cpu_core@MEM_INST_RETIRED.SPLIT_STORES@ * min(cpu_core@MEM_INST_RETIRED.SPLIT_STORES@R, 1) / tma_info_thread_clks tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents rate of split store accesses This metric represents rate of split store accesses.  Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4 100%    000tma_sq_full BvMB;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group (cpu_core@XQ.FULL@ + cpu_core@L1D_MISS.L2_STALLS@) / tma_info_thread_clks tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors) This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_bottleneck_data_cache_memory_bandwidth, tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth 100%    000tma_store_early_blk TopdownL4;tma_L4_group;tma_l1_bound_group 7 * cpu_core@LD_BLOCKS.STORE_EARLY\,cmask\=1@ / tma_info_thread_clks tma_store_early_blk > 0.2 This metric estimates clocks wasted due to loads blocked due to unknown store address (did not do memory disambiguation) or due to unknown store data  100%    000tma_store_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (cpu_core@UOPS_DISPATCHED.STD@ + cpu_core@UOPS_DISPATCHED.STA@) / (7 * tma_info_thread_clks) tma_store_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations. Sample with: UOPS_DISPATCHED.PORT_7_8 100%    000tma_store_stlb_hit MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group max(0, tma_dtlb_store - tma_store_stlb_miss) tma_store_stlb_hit > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)  100%    000tma_store_stlb_miss MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group cpu_core@DTLB_STORE_MISSES.WALK_ACTIVE@ / tma_info_thread_clks tma_store_stlb_miss > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk  100%    000lpm_cs_l2_misses lpm_cs d_ratio(L2_RQSTS.DEMAND_DATA_RD_MISS + L2_RQSTS.RFO_MISS + L2_RQSTS.CODE_RD_MISS, context\-switches)  L2 misses per context switch  1l2_misses/cs    000lpm_br_taken_insn_between_branches lpm_br;lpm_br_taken d_ratio(instructions, BR_INST_RETIRED.ANY)  The number of instructions divided by the number of taken branches  1insn    000lpm_br_taken_mispred lpm_br;lpm_br_taken d_ratio(BR_INST_RETIRED.MISPRED_TAKEN, BR_INST_RETIRED.ANY)  The number of retired taken branch instructions that were mispredicted as a percentage of all taken branches  100%    000lpm_br_taken_retired lpm_br;lpm_br_taken d_ratio(BR_INST_RETIRED.ANY, duration_time)  The number of taken branches that were retired per second  1insn/s    000lpm_br_total_insn_between_branches lpm_br;lpm_br_total d_ratio(instructions, BR_INST_RETIRED.ANY)  The number of instructions divided by the number of branches  1insn    000lpm_br_total_mispred lpm_br;lpm_br_total d_ratio(BR_INST_RETIRED.MISPRED, BR_INST_RETIRED.ANY)  The number of branch instructions retired, of any type, that were not correctly predicted as a percentage of all branch instrucions  100%    000lpm_br_total_retired lpm_br;lpm_br_total d_ratio(BR_INST_RETIRED.ANY, duration_time)  The number of branch instructions retired per second  1insn/s    000lpm_fpu_128_single_flops lpm_fpu;lpm_fpu_128;lpm_fpu_128_single d_ratio(SIMD_INST_RETIRED.PACKED_SINGLE * 4, duration_time)  128-bit packed single floating point operations per second  1flops/s    000lpm_fpu_128_single_of_total lpm_fpu;lpm_fpu_128;lpm_fpu_128_single d_ratio(SIMD_INST_RETIRED.PACKED_SINGLE * 4, SIMD_INST_RETIRED.SCALAR_SINGLE + SIMD_INST_RETIRED.SCALAR_DOUBLE + 4 * SIMD_INST_RETIRED.PACKED_SINGLE)  128-bit packed single floating point operations per second  100%    000lpm_fpu_128_single_ops lpm_fpu;lpm_fpu_128;lpm_fpu_128_single d_ratio(SIMD_INST_RETIRED.PACKED_SINGLE, duration_time)  128-bit packed single operations per second  1ops/s    000lpm_fpu_64_double_flops lpm_fpu;lpm_fpu_64;lpm_fpu_64_double d_ratio(SIMD_INST_RETIRED.SCALAR_DOUBLE, duration_time)  64-bit double floating point operations per second  1flops/s    000lpm_fpu_64_double_of_total lpm_fpu;lpm_fpu_64;lpm_fpu_64_double d_ratio(SIMD_INST_RETIRED.SCALAR_DOUBLE, SIMD_INST_RETIRED.SCALAR_SINGLE + SIMD_INST_RETIRED.SCALAR_DOUBLE + 4 * SIMD_INST_RETIRED.PACKED_SINGLE)  64-bit double floating point operations per second  100%    000lpm_fpu_64_double_ops lpm_fpu;lpm_fpu_64;lpm_fpu_64_double d_ratio(SIMD_INST_RETIRED.SCALAR_DOUBLE, duration_time)  64-bit double operations per second  1ops/s    000lpm_fpu_64_single_flops lpm_fpu;lpm_fpu_64;lpm_fpu_64_single d_ratio(SIMD_INST_RETIRED.SCALAR_SINGLE, duration_time)  64-bit single floating point operations per second  1flops/s    000lpm_fpu_64_single_of_total lpm_fpu;lpm_fpu_64;lpm_fpu_64_single d_ratio(SIMD_INST_RETIRED.SCALAR_SINGLE, SIMD_INST_RETIRED.SCALAR_SINGLE + SIMD_INST_RETIRED.SCALAR_DOUBLE + 4 * SIMD_INST_RETIRED.PACKED_SINGLE)  64-bit single floating point operations per second  100%    000lpm_fpu_64_single_ops lpm_fpu;lpm_fpu_64;lpm_fpu_64_single d_ratio(SIMD_INST_RETIRED.SCALAR_SINGLE, duration_time)  64-bit single operations per second  1ops/s    000lpm_fpu_assists lpm_fpu d_ratio(FP_ASSIST.S, cycles)  FP assists as a percentage of cycles  100%    000lpm_fpu_total_flopc lpm_fpu;lpm_fpu_total d_ratio(SIMD_INST_RETIRED.SCALAR_SINGLE + SIMD_INST_RETIRED.SCALAR_DOUBLE + 4 * SIMD_INST_RETIRED.PACKED_SINGLE, cycles)  Floating point operations per cycle  1flops/cycle    000lpm_fpu_total_flops lpm_fpu;lpm_fpu_total d_ratio(SIMD_INST_RETIRED.SCALAR_SINGLE + SIMD_INST_RETIRED.SCALAR_DOUBLE + 4 * SIMD_INST_RETIRED.PACKED_SINGLE, duration_time)  Floating point operations per second  1flops/s    000C3_Core_Residency Power cstate_core@c3\-residency@ / msr@tsc@  C3 residency percent per core  100%    000C7_Pkg_Residency Power cstate_pkg@c7\-residency@ / msr@tsc@  C7 residency percent per package  100%    000tma_4k_aliasing TopdownL4;tma_L4_group;tma_l1_bound_group LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / tma_info_thread_clks tma_4k_aliasing > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound) 100%    000tma_alu_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / tma_info_thread_slots tma_alu_op_utilization > 0.4 This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations  100%    000tma_assists BvIO;TopdownL4;tma_L4_group;tma_microcode_sequencer_group 66 * OTHER_ASSISTS.ANY_WB_ASSIST / tma_info_thread_slots tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1) This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY 100%    000tma_backend_bound BvOB;TmaL1;TopdownL1;tma_L1_group 1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring) tma_backend_bound > 0.2 This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound 100%  TopdownL1  000tma_bad_speculation TmaL1;TopdownL1;tma_L1_group (UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / tma_info_thread_slots tma_bad_speculation > 0.15 This category represents fraction of slots wasted due to incorrect speculations This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example 100%  TopdownL1  000tma_branch_mispredicts BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15 This metric represents fraction of slots the CPU has wasted due to Branch Misprediction This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_bad_spec_branch_misprediction_cost, tma_mispredicts_resteers 100%  TopdownL2  010tma_branch_resteers FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group 12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / tma_info_thread_clks tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES 100%    000tma_clears_resteers BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueMC MACHINE_CLEARS.COUNT * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) tma_clears_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Related metrics: tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches 100%    000tma_contested_accesses BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS)))) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100%    010tma_core_bound Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group tma_backend_bound - tma_memory_bound tma_core_bound > 0.1 & tma_backend_bound > 0.2 This metric represents fraction of slots where Core non-memory issues were of a bottleneck This metric represents fraction of slots where Core non-memory issues were of a bottleneck.  Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations) 100%  TopdownL2  010tma_data_sharing BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100%    010tma_divider BvCB;TopdownL3;tma_L3_group;tma_core_bound_group ARITH.FPU_DIV_ACTIVE / tma_info_core_core_clks tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric represents fraction of cycles where the Divider unit was active This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE 100%    000tma_dram_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_MISS / tma_info_thread_clks tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS 100%    030tma_dsb DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group (IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / tma_info_core_core_clks / 2 tma_dsb > 0.15 & tma_fetch_bandwidth > 0.2 This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline.  For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here 100%    000tma_dsb_switches DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_thread_clks tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Related metrics: tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 100%    000tma_dtlb_load BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group (8 * DTLB_LOAD_MISSES.STLB_HIT + cpu@DTLB_LOAD_MISSES.WALK_DURATION\,cmask\=1@ + 7 * DTLB_LOAD_MISSES.WALK_COMPLETED) / tma_info_thread_clks tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store 100%    000tma_dtlb_store BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group (8 * DTLB_STORE_MISSES.STLB_HIT + cpu@DTLB_STORE_MISSES.WALK_DURATION\,cmask\=1@ + 7 * DTLB_STORE_MISSES.WALK_COMPLETED) / tma_info_thread_clks tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses.  As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead.  Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page.  Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_UOPS_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load 100%    000tma_false_sharing BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group 60 * OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100%    000tma_fb_full BvMB;MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group tma_info_memory_load_miss_real_latency * cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ / tma_info_thread_clks tma_fb_full > 0.3 This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores 100%    010tma_fetch_bandwidth FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB tma_frontend_bound - tma_fetch_latency tma_fetch_bandwidth > 0.2 This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues.  For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Related metrics: tma_dsb_switches, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 100%  TopdownL2  000tma_fetch_latency Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group 4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / tma_info_thread_slots tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15 This metric represents fraction of slots the CPU was stalled due to Frontend latency issues This metric represents fraction of slots the CPU was stalled due to Frontend latency issues.  For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END 100%  TopdownL2  000tma_fp_scalar Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P FP_ARITH_INST_RETIRED.SCALAR / UOPS_RETIRED.RETIRE_SLOTS tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_fp_vector Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P FP_ARITH_INST_RETIRED.VECTOR / UOPS_RETIRED.RETIRE_SLOTS tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_fp_vector_128b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting prior to LNL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_fp_vector_256b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting prior to LNL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_frontend_bound BvFB;BvIO;PGO;TmaL1;TopdownL1;tma_L1_group IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_thread_slots tma_frontend_bound > 0.15 This category represents fraction of slots where the processor's Frontend undersupplies its Backend This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound 100%  TopdownL1  000tma_heavy_operations Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group tma_microcode_sequencer tma_heavy_operations > 0.1 This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.([ICL+] Note this may overcount due to approximation using indirect events; [ADL+]) 100%  TopdownL2  000tma_icache_misses BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group ICACHE.IFDATA_STALL / tma_info_thread_clks tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to instruction cache misses  100%    000tma_info_bad_spec_ipmisp_indirect Bad;BrMispredicts tma_info_inst_mix_instructions / (UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * BR_MISP_EXEC.INDIRECT) tma_info_bad_spec_ipmisp_indirect < 1e3 Instructions per retired Mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate)      000tma_info_bad_spec_ipmispredict Bad;BadSpec;BrMispredicts INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES tma_info_bad_spec_ipmispredict < 200 Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)      000tma_info_core_core_clks SMT (CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else tma_info_thread_clks))  Core actual clocks when any Logical Processor is active on the Physical Core      000tma_info_core_coreipc Ret;SMT;TmaL1;tma_L1_group INST_RETIRED.ANY / tma_info_core_core_clks  Instructions Per Cycle across hyper-threads (per physical core)      000tma_info_core_flopc Flops;Ret (FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / tma_info_core_core_clks  Floating Point Operations Per Cycle      000tma_info_core_fp_arith_utilization Cor;Flops;HPC (FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED.VECTOR) / (2 * tma_info_core_core_clks)  Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width) Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)     000tma_info_core_ilp Backend;Cor;Pipeline;PortsUtil UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\,cmask\=1@  Instruction-Level-Parallelism (average number of uops executed when there is execution) per thread (logical-processor)      000tma_info_frontend_dsb_coverage DSB;Fed;FetchBW;tma_issueFB IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS) tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 4 > 0.35 Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache) Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_inst_mix_iptb, tma_lcp     000tma_info_frontend_ipunknown_branch Fed tma_info_inst_mix_instructions / BACLEARS.ANY  Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)      000tma_info_frontend_tbpc Branches;FetchBW BR_INST_RETIRED.NEAR_TAKEN / tma_info_thread_clks  Taken Branches retired Per Cycle      000tma_info_inst_mix_bptkbranch Branches;Fed;PGO BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN  Branch instructions per taken branch      000tma_info_inst_mix_instructions Summary;TmaL1;tma_L1_group INST_RETIRED.ANY  Total number of retired Instructions Total number of retired Instructions. Sample with: INST_RETIRED.PREC_DIST     000tma_info_inst_mix_iparith Flops;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED.VECTOR) tma_info_inst_mix_iparith < 10 Instructions per FP Arithmetic instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW     000tma_info_inst_mix_iparith_avx128 Flops;FpVector;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) tma_info_inst_mix_iparith_avx128 < 10 Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting     000tma_info_inst_mix_iparith_avx256 Flops;FpVector;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) tma_info_inst_mix_iparith_avx256 < 10 Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting     000tma_info_inst_mix_iparith_scalar_dp Flops;FpScalar;InsType INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE tma_info_inst_mix_iparith_scalar_dp < 10 Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting     000tma_info_inst_mix_iparith_scalar_sp Flops;FpScalar;InsType INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE tma_info_inst_mix_iparith_scalar_sp < 10 Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting     000tma_info_inst_mix_ipbranch Branches;Fed;InsType INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES tma_info_inst_mix_ipbranch < 8 Instructions per Branch (lower number means higher occurrence rate)      000tma_info_inst_mix_ipcall Branches;Fed;PGO INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL tma_info_inst_mix_ipcall < 200 Instructions per (near) call (lower number means higher occurrence rate)      000tma_info_inst_mix_ipflop Flops;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) tma_info_inst_mix_ipflop < 10 Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)      000tma_info_inst_mix_ipload InsType INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS tma_info_inst_mix_ipload < 3 Instructions per Load (lower number means higher occurrence rate)      000tma_info_inst_mix_ipstore InsType INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES tma_info_inst_mix_ipstore < 8 Instructions per Store (lower number means higher occurrence rate)      000tma_info_inst_mix_iptb Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN tma_info_inst_mix_iptb < 9 Instructions per taken branch Instructions per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_lcp     000tma_info_memory_l1d_cache_fill_bw Mem;MemoryBW 64 * L1D.REPLACEMENT / 1e9 / tma_info_system_time  Average per-thread data fill bandwidth to the L1 data cache [GB / sec]      000tma_info_memory_l1mpki CacheHits;Mem 1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY  L1 cache true misses per kilo instruction for retired demand loads      000tma_info_memory_l2_cache_fill_bw Mem;MemoryBW 64 * L2_LINES_IN.ALL / 1e9 / tma_info_system_time  Average per-thread data fill bandwidth to the L2 cache [GB / sec]      000tma_info_memory_l2hpki_all CacheHits;Mem 1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY  L2 cache hits per kilo instruction for all request types (including speculative)      000tma_info_memory_l2hpki_load CacheHits;Mem 1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY  L2 cache hits per kilo instruction for all demand loads  (including speculative)      000tma_info_memory_l2mpki Backend;CacheHits;Mem 1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY  L2 cache true misses per kilo instruction for retired demand loads      000tma_info_memory_l2mpki_all CacheHits;Mem;Offcore 1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY  L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)      000tma_info_memory_l2mpki_load CacheHits;Mem 1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY  L2 cache ([RKL+] true) misses per kilo instruction for all demand loads  (including speculative)      000tma_info_memory_l2mpki_rfo CacheMisses;Offcore 1e3 * OFFCORE_REQUESTS.DEMAND_RFO / INST_RETIRED.ANY  Offcore requests (L2 cache miss) per kilo instruction for demand RFOs      000tma_info_memory_l3_cache_fill_bw Mem;MemoryBW 64 * LONGEST_LAT_CACHE.MISS / 1e9 / tma_info_system_time  Average per-thread data fill bandwidth to the L3 cache [GB / sec]      000tma_info_memory_l3mpki Mem 1e3 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY  L3 cache true misses per kilo instruction for retired demand loads      000tma_info_memory_latency_data_l2_mlp Memory_BW;Offcore OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD  Average Parallel L2 cache miss data reads      000tma_info_memory_latency_load_l2_miss_latency LockCont;Memory_Lat;Offcore OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD  Average Latency for L2 cache miss demand Loads      000tma_info_memory_latency_load_l2_mlp Memory_BW;Offcore OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD  Average Parallel L2 cache miss demand Loads      000tma_info_memory_load_miss_real_latency Mem;MemoryBound;MemoryLat L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB)  Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)      010tma_info_memory_mlp Mem;MemoryBW;MemoryBound L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES  Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)     010tma_info_memory_tlb_page_walks_utilization Mem;MemoryTLB (cpu@ITLB_MISSES.WALK_DURATION\,cmask\=1@ + cpu@DTLB_LOAD_MISSES.WALK_DURATION\,cmask\=1@ + cpu@DTLB_STORE_MISSES.WALK_DURATION\,cmask\=1@ + 7 * (DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED)) / tma_info_core_core_clks tma_info_memory_tlb_page_walks_utilization > 0.5 Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses      000tma_info_pipeline_execute Cor;Pipeline;PortsUtil;SMT UOPS_EXECUTED.THREAD / (cpu@UOPS_EXECUTED.CORE\,cmask\=1@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)  Mem;Backend;CacheHits      000tma_info_pipeline_retire Pipeline;Ret UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\,cmask\=1@  Average number of Uops retired in cycles where at least one uop has retired      000tma_info_system_core_frequency Power;Summary tma_info_system_turbo_utilization * msr@tsc@ / 1e9 / tma_info_system_time  Measured Average Core Frequency for unhalted processors [GHz]      000tma_info_system_cpus_utilized Summary CPU_CLK_UNHALTED.REF_TSC / msr@tsc@  Average number of utilized CPUs      000tma_info_system_dram_bw_use HPC;MemOffcore;MemoryBW;SoC;tma_issueBW 64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / tma_info_system_time / 1e3  Average external Memory Bandwidth Use for reads and writes [GB / sec] Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_fb_full, tma_mem_bandwidth, tma_sq_full     000tma_info_system_gflops Cor;Flops;HPC (FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / tma_info_system_time  Giga Floating Point Operations Per Second Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width     000tma_info_system_ipfarbranch Branches;OS INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u tma_info_system_ipfarbranch < 1e6 Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]      000tma_info_system_kernel_cpi OS CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k  Cycles Per Instruction for the Operating System (OS) Kernel mode      000tma_info_system_kernel_utilization OS CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD tma_info_system_kernel_utilization > 0.05 Fraction of cycles spent in the Operating System (OS) Kernel mode      000tma_info_system_mux Summary CPU_CLK_UNHALTED.THREAD_P / CPU_CLK_UNHALTED.THREAD tma_info_system_mux > 1.1 | tma_info_system_mux < 0.9 PerfMon Event Multiplexing accuracy indicator      000tma_info_system_smt_2t_utilization SMT (1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)  Fraction of cycles where both hardware Logical Processors were active      000tma_info_system_turbo_utilization Power tma_info_thread_clks / CPU_CLK_UNHALTED.REF_TSC  Average Frequency Utilization relative nominal frequency      000tma_info_thread_clks Pipeline CPU_CLK_UNHALTED.THREAD  Per-Logical Processor actual clocks when the Logical Processor is active      000tma_info_thread_execute_per_issue Cor;Pipeline UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY  The ratio of Executed- by Issued-Uops The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of "execute" at rename stage     000tma_info_thread_ipc Ret;Summary INST_RETIRED.ANY / tma_info_thread_clks  Instructions Per Cycle (per Logical Processor)      000tma_info_thread_slots TmaL1;tma_L1_group 4 * tma_info_core_core_clks  Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)      000tma_info_thread_uoppi Pipeline;Ret;Retire UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY tma_info_thread_uoppi > 1.05 Uops Per Instruction      000tma_info_thread_uptb Branches;Fed;FetchBW UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN tma_info_thread_uptb < 6 Uops per taken branch      000tma_itlb_misses BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group (14 * ITLB_MISSES.STLB_HIT + cpu@ITLB_MISSES.WALK_DURATION\,cmask\=1@ + 7 * ITLB_MISSES.WALK_COMPLETED) / tma_info_thread_clks tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED 100%    000tma_l1_bound CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / tma_info_thread_clks, 0) tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled without loads missing the L1 Data (L1D) cache This metric estimates how often the CPU was stalled without loads missing the L1 Data (L1D) cache.  The L1D cache typically has the shortest latency.  However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1D. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_UOPS_RETIRED.L1_HIT_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1 100%    000tma_l2_bound BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to L2 cache accesses by loads This metric estimates how often the CPU was stalled due to L2 cache accesses by loads.  Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L2_HIT_PS 100%    000tma_l3_bound CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_MISS / tma_info_thread_clks tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core.  Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS 100%    030tma_l3_hit_latency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS. Related metrics: tma_mem_latency 100%    010tma_lcp FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB ILD_STALL.LCP / tma_info_thread_clks tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs) This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb 100%    000tma_light_operations Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group tma_retiring - tma_heavy_operations tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation) This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .). Sample with: INST_RETIRED.PREC_DIST 100%  TopdownL2  000tma_load_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * tma_info_core_core_clks) tma_load_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3 100%    000tma_lock_latency LockCont;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / tma_info_thread_clks tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_UOPS_RETIRED.LOCK_LOADS_PS. Related metrics: tma_store_latency 100%    010tma_machine_clears BadSpec;BvMS;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn tma_bad_speculation - tma_branch_mispredicts tma_machine_clears > 0.1 & tma_bad_speculation > 0.15 This metric represents fraction of slots the CPU has wasted due to Machine Clears This metric represents fraction of slots the CPU has wasted due to Machine Clears.  These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache 100%  TopdownL2  010tma_mem_bandwidth BvMB;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=4@) / tma_info_thread_clks tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM).  The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_sq_full 100%    000tma_mem_latency BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM) This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM).  This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: tma_l3_hit_latency 100%    000tma_memory_bound Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group (CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB) / (CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if tma_info_thread_ipc > 1.8 else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) * tma_backend_bound tma_memory_bound > 0.2 & tma_backend_bound > 0.2 This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two) 100%  TopdownL2  010tma_microcode_sequencer MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / tma_info_thread_slots tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1 This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_ms_switches 100%    000tma_mispredicts_resteers BadSpec;BrMispredicts;BvMP;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM BR_MISP_RETIRED.ALL_BRANCHES * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost 100%    000tma_mite DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group (IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / tma_info_core_core_clks / 2 tma_mite > 0.1 & tma_fetch_bandwidth > 0.2 This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline) This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck 100%    000tma_ms_switches FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO 2 * IDQ.MS_SWITCHES / tma_info_thread_clks tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation 100%    000tma_port_0 Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED_PORT.PORT_0 / tma_info_core_core_clks tma_port_0 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_port_1 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED_PORT.PORT_1 / tma_info_core_core_clks tma_port_1 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_port_2 TopdownL6;tma_L6_group;tma_load_op_utilization_group UOPS_DISPATCHED_PORT.PORT_2 / tma_info_core_core_clks tma_port_2 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads) This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads). Sample with: UOPS_DISPATCHED_PORT.PORT_2 100%    000tma_port_3 TopdownL6;tma_L6_group;tma_load_op_utilization_group UOPS_DISPATCHED_PORT.PORT_3 / tma_info_core_core_clks tma_port_3 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads) This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads). Sample with: UOPS_DISPATCHED_PORT.PORT_3 100%    000tma_port_4 TopdownL6;tma_L6_group;tma_issueSpSt;tma_store_op_utilization_group tma_store_op_utilization tma_port_4 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data) This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data). Sample with: UOPS_DISPATCHED_PORT.PORT_4. Related metrics: tma_split_stores 100%    000tma_port_5 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED_PORT.PORT_5 / tma_info_core_core_clks tma_port_5 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU). Sample with: UOPS_DISPATCHED.PORT_5. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_6, tma_ports_utilized_2 100%    000tma_port_6 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED_PORT.PORT_6 / tma_info_core_core_clks tma_port_6 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2 100%    000tma_port_7 TopdownL6;tma_L6_group;tma_store_op_utilization_group UOPS_DISPATCHED_PORT.PORT_7 / tma_info_core_core_clks tma_port_7 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address) This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address). Sample with: UOPS_DISPATCHED_PORT.PORT_7 100%    000tma_ports_utilization PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group (CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if tma_info_thread_ipc > 1.8 else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB - RESOURCE_STALLS.SB - CYCLE_ACTIVITY.STALLS_MEM_ANY) / tma_info_thread_clks tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations 100%    010tma_ports_utilized_0 PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group (cpu@UOPS_EXECUTED.CORE\,inv\,cmask\=1@ / 2 if #SMT_on else CYCLE_ACTIVITY.STALLS_TOTAL - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0)) / tma_info_core_core_clks tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric 100%    000tma_ports_utilized_1 PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group ((cpu@UOPS_EXECUTED.CORE\,cmask\=1@ - cpu@UOPS_EXECUTED.CORE\,cmask\=2@) / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / tma_info_core_core_clks tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Related metrics: tma_l1_bound 100%    000tma_ports_utilized_2 PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group ((cpu@UOPS_EXECUTED.CORE\,cmask\=2@ - cpu@UOPS_EXECUTED.CORE\,cmask\=3@) / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / tma_info_core_core_clks tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).  Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6 100%    000tma_ports_utilized_3m BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group (cpu@UOPS_EXECUTED.CORE\,cmask\=3@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / tma_info_core_core_clks tma_ports_utilized_3m > 0.4 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)  100%    000tma_retiring BvUW;TmaL1;TopdownL1;tma_L1_group UOPS_RETIRED.RETIRE_SLOTS / tma_info_thread_slots tma_retiring > 0.7 | tma_heavy_operations > 0.1 This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category.  Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved.  Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance.  For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS 100%  TopdownL1  000tma_split_loads TopdownL4;tma_L4_group;tma_l1_bound_group tma_info_memory_load_miss_real_latency * LD_BLOCKS.NO_SR / tma_info_thread_clks tma_split_loads > 0.3 This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_UOPS_RETIRED.SPLIT_LOADS_PS 100%    010tma_split_stores TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group 2 * MEM_UOPS_RETIRED.SPLIT_STORES / tma_info_core_core_clks tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents rate of split store accesses This metric represents rate of split store accesses.  Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_UOPS_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4 100%    000tma_sq_full BvMB;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group (OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / tma_info_core_core_clks tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors) This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth 100%    000tma_store_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group RESOURCE_STALLS.SB / tma_info_thread_clks tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_UOPS_RETIRED.ALL_STORES_PS 100%    000tma_store_fwd_blk TopdownL4;tma_L4_group;tma_l1_bound_group 13 * LD_BLOCKS.STORE_FORWARD / tma_info_thread_clks tma_store_fwd_blk > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading 100%    000tma_store_latency BvML;LockCont;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group (L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles the CPU spent handling L1D store misses This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency 100%    010tma_store_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group UOPS_DISPATCHED_PORT.PORT_4 / tma_info_core_core_clks tma_store_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations  100%    000tma_unknown_branches BigFootprint;BvBC;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group tma_branch_resteers - tma_mispredicts_resteers - tma_clears_resteers tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to new branch address clears This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches. Sample with: BACLEARS.ANY 100%    000tma_x87_use Compute;TopdownL4;tma_L4_group;tma_fp_arith_group INST_RETIRED.X87 * tma_info_thread_uoppi / UOPS_RETIRED.RETIRE_SLOTS tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric serves as an approximation of legacy x87 usage This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint 100%    000Breakdown of transactional memory statistics lpm_br_cond_insn_between_branches lpm_br;lpm_br_cond d_ratio(instructions, BR_INST_RETIRED.CONDITIONAL)  The number of instructions divided by the number of conditional branches  1insn    000lpm_br_cond_mispred lpm_br;lpm_br_cond d_ratio(BR_MISP_RETIRED.CONDITIONAL, BR_INST_RETIRED.CONDITIONAL)  Retired conditional branch instructions mispredicted as a percentage of all conditional branches  100%    000lpm_br_cond_retired lpm_br;lpm_br_cond d_ratio(BR_INST_RETIRED.CONDITIONAL, duration_time)  Retired conditional branch instructions  1insn/s    000lpm_cs_l2_misses lpm_cs d_ratio(L2_RQSTS.DEMAND_DATA_RD_MISS + L2_RQSTS.RFO_MISS + L2_RQSTS.CODE_RD_MISS + L2_RQSTS.L2_PF_MISS, context\-switches)  L2 misses per context switch  1l2_misses/cs    000lpm_fpu_assists lpm_fpu d_ratio(FP_ASSIST.ANY, cycles)  FP assists as a percentage of cycles  100%    000lpm_fpu_total_flopc lpm_fpu;lpm_fpu_total d_ratio(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 4 * FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + 4 * FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE, cycles)  Floating point operations per cycle  1flops/cycle    000lpm_ilp_inst_ret_0 lpm_ilp 1 - d_ratio(max(INST_RETIRED.ANY_P@cmask\=1@ - INST_RETIRED.ANY_P@cmask\=2@, 0), CPU_CLK_UNHALTED.THREAD_P_ANY) - d_ratio(max(INST_RETIRED.ANY_P@cmask\=2@ - INST_RETIRED.ANY_P@cmask\=3@, 0), CPU_CLK_UNHALTED.THREAD_P_ANY) - d_ratio(max(INST_RETIRED.ANY_P@cmask\=3@ - INST_RETIRED.ANY_P@cmask\=4@, 0), CPU_CLK_UNHALTED.THREAD_P_ANY) - d_ratio(max(INST_RETIRED.ANY_P@cmask\=4@ - INST_RETIRED.ANY_P@cmask\=5@, 0), CPU_CLK_UNHALTED.THREAD_P_ANY) - d_ratio(INST_RETIRED.ANY_P@cmask\=5@, CPU_CLK_UNHALTED.THREAD_P_ANY)  Instructions retired in 0 cycles as a percentage of all cycles  100%    000lpm_ilp_inst_ret_1 lpm_ilp d_ratio(max(INST_RETIRED.ANY_P@cmask\=1@ - INST_RETIRED.ANY_P@cmask\=2@, 0), CPU_CLK_UNHALTED.THREAD_P_ANY)  Instructions retired in 1 cycles as a percentage of all cycles  100%    000lpm_ilp_inst_ret_2 lpm_ilp d_ratio(max(INST_RETIRED.ANY_P@cmask\=2@ - INST_RETIRED.ANY_P@cmask\=3@, 0), CPU_CLK_UNHALTED.THREAD_P_ANY)  Instructions retired in 2 cycles as a percentage of all cycles  100%    000lpm_ilp_inst_ret_3 lpm_ilp d_ratio(max(INST_RETIRED.ANY_P@cmask\=3@ - INST_RETIRED.ANY_P@cmask\=4@, 0), CPU_CLK_UNHALTED.THREAD_P_ANY)  Instructions retired in 3 cycles as a percentage of all cycles  100%    000lpm_ilp_inst_ret_4 lpm_ilp d_ratio(max(INST_RETIRED.ANY_P@cmask\=4@ - INST_RETIRED.ANY_P@cmask\=5@, 0), CPU_CLK_UNHALTED.THREAD_P_ANY)  Instructions retired in 4 cycles as a percentage of all cycles  100%    000lpm_ilp_inst_ret_5 lpm_ilp d_ratio(INST_RETIRED.ANY_P@cmask\=5@, CPU_CLK_UNHALTED.THREAD_P_ANY)  Instructions retired in 5 or more cycles as a percentage of all cycles  100%    000lpm_l2_totals_out lpm_l2;lpm_l2_totals d_ratio((L2_LINES_OUT.DEMAND_CLEAN / 2 if #smt_on else L2_LINES_OUT.DEMAND_CLEAN) + L2_LINES_IN.S, duration_time)  L2 cache total out per second  1Out/s    000lpm_ldst_ld_hit_swpf lpm_ldst d_ratio(LOAD_HIT_PRE.SW_PF, duration_time)  Load hit software prefetches per second  1swpf/s    000lpm_port_0 lpm_ports d_ratio(UOPS_DISPATCHED_PORT.PORT_0, (CPU_CLK_UNHALTED.THREAD_P_ANY / 2 if #smt_on else CPU_CLK_UNHALTED.THREAD_P_ANY))  port_0 utilization (higher is better)  100%    000lpm_port_1 lpm_ports d_ratio(UOPS_DISPATCHED_PORT.PORT_1, (CPU_CLK_UNHALTED.THREAD_P_ANY / 2 if #smt_on else CPU_CLK_UNHALTED.THREAD_P_ANY))  port_1 utilization (higher is better)  100%    000lpm_port_2 lpm_ports d_ratio(UOPS_DISPATCHED_PORT.PORT_2, (CPU_CLK_UNHALTED.THREAD_P_ANY / 2 if #smt_on else CPU_CLK_UNHALTED.THREAD_P_ANY))  port_2 utilization (higher is better)  100%    000lpm_port_3 lpm_ports d_ratio(UOPS_DISPATCHED_PORT.PORT_3, (CPU_CLK_UNHALTED.THREAD_P_ANY / 2 if #smt_on else CPU_CLK_UNHALTED.THREAD_P_ANY))  port_3 utilization (higher is better)  100%    000lpm_port_4 lpm_ports d_ratio(UOPS_DISPATCHED_PORT.PORT_4, (CPU_CLK_UNHALTED.THREAD_P_ANY / 2 if #smt_on else CPU_CLK_UNHALTED.THREAD_P_ANY))  port_4 utilization (higher is better)  100%    000lpm_port_5 lpm_ports d_ratio(UOPS_DISPATCHED_PORT.PORT_5, (CPU_CLK_UNHALTED.THREAD_P_ANY / 2 if #smt_on else CPU_CLK_UNHALTED.THREAD_P_ANY))  port_5 utilization (higher is better)  100%    000lpm_port_6 lpm_ports d_ratio(UOPS_DISPATCHED_PORT.PORT_6, (CPU_CLK_UNHALTED.THREAD_P_ANY / 2 if #smt_on else CPU_CLK_UNHALTED.THREAD_P_ANY))  port_6 utilization (higher is better)  100%    000lpm_port_7 lpm_ports d_ratio(UOPS_DISPATCHED_PORT.PORT_7, (CPU_CLK_UNHALTED.THREAD_P_ANY / 2 if #smt_on else CPU_CLK_UNHALTED.THREAD_P_ANY))  port_7 utilization (higher is better)  100%    000tsx_aborted_cycles transaction (max(cpu@cycles\-t@ - cpu@cycles\-ct@, 0) / cycles if has_event(cpu@cycles\-t@) else 0)  Percentage of cycles in aborted transactions  100%    000tsx_cycles_per_elision transaction (cpu@cycles\-t@ / cpu@el\-start@ if has_event(cpu@el\-start@) else 0)  Number of cycles within a transaction divided by the number of elisions  1cycles / elision    000tsx_cycles_per_transaction transaction (cpu@cycles\-t@ / cpu@tx\-start@ if has_event(cpu@cycles\-t@) else 0)  Number of cycles within a transaction divided by the number of transactions  1cycles / transaction    000tsx_transactional_cycles transaction (cpu@cycles\-t@ / cycles if has_event(cpu@cycles\-t@) else 0)  Percentage of cycles within a transaction region  100%    000tma_assists BvIO;TopdownL4;tma_L4_group;tma_microcode_sequencer_group 66 * OTHER_ASSISTS.ANY_WB_ASSIST / tma_info_thread_slots tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1) This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY 100%    000tma_backend_bound BvOB;TmaL1;TopdownL1;tma_L1_group 1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring) tma_backend_bound > 0.2 This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS 100%  TopdownL1  000tma_branch_mispredicts BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15 This metric represents fraction of slots the CPU has wasted due to Branch Misprediction This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS. Related metrics: tma_info_bad_spec_branch_misprediction_cost, tma_mispredicts_resteers 100%  TopdownL2  010tma_clears_resteers BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueMC MACHINE_CLEARS.COUNT * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) tma_clears_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches 100%    000tma_contested_accesses BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS)))) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100%    010tma_data_sharing BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100%    010tma_divider BvCB;TopdownL3;tma_L3_group;tma_core_bound_group ARITH.FPU_DIV_ACTIVE / tma_info_core_core_clks tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric represents fraction of cycles where the Divider unit was active This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIV_ACTIVE 100%    000tma_dram_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_MISS / tma_info_thread_clks tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS 100%    030tma_dsb_switches DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_thread_clks tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 100%    000tma_dtlb_load BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group (8 * DTLB_LOAD_MISSES.STLB_HIT + cpu@DTLB_LOAD_MISSES.WALK_DURATION\,cmask\=1@ + 7 * DTLB_LOAD_MISSES.WALK_COMPLETED) / tma_info_thread_clks tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store 100%    000tma_dtlb_store BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group (8 * DTLB_STORE_MISSES.STLB_HIT + cpu@DTLB_STORE_MISSES.WALK_DURATION\,cmask\=1@ + 7 * DTLB_STORE_MISSES.WALK_COMPLETED) / tma_info_thread_clks tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses.  As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead.  Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page.  Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load 100%    000tma_fetch_bandwidth FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB tma_frontend_bound - tma_fetch_latency tma_fetch_bandwidth > 0.2 This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues.  For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1;FRONTEND_RETIRED.LATENCY_GE_1;FRONTEND_RETIRED.LATENCY_GE_2. Related metrics: tma_dsb_switches, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 100%  TopdownL2  000tma_fetch_latency Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group 4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / tma_info_thread_slots tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15 This metric represents fraction of slots the CPU was stalled due to Frontend latency issues This metric represents fraction of slots the CPU was stalled due to Frontend latency issues.  For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS 100%  TopdownL2  000tma_frontend_bound BvFB;BvIO;PGO;TmaL1;TopdownL1;tma_L1_group IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_thread_slots tma_frontend_bound > 0.15 This category represents fraction of slots where the processor's Frontend undersupplies its Backend This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS 100%  TopdownL1  000tma_heavy_operations Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group tma_microcode_sequencer tma_heavy_operations > 0.1 This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.([ICL+] Note this may overcount due to approximation using indirect events; [ADL+]). Sample with: UOPS_RETIRED.HEAVY 100%  TopdownL2  000tma_icache_misses BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group ICACHE.IFDATA_STALL / tma_info_thread_clks tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to instruction cache misses This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS 100%    000tma_info_system_dram_bw_use HPC;MemOffcore;MemoryBW;SoC;tma_issueBW 64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / tma_info_system_time  Average external Memory Bandwidth Use for reads and writes [GB / sec] Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_fb_full, tma_mem_bandwidth, tma_sq_full     000tma_info_system_socket_clks SoC cbox_0@event\=0x0@  Socket actual clocks when any core is active on that socket      000tma_itlb_misses BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group (14 * ITLB_MISSES.STLB_HIT + cpu@ITLB_MISSES.WALK_DURATION\,cmask\=1@ + 7 * ITLB_MISSES.WALK_COMPLETED) / tma_info_thread_clks tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS 100%    000tma_l1_bound CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / tma_info_thread_clks, 0) tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled without loads missing the L1 Data (L1D) cache This metric estimates how often the CPU was stalled without loads missing the L1 Data (L1D) cache.  The L1D cache typically has the shortest latency.  However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1D. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1 100%    000tma_l2_bound BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to L2 cache accesses by loads This metric estimates how often the CPU was stalled due to L2 cache accesses by loads.  Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT 100%    000tma_l3_bound CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_MISS / tma_info_thread_clks tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core.  Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS 100%    030tma_l3_hit_latency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_mem_latency 100%    010tma_load_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * tma_info_core_core_clks) tma_load_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3_10 100%    000tma_lock_latency LockCont;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / tma_info_thread_clks tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS. Related metrics: tma_store_latency 100%    010tma_microcode_sequencer MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / tma_info_thread_slots tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1 This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: UOPS_RETIRED.MS. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_ms_switches 100%    000tma_mispredicts_resteers BadSpec;BrMispredicts;BvMP;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM BR_MISP_RETIRED.ALL_BRANCHES * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost 100%    000tma_mite DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group (IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / tma_info_core_core_clks / 2 tma_mite > 0.1 & tma_fetch_bandwidth > 0.2 This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline) This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS 100%    000tma_port_0 Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED_PORT.PORT_0 / tma_info_core_core_clks tma_port_0 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_port_1 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED_PORT.PORT_1 / tma_info_core_core_clks tma_port_1 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_port_2 TopdownL6;tma_L6_group;tma_load_op_utilization_group UOPS_DISPATCHED_PORT.PORT_2 / tma_info_core_core_clks tma_port_2 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads)  100%    000tma_port_3 TopdownL6;tma_L6_group;tma_load_op_utilization_group UOPS_DISPATCHED_PORT.PORT_3 / tma_info_core_core_clks tma_port_3 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads)  100%    000tma_port_4 TopdownL6;tma_L6_group;tma_issueSpSt;tma_store_op_utilization_group tma_store_op_utilization tma_port_4 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data) This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data). Related metrics: tma_split_stores 100%    000tma_port_5 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED_PORT.PORT_5 / tma_info_core_core_clks tma_port_5 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU). Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_6, tma_ports_utilized_2 100%    000tma_port_6 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED_PORT.PORT_6 / tma_info_core_core_clks tma_port_6 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU). Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2 100%    000tma_port_7 TopdownL6;tma_L6_group;tma_store_op_utilization_group UOPS_DISPATCHED_PORT.PORT_7 / tma_info_core_core_clks tma_port_7 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)  100%    000tma_ports_utilized_1 PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group ((cpu@UOPS_EXECUTED.CORE\,cmask\=1@ - cpu@UOPS_EXECUTED.CORE\,cmask\=2@) / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / tma_info_core_core_clks tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL. Related metrics: tma_l1_bound 100%    000tma_ports_utilized_2 PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group ((cpu@UOPS_EXECUTED.CORE\,cmask\=2@ - cpu@UOPS_EXECUTED.CORE\,cmask\=3@) / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / tma_info_core_core_clks tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).  Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6 100%    000tma_ports_utilized_3m BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group (cpu@UOPS_EXECUTED.CORE\,cmask\=3@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / tma_info_core_core_clks tma_ports_utilized_3m > 0.4 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3 100%    000tma_retiring BvUW;TmaL1;TopdownL1;tma_L1_group UOPS_RETIRED.RETIRE_SLOTS / tma_info_thread_slots tma_retiring > 0.7 | tma_heavy_operations > 0.1 This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category.  Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved.  Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance.  For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS 100%  TopdownL1  000tma_split_loads TopdownL4;tma_L4_group;tma_l1_bound_group tma_info_memory_load_miss_real_latency * LD_BLOCKS.NO_SR / tma_info_thread_clks tma_split_loads > 0.3 This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS 100%    010tma_split_stores TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group 2 * MEM_UOPS_RETIRED.SPLIT_STORES / tma_info_core_core_clks tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents rate of split store accesses This metric represents rate of split store accesses.  Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4 100%    000tma_store_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group RESOURCE_STALLS.SB / tma_info_thread_clks tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS 100%    000tma_store_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group UOPS_DISPATCHED_PORT.PORT_4 / tma_info_core_core_clks tma_store_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations. Sample with: UOPS_DISPATCHED.PORT_7_8 100%    000tma_unknown_branches BigFootprint;BvBC;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group tma_branch_resteers - tma_mispredicts_resteers - tma_clears_resteers tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to new branch address clears This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches. Sample with: FRONTEND_RETIRED.UNKNOWN_BRANCH 100%    000lpm_mem Memory Bandwidth breakdown local vs. remote (remote requests in). directory updates not included lpm_mem_bw lpm_mem_bw_ddr DDR Memory Bandwidth lpm_cstate_c0 lpm_cstate d_ratio(UNC_P_POWER_STATE_OCCUPANCY.CORES_C0, UNC_P_CLOCKTICKS)  C-State cores in C0/C1  1cores    000lpm_cstate_c3 lpm_cstate d_ratio(UNC_P_POWER_STATE_OCCUPANCY.CORES_C3, UNC_P_CLOCKTICKS)  C-State cores in C3  1cores    000lpm_cstate_c6 lpm_cstate d_ratio((max(UNC_P_POWER_STATE_OCCUPANCY.CORES_C6 - (UNC_P_POWER_STATE_OCCUPANCY.CORES_C0 + UNC_P_POWER_STATE_OCCUPANCY.CORES_C3 + UNC_P_POWER_STATE_OCCUPANCY.CORES_C6 - UNC_P_CLOCKTICKS * (#num_cores / #num_packages)), 0) if UNC_P_POWER_STATE_OCCUPANCY.CORES_C0 + UNC_P_POWER_STATE_OCCUPANCY.CORES_C3 + UNC_P_POWER_STATE_OCCUPANCY.CORES_C6 > UNC_P_CLOCKTICKS * (#num_cores / #num_packages) else UNC_P_POWER_STATE_OCCUPANCY.CORES_C6), UNC_P_CLOCKTICKS)  C-State cores in C6/C7  1cores    000lpm_mem_bw_ddr_read lpm_mem_bw;lpm_mem_bw_ddr d_ratio(UNC_M_CAS_COUNT.RD, duration_time)  DDR memory read bandwidth  6.4e-05MB/s    000lpm_mem_bw_ddr_total lpm_mem_bw;lpm_mem_bw_ddr d_ratio(UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR, duration_time)  DDR memory write bandwidth  6.4e-05MB/s    000lpm_mem_bw_ddr_write lpm_mem_bw;lpm_mem_bw_ddr d_ratio(UNC_M_CAS_COUNT.WR, duration_time)  DDR memory write bandwidth  6.4e-05MB/s    000lpm_mem_local_read lpm_mem;lpm_mem_local d_ratio(UNC_H_REQUESTS.READS_LOCAL, duration_time)  Local memory read bandwidth not including directory updates  6.4e-05MB/s    000lpm_mem_local_write lpm_mem;lpm_mem_local d_ratio(UNC_H_REQUESTS.WRITES_LOCAL, duration_time)  Local memory write bandwidth not including directory updates  6.4e-05MB/s    000lpm_mem_remote_read lpm_mem;lpm_mem_remote d_ratio(UNC_H_REQUESTS.READS_REMOTE, duration_time)  Remote memory read bandwidth not including directory updates  6.4e-05MB/s    000lpm_mem_remote_write lpm_mem;lpm_mem_remote d_ratio(UNC_H_REQUESTS.WRITES_REMOTE, duration_time)  Remote memory write bandwidth not including directory updates  6.4e-05MB/s    000lpm_mem_sat  d_ratio(UNC_C_FAST_ASSERTED, UNC_C_CLOCKTICKS)  Mesh Bandwidth saturation (% CBOX cycles with FAST signal asserted, include QPI bandwidth saturation), lower is better  100%    000lpm_miss_lat_loc lpm_miss_lat duration_time * 1e9 * UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE@filter_opc\=0x182@ / (UNC_C_CLOCKTICKS / source_count(UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE@filter_opc\=0x182@) * UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE@filter_opc\=0x182@)  Local to a socket miss latency in nanoseconds  1ns    000lpm_miss_lat_rem lpm_miss_lat duration_time * 1e9 * UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE@filter_opc\=0x182@ / (UNC_C_CLOCKTICKS / source_count(UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE@filter_opc\=0x182@) * UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE@filter_opc\=0x182@)  Remote to a socket miss latency in nanoseconds  1ns    000cpi  CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY  Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles  1per_instr    000cpu_operating_frequency  CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9  CPU operating frequency (in GHz)  1GHz    000cpu_utilization  tma_info_system_cpus_utilized  Percentage of time spent in the active CPU power state C0  100%    000dtlb_load_mpi  DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY  Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB 1per_instr    000dtlb_store_mpi  DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY  Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB 1per_instr    000io_bandwidth_read  cbox@UNC_C_TOR_INSERTS.OPCODE\,filter_opc\=0x19e@ * 64 / 1e6 / duration_time  Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU  1MB/s    000io_bandwidth_write  (cbox@UNC_C_TOR_INSERTS.OPCODE\,filter_opc\=0x1c8\,filter_tid\=0x3e@ + cbox@UNC_C_TOR_INSERTS.OPCODE\,filter_opc\=0x180\,filter_tid\=0x3e@) * 64 / 1e6 / duration_time  Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU  1MB/s    000itlb_large_page_mpi  ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY  Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB 1per_instr    000itlb_mpi  ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY  Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB 1per_instr    000l1_i_code_read_misses_with_prefetches_per_instr  L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY  Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions  1per_instr    000l1d_demand_data_read_hits_per_instr  MEM_LOAD_UOPS_RETIRED.L1_HIT / INST_RETIRED.ANY  Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions  1per_instr    000l1d_mpi  L1D.REPLACEMENT / INST_RETIRED.ANY  Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions  1per_instr    000l2_demand_code_mpi  L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY  Ratio of number of code read request missing L2 cache to the total number of completed instructions  1per_instr    000l2_demand_data_read_hits_per_instr  MEM_LOAD_UOPS_RETIRED.L2_HIT / INST_RETIRED.ANY  Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions  1per_instr    000l2_demand_data_read_mpi  MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY  Ratio of number of completed data read request missing L2 cache to the total number of completed instructions  1per_instr    000l2_mpi  L2_LINES_IN.ALL / INST_RETIRED.ANY  Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions  1per_instr    000llc_code_read_mpi_demand_plus_prefetch  (cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\,filter_opc\=0x181@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\,filter_opc\=0x191@) / INST_RETIRED.ANY  Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions  1per_instr    000llc_data_read_demand_plus_prefetch_miss_latency  1e9 * (cbox@UNC_C_TOR_OCCUPANCY.MISS_OPCODE\,filter_opc\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\,filter_opc\=0x182@) / (UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time  Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) in nano seconds  1ns    000llc_data_read_demand_plus_prefetch_miss_latency_for_local_requests  1e9 * (cbox@UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE\,filter_opc\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\,filter_opc\=0x182@) / (UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time  Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to local memory in nano seconds  1ns    000llc_data_read_demand_plus_prefetch_miss_latency_for_remote_requests  1e9 * (cbox@UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE\,filter_opc\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\,filter_opc\=0x182@) / (UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time  Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to remote memory in nano seconds  1ns    000llc_data_read_mpi_demand_plus_prefetch  (cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\,filter_opc\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\,filter_opc\=0x192@) / INST_RETIRED.ANY  Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions  1per_instr    000loads_per_instr  MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY  The ratio of number of completed memory load instructions to the total number completed instructions  1per_instr    000memory_bandwidth_read  UNC_M_CAS_COUNT.RD * 64 / 1e6 / duration_time  DDR memory read bandwidth (MB/sec)  1MB/s    000memory_bandwidth_total  (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) * 64 / 1e6 / duration_time  DDR memory bandwidth (MB/sec)  1MB/s    000memory_bandwidth_write  UNC_M_CAS_COUNT.WR * 64 / 1e6 / duration_time  DDR memory write bandwidth (MB/sec)  1MB/s    000numa_reads_addressed_to_local_dram  cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\,filter_opc\=0x182@ / (cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\,filter_opc\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\,filter_opc\=0x182@)  Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches  100%    000numa_reads_addressed_to_remote_dram  cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\,filter_opc\=0x182@ / (cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\,filter_opc\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\,filter_opc\=0x182@)  Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches  100%    000percent_uops_delivered_from_decoded_icache  IDQ.DSB_UOPS / UOPS_ISSUED.ANY  Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue  100%    000percent_uops_delivered_from_legacy_decode_pipeline  IDQ.MITE_UOPS / UOPS_ISSUED.ANY  Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue  100%    000percent_uops_delivered_from_loop_stream_detector  LSD.UOPS / UOPS_ISSUED.ANY  Uops delivered from loop stream detector(LSD) as a percent of total uops delivered to Instruction Decode Queue  100%    000percent_uops_delivered_from_microcode_sequencer  IDQ.MS_UOPS / UOPS_ISSUED.ANY  Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue  100%    000qpi_data_transmit_bw  UNC_Q_TxL_FLITS_G0.DATA * 8 / 1e6 / duration_time  Intel(R) Quick Path Interconnect (QPI) data transmit bandwidth (MB/sec)  1MB/s    000stores_per_instr  MEM_UOPS_RETIRED.ALL_STORES / INST_RETIRED.ANY  The ratio of number of completed memory store instructions to the total number completed instructions  1per_instr    000tma_contested_accesses BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100%    010tma_data_sharing BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100%    010tma_false_sharing BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group (200 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM + 60 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE) / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100%    000tma_info_memory_tlb_page_walks_utilization Mem;MemoryTLB (ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * (DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED)) / (2 * tma_info_core_core_clks) tma_info_memory_tlb_page_walks_utilization > 0.5 Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses      000tma_info_system_mem_parallel_reads Mem;MemoryBW;SoC UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\=0x182@ / UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\=0x182\,thresh\=1@  Average number of parallel data read requests to external memory Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches     010tma_info_system_mem_read_latency Mem;MemoryLat;SoC 1e9 * (UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\=0x182@ / UNC_C_TOR_INSERTS.MISS_OPCODE@filter_opc\=0x182@) / (tma_info_system_socket_clks / tma_info_system_time)  Average latency of data read request to external memory (in nanoseconds) Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)     000tma_info_system_power Power;SoC (power@energy\-pkg@ * 61 + 15.6 * power@energy\-ram@) / (duration_time * 1e6)  Total package Power in Watts      000tma_l3_hit_latency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 41 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS. Related metrics: tma_mem_latency 100%    010tma_local_mem Server;TopdownL5;tma_L5_group;tma_mem_latency_group 200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / tma_info_thread_clks tma_local_mem > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM_PS 100%    010tma_remote_cache Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_issueSyncxn;tma_mem_latency_group (200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 180 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / tma_info_thread_clks tma_remote_cache > 0.05 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD_PS. Related metrics: tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears 100%    010tma_remote_mem Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group 310 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / tma_info_thread_clks tma_remote_mem > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM_PS 100%    010uncore_frequency  UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages) / 1e9 / duration_time  Uncore operating frequency in GHz  1GHz    000dtlb_2mb_large_page_load_mpi  DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY  Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB 1per_instr    000io_bandwidth_read  (UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3) * 4 / 1e6 / duration_time  Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU  1MB/s    000io_bandwidth_write  (UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3) * 4 / 1e6 / duration_time  Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU  1MB/s    000l1d_demand_data_read_hits_per_instr  MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY  Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions  1per_instr    000l2_demand_data_read_hits_per_instr  MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY  Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions  1per_instr    000l2_demand_data_read_mpi  MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY  Ratio of number of completed data read request missing L2 cache to the total number of completed instructions  1per_instr    000llc_code_read_mpi_demand_plus_prefetch  cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x12cc0233@ / INST_RETIRED.ANY  Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions  1per_instr    000llc_data_read_demand_plus_prefetch_miss_latency  1e9 * (cha@UNC_CHA_TOR_OCCUPANCY.IA_MISS\,config1\=0x40433@ / cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40433@) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages)) * duration_time  Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) in nano seconds  1ns    000llc_data_read_demand_plus_prefetch_miss_latency_for_local_requests  1e9 * (cha@UNC_CHA_TOR_OCCUPANCY.IA_MISS\,config1\=0x40432@ / cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40432@) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages)) * duration_time  Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to local memory in nano seconds  1ns    000llc_data_read_demand_plus_prefetch_miss_latency_for_remote_requests  1e9 * (cha@UNC_CHA_TOR_OCCUPANCY.IA_MISS\,config1\=0x40431@ / cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40431@) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages)) * duration_time  Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to remote memory in nano seconds  1ns    000llc_data_read_mpi_demand_plus_prefetch  cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x12d40433@ / INST_RETIRED.ANY  Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions  1per_instr    000llc_miss_local_memory_bandwidth_read  UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1e6 / duration_time  Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory  1MB/s    000llc_miss_local_memory_bandwidth_write  UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1e6 / duration_time  Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory  1MB/s    000llc_miss_remote_memory_bandwidth_read  UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1e6 / duration_time  Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory  1MB/s    000llc_miss_remote_memory_bandwidth_write  UNC_CHA_REQUESTS.WRITES_REMOTE * 64 / 1e6 / duration_time  Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory  1MB/s    000loads_per_instr  MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY  The ratio of number of completed memory load instructions to the total number completed instructions  1per_instr    000numa_reads_addressed_to_local_dram  cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40432@ / (cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40432@ + cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40431@)  Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches  100%    000numa_reads_addressed_to_remote_dram  cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40431@ / (cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40432@ + cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40431@)  Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches  100%    000percent_uops_delivered_from_decoded_icache  IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)  Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue  100%    000percent_uops_delivered_from_legacy_decode_pipeline  IDQ.MITE_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)  Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue  100%    000percent_uops_delivered_from_microcode_sequencer  IDQ.MS_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)  Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue  100%    000pmem_memory_bandwidth_read  UNC_M_PMM_RPQ_INSERTS * 64 / 1e6 / duration_time  Intel(R) Optane(TM) Persistent Memory(PMEM) memory read bandwidth (MB/sec)  1MB/s    000pmem_memory_bandwidth_total  (UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS) * 64 / 1e6 / duration_time  Intel(R) Optane(TM) Persistent Memory(PMEM) memory bandwidth (MB/sec)  1MB/s    000pmem_memory_bandwidth_write  UNC_M_PMM_WPQ_INSERTS * 64 / 1e6 / duration_time  Intel(R) Optane(TM) Persistent Memory(PMEM) memory write bandwidth (MB/sec)  1MB/s    000stores_per_instr  MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY  The ratio of number of completed memory store instructions to the total number completed instructions  1per_instr    000tma_alu_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / tma_info_thread_slots tma_alu_op_utilization > 0.4 This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations  100%    020tma_assists BvIO;TopdownL4;tma_L4_group;tma_microcode_sequencer_group 34 * (FP_ASSIST.ANY + OTHER_ASSISTS.ANY) / tma_info_thread_slots tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1) This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY 100%    000tma_backend_bound BvOB;TmaL1;TopdownL1;tma_L1_group 1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / tma_info_thread_slots tma_backend_bound > 0.2 This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound 100%  TopdownL1  000tma_bottleneck_big_code BigFootprint;BvBC;Fed;Frontend;IcMiss;MemoryTLB 100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) tma_bottleneck_big_code > 20 Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)      010tma_bottleneck_branching_overhead BvBO;Ret 100 * ((BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIRED.NOP) / tma_info_thread_slots) tma_bottleneck_branching_overhead > 5 Total pipeline cost of instructions used for program control-flow - a subset of the Retiring category in TMA Total pipeline cost of instructions used for program control-flow - a subset of the Retiring category in TMA. Examples include function calls; loops and alignments. (A lower bound)     000tma_bottleneck_compute_bound_est BvCB;Cor;tma_issueComp 100 * (tma_core_bound * tma_divider / (tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_core_bound * (tma_ports_utilization / (tma_divider + tma_ports_utilization + tma_serializing_operation)) * (tma_ports_utilized_3m / (tma_ports_utilized_0 + tma_ports_utilized_1 + tma_ports_utilized_2 + tma_ports_utilized_3m))) tma_bottleneck_compute_bound_est > 20 Total pipeline cost when the execution is compute-bound - an estimation Total pipeline cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as well as when long-latency execution units are busy. Related metrics:      010tma_bottleneck_data_cache_memory_bandwidth BvMB;Mem;MemoryBW;Offcore;tma_issueBW 100 * (tma_memory_bound * (tma_dram_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * (tma_l1_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))) tma_bottleneck_data_cache_memory_bandwidth > 20 Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full     010tma_bottleneck_data_cache_memory_latency BvML;Mem;MemoryLat;Offcore;tma_issueLat 100 * (tma_memory_bound * (tma_dram_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * tma_l2_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) + tma_memory_bound * (tma_l1_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l1_latency_dependency / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_l1_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_lock_latency / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_l1_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_split_loads / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_split_stores / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency)) + tma_memory_bound * (tma_store_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency))) tma_bottleneck_data_cache_memory_latency > 20 Total pipeline cost of external Memory- or Cache-Latency related bottlenecks Total pipeline cost of external Memory- or Cache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_mem_latency     010tma_bottleneck_instruction_fetch_bw BvFB;Fed;FetchBW;Frontend 100 * (tma_frontend_bound - (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) - tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteers * (10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts)) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_bottleneck_big_code tma_bottleneck_instruction_fetch_bw > 20 Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)      010tma_bottleneck_irregular_overhead Bad;BvIO;Cor;Ret;tma_issueMS 100 * (tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteers * (10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts)) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts * tma_branch_mispredicts + tma_machine_clears * tma_other_nukes / tma_other_nukes + tma_core_bound * (tma_serializing_operation + tma_core_bound * RS_EVENTS.EMPTY_CYCLES / tma_info_thread_clks * tma_ports_utilized_0) / (tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations) tma_bottleneck_irregular_overhead > 10 Total pipeline cost of irregular execution (e.g Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloads, overhead in system services or virtualized environments). Related metrics: tma_microcode_sequencer, tma_ms_switches     010tma_bottleneck_memory_data_tlbs BvMT;Mem;MemoryTLB;Offcore;tma_issueTLB 100 * (tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency))) tma_bottleneck_memory_data_tlbs > 20 Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs) Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store     010tma_bottleneck_memory_synchronization BvMS;LockCont;Mem;Offcore;tma_issueSyncxn 100 * (tma_memory_bound * (tma_dram_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) * tma_remote_cache / (tma_local_mem + tma_remote_cache + tma_remote_mem) + tma_l3_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_contested_accesses + tma_data_sharing) / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full) + tma_store_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * tma_false_sharing / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency - tma_store_latency)) + tma_machine_clears * (1 - tma_other_nukes / tma_other_nukes)) tma_bottleneck_memory_synchronization > 10 Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors) Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors). Related metrics: tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache     010tma_bottleneck_mispredictions Bad;BadSpec;BrMispredicts;BvMP;tma_issueBM 100 * (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) tma_bottleneck_mispredictions > 20 Total pipeline cost of Branch Misprediction related bottlenecks Total pipeline cost of Branch Misprediction related bottlenecks. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost, tma_mispredicts_resteers     010tma_bottleneck_other_bottlenecks BvOB;Cor;Offcore 100 - (tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_data_cache_memory_bandwidth + tma_bottleneck_data_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work) tma_bottleneck_other_bottlenecks > 20 Total pipeline cost of remaining bottlenecks in the back-end Total pipeline cost of remaining bottlenecks in the back-end. Examples include data-dependencies (Core Bound when Low ILP) and other unlisted memory-related stalls     010tma_bottleneck_useful_work BvUW;Ret 100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIRED.NOP) / tma_info_thread_slots - tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations) tma_bottleneck_useful_work > 20 Total pipeline cost of "useful operations" - the portion of Retiring category not covered by Branching_Overhead nor Irregular_Overhead      010tma_branch_mispredicts BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15 This metric represents fraction of slots the CPU has wasted due to Branch Misprediction This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_bottleneck_mispredictions, tma_info_bad_spec_branch_misprediction_cost, tma_mispredicts_resteers 100%  TopdownL2  010tma_branch_resteers FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_thread_clks + tma_unknown_branches tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES 100%    000tma_cisc TopdownL4;tma_L4_group;tma_microcode_sequencer_group max(0, tma_microcode_sequencer - tma_assists) tma_cisc > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1) This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources 100%    010tma_clears_resteers BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueMC (1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_thread_clks tma_clears_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches 100%    000tma_code_stlb_miss FetchLat;MemoryTLB;TopdownL4;tma_L4_group;tma_itlb_misses_group ITLB_MISSES.WALK_ACTIVE / tma_info_thread_clks tma_code_stlb_miss > 0.05 & (tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by instruction fetches, performing a hardware page walk  100%    000tma_code_stlb_miss_2m FetchLat;MemoryTLB;TopdownL5;tma_L5_group;tma_code_stlb_miss_group tma_code_stlb_miss * ITLB_MISSES.WALK_COMPLETED_2M_4M / (ITLB_MISSES.WALK_COMPLETED_4K + ITLB_MISSES.WALK_COMPLETED_2M_4M) tma_code_stlb_miss_2m > 0.05 & (tma_code_stlb_miss > 0.05 & (tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))) This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 2 or 4 MB pages for (instruction) code accesses  100%    000tma_code_stlb_miss_4k FetchLat;MemoryTLB;TopdownL5;tma_L5_group;tma_code_stlb_miss_group tma_code_stlb_miss * ITLB_MISSES.WALK_COMPLETED_4K / (ITLB_MISSES.WALK_COMPLETED_4K + ITLB_MISSES.WALK_COMPLETED_2M_4M) tma_code_stlb_miss_4k > 0.05 & (tma_code_stlb_miss > 0.05 & (tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))) This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 4 KB pages for (instruction) code accesses  100%    000tma_contested_accesses BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (44 * tma_info_system_core_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD))) + 44 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_bottleneck_memory_synchronization, tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100%    010tma_cxl_mem_bound MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (((1 - ((19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) if #has_pmem > 0 else 0) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) if #has_pmem > 0 else 0))) if #has_pmem > 0 else 1)) * (CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_thread_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks - tma_l2_bound) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0) if #has_pmem > 0 else 0) tma_cxl_mem_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external CXL Memory by loads (e.g This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external CXL Memory by loads (e.g. 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory, PMM - Persistent Memory Module [from CLX to SPR] or any other CXL Type3 Memory [EMR onwards]) 100%    000tma_data_sharing BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 44 * tma_info_system_core_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_bottleneck_memory_synchronization, tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100%    010tma_decoder0_alone DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_issueD0;tma_mite_group (cpu@INST_DECODED.DECODERS\,cmask\=1@ - cpu@INST_DECODED.DECODERS\,cmask\=2@) / tma_info_core_core_clks / 2 tma_decoder0_alone > 0.1 & (tma_mite > 0.1 & tma_fetch_bandwidth > 0.2) This metric represents fraction of cycles where decoder-0 was the only active decoder This metric represents fraction of cycles where decoder-0 was the only active decoder. Related metrics: tma_few_uops_instructions 100%    000tma_divider BvCB;TopdownL3;tma_L3_group;tma_core_bound_group ARITH.DIVIDER_ACTIVE / tma_info_thread_clks tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric represents fraction of cycles where the Divider unit was active This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE 100%    000tma_dram_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_thread_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks - tma_l2_bound - tma_cxl_mem_bound if #has_pmem > 0 else CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_thread_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks - tma_l2_bound) tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS 100%    010tma_dsb DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group (IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / tma_info_core_core_clks / 2 tma_dsb > 0.15 & tma_fetch_bandwidth > 0.2 This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline.  For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here 100%    000tma_dsb_switches DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_thread_clks tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 100%    000tma_dtlb_load BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group min(9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\,cmask\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_bottleneck_memory_data_tlbs, tma_dtlb_store 100%    020tma_dtlb_store BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group (9 * cpu@DTLB_STORE_MISSES.STLB_HIT\,cmask\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / tma_info_core_core_clks tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses.  As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead.  Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page.  Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_bottleneck_memory_data_tlbs, tma_dtlb_load 100%    000tma_false_sharing BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group (110 * tma_info_system_core_frequency * (OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM + OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM) + 47.5 * tma_info_system_core_frequency * (OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE)) / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_bottleneck_memory_synchronization, tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100%    010tma_fb_full BvMB;MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group tma_info_memory_load_miss_real_latency * cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ / tma_info_thread_clks tma_fb_full > 0.3 This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_bottleneck_data_cache_memory_bandwidth, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores 100%    020tma_fetch_bandwidth FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB tma_frontend_bound - tma_fetch_latency tma_fetch_bandwidth > 0.2 This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues.  For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1;FRONTEND_RETIRED.LATENCY_GE_1;FRONTEND_RETIRED.LATENCY_GE_2. Related metrics: tma_dsb_switches, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 100%  TopdownL2  000tma_few_uops_instructions TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueD0 tma_heavy_operations - tma_microcode_sequencer tma_few_uops_instructions > 0.05 & tma_heavy_operations > 0.1 This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or more uops This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or more uops. This highly-correlates with the number of uops in such instructions. Related metrics: tma_decoder0_alone 100%    020tma_fp_arith HPC;TopdownL3;tma_L3_group;tma_light_operations_group tma_x87_use + tma_fp_scalar + tma_fp_vector tma_fp_arith > 0.2 & tma_light_operations > 0.6 This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired) This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of "Uops" CountDomain and FMA double-counting 100%    010tma_fp_assists HPC;TopdownL5;tma_L5_group;tma_assists_group 34 * FP_ASSIST.ANY / tma_info_thread_slots tma_fp_assists > 0.1 This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called Denormals) 100%    000tma_fp_vector Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\,umask\=0xfc@ / UOPS_RETIRED.RETIRE_SLOTS tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_fp_vector_512b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS tma_fp_vector_512b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_fused_instructions Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * UOPS_RETIRED.MACRO_FUSED / UOPS_RETIRED.RETIRE_SLOTS tma_fused_instructions > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Other_Light_Ops in MTL!)} 100%    000tma_heavy_operations Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group (UOPS_RETIRED.RETIRE_SLOTS + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY) / tma_info_thread_slots tma_heavy_operations > 0.1 This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.([ICL+] Note this may overcount due to approximation using indirect events; [ADL+]) 100%  TopdownL2  000tma_icache_misses BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group (ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\,cmask\=1\,edge@) / tma_info_thread_clks tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to instruction cache misses This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS 100%    000tma_info_bad_spec_branch_misprediction_cost Bad;BrMispredicts;tma_issueBM tma_bottleneck_mispredictions * tma_info_thread_slots / 4 / BR_MISP_RETIRED.ALL_BRANCHES / 100  Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear) Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_bottleneck_mispredictions, tma_branch_mispredicts, tma_mispredicts_resteers     010tma_info_bad_spec_spec_clears_ratio BrMispredicts INT_MISC.CLEARS_COUNT / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)  Speculative to Retired ratio of all clears (covering Mispredicts and nukes)      000tma_info_botlnk_l0_core_bound_likely Cor;SMT (100 * (1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if tma_info_system_smt_2t_utilization > 0.5 else 0) tma_info_botlnk_l0_core_bound_likely > 0.5 Probability of Core Bound bottleneck hidden by SMT-profiling artifacts      010tma_info_botlnk_l2_dsb_bandwidth DSB;Fed;FetchBW;tma_issueFB 100 * (tma_frontend_bound * (tma_fetch_bandwidth / (tma_fetch_bandwidth + tma_fetch_latency)) * (tma_dsb / (tma_dsb + tma_mite))) tma_info_botlnk_l2_dsb_bandwidth > 10 Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp     010tma_info_botlnk_l2_dsb_misses DSBmiss;Fed;tma_issueFB 100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite)) tma_info_botlnk_l2_dsb_misses > 10 Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp     010tma_info_botlnk_l2_ic_misses Fed;FetchLat;IcMiss;tma_issueFL 100 * (tma_fetch_latency * tma_icache_misses / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) tma_info_botlnk_l2_ic_misses > 5 Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck. Related metrics:      010tma_info_branches_callret Bad;Branches (BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES  Fraction of branches that are CALL or RET      000tma_info_branches_cond_nt Bad;Branches;CodeGen;PGO BR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRANCHES  Fraction of branches that are non-taken conditionals      000tma_info_branches_cond_tk Bad;Branches;CodeGen;PGO (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) / BR_INST_RETIRED.ALL_BRANCHES  Fraction of branches that are taken conditionals      000tma_info_branches_jump Bad;Branches (BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.COND - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES  Fraction of branches that are unconditional (direct or indirect) jumps      010tma_info_core_epc Power UOPS_EXECUTED.THREAD / tma_info_thread_clks  uops Executed per Cycle      000tma_info_core_flopc Flops;Ret (FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / tma_info_core_core_clks  Floating Point Operations Per Cycle      010tma_info_core_fp_arith_utilization Cor;Flops;HPC (FP_ARITH_INST_RETIRED.SCALAR + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\,umask\=0xfc@) / (2 * tma_info_core_core_clks)  Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width) Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)     000tma_info_frontend_dsb_coverage DSB;Fed;FetchBW;tma_issueFB IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS) tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 4 > 0.35 Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache) Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp     000tma_info_frontend_dsb_switch_cost DSBmiss DSB2MITE_SWITCHES.PENALTY_CYCLES / DSB2MITE_SWITCHES.COUNT  Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details      000tma_info_frontend_fetch_upc Fed;FetchBW UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\,cmask\=1@  Average number of Uops issued by front-end when it issued something      000tma_info_frontend_icache_miss_latency Fed;FetchLat;IcMiss ICACHE_16B.IFDATA_STALL / cpu@ICACHE_16B.IFDATA_STALL\,cmask\=1\,edge@ + 2  Average Latency for L1 instruction cache misses      000tma_info_frontend_ipdsb_miss_ret DSBmiss;Fed INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS tma_info_frontend_ipdsb_miss_ret < 50 Instructions per non-speculative DSB miss (lower number means higher occurrence rate)      000tma_info_frontend_l2mpki_code IcMiss 1e3 * FRONTEND_RETIRED.L2_MISS / INST_RETIRED.ANY  L2 cache true code cacheline misses per kilo instruction      000tma_info_frontend_l2mpki_code_all IcMiss 1e3 * L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY  L2 cache speculative code cacheline misses per kilo instruction      000tma_info_inst_mix_iparith Flops;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\,umask\=0xfc@) tma_info_inst_mix_iparith < 10 Instructions per FP Arithmetic instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW     000tma_info_inst_mix_iparith_avx512 Flops;FpVector;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) tma_info_inst_mix_iparith_avx512 < 10 Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting     000tma_info_inst_mix_ipflop Flops;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) tma_info_inst_mix_ipflop < 10 Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)      010tma_info_inst_mix_ipload InsType INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS tma_info_inst_mix_ipload < 3 Instructions per Load (lower number means higher occurrence rate)      000tma_info_inst_mix_ippause Flops;FpVector;InsType tma_info_inst_mix_instructions / ROB_MISC_EVENTS.PAUSE_INST  Instructions per PAUSE (lower number means higher occurrence rate)      000tma_info_inst_mix_ipstore InsType INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES tma_info_inst_mix_ipstore < 8 Instructions per Store (lower number means higher occurrence rate)      000tma_info_inst_mix_ipswpf Prefetches INST_RETIRED.ANY / SW_PREFETCH_ACCESS.ANY tma_info_inst_mix_ipswpf < 100 Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)      000tma_info_inst_mix_iptb Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN tma_info_inst_mix_iptb < 9 Instructions per taken branch Instructions per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_lcp     000tma_info_memory_core_l2_evictions_nonsilent_pki L2Evicts;Mem;Server 1e3 * L2_LINES_OUT.NON_SILENT / tma_info_inst_mix_instructions  Rate of non silent evictions from the L2 cache per Kilo instruction      000tma_info_memory_core_l2_evictions_silent_pki L2Evicts;Mem;Server 1e3 * L2_LINES_OUT.SILENT / tma_info_inst_mix_instructions  Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)      000tma_info_memory_fb_hpki CacheHits;Mem 1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY  Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)      000tma_info_memory_l1mpki CacheHits;Mem 1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY  L1 cache true misses per kilo instruction for retired demand loads      000tma_info_memory_l1mpki_load CacheHits;Mem 1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY  L1 cache true misses per kilo instruction for all demand loads (including speculative)      000tma_info_memory_l2mpki Backend;CacheHits;Mem 1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY  L2 cache true misses per kilo instruction for retired demand loads      000tma_info_memory_l3_cache_access_bw Mem;MemoryBW;Offcore 64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / tma_info_system_time  Average per-thread data access bandwidth to the L3 cache [GB / sec]      000tma_info_memory_l3mpki Mem 1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY  L3 cache true misses per kilo instruction for retired demand loads      000tma_info_memory_load_miss_real_latency Mem;MemoryBound;MemoryLat L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT)  Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)      000tma_info_memory_mix_uc_load_pki Mem 1e3 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY  Un-cacheable retired load per kilo instruction      000tma_info_memory_mlp Mem;MemoryBW;MemoryBound L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES  Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)     000tma_info_memory_tlb_code_stlb_mpki Fed;MemoryTLB 1e3 * ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY  STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)      000tma_info_memory_tlb_load_stlb_mpki Mem;MemoryTLB 1e3 * DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY  STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)      000tma_info_memory_tlb_page_walks_utilization Mem;MemoryTLB (ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING) / (2 * tma_info_core_core_clks) tma_info_memory_tlb_page_walks_utilization > 0.5 Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses      020tma_info_memory_tlb_store_stlb_mpki Mem;MemoryTLB 1e3 * DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY  STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)      000tma_info_pipeline_execute Cor;Pipeline;PortsUtil;SMT UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else cpu@UOPS_EXECUTED.THREAD\,cmask\=1@)  Mem;Backend;CacheHits      000tma_info_pipeline_fetch_dsb Fed;FetchBW IDQ.DSB_UOPS / IDQ.DSB_CYCLES_ANY  Average number of uops fetched from DSB per cycle      000tma_info_pipeline_fetch_mite Fed;FetchBW IDQ.MITE_UOPS / IDQ.MITE_CYCLES  Average number of uops fetched from MITE per cycle      000tma_info_pipeline_fetch_ms Fed;FetchLat;MicroSeq IDQ.MS_UOPS / cpu@IDQ.MS_UOPS\,cmask\=1@  Average number of uops fetched from MS per cycle      000tma_info_pipeline_ipassist MicroSeq;Pipeline;Ret;Retire INST_RETIRED.ANY / (FP_ASSIST.ANY + OTHER_ASSISTS.ANY) tma_info_pipeline_ipassist < 100e3 Instructions per a microcode Assist invocation Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate)     000tma_info_system_cxl_mem_read_bw MemOffcore;MemoryBW;Server;SoC (64 * UNC_M_PMM_RPQ_INSERTS / 1e9 / tma_info_system_time if #has_pmem > 0 else 0)  Average 3DXP Memory Bandwidth Use for reads [GB / sec]      000tma_info_system_cxl_mem_write_bw MemOffcore;MemoryBW;Server;SoC (64 * UNC_M_PMM_WPQ_INSERTS / 1e9 / tma_info_system_time if #has_pmem > 0 else 0)  Average 3DXP Memory Bandwidth Use for Writes [GB / sec]      000tma_info_system_dram_bw_use HPC;MemOffcore;MemoryBW;SoC;tma_issueBW 64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / tma_info_system_time  Average external Memory Bandwidth Use for reads and writes [GB / sec] Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_bottleneck_data_cache_memory_bandwidth, tma_fb_full, tma_mem_bandwidth, tma_sq_full     000tma_info_system_gflops Cor;Flops;HPC (FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1e9 / tma_info_system_time  Giga Floating Point Operations Per Second Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width     010tma_info_system_io_read_bw IoBW;MemOffcore;Server;SoC (UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3) * 4 / 1e9 / tma_info_system_time  Average IO (network or disk) Bandwidth Use for Reads [GB / sec] Average IO (network or disk) Bandwidth Use for Reads [GB / sec]. Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU     000tma_info_system_io_write_bw IoBW;MemOffcore;Server;SoC (UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3) * 4 / 1e9 / tma_info_system_time  Average IO (network or disk) Bandwidth Use for Writes [GB / sec] Average IO (network or disk) Bandwidth Use for Writes [GB / sec]. Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU     000tma_info_system_mem_dram_read_latency MemOffcore;MemoryLat;Server;SoC 1e9 * (UNC_M_RPQ_OCCUPANCY / UNC_M_RPQ_INSERTS) / imc_0@event\=0x0@  Average latency of data read request to external DRAM memory [in nanoseconds] Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches     000tma_info_system_mem_parallel_reads Mem;MemoryBW;SoC UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD@thresh\=1@  Average number of parallel data read requests to external memory Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches     000tma_info_system_mem_pmm_read_latency MemOffcore;MemoryLat;Server;SoC (1e9 * (UNC_M_PMM_RPQ_OCCUPANCY.ALL / UNC_M_PMM_RPQ_INSERTS) / imc_0@event\=0x0@ if #has_pmem > 0 else 0)  Average latency of data read request to external 3D X-Point memory [in nanoseconds] Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches     000tma_info_system_mem_read_latency Mem;MemoryLat;SoC 1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (tma_info_system_socket_clks / tma_info_system_time)  Average latency of data read request to external memory (in nanoseconds) Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)     000tma_info_system_power_license0_utilization Power (CORE_POWER.LVL0_TURBO_LICENSE / 2 / tma_info_core_core_clks if #SMT_on else CORE_POWER.LVL0_TURBO_LICENSE / tma_info_core_core_clks)  Fraction of Core cycles where the core was running with power-delivery for baseline license level 0 Fraction of Core cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes     000tma_info_system_power_license1_utilization Power (CORE_POWER.LVL1_TURBO_LICENSE / 2 / tma_info_core_core_clks if #SMT_on else CORE_POWER.LVL1_TURBO_LICENSE / tma_info_core_core_clks) tma_info_system_power_license1_utilization > 0.5 Fraction of Core cycles where the core was running with power-delivery for license level 1 Fraction of Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions     000tma_info_system_power_license2_utilization Power (CORE_POWER.LVL2_TURBO_LICENSE / 2 / tma_info_core_core_clks if #SMT_on else CORE_POWER.LVL2_TURBO_LICENSE / tma_info_core_core_clks) tma_info_system_power_license2_utilization > 0.5 Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX) Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX).  This includes high current AVX 512-bit instructions     000tma_info_system_socket_clks SoC cha_0@event\=0x0@  Socket actual clocks when any core is active on that socket      000tma_itlb_misses BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group ICACHE_TAG.STALLS / tma_info_thread_clks tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS 100%    000tma_l1_latency_dependency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_l1_bound_group min(2 * (MEM_INST_RETIRED.ALL_LOADS - MEM_LOAD_RETIRED.FB_HIT - MEM_LOAD_RETIRED.L1_MISS) * 20 / 100, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks tma_l1_latency_dependency > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric ([SKL+] roughly; [LNL]) estimates fraction of cycles with demand load accesses that hit the L1D cache This metric ([SKL+] roughly; [LNL]) estimates fraction of cycles with demand load accesses that hit the L1D cache. The short latency of the L1D cache may be exposed in pointer-chasing memory access patterns as an example. Sample with: MEM_LOAD_RETIRED.L1_HIT 100%    010tma_l2_bound BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks) tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to L2 cache accesses by loads This metric estimates how often the CPU was stalled due to L2 cache accesses by loads.  Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT 100%    010tma_l2_hit_latency MemoryLat;TopdownL4;tma_L4_group;tma_l2_bound_group 3.5 * tma_info_system_core_frequency * MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_l2_hit_latency > 0.05 & (tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles with demand load accesses that hit the L2 cache under unloaded scenarios (possibly L2 latency limited) This metric represents fraction of cycles with demand load accesses that hit the L2 cache under unloaded scenarios (possibly L2 latency limited).  Avoiding L1 cache misses (i.e. L1 misses/L2 hits) will improve the latency. Sample with: MEM_LOAD_RETIRED.L2_HIT 100%    000tma_l3_bound CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / tma_info_thread_clks tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core.  Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS 100%    000tma_l3_hit_latency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 17 * tma_info_system_core_frequency * (MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2)) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_bottleneck_data_cache_memory_latency, tma_mem_latency 100%    000tma_lcp FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB DECODE.LCP / tma_info_thread_clks tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs) This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb 100%    000tma_load_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * tma_info_core_core_clks) tma_load_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3 100%    020tma_load_stlb_hit MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group tma_dtlb_load - tma_load_stlb_miss tma_load_stlb_hit > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)  100%    020tma_load_stlb_miss MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group DTLB_LOAD_MISSES.WALK_ACTIVE / tma_info_thread_clks tma_load_stlb_miss > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk  100%    000tma_load_stlb_miss_1g MemoryTLB;TopdownL6;tma_L6_group;tma_load_stlb_miss_group tma_load_stlb_miss * DTLB_LOAD_MISSES.WALK_COMPLETED_1G / (DTLB_LOAD_MISSES.WALK_COMPLETED_4K + DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M + DTLB_LOAD_MISSES.WALK_COMPLETED_1G) tma_load_stlb_miss_1g > 0.05 & (tma_load_stlb_miss > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))) This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 1 GB pages for data load accesses  100%    020tma_load_stlb_miss_2m MemoryTLB;TopdownL6;tma_L6_group;tma_load_stlb_miss_group tma_load_stlb_miss * DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / (DTLB_LOAD_MISSES.WALK_COMPLETED_4K + DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M + DTLB_LOAD_MISSES.WALK_COMPLETED_1G) tma_load_stlb_miss_2m > 0.05 & (tma_load_stlb_miss > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))) This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 2 or 4 MB pages for data load accesses  100%    020tma_load_stlb_miss_4k MemoryTLB;TopdownL6;tma_L6_group;tma_load_stlb_miss_group tma_load_stlb_miss * DTLB_LOAD_MISSES.WALK_COMPLETED_4K / (DTLB_LOAD_MISSES.WALK_COMPLETED_4K + DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M + DTLB_LOAD_MISSES.WALK_COMPLETED_1G) tma_load_stlb_miss_4k > 0.05 & (tma_load_stlb_miss > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))) This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 4 KB pages for data load accesses  100%    020tma_local_mem Server;TopdownL5;tma_L5_group;tma_mem_latency_group 59.5 * tma_info_system_core_frequency * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_local_mem > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM 100%    000tma_lock_latency LockCont;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group (12 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (11 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / tma_info_thread_clks tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS. Related metrics: tma_store_latency 100%    010tma_machine_clears BadSpec;BvMS;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn tma_bad_speculation - tma_branch_mispredicts tma_machine_clears > 0.1 & tma_bad_speculation > 0.15 This metric represents fraction of slots the CPU has wasted due to Machine Clears This metric represents fraction of slots the CPU has wasted due to Machine Clears.  These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_bottleneck_memory_synchronization, tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache 100%  TopdownL2  010tma_mem_bandwidth BvMB;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=4@) / tma_info_thread_clks tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM).  The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_bottleneck_data_cache_memory_bandwidth, tma_fb_full, tma_info_system_dram_bw_use, tma_sq_full 100%    000tma_mem_latency BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM) This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM).  This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: tma_bottleneck_data_cache_memory_latency, tma_l3_hit_latency 100%    000tma_memory_bound Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group (CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * tma_backend_bound tma_memory_bound > 0.2 & tma_backend_bound > 0.2 This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two) 100%  TopdownL2  010tma_memory_operations Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY tma_memory_operations > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses  100%    000tma_microcode_sequencer MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / tma_info_thread_slots tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1 This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS. Related metrics: tma_bottleneck_irregular_overhead, tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_ms_switches 100%    000tma_mispredicts_resteers BadSpec;BrMispredicts;BvMP;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_thread_clks tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_bottleneck_mispredictions, tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost 100%    010tma_mixing_vectors TopdownL5;tma_L5_group;tma_issueMV;tma_ports_utilized_0_group UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY tma_mixing_vectors > 0.05 This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [ADL+] cycles) This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [ADL+] cycles). Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic. Related metrics: tma_ms_switches 100%    000tma_ms_switches FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO 2 * IDQ.MS_SWITCHES / tma_info_thread_clks tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_bottleneck_irregular_overhead, tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation 100%    000tma_non_fused_branches Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - UOPS_RETIRED.MACRO_FUSED) / UOPS_RETIRED.RETIRE_SLOTS tma_non_fused_branches > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused 100%    000tma_nop_instructions BvBO;Pipeline;TopdownL4;tma_L4_group;tma_other_light_ops_group tma_light_operations * INST_RETIRED.NOP / UOPS_RETIRED.RETIRE_SLOTS tma_nop_instructions > 0.1 & (tma_other_light_ops > 0.3 & tma_light_operations > 0.6) This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP_PS 100%    000tma_other_light_ops Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches)) tma_other_light_ops > 0.3 & tma_light_operations > 0.6 This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting 100%    010tma_other_mispredicts BrMispredicts;BvIO;TopdownL3;tma_L3_group;tma_branch_mispredicts_group max(tma_branch_mispredicts * (1 - BR_MISP_RETIRED.ALL_BRANCHES / (INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT)), 0.0001) tma_other_mispredicts > 0.05 & (tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15) This metric estimates fraction of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches or other types)  100%    010tma_other_nukes BvIO;Machine_Clears;TopdownL3;tma_L3_group;tma_machine_clears_group max(tma_machine_clears * (1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT), 0.0001) tma_other_nukes > 0.05 & (tma_machine_clears > 0.1 & tma_bad_speculation > 0.15) This metric represents fraction of slots the CPU has wasted due to Nukes (Machine Clears) not related to memory ordering  100%    010tma_ports_utilization PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group ((tma_ports_utilized_0 * tma_info_thread_clks + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / tma_info_thread_clks if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / tma_info_thread_clks) tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations 100%    010tma_ports_utilized_0 PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group EXE_ACTIVITY.EXE_BOUND_0_PORTS / tma_info_thread_clks tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric 100%    000tma_ports_utilized_1 PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group ((UOPS_EXECUTED.CORE_CYCLES_GE_1 - UOPS_EXECUTED.CORE_CYCLES_GE_2) / 2 if #SMT_on else EXE_ACTIVITY.1_PORTS_UTIL) / tma_info_core_core_clks tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Related metrics: tma_l1_bound 100%    000tma_ports_utilized_2 PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group ((UOPS_EXECUTED.CORE_CYCLES_GE_2 - UOPS_EXECUTED.CORE_CYCLES_GE_3) / 2 if #SMT_on else EXE_ACTIVITY.2_PORTS_UTIL) / tma_info_core_core_clks tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).  Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6 100%    000tma_ports_utilized_3m BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group (UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_3) / tma_info_core_core_clks tma_ports_utilized_3m > 0.4 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)  100%    000tma_remote_cache Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_issueSyncxn;tma_mem_latency_group (89.5 * tma_info_system_core_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + 89.5 * tma_info_system_core_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_remote_cache > 0.05 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD_PS. Related metrics: tma_bottleneck_memory_synchronization, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears 100%    020tma_remote_mem Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group 127 * tma_info_system_core_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_remote_mem > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM_PS 100%    000tma_serializing_operation BvIO;PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group;tma_issueSO PARTIAL_RAT_STALLS.SCOREBOARD / tma_info_thread_clks tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: PARTIAL_RAT_STALLS.SCOREBOARD. Related metrics: tma_ms_switches 100%    000tma_slow_pause TopdownL4;tma_L4_group;tma_serializing_operation_group 40 * ROB_MISC_EVENTS.PAUSE_INST / tma_info_thread_clks tma_slow_pause > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: MISC_RETIRED.PAUSE_INST 100%    000tma_split_loads TopdownL4;tma_L4_group;tma_l1_bound_group tma_info_memory_load_miss_real_latency * LD_BLOCKS.NO_SR / tma_info_thread_clks tma_split_loads > 0.3 This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS 100%    020tma_split_stores TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group MEM_INST_RETIRED.SPLIT_STORES / tma_info_core_core_clks tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents rate of split store accesses This metric represents rate of split store accesses.  Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4 100%    000tma_sq_full BvMB;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group (OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / tma_info_core_core_clks tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors) This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_bottleneck_data_cache_memory_bandwidth, tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth 100%    000tma_store_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group EXE_ACTIVITY.BOUND_ON_STORES / tma_info_thread_clks tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS 100%    000tma_store_latency BvML;LockCont;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group (L2_RQSTS.RFO_HIT * 11 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles the CPU spent handling L1D store misses This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency 100%    020tma_store_stlb_miss MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group DTLB_STORE_MISSES.WALK_ACTIVE / tma_info_core_core_clks tma_store_stlb_miss > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk  100%    000tma_store_stlb_miss_1g MemoryTLB;TopdownL6;tma_L6_group;tma_store_stlb_miss_group tma_store_stlb_miss * DTLB_STORE_MISSES.WALK_COMPLETED_1G / (DTLB_STORE_MISSES.WALK_COMPLETED_4K + DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M + DTLB_STORE_MISSES.WALK_COMPLETED_1G) tma_store_stlb_miss_1g > 0.05 & (tma_store_stlb_miss > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))) This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 1 GB pages for data store accesses  100%    020tma_store_stlb_miss_2m MemoryTLB;TopdownL6;tma_L6_group;tma_store_stlb_miss_group tma_store_stlb_miss * DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M / (DTLB_STORE_MISSES.WALK_COMPLETED_4K + DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M + DTLB_STORE_MISSES.WALK_COMPLETED_1G) tma_store_stlb_miss_2m > 0.05 & (tma_store_stlb_miss > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))) This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 2 or 4 MB pages for data store accesses  100%    020tma_store_stlb_miss_4k MemoryTLB;TopdownL6;tma_L6_group;tma_store_stlb_miss_group tma_store_stlb_miss * DTLB_STORE_MISSES.WALK_COMPLETED_4K / (DTLB_STORE_MISSES.WALK_COMPLETED_4K + DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M + DTLB_STORE_MISSES.WALK_COMPLETED_1G) tma_store_stlb_miss_4k > 0.05 & (tma_store_stlb_miss > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))) This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 4 KB pages for data store accesses  100%    020tma_unknown_branches BigFootprint;BvBC;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group 9 * BACLEARS.ANY / tma_info_thread_clks tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to new branch address clears This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches. Sample with: BACLEARS.ANY 100%    000tma_x87_use Compute;TopdownL4;tma_L4_group;tma_fp_arith_group tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric serves as an approximation of legacy x87 usage This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint 100%    000uncore_frequency  UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages) / 1e9 / duration_time  Uncore operating frequency in GHz  1GHz    000upi_data_receive_bw  UNC_UPI_RxL_FLITS.ALL_DATA * 7.111111111111111 / 1e6 / duration_time  Intel(R) Ultra Path Interconnect (UPI) data receive bandwidth (MB/sec)  1MB/s    000upi_data_transmit_bw  UNC_UPI_TxL_FLITS.ALL_DATA * 7.111111111111111 / 1e6 / duration_time  Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)  1MB/s    000lpm_mem_bw_pmm PMM Memory Bandwidth lpm_upi_bw UPI Bandwidth lpm_br_cond_mispred lpm_br;lpm_br_cond d_ratio(BR_MISP_RETIRED.CONDITIONAL, BR_INST_RETIRED.COND)  Retired conditional branch instructions mispredicted as a percentage of all conditional branches  100%    000lpm_cs_l2_misses lpm_cs d_ratio(L2_RQSTS.DEMAND_DATA_RD_MISS + L2_RQSTS.RFO_MISS + L2_RQSTS.CODE_RD_MISS + L2_RQSTS.PF_MISS, context\-switches)  L2 misses per context switch  1l2_misses/cs    000lpm_cstate_c0 lpm_cstate d_ratio(UNC_P_POWER_STATE_OCCUPANCY.CORES_C0, UNC_P_CLOCKTICKS)  C-State cores in C0/C1 (metric should be considered experimental as it contains experimental events)  1cores    000lpm_cstate_c3 lpm_cstate d_ratio(UNC_P_POWER_STATE_OCCUPANCY.CORES_C3, UNC_P_CLOCKTICKS)  C-State cores in C3 (metric should be considered experimental as it contains experimental events)  1cores    000lpm_cstate_c6 lpm_cstate d_ratio((max(UNC_P_POWER_STATE_OCCUPANCY.CORES_C6 - (UNC_P_POWER_STATE_OCCUPANCY.CORES_C0 + UNC_P_POWER_STATE_OCCUPANCY.CORES_C3 + UNC_P_POWER_STATE_OCCUPANCY.CORES_C6 - UNC_P_CLOCKTICKS * (#num_cores / #num_packages)), 0) if UNC_P_POWER_STATE_OCCUPANCY.CORES_C0 + UNC_P_POWER_STATE_OCCUPANCY.CORES_C3 + UNC_P_POWER_STATE_OCCUPANCY.CORES_C6 > UNC_P_CLOCKTICKS * (#num_cores / #num_packages) else UNC_P_POWER_STATE_OCCUPANCY.CORES_C6), UNC_P_CLOCKTICKS)  C-State cores in C6/C7 (metric should be considered experimental as it contains experimental events)  1cores    000lpm_dir_lookup_hits lpm_dir d_ratio(UNC_M2M_DIRECTORY_HIT.DIRTY_I@umask\=0xFF\,name\=UNC_M2M_DIRECTORY_HIT.ANY@, UNC_M2M_DIRECTORY_HIT.DIRTY_I@umask\=0xFF\,name\=UNC_M2M_DIRECTORY_HIT.ANY@ + UNC_M2M_DIRECTORY_MISS.DIRTY_I@umask\=0xFF\,name\=UNC_M2M_DIRECTORY_MISS.ANY@)    100%    000lpm_dir_lookup_misses lpm_dir d_ratio(UNC_M2M_DIRECTORY_MISS.DIRTY_I@umask\=0xFF\,name\=UNC_M2M_DIRECTORY_MISS.ANY@, UNC_M2M_DIRECTORY_HIT.DIRTY_I@umask\=0xFF\,name\=UNC_M2M_DIRECTORY_HIT.ANY@ + UNC_M2M_DIRECTORY_MISS.DIRTY_I@umask\=0xFF\,name\=UNC_M2M_DIRECTORY_MISS.ANY@)    100%    000lpm_dir_lookup_rate lpm_dir d_ratio(UNC_M2M_DIRECTORY_HIT.DIRTY_I@umask\=0xFF\,name\=UNC_M2M_DIRECTORY_HIT.ANY@ + UNC_M2M_DIRECTORY_MISS.DIRTY_I@umask\=0xFF\,name\=UNC_M2M_DIRECTORY_MISS.ANY@, duration_time)    1requests/s    000lpm_dir_update_bw lpm_dir d_ratio(UNC_M2M_DIRECTORY_UPDATE.ANY + UNC_CHA_DIR_UPDATE.HA@umask\=3\,name\=UNC_CHA_DIR_UPDATE.ANY@, duration_time)    6.4e-05MB/s    000lpm_dir_update_requests lpm_dir d_ratio(UNC_M2M_DIRECTORY_UPDATE.ANY + UNC_CHA_DIR_UPDATE.HA@umask\=3\,name\=UNC_CHA_DIR_UPDATE.ANY@, duration_time)    1requests/s    000lpm_fpu_128_double_of_total lpm_fpu;lpm_fpu_128;lpm_fpu_128_double d_ratio(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE * 2, FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 4 * FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + 4 * FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + 8 * FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE)  128-bit packed double floating point operations per second  100%    000lpm_fpu_128_single_of_total lpm_fpu;lpm_fpu_128;lpm_fpu_128_single d_ratio(FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE * 4, FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 4 * FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + 4 * FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + 8 * FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE)  128-bit packed single floating point operations per second  100%    000lpm_fpu_256_double_of_total lpm_fpu;lpm_fpu_256;lpm_fpu_256_double d_ratio(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE * 4, FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 4 * FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + 4 * FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + 8 * FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE)  128-bit packed double floating point operations per second  100%    000lpm_fpu_256_single_of_total lpm_fpu;lpm_fpu_256;lpm_fpu_256_single d_ratio(FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE * 8, FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 4 * FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + 4 * FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + 8 * FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE)  128-bit packed single floating point operations per second  100%    000lpm_fpu_512_double_flops lpm_fpu;lpm_fpu_512;lpm_fpu_512_double d_ratio(FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE * 8, duration_time)  128-bit packed double floating point operations per second  1flops/s    000lpm_fpu_512_double_of_total lpm_fpu;lpm_fpu_512;lpm_fpu_512_double d_ratio(FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE * 8, FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 4 * FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + 4 * FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + 8 * FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE)  128-bit packed double floating point operations per second  100%    000lpm_fpu_512_double_ops lpm_fpu;lpm_fpu_512;lpm_fpu_512_double d_ratio(FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE, duration_time)  128-bit packed double operations per second  1ops/s    000lpm_fpu_512_single_flops lpm_fpu;lpm_fpu_512;lpm_fpu_512_single d_ratio(FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE * 16, duration_time)  128-bit packed single floating point operations per second  1flops/s    000lpm_fpu_512_single_of_total lpm_fpu;lpm_fpu_512;lpm_fpu_512_single d_ratio(FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE * 16, FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 4 * FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + 4 * FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + 8 * FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE)  128-bit packed single floating point operations per second  100%    000lpm_fpu_512_single_ops lpm_fpu;lpm_fpu_512;lpm_fpu_512_single d_ratio(FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE, duration_time)  128-bit packed single operations per second  1ops/s    000lpm_fpu_64_double_of_total lpm_fpu;lpm_fpu_64;lpm_fpu_64_double d_ratio(FP_ARITH_INST_RETIRED.SCALAR_DOUBLE, FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 4 * FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + 4 * FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + 8 * FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE)  64-bit double floating point operations per second  100%    000lpm_fpu_64_single_of_total lpm_fpu;lpm_fpu_64;lpm_fpu_64_single d_ratio(FP_ARITH_INST_RETIRED.SCALAR_SINGLE, FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 4 * FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + 4 * FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + 8 * FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE)  64-bit single floating point operations per second  100%    000lpm_fpu_total_flopc lpm_fpu;lpm_fpu_total d_ratio(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 4 * FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + 4 * FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + 8 * FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE, cycles)  Floating point operations per cycle  1flops/cycle    000lpm_fpu_total_flops lpm_fpu;lpm_fpu_total d_ratio(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 4 * FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + 4 * FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + 8 * FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE, duration_time)  Floating point operations per second  1flops/s    000lpm_l2_evict_mef_lines_dropped lpm_l2;lpm_l2_evict;lpm_l2_evict_mef_lines d_ratio(IDI_MISC.WB_DOWNGRADE, duration_time)  L2 evictions M/E/F lines dropped per second  1dropped/s    000lpm_l2_evict_mef_lines_l3_hot_lru lpm_l2;lpm_l2_evict;lpm_l2_evict_mef_lines d_ratio(IDI_MISC.WB_UPGRADE, duration_time)  L2 evictions M/E/F lines L3 hot LRU per second  1HotLRU/s    000lpm_l2_hwpf_hits lpm_l2;lpm_l2_hwpf d_ratio(L2_RQSTS.PF_HIT, L2_RQSTS.PF_HIT + L2_RQSTS.PF_MISS)  L2 cache hardware prefetcher hits  100%    000lpm_l2_hwpf_misses lpm_l2;lpm_l2_hwpf d_ratio(L2_RQSTS.PF_MISS, duration_time)  L2 cache hardware prefetcher misses per second  100%    000lpm_l2_hwpf_misses lpm_l2;lpm_l2_hwpf d_ratio(L2_RQSTS.PF_MISS, L2_RQSTS.PF_HIT + L2_RQSTS.PF_MISS)  L2 cache hardware prefetcher misses  100%    000lpm_l2_hwpf_requests lpm_l2;lpm_l2_hwpf d_ratio(L2_RQSTS.PF_HIT + L2_RQSTS.PF_MISS, duration_time)  L2 cache hardware prefetcher requests per second  100%    000lpm_l2_hwpf_useless lpm_l2;lpm_l2_hwpf d_ratio(L2_LINES_OUT.USELESS_HWPF, duration_time)  L2 cache hardware prefetcher useless prefetches per second  100%    000lpm_mem_bw_pmm_read lpm_mem_bw;lpm_mem_bw_pmm d_ratio(UNC_M_PMM_RPQ_INSERTS, duration_time)  PMM memory read bandwidth  6.4e-05MB/s    000lpm_mem_bw_pmm_total lpm_mem_bw;lpm_mem_bw_pmm d_ratio(UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS, duration_time)  PMM memory write bandwidth  6.4e-05MB/s    000lpm_mem_bw_pmm_write lpm_mem_bw;lpm_mem_bw_pmm d_ratio(UNC_M_PMM_WPQ_INSERTS, duration_time)  PMM memory write bandwidth  6.4e-05MB/s    000lpm_mem_local_read lpm_mem;lpm_mem_local d_ratio(UNC_CHA_REQUESTS.READS_LOCAL, duration_time)  Local memory read bandwidth not including directory updates  6.4e-05MB/s    000lpm_mem_local_write lpm_mem;lpm_mem_local d_ratio(UNC_CHA_REQUESTS.WRITES_LOCAL, duration_time)  Local memory write bandwidth not including directory updates  6.4e-05MB/s    000lpm_mem_remote_read lpm_mem;lpm_mem_remote d_ratio(UNC_CHA_REQUESTS.READS_REMOTE, duration_time)  Remote memory read bandwidth not including directory updates  6.4e-05MB/s    000lpm_mem_remote_write lpm_mem;lpm_mem_remote d_ratio(UNC_CHA_REQUESTS.WRITES_REMOTE, duration_time)  Remote memory write bandwidth not including directory updates  6.4e-05MB/s    000lpm_mem_sat  d_ratio(UNC_CHA_FAST_ASSERTED.VERT, UNC_CHA_CLOCKTICKS)  Mesh Bandwidth saturation (% CHA cycles with FAST signal asserted, include UPI bandwidth saturation), lower is better (metric should be considered experimental as it contains experimental events)  100%    000lpm_miss_lat_loc lpm_miss_lat duration_time * 1e9 * UNC_CHA_TOR_OCCUPANCY.IA_MISS@filter_opc0\=0x202\,filter_opc1\=0x25a\,filter_loc\,filter_nm\,filter_not_nm@ / (UNC_CHA_CLOCKTICKS / source_count(UNC_CHA_TOR_INSERTS.IA_MISS@filter_opc0\=0x202\,filter_opc1\=0x25a\,filter_loc\,filter_nm\,filter_not_nm@) * UNC_CHA_TOR_INSERTS.IA_MISS@filter_opc0\=0x202\,filter_opc1\=0x25a\,filter_loc\,filter_nm\,filter_not_nm@)  Local to a socket miss latency in nanoseconds  1ns    000lpm_miss_lat_rem lpm_miss_lat duration_time * 1e9 * UNC_CHA_TOR_OCCUPANCY.IA_MISS@filter_opc0\=0x202\,filter_opc1\=0x25a\,filter_rem\,filter_nm\,filter_not_nm@ / (UNC_CHA_CLOCKTICKS / source_count(UNC_CHA_TOR_INSERTS.IA_MISS@filter_opc0\=0x202\,filter_opc1\=0x25a\,filter_rem\,filter_nm\,filter_not_nm@) * UNC_CHA_TOR_INSERTS.IA_MISS@filter_opc0\=0x202\,filter_opc1\=0x25a\,filter_rem\,filter_nm\,filter_not_nm@)  Remote to a socket miss latency in nanoseconds  1ns    000lpm_upi_bw_read lpm_upi_bw d_ratio(UNC_UPI_RxL_FLITS.ALL_DATA, duration_time)  UPI read bandwidth  7.111111111111111e-06MB/s    000lpm_upi_bw_write lpm_upi_bw d_ratio(UNC_UPI_TxL_FLITS.ALL_DATA, duration_time)  DDR memory write bandwidth  7.111111111111111e-06MB/s    000IoBW LLC_MISSES.PCIE_READ  UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3  PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0 Counts every read request for 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus 4Bytes    000LLC_MISSES.PCIE_WRITE  UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3  PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0 Counts every write request of 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus 4Bytes    000UNC_M_PMM_BANDWIDTH.TOTAL  UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS  Intel Optane DC persistent memory bandwidth total (MiB/sec). Derived from unc_m_pmm_rpq_inserts  6.103515625E-5MiB/sec    000UNC_M_PMM_READ_LATENCY  UNC_M_PMM_RPQ_OCCUPANCY.ALL / UNC_M_PMM_RPQ_INSERTS / UNC_M_CLOCKTICKS  Intel Optane DC persistent memory read latency (ns). Derived from unc_m_pmm_rpq_occupancy.all  6000000000ns    000power_channel_ppd  UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS * 100  Cycles where DRAM ranks are in power down (CKE) mode+C37 Counts cycles when all the ranks in the channel are in PPD (PreCharge Power Down) mode. If IBT (Input Buffer Terminators)=off is enabled, then this event counts the cycles in PPD mode. If IBT=off is not enabled, then this event counts the number of cycles when being in PPD mode could have been taken advantage of     000power_self_refresh  UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS * 100  Cycles Memory is in self refresh power mode Counts the number of cycles when the iMC (memory controller) is in self-refresh and has a clock. This happens in some ACPI CPU package C-states for the sleep levels. For example, the PCU (Power Control Unit) may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Intel? Dynamic Power Technology.  Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases     000IPC  INST_RETIRED.ANY / cycles  Instructions Per Cycle (per Logical Processor)      000CPI  1 / IPC  Cycles Per Instruction (per Logical Processor)      000CLKS  cycles  Per-Logical Processor actual clocks when the Logical Processor is active      000IpMispredict  INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES  Number of Instructions per non-speculative Branch Misprediction (JEClear)      000IpBranch  INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES  Instructions per Branch (lower number means higher occurrence rate)      000Instructions  INST_RETIRED.ANY  Total number of retired Instructions      000L3_Cache_Fill_BW  64 * LONGEST_LAT_CACHE.MISS / 1e9  Average per-core data fill bandwidth to the L3 cache [GB / sec]      000CPU_Utilization  CPU_CLK_UNHALTED.REF_TSC / msr@tsc@  Average CPU Utilization      000Average_Frequency  cycles / CPU_CLK_UNHALTED.REF_TSC * msr@tsc@ / 1e9  Measured Average Frequency for unhalted processors [GHz]      000Turbo_Utilization  cycles / CPU_CLK_UNHALTED.REF_TSC  Average Frequency Utilization relative nominal frequency      000Kernel_Utilization  cycles:k / cycles  Fraction of cycles spent in the Operating System (OS) Kernel mode      000lpm_br_cond_insn_between_branches lpm_br;lpm_br_cond d_ratio(instructions, BR_INST_RETIRED.TAKEN_JCC)  The number of instructions divided by the number of conditional branches  1insn    000lpm_br_cond_mispred lpm_br;lpm_br_cond d_ratio(BR_MISP_RETIRED.TAKEN_JCC, BR_INST_RETIRED.TAKEN_JCC)  Retired conditional branch instructions mispredicted as a percentage of all conditional branches  100%    000lpm_br_cond_retired lpm_br;lpm_br_cond d_ratio(BR_INST_RETIRED.TAKEN_JCC, duration_time)  Retired conditional branch instructions  1insn/s    000lpm_br_taken_mispred lpm_br;lpm_br_taken d_ratio(BR_MISP_RETIRED.TAKEN_JCC, BR_INST_RETIRED.ALL_BRANCHES)  The number of retired taken branch instructions that were mispredicted as a percentage of all taken branches  100%    000lpm_cs_br_taken lpm_cs d_ratio(BR_INST_RETIRED.TAKEN_JCC, context\-switches)  Branches taken per context switch  1br_taken/cs    000lpm_ldst_ret_lds_1 lpm_ldst;lpm_ldst_ret_lds d_ratio(max(MEM_UOPS_RETIRED.ALL_LOADS@cmask\=1@ - MEM_UOPS_RETIRED.ALL_LOADS@cmask\=2@, 0), CPU_CLK_UNHALTED.CORE_P)  Retired loads in 1 cycle  100%    020lpm_ldst_ret_lds_2 lpm_ldst;lpm_ldst_ret_lds d_ratio(max(MEM_UOPS_RETIRED.ALL_LOADS@cmask\=2@ - MEM_UOPS_RETIRED.ALL_LOADS@cmask\=3@, 0), CPU_CLK_UNHALTED.CORE_P)  Retired loads in 2 cycles  100%    020lpm_ldst_ret_lds_3 lpm_ldst;lpm_ldst_ret_lds d_ratio(MEM_UOPS_RETIRED.ALL_LOADS@cmask\=3@, CPU_CLK_UNHALTED.CORE_P)  Retired loads in 3 or more cycles  100%    000lpm_ldst_ret_sts_1 lpm_ldst;lpm_ldst_ret_sts d_ratio(max(MEM_UOPS_RETIRED.ALL_STORES@cmask\=1@ - MEM_UOPS_RETIRED.ALL_STORES@cmask\=2@, 0), CPU_CLK_UNHALTED.CORE_P)  Retired stores in 1 cycle  100%    020lpm_ldst_ret_sts_2 lpm_ldst;lpm_ldst_ret_sts d_ratio(max(MEM_UOPS_RETIRED.ALL_STORES@cmask\=2@ - MEM_UOPS_RETIRED.ALL_STORES@cmask\=3@, 0), CPU_CLK_UNHALTED.CORE_P)  Retired stores in 2 cycles  100%    020lpm_ldst_ret_sts_3 lpm_ldst;lpm_ldst_ret_sts d_ratio(MEM_UOPS_RETIRED.ALL_STORES@cmask\=3@, CPU_CLK_UNHALTED.CORE_P)  Retired stores in 3 more cycles  100%    000cpu_cstate_c0 cpu_cstate UNC_P_POWER_STATE_OCCUPANCY_CORES_C0 / UNC_P_CLOCKTICKS * #num_packages  The average number of cores that are in cstate C0 as observed by the power control unit (PCU)      000cpu_cstate_c6 cpu_cstate UNC_P_POWER_STATE_OCCUPANCY_CORES_C6 / UNC_P_CLOCKTICKS * #num_packages  The average number of cores are in cstate C6 as observed by the power control unit (PCU)      000dtlb_2nd_level_2mb_large_page_load_mpi  DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY  Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB 1per_instr    000dtlb_2nd_level_load_mpi  DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY  Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB 1per_instr    000dtlb_2nd_level_store_mpi  DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY  Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB 1per_instr    000io_bandwidth_read  UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1e6 / duration_time  Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU  1MB/s    000io_bandwidth_read_l3_miss  UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR * 64 / 1e6 / duration_time  Bandwidth of inbound IO reads that are initiated by end device controllers that are requesting memory from the CPU and miss the L3 cache  1MB/s    000io_bandwidth_read_local  UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL * 64 / 1e6 / duration_time  Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the local CPU socket  1MB/s    000io_bandwidth_read_remote  UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE * 64 / 1e6 / duration_time  Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from a remote CPU socket  1MB/s    000io_bandwidth_write  (UNC_CHA_TOR_INSERTS.IO_ITOM + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR) * 64 / 1e6 / duration_time  Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU  1MB/s    000io_bandwidth_write_l3_miss  (UNC_CHA_TOR_INSERTS.IO_MISS_ITOM + UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR) * 64 / 1e6 / duration_time  Bandwidth of inbound IO writes that are initiated by end device controllers that are writing memory to the CPU  1MB/s    000io_bandwidth_write_local  (UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL) * 64 / 1e6 / duration_time  Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the local CPU socket  1MB/s    000io_bandwidth_write_remote  (UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE) * 64 / 1e6 / duration_time  Bandwidth of IO writes that are initiated by end device controllers that are writing memory to a remote CPU socket  1MB/s    000io_full_write_l3_miss  UNC_CHA_TOR_INSERTS.IO_MISS_ITOM / UNC_CHA_TOR_INSERTS.IO_ITOM  Percentage of inbound full cacheline writes initiated by end device controllers that miss the L3 cache  100%    000io_partial_write_l3_miss  (UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_RFO) / (UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_RFO)  Percentage of inbound partial cacheline writes initiated by end device controllers that miss the L3 cache  100%    000io_read_l3_miss  UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR / UNC_CHA_TOR_INSERTS.IO_PCIRDCUR  Percentage of inbound reads initiated by end device controllers that miss the L3 cache  100%    000itlb_2nd_level_large_page_mpi  ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY  Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB 1per_instr    000itlb_2nd_level_mpi  ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY  Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB 1per_instr    000llc_code_read_mpi_demand_plus_prefetch  UNC_CHA_TOR_INSERTS.IA_MISS_CRD / INST_RETIRED.ANY  Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions  1per_instr    000llc_data_read_mpi_demand_plus_prefetch  (UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA + UNC_CHA_TOR_INSERTS.IA_MISS_DRD + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF) / INST_RETIRED.ANY  Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions  1per_instr    000llc_demand_data_read_miss_latency  1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD) * #num_packages)) * duration_time  Average latency of a last level cache (LLC) demand data read miss (read memory access) in nano seconds  1ns    000llc_demand_data_read_miss_latency_for_local_requests  1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL) * #num_packages)) * duration_time  Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to local memory in nano seconds  1ns    000llc_demand_data_read_miss_latency_for_remote_requests  1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE) * #num_packages)) * duration_time  Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to remote memory in nano seconds  1ns    000llc_demand_data_read_miss_to_dram_latency  1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR) * #num_packages)) * duration_time  Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to DRAM in nano seconds  1ns    000memory_extra_write_bw_due_to_directory_updates  (UNC_CHA_DIR_UPDATE.HA + UNC_CHA_DIR_UPDATE.TOR + UNC_M2M_DIRECTORY_UPDATE.ANY) * 64 / 1e6 / duration_time  Memory write bandwidth (MB/sec) caused by directory updates; includes DDR and Intel(R) Optane(TM) Persistent Memory(PMEM)  1MB/s    000numa_reads_addressed_to_local_dram  (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE)  Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches  100%    000numa_reads_addressed_to_remote_dram  (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE)  Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches  100%    000tma_alu_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5_11 + UOPS_DISPATCHED.PORT_6) / (5 * tma_info_core_core_clks) tma_alu_op_utilization > 0.4 This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations  100%    000tma_amx_busy BvCB;Compute;HPC;Server;TopdownL3;tma_L3_group;tma_core_bound_group EXE.AMX_BUSY / tma_info_core_core_clks tma_amx_busy > 0.5 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric estimates fraction of cycles where the Advanced Matrix eXtensions (AMX) execution engine was busy with tile (arithmetic) operations  100%    000tma_assists BvIO;TopdownL4;tma_L4_group;tma_microcode_sequencer_group 78 * ASSISTS.ANY / tma_info_thread_slots tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1) This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY 100%    000tma_avx_assists HPC;TopdownL5;tma_L5_group;tma_assists_group 63 * ASSISTS.SSE_AVX_MIX / tma_info_thread_slots tma_avx_assists > 0.1 This metric estimates fraction of slots the CPU retired uops as a result of handing SSE to AVX* or AVX* to SSE transition Assists  100%    000tma_backend_bound BvOB;Default;TmaL1;TopdownL1;tma_L1_group topdown\-be\-bound / (topdown\-fe\-bound + topdown\-bad\-spec + topdown\-retiring + topdown\-be\-bound) tma_backend_bound > 0.2 This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS 100%  TopdownL1;Default TopdownL1 000tma_bottleneck_compute_bound_est BvCB;Cor;tma_issueComp 100 * (tma_core_bound * tma_divider / (tma_amx_busy + tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_core_bound * tma_amx_busy / (tma_amx_busy + tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_core_bound * (tma_ports_utilization / (tma_amx_busy + tma_divider + tma_ports_utilization + tma_serializing_operation)) * (tma_ports_utilized_3m / (tma_ports_utilized_0 + tma_ports_utilized_1 + tma_ports_utilized_2 + tma_ports_utilized_3m))) tma_bottleneck_compute_bound_est > 20 Total pipeline cost when the execution is compute-bound - an estimation Total pipeline cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as well as when long-latency execution units are busy. Related metrics:      000tma_bottleneck_data_cache_memory_bandwidth BvMB;Mem;MemoryBW;Offcore;tma_issueBW 100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + 0 / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_fb_full / (tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))) tma_bottleneck_data_cache_memory_bandwidth > 20 Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full     000tma_bottleneck_data_cache_memory_latency BvML;Mem;MemoryLat;Offcore;tma_issueLat 100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + 0 / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l1_latency_dependency / (tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_lock_latency / (tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_split_loads / (tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_split_stores / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) tma_bottleneck_data_cache_memory_latency > 20 Total pipeline cost of external Memory- or Cache-Latency related bottlenecks Total pipeline cost of external Memory- or Cache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_mem_latency     000tma_bottleneck_instruction_fetch_bw BvFB;Fed;FetchBW;Frontend 100 * (tma_frontend_bound - (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) - (1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\,cmask\=1@) * (tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_ms)) - tma_bottleneck_big_code tma_bottleneck_instruction_fetch_bw > 20 Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)      000tma_bottleneck_irregular_overhead Bad;BvIO;Cor;Ret;tma_issueMS 100 * ((1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\,cmask\=1@) * (tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_ms) + 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts * tma_branch_mispredicts + tma_machine_clears * tma_other_nukes / tma_other_nukes + tma_core_bound * (tma_serializing_operation + RS.EMPTY_RESOURCE / tma_info_thread_clks * tma_ports_utilized_0) / (tma_amx_busy + tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations) tma_bottleneck_irregular_overhead > 10 Total pipeline cost of irregular execution (e.g Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloads, overhead in system services or virtualized environments). Related metrics: tma_microcode_sequencer, tma_ms_switches     000tma_bottleneck_memory_synchronization BvMS;LockCont;Mem;Offcore;tma_issueSyncxn 100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) * tma_remote_cache / (tma_local_mem + tma_remote_cache + tma_remote_mem) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_contested_accesses + tma_data_sharing) / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * tma_false_sharing / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores - tma_store_latency)) + tma_machine_clears * (1 - tma_other_nukes / tma_other_nukes)) tma_bottleneck_memory_synchronization > 10 Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors) Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors). Related metrics: tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache     000tma_bottleneck_useful_work BvUW;Ret 100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIRED.NOP) / tma_info_thread_slots - tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations) tma_bottleneck_useful_work > 20 Total pipeline cost of "useful operations" - the portion of Retiring category not covered by Branching_Overhead nor Irregular_Overhead      000tma_branch_mispredicts BadSpec;BrMispredicts;BvMP;Default;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM topdown\-br\-mispredict / (topdown\-fe\-bound + topdown\-bad\-spec + topdown\-retiring + topdown\-be\-bound) tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15 This metric represents fraction of slots the CPU has wasted due to Branch Misprediction This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS. Related metrics: tma_bottleneck_mispredictions, tma_info_bad_spec_branch_misprediction_cost, tma_mispredicts_resteers 100%  TopdownL2;Default TopdownL2 000tma_c01_wait C0Wait;TopdownL4;tma_L4_group;tma_serializing_operation_group CPU_CLK_UNHALTED.C01 / tma_info_thread_clks tma_c01_wait > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU was stalled due staying in C0.1 power-performance optimized state (Faster wakeup time; Smaller power savings)  100%    000tma_c02_wait C0Wait;TopdownL4;tma_L4_group;tma_serializing_operation_group CPU_CLK_UNHALTED.C02 / tma_info_thread_clks tma_c02_wait > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU was stalled due staying in C0.2 power-performance optimized state (Slower wakeup time; Larger power savings)  100%    000tma_clears_resteers BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueMC (1 - tma_branch_mispredicts / tma_bad_speculation) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_thread_clks tma_clears_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches 100%    000tma_code_l2_miss FetchLat;IcMiss;Offcore;TopdownL4;tma_L4_group;tma_icache_misses_group OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD / tma_info_thread_clks tma_code_l2_miss > 0.05 & (tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric estimates fraction of cycles the CPU was stalled due to instruction cache misses that miss in the L2 cache  100%    000tma_contested_accesses BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (76.6 * tma_info_system_core_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + 74.6 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS. Related metrics: tma_bottleneck_memory_synchronization, tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100%    000tma_core_bound Backend;Compute;Default;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group max(0, tma_backend_bound - tma_memory_bound) tma_core_bound > 0.1 & tma_backend_bound > 0.2 This metric represents fraction of slots where Core non-memory issues were of a bottleneck This metric represents fraction of slots where Core non-memory issues were of a bottleneck.  Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations) 100%  TopdownL2;Default TopdownL2 000tma_data_sharing BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 74.6 * tma_info_system_core_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD. Related metrics: tma_bottleneck_memory_synchronization, tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100%    010tma_divider BvCB;TopdownL3;tma_L3_group;tma_core_bound_group ARITH.DIV_ACTIVE / tma_info_thread_clks tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric represents fraction of cycles where the Divider unit was active This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIV_ACTIVE 100%    000tma_dram_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group MEMORY_ACTIVITY.STALLS_L3_MISS / tma_info_thread_clks tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS 100%    000tma_dtlb_load BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group min(7 * cpu@DTLB_LOAD_MISSES.STLB_HIT\,cmask\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMORY_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_bottleneck_memory_data_tlbs, tma_dtlb_store 100%    000tma_dtlb_store BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group (7 * cpu@DTLB_STORE_MISSES.STLB_HIT\,cmask\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / tma_info_core_core_clks tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses.  As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead.  Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page.  Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_bottleneck_memory_data_tlbs, tma_dtlb_load 100%    000tma_false_sharing BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group (170 * tma_info_system_core_frequency * OCR.DEMAND_RFO.L3_MISS@offcore_rsp\=0x103b800002@ + 81 * tma_info_system_core_frequency * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM) / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_bottleneck_memory_synchronization, tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100%    000tma_fb_full BvMB;MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group L1D_PEND_MISS.FB_FULL / tma_info_thread_clks tma_fb_full > 0.3 This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_bottleneck_data_cache_memory_bandwidth, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores 100%    000tma_fetch_bandwidth Default;FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB max(0, tma_frontend_bound - tma_fetch_latency) tma_fetch_bandwidth > 0.2 This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues.  For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1;FRONTEND_RETIRED.LATENCY_GE_1;FRONTEND_RETIRED.LATENCY_GE_2. Related metrics: tma_dsb_switches, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 100%  TopdownL2;Default TopdownL2 000tma_fetch_latency Default;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group topdown\-fetch\-lat / (topdown\-fe\-bound + topdown\-bad\-spec + topdown\-retiring + topdown\-be\-bound) - INT_MISC.UOP_DROPPING / tma_info_thread_slots tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15 This metric represents fraction of slots the CPU was stalled due to Frontend latency issues This metric represents fraction of slots the CPU was stalled due to Frontend latency issues.  For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS 100%  TopdownL2;Default TopdownL2 000tma_fp_assists HPC;TopdownL5;tma_L5_group;tma_assists_group 30 * ASSISTS.FP / tma_info_thread_slots tma_fp_assists > 0.1 This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called Denormals) 100%    000tma_fp_divider TopdownL4;tma_L4_group;tma_divider_group ARITH.FPDIV_ACTIVE / tma_info_thread_clks tma_fp_divider > 0.2 & (tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles where the Floating-Point Divider unit was active  100%    000tma_fp_scalar Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P (FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED2.SCALAR) / (tma_retiring * tma_info_thread_slots) tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_fp_vector Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P (FP_ARITH_INST_RETIRED.VECTOR + FP_ARITH_INST_RETIRED2.VECTOR) / (tma_retiring * tma_info_thread_slots) tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_fp_vector_128b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.128B_PACKED_HALF) / (tma_retiring * tma_info_thread_slots) tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting prior to LNL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_fp_vector_256b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.256B_PACKED_HALF) / (tma_retiring * tma_info_thread_slots) tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting prior to LNL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_fp_vector_512b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.512B_PACKED_HALF) / (tma_retiring * tma_info_thread_slots) tma_fp_vector_512b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_frontend_bound BvFB;BvIO;Default;PGO;TmaL1;TopdownL1;tma_L1_group topdown\-fe\-bound / (topdown\-fe\-bound + topdown\-bad\-spec + topdown\-retiring + topdown\-be\-bound) - INT_MISC.UOP_DROPPING / tma_info_thread_slots tma_frontend_bound > 0.15 This category represents fraction of slots where the processor's Frontend undersupplies its Backend This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS 100%  TopdownL1;Default TopdownL1 000tma_fused_instructions Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * INST_RETIRED.MACRO_FUSED / (tma_retiring * tma_info_thread_slots) tma_fused_instructions > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Other_Light_Ops in MTL!)} 100%    000tma_heavy_operations Default;Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group topdown\-heavy\-ops / (topdown\-fe\-bound + topdown\-bad\-spec + topdown\-retiring + topdown\-be\-bound) tma_heavy_operations > 0.1 This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.([ICL+] Note this may overcount due to approximation using indirect events; [ADL+]). Sample with: UOPS_RETIRED.HEAVY 100%  TopdownL2;Default TopdownL2 000tma_icache_misses BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group ICACHE_DATA.STALLS / tma_info_thread_clks tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to instruction cache misses This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS 100%    000tma_info_bad_spec_branch_misprediction_cost Bad;BrMispredicts;tma_issueBM tma_bottleneck_mispredictions * tma_info_thread_slots / 6 / BR_MISP_RETIRED.ALL_BRANCHES / 100  Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear) Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_bottleneck_mispredictions, tma_branch_mispredicts, tma_mispredicts_resteers     000tma_info_bad_spec_ipmisp_cond_ntaken Bad;BrMispredicts INST_RETIRED.ANY / BR_MISP_RETIRED.COND_NTAKEN tma_info_bad_spec_ipmisp_cond_ntaken < 200 Instructions per retired Mispredicts for conditional non-taken branches (lower number means higher occurrence rate)      000tma_info_bad_spec_ipmisp_cond_taken Bad;BrMispredicts INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN tma_info_bad_spec_ipmisp_cond_taken < 200 Instructions per retired Mispredicts for conditional taken branches (lower number means higher occurrence rate)      000tma_info_bad_spec_ipmisp_indirect Bad;BrMispredicts INST_RETIRED.ANY / BR_MISP_RETIRED.INDIRECT tma_info_bad_spec_ipmisp_indirect < 1e3 Instructions per retired Mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate)      000tma_info_bad_spec_ipmisp_ret Bad;BrMispredicts INST_RETIRED.ANY / BR_MISP_RETIRED.RET tma_info_bad_spec_ipmisp_ret < 500 Instructions per retired Mispredicts for return branches (lower number means higher occurrence rate)      000tma_info_botlnk_l2_dsb_bandwidth DSB;Fed;FetchBW;tma_issueFB 100 * (tma_frontend_bound * (tma_fetch_bandwidth / (tma_fetch_bandwidth + tma_fetch_latency)) * (tma_dsb / (tma_dsb + tma_mite + tma_ms))) tma_info_botlnk_l2_dsb_bandwidth > 10 Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp     000tma_info_botlnk_l2_dsb_misses DSBmiss;Fed;tma_issueFB 100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite + tma_ms)) tma_info_botlnk_l2_dsb_misses > 10 Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp     000tma_info_branches_cond_nt Bad;Branches;CodeGen;PGO BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES  Fraction of branches that are non-taken conditionals      000tma_info_branches_cond_tk Bad;Branches;CodeGen;PGO BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES  Fraction of branches that are taken conditionals      000tma_info_branches_jump Bad;Branches (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES  Fraction of branches that are unconditional (direct or indirect) jumps      000tma_info_core_core_clks SMT (CPU_CLK_UNHALTED.DISTRIBUTED if #SMT_on else tma_info_thread_clks)  Core actual clocks when any Logical Processor is active on the Physical Core      000tma_info_core_flopc Flops;Ret (FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED2.SCALAR_HALF + 2 * (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF) + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * (FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + FP_ARITH_INST_RETIRED.8_FLOPS) + 16 * (FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) + 32 * FP_ARITH_INST_RETIRED2.512B_PACKED_HALF) / tma_info_core_core_clks  Floating Point Operations Per Cycle      000tma_info_core_fp_arith_utilization Cor;Flops;HPC (FP_ARITH_DISPATCHED.PORT_0 + FP_ARITH_DISPATCHED.PORT_1 + FP_ARITH_DISPATCHED.PORT_5) / (2 * tma_info_core_core_clks)  Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width) Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)     000tma_info_frontend_dsb_coverage DSB;Fed;FetchBW;tma_issueFB IDQ.DSB_UOPS / UOPS_ISSUED.ANY tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 6 > 0.35 Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache) Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp     000tma_info_frontend_dsb_switch_cost DSBmiss DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@DSB2MITE_SWITCHES.PENALTY_CYCLES\,cmask\=1\,edge@  Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details      000tma_info_frontend_icache_miss_latency Fed;FetchLat;IcMiss ICACHE_DATA.STALLS / cpu@ICACHE_DATA.STALLS\,cmask\=1\,edge@  Average Latency for L1 instruction cache misses      000tma_info_frontend_unknown_branch_cost Fed INT_MISC.UNKNOWN_BRANCH_CYCLES / cpu@INT_MISC.UNKNOWN_BRANCH_CYCLES\,cmask\=1\,edge@  Average number of cycles the front-end was delayed due to an Unknown Branch detection Average number of cycles the front-end was delayed due to an Unknown Branch detection. See Unknown_Branches node     000tma_info_inst_mix_iparith Flops;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED2.SCALAR + (FP_ARITH_INST_RETIRED.VECTOR + FP_ARITH_INST_RETIRED2.VECTOR)) tma_info_inst_mix_iparith < 10 Instructions per FP Arithmetic instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW     000tma_info_inst_mix_iparith_avx128 Flops;FpVector;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.128B_PACKED_HALF) tma_info_inst_mix_iparith_avx128 < 10 Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting     000tma_info_inst_mix_iparith_avx256 Flops;FpVector;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.256B_PACKED_HALF) tma_info_inst_mix_iparith_avx256 < 10 Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting     000tma_info_inst_mix_iparith_avx512 Flops;FpVector;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.512B_PACKED_HALF) tma_info_inst_mix_iparith_avx512 < 10 Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting     000tma_info_inst_mix_iparith_scalar_hp Flops;FpScalar;InsType;Server INST_RETIRED.ANY / FP_ARITH_INST_RETIRED2.SCALAR tma_info_inst_mix_iparith_scalar_hp < 10 Instructions per FP Arithmetic Scalar Half-Precision instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic Scalar Half-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting     000tma_info_inst_mix_ipflop Flops;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED2.SCALAR_HALF + 2 * (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF) + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * (FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + FP_ARITH_INST_RETIRED.8_FLOPS) + 16 * (FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) + 32 * FP_ARITH_INST_RETIRED2.512B_PACKED_HALF) tma_info_inst_mix_ipflop < 10 Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)      000tma_info_inst_mix_ippause Flops;FpVector;InsType tma_info_inst_mix_instructions / CPU_CLK_UNHALTED.PAUSE_INST  Instructions per PAUSE (lower number means higher occurrence rate)      000tma_info_inst_mix_iptb Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN tma_info_inst_mix_iptb < 13 Instructions per taken branch Instructions per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_lcp     000tma_info_memory_l2mpki_rfo CacheMisses;Offcore 1e3 * L2_RQSTS.RFO_MISS / INST_RETIRED.ANY  Offcore requests (L2 cache miss) per kilo instruction for demand RFOs      000tma_info_memory_latency_data_l2_mlp Memory_BW;Offcore OFFCORE_REQUESTS_OUTSTANDING.DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD  Average Parallel L2 cache miss data reads      000tma_info_memory_latency_load_l2_mlp Memory_BW;Offcore OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / cpu@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\,cmask\=1@  Average Parallel L2 cache miss demand Loads      000tma_info_memory_latency_load_l3_miss_latency Memory_Lat;Offcore OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD / OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD  Average Latency for L3 cache miss demand Loads      000tma_info_memory_load_miss_real_latency Mem;MemoryBound;MemoryLat L1D_PEND_MISS.PENDING / MEM_LOAD_COMPLETED.L1_MISS_ANY  Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)      000tma_info_memory_mix_bus_lock_pki Mem 1e3 * SQ_MISC.BUS_LOCK / INST_RETIRED.ANY  "Bus lock" per kilo instruction      000tma_info_memory_mix_offcore_mwrite_any_pki Offcore;Server 1e3 * OCR.MODIFIED_WRITE.ANY_RESPONSE / tma_info_inst_mix_instructions  Off-core accesses per kilo instruction for modified write requests      000tma_info_memory_mix_offcore_read_any_pki CacheHits;Offcore;Server 1e3 * OCR.READS_TO_CORE.ANY_RESPONSE / tma_info_inst_mix_instructions  Off-core accesses per kilo instruction for reads-to-core requests (speculative; including in-core HW prefetches)      000tma_info_memory_mix_offcore_read_l3m_pki Offcore;Server 1e3 * OCR.READS_TO_CORE.L3_MISS / tma_info_inst_mix_instructions  L3 cache misses per kilo instruction for reads-to-core requests (speculative; including in-core HW prefetches)      000tma_info_memory_prefetches_useless_hwpf Prefetches L2_LINES_OUT.USELESS_HWPF / (L2_LINES_OUT.SILENT + L2_LINES_OUT.NON_SILENT) tma_info_memory_prefetches_useless_hwpf > 0.15 Rate of L2 HW prefetched lines that were not used by demand accesses      000tma_info_memory_soc_r2c_dram_bw HPC;Mem;MemoryBW;Offcore;Server 64 * OCR.READS_TO_CORE.DRAM / 1e9 / tma_info_system_time  Average DRAM BW for Reads-to-Core (R2C) covering for memory attached to local- and remote-socket Average DRAM BW for Reads-to-Core (R2C) covering for memory attached to local- and remote-socket. See R2C_Offcore_BW     000tma_info_memory_soc_r2c_l3m_bw HPC;Mem;MemoryBW;Offcore;Server 64 * OCR.READS_TO_CORE.L3_MISS / 1e9 / tma_info_system_time  Average L3-cache miss BW for Reads-to-Core (R2C) Average L3-cache miss BW for Reads-to-Core (R2C). This covering going to DRAM or other memory off-chip memory tears. See R2C_Offcore_BW     000tma_info_memory_soc_r2c_offcore_bw HPC;Mem;MemoryBW;Offcore;Server 64 * OCR.READS_TO_CORE.ANY_RESPONSE / 1e9 / tma_info_system_time  Average Off-core access BW for Reads-to-Core (R2C) Average Off-core access BW for Reads-to-Core (R2C). R2C account for demand or prefetch load/RFO/code access that fill data into the Core caches     000tma_info_memory_tlb_page_walks_utilization Mem;MemoryTLB (ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING) / (4 * tma_info_core_core_clks) tma_info_memory_tlb_page_walks_utilization > 0.5 Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses      000tma_info_pipeline_fetch_mite Fed;FetchBW IDQ.MITE_UOPS / IDQ.MITE_CYCLES_ANY  Average number of uops fetched from MITE per cycle      000tma_info_pipeline_ipassist MicroSeq;Pipeline;Ret;Retire INST_RETIRED.ANY / ASSISTS.ANY tma_info_pipeline_ipassist < 100e3 Instructions per a microcode Assist invocation Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate)     000tma_info_pipeline_retire Pipeline;Ret tma_retiring * tma_info_thread_slots / cpu@UOPS_RETIRED.SLOTS\,cmask\=1@  Average number of Uops retired in cycles where at least one uop has retired      000tma_info_pipeline_strings_cycles MicroSeq;Pipeline;Ret INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.SLOTS\,cmask\=1@ tma_info_pipeline_strings_cycles > 0.1 Estimated fraction of retirement-cycles dealing with repeat instructions      000tma_info_system_c0_wait C0Wait CPU_CLK_UNHALTED.C0_WAIT / tma_info_thread_clks tma_info_system_c0_wait > 0.05 Fraction of cycles the processor is waiting yet unhalted; covering legacy PAUSE instruction, as well as C0.1 / C0.2 power-performance optimized states      000tma_info_system_gflops Cor;Flops;HPC (FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED2.SCALAR_HALF + 2 * (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF) + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * (FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + FP_ARITH_INST_RETIRED.8_FLOPS) + 16 * (FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) + 32 * FP_ARITH_INST_RETIRED2.512B_PACKED_HALF) / 1e9 / tma_info_system_time  Giga Floating Point Operations Per Second Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width     000tma_info_system_io_read_bw IoBW;MemOffcore;Server;SoC UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1e9 / tma_info_system_time  Average IO (network or disk) Bandwidth Use for Reads [GB / sec] Average IO (network or disk) Bandwidth Use for Reads [GB / sec]. Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU     000tma_info_system_io_write_bw IoBW;MemOffcore;Server;SoC (UNC_CHA_TOR_INSERTS.IO_ITOM + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR) * 64 / 1e9 / tma_info_system_time  Average IO (network or disk) Bandwidth Use for Writes [GB / sec] Average IO (network or disk) Bandwidth Use for Writes [GB / sec]. Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU     000tma_info_system_mem_dram_read_latency MemOffcore;MemoryLat;Server;SoC 1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / uncore_cha_0@event\=0x1@  Average latency of data read request to external DRAM memory [in nanoseconds] Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches     000tma_info_system_mem_irq_duplicate_address LockCont;MemOffcore;Server;SoC UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH / UNC_CHA_CLOCKTICKS tma_info_system_mem_irq_duplicate_address > 0.1 Fraction of Uncore cycles where requests got rejected due to duplicate address already in IRQ ingress queue in the cache homing agent      000tma_info_system_smt_2t_utilization SMT (1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0)  Fraction of cycles where both hardware Logical Processors were active      000tma_info_system_socket_clks SoC uncore_cha_0@event\=0x1@  Socket actual clocks when any core is active on that socket      000tma_info_system_upi_data_transmit_bw Server;SoC UNC_UPI_TxL_FLITS.ALL_DATA * 64 / 9 / 1e6  Cross-socket Ultra Path Interconnect (UPI) data transmit bandwidth for data only [MB / sec]      000tma_info_thread_slots TmaL1;tma_L1_group TOPDOWN.SLOTS  Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)      000tma_info_thread_slots_utilization SMT;TmaL1;tma_L1_group (tma_info_thread_slots / (TOPDOWN.SLOTS / 2) if #SMT_on else 1)  Fraction of Physical Core issue-slots utilized by this Logical Processor      000tma_info_thread_uoppi Pipeline;Ret;Retire tma_retiring * tma_info_thread_slots / INST_RETIRED.ANY tma_info_thread_uoppi > 1.05 Uops Per Instruction      000tma_info_thread_uptb Branches;Fed;FetchBW tma_retiring * tma_info_thread_slots / BR_INST_RETIRED.NEAR_TAKEN tma_info_thread_uptb < 9 Uops per taken branch      000tma_int_vector_128b Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group;tma_issue2P (INT_VEC_RETIRED.ADD_128 + INT_VEC_RETIRED.VNNI_128) / (tma_retiring * tma_info_thread_slots) tma_int_vector_128b > 0.1 & (tma_int_operations > 0.1 & tma_light_operations > 0.6) This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_int_vector_256b Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group;tma_issue2P (INT_VEC_RETIRED.ADD_256 + INT_VEC_RETIRED.MUL_256 + INT_VEC_RETIRED.VNNI_256) / (tma_retiring * tma_info_thread_slots) tma_int_vector_256b > 0.1 & (tma_int_operations > 0.1 & tma_light_operations > 0.6) This metric represents 256-bit vector Integer ADD/SUB/SAD/MUL or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired This metric represents 256-bit vector Integer ADD/SUB/SAD/MUL or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_l1_bound CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group max((EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS) / tma_info_thread_clks, 0) tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled without loads missing the L1 Data (L1D) cache This metric estimates how often the CPU was stalled without loads missing the L1 Data (L1D) cache.  The L1D cache typically has the shortest latency.  However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1D. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1 100%    000tma_l1_latency_dependency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_l1_bound_group min(2 * (MEM_INST_RETIRED.ALL_LOADS - MEM_LOAD_RETIRED.FB_HIT - MEM_LOAD_RETIRED.L1_MISS) * 20 / 100, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMORY_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks tma_l1_latency_dependency > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric ([SKL+] roughly; [LNL]) estimates fraction of cycles with demand load accesses that hit the L1D cache This metric ([SKL+] roughly; [LNL]) estimates fraction of cycles with demand load accesses that hit the L1D cache. The short latency of the L1D cache may be exposed in pointer-chasing memory access patterns as an example. Sample with: MEM_LOAD_RETIRED.L1_HIT 100%    000tma_l2_bound BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to L2 cache accesses by loads This metric estimates how often the CPU was stalled due to L2 cache accesses by loads.  Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT 100%    000tma_l2_hit_latency MemoryLat;TopdownL4;tma_L4_group;tma_l2_bound_group 4.4 * tma_info_system_core_frequency * MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_l2_hit_latency > 0.05 & (tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles with demand load accesses that hit the L2 cache under unloaded scenarios (possibly L2 latency limited) This metric represents fraction of cycles with demand load accesses that hit the L2 cache under unloaded scenarios (possibly L2 latency limited).  Avoiding L1 cache misses (i.e. L1 misses/L2 hits) will improve the latency. Sample with: MEM_LOAD_RETIRED.L2_HIT 100%    000tma_l3_bound CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS) / tma_info_thread_clks tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core.  Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS 100%    000tma_l3_hit_latency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 32.6 * tma_info_system_core_frequency * (MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2)) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_bottleneck_data_cache_memory_latency, tma_mem_latency 100%    000tma_light_operations Default;Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group max(0, tma_retiring - tma_heavy_operations) tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation) This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .). Sample with: INST_RETIRED.PREC_DIST 100%  TopdownL2;Default TopdownL2 000tma_load_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group UOPS_DISPATCHED.PORT_2_3_10 / (3 * tma_info_core_core_clks) tma_load_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3_10 100%    000tma_load_stlb_miss_1g MemoryTLB;TopdownL6;tma_L6_group;tma_load_stlb_miss_group tma_load_stlb_miss * DTLB_LOAD_MISSES.WALK_COMPLETED_1G / (DTLB_LOAD_MISSES.WALK_COMPLETED_4K + DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M + DTLB_LOAD_MISSES.WALK_COMPLETED_1G) tma_load_stlb_miss_1g > 0.05 & (tma_load_stlb_miss > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))) This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 1 GB pages for data load accesses  100%    000tma_load_stlb_miss_2m MemoryTLB;TopdownL6;tma_L6_group;tma_load_stlb_miss_group tma_load_stlb_miss * DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / (DTLB_LOAD_MISSES.WALK_COMPLETED_4K + DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M + DTLB_LOAD_MISSES.WALK_COMPLETED_1G) tma_load_stlb_miss_2m > 0.05 & (tma_load_stlb_miss > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))) This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 2 or 4 MB pages for data load accesses  100%    000tma_load_stlb_miss_4k MemoryTLB;TopdownL6;tma_L6_group;tma_load_stlb_miss_group tma_load_stlb_miss * DTLB_LOAD_MISSES.WALK_COMPLETED_4K / (DTLB_LOAD_MISSES.WALK_COMPLETED_4K + DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M + DTLB_LOAD_MISSES.WALK_COMPLETED_1G) tma_load_stlb_miss_4k > 0.05 & (tma_load_stlb_miss > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))) This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 4 KB pages for data load accesses  100%    000tma_local_mem Server;TopdownL5;tma_L5_group;tma_mem_latency_group 72 * tma_info_system_core_frequency * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_local_mem > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM 100%    000tma_lock_latency LockCont;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group (16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / tma_info_thread_clks tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS. Related metrics: tma_store_latency 100%    010tma_machine_clears BadSpec;BvMS;Default;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn max(0, tma_bad_speculation - tma_branch_mispredicts) tma_machine_clears > 0.1 & tma_bad_speculation > 0.15 This metric represents fraction of slots the CPU has wasted due to Machine Clears This metric represents fraction of slots the CPU has wasted due to Machine Clears.  These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_bottleneck_memory_synchronization, tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache 100%  TopdownL2;Default TopdownL2 000tma_mba_stalls MemoryBW;Offcore;Server;TopdownL5;tma_L5_group;tma_mem_bandwidth_group INT_MISC.MBA_STALLS / tma_info_thread_clks tma_mba_stalls > 0.1 & (tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles where the core's performance was likely hurt due to memory bandwidth Allocation feature (RDT's memory bandwidth throttling)  100%    000tma_memory_bound Backend;Default;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group topdown\-mem\-bound / (topdown\-fe\-bound + topdown\-bad\-spec + topdown\-retiring + topdown\-be\-bound) tma_memory_bound > 0.2 & tma_backend_bound > 0.2 This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two) 100%  TopdownL2;Default TopdownL2 000tma_memory_fence TopdownL4;tma_L4_group;tma_serializing_operation_group 13 * MISC2_RETIRED.LFENCE / tma_info_thread_clks tma_memory_fence > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU was stalled due to LFENCE Instructions  100%    000tma_memory_operations Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * MEM_UOP_RETIRED.ANY / (tma_retiring * tma_info_thread_slots) tma_memory_operations > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses  100%    000tma_microcode_sequencer MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS UOPS_RETIRED.MS / tma_info_thread_slots tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1 This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: UOPS_RETIRED.MS. Related metrics: tma_bottleneck_irregular_overhead, tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_ms_switches 100%    000tma_mispredicts_resteers BadSpec;BrMispredicts;BvMP;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM tma_branch_mispredicts / tma_bad_speculation * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_thread_clks tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_bottleneck_mispredictions, tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost 100%    000tma_mite DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group (IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / tma_info_core_core_clks / 2 tma_mite > 0.1 & tma_fetch_bandwidth > 0.2 This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline) This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS 100%    000tma_mixing_vectors TopdownL5;tma_L5_group;tma_issueMV;tma_ports_utilized_0_group 160 * ASSISTS.SSE_AVX_MIX / tma_info_thread_clks tma_mixing_vectors > 0.05 This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [ADL+] cycles) This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [ADL+] cycles). Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic. Related metrics: tma_ms_switches 100%    000tma_ms MicroSeq;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group max(IDQ.MS_CYCLES_ANY, cpu@UOPS_RETIRED.MS\,cmask\=1@ / (UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY)) / tma_info_core_core_clks / 2.4 tma_ms > 0.05 & tma_fetch_bandwidth > 0.2 This metric represents Core fraction of cycles in which CPU was likely limited due to the Microcode Sequencer (MS) unit - see Microcode_Sequencer node for details  100%    000tma_ms_switches FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO 3 * cpu@UOPS_RETIRED.MS\,cmask\=1\,edge@ / (UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY) / tma_info_thread_clks tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_bottleneck_irregular_overhead, tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation 100%    000tma_non_fused_branches Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - INST_RETIRED.MACRO_FUSED) / (tma_retiring * tma_info_thread_slots) tma_non_fused_branches > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused 100%    000tma_nop_instructions BvBO;Pipeline;TopdownL4;tma_L4_group;tma_other_light_ops_group tma_light_operations * INST_RETIRED.NOP / (tma_retiring * tma_info_thread_slots) tma_nop_instructions > 0.1 & (tma_other_light_ops > 0.3 & tma_light_operations > 0.6) This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP 100%    000tma_other_mispredicts BrMispredicts;BvIO;TopdownL3;tma_L3_group;tma_branch_mispredicts_group max(tma_branch_mispredicts * (1 - BR_MISP_RETIRED.ALL_BRANCHES / (INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT)), 0.0001) tma_other_mispredicts > 0.05 & (tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15) This metric estimates fraction of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches or other types)  100%    000tma_other_nukes BvIO;Machine_Clears;TopdownL3;tma_L3_group;tma_machine_clears_group max(tma_machine_clears * (1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT), 0.0001) tma_other_nukes > 0.05 & (tma_machine_clears > 0.1 & tma_bad_speculation > 0.15) This metric represents fraction of slots the CPU has wasted due to Nukes (Machine Clears) not related to memory ordering  100%    000tma_page_faults TopdownL5;tma_L5_group;tma_assists_group 99 * ASSISTS.PAGE_FAULT / tma_info_thread_slots tma_page_faults > 0.05 This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults. A Page Fault may apply on first application access to a memory page. Note operating system handling of page faults accounts for the majority of its cost 100%    000tma_port_0 Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED.PORT_0 / tma_info_core_core_clks tma_port_0 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_port_1 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED.PORT_1 / tma_info_core_core_clks tma_port_1 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_port_6 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED.PORT_6 / tma_info_core_core_clks tma_port_6 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU). Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2 100%    000tma_ports_utilization PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group ((tma_ports_utilized_0 * tma_info_thread_clks + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_3_PORTS_UTIL)) / tma_info_thread_clks if ARITH.DIV_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_3_PORTS_UTIL) / tma_info_thread_clks) tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations 100%    020tma_ports_utilized_0 PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group (EXE_ACTIVITY.EXE_BOUND_0_PORTS + max(RS.EMPTY_RESOURCE - RESOURCE_STALLS.SCOREBOARD, 0)) / tma_info_thread_clks * (CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS) / tma_info_thread_clks tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric 100%    040tma_ports_utilized_1 PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group EXE_ACTIVITY.1_PORTS_UTIL / tma_info_thread_clks tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL. Related metrics: tma_l1_bound 100%    040tma_ports_utilized_2 PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group EXE_ACTIVITY.2_PORTS_UTIL / tma_info_thread_clks tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).  Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6 100%    000tma_ports_utilized_3m BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group UOPS_EXECUTED.CYCLES_GE_3 / tma_info_thread_clks tma_ports_utilized_3m > 0.4 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3 100%    000tma_remote_cache Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_issueSyncxn;tma_mem_latency_group (133 * tma_info_system_core_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + 133 * tma_info_system_core_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_remote_cache > 0.05 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD_PS. Related metrics: tma_bottleneck_memory_synchronization, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears 100%    000tma_remote_mem Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group 153 * tma_info_system_core_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_remote_mem > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM_PS 100%    000tma_retiring BvUW;Default;TmaL1;TopdownL1;tma_L1_group topdown\-retiring / (topdown\-fe\-bound + topdown\-bad\-spec + topdown\-retiring + topdown\-be\-bound) tma_retiring > 0.7 | tma_heavy_operations > 0.1 This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category.  Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved.  Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance.  For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS 100%  TopdownL1;Default TopdownL1 000tma_serializing_operation BvIO;PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group;tma_issueSO RESOURCE_STALLS.SCOREBOARD / tma_info_thread_clks + tma_c02_wait tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: RESOURCE_STALLS.SCOREBOARD. Related metrics: tma_ms_switches 100%    000tma_shuffles_256b HPC;Pipeline;TopdownL4;tma_L4_group;tma_other_light_ops_group tma_light_operations * INT_VEC_RETIRED.SHUFFLES / (tma_retiring * tma_info_thread_slots) tma_shuffles_256b > 0.1 & (tma_other_light_ops > 0.3 & tma_light_operations > 0.6) This metric represents fraction of slots where the CPU was retiring Shuffle operations of 256-bit vector size (FP or Integer) This metric represents fraction of slots where the CPU was retiring Shuffle operations of 256-bit vector size (FP or Integer). Shuffles may incur slow cross "vector lane" data transfers 100%    000tma_slow_pause TopdownL4;tma_L4_group;tma_serializing_operation_group CPU_CLK_UNHALTED.PAUSE / tma_info_thread_clks tma_slow_pause > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: CPU_CLK_UNHALTED.PAUSE_INST 100%    000tma_split_loads TopdownL4;tma_L4_group;tma_l1_bound_group tma_info_memory_load_miss_real_latency * LD_BLOCKS.NO_SR / tma_info_thread_clks tma_split_loads > 0.3 This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS 100%    000tma_sq_full BvMB;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group (XQ.FULL_CYCLES + L1D_PEND_MISS.L2_STALLS) / tma_info_thread_clks tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors) This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_bottleneck_data_cache_memory_bandwidth, tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth 100%    000tma_store_latency BvML;LockCont;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group (MEM_STORE_RETIRED.L2_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles the CPU spent handling L1D store misses This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency 100%    000tma_store_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_8) / (4 * tma_info_core_core_clks) tma_store_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations. Sample with: UOPS_DISPATCHED.PORT_7_8 100%    000tma_store_stlb_miss_1g MemoryTLB;TopdownL6;tma_L6_group;tma_store_stlb_miss_group tma_store_stlb_miss * DTLB_STORE_MISSES.WALK_COMPLETED_1G / (DTLB_STORE_MISSES.WALK_COMPLETED_4K + DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M + DTLB_STORE_MISSES.WALK_COMPLETED_1G) tma_store_stlb_miss_1g > 0.05 & (tma_store_stlb_miss > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))) This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 1 GB pages for data store accesses  100%    000tma_store_stlb_miss_2m MemoryTLB;TopdownL6;tma_L6_group;tma_store_stlb_miss_group tma_store_stlb_miss * DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M / (DTLB_STORE_MISSES.WALK_COMPLETED_4K + DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M + DTLB_STORE_MISSES.WALK_COMPLETED_1G) tma_store_stlb_miss_2m > 0.05 & (tma_store_stlb_miss > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))) This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 2 or 4 MB pages for data store accesses  100%    000tma_store_stlb_miss_4k MemoryTLB;TopdownL6;tma_L6_group;tma_store_stlb_miss_group tma_store_stlb_miss * DTLB_STORE_MISSES.WALK_COMPLETED_4K / (DTLB_STORE_MISSES.WALK_COMPLETED_4K + DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M + DTLB_STORE_MISSES.WALK_COMPLETED_1G) tma_store_stlb_miss_4k > 0.05 & (tma_store_stlb_miss > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))) This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 4 KB pages for data store accesses  100%    000tma_streaming_stores MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueSmSt;tma_store_bound_group 9 * OCR.STREAMING_WR.ANY_RESPONSE / tma_info_thread_clks tma_streaming_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates how often CPU was stalled  due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores This metric estimates how often CPU was stalled  due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck. Sample with: OCR.STREAMING_WR.ANY_RESPONSE. Related metrics: tma_fb_full 100%    000tma_unknown_branches BigFootprint;BvBC;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group INT_MISC.UNKNOWN_BRANCH_CYCLES / tma_info_thread_clks tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to new branch address clears This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches. Sample with: FRONTEND_RETIRED.UNKNOWN_BRANCH 100%    000lpm_fpu_total_flopc lpm_fpu;lpm_fpu_total d_ratio(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 4 * FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + 4 * FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + 8 * FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE, cycles)  Floating point operations per cycle  1flops/cycle    020lpm_miss_lat_loc lpm_miss_lat duration_time * 1e9 * UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL / (UNC_CHA_CLOCKTICKS / source_count(UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL) * UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL)  Local to a socket miss latency in nanoseconds  1ns    000lpm_miss_lat_rem lpm_miss_lat duration_time * 1e9 * UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE / (UNC_CHA_CLOCKTICKS / source_count(UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE) * UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE)  Remote to a socket miss latency in nanoseconds  1ns    000tma_mem_bandwidth_group Metrics contributing to tma_mem_bandwidth category lpm_br_total_insn_fe_resteers lpm_br;lpm_br_total d_ratio(BACLEARS.ALL, duration_time)  The number of resync branches per second  1req/s    000cpu_utilization  tma_info_system_cpu_utilization  Percentage of time spent in the active CPU power state C0  100%    000io_full_write_l3_miss  UNC_CHA_TOR_INSERTS.IO_MISS_ITOM / UNC_CHA_TOR_INSERTS.IO_ITOM  The percent of inbound full cache line writes initiated by IO that miss the L3 cache  100%    000io_msi  UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX_POSTED / duration_time  Message Signaled Interrupts (MSI) per second sent by the integrated I/O traffic controller (IIO) to System Configuration Controller (Ubox)  1per_sec    000io_partial_write_l3_miss  (UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_RFO) / (UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_RFO)  The percent of inbound partial writes initiated by IO that miss the L3 cache  100%    000io_read_l3_miss  UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR / UNC_CHA_TOR_INSERTS.IO_PCIRDCUR  The percent of inbound reads initiated by IO that miss the L3 cache  100%    000l1_i_code_read_misses_with_prefetches_per_instr  ICACHE.MISSES / INST_RETIRED.ANY  Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions  1per_instr    000l2_mpi  LONGEST_LAT_CACHE.REFERENCE / INST_RETIRED.ANY  Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions  1per_instr    000llc_code_read_mpi_demand_plus_prefetch  (UNC_CHA_TOR_INSERTS.IA_MISS_CRD + UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF) / INST_RETIRED.ANY  Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions  1per_instr    000llc_data_read_mpi_demand_plus_prefetch  (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF + UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA) / INST_RETIRED.ANY  Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions  1per_instr    000loads_retired_per_instr  MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY  Load operations retired per instruction  1per_instr    000memory_bandwidth_read  (UNC_M_CAS_COUNT_SCH0.RD + UNC_M_CAS_COUNT_SCH1.RD) * 64 / 1e6 / duration_time  DDR memory read bandwidth (MB/sec)  1MB/s    000memory_bandwidth_total  (UNC_M_CAS_COUNT_SCH0.RD + UNC_M_CAS_COUNT_SCH1.RD + UNC_M_CAS_COUNT_SCH0.WR + UNC_M_CAS_COUNT_SCH1.WR) * 64 / 1e6 / duration_time  DDR memory bandwidth (MB/sec)  1MB/s    000memory_bandwidth_write  (UNC_M_CAS_COUNT_SCH0.WR + UNC_M_CAS_COUNT_SCH1.WR) * 64 / 1e6 / duration_time  DDR memory write bandwidth (MB/sec)  1MB/s    000stores_retired_per_instr  MEM_UOPS_RETIRED.ALL_STORES / INST_RETIRED.ANY  Store operations retired per instruction  1per_instr    000tma_backend_bound TopdownL1;tma_L1_group TOPDOWN_BE_BOUND.ALL_P / (6 * CPU_CLK_UNHALTED.CORE) tma_backend_bound > 0.1 Counts the total number of issue slots that were not consumed by the backend due to backend stalls Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count 100%  TopdownL1  000tma_bad_speculation TopdownL1;tma_L1_group TOPDOWN_BAD_SPECULATION.ALL_P / (6 * CPU_CLK_UNHALTED.CORE) tma_bad_speculation > 0.15 Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear 100%  TopdownL1  000tma_branch_detect TopdownL3;tma_L3_group;tma_ifetch_latency_group TOPDOWN_FE_BOUND.BRANCH_DETECT / (6 * CPU_CLK_UNHALTED.CORE) tma_branch_detect > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches 100%    000tma_branch_mispredicts TopdownL2;tma_L2_group;tma_bad_speculation_group TOPDOWN_BAD_SPECULATION.MISPREDICT / (6 * CPU_CLK_UNHALTED.CORE) tma_branch_mispredicts > 0.05 & tma_bad_speculation > 0.15 Counts the number of issue slots that were not consumed by the backend due to branch mispredicts  100%  TopdownL2  000tma_branch_resteer TopdownL3;tma_L3_group;tma_ifetch_latency_group TOPDOWN_FE_BOUND.BRANCH_RESTEER / (6 * CPU_CLK_UNHALTED.CORE) tma_branch_resteer > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch  100%    000tma_cisc TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group TOPDOWN_FE_BOUND.CISC / (6 * CPU_CLK_UNHALTED.CORE) tma_cisc > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to the microcode sequencer (MS)  100%    000tma_core_bound TopdownL2;tma_L2_group;tma_backend_bound_group TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS / (6 * CPU_CLK_UNHALTED.CORE) tma_core_bound > 0.1 & tma_backend_bound > 0.1 Counts the number of cycles due to backend bound stalls that are bounded by core restrictions and not attributed to an outstanding load or stores, or resource limitation  100%  TopdownL2  000tma_decode TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group TOPDOWN_FE_BOUND.DECODE / (6 * CPU_CLK_UNHALTED.CORE) tma_decode > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to decode stalls  100%    000tma_fast_nuke TopdownL3;tma_L3_group;tma_machine_clears_group TOPDOWN_BAD_SPECULATION.FASTNUKE / (6 * CPU_CLK_UNHALTED.CORE) tma_fast_nuke > 0.05 & (tma_machine_clears > 0.05 & tma_bad_speculation > 0.15) Counts the number of issue slots that were not consumed by the backend due to a machine clear that does not require the use of microcode, classified as a fast nuke, due to memory ordering, memory disambiguation and memory renaming  100%    000tma_frontend_bound TopdownL1;tma_L1_group TOPDOWN_FE_BOUND.ALL_P / (6 * CPU_CLK_UNHALTED.CORE) tma_frontend_bound > 0.2 Counts the number of issue slots that were not consumed by the backend due to frontend stalls  100%  TopdownL1  000tma_icache_misses TopdownL3;tma_L3_group;tma_ifetch_latency_group TOPDOWN_FE_BOUND.ICACHE / (6 * CPU_CLK_UNHALTED.CORE) tma_icache_misses > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to instruction cache misses  100%    000tma_ifetch_bandwidth TopdownL2;tma_L2_group;tma_frontend_bound_group TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH / (6 * CPU_CLK_UNHALTED.CORE) tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2 Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations  100%  TopdownL2  000tma_ifetch_latency TopdownL2;tma_L2_group;tma_frontend_bound_group TOPDOWN_FE_BOUND.FRONTEND_LATENCY / (6 * CPU_CLK_UNHALTED.CORE) tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2 Counts the number of issue slots that were not delivered by the frontend due to frontend latency restrictions due to icache misses, itlb misses, branch detection, and resteer limitations  100%  TopdownL2  000tma_info_arith_inst_mix_ipflop Flops INST_RETIRED.ANY / FP_FLOPS_RETIRED.ALL  Instructions per Floating Point (FP) Operation      000tma_info_arith_inst_mix_ipfparith_avx128 Flops INST_RETIRED.ANY / (FP_INST_RETIRED.128B_DP + FP_INST_RETIRED.128B_SP)  Instructions per FP Arithmetic AVX/SSE 128-bit instruction      000tma_info_arith_inst_mix_ipfparith_scalar_dp Flops INST_RETIRED.ANY / FP_INST_RETIRED.64B_DP  Instructions per FP Arithmetic Scalar Double-Precision instruction      000tma_info_arith_inst_mix_ipfparith_scalar_sp Flops INST_RETIRED.ANY / FP_INST_RETIRED.32B_SP  Instructions per FP Arithmetic Scalar Single-Precision instruction      000tma_info_bottleneck_%_ifetch_miss_bound_cycles Ifetch 100 * MEM_BOUND_STALLS_IFETCH.ALL / CPU_CLK_UNHALTED.CORE  Percentage of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icache or ITLB Miss Percentage of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icache or ITLB Miss. See Info.Ifetch_Bound     000tma_info_bottleneck_%_load_miss_bound_cycles Load_Store_Miss 100 * MEM_BOUND_STALLS_LOAD.ALL / CPU_CLK_UNHALTED.CORE  Percentage of time that retirement is stalled due to an L1 miss Percentage of time that retirement is stalled due to an L1 miss. See Info.Load_Miss_Bound     000tma_info_br_inst_mix_ipcall  INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL  Instruction per (near) call (lower number means higher occurrence rate)      000tma_info_core_flopc Flops FP_FLOPS_RETIRED.ALL / CPU_CLK_UNHALTED.CORE  Floating Point Operations Per Cycle      000tma_info_core_upi  TOPDOWN_RETIRING.ALL_P / INST_RETIRED.ANY  Uops Per Instruction      000tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l2hit  100 * MEM_BOUND_STALLS_IFETCH.L2_HIT / MEM_BOUND_STALLS_IFETCH.ALL  Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L2      000tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l2miss  100 * (MEM_BOUND_STALLS_IFETCH.LLC_HIT + MEM_BOUND_STALLS_IFETCH.LLC_MISS) / MEM_BOUND_STALLS_IFETCH.ALL  Percentage of ifetch miss bound stalls, where the ifetch miss doesn't hit in the L2      000tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l3hit  100 * MEM_BOUND_STALLS_IFETCH.LLC_HIT / MEM_BOUND_STALLS_IFETCH.ALL  Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L3      000tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l3miss  100 * MEM_BOUND_STALLS_IFETCH.LLC_MISS / MEM_BOUND_STALLS_IFETCH.ALL  Percentage of ifetch miss bound stalls, where the ifetch miss subsequently misses in the L3      000tma_info_load_miss_bound_%_loadmissbound_with_l2hit load_store_bound 100 * MEM_BOUND_STALLS_LOAD.L2_HIT / MEM_BOUND_STALLS_LOAD.ALL  Percentage of memory bound stalls where retirement is stalled due to an L1 miss that hit the L2      000tma_info_load_miss_bound_%_loadmissbound_with_l2miss load_store_bound 100 * (MEM_BOUND_STALLS_LOAD.LLC_HIT + MEM_BOUND_STALLS_LOAD.LLC_MISS) / MEM_BOUND_STALLS_LOAD.ALL  Percentage of memory bound stalls where retirement is stalled due to an L1 miss that subsequently misses in the L2      000tma_info_load_miss_bound_%_loadmissbound_with_l3hit load_store_bound 100 * MEM_BOUND_STALLS_LOAD.LLC_HIT / MEM_BOUND_STALLS_LOAD.ALL  Percentage of memory bound stalls where retirement is stalled due to an L1 miss that hit the L3      000tma_info_load_miss_bound_%_loadmissbound_with_l3miss load_store_bound 100 * MEM_BOUND_STALLS_LOAD.LLC_MISS / MEM_BOUND_STALLS_LOAD.ALL  Percentage of memory bound stalls where retirement is stalled due to an L1 miss that subsequently misses the L3      000tma_info_load_store_bound_load_bound load_store_bound 100 * (LD_HEAD.L1_BOUND_AT_RET + MEM_BOUND_STALLS_LOAD.ALL) / CPU_CLK_UNHALTED.CORE  Counts the number of cycles that the oldest load of the load buffer is stalled at retirement      000tma_info_mem_exec_blocks_%_loads_with_adressaliasing  100 * LD_BLOCKS.ADDRESS_ALIAS / MEM_UOPS_RETIRED.ALL_LOADS  Percentage of total non-speculative loads with an address aliasing block      000tma_info_mem_mix_memload_ratio  1e3 * MEM_UOPS_RETIRED.ALL_LOADS / TOPDOWN_RETIRING.ALL_P  Ratio of mem load uops to all uops      000tma_info_serialization_%_tpause_cycles  100 * SERIALIZATION.C01_MS_SCB / (6 * CPU_CLK_UNHALTED.CORE)  Percentage of time that the core is stalled due to a TPAUSE or UMWAIT instruction      000tma_info_system_gflops Flops FP_FLOPS_RETIRED.ALL / (duration_time * 1e9)  Giga Floating Point Operations Per Second Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width     000tma_info_uop_mix_fpdiv_uop_ratio  100 * UOPS_RETIRED.FPDIV / TOPDOWN_RETIRING.ALL_P  Percentage of all uops which are FPDiv uops      000tma_info_uop_mix_idiv_uop_ratio  100 * UOPS_RETIRED.IDIV / TOPDOWN_RETIRING.ALL_P  Percentage of all uops which are IDiv uops      000tma_info_uop_mix_microcode_uop_ratio  100 * UOPS_RETIRED.MS / TOPDOWN_RETIRING.ALL_P  Percentage of all uops which are microcode ops      000tma_info_uop_mix_x87_uop_ratio  100 * UOPS_RETIRED.X87 / TOPDOWN_RETIRING.ALL_P  Percentage of all uops which are x87 uops      000tma_itlb_misses TopdownL3;tma_L3_group;tma_ifetch_latency_group TOPDOWN_FE_BOUND.ITLB_MISS / (6 * CPU_CLK_UNHALTED.CORE) tma_itlb_misses > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses  100%    000tma_machine_clears TopdownL2;tma_L2_group;tma_bad_speculation_group TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS / (6 * CPU_CLK_UNHALTED.CORE) tma_machine_clears > 0.05 & tma_bad_speculation > 0.15 Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation  100%  TopdownL2  000tma_mem_scheduler TopdownL3;tma_L3_group;tma_resource_bound_group TOPDOWN_BE_BOUND.MEM_SCHEDULER / (6 * CPU_CLK_UNHALTED.CORE) tma_mem_scheduler > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops  100%    000tma_non_mem_scheduler TopdownL3;tma_L3_group;tma_resource_bound_group TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER / (6 * CPU_CLK_UNHALTED.CORE) tma_non_mem_scheduler > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops  100%    000tma_nuke TopdownL3;tma_L3_group;tma_machine_clears_group TOPDOWN_BAD_SPECULATION.NUKE / (6 * CPU_CLK_UNHALTED.CORE) tma_nuke > 0.05 & (tma_machine_clears > 0.05 & tma_bad_speculation > 0.15) Counts the number of issue slots that were not consumed by the backend due to a machine clear that requires the use of microcode (slow nuke)  100%    000tma_other_fb TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group TOPDOWN_FE_BOUND.OTHER / (6 * CPU_CLK_UNHALTED.CORE) tma_other_fb > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to other common frontend stalls not categorized  100%    000tma_predecode TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group TOPDOWN_FE_BOUND.PREDECODE / (6 * CPU_CLK_UNHALTED.CORE) tma_predecode > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to wrong predecodes  100%    000tma_register TopdownL3;tma_L3_group;tma_resource_bound_group TOPDOWN_BE_BOUND.REGISTER / (6 * CPU_CLK_UNHALTED.CORE) tma_register > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls)  100%    000tma_reorder_buffer TopdownL3;tma_L3_group;tma_resource_bound_group TOPDOWN_BE_BOUND.REORDER_BUFFER / (6 * CPU_CLK_UNHALTED.CORE) tma_reorder_buffer > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to the reorder buffer being full (ROB stalls)  100%    000tma_retiring TopdownL1;tma_L1_group TOPDOWN_RETIRING.ALL_P / (6 * CPU_CLK_UNHALTED.CORE) tma_retiring > 0.75 Counts the number of issue slots that result in retirement slots  100%  TopdownL1  000tma_serialization TopdownL3;tma_L3_group;tma_resource_bound_group TOPDOWN_BE_BOUND.SERIALIZATION / (6 * CPU_CLK_UNHALTED.CORE) tma_serialization > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS)  100%    000cpu_cstate_c0 cpu_cstate UNC_P_POWER_STATE_OCCUPANCY_CORES_C0 / pcu_0@UNC_P_CLOCKTICKS@ * #num_packages  The average number of cores that are in cstate C0 as observed by the power control unit (PCU)      000cpu_cstate_c6 cpu_cstate UNC_P_POWER_STATE_OCCUPANCY_CORES_C6 / pcu_0@UNC_P_CLOCKTICKS@ * #num_packages  The average number of cores are in cstate C6 as observed by the power control unit (PCU)      000iio_bandwidth_read  UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.ALL_PARTS * 4 / 1e6 / duration_time  Bandwidth observed by the integrated I/O traffic controller (IIO) of IO reads that are initiated by end device controllers that are requesting memory from the CPU  1MB/s    000iio_bandwidth_write  UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.ALL_PARTS * 4 / 1e6 / duration_time  Bandwidth observed by the integrated I/O traffic controller (IIO) of IO writes that are initiated by end device controllers that are writing memory to the CPU  1MB/s    000tma_bottleneck_data_cache_memory_bandwidth BvMB;Mem;MemoryBW;Offcore;tma_issueBW 100 * (tma_memory_bound * (tma_dram_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * (tma_l1_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_fb_full / (tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))) tma_bottleneck_data_cache_memory_bandwidth > 20 Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full     000tma_bottleneck_data_cache_memory_latency BvML;Mem;MemoryLat;Offcore;tma_issueLat 100 * (tma_memory_bound * (tma_dram_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + 0 / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency) + tma_memory_bound * (tma_l3_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * tma_l2_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) + tma_memory_bound * (tma_l1_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l1_latency_dependency / (tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_l1_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_lock_latency / (tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_l1_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_split_loads / (tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_split_stores / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)) + tma_memory_bound * (tma_store_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) tma_bottleneck_data_cache_memory_latency > 20 Total pipeline cost of external Memory- or Cache-Latency related bottlenecks Total pipeline cost of external Memory- or Cache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_mem_latency     000tma_bottleneck_memory_data_tlbs BvMT;Mem;MemoryTLB;Offcore;tma_issueTLB 100 * (tma_memory_bound * (tma_l1_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_load / (tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) tma_bottleneck_memory_data_tlbs > 20 Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs) Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store     000tma_bottleneck_memory_synchronization BvMS;LockCont;Mem;Offcore;tma_issueSyncxn 100 * (tma_memory_bound * (tma_dram_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) * tma_remote_cache / (tma_local_mem + tma_remote_cache + tma_remote_mem) + tma_l3_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_contested_accesses + tma_data_sharing) / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full) + tma_store_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * tma_false_sharing / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores - tma_store_latency)) + tma_machine_clears * (1 - tma_other_nukes / tma_other_nukes)) tma_bottleneck_memory_synchronization > 10 Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors) Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors). Related metrics: tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache     000tma_code_l2_hit FetchLat;IcMiss;Offcore;TopdownL4;tma_L4_group;tma_icache_misses_group max(0, FRONTEND_RETIRED.L1I_MISS * FRONTEND_RETIRED.L1I_MISS:R / tma_info_thread_clks - tma_code_l2_miss) tma_code_l2_hit > 0.05 & (tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric estimates fraction of cycles the CPU was stalled due to instruction cache misses that hit in the L2 cache  100%    000tma_code_l2_miss FetchLat;IcMiss;Offcore;TopdownL4;tma_L4_group;tma_icache_misses_group FRONTEND_RETIRED.L2_MISS * FRONTEND_RETIRED.L2_MISS:R / tma_info_thread_clks tma_code_l2_miss > 0.05 & (tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric estimates fraction of cycles the CPU was stalled due to instruction cache misses that miss in the L2 cache  100%    000tma_code_stlb_hit FetchLat;MemoryTLB;TopdownL4;tma_L4_group;tma_itlb_misses_group max(0, FRONTEND_RETIRED.ITLB_MISS * FRONTEND_RETIRED.ITLB_MISS:R / tma_info_thread_clks - tma_code_stlb_miss) tma_code_stlb_hit > 0.05 & (tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric roughly estimates the fraction of cycles where the (first level) ITLB was missed by instructions fetches, that later on hit in second-level TLB (STLB)  100%    000tma_code_stlb_miss FetchLat;MemoryTLB;TopdownL4;tma_L4_group;tma_itlb_misses_group FRONTEND_RETIRED.STLB_MISS * FRONTEND_RETIRED.STLB_MISS:R / tma_info_thread_clks tma_code_stlb_miss > 0.05 & (tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by instruction fetches, performing a hardware page walk  100%    000tma_code_stlb_miss_2m FetchLat;MemoryTLB;TopdownL5;tma_L5_group;tma_code_stlb_miss_group ITLB_MISSES.WALK_ACTIVE / tma_info_thread_clks * ITLB_MISSES.WALK_COMPLETED_2M_4M / (ITLB_MISSES.WALK_COMPLETED_4K + ITLB_MISSES.WALK_COMPLETED_2M_4M) tma_code_stlb_miss_2m > 0.05 & (tma_code_stlb_miss > 0.05 & (tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))) This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 2 or 4 MB pages for (instruction) code accesses  100%    000tma_code_stlb_miss_4k FetchLat;MemoryTLB;TopdownL5;tma_L5_group;tma_code_stlb_miss_group ITLB_MISSES.WALK_ACTIVE / tma_info_thread_clks * ITLB_MISSES.WALK_COMPLETED_4K / (ITLB_MISSES.WALK_COMPLETED_4K + ITLB_MISSES.WALK_COMPLETED_2M_4M) tma_code_stlb_miss_4k > 0.05 & (tma_code_stlb_miss > 0.05 & (tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))) This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 4 KB pages for (instruction) code accesses  100%    000tma_cond_nt_mispredicts BrMispredicts;TopdownL3;tma_L3_group;tma_branch_mispredicts_group BR_MISP_RETIRED.COND_NTAKEN_COST * BR_MISP_RETIRED.COND_NTAKEN_COST:R / tma_info_thread_clks tma_cond_nt_mispredicts > 0.05 & (tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15) This metric represents fraction of cycles the CPU was stalled due to retired misprediction by non-taken conditional branches  100%    000tma_cond_tk_mispredicts BrMispredicts;TopdownL3;tma_L3_group;tma_branch_mispredicts_group BR_MISP_RETIRED.COND_TAKEN_COST * BR_MISP_RETIRED.COND_TAKEN_COST:R / tma_info_thread_clks tma_cond_tk_mispredicts > 0.05 & (tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15) This metric represents fraction of cycles the CPU was stalled due to misprediction by taken conditional branches  100%    000tma_contested_accesses BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS * min(MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS:R, 74.6 * tma_info_system_core_frequency) + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * min(MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD:R, 76.6 * tma_info_system_core_frequency) * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS. Related metrics: tma_bottleneck_memory_synchronization, tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100%    000tma_cxl_mem_bound MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (((1 - ((19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_CXL_MEM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) if #has_pmem > 0 else 0) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_CXL_MEM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) if #has_pmem > 0 else 0))) if #has_pmem > 0 else 1)) * (MEMORY_ACTIVITY.STALLS_L3_MISS / tma_info_thread_clks) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_CXL_MEM + MEM_LOAD_RETIRED.LOCAL_CXL_MEM) > MEM_LOAD_RETIRED.L1_MISS else 0) if #has_pmem > 0 else 0) tma_cxl_mem_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external CXL Memory by loads (e.g This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external CXL Memory by loads (e.g. 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory, PMM - Persistent Memory Module [from CLX to SPR] or any other CXL Type3 Memory [EMR onwards]) 100%    000tma_data_sharing BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD * min(MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD:R, 74.6 * tma_info_system_core_frequency) + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * min(MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD:R, 74.6 * tma_info_system_core_frequency) * (1 - OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD. Related metrics: tma_bottleneck_memory_synchronization, tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100%    010tma_dram_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (MEMORY_ACTIVITY.STALLS_L3_MISS / tma_info_thread_clks - tma_cxl_mem_bound if #has_pmem > 0 else MEMORY_ACTIVITY.STALLS_L3_MISS / tma_info_thread_clks) tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS 100%    000tma_dtlb_load BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group MEM_INST_RETIRED.STLB_HIT_LOADS * min(MEM_INST_RETIRED.STLB_HIT_LOADS:R, 7) / tma_info_thread_clks + tma_load_stlb_miss tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_bottleneck_memory_data_tlbs, tma_dtlb_store 100%    000tma_dtlb_store BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group MEM_INST_RETIRED.STLB_HIT_STORES * min(MEM_INST_RETIRED.STLB_HIT_STORES:R, 7) / tma_info_thread_clks + tma_store_stlb_miss tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses.  As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead.  Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page.  Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_bottleneck_memory_data_tlbs, tma_dtlb_load 100%    000tma_ind_call_mispredicts BrMispredicts;TopdownL3;tma_L3_group;tma_branch_mispredicts_group BR_MISP_RETIRED.INDIRECT_CALL_COST * BR_MISP_RETIRED.INDIRECT_CALL_COST:R / tma_info_thread_clks tma_ind_call_mispredicts > 0.05 & (tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15) This metric represents fraction of cycles the CPU was stalled due to retired misprediction by indirect CALL instructions  100%    000tma_ind_jump_mispredicts BrMispredicts;TopdownL3;tma_L3_group;tma_branch_mispredicts_group max((BR_MISP_RETIRED.INDIRECT_COST * BR_MISP_RETIRED.INDIRECT_COST:R - BR_MISP_RETIRED.INDIRECT_CALL_COST * BR_MISP_RETIRED.INDIRECT_CALL_COST:R) / tma_info_thread_clks, 0) tma_ind_jump_mispredicts > 0.05 & (tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15) This metric represents fraction of cycles the CPU was stalled due to retired misprediction by indirect JMP instructions  100%    000tma_info_core_flopc Flops;Ret (cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\,umask\=0x03@ + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * cpu@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE\,umask\=0x18@ + 8 * cpu@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE\,umask\=0x60@ + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / tma_info_core_core_clks  Floating Point Operations Per Cycle      000tma_info_frontend_dsb_switches_ret DSBmiss;Fed;FetchLat FRONTEND_RETIRED.ANY_DSB_MISS * FRONTEND_RETIRED.ANY_DSB_MISS:R / tma_info_thread_clks tma_info_frontend_dsb_switches_ret > 0.05 This metric represents fraction of cycles the CPU retirement was stalled likely due to retired DSB misses      000tma_info_frontend_icache_miss_latency Fed;FetchLat;IcMiss ICACHE_DATA.STALLS / ICACHE_DATA.STALL_PERIODS  Average Latency for L1 instruction cache misses      000tma_info_frontend_ms_latency_ret Fed;FetchLat;MicroSeq FRONTEND_RETIRED.MS_FLOWS * FRONTEND_RETIRED.MS_FLOWS:R / tma_info_thread_clks tma_info_frontend_ms_latency_ret > 0.05 This metric represents fraction of cycles the CPU retirement was stalled likely due to retired operations that invoke the Microcode Sequencer      000tma_info_frontend_unknown_branches_ret Fed;FetchLat FRONTEND_RETIRED.UNKNOWN_BRANCH * FRONTEND_RETIRED.UNKNOWN_BRANCH:R / tma_info_thread_clks  This metric represents fraction of cycles the CPU retirement was stalled likely due to retired branches who got branch address clears      000tma_info_inst_mix_ipflop Flops;InsType INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\,umask\=0x03@ + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * cpu@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE\,umask\=0x18@ + 8 * cpu@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE\,umask\=0x60@ + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) tma_info_inst_mix_ipflop < 10 Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)      000tma_info_memory_tlb_load_stlb_miss_ret Mem;MemoryTLB MEM_INST_RETIRED.STLB_MISS_LOADS * MEM_INST_RETIRED.STLB_MISS_LOADS:R / tma_info_thread_clks tma_info_memory_tlb_load_stlb_miss_ret > 0.05 This metric represents fraction of cycles the CPU retirement was stalled likely due to STLB misses by demand loads      000tma_info_memory_tlb_store_stlb_miss_ret Mem;MemoryTLB MEM_INST_RETIRED.STLB_MISS_STORES * MEM_INST_RETIRED.STLB_MISS_STORES:R / tma_info_thread_clks tma_info_memory_tlb_store_stlb_miss_ret > 0.05 This metric represents fraction of cycles the CPU retirement was stalled likely due to STLB misses by demand stores      000tma_info_system_cxl_mem_read_bw MemOffcore;MemoryBW;Server;SoC (64 * UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_DATA / 1e9 / tma_info_system_time if #has_pmem > 0 else 0)  Average 3DXP Memory Bandwidth Use for reads [GB / sec]      000tma_info_system_cxl_mem_write_bw MemOffcore;MemoryBW;Server;SoC (64 * UNC_CXLDP_TxC_AGF_INSERTS.M2S_DATA / 1e9 / tma_info_system_time if #has_pmem > 0 else 0)  Average 3DXP Memory Bandwidth Use for Writes [GB / sec]      000tma_info_system_dram_bw_use HPC;MemOffcore;MemoryBW;SoC;tma_issueBW 64 * (UNC_M_CAS_COUNT_SCH0.RD + UNC_M_CAS_COUNT_SCH1.RD + UNC_M_CAS_COUNT_SCH0.WR + UNC_M_CAS_COUNT_SCH1.WR) / 1e9 / tma_info_system_time  Average external Memory Bandwidth Use for reads and writes [GB / sec] Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_bottleneck_data_cache_memory_bandwidth, tma_fb_full, tma_mem_bandwidth, tma_sq_full     000tma_info_system_gflops Cor;Flops;HPC (cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\,umask\=0x03@ + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * cpu@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE\,umask\=0x18@ + 8 * cpu@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE\,umask\=0x60@ + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1e9 / tma_info_system_time  Giga Floating Point Operations Per Second Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width     000tma_l2_hit_latency MemoryLat;TopdownL4;tma_L4_group;tma_l2_bound_group MEM_LOAD_RETIRED.L2_HIT * min(MEM_LOAD_RETIRED.L2_HIT:R, 4.4 * tma_info_system_core_frequency) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_l2_hit_latency > 0.05 & (tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles with demand load accesses that hit the L2 cache under unloaded scenarios (possibly L2 latency limited) This metric represents fraction of cycles with demand load accesses that hit the L2 cache under unloaded scenarios (possibly L2 latency limited).  Avoiding L1 cache misses (i.e. L1 misses/L2 hits) will improve the latency. Sample with: MEM_LOAD_RETIRED.L2_HIT 100%    000tma_l3_hit_latency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group MEM_LOAD_RETIRED.L3_HIT * min(MEM_LOAD_RETIRED.L3_HIT:R, 32.6 * tma_info_system_core_frequency) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_bottleneck_data_cache_memory_latency, tma_mem_latency 100%    000tma_local_mem Server;TopdownL5;tma_L5_group;tma_mem_latency_group MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM:R * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_local_mem > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM 100%    000tma_lock_latency LockCont;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group MEM_INST_RETIRED.LOCK_LOADS * MEM_INST_RETIRED.LOCK_LOADS:R / tma_info_thread_clks tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS. Related metrics: tma_store_latency 100%    010tma_mem_bandwidth BvMB;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.DATA_RD\,cmask\=4@) / tma_info_thread_clks tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM).  The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_bottleneck_data_cache_memory_bandwidth, tma_fb_full, tma_info_system_dram_bw_use, tma_sq_full 100%    000tma_port_0 Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED.PORT_0 / tma_info_core_core_clks tma_port_0 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_port_1 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED.PORT_1 / tma_info_core_core_clks tma_port_1 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_port_6 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED.PORT_6 / tma_info_core_core_clks tma_port_6 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2 100%    000tma_ports_utilized_0 PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group max(EXE_ACTIVITY.EXE_BOUND_0_PORTS - RESOURCE_STALLS.SCOREBOARD, 0) / tma_info_thread_clks tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric 100%    040tma_remote_cache Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_issueSyncxn;tma_mem_latency_group (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * PEBS + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * PEBS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_remote_cache > 0.05 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD_PS. Related metrics: tma_bottleneck_memory_synchronization, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears 100%    000tma_remote_mem Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * PEBS * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_remote_mem > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM_PS 100%    000tma_ret_mispredicts BrMispredicts;TopdownL3;tma_L3_group;tma_branch_mispredicts_group BR_MISP_RETIRED.RET_COST * BR_MISP_RETIRED.RET_COST:R / tma_info_thread_clks tma_ret_mispredicts > 0.05 & (tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15) This metric represents fraction of cycles the CPU was stalled due to retired misprediction by (indirect) RET instructions  100%    000tma_split_loads TopdownL4;tma_L4_group;tma_l1_bound_group MEM_INST_RETIRED.SPLIT_LOADS * min(MEM_INST_RETIRED.SPLIT_LOADS:R, tma_info_memory_load_miss_real_latency) / tma_info_thread_clks tma_split_loads > 0.3 This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS 100%    000tma_split_stores TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group MEM_INST_RETIRED.SPLIT_STORES * min(MEM_INST_RETIRED.SPLIT_STORES:R, 1) / tma_info_thread_clks tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents rate of split store accesses This metric represents rate of split store accesses.  Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4 100%    000lpm_l2_totals_out lpm_l2;lpm_l2_totals d_ratio((L2_LINES_OUT.DEMAND_CLEAN / 2 if #smt_on else L2_LINES_OUT.DEMAND_CLEAN) + L2_LINES_OUT.DEMAND_DIRTY, duration_time)  L2 cache total out per second  1Out/s    000tma_divider BvCB;TopdownL3;tma_L3_group;tma_core_bound_group 10 * ARITH.DIVIDER_UOPS / tma_info_core_core_clks tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric represents fraction of cycles where the Divider unit was active This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE 100%    000tma_dram_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / tma_info_thread_clks tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS 100%    030tma_dtlb_load BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group (8 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION) / tma_info_thread_clks tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store 100%    000tma_dtlb_store BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group (8 * DTLB_STORE_MISSES.STLB_HIT + DTLB_STORE_MISSES.WALK_DURATION) / tma_info_thread_clks tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses.  As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead.  Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page.  Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_UOPS_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load 100%    000tma_false_sharing BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group 60 * OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100%    000tma_fb_full BvMB;MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group tma_info_memory_load_miss_real_latency * cpu@L1D_PEND_MISS.REQUEST_FB_FULL\,cmask\=1@ / tma_info_thread_clks tma_fb_full > 0.3 This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores 100%    010tma_fetch_latency Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group 4 * min(CPU_CLK_UNHALTED.THREAD, IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE) / tma_info_thread_slots tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15 This metric represents fraction of slots the CPU was stalled due to Frontend latency issues This metric represents fraction of slots the CPU was stalled due to Frontend latency issues.  For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END 100%  TopdownL2  000tma_info_core_ilp Backend;Cor;Pipeline;PortsUtil (UOPS_EXECUTED.CORE / 2 / (cpu@UOPS_EXECUTED.CORE\,cmask\=1@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\,cmask\=1@) if #SMT_on else UOPS_EXECUTED.CORE / (cpu@UOPS_EXECUTED.CORE\,cmask\=1@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\,cmask\=1@))  Instruction-Level-Parallelism (average number of uops executed when there is execution) per thread (logical-processor)      000tma_info_memory_tlb_page_walks_utilization Mem;MemoryTLB (ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION) / tma_info_core_core_clks tma_info_memory_tlb_page_walks_utilization > 0.5 Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses      000tma_itlb_misses BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group (14 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION) / tma_info_thread_clks tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED 100%    000tma_l1_bound CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group max((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) - CYCLE_ACTIVITY.STALLS_L1D_PENDING) / tma_info_thread_clks, 0) tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled without loads missing the L1 Data (L1D) cache This metric estimates how often the CPU was stalled without loads missing the L1 Data (L1D) cache.  The L1D cache typically has the shortest latency.  However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1D. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_UOPS_RETIRED.L1_HIT_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1 100%    000tma_l2_bound BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (CYCLE_ACTIVITY.STALLS_L1D_PENDING - CYCLE_ACTIVITY.STALLS_L2_PENDING) / tma_info_thread_clks tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to L2 cache accesses by loads This metric estimates how often the CPU was stalled due to L2 cache accesses by loads.  Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L2_HIT_PS 100%    000tma_l3_bound CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / tma_info_thread_clks tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core.  Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS 100%    030tma_mem_bandwidth BvMB;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=6@) / tma_info_thread_clks tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM).  The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_sq_full 100%    000tma_memory_bound Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\,cmask\=1@ - (cpu@UOPS_EXECUTED.CORE\,cmask\=3@ if tma_info_thread_ipc > 1.8 else cpu@UOPS_EXECUTED.CORE\,cmask\=2@)) / 2 - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB if #SMT_on else min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\,cmask\=1@ - (cpu@UOPS_EXECUTED.CORE\,cmask\=3@ if tma_info_thread_ipc > 1.8 else cpu@UOPS_EXECUTED.CORE\,cmask\=2@) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) * tma_backend_bound tma_memory_bound > 0.2 & tma_backend_bound > 0.2 This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two) 100%  TopdownL2  010tma_ports_utilization PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group ((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\,cmask\=1@ - (cpu@UOPS_EXECUTED.CORE\,cmask\=3@ if tma_info_thread_ipc > 1.8 else cpu@UOPS_EXECUTED.CORE\,cmask\=2@)) / 2 - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB if #SMT_on else min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\,cmask\=1@ - (cpu@UOPS_EXECUTED.CORE\,cmask\=3@ if tma_info_thread_ipc > 1.8 else cpu@UOPS_EXECUTED.CORE\,cmask\=2@) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING)) / tma_info_thread_clks tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations 100%    010tma_ports_utilized_0 PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group (cpu@UOPS_EXECUTED.CORE\,inv\,cmask\=1@ / 2 if #SMT_on else min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0)) / tma_info_core_core_clks tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric 100%    000tma_ports_utilized_1 PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group ((cpu@UOPS_EXECUTED.CORE\,cmask\=1@ - cpu@UOPS_EXECUTED.CORE\,cmask\=2@) / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\,cmask\=1@ - cpu@UOPS_EXECUTED.CORE\,cmask\=2@) / tma_info_core_core_clks tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Related metrics: tma_l1_bound 100%    000tma_ports_utilized_2 PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group ((cpu@UOPS_EXECUTED.CORE\,cmask\=2@ - cpu@UOPS_EXECUTED.CORE\,cmask\=3@) / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\,cmask\=2@ - cpu@UOPS_EXECUTED.CORE\,cmask\=3@) / tma_info_core_core_clks tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).  Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6 100%    000tma_ports_utilized_3m BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group (cpu@UOPS_EXECUTED.CORE\,cmask\=3@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\,cmask\=3@) / tma_info_core_core_clks tma_ports_utilized_3m > 0.4 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)  100%    000io_bandwidth_write  cbox@UNC_C_TOR_INSERTS.OPCODE\,filter_opc\=0x1c8\,filter_tid\=0x3e@ * 64 / 1e6 / duration_time  Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU  1MB/s    000percent_uops_delivered_from_loop_stream_detector  (UOPS_ISSUED.ANY - IDQ.MITE_UOPS - IDQ.MS_UOPS - IDQ.DSB_UOPS) / UOPS_ISSUED.ANY  Uops delivered from loop stream detector(LSD) as a percent of total uops delivered to Instruction Decode Queue  100%    000lpm_port_2_3 lpm_ports d_ratio(UOPS_DISPATCHED.PORT_2_3, (CPU_CLK_UNHALTED.DISTRIBUTED / 2 if #smt_on else CPU_CLK_UNHALTED.DISTRIBUTED))  port_2_3 utilization (higher is better)  100%    000lpm_port_5 lpm_ports d_ratio(UOPS_DISPATCHED.PORT_5, (CPU_CLK_UNHALTED.DISTRIBUTED / 2 if #smt_on else CPU_CLK_UNHALTED.DISTRIBUTED))  port_5 utilization (higher is better)  100%    000C9_Pkg_Residency Power cstate_pkg@c9\-residency@ / msr@tsc@  C9 residency percent per package  100%    000tma_alu_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5 + UOPS_DISPATCHED.PORT_6) / (4 * tma_info_core_core_clks) tma_alu_op_utilization > 0.4 This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations  100%    000tma_assists BvIO;TopdownL4;tma_L4_group;tma_microcode_sequencer_group 34 * ASSISTS.ANY / tma_info_thread_slots tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1) This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY 100%    000tma_backend_bound BvOB;Default;TmaL1;TopdownL1;tma_L1_group topdown\-be\-bound / (topdown\-fe\-bound + topdown\-bad\-spec + topdown\-retiring + topdown\-be\-bound) + 5 * INT_MISC.CLEARS_COUNT / tma_info_thread_slots tma_backend_bound > 0.2 This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS 100%  TopdownL1;Default TopdownL1 000tma_bottleneck_data_cache_memory_bandwidth BvMB;Mem;MemoryBW;Offcore;tma_issueBW 100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))) tma_bottleneck_data_cache_memory_bandwidth > 20 Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full     010tma_bottleneck_data_cache_memory_latency BvML;Mem;MemoryLat;Offcore;tma_issueLat 100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l1_latency_dependency / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_lock_latency / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_split_loads / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_split_stores / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) tma_bottleneck_data_cache_memory_latency > 20 Total pipeline cost of external Memory- or Cache-Latency related bottlenecks Total pipeline cost of external Memory- or Cache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_mem_latency     010tma_bottleneck_instruction_fetch_bw BvFB;Fed;FetchBW;Frontend 100 * (tma_frontend_bound - (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) - tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * (tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clears_resteers + 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts * tma_mispredicts_resteers) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_ms)) - tma_bottleneck_big_code tma_bottleneck_instruction_fetch_bw > 20 Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)      010tma_bottleneck_irregular_overhead Bad;BvIO;Cor;Ret;tma_issueMS 100 * (tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * (tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clears_resteers + 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts * tma_mispredicts_resteers) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_ms) + 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts * tma_branch_mispredicts + tma_machine_clears * tma_other_nukes / tma_other_nukes + tma_core_bound * (tma_serializing_operation + tma_core_bound * RS_EVENTS.EMPTY_CYCLES / tma_info_thread_clks * tma_ports_utilized_0) / (tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations) tma_bottleneck_irregular_overhead > 10 Total pipeline cost of irregular execution (e.g Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloads, overhead in system services or virtualized environments). Related metrics: tma_microcode_sequencer, tma_ms_switches     010tma_bottleneck_memory_data_tlbs BvMT;Mem;MemoryTLB;Offcore;tma_issueTLB 100 * (tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) tma_bottleneck_memory_data_tlbs > 20 Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs) Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store     010tma_bottleneck_memory_synchronization BvMS;LockCont;Mem;Offcore;tma_issueSyncxn 100 * (tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_contested_accesses + tma_data_sharing) / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * tma_false_sharing / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores - tma_store_latency)) + tma_machine_clears * (1 - tma_other_nukes / tma_other_nukes)) tma_bottleneck_memory_synchronization > 10 Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors) Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors). Related metrics: tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache     010tma_branch_instructions Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * BR_INST_RETIRED.ALL_BRANCHES / (tma_retiring * tma_info_thread_slots) tma_branch_instructions > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring branch instructions  100%    000tma_branch_mispredicts BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15 This metric represents fraction of slots the CPU has wasted due to Branch Misprediction This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_bottleneck_mispredictions, tma_info_bad_spec_branch_misprediction_cost, tma_mispredicts_resteers 100%  TopdownL2  000tma_contested_accesses BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (29 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM + 23.5 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_bottleneck_memory_synchronization, tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100%    010tma_data_sharing BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 23.5 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_bottleneck_memory_synchronization, tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100%    010tma_dram_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_thread_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks - tma_l2_bound tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS 100%    010tma_dtlb_load BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group min(7 * cpu@DTLB_LOAD_MISSES.STLB_HIT\,cmask\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_bottleneck_memory_data_tlbs, tma_dtlb_store 100%    000tma_false_sharing BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group 32.5 * tma_info_system_core_frequency * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_bottleneck_memory_synchronization, tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100%    000tma_fetch_latency Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group (5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / tma_info_thread_slots tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15 This metric represents fraction of slots the CPU was stalled due to Frontend latency issues This metric represents fraction of slots the CPU was stalled due to Frontend latency issues.  For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS 100%  TopdownL2  000tma_few_uops_instructions TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueD0 tma_heavy_operations - tma_microcode_sequencer tma_few_uops_instructions > 0.05 & tma_heavy_operations > 0.1 This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or more uops This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or more uops. This highly-correlates with the number of uops in such instructions. Related metrics: tma_decoder0_alone 100%    000tma_fp_assists HPC;TopdownL5;tma_L5_group;tma_assists_group 34 * ASSISTS.FP / tma_info_thread_slots tma_fp_assists > 0.1 This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called Denormals) 100%    000tma_fp_divider TopdownL4;tma_L4_group;tma_divider_group ARITH.FP_DIVIDER_ACTIVE / tma_info_thread_clks tma_fp_divider > 0.2 & (tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles where the Floating-Point Divider unit was active  100%    000tma_fp_scalar Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P FP_ARITH_INST_RETIRED.SCALAR / (tma_retiring * tma_info_thread_slots) tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_fp_vector Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P FP_ARITH_INST_RETIRED.VECTOR / (tma_retiring * tma_info_thread_slots) tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_fp_vector_128b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / (tma_retiring * tma_info_thread_slots) tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting prior to LNL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_fp_vector_256b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / (tma_retiring * tma_info_thread_slots) tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting prior to LNL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_fp_vector_512b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / (tma_retiring * tma_info_thread_slots) tma_fp_vector_512b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_heavy_operations Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group tma_microcode_sequencer + tma_retiring * (UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\,cmask\=1@) / IDQ.MITE_UOPS tma_heavy_operations > 0.1 This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.([ICL+] Note this may overcount due to approximation using indirect events; [ADL+]) 100%  TopdownL2  000tma_info_bad_spec_branch_misprediction_cost Bad;BrMispredicts;tma_issueBM tma_bottleneck_mispredictions * tma_info_thread_slots / 5 / BR_MISP_RETIRED.ALL_BRANCHES / 100  Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear) Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_bottleneck_mispredictions, tma_branch_mispredicts, tma_mispredicts_resteers     010tma_info_botlnk_l2_dsb_bandwidth DSB;Fed;FetchBW;tma_issueFB 100 * (tma_frontend_bound * (tma_fetch_bandwidth / (tma_fetch_bandwidth + tma_fetch_latency)) * (tma_dsb / (tma_dsb + tma_lsd + tma_mite + tma_ms))) tma_info_botlnk_l2_dsb_bandwidth > 10 Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp     010tma_info_botlnk_l2_dsb_misses DSBmiss;Fed;tma_issueFB 100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_lsd + tma_mite + tma_ms)) tma_info_botlnk_l2_dsb_misses > 10 Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp     010tma_info_core_flopc Flops;Ret (FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / tma_info_core_core_clks  Floating Point Operations Per Cycle      000tma_info_frontend_dsb_coverage DSB;Fed;FetchBW;tma_issueFB IDQ.DSB_UOPS / UOPS_ISSUED.ANY tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 5 > 0.35 Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache) Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp     000tma_info_frontend_icache_miss_latency Fed;FetchLat;IcMiss ICACHE_16B.IFDATA_STALL / cpu@ICACHE_16B.IFDATA_STALL\,cmask\=1\,edge@  Average Latency for L1 instruction cache misses      000tma_info_frontend_lsd_coverage Fed;LSD LSD.UOPS / UOPS_ISSUED.ANY  Fraction of Uops delivered by the LSD (Loop Stream Detector; aka Loop Cache)      000tma_info_inst_mix_ipflop Flops;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) tma_info_inst_mix_ipflop < 10 Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)      000tma_info_inst_mix_ippause Flops;FpVector;InsType tma_info_inst_mix_instructions / MISC_RETIRED.PAUSE_INST  Instructions per PAUSE (lower number means higher occurrence rate)      000tma_info_inst_mix_iptb Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN tma_info_inst_mix_iptb < 11 Instructions per taken branch Instructions per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_lcp     000tma_info_memory_l2mpki_all CacheHits;Mem;Offcore 1e3 * (OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_REQUESTS.DEMAND_DATA_RD + L2_RQSTS.ALL_DEMAND_MISS + L2_RQSTS.SWPF_MISS) / tma_info_inst_mix_instructions  L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)      000tma_info_memory_tlb_page_walks_utilization Mem;MemoryTLB (ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING) / (2 * tma_info_core_core_clks) tma_info_memory_tlb_page_walks_utilization > 0.5 Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses      000tma_info_pipeline_fetch_lsd Fed;FetchBW LSD.UOPS / LSD.CYCLES_ACTIVE  Average number of uops fetched from LSD per cycle      000tma_info_system_gflops Cor;Flops;HPC (FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1e9 / tma_info_system_time  Giga Floating Point Operations Per Second Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width     000tma_info_system_power_license0_utilization Power CORE_POWER.LVL0_TURBO_LICENSE / tma_info_core_core_clks  Fraction of Core cycles where the core was running with power-delivery for baseline license level 0 Fraction of Core cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes     000tma_info_system_power_license1_utilization Power CORE_POWER.LVL1_TURBO_LICENSE / tma_info_core_core_clks tma_info_system_power_license1_utilization > 0.5 Fraction of Core cycles where the core was running with power-delivery for license level 1 Fraction of Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions     000tma_info_system_power_license2_utilization Power CORE_POWER.LVL2_TURBO_LICENSE / tma_info_core_core_clks tma_info_system_power_license2_utilization > 0.5 Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX) Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX).  This includes high current AVX 512-bit instructions     000tma_info_thread_uptb Branches;Fed;FetchBW tma_retiring * tma_info_thread_slots / BR_INST_RETIRED.NEAR_TAKEN tma_info_thread_uptb < 7.5 Uops per taken branch      000tma_l1_latency_dependency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_l1_bound_group min(2 * (MEM_INST_RETIRED.ALL_LOADS - MEM_LOAD_RETIRED.FB_HIT - MEM_LOAD_RETIRED.L1_MISS) * 20 / 100, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks tma_l1_latency_dependency > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric ([SKL+] roughly; [LNL]) estimates fraction of cycles with demand load accesses that hit the L1D cache This metric ([SKL+] roughly; [LNL]) estimates fraction of cycles with demand load accesses that hit the L1D cache. The short latency of the L1D cache may be exposed in pointer-chasing memory access patterns as an example. Sample with: MEM_LOAD_RETIRED.L1_HIT 100%    000tma_l2_bound BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + L1D_PEND_MISS.FB_FULL_PERIODS) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks) tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to L2 cache accesses by loads This metric estimates how often the CPU was stalled due to L2 cache accesses by loads.  Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT 100%    010tma_l3_hit_latency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 9 * tma_info_system_core_frequency * (MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2)) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_bottleneck_data_cache_memory_latency, tma_mem_latency 100%    000tma_load_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group UOPS_DISPATCHED.PORT_2_3 / (2 * tma_info_core_core_clks) tma_load_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3 100%    000tma_lsd FetchBW;LSD;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group (LSD.CYCLES_ACTIVE - LSD.CYCLES_OK) / tma_info_core_core_clks / 2 tma_lsd > 0.15 & tma_fetch_bandwidth > 0.2 This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit.  LSD typically does well sustaining Uop supply. However; in some rare cases; optimal uop-delivery could not be reached for small loops whose size (in terms of number of uops) does not suit well the LSD structure 100%    000tma_memory_bound Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group (CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * tma_backend_bound tma_memory_bound > 0.2 & tma_backend_bound > 0.2 This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two) 100%  TopdownL2  000tma_memory_operations Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY tma_memory_operations > 0.1 & tma_light_operations > 0.6 This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses  100%    010tma_microcode_sequencer MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / tma_info_thread_slots tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1 This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS. Related metrics: tma_bottleneck_irregular_overhead, tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_ms_switches 100%    000tma_mispredicts_resteers BadSpec;BrMispredicts;BvMP;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_thread_clks tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_bottleneck_mispredictions, tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost 100%    000tma_mite_4wide DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_mite_group (cpu@IDQ.MITE_UOPS\,cmask\=4@ - cpu@IDQ.MITE_UOPS\,cmask\=5@) / tma_info_thread_clks tma_mite_4wide > 0.05 & (tma_mite > 0.1 & tma_fetch_bandwidth > 0.2) This metric represents fraction of cycles where (only) 4 uops were delivered by the MITE pipeline  100%    000tma_ms MicroSeq;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group cpu@IDQ.MS_UOPS\,cmask\=1@ / tma_info_core_core_clks / 3.3 tma_ms > 0.05 & tma_fetch_bandwidth > 0.2 This metric represents Core fraction of cycles in which CPU was likely limited due to the Microcode Sequencer (MS) unit - see Microcode_Sequencer node for details  100%    000tma_ms_switches FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO 3 * IDQ.MS_SWITCHES / tma_info_thread_clks tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_bottleneck_irregular_overhead, tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation 100%    000tma_other_light_ops Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_branch_instructions)) tma_other_light_ops > 0.3 & tma_light_operations > 0.6 This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting 100%    010tma_port_0 Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED.PORT_0 / tma_info_core_core_clks tma_port_0 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_port_1 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED.PORT_1 / tma_info_core_core_clks tma_port_1 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_port_5 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED.PORT_5 / tma_info_core_core_clks tma_port_5 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU). Sample with: UOPS_DISPATCHED.PORT_5. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_6, tma_ports_utilized_2 100%    000tma_port_6 TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P UOPS_DISPATCHED.PORT_6 / tma_info_core_core_clks tma_port_6 > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU) This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2 100%    000tma_ports_utilization PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group ((tma_ports_utilized_0 * tma_info_thread_clks + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / tma_info_thread_clks if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / tma_info_thread_clks) tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations 100%    000tma_ports_utilized_0 PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group cpu@EXE_ACTIVITY.3_PORTS_UTIL\,umask\=0x80@ / tma_info_thread_clks tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric 100%    000tma_ports_utilized_1 PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group EXE_ACTIVITY.1_PORTS_UTIL / tma_info_thread_clks tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL. Related metrics: tma_l1_bound 100%    000tma_ports_utilized_2 PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group EXE_ACTIVITY.2_PORTS_UTIL / tma_info_thread_clks tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).  Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6 100%    000tma_serializing_operation BvIO;PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group;tma_issueSO RESOURCE_STALLS.SCOREBOARD / tma_info_thread_clks tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: RESOURCE_STALLS.SCOREBOARD. Related metrics: tma_ms_switches 100%    000tma_slow_pause TopdownL4;tma_L4_group;tma_serializing_operation_group 140 * MISC_RETIRED.PAUSE_INST / tma_info_thread_clks tma_slow_pause > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: MISC_RETIRED.PAUSE_INST 100%    000tma_sq_full BvMB;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group L1D_PEND_MISS.L2_STALL / tma_info_thread_clks tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors) This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_bottleneck_data_cache_memory_bandwidth, tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth 100%    000tma_store_latency BvML;LockCont;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group (L2_RQSTS.RFO_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles the CPU spent handling L1D store misses This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency 100%    000tma_unknown_branches BigFootprint;BvBC;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group 10 * BACLEARS.ANY / tma_info_thread_clks tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)) This metric represents fraction of cycles the CPU was stalled due to new branch address clears This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches. Sample with: BACLEARS.ANY 100%    000lpm_mem_sat  d_ratio(UNC_CHA_DISTRESS_ASSERTED.VERT, UNC_CHA_CLOCKTICKS)  Mesh Bandwidth saturation (% CHA cycles with FAST signal asserted, include UPI bandwidth saturation), lower is better (metric should be considered experimental as it contains experimental events)  100%    000io_bandwidth_read  (UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR + UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR) * 64 / 1e6 / duration_time  Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU  1MB/s    000io_bandwidth_write  (UNC_CHA_TOR_INSERTS.IO_HIT_ITOM + UNC_CHA_TOR_INSERTS.IO_MISS_ITOM + UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR) * 64 / 1e6 / duration_time  Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU  1MB/s    000llc_demand_data_read_miss_to_pmem_latency  1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM) * #num_packages)) * duration_time  Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to Intel(R) Optane(TM) Persistent Memory(PMEM) in nano seconds  1ns    000tma_bottleneck_data_cache_memory_latency BvML;Mem;MemoryLat;Offcore;tma_issueLat 100 * (tma_memory_bound * (tma_dram_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * tma_l2_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) + tma_memory_bound * (tma_l1_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l1_latency_dependency / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_l1_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_lock_latency / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_l1_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_split_loads / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_split_stores / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)) + tma_memory_bound * (tma_store_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) tma_bottleneck_data_cache_memory_latency > 20 Total pipeline cost of external Memory- or Cache-Latency related bottlenecks Total pipeline cost of external Memory- or Cache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_mem_latency     010tma_bottleneck_memory_data_tlbs BvMT;Mem;MemoryTLB;Offcore;tma_issueTLB 100 * (tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) tma_bottleneck_memory_data_tlbs > 20 Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs) Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store     010tma_bottleneck_memory_synchronization BvMS;LockCont;Mem;Offcore;tma_issueSyncxn 100 * (tma_memory_bound * (tma_dram_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) * tma_remote_cache / (tma_local_mem + tma_remote_cache + tma_remote_mem) + tma_l3_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_contested_accesses + tma_data_sharing) / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full) + tma_store_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * tma_false_sharing / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores - tma_store_latency)) + tma_machine_clears * (1 - tma_other_nukes / tma_other_nukes)) tma_bottleneck_memory_synchronization > 10 Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors) Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors). Related metrics: tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache     010tma_contested_accesses BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (44 * tma_info_system_core_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + 43.5 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_bottleneck_memory_synchronization, tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100%    010tma_data_sharing BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 43.5 * tma_info_system_core_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_bottleneck_memory_synchronization, tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100%    010tma_false_sharing BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group (120 * tma_info_system_core_frequency * OCR.DEMAND_RFO.L3_MISS@offcore_rsp\=0x103b800002@ + 48 * tma_info_system_core_frequency * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM) / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_bottleneck_memory_synchronization, tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100%    000tma_info_botlnk_l2_dsb_bandwidth DSB;Fed;FetchBW;tma_issueFB 100 * (tma_frontend_bound * (tma_fetch_bandwidth / (tma_fetch_bandwidth + tma_fetch_latency)) * (tma_dsb / (tma_dsb + tma_mite + tma_ms))) tma_info_botlnk_l2_dsb_bandwidth > 10 Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp     010tma_info_botlnk_l2_dsb_misses DSBmiss;Fed;tma_issueFB 100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite + tma_ms)) tma_info_botlnk_l2_dsb_misses > 10 Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp     010tma_info_system_io_write_bw IoBW;MemOffcore;Server;SoC (UNC_CHA_TOR_INSERTS.IO_HIT_ITOM + UNC_CHA_TOR_INSERTS.IO_MISS_ITOM + UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR) * 64 / 1e9 / tma_info_system_time  Average IO (network or disk) Bandwidth Use for Writes [GB / sec] Average IO (network or disk) Bandwidth Use for Writes [GB / sec]. Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU     000tma_info_system_mem_dram_read_latency MemOffcore;MemoryLat;Server;SoC 1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / cha_0@event\=0x0@  Average latency of data read request to external DRAM memory [in nanoseconds] Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches     000tma_info_system_mem_parallel_reads Mem;MemoryBW;SoC UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD@thresh\=1@  Average number of parallel data read requests to external memory Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches     010tma_info_system_mem_pmm_read_latency MemOffcore;MemoryLat;Server;SoC (1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / cha_0@event\=0x0@ if #has_pmem > 0 else 0)  Average latency of data read request to external 3D X-Point memory [in nanoseconds] Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches     000tma_l2_hit_latency MemoryLat;TopdownL4;tma_L4_group;tma_l2_bound_group 4 * tma_info_system_core_frequency * MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_l2_hit_latency > 0.05 & (tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles with demand load accesses that hit the L2 cache under unloaded scenarios (possibly L2 latency limited) This metric represents fraction of cycles with demand load accesses that hit the L2 cache under unloaded scenarios (possibly L2 latency limited).  Avoiding L1 cache misses (i.e. L1 misses/L2 hits) will improve the latency. Sample with: MEM_LOAD_RETIRED.L2_HIT 100%    000tma_l3_hit_latency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 19 * tma_info_system_core_frequency * (MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2)) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_bottleneck_data_cache_memory_latency, tma_mem_latency 100%    000tma_local_mem Server;TopdownL5;tma_L5_group;tma_mem_latency_group 43.5 * tma_info_system_core_frequency * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_local_mem > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM 100%    000tma_remote_cache Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_issueSyncxn;tma_mem_latency_group (97 * tma_info_system_core_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + 97 * tma_info_system_core_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_remote_cache > 0.05 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD_PS. Related metrics: tma_bottleneck_memory_synchronization, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears 100%    000tma_remote_mem Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group 108 * tma_info_system_core_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_remote_mem > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM_PS 100%    000tma_slow_pause TopdownL4;tma_L4_group;tma_serializing_operation_group 37 * MISC_RETIRED.PAUSE_INST / tma_info_thread_clks tma_slow_pause > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: MISC_RETIRED.PAUSE_INST 100%    000lpm_l2_rd_hits lpm_l2;lpm_l2_rd d_ratio(L2_RQSTS.ALL_DEMAND_DATA_RD - L2_RQSTS.DEMAND_DATA_RD_HIT, L2_RQSTS.ALL_DEMAND_DATA_RD)  L2 cache data read hits  100%    000lpm_l2_rd_hits lpm_l2;lpm_l2_rd d_ratio(L2_RQSTS.DEMAND_DATA_RD_HIT, L2_RQSTS.ALL_DEMAND_DATA_RD)  L2 cache data read hits  100%    000lpm_l2_rd_misses lpm_l2;lpm_l2_rd d_ratio(L2_RQSTS.ALL_DEMAND_DATA_RD - L2_RQSTS.DEMAND_DATA_RD_HIT, duration_time)  L2 cache data read misses per second  1misses/s    000lpm_l2_rd_requests lpm_l2;lpm_l2_rd d_ratio(L2_RQSTS.ALL_DEMAND_DATA_RD, duration_time)  L2 cache data read requests per second  1requests/s    000lpm_port_0_core lpm_ports d_ratio(UOPS_DISPATCHED_PORT.PORT_0_CORE, CPU_CLK_UNHALTED.THREAD_P_ANY)  port_0_core utilization (higher is better)  100%    000lpm_port_1_core lpm_ports d_ratio(UOPS_DISPATCHED_PORT.PORT_1_CORE, CPU_CLK_UNHALTED.THREAD_P_ANY)  port_1_core utilization (higher is better)  100%    000lpm_port_2_core lpm_ports d_ratio(UOPS_DISPATCHED_PORT.PORT_2_CORE, CPU_CLK_UNHALTED.THREAD_P_ANY)  port_2_core utilization (higher is better)  100%    000lpm_port_3_core lpm_ports d_ratio(UOPS_DISPATCHED_PORT.PORT_3_CORE, CPU_CLK_UNHALTED.THREAD_P_ANY)  port_3_core utilization (higher is better)  100%    000lpm_port_4_core lpm_ports d_ratio(UOPS_DISPATCHED_PORT.PORT_4_CORE, CPU_CLK_UNHALTED.THREAD_P_ANY)  port_4_core utilization (higher is better)  100%    000lpm_port_5_core lpm_ports d_ratio(UOPS_DISPATCHED_PORT.PORT_5_CORE, CPU_CLK_UNHALTED.THREAD_P_ANY)  port_5_core utilization (higher is better)  100%    000tma_alu_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5) / (3 * tma_info_core_core_clks) tma_alu_op_utilization > 0.4 This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations  100%    000tma_contested_accesses BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (60 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.LLC_MISS))) + 43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.LLC_MISS)))) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100%    010tma_data_sharing BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.LLC_MISS))) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100%    010tma_dram_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (1 - MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / tma_info_thread_clks tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS 100%    030tma_dtlb_load BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group (7 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION) / tma_info_thread_clks tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store 100%    000tma_dtlb_store BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group (7 * DTLB_STORE_MISSES.STLB_HIT + DTLB_STORE_MISSES.WALK_DURATION) / tma_info_thread_clks tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses.  As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead.  Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page.  Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_UOPS_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load 100%    000tma_false_sharing BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group 60 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100%    000tma_fp_scalar Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P (FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) / UOPS_EXECUTED.THREAD tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_fp_vector Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P (FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) / UOPS_EXECUTED.THREAD tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_fp_vector_128b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE) / UOPS_EXECUTED.THREAD tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting prior to LNL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_fp_vector_256b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (SIMD_FP_256.PACKED_DOUBLE + SIMD_FP_256.PACKED_SINGLE) / UOPS_EXECUTED.THREAD tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting prior to LNL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2 100%    000tma_icache_misses BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group ICACHE.IFETCH_STALL / tma_info_thread_clks - tma_itlb_misses tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to instruction cache misses  100%    000tma_info_core_flopc Flops;Ret (FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / tma_info_core_core_clks  Floating Point Operations Per Cycle      000tma_info_inst_mix_iparith Flops;InsType 1 / (tma_fp_scalar + tma_fp_vector) tma_info_inst_mix_iparith < 10 Instructions per FP Arithmetic instruction (lower number means higher occurrence rate) Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW     000tma_info_memory_l3mpki Mem 1e3 * MEM_LOAD_UOPS_RETIRED.LLC_MISS / INST_RETIRED.ANY  L3 cache true misses per kilo instruction for retired demand loads      000tma_info_system_gflops Cor;Flops;HPC (FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / 1e9 / tma_info_system_time  Giga Floating Point Operations Per Second Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width     000tma_info_system_power Power;SoC power@energy\-pkg@ * 15.6 / (tma_info_system_time * 1e6)  Total package Power in Watts      000tma_itlb_misses BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group (12 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION) / tma_info_thread_clks tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED 100%    000tma_l3_bound CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / tma_info_thread_clks tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core.  Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS 100%    030tma_l3_hit_latency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 29 * (MEM_LOAD_UOPS_RETIRED.LLC_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.LLC_MISS))) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS. Related metrics: tma_mem_latency 100%    010tma_load_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * tma_info_core_core_clks) tma_load_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3 100%    000tma_memory_bound Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if tma_info_thread_ipc > 1.8 else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) * tma_backend_bound tma_memory_bound > 0.2 & tma_backend_bound > 0.2 This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two) 100%  TopdownL2  010tma_ms_switches FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO 3 * IDQ.MS_SWITCHES / tma_info_thread_clks tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation 100%    000tma_ports_utilization PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if tma_info_thread_ipc > 1.8 else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING)) / tma_info_thread_clks tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations 100%    010tma_split_loads TopdownL4;tma_L4_group;tma_l1_bound_group 13 * LD_BLOCKS.NO_SR / tma_info_thread_clks tma_split_loads > 0.3 This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_UOPS_RETIRED.SPLIT_LOADS_PS 100%    010tma_x87_use Compute;TopdownL4;tma_L4_group;tma_fp_arith_group UOPS_RETIRED.RETIRE_SLOTS * FP_COMP_OPS_EXE.X87 / UOPS_EXECUTED.THREAD tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric serves as an approximation of legacy x87 usage This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint 100%    000tma_contested_accesses BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (60 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) + 43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD)))) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100%    010tma_data_sharing BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100%    010tma_info_system_power Power;SoC (power@energy\-pkg@ + power@energy\-ram@) * 15.6 / (duration_time * 1e6)  Total package Power in Watts      000tma_l3_hit_latency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 41 * (MEM_LOAD_UOPS_RETIRED.LLC_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS. Related metrics: tma_mem_latency 100%    010tma_local_mem Server;TopdownL5;tma_L5_group;tma_mem_latency_group 200 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / tma_info_thread_clks tma_local_mem > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM_PS 100%    010tma_remote_cache Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_issueSyncxn;tma_mem_latency_group (200 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) + 180 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD)))) / tma_info_thread_clks tma_remote_cache > 0.05 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD_PS. Related metrics: tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears 100%    010tma_remote_mem Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group 310 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / tma_info_thread_clks tma_remote_mem > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))) This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM_PS 100%    010lpm_miss_lat_loc lpm_miss_lat duration_time * 1e9 * UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\=0x182@ / (UNC_C_CLOCKTICKS / source_count(UNC_C_TOR_INSERTS.MISS_OPCODE@filter_opc\=0x182@) * UNC_C_TOR_INSERTS.MISS_OPCODE@filter_opc\=0x182@)  Local to a socket miss latency in nanoseconds  1ns    000lpm_miss_lat_rem lpm_miss_lat duration_time * 1e9 * UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE@filter_opc\=0x182@ / (UNC_C_CLOCKTICKS / source_count(UNC_C_TOR_INSERTS.NID_MISS_OPCODE@filter_opc\=0x182@) * UNC_C_TOR_INSERTS.NID_MISS_OPCODE@filter_opc\=0x182@)  Remote to a socket miss latency in nanoseconds  1ns    000tma_dsb_switches DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_thread_clks tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Related metrics: tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_lcp 100%    000tma_dtlb_load BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group (7 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION) / tma_info_thread_clks tma_dtlb_load > 0.1 This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store 100%    000tma_fetch_bandwidth FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB tma_frontend_bound - tma_fetch_latency tma_fetch_bandwidth > 0.2 This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues.  For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Related metrics: tma_dsb_switches, tma_info_frontend_dsb_coverage, tma_lcp 100%  TopdownL2  000tma_fp_scalar Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P (FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) / UOPS_DISPATCHED.THREAD tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_6, tma_ports_utilized_2 100%    000tma_fp_vector Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P (FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) / UOPS_DISPATCHED.THREAD tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_6, tma_ports_utilized_2 100%    000tma_fp_vector_128b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE) / UOPS_DISPATCHED.THREAD tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting prior to LNL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_6, tma_ports_utilized_2 100%    000tma_fp_vector_256b Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P (SIMD_FP_256.PACKED_DOUBLE + SIMD_FP_256.PACKED_SINGLE) / UOPS_DISPATCHED.THREAD tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)) This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting prior to LNL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_512b, tma_port_6, tma_ports_utilized_2 100%    000tma_info_core_ilp Backend;Cor;Pipeline;PortsUtil UOPS_DISPATCHED.THREAD / (cpu@UOPS_DISPATCHED.CORE\,cmask\=1@ / 2 if #SMT_on else cpu@UOPS_DISPATCHED.CORE\,cmask\=1@)  Instruction-Level-Parallelism (average number of uops executed when there is execution) per thread (logical-processor)      000tma_info_frontend_dsb_coverage DSB;Fed;FetchBW;tma_issueFB IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS) tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 4 > 0.35 Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache) Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_lcp     000tma_info_system_dram_bw_use HPC;MemOffcore;MemoryBW;SoC;tma_issueBW 64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / tma_info_system_time  Average external Memory Bandwidth Use for reads and writes [GB / sec] Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_mem_bandwidth     000tma_info_thread_execute_per_issue Cor;Pipeline UOPS_DISPATCHED.THREAD / UOPS_ISSUED.ANY  The ratio of Executed- by Issued-Uops The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of "execute" at rename stage     000tma_lcp FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB ILD_STALL.LCP / tma_info_thread_clks tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs) This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage 100%    000tma_machine_clears BadSpec;BvMS;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn tma_bad_speculation - tma_branch_mispredicts tma_machine_clears > 0.1 & tma_bad_speculation > 0.15 This metric represents fraction of slots the CPU has wasted due to Machine Clears This metric represents fraction of slots the CPU has wasted due to Machine Clears.  These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache 100%  TopdownL2  010tma_mem_bandwidth BvMB;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=6@) / tma_info_thread_clks tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM) This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM).  The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_info_system_dram_bw_use 100%    000tma_mem_latency BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM) This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM).  This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics:  100%    000tma_memory_bound Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_L1D_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_DISPATCH) + cpu@UOPS_DISPATCHED.THREAD\,cmask\=1@ - (cpu@UOPS_DISPATCHED.THREAD\,cmask\=3@ if tma_info_thread_ipc > 1.8 else cpu@UOPS_DISPATCHED.THREAD\,cmask\=2@) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) * tma_backend_bound tma_memory_bound > 0.2 & tma_backend_bound > 0.2 This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two) 100%  TopdownL2  010tma_ports_utilization PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_DISPATCH) + cpu@UOPS_DISPATCHED.THREAD\,cmask\=1@ - (cpu@UOPS_DISPATCHED.THREAD\,cmask\=3@ if tma_info_thread_ipc > 1.8 else cpu@UOPS_DISPATCHED.THREAD\,cmask\=2@) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_L1D_PENDING)) / tma_info_thread_clks tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related) This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations 100%    010tma_x87_use Compute;TopdownL4;tma_L4_group;tma_fp_arith_group UOPS_RETIRED.RETIRE_SLOTS * FP_COMP_OPS_EXE.X87 / UOPS_DISPATCHED.THREAD tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6) This metric serves as an approximation of legacy x87 usage This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint 100%    000tma_fetch_bandwidth FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB max(0, tma_frontend_bound - tma_fetch_latency) tma_fetch_bandwidth > 0.2 This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues.  For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Related metrics: tma_dsb_switches, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp 100%  TopdownL2  000tma_frontend_bound BvFB;BvIO;Default;PGO;TmaL1;TopdownL1;tma_L1_group cpu_core@topdown\-fe\-bound@ / (cpu_core@topdown\-fe\-bound@ + cpu_core@topdown\-bad\-spec@ + cpu_core@topdown\-retiring@ + cpu_core@topdown\-be\-bound@) tma_frontend_bound > 0.15 This category represents fraction of slots where the processor's Frontend undersupplies its Backend This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound 100%  TopdownL1;Default TopdownL1 000tma_l1_latency_dependency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_l1_bound_group 4 * cpu_core@DEPENDENT_LOADS.ANY\,cmask\=1@ / tma_info_thread_clks tma_l1_latency_dependency > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric ([SKL+] roughly; [LNL]) estimates fraction of cycles with demand load accesses that hit the L1D cache This metric ([SKL+] roughly; [LNL]) estimates fraction of cycles with demand load accesses that hit the L1D cache. The short latency of the L1D cache may be exposed in pointer-chasing memory access patterns as an example. Sample with: MEM_LOAD_UOPS_RETIRED.L1_HIT_PS 100%    000tma_load_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group cpu_core@UOPS_DISPATCHED.LOAD@ / (3 * tma_info_thread_clks) tma_load_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3 100%    000tma_store_op_utilization TopdownL5;tma_L5_group;tma_ports_utilized_3m_group (cpu_core@UOPS_DISPATCHED.STD@ + cpu_core@UOPS_DISPATCHED.STA@) / (7 * tma_info_thread_clks) tma_store_op_utilization > 0.6 This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations  100%    000tma_backend_bound Default;TopdownL1;tma_L1_group cpu_atom@TOPDOWN_BE_BOUND.ALL_P@ / (6 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_backend_bound > 0.1 Counts the total number of issue slots that were not consumed by the backend due to backend stalls Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count 100%  TopdownL1;Default TopdownL1 000tma_bad_speculation Default;TopdownL1;tma_L1_group cpu_atom@TOPDOWN_BAD_SPECULATION.ALL_P@ / (6 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_bad_speculation > 0.15 Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear 100%  TopdownL1;Default TopdownL1 000tma_branch_detect TopdownL3;tma_L3_group;tma_ifetch_latency_group cpu_atom@TOPDOWN_FE_BOUND.BRANCH_DETECT@ / (6 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_branch_detect > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches 100%    000tma_branch_mispredicts TopdownL2;tma_L2_group;tma_bad_speculation_group cpu_atom@TOPDOWN_BAD_SPECULATION.MISPREDICT@ / (6 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_branch_mispredicts > 0.05 & tma_bad_speculation > 0.15 Counts the number of issue slots that were not consumed by the backend due to branch mispredicts  100%  TopdownL2  000tma_branch_resteer TopdownL3;tma_L3_group;tma_ifetch_latency_group cpu_atom@TOPDOWN_FE_BOUND.BRANCH_RESTEER@ / (6 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_branch_resteer > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch  100%    000tma_cisc TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group cpu_atom@TOPDOWN_FE_BOUND.CISC@ / (6 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_cisc > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to the microcode sequencer (MS)  100%    000tma_core_bound TopdownL2;tma_L2_group;tma_backend_bound_group cpu_atom@TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS@ / (6 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_core_bound > 0.1 & tma_backend_bound > 0.1 Counts the number of cycles due to backend bound stalls that are bounded by core restrictions and not attributed to an outstanding load or stores, or resource limitation  100%  TopdownL2  000tma_decode TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group cpu_atom@TOPDOWN_FE_BOUND.DECODE@ / (6 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_decode > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to decode stalls  100%    000tma_fast_nuke TopdownL3;tma_L3_group;tma_machine_clears_group cpu_atom@TOPDOWN_BAD_SPECULATION.FASTNUKE@ / (6 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_fast_nuke > 0.05 & (tma_machine_clears > 0.05 & tma_bad_speculation > 0.15) Counts the number of issue slots that were not consumed by the backend due to a machine clear that does not require the use of microcode, classified as a fast nuke, due to memory ordering, memory disambiguation and memory renaming  100%    000tma_frontend_bound Default;TopdownL1;tma_L1_group cpu_atom@TOPDOWN_FE_BOUND.ALL_P@ / (6 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_frontend_bound > 0.2 Counts the number of issue slots that were not consumed by the backend due to frontend stalls  100%  TopdownL1;Default TopdownL1 000tma_icache_misses TopdownL3;tma_L3_group;tma_ifetch_latency_group cpu_atom@TOPDOWN_FE_BOUND.ICACHE@ / (6 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_icache_misses > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to instruction cache misses  100%    000tma_ifetch_bandwidth TopdownL2;tma_L2_group;tma_frontend_bound_group cpu_atom@TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH@ / (6 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2 Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations  100%  TopdownL2  000tma_ifetch_latency TopdownL2;tma_L2_group;tma_frontend_bound_group cpu_atom@TOPDOWN_FE_BOUND.FRONTEND_LATENCY@ / (6 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2 Counts the number of issue slots that were not delivered by the frontend due to frontend latency restrictions due to icache misses, itlb misses, branch detection, and resteer limitations  100%  TopdownL2  000tma_info_core_upi  cpu_atom@TOPDOWN_RETIRING.ALL_P@ / cpu_atom@INST_RETIRED.ANY@  Uops Per Instruction      000tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l2miss  100 * (cpu_atom@MEM_BOUND_STALLS_IFETCH.LLC_HIT@ + cpu_atom@MEM_BOUND_STALLS_IFETCH.LLC_MISS@) / cpu_atom@MEM_BOUND_STALLS_IFETCH.ALL@  Percentage of ifetch miss bound stalls, where the ifetch miss doesn't hit in the L2      000tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l3miss  100 * cpu_atom@MEM_BOUND_STALLS_IFETCH.LLC_MISS@ / cpu_atom@MEM_BOUND_STALLS_IFETCH.ALL@  Percentage of ifetch miss bound stalls, where the ifetch miss subsequently misses in the L3      000tma_info_load_miss_bound_%_loadmissbound_with_l2miss load_store_bound 100 * (cpu_atom@MEM_BOUND_STALLS_LOAD.LLC_HIT@ + cpu_atom@MEM_BOUND_STALLS_LOAD.LLC_MISS@) / cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@  Percentage of memory bound stalls where retirement is stalled due to an L1 miss that subsequently misses in the L2      000tma_info_load_miss_bound_%_loadmissbound_with_l3miss load_store_bound 100 * cpu_atom@MEM_BOUND_STALLS_LOAD.LLC_MISS@ / cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@  Percentage of memory bound stalls where retirement is stalled due to an L1 miss that subsequently misses the L3      000tma_info_mem_mix_memload_ratio  1e3 * cpu_atom@MEM_UOPS_RETIRED.ALL_LOADS@ / cpu_atom@TOPDOWN_RETIRING.ALL_P@  Ratio of mem load uops to all uops      000tma_info_serialization_%_tpause_cycles  100 * cpu_atom@SERIALIZATION.C01_MS_SCB@ / (6 * cpu_atom@CPU_CLK_UNHALTED.CORE@)  Percentage of time that the core is stalled due to a TPAUSE or UMWAIT instruction      000tma_info_uop_mix_fpdiv_uop_ratio  100 * cpu_atom@UOPS_RETIRED.FPDIV@ / cpu_atom@TOPDOWN_RETIRING.ALL_P@  Percentage of all uops which are FPDiv uops      000tma_info_uop_mix_idiv_uop_ratio  100 * cpu_atom@UOPS_RETIRED.IDIV@ / cpu_atom@TOPDOWN_RETIRING.ALL_P@  Percentage of all uops which are IDiv uops      000tma_info_uop_mix_microcode_uop_ratio  100 * cpu_atom@UOPS_RETIRED.MS@ / cpu_atom@TOPDOWN_RETIRING.ALL_P@  Percentage of all uops which are microcode ops      000tma_info_uop_mix_x87_uop_ratio  100 * cpu_atom@UOPS_RETIRED.X87@ / cpu_atom@TOPDOWN_RETIRING.ALL_P@  Percentage of all uops which are x87 uops      000tma_itlb_misses TopdownL3;tma_L3_group;tma_ifetch_latency_group cpu_atom@TOPDOWN_FE_BOUND.ITLB_MISS@ / (6 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_itlb_misses > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses  100%    000tma_machine_clears TopdownL2;tma_L2_group;tma_bad_speculation_group cpu_atom@TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS@ / (6 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_machine_clears > 0.05 & tma_bad_speculation > 0.15 Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation  100%  TopdownL2  000tma_mem_scheduler TopdownL3;tma_L3_group;tma_resource_bound_group cpu_atom@TOPDOWN_BE_BOUND.MEM_SCHEDULER@ / (6 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_mem_scheduler > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops  100%    000tma_non_mem_scheduler TopdownL3;tma_L3_group;tma_resource_bound_group cpu_atom@TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER@ / (6 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_non_mem_scheduler > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops  100%    000tma_nuke TopdownL3;tma_L3_group;tma_machine_clears_group cpu_atom@TOPDOWN_BAD_SPECULATION.NUKE@ / (6 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_nuke > 0.05 & (tma_machine_clears > 0.05 & tma_bad_speculation > 0.15) Counts the number of issue slots that were not consumed by the backend due to a machine clear that requires the use of microcode (slow nuke)  100%    000tma_other_fb TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group cpu_atom@TOPDOWN_FE_BOUND.OTHER@ / (6 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_other_fb > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to other common frontend stalls not categorized  100%    000tma_predecode TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group cpu_atom@TOPDOWN_FE_BOUND.PREDECODE@ / (6 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_predecode > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2) Counts the number of issue slots that were not delivered by the frontend due to wrong predecodes  100%    000tma_register TopdownL3;tma_L3_group;tma_resource_bound_group cpu_atom@TOPDOWN_BE_BOUND.REGISTER@ / (6 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_register > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls)  100%    000tma_reorder_buffer TopdownL3;tma_L3_group;tma_resource_bound_group cpu_atom@TOPDOWN_BE_BOUND.REORDER_BUFFER@ / (6 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_reorder_buffer > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to the reorder buffer being full (ROB stalls)  100%    000tma_retiring Default;TopdownL1;tma_L1_group cpu_atom@TOPDOWN_RETIRING.ALL_P@ / (6 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_retiring > 0.75 Counts the number of issue slots that result in retirement slots  100%  TopdownL1;Default TopdownL1 000tma_serialization TopdownL3;tma_L3_group;tma_resource_bound_group cpu_atom@TOPDOWN_BE_BOUND.SERIALIZATION@ / (6 * cpu_atom@CPU_CLK_UNHALTED.CORE@) tma_serialization > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1) Counts the number of issue slots that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS)  100%    000tma_bottleneck_memory_data_tlbs BvMT;Mem;MemoryTLB;Offcore;tma_issueTLB 100 * (tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_load / (tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) tma_bottleneck_memory_data_tlbs > 20 Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs) Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store     000tma_cond_tk_mispredicts BrMispredicts;TopdownL3;tma_L3_group;tma_branch_mispredicts_group cpu_core@BR_MISP_RETIRED.COND_TAKEN_COST@ * cpu_core@BR_MISP_RETIRED.COND_TAKEN_COST@R / tma_info_thread_clks tma_cond_tk_mispredicts > 0.05 & (tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15) This metric represents fraction of cycles the CPU was stalled due to misprediction by taken conditional branches  100%    000tma_contested_accesses BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS@ * min(cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS@R, 24 * tma_info_system_core_frequency) + cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD@ * min(cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD@R, 25 * tma_info_system_core_frequency) * (cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM@ / (cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM@ + cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD@))) * (1 + cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / 2) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS. Related metrics: tma_bottleneck_memory_synchronization, tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100%    000tma_data_sharing BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD@ * min(cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD@R, 24 * tma_info_system_core_frequency) + cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD@ * min(cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD@R, 24 * tma_info_system_core_frequency) * (1 - cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM@ / (cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM@ + cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD@))) * (1 + cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / 2) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD. Related metrics: tma_bottleneck_memory_synchronization, tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100%    010tma_info_system_dram_bw_use HPC;MemOffcore;MemoryBW;SoC;tma_issueBW 64 * (UNC_HAC_ARB_TRK_REQUESTS.ALL + UNC_HAC_ARB_COH_TRK_REQUESTS.ALL) / 1e9 / tma_info_system_time  Average external Memory Bandwidth Use for reads and writes [GB / sec] Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_bottleneck_data_cache_memory_bandwidth, tma_fb_full, tma_mem_bandwidth, tma_sq_full     000tma_ports_utilized_0 PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group max(cpu_core@EXE_ACTIVITY.EXE_BOUND_0_PORTS@ - cpu_core@RESOURCE_STALLS.SCOREBOARD@, 0) / tma_info_thread_clks tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise) This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric 100%    040lpm_br_total_mispred lpm_br;lpm_br_total d_ratio(BR_MISP_EXEC.ANY, BR_INST_RETIRED.ALL_BRANCHES)  The number of branch instructions retired, of any type, that were not correctly predicted as a percentage of all branch instrucions  100%    000tma_info_system_mem_parallel_reads Mem;MemoryBW;SoC UNC_ARB_DAT_OCCUPANCY.RD / UNC_ARB_DAT_OCCUPANCY.RD@cmask\=1@  Average number of parallel data read requests to external memory Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches     010tma_dram_bound MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (1 - MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / tma_info_thread_clks tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS 100%    030tma_info_system_dram_bw_use HPC;MemOffcore;MemoryBW;SoC;tma_issueBW 64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / tma_info_system_time / 1e3  Average external Memory Bandwidth Use for reads and writes [GB / sec] Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_mem_bandwidth     000tma_l3_bound CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / tma_info_thread_clks tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core.  Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS 100%    030tma_bottleneck_data_cache_memory_latency BvML;Mem;MemoryLat;Offcore;tma_issueLat 100 * (tma_memory_bound * (tma_dram_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * tma_l2_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) + tma_memory_bound * (tma_l1_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l1_latency_dependency / (tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_l1_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_lock_latency / (tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_l1_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_split_loads / (tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_split_stores / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)) + tma_memory_bound * (tma_store_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) tma_bottleneck_data_cache_memory_latency > 20 Total pipeline cost of external Memory- or Cache-Latency related bottlenecks Total pipeline cost of external Memory- or Cache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_mem_latency     000tma_bottleneck_memory_data_tlbs BvMT;Mem;MemoryTLB;Offcore;tma_issueTLB 100 * (tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_cxl_mem_bound + tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) tma_bottleneck_memory_data_tlbs > 20 Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs) Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store     000tma_cxl_mem_bound MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group (((1 - ((19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) if #has_pmem > 0 else 0) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) if #has_pmem > 0 else 0))) if #has_pmem > 0 else 1)) * (MEMORY_ACTIVITY.STALLS_L3_MISS / tma_info_thread_clks) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0) if #has_pmem > 0 else 0) tma_cxl_mem_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2) This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external CXL Memory by loads (e.g This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external CXL Memory by loads (e.g. 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory, PMM - Persistent Memory Module [from CLX to SPR] or any other CXL Type3 Memory [EMR onwards]) 100%    000tma_divider BvCB;TopdownL3;tma_L3_group;tma_core_bound_group ARITH.DIV_ACTIVE / tma_info_thread_clks tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2) This metric represents fraction of cycles where the Divider unit was active This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE 100%    000tma_info_system_mem_pmm_read_latency MemOffcore;MemoryLat;Server;SoC (1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / uncore_cha_0@event\=0x1@ if #has_pmem > 0 else 0)  Average latency of data read request to external 3D X-Point memory [in nanoseconds] Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches     000tma_ms_switches FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO 3 * cpu@UOPS_RETIRED.MS\,cmask\=1\,edge@ / (UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY) / tma_info_thread_clks tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS) This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: FRONTEND_RETIRED.MS_FLOWS. Related metrics: tma_bottleneck_irregular_overhead, tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation 100%    000cpu_cstate_c6 cpu_cstate UNC_P_POWER_STATE_OCCUPANCY_CORES_C6 / pcu_0@UNC_P_CLOCKTICKS@ * #num_packages  The average number of cores that are in cstate C6 as observed by the power control unit (PCU)      000iio_bandwidth_read  UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.ALL_PARTS * 4 / 1e6 / duration_time  Bandwidth observed by the integrated I/O traffic contoller (IIO) of IO reads that are initiated by end device controllers that are requesting memory from the CPU  1MB/s    000llc_demand_data_read_miss_latency  1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT) * #num_packages)) * duration_time  Average latency of a last level cache (LLC) demand data read miss (read memory access) in nano seconds  1ns    000numa_reads_addressed_to_local_dram  (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_LOCAL) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_REMOTE)  Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches  100%    000numa_reads_addressed_to_remote_dram  (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_REMOTE) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_REMOTE)  Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches  100%    000tma_bottleneck_data_cache_memory_latency BvML;Mem;MemoryLat;Offcore;tma_issueLat 100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l1_latency_dependency / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_lock_latency / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_split_loads / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_split_stores / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency))) tma_bottleneck_data_cache_memory_latency > 20 Total pipeline cost of external Memory- or Cache-Latency related bottlenecks Total pipeline cost of external Memory- or Cache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_mem_latency     010tma_bottleneck_memory_data_tlbs BvMT;Mem;MemoryTLB;Offcore;tma_issueTLB 100 * (tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency))) tma_bottleneck_memory_data_tlbs > 20 Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs) Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store     010tma_bottleneck_memory_synchronization BvMS;LockCont;Mem;Offcore;tma_issueSyncxn 100 * (tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_contested_accesses + tma_data_sharing) / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * tma_false_sharing / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency - tma_store_latency)) + tma_machine_clears * (1 - tma_other_nukes / tma_other_nukes)) tma_bottleneck_memory_synchronization > 10 Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors) Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors). Related metrics: tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache     010tma_contested_accesses BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (18.5 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM + 16.5 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_bottleneck_memory_synchronization, tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100%    010tma_data_sharing BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 16.5 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_bottleneck_memory_synchronization, tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100%    010tma_false_sharing BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group 22 * tma_info_system_core_frequency * OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_bottleneck_memory_synchronization, tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100%    010tma_info_core_flopc Flops;Ret (FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / tma_info_core_core_clks  Floating Point Operations Per Cycle      010tma_info_inst_mix_ipflop Flops;InsType INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) tma_info_inst_mix_ipflop < 10 Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)      010tma_info_system_gflops Cor;Flops;HPC (FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / tma_info_system_time  Giga Floating Point Operations Per Second Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width     010tma_info_system_mem_parallel_reads Mem;MemoryBW;SoC UNC_ARB_TRK_OCCUPANCY.DATA_READ / UNC_ARB_TRK_OCCUPANCY.DATA_READ@cmask\=1@  Average number of parallel data read requests to external memory Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches     000tma_info_system_mem_read_latency Mem;MemoryLat;SoC 1e9 * (UNC_ARB_TRK_OCCUPANCY.DATA_READ / UNC_ARB_TRK_REQUESTS.DATA_READ) / (tma_info_system_socket_clks / tma_info_system_time)  Average latency of data read request to external memory (in nanoseconds) Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)     000tma_l3_hit_latency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 6.5 * tma_info_system_core_frequency * (MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2)) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_bottleneck_data_cache_memory_latency, tma_mem_latency 100%    000tma_lock_latency LockCont;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group (12 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (9 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / tma_info_thread_clks tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS. Related metrics: tma_store_latency 100%    010tma_store_latency BvML;LockCont;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group (L2_RQSTS.RFO_HIT * 9 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles the CPU spent handling L1D store misses This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency 100%    020llc_data_read_demand_plus_prefetch_miss_latency  1e9 * (cha@UNC_CHA_TOR_OCCUPANCY.IA_MISS\,config1\=0x40433@ / cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40433@) / (UNC_CHA_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time  Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) in nano seconds  1ns    000llc_data_read_demand_plus_prefetch_miss_latency_for_local_requests  1e9 * (cha@UNC_CHA_TOR_OCCUPANCY.IA_MISS\,config1\=0x40432@ / cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40432@) / (UNC_CHA_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time  Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to local memory in nano seconds  1ns    000llc_data_read_demand_plus_prefetch_miss_latency_for_remote_requests  1e9 * (cha@UNC_CHA_TOR_OCCUPANCY.IA_MISS\,config1\=0x40431@ / cha@UNC_CHA_TOR_INSERTS.IA_MISS\,config1\=0x40431@) / (UNC_CHA_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time  Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to remote memory in nano seconds  1ns    000tma_bottleneck_memory_synchronization BvMS;LockCont;Mem;Offcore;tma_issueSyncxn 100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) * tma_remote_cache / (tma_local_mem + tma_remote_cache + tma_remote_mem) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_contested_accesses + tma_data_sharing) / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * tma_false_sharing / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency - tma_store_latency)) + tma_machine_clears * (1 - tma_other_nukes / tma_other_nukes)) tma_bottleneck_memory_synchronization > 10 Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors) Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors). Related metrics: tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache     010tma_contested_accesses BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (44 * tma_info_system_core_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + 44 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_bottleneck_memory_synchronization, tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100%    010tma_data_sharing BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 44 * tma_info_system_core_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_bottleneck_memory_synchronization, tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100%    010tma_false_sharing BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group (110 * tma_info_system_core_frequency * (OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM + OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM) + 47.5 * tma_info_system_core_frequency * (OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE)) / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_bottleneck_memory_synchronization, tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100%    010uncore_frequency  UNC_CHA_CLOCKTICKS / (#num_cores / #num_packages * #num_packages) / 1e9 / duration_time  Uncore operating frequency in GHz  1GHz    000power_channel_ppd  UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS * 100  Cycles where DRAM ranks are in power down (CKE) mode Counts cycles when all the ranks in the channel are in PPD (PreCharge Power Down) mode. If IBT (Input Buffer Terminators)=off is enabled, then this event counts the cycles in PPD mode. If IBT=off is not enabled, then this event counts the number of cycles when being in PPD mode could have been taken advantage of     000LLC_MISSES.PCIE_READ  UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3  PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 4Bytes    000LLC_MISSES.PCIE_WRITE  UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3  PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 4Bytes    000power_channel_ppd  UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS * 100  Cycles where DRAM ranks are in power down (CKE) mode Channel PPD Cycles : Number of cycles when all the ranks in the channel are in PPD mode.  If IBT=off is enabled, then this can be used to count those cycles.  If it is not enabled, then this can count the number of cycles when that could have been taken advantage of     000power_self_refresh  UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS * 100  Cycles Memory is in self refresh power mode Clock-Enabled Self-Refresh : Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock.  This happens in some package C-states.  For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing.  One use of this is for Monroe technology.  Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases     000tma_contested_accesses BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group (49 * tma_info_system_core_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + 48 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS. Related metrics: tma_bottleneck_memory_synchronization, tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache 100%    010tma_data_sharing BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group 48 * tma_info_system_core_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD. Related metrics: tma_bottleneck_memory_synchronization, tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache 100%    010tma_false_sharing BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group 54 * tma_info_system_core_frequency * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / tma_info_thread_clks tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric roughly estimates how often CPU was handling synchronizations due to False Sharing This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_bottleneck_memory_synchronization, tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache 100%    000tma_l2_hit_latency MemoryLat;TopdownL4;tma_L4_group;tma_l2_bound_group 5 * tma_info_system_core_frequency * MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks tma_l2_hit_latency > 0.05 & (tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric represents fraction of cycles with demand load accesses that hit the L2 cache under unloaded scenarios (possibly L2 latency limited) This metric represents fraction of cycles with demand load accesses that hit the L2 cache under unloaded scenarios (possibly L2 latency limited).  Avoiding L1 cache misses (i.e. L1 misses/L2 hits) will improve the latency. Sample with: MEM_LOAD_RETIRED.L2_HIT 100%    000tma_l3_hit_latency BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group 17.5 * tma_info_system_core_frequency * (MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2)) / tma_info_thread_clks tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited) This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_bottleneck_data_cache_memory_latency, tma_mem_latency 100%    000          i[ q[ [ q[ [ q[ Ö[ q[ Ж[ q[ ޖ[ q[ [ q[ [ q[ [ q[ [ q[ [ q[  [ q[ [ q[ 
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[ ˘[ [ [ $[ 3[ 1[ g[ >[ [ K[ ϙ[ X[ u[ [ [ [ [ 7[ Q[ [ [ ۛ[ [ *[ C[ w[ [ [ Μ[ [ [ @[ T[ [ [ ȝ[ [ [ /[ b[ u[ [ [ [ [ 3[ N[ [ [ ϟ[ [  [ 9[ m[ [ [ Ơ[ [ [ [ *[ P[ ^[ [ [ [ ġ[ [ [ [ ([ N[ [[ [ [ [ [ [ [ [ %[ L[ X[ ~[ [ [ [ [ [ [ ,[ V[ c[ [ [ Ѥ[ [ [ %[ S[ f[ [ [ [ [ <[ U[ [ [ 2Vc JVc ֦[ [ [ 4[ f[ [ [ ̧[ [ [ E[ a[ [ [ [ [ <[ U[ [ [ ʩ[ [ %[ ;[ l[ [ Ū[ ߪ[ P ._ ._ /_ o0_ 2H[ I[ {J[ K[ L[ aM[ N[ N[ GO[ O[ Q[ tQ[ S[ T[ T[ KU[ U[ ;m[ m[ [  \ m\ )\ \ \ 
\ [         ,T T T WT ƂT -T '	Y T `T  ԄT 7T T 
T T T iT ̇T 4T T  T {T T {T ߊT MT T 8T T 8T T T T QX X T S S lT T T T T T _X T T T X vT OX 
Y ʳT GT @X X R|T tET ET nFT FT PGT GT 7HT HT 	IT vIT IT sJT JT lKT T YT T %T T ߓT T ST FT T 3T T T T |T T T  T X RT X IS S S |S S GS S 	S wS הS S @S S XS S S jS S S S YS S řS 1S S S S S cS S S S ҝS @S S )S S _S S  S S ]S S MS S S S S S XS BS S S `S ʥS #S S ۦS AS S S S S KS S  S S S MS AT X |T L}T }T ~T T S S T T gT ڙT ?T ŚT RT RT S &S ̭S pS S S _S S S LS S S 6S شS xS S S T "S S ?S S ;S ҹS T AY Y X Y &S PX %X U&X &X 'X 'X 'X S a(X (X S)X )X l*X *X +X +X S S ST OTT )S S HS S S lS S TT S 6S S }S wUT S VT VT S :S S S LS S S 2WT ;S S S  S WT S dXT XT \S S }S 7S S S 4S YT S qS S S ZT WS ZT F[T S vS S S S =S S [T qS 
S S SS p\T S ]T ]T S S S ?S S mS ^T S S 0S S ^T cS 0_T _T S S XS $S S S WS v`T S S wS %S  aT S aT _bT tS S S S [S 'S S bT gS S S \S cT S VdT dT S DS S S wS ;S S eT S ,S S S 4fT 6S fT tgT S mS S S S d T  T hT T UT T T hT _T ZiT iT T T ?T T T T "	T jT 	T u
T -T T 5kT |T kT rlT $T T YT T T T 8T mT T T @T T mT T RnT nT +T T LT T T sT T T @T T T toT &T pT pT T YT T T T H T  T BqT !T 3"T "T #T qT 7$T rT  sT $T j%T &T &T 'T Y(T (T sT )T D*T *T +T ^tT H,T  uT uT ,T y-T ".T .T /T d0T 0T 4vT 1T L2T 3T 3T vT M4T vwT xT 4T |5T $6T 6T 7T c8T 8T xT 9T H:T :T ;T HyT F<T yT ~zT <T q=T >T >T ?T P@T @T {T AT /BT BT CT {T {~T &T T ՛T ;T T T iT ؝T 9T T T tT T ~T GT KT \LT LT [MT MT LNT NT AOT OT ,PT PT 'QT QT RT T T gT CX X X WX X MX X CX X ɀT X 'DT HT ʠT LT ΡT PT DT ET ZST XT עT FT T *T T 3T 	Y  
Y T T DT T T T T sT T aT ۫T =T T T T T jT T OT įT 7T T                     ._ /_ o0_ 2H[ I[ {J[ K[ L[ aM[ N[ N[ GO[ O[ Q[ tQ[ S[ T[ T[ KU[ U[ ;m[ m[ [  \ m\ )\ \ \ 
\ [         ,T T T WT ƂT -T T T `T  ԄT 7T T 
T T T iT ̇T 4T T  T {T T {T ߊT MT T 8T T 8T T T T QX X T S S lT T T T T T T T T X vT OX ʳT GT @X X R|T tET ET nFT FT PGT GT 7HT HT 	IT vIT IT sJT JT lKT T YT T %T T ߓT T ST FT T 3T T T T |T T T  T RT X IS S S |S S GS S 	S wS הS S @S S XS S S jS S S S YS S řS 1S S S S S cS S S S ҝS @S S )S S _S S  S S ]S S MS S S S S S XS BS S S `S ʥS #S S ۦS AS S S S S KS S  S S S MS AT X |T L}T }T ~T T S S T T gT ڙT ?T ŚT RT RT S &S ̭S pS S S _S S S LS S S 6S شS xS S S T "S S ?S S ;S ҹS T X 8S ܻS X &S %X U&X &X 'X 'X 'X S XX a(X (X S)X )X l*X *X +X +X S S ST OTT )S S HS S S lS X X S lX S }S &X S VT VT S :S S S LS S X X ;S X S  S VX S dXT XT \S S }S 7S S S kX X S X S S X WS ZT F[T S vS S S S =S X X qS `X S SS X S ]T ]T S S S ?S S X OX S X 0S S X cS 0_T _T S S XS $S S S DX eX S X wS %S X S aT _bT tS S S S [S 'S X X gS `X S \S eX S VdT dT S DS S S wS ;S 	X X S X S S X 6S fT tgT S mS S S S d T rX [X T "X T T X _T ZiT iT T T ?T T T T X X 	T X -T T FX |T kT rlT $T T YT T T T BX X T X @T T X T RnT nT +T T LT T T sT X T KX T T -X X X _ Y X +X X X XX X X  Y bX X X bX Y 7$T rT  sT $T j%T &T &T 'T Y(T 	X ?Y )T X *T +T Y H,T  uT uT ,T y-T ".T .T /T d0T nX Y 1T X 3T 3T $Y M4T vwT xT 4T |5T $6T 6T 7T c8T X Y 9T }X :T ;T eY F<T yT ~zT <T q=T >T >T ?T P@T 2X Y AT X BT CT Y {~T &T T ՛T ;T T T iT ؝T 9T T T tT T ~T GT KT \LT LT [MT MT LNT NT AOT OT ,PT PT 'QT QT RT T T gT CX X X WX X MX X CX X ɀT X 'DT HT ʠT LT ΡT PT DT ET ZST XT עT FT T *T T 3T ХT gT T T DT T T T T sT T aT ۫T =T T T T T jT T OT įT 7T T ._ /_ o0_ 2H[ I[ {J[ K[ L[ aM[ N[ N[ GO[ O[ Q[ tQ[ S[ T[ T[ KU[ U[ ;m[ m[ [  \ m\ )\ \ \ 
\ [         ,T T T WT ƂT -T T T `T  ԄT 7T T 
T T T iT ̇T 4T T  T {T T {T ߊT MT T 8T T 8T T T T QX X T S S lT T T T T T _X T T T X vT OX X ʳT GT @X X R|T tET ET nFT FT PGT GT 7HT HT 	IT vIT IT sJT JT lKT T YT T %T T ߓT T ST FT T 3T T T T |T T T  T X RT X IS S S |S S GS S 	S wS הS S @S S XS S S jS S S S YS S řS 1S S S S S cS S S S ҝS @S S )S S _S S  S S ]S S MS S S S S S XS BS S S `S ʥS #S S ۦS AS S S S S KS S  S S S MS AT X |T L}T }T ~T T S S T T gT ڙT ?T ŚT RT RT S &S ̭S pS S S _S S S LS S S 6S شS xS S S T "S S ?S S ;S ҹS T PX %X U&X &X 'X 'X 'X S a(X (X S)X )X l*X *X +X +X S ,X R-X X dX -X .X +/X /X 0X ;1X 1X X 2X X >3X 4X DX X 4X D5X 5X 6X :7X 7X 8X X F9X 9X 9X :X ԢX X Y;X ;X <X B=X =X >X A?X (X @X ϤX @X pAX lX X 
BX BX 4CX CX DX /EX EX X ~FX OX GX GX X X yHX IX IX GJX JX KX +LX &X LX ĩX MX PNX XX X NX OX ,PX PX QX ?RX RX X SX SX ETX 	UX X X UX 9VX VX tWX XX XX [YX 4X ZX ӮX ZX [X hX X $\X \X ^]X ^X ^X q_X `X X `X cX waX IbX  X X bX cX 7dX dX eX \fX fX `X gX X thX DiX X iX iX jX ,kX kX lX KmX mX X nX X ]oX 'pX XX X pX cqX qX rX YsX 
tX tX X euX MX 
vX vX X X `wX wX xX %yX yX qzX  {X $X {X X S|X }X PX X }X G~X ~X X +X րX iX X %X 3X ĂX X ȾX {X .X ʄX dX X X qX 
X X ̈X X qX 6X XX X ъX hX X X OX X X X LX >X X X X X LX X xX  X ʓX vX 
X X ǕX X gX -X PX X ɗX aX X X KX X X X KX 9X {~T &T T ՛T ;T T T iT ؝T 9T T T tT T ~T GT KT \LT LT [MT MT LNT NT AOT OT ,PT PT 'QT QT RT T T gT CX X X WX X MX X CX X ɀT X 'DT HT ʠT LT ΡT PT DT ET ZST XT עT FT T *T T 3T ХT gT T T DT T T T T sT T aT ۫T =T T T T T jT T OT įT 7T T         Y Y SY Y &Y Y S+^ Y `d {Y B[ C[ E[ F[ G[ 2H[ H[ I[ {J[ 1K[ K[ L[ aM[ N[ N[ GO[ O[ P[ Q[ tQ[ 3^ R[ S[ S[ T[ T[ KU[ U[ [V[ a X[ Y[ a G\[ ][ Ba _[ T`[ ia b[ a aa a Ba a <a c[ a f[ f[ 	a 3i[ i[ ?Rc a ;m[ m[ an[ p[ q[ hr[ :s[ t[ t[ u[ jv[ w[ Zx[ x[ y[ 3z[ h{[ |[ |[ }[ }[ '~[ ~[ [ T[ [ Á[ [ 2[ Ń[ \[ N[ [ _d [ ?`d 	[ [ [ [ \[ [ /[ e[  [ K[ [ [ [ 
\ [ +^ bad bd fd Y M>` ?` A` jd od wd {d Rd Єd Jd` f` i` d Dd n` X] {t` Y 1b Y `w` x` z` f Y %f ` ` 8d ` 0` d +Ib f {Pb @Y d ad U Z d gd d d ͭd d d mb d wb Xd {b |b }b ~b ^ ` ` yd Ƚd ` ` pb b Åb 1Z b ΅^ ` dd y^ ^ d mb A` bd ` 4^ `  ` d ^ ^ ^ ގ^ ^ b^ ` 8^ ^ ^ ^ d ` 5d K` ` d VZ /WZ WZ }XZ E` H^ %` ` ^ L^ ^ ` w^ 9^ b 2` ^ ` ^ ˥^ b ` b }` ` ȥb W` =` d ` ` O` d b Y` b b ^ ExZ ݭ^ \yZ jd o^ ^ @^ Sf ԀZ ^ Z 6d d d b vZ Z ^ =^ &Z Ŷ^ ܷ^ b b \b 4d Z Q
a _ d d f Ca f a Z d Z !a b b Yb 4b Zd Z 3a e8a d d d Rd b d VGa d ,d 	c d Ic c >d d d d |d I]a he 
e >'c 0c e e o;c wa e h|a !_ e Cc d-[ a fEc Gc Ic 4Lc e ҍa ZA_ Y B_ C_     X X /!X     X X X .                 gY; 7   1   X  Y; !                     ; ; x;  dQ ; ; ; `; ; ;  ; Q!; !; w"; c$; %; %&; &; 2(; !); *; ; #; 9   ) +; 0;   e      1; M p: : : Z; h[; 4( o\; ]; $_; z`; a; Mb; ( 	"X V#X $X ig;     _X 0 - X   $  * * * O   : $: : ~: Z: B: ): {: 3: : 0: : : : 2: : : E: /: : : q: : *:   j: ? G :  : a: Q: zT7 : .: 92; = }X е  8; ;; $=; T<; l>; ?; gh; `i; ( M ) ) j; # )  de:   &5 f: g: 	i:  L e
 [    aX OX c    D> r@;  RX W bR  7 D;     j: l: l: m: n: o: p: q: -X u: 7X  w: X y: {: |: ~: : : ': c% ' ( }* 0, - / D1  F; =	X : : U; f  S b 1 C
X +X 9X  /X )X  : L  G; FI; G; + + + +  + z!+ 0: X : d: : : [: ) k) J;   ; ; <"+ #+ $+ L; L; M; N; O; P; vQ; dR; '+   	 
 x     C  aS; 'T; MX U W; nX;     f f f f         a a Sa F[ G[ 2H[ a I[ {J[ 1K[ K[ L[ aM[ N[ N[ GO[ O[ a Q[ tQ[ [ S[ B[ a ia 3a T[ T[ KU[ U[ ;m[ m[ [  \ m\ )\ \ \ >\ \ La a a a Na a 	\ s
\ >_ _ c_ e ˽a a 
\ [ 3& #0 0 0 0 0 gE F0 0 20 0 R0 0 >0 0 H0 0 >0 0 0 1  1 1 W& X& tX& 1                         X ( a( 3 y3 3 3 &3 w3 3 3 3 3 3 G3 3 HJ 3 63 JJ KJ MJ 83 r3 3                          YG PG GG >G 5G /G )G #G G G G G G G G G G G G G G G G G G G G G G G G zG qG hG `G XG PG HG CG >G 9G 4G /G 'G G G G G G G G G G G G G G G G G G G  H H H H H yH pH gH ^H X	H R
H LH FH @H 7H .H &H H H H 	H H H H H H W K.2 ]H |H H H @ H $$H .2 /2 Y%H (H F,H /H 5AH DH HH KH 93H 6H 4:H =H OH RH UH rYH \H _H 02 F32 52 z82 ;2 =2 N@2 B2 D2 F2 I2 SL2 	O2 Q2 xT2 1W2 W2 AX2 X2 QY2 Y2 gZ2 Z2 }[2 \2 \2 ]2 ]2 )^2 ^2 A_2 _2 \`2 NaH aH 	b2 b2 !c2 c2 9d2 d2 )e2 e2 +f2 f2 ?g2 g2 Vh2 h2 ii2 i2 uj2 j2 k2 l2 l2 m2 m2 +n2 n2 7o2 o2 Kp2 p2 _q2 q2 yr2 s2 s2 t2 t2 1u2 lbH cH u2 v2 v2 v2 \w2 w2 .x2 x2 y2 }y2 y2 Sz2 z2 /{2 {2 Ń2 ?2 2 32 2 K2 cH dH eH fH gH hH iH jH kH /mH mH nH nH oH zoH oH jpH pH WqH qH +2 2 ܑ2 2 2 j2 2 D2 2 ؚ2 "2 o2 !rH sH fuH wH xH FzH {H |H |}H B~H ~H H H OH H H tH H H CH H H EH H mH H H H "H H *H MH [H lH ]H H H H H šH H H H H OH H ͩH H NH H ҮH H SH H ѳH H RH H ָH H WH H սH H VH H H H [H H H H ZH H H  H bH H H $H eH H H +H lH H H 2 2H >H MH YH hH tH H qH bH PH AH /H  H H [H H H :H H H H H H H H  I  I I I I I I I I 	I t
I I I nI I 6I I I JI I I bI I MI I I e I !I #I M$I u%I &I (I c)I *I +I ,I -I .I N/I 70I ,1I 2I 2I 3I 5I P6I 7I 8I :I e;I <I =I ?I @I AI BCI DI *FI GI HI II JI KI LI MI wNI ^OI HPI /QI RI  SI SI TI VI aXI "ZI [I {]I H_I `I bI dI sfI 2hI iI kI gmI =oI pI rI tI YvI wI yI zI |I Q~I I I =I I I I I qI JI I I I uI I I  I ՒI I I ٗI I ҚI &I wI ˞I I pI I I UI I I I I 1I I I }I [I ԷI JI I I VI I -I I I I \I I GI                         0R@ 1S@ 2T@ 3U@ 4V@ 8W@ <X@ @Y@ DZ@ H[@ I\@ J]@ L^@ N_@ P`@ Ra@ Wb@ \c@ ad@ fe@ kf@ mg@ oh@ pi@ qj@ rk@ sl@ wm@ {n@ o@ p@ q@ r@ s@ t@ u@ v@ w@ x@ y@ z@ {@ |@ }@ ~@ @ @ @ @ @ @ @ @ Ƈ@ ǈ@ ȉ@ ʊ@ ̋@ Ό@ Ѝ@ Վ@ ڏ@ ߐ@ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ 	@ @ @ @ @ @ @ #@ (@ *@ ,@ @ @ x@ @ |q! @@ ԭ@ K@ @ :@ g@ @ @ @ @ *@ A@ @ B@ @ m@ @ j@ @ I@ @ X@ @ m@ @ l@ @ q A A A yA A ~A A c	A 	A h
A 
A A HA A A _A A JA A A >A A CA A .A A A "A A 'A A 'A (A A 2 A T"A "A #A #A L$A $A (%A %A %A p&A X'A 'A K(A 9)A )A *A *A *A a+A +A B,A .A /A 1A W 22A W 2A 3A W 4A W ^5A 4W .6A 6A W 7A :8A 8A H9A 9A P:A :A V;A ;A <A I=A =A H>A >A S?A ?A Y@A @A VAA NBA BA CIA %JA KA zLA LA _MA ?NA NA NA OA PA PA QA RA dRA RA SA TA UA WA XA AYA CZA t[A \A )]A ]A ;^A ^A -_A _A 1`A `A 2aA aA bA bA eA eA ! ! fA `! fA _gA ! ! t! ! gA riA kA lA pnA pA qA rA fsA 6tA tA uA vA kwA ;xA xA zA [|A ~A A ^A A A gA A tA A A ԌA ύA A A 5A PA KA ~A A A A A A 6A WA bA A A =A A ҦA A jA A A HA A گA &A rA A 
A SA A A .A zA ƼA A ^A A A 9A A A A fA A A GA A A )A tA A A XA A A " " A 2A A iA 7A A xA A K#" "" #" $" k$" $" 5%" %" A :A A A &A A A A A rA A JA A "A A A A A {A A XA A iA A LA A (A A aA A A A A ,A A A A sA A A A A A 
A A A A A ~A A A ,A A nA A /A 5 B >B ZB `B iB B B B mB x	B 
B B B |B B XB B B pB B LB B B ~B B aB B -!B "B #$B %B &B N(B )B *B !,B y-B .B -0B 1B 2B 3B 4B 5B T6B G7B F8B 09B :B :B N<B =B >B @B uAB BB 'DB xEB FB ,HB IB JB kLB MB aOB PB QB RB SB TB UB VB |WB pXB aYB UZB F[B <\B 2]B _B `B bB ,dB fB gB iB }kB KmB 1oB pB rB itB MvB -xB yB {B }B qB B B +B B B 9B B B B hB HB +B B B B B B AB B B 
B ɜB B 'B B B B VB B B jB ȫB B mB ˯B %B B B B B |B B kB B B B B B XB B CB B B B B B B B pB &B B $B  B B   C  C C C bC C C &C C C C cC C C {C 	C 
C 
C [C C >C C C :C                         'A@ B@ v. C@ FD@ K! ! E@ J! ! ! t ! . . . . . :. Ώ. =. . <. ͑. ^. %. . ߔ. . . . E@ 5F@ F@ G@ G@ H@ H@ H@ ]I@ I@ .! /! 0! 1! 2! k. Ϙ. -. . . L. . UJ@ NL@ ?! NN@ @! NA! A! A! SB! B! C! XC! C! D! P@ I. Q. Y. V. . Ƞ. vI                          W  W I qI 9I I I I I 1I I I I W I I RI I I I @ J  J  J jW v3 z3 5}3 X3 {3 3 W 3 3 J W J 5 X X J &J rJ J J J J =J 3 3 $3 ף3 2J 3J 5J _9J b3 A3  3 3 =J ?J 2BJ DJ         1 /1 1 1 61 1 1 =1 E                             [W >W !W E XE @E E E E hE E E OE E bE .E \E E E E E HE yE E )E E ~E 	E E BE E E ZE E dE E E ;E E n F DF F }F F ~F 	F F CF F jF :F F gF F _F F F F F < F 	"F #F 0%F &F N(F )F +F -F P/F 0F 2F 4F g6F 8F 9F :F <F I>F ?F nAF =CF DF hFF GF IF 8KF 5MF NF PF nRF nTF #VF WF YF S[F \F ^F `F qbF  dF fF gF iF VkF lF @nF pF qF 1sF tF vF xF yF 0{F |F V1 X1 &Z1 [1 ]1 z_1 a1 b1 Z~F F W <W W 3W F FF F _F ڍF CF W QW W FW F F )F ěF <F F ȟF eF F ,F ~F F sF F @F F F F GF F ԵF ׷F F jF "F ȾF nF kF F F F F YF 1F 1 1 51 c1 u1 1 Ó1 1 l1 1 ܘ1 !1 Z1 1 Ӝ1 F 1 A1 1 F F F F WF F F 1 01 F TF %F 'F )F F F F 1 1 1 1 ?1 /1 )1 1 ʰ1 1 m1 Z1 tF F F F F F F F ]F 0F F YF 1 01 ϶1 f1 1 1 1 1 F 1 1 F F F F IF rF F F F F F \1 1 1 1 F EF F AF G G MG G G <	G 
G yG G oG AG G rG G G XG G G G yG E!G "G j$G %G 'G >)G *G i,G -G M/G 1G 2G 54G 5G 7G  9G :G %<G =G ?G @G dBG 
DG EG ^GG HG JG LG MG NG PG FRG SG iUG 7WG XG `ZG [G ]G -_G )aG bG dG _fG ^hG jG kG mG 1 1 ^1 /1 1 1 1 ^1 ?oG pG /rG sG uG )wG xG zG |G }G 7G πG 1 1 1 i1 1  2 2 p2 gG ΃G 5G G fG G oG 0G G ?G G G }G 8G G ;G G iG ܝG rG G .G wG G lG G 9G ܪG 4G G G G _G bG G G G G nG LG G G <2 <!2 "2 $2 ~&2 (2 9*2 ,2                             f; `; Z; T; N; K; H; E; B; ?; 9; 3; .; ); $; ; ; ; ;  < < < < < < < < < < 	< 
< < < < < < < < < < < < < < < < < < < < < <  < !< "< }#< x$< s%< n&< i'< g(< e)< c*< a+< _,< Z-< U.< O/< I0< C1< =2< :3< 74< 45< 16< .7< (8< "9< :< ;< << =< >< 
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= T= W = = Z+ = = = + = + '+ + +  3+ |+ &= = `= = `= = c= = m =  = != "= "= #=  $= $= -%= %= .&= &= 0'= P)= )= c*= *= o+= += n,= ,= q-= -= m.= 3, , 3= 75= 6= c8= g
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= 1= = := ]= = = {= , != = k, P= = D= E= = k, Z= = 	> j> > > %> , 5> 6K> Z> ]> e> [g> h> p> lr> s> I- v> x> M- y> {> t|> }> $> > > W- > > > > :> > g- G> ڔ> ^> '> ~> > <> w> ֣> N> Ŧ> > 0> > ߪ> 
> 7> k> ǰ> g> > r> > P> > - r- > - > ;> "- 7> > W> > > - S> > > > (> > }> - P> :> 1 ? ? . =	. 
. Z.  ? ? . e. . ? . p? ? ". ? =? ? (. @? ? S-. y? "? ? 8 ? b>. "? /$? %? (? )? &+? &? ,? D.? /? 0? 2? P3? 5? 7? 8? ;? <? =? >? ?? @? A? B? C? D? E? F? G? H? I? J? L? `M? N? O? cQ? R? 1T? U? V? NX? Y? #[? o\? ]? `_? `? 5b? c? d? 'f? rg? h? i? Lk? l? m? 
o? p? p? q? r? }s? ut? Xu? >v? w? ax? y? z? |? l}? ~? ? Z? ?  ? l? ? *? ? ? ^? R? I? =? 4? ? ? ? ? ̔? ? ? ? ? W? ? ԝ? _? 3? ? ? ? [? :? ? ɭ? ]? :? ? Դ? ? ? ;? ӻ? v? ? ? B? ? ? 7? ? ? ? ? z? V? ? ? ? ? *? ? A? ? ? I? ? ? ? \? ? ? [? ? ? I? ? ? g? ? H? @ 
@ |@ @ ? 1? ? "@ Y@ @ :@ @ "@ ?$@ g&@ )@ \-@ 0@ `. a. b. nd. I4@ 5@ 7@ 9@ f. g. Ki. j. :@ W<@ =@ ?@ l. um. ]n. Fo. 1p. p.                             {	 }	 ~	 ~	 ~	 3* T5* P6* 7* 8* s:* ;* <* =* >* FB* rC* D* F* %G* vH* $* *  * X!* !* "* @$* $* b%* 3) <  <I* I  K* `) cK* |	 } b* Uc*  1 `d* ƨ
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 F t* 
 .
 Iv* 6)   O 8) $P* R* .T* w* U* :) ;) W*     Y      h" )# # $ =) e>) ?) A) B) @D) E) F) H) I) J) y* mz* {* K) $M) [N) ~O) ) ) W+* ) P) S) T) Q) +V) zW) ) ) ) =,* X) Z) l) ) 1[) m ) o Fr (t ]p ]) ^) ) x) ) `) ) (b) f) `h) c) j) l) ) r) 1) n) Iq) ) sr) t) v) s) rw) x) ) ) ?) y) ڀ h)  Ɖ  t 0{) }) ) p) ) ) M M) ) ) ) ) *) () ) ӊ) ) ݈) ǎ) ) s) ) G) U) c) ) ) ) ) )  ) ) ) J) ) )  * ԡ) ) ) !) ۨ) ) C* * * I) G) ) 8* * ð)  ) * 	* -* h
* * &O ?) * .* .* * ) * 3) ) G) ַ) ) ) I* * * ) |P  ) @* <* 
0* >* ) y) ) ) ) ) $* %* ,* 0* 2* g) * * W*  G[*  j\* ^       
]*    1  k     t]* a Z^* \) "_* `* a*     f a a sa         Y *^ SY Y &Y Y S+^ {Y _ _ (_ <` _ >_ #` m` _ _ }_ ` J_ _ ` d ` e_ *!` f ef f '` /(` (` )` *` k+` [ 	a @[ F[ G[ 2H[ H[ I[ {J[ 1K[ K[ L[ aM[ N[ N[ GO[ O[ P[ Q[ tQ[ ْa R[ S[ S[ a ia 3a T[ T[ KU[ U[ a a a a Ja [V[ a X[ Y[ a G\[ ][ Ba _[ T`[ ia b[ a aa a Ba a <a c[ a f[ f[ 	a 3i[ 1_ a a ;m[ m[ 3_ 6_ 6_ 7_ 8_ _9_ t[ Ou[ jv[ ҳa a Ca ^a a a w[ Zx[ x[ y[ z[ h{[ |[ |[ :_ }[ '~[ ~[ [ T[ [ Á[ [ 2[ Ń[ >_ _ c_ a a Na  a a ˽a a \[ Z;_ <_ <_ =_ Z>_ ?_ ?_ @_ [ [ \[ [ /[ e[  [ K[ [ [ [ za a s_ _ r_ ",` -` _ _ _ 
\ [ #4` +^ 4` I6` w:` 7^ M>` ?` A` jd Tf Q` V` f f Jd` f` i` uk` n` q` {t` Y `w` x` z` f I^ f ` ` 8d ` 0` )` ` f ` ` p_ ` ı` ` o^ ` t^ w^ `` r_ 3` ` ` ` O^ ^ ` ` ` ;` ` ` 2` ` ` ^ ΅^ ` ` 7` ^ j` Z` A` ` ` 4^ `  ` ^ ^ ^ ` ^ b^ ` 8^ ^ ^ ^ [` ` K` ` ` VZ /WZ m` =` WZ }XZ E` H^ %` ` ^ L^ ^ ` w^ 9^ ^ 2` ^ ` ^ ˥^ ^ ` }` ` W` =` -` ` ` O` ` Y` ` _^ ^ ExZ ݭ^ ` e` 1` $` o^ ^ @^ ` z` Ra ^ p` a a a ̴^ 	a Z ^ Z =^ &Z Ŷ^ ܷ^ \^ ^ ^ Q
a _ Ha La `a Ca a a R^ =a B a !a c#a %a 'a *a ,a 0a 3a e8a ;a \?a @a Da _ VGa Ia Na Qa \Sa Ua ^Wa ^ |^ ^ c^ )^ ^ #^  _ Xa I]a _a Pda Sha Jja na _ hqa ua wa rya h|a !_ Ta (_ d-[ a qa a a ?a ҍa ZA_ B_ B_ C_ .f la a         % h% 8% % % >% % ,% %  % % % % 9% % %% % #% % % h% % x% % % 
% |% % % % % z% % % P% % X%  % % N% % % K% % % % % H% % % % % & & ^W W & & & & 
& & E& & & & & Q& ^& & & & m& & & *& & W& & & & 5&  & "& 7%& %& && && && e'& -& '& H(& (& $)& )& *& w*& *& S+& ,& /-& /& ]0& 1& 1& V2& 2& 4& X5&  6& 6& 3& *4& X7& 7& 8& -9& 9& ;& <& =& >& @& $A& B& #C& D& C& 1E& F& F& G& H& mH& H& YI& I& NJ& J& 8K& K& zL& L& mM&  N& O& Q& 4R&             3& R& S& 6T& T& U& V& "W& W& X& tX& bl                 v ( a( ( ( ( (   9  ( y     M ( )( ( F( O v  (                             " e" 2" " " " l" 9" " " " p" @" " " " t" D" " " " {" H" " " "  # O# # # # # V# ## # # # ]	# *
# 
# # # d# 5# # # # |# P# # # # C# # # L# # # {# k# Y# # "# ^%# (# 
,# ]/# 2# 	6# _9# <# @# aC# zE# G# vH# I# I# PJ# J# K# }L# VM# /N# O# O# P# Q# tR# OS# *T# U# U# V# W# X# Y# Y# 2Z# Z# &[# [# ,\# \# I]# ]# ^# _# `# a# b# c# d# e# g# g# i# i# j# Ul# m# n# n# o# p# q# r# s# 7u# @v# w# x# y# u{# |# }# # f# _# # 8# p# # ̇# 1# ,# |# 	# A# # # # # M# ڕ# # # # # 6# # # # ڟ# $# # ݣ# (# -# # # ˩# R# # # ŭ# # I# '# ΰ# z# D# 
# X# # # [# l# # u# # *# K# # # =# # # S# # # # # # # # # <# # # # # # # # # :# # n# # v# # # # *# # # # ?# # 3# # # t# %# # }# f# E# # # # b# # # # q# 8# q#  $ $ 5$ 1$ 	$ $ S$ $ $ 5$ ;$ $ .$ R$  $ "$ $$ &$ ($ s+$ -$ /$ 1$ 4$ 6$ ?8$ :$ D<$ =$ H?$ A$ PB$ C$ E$ aG$ I$ eJ$ L$ mM$ O$ P$ lQ$ Q$ SR$ S$ S$ (T$ T$ U$ <V$ V$ W$ X$ aZ$ [$ <]$ ]$ y^$ _$ _$ S`$ `$ gb$ c$ Xe$ f$ Ih$ i$ 8k$ l$ m$ m$ n$ o$ p$ {q$ ir$ Ts$ ?t$ -u$ v$ #w$ .x$ 9y$ Dz$ R{$ `|$ k}$ v~$ $ $ $ $ $ $ Ʌ$ Ԇ$ $ $ $ $ $ $ *$ 8$ $ $ 0$ ֑$ $ ,$ ד$ $ t$ h$ \$ T$ $ $ [$ $ $ f$ $ ĝ$ f$ $ $ J$ $ $ 9$ $ 1$ $ '$ $ %$ $ $ $ ï$ ̰$ Ʊ$ $ $ $ ĵ$ $ b$ 6$ !$ $ $ $ Ѽ$ $ $ $ j$ R$ :$  $ 1$ B$ S$ b$ v$ $ $ $ $ `$ $ $ X$ $ $ T$ $ $ U$ $ $ Z$ 
$ $ j$ $ $ [$ $ $ C$ $ $ 0$ $ ($ $ $ $ $ $ $ $ $ $ $ $ z$ $ $ $ $ $ $ "$ :$ $ $ $ $ x$ I$ $ $ $ $ d$  % % % % % 6% `% % 	% 
% % 8% S% q% % % % % % S% % % ~% 6% N% i% % % % % % *!% Y"% #% ]$% 5%% 
&% &% '% (% Z)% (*% *% +% ,% Z-% .% /% >1% 2% %4% 5% a7% 8% }:% <% =% >% @% 9B% C% AE% F% .H% qI% J% L% M% N% TO% 	P% P% vQ% .R% R% jT% U% eW% X% BZ% [% :]% [^% _% `% a% b% 	d% e% e% f% >g% g% h% ii% j% j% k% l% |m% Xn% 3o% o% q% qt% w% {% _~% % % Q% % % =% % ט% % % I% n% f% w% B% Q% % ̷% ȸ% ݹ% % % % 0% '% 7% % % a% % % % j%                 H! }I! HJ! K! K! L! zM! EN! O! O! P! tQ! BR! S! S! T! nU! <V! 
W! W! X! kY! 6Z! [! [! \! h]! 3^! ^! _! `! ea! 0b! b! c! d! be! -f! f! g! h! \i! *j! j! k! l! fm! 8n! 
o! o! Zp! p! 4q! |q! q! r! \s! Mt! mu! iv! 3w! <x! x! 2y! y! (z! z! {! {! {! }! ! ! ! l! ! f! ! Z! х! H! ! ! ! ! ! ! ! x! \! >! ,! ! m! ! ! l! ! ! e! ! ! ^! ! ! ! 8! ! j! ܾ! ! e! ! e! ! Z! _! ! ! !  ! ! ! >! ! o! H! !! ! ! ! ! ! 	! ! ! ! 	! ! ! ! $! r! ! ! m! ! }! ! ! ! ! ! W! `! ! ! t! ! .! ! ! o! ! w! ! ! K! ! ! ! q! ! [! ! I! ! ! ! d! E! )! 
! ! ! ! ! !  " " " " " " " " " 	" 
" " " " " " "" ." :" C" L" U" ^" j" " " u" " Q" " 0" "  " x "  " D!" !" "" "" K#" "" #" $" k$" $" 5%" %" &" &" )(" ("  '" '" V)" )" F*" *" H+" +" L," ," Q-" -" A." ." P/" /" U0" 0" G1" 1" V2" 2" e3" 3" n4" 
5" 5" J6" 6" \7" 7" k8" 8" p9" 9" Z:" :" ?;" ;" `=" =" 7<" <" >" >" }?" @" o@" @" ~A" A" tB" B" C" 2D" D" {E" E" qF" F" G" H" }I" SJ" ,K" K" L" M" kN" =O" P" ,Q" OR" oS" T" U" V" W" %Y" MZ" u[" \" ]" ^" _" a" /b" Kc" dd" e" e" f" ?g" g" h" i" j" k" 	m" "n" 8o" ep" q" r" s" t" u" hv" >w" x" x" y" |z" E{" |" |" }" a~" " " " g" " " " " >" Ѝ" )" ː" i" " m" ܖ" V" " !" " " " p" #" ٠" " B" " z" " q" " J" ׫" >" ]" " " " ߲" " " b" " " J" " " 6" " " " h" " " " y"  " " M" " Y" " g" " h" " \" " V" " E" " )" " " }%                         l! ! ! ! ! ! X! ! ! K! ! ! J! ! ! t !  ! D!! !! O"! "! l#! #! A$! $! W%! %! R&! 
'! '! j(! )! )! *! *! C+! +! #,! ,! -! -! -! .! .! /! 0! 1! 2! l3! 3! ,4! 4! 4! H5! 5! 6! 7! 9! ;! ?! m=! @! NA! A! A! SB! B! C! XC! C! D! _D! DE! $F! F! dG!                 ' ' t'  '   p ~' ( ( ( ( l( 	( 	( 8( ( ( ( (  j  q  &  W  NW j j j j j m p s v  "(  -  w   l   t $	 .%( &( '(    0   C(( (( )( j)( )( 6*( *( +( h+( +( 0,( ,( ,( V-( -( .( |.( .( V/( /( G0( 0( ,1( 1( 1( N2( 2( 3( 3( 3( L4( 4( 5( r5( 5( 66( 6( 6( \7( 7( L8( 8( ?9( 9( :( f:( :( 2;( ;( ;( d<( <( ,=( =( =( R>( >( ?( x?( ?( R@( @( CA( A( (B( B( B( JC( C( D( |D( D( HE( E( F( nF( F( 2G( G( G( XH( H( HI( I( ;J( J(  K( bK( K( .L( L( L( `M( M( (N( N( N( NO( O( P( tP( P( NQ( Q( ?R( R( $S( ~S( S( FT( T( U( xU( U( DV( V( W( jW( W( .X( X( X( TY( Y( DZ( Z( 7[( [( [( ^\( \( *]( ]( ]( \^( ^( $_( _( _( J`( `( a( pa( a( Jb( b( ;c( c(  d( zd( d( Be( e( f( tf( f( @g( g( h( fh( h( *i( i( i( Pj( j( @k( k( 3l( T n( p( Z [ [ ( m( ( m( a d ( ( ܘ( >( ( 
( p( ֚( <( ( ( f( Ȝ( *( ( ( P( ( *( ( ( (  ( Z( ( "( ( ( T( (  ( ( ( F( ( 
( l( Φ( 0( (  ( ( ( ~( ة( :( ( ( l( ҫ( 8( (  ( b( ĭ( &( ( ( L( ( &( ( ( ( ( V( ( ( ( ( P( ( ( ~( ( B( ( ( h( ʷ( ,( ( ( ( ( z( Ժ( 6( ( ( h( μ( 4( ( ( ^( ( "( ( ( H( ( "( ( ( ( ( R( ( ( ( ( L( ( ( z( ( >( ( ( d( ( (( ( ( ( ( v( ( 2( ( ( d( ( 0( ( ( Z( ( ( ( ( D( ( ( ( ( ( ( N( ( ( |( ( H( ( ( v( ( :( ( ( `( ( $( ( ( ( jf                     X& [[& ]& x^& _& _& W`& `& a& b& b& c& c& ,d& d& Ze& e& f& g& 
i& Lj& kk& yl& m& n& p& Hq& fr& ss& t& u& v& 5x& Oy& Xz& a{& |& }& & ,& 4& <& Ʉ& & & 6& ?& H& ֏& & $& G& O& W& & b& & & 1& Q& & a& & & 2& Q& & & & & & & M& l& & ͻ& &  & & & & & & & & & & & & & & & & & '& )& :& ?& V& m& & & & & & '& z& & !& & ]& & & M& & w& & & W& & & & & `& & & }& 2& & & `& & & & 9& & & Z&  '  ' ' 6' ' ' T' ' ' ^' ' ' s' *	' 	' 
' P' ' ' z' 3' ' ' `' ' ' ' D' ' ' s' .' ' ' `' ' ' ' A' ' ' h' !' ' ' L ' !' !' v"' ,#' #' $' O%' &' &' v'' .(' (' )' X*' +' +' ,' 8-' -' .' d/' 0' 0' 1' M2' 3' 3' !4' 4' 5' t5' 5' Z6' 6' B7' 7' *8' 8' 
9' z9' 9' \:' :' z;' &<' <' ~=' +>' >' F?' ?' "@' @'  A' pA' A' RB' B' 4C' C' D' D' D' pE' E' VF' F' xG' &H' H' I' 1J' J' K' @L' L' M' QN' N' O' UP' Q' Q' [R' 	S' S' eT' U' U' qV' W' W' rX' Y' Y' uZ' "[' [' |\' )]' ]' ^' 2_' _' `' 9a' a' b' Dc' c' d' Qe' f' f' 'h' Yi' j' k' m' "n' o' p' r' Ms' mt' u' v' +x' {y' z' {' |' P~' |' ˀ' ' ' -' ' ,' ' ύ' ' ' ' ' `' ' Ț' ' ˞' D' ̣' I' |' ' ' ' ' ' K' }' ' ' _' ' ' ' 6' p' ' ' ' ' ' ' ' ' |' ' ' ' ' ' >' N' ' ' ' '  ' B' s' ' ' ' ' '  ' 1' b' ' ' H' ' ' K' ' ' Z'                           n  v     -  C  \  w  w    =  O  <  L  W  s  /   K  `  G  1  U  A  Y  q '   s 7    M    c '   s :    M    c '   v =    M    c '   y A 	   d /    W X   a  # v : 	  j #   T   " P% '' O( g) * , g- B. )/ 0 1 =2 2 M3 4 4 H5 5 6 77 68 8 9 q: = A [D G J ?N Q T &X q[ ^ b d /f $g h i .j ]k l m 
o o Vp q q ,r r <s s v x { O}       ˅   w   w ] C )   u N '     ޓ  <  l  g  ` ڤ  8  " ,   6  ڮ  ~ L 0   j ۴ l ݵ N  B ŷ M  ?   P   ^ Խ J Ⱦ A  0  "   b 
 }  e  V  d  p  t    f        U  )   d  0   p  :    T    P    p \ C *      f | ] B !         )              I   z 1   U	 	 
  V 
  { ;    I    @    ]    D    :   n  ! ! " c# $ $ % & N( ) + + B, , j- . . 0 t1 2 P4 5 07 8 x9 U: /; 	< < = > ? i@ KA 0B C D F P\ {^ O GQ BT U W Z j l ` b bd e g 9i <H H I J L 5M wN n o p q r s t u v w x y z { | } ~  À Ł ǂ Ƀ ˄ Ѕ  s v P r ׌ ڍ  6  @ ǒ ]  \  p      y U   j .     Ӫ   W       5  ɶ  R  v   F 9  y   F     I    R   )    { J    ~ F        $ = ^     	  0 B T i { *   :         ! G m   _ .    d &   r	 4
 
  F  I  .  .  K  (  Z   P" # +% e& ' g) * l+ , , v- ". . o/ 0 j2 3 %5 6 58 9 : ; < = ? .@ V Y ] :` ac f i l 8A C F UI 
L N sQ T o /s vv y } K  ن  e   2 < D * .  .  4   0  ު >   a  #   R      \  ,   .  X     M  ~   B  l   3  a   ,  V         G    u      @    n      6    m  
	  	  D
  
        A    8    P    _    s          9    W    k    z          !    E    ]    v      5    g   !  !  6"  "  `#  #  $  =%  %  y&  '  '  X(  (  )  5*  *  a+  +  ,  -  -  Q.  .  /  -0  0  A1  1  T2  2  j3  3  4  5  5  6  6  +7  7  %8  8  V9  9  :  ;  ;  D<  <  =  o=  =  7>  >  /?  ?  I@  @  cA  A  }B  
C  C  8D  D  qE  F  F  6G  G  dH  H  jI  I  {J  	K  K  L  L  GM  M  N  O  O  IP  P  cQ  R  R  6S  S  aT  T  U  /V  V  dW  W  X  -Y  Y  XZ  Z  [   \  \  O]  ]  ^  &_  _  Z`  `  a  (b  b  ]c  c  d  e  e  (f  f  6g  g  Jh  h  i  j  j  Wk  k  l  m  m  In  n  ~o  p  p  Fq  q  {r  s  s  Gt  t  ru  u  v  6w  w  ex  x  y  /z  z  k{  |  |  ;}  }  T~  ~    -  ƀ  \      *  ƃ  _      !    L    }      A  ڊ  v      B  ܍  m      1  ɐ  `          F  ͔  W  ޕ  e    v      ,    Q  ߚ  p          #    9  ɟ  V    s           H        !    -    !    F  ܥ  s    T    ԫ  q      .      1  ر    &  г  z  !  ȵ  o      j      _      Z      O      J    w      9    ^          @    y      M    ~      F    p      ,    U    r          @    q      9    _          G    t      1    V    {      A    z      J    {      C    p      ,    U    z      $    A    V          O    |      8    a          Q          R     ! !! ! K! ! a! ! ! ! ! P! ! 	! ~! ! ! D	! ! r
! ! ! >! ! p! ! ! B! ! x! ! ! >!     ={ dQ | | 
~  H w b t U D f/ `2   ": , X  i  9  
* {* * Z+ + 7, , 6  o  Ɏ  1 ڕ Ж J  UK K }M   Q S - t dW US U W ( @( ( 4( ( ( F( ( ( )( ( ( ( ( B( ( (       # >& f) |, / W %W < A D rG 05 QP C[ ]\ ] ^ _ 4` a b d e f h i +k l n &o ?p r Ĕ  Y   C    s (t t u Wv - - w x Kz { V} ~ Y  < w م  A a     g g  Ē  =   . Ƥ æ  D  4 )( H( z( 	( ( ( M ) ) ) . / 1 x4 = &5 5 Q7 98 8  y9 D D : e
 [  H _; mK 9< == K c  D> (   @ > y@  7 6 i +o r  *B tC aD `E 
F ?G wH I J K L vM KN O OW <Q S T V X NY Z Z [   ğ  s F   vIW f   S b 1 <          F  Y C gPW QW RW QW SW +UW VW W 
W W ՟W ĠW UW VW DXW 6WW WYW ZW W GW cW 4W W W A[W [W {]W {\W ^W _W W fW W EW W W T`W taW bW cW bW dW fW ׫W aW W JW .W W fW \gW iW hW "jW OkW W W W sW YW @W 
lW lW \nW TmW ioW pW )W W ѶW W xW [W MqW qW sW rW tW uW @W ּW W ŽW W W vW wW yW dxW zW A|W W wW dW W W W |W }W W v~W W W W W W W W W W pW CW (W cW W W 5W DW /W $W W PW W W W ;W W W W W W W W @W W ݐW W W EW W W W W W W   Ķ M    i 	 u
 '  x 
  I    B! ! ," " ) k)     D      W  ѽ Ҿ ӿ        K    ̈ ^    1      K   >         Y *^ SY Y &Y Y S+^ {Y [ 	a @[ F[ G[ 2H[ H[ I[ {J[ 1K[ K[ L[ aM[ N[ N[ GO[ O[ P[ Q[ tQ[ ْa R[ S[ S[ T[ T[ KU[ U[ [V[ ,W[ X[ Y[ Z[ G\[ ][ ][ _[ T`[ %a[ b[ c[ dd[ f[ f[ g[ 3i[ 1_ 12_ k[ ;m[ m[ 3_ 6_ 6_ 7_ 8_ _9_ t[ Ou[ jv[ Ca ӵa a a w[ Zx[ x[ y[ 3z[ h{[ |[ |[ :_ }[ '~[ ~[ [ T[ [ Á[ [ 2[ Ń[ \[ Z;_ <_ <_ =_ Z>_ ?_ ?_ @_ [ [ \[ [ /[ e[  [ K[ [ [ [ 
\ [ +^ 4` I6` w:` 7^ M>` ?` A` jd Tf Q` V` f f Jd` f` i` uk` n` q` {t` Y `w` x` z` f I^ ۓf ` ` 8d ` 0` )` ` Ɨf ` ` p_ ` ı` ` o^ r^ t^ w^ r_ 3` ` ` ` O^ ^ ` ` ` ;` ` ` 2` ` ` ^ ΅^ ` Rf y^ ^ j` Z` A` ` ` 4^ `  ` ^ ^ ^ ގ^ ^ b^ 8^ ^ ^ ^ Xf ` K` ` ` VZ /WZ WZ }XZ E` H^ %` ` ^ L^ ^ ` w^ 9^ ^ 2` ^ ` ^ ˥^ ^ ` }` ` W` =` -` ` ` O` ` Y` ` _^ ^ ExZ ݭ^ \yZ f o^ ^ @^ [f f ^ Z ̴^ vZ Z ^ =^ &Z Ŷ^ ܷ^ \^ ^ ^ Q
a _ Ha La `a Ca 2f a R^ =a B a !a c#a %a 'a f 0a 3a e8a ;a \?a @a Da _ VGa Ia Na Qa \Sa Ua ^Wa ^ |^ ^ c^ )^ ^ #^  _ Xa I]a _a Pda Sha _ hqa ua wa rya h|a !_ \f (_ d-[ a qa a a ?a ҍa ZA_ B_ B_ C_          ԡ b  r     8 ʦ V    %         T KW 9 LW MW NW NW  ={ dQ | | 
~  H w b t U D f/ `2   ": , X 6  o  Ɏ  1 ڕ Ж J  UK K }M   Q S - t dW US U W ( @( ( 4( ( ( F( ( ( )( ( ( ( ( B( ( (       # >& f) |, / A D rG 05 QP C[ ]\ ] ^ _ 4` a b d e f h i +k l n &o ?p r Ĕ  Y   C    s (t t u Wv w x Kz { V} ~ Y  < w م  A a     g g  Ē  =   . Ƥ æ  D  4 )( H( z( 	( ( ( M ) ) ) . / 1 x4 = &5 fV RV 98 8  y9 D D : e
 [  H _; mK 9< == K c  D> (   IW > y@  7 6 i +o r  *B tC aD `E 
F ?G wH I J K L vM S T V X NY Z Z [   ğ  s F   vIW f   S b 1 <          F  Y C  GV tV V V  W V ;V V iV V V 8V |!W V gV V V V 1V hV "W  V V 5V V V aV V "W 0V V eV V#W $W #W %%W T&W %W &W 'W #(W &  ϶  r  (W V 8V V V e)W |V V V ZV   - e  f V 	 V V "V MV 
*W V pV V V V *V YV *W V V V V V >V mV <+W V V .V V V RV V +W V V BV p,W -W -W 3.W Z/W .W /W 0W 1W :  ߾  ~  1W V 	V mV V W2W EV V V V T   e  $ V  EV zV V V 2W V MV V V V V ^V 3W V V 7V V V kV V :4W FV V V V T W V  W 4W W -W W ~5W 6W 6W Y7W 8W 7W 19W 9W k:W ;W ;W g<W =W =W `>W ?W gW W 
W WW ?W W W EW W '	W W 	W Y@W o
W W W  SW hW W W  AW W W W !W :W W W AW XW W uW W W W W "BW 4W W QW W W eW W BW W W -W FCW _DW CW DW FW }EW FW +GW GW  ( ]   & JHW W W HW uW HW W W 3W W     >  S W   Ķ M    i 	 u
 '  x 
  I    B! ! ," " ) k)     D      W  ѽ Ҿ ӿ        K    ̈ ^    1      K   >                 a a Sa F[ G[ 2H[ a I[ {J[ }Vc K[ L[ aM[ N[ N[ GO[ O[ a Q[ tQ[ [ S[ B[ T[ T[ KU[ U[ ;m[ m[ [  \ m\ )\ \ \ >\ \ La a a a Na a 	\ s
\ 
\ [     LRV SV kUV bV heV uhV fkV PnV [qV KtV wV zV }V V ^V V ƈV V fV *V $V V 'V V ʝV VV _V V `V WV eXV YV V V V {V DV V QV ^V sV V V BV V V V V ]V 8ZV uV V JV V JV V V V wV yV V QV  V !V  V "V #V %V %$V &V &V k'V )V (V *V *V y+V T,V -V -V .V /V 0V 1V 63V 62V H4V 5V 6V 7V 6V 8V x9V o:V 0;V ;V <V O>V P=V `?V +@V @V AV BV DV wCV EV FV -HV +GV AIV JV V \V V V V 
V JV ;KV LV KV MV NV PV OV  V V >V V                         Y Y Y SY Y &Y Y Y _ Yc Vxf _ Wc Ha 9a a %yf c a Xa Ja *a a a a a Wc <Xc Yc "Zc a a Zc s_ _ _ [c \c ]c .zf /(` (` )` *` 
_c [ w[ @[ F[ G[ 2H[ H[ I[ {J[ 1K[ K[ L[ aM[ N[ N[ GO[ O[ P[ Q[ tQ[ [ S[ B[ T[ T[ KU[ U[ ;m[ m[ [  \ m\ )\ \ \ >\ \ o\ 8\ \ \ q\ >	\ 	\ s
\ a a Na  a ˽a a za a _c #`c `c {f k}f 
\ [ ac "Y bc cc fgc }jc kc :mc lnc oc qc rc sc tc evc wc rxc ,yc yc [ |zc |c 
[ I[ 0}c {[ [ \[ [ [ 8[ [ d[ [ [ [ V[ }c [ ?~c ~c lc lc ?c #c c 5c #c [ #c [ b[ [ [ c y[ M[ [ [ [ 2[ [ R[ [ o[ ևc \c V[ c [ J[ [ *c c 9c Ƌc Ic c =c c ~c ֓c !c Vc c xY 
c ͙c ͏a a                     ?8 ?8 aA8 A8 B8 C8 C8 1D8 E8 kF8 
G8 G8 D8 TE8 >H8 H8 HI8 I8 ZJ8 J8 K8 L8 pM8 N8 uO8 P8 JQ8 BR8  S8 S8 T8 V8 Y8 3[8 [8 \8 \8 ,& /-& \8 ^]8 ]8 ^8 +_8 _8 Za8 a8 b8 c8 ;`8 `8 c8 7d8 d8 He8 e8 tf8 f8 h8 h8 i8 j8 k8 l8 m8 |n8 Vo8     #0 0 0 0 0                             v
7 3 3 3 3 3 3 3 3 83 r3 =.8                 6 6 96 j. Ώ. =. 6 -8 a6 ǎ6 *6 6 6             o6 6 6 h6 6 6 i8 8 Z8 6 b6 8 6 @6 6 (6 6 ]8 Տ8 N8  6 n6 א8 6 L6 6 46 6 }8 8 s8 8 i8 8 ]8 ז8 -8 8 _8 6 c6 	8 v8 Q8 ˗8 E8 8 98 8 38 8 6 ?6 6 6 %6 6 %6 6 6 L6 c6 z6 6 6 	6 6  7  7 7 ֝8 8 8 8 8 8 8 8 8 8 7 7 b7 7 n7 7 z7 7 x	7 	7                         Ð6 6 6 v6 .6 6 6 Y6 6 ϖ6 6 !6 6 ;6 ș6 U6 6 {6 6 6 Z6 6 6 p6 "6 נ6 6 A6 6 6 96 פ6 u6 6 6 U6 6 0p8 p8 q8 6 26 ͩ6 h6 6 6 ?6 ݬ6 tr8 {6 6 6 I6 6 6 6 6 Bs8 s8 t8 du8 v8 v8 w8 Ex8 x8 W6 6 6 v6 +6 6 6 S6 6 b6 6 y8 
6 d6 Ĺ6 6 y6 
z8 yz8 6 b6 z8 ٻ6 V{8 {8 -|8 ~|8 |8 D}8 }8 $~8 ~8 ~8 8 ڀ8 \8 8 s8 8 f8 M6 6 6 6 6 G6 ؃8 6 61 6 ?8 K6 6 6 R6 6 6 _6 6 8 6 k6 6 6 o6 6 6 |6 8 r8 +6 6 m6 6 6 S6 6 6 ?6 6 6 6 6 b6 6 6 =8 8 ň8 8 M8 8 ۋ8 8 K6 6 6 6 W6 6 6 6 . }. s~7 ~7 5             5 >7 &7 7 7 #5 5 5 5 5 q5 M5 j7 .5 5 5 5 i5 5 5 5 5 5 5 )5 5 *5 5 25 )5 7 J7 7 ]7 7 5 5 M5 7 5 5 5 5 g5 a5 [5 U5 ȋ7 7 7 7 O5 )5 5 5  6 6 }6 7 k6 7 7 a7 Б7 27 7 7 ^7 7 7 7 7 p6 t6 K7 X6 A6 *7 /6 	6 7 
6 
6 	7 7 l7 d6 7 7 ?7 מ7 c7 7 7 7 7 -7 7 O7 7 q7  7 7  7 7 6 k6 6 6 P6 #6 6 `6 &6 6 , 6 X6 (6 6 6 6 v6 06 6 6 M6 6 6 j6 56 6 6 6 e7 M7 , 7 i 6 *!6 U"6 *#6 a	V 
V +- j$6 (%6 &6 !- &6 $- (6 7 '6 7 !7 -7 7 7 )6 
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8 .-8 V e8 6 8 d6 6 Z8 8 8 8 w8 8 8 !8 8 8 8 8 |8 8 l8 &8 8 8 8 *8 8 '8 8 8 8 	8 8 8 M8 8 8 8 8 8 w8 8 a 8  8 k!8 !8 5"8 "8 #8 6 6 #8 }6 6 j6 #8 W$8 Ո6 $8 F6 9%8 6 %8 "6 Ǌ6 )&8 &8 '8 '8  (8 u(8 (8 e)8 )8 r*8 +8 +8 ,8 96 6 6     T m;	 {	 V NV _ /V sV V V 	 V g V j 7	 ul q 1t u w M
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  pM             Y X5  5 65  ' s5 |U i  U 5 mU U U  	 ;	 	 9	 X	 	 XK L L DM ~	 	 9	 h	 	 	 	 	 0	 [	 	 	 ,d "	 d "	 F#	 $	 A&	 '	 	 	 }W
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                             Y Y Y &Y {Y _ a a _ (_ Ha 9a a c c a Xa Ja *a a a a a 	a a a a a }_ ` J_ _ ` d ` e_ Za Za a a a a e /(` (` )` *` k+` 2B[ C[ AF[ F[ G[ 2H[ H[ I[ {J[ 1K[ K[ L[ aM[ N[ N[ GO[ O[ P[ Q[ tQ[ Q[ R[ S[ S[ T[ T[ KU[ U[ a a a a Ja [V[ a X[ Y[ a G\[ ][ Ba _[ T`[ ia b[ a aa a Ba a <a c[ a f[ f[ 	a 3i[ i[ ?Rc a ;m[ m[ an[ p[ q[ hr[ :s[ t[ t[ Ou[ jv[ w[ Zx[ x[ y[ 3z[ h{[ |[ |[ }[ }[ '~[ ~[ [ T[ [ Á[ [ 2[ Ń[ >_ _ c_ 5a a ca a a Na  a Tc #Uc \[ N[ [ [ [ G[ 	[ [ [ [ \[ [ /[ e[  [ K[ [ [ [ za a s_ _ r_ a a ya .` 0` '1` 2` 2` {3` 
\ [ #4` Ja a a b )b Y Y ?` b c c[f b b Tdf Rc Y Y &b (b n` ,b -b Y :/b Y 1b Y `w` x` z` 3b 8b gf ;b ` >of c ` 0` Db +Ib Lb {Pb Sb uWb Y U Z Zb m\b ]b Y`b fcb fb ib mb qb tb wb |yb {b |b }b ~b ^ ` &Z b ށb ,Z ` pb b Åb 1Z b ΅^ ` fb lb ^ b mb A` rb ` 4^ `  ` ^ "b ^ ^ pb Zb `b `b 8^ ^b ^ ^ ^ b ` wb K` ` 1b VZ /WZ m` =` WZ }XZ E` H^ %` ` ^ L^ ^ ` w^ 9^ b 2` ^ ` Nb ˥^ b b b b b գb פb }` ` ȥb æb b Vb W` =` b ` ` O` b b b xb fb ^ ExZ ݭ^ 3` ` ` sb b b o^ ^ @^ b b z` fqf Ra ^ p` b b Z ^ Z 8b =^ &Z Ŷ^ ܷ^ b b \b b Z -Z b b Q
a b b b )b b b a Yb ?b Z !a b b Yb b 4b b cb 3a e8a b zb b 1b xb b Wb b sf c 	c >Z Ic c c qd d I	d c c c D#c >'c )c ".c 0c 4c j7c 9c o;c wa >=c h|a !_ @c Cc d-[ a fEc Gc Ic 4Lc Oc ҍa ZA_ B_ C_ ͏a la a         ʉ0 H0 E0 % >% % ,% %  % % % B0 9% % %% % #% % % h% % x% % % 
% |% ,0 0 % % z% % 0 0 Ś0 *0 0  0 h0 ֜0 =0 0 0 0 _0 0 0 ª0 ɬ0 Ю0 0 0 0 & Q0 0 {0 Ѷ0 0 Ƹ0 ̹0 0 0 0 0 0 0 C0 0 0 C0 0 7%& %& && && && e'& 0 '& H(& (& $)& )& *& w*& *& ?0 ,& /-& 0 W0 0 -0 0 0 j0 0 80 0 0 20 0 0 a0 $0 0 :0 0 P0 0 50 30 0 J0 `0 S0 F0 90 50 Q& 00                         #0 0 0 0 0 F0 0 <0 0 20 0 B0 0 R0 0 >0 0 H0 0 >0 0 0 1  1 1 W& X& tX& 1                 n3 ( a( 3 y3 3 3 &3 w3 3 3 3 3 3 G3 3 3 63 3 3 3 83 r3 3                              {0 |0 }0 ~0 0 q0 ^0 80 J0 \0 t0 0 0 0         d3 3 3 03 3 	3 3 3 .3 3 {3 3 E3 3 '3 3 3 3 3 [3 3 K3 3 3 {3 3 3 !3 3 "3 ~3 x3 83 3 (3 }3 3 3  3 "!3 !3 "3 9#3 #3 o$3 %3 %3 &3 ('3 (3 }(3 (3 7)3 )3 +3 .3 03 33 [63 593 >3 }D3 F3 yI3 L3 vN3 Q3                     W/ 7/ / / 	/ _
/ 
/ %/ / / / / / {/ 7/ / "/ / / / / / / / / 	/ F/ =/ / u / !/ )#/ M$/ %/ &/ '/ (/ )/ m+/ c,/ Y-/ h./ // 0/ 1/ 3/ 4/ }5/ 6/ +8/ 9/ :/ V</ >/ l?/ @/ B/ C/ D/ EF/ G/ OI/ J/ K/ gM/ N/ O/ Q/ R/ XT/ U/ W/ X/ Y/ 0[/ x\/ ]/ ^/ `/ a/ b/ b/ qc/ {d/ de/ .f/ g/ g/ i/ i/ j/ pk/ Wl/ n/ q/ s/ v/ x/ {/ ~/ / / s/ / / / m/ ٗ/ @/ _/ |/ / / Ξ/ / / 
/ ك/ =/ ʄ/ / / J/ [/ ./ / / / O/ ɍ/ / / / / ֒/ / / / 9/ 0/ / / X/ / ߤ/ / K/ Ħ/ >/ / װ/ Ǳ/ / {/ X/ 5/ / ȸ/ X/ B/ ½/ / / e/ ;/ / / 5/ 
/ / / / u/ N/ +/ / / / / Z/ / / / R/ "/ / / / b/ 5/ / / / / / / / / / \/ 0/ 
/ / / / _/ )/ / / / T/ !/ / / / / / / $ $ / c/ 3/ / / / v 0 I0 0 0 0 0 r0 L0 &0  0 0 
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U0 !Y0 Q]0 ;a0 ie0 f0 !h0 <i0 pj0 ^k0 l0 4m0 m0 |n0  o0 o0 hp0 p0 }q0 r0 r0 s0 t0 u0 s0 t0 u0 v0 zv0 v0 sw0 x0 x0 +y0 y0 ^z0 {0                 -2 K.2 .2 /2 02 F32 52 z82 ;2 =2 N@2 B2 D2 F2 I2 SL2 	O2 Q2 xT2 1W2 W2 AX2 X2 QY2 Y2 gZ2 Z2 }[2 \2 \2 ]2 ]2 )^2 ^2 A_2 _2 \`2 `2 za2 	b2 b2 !c2 c2 9d2 d2 )e2 e2 +f2 f2 ?g2 g2 Vh2 h2 ii2 i2 uj2 j2 k2 l2 l2 m2 m2 +n2 n2 7o2 o2 Kp2 p2 _q2 q2 yr2 s2 s2 t2 t2 1u2 u2 v2 v2 v2 \w2 w2 .x2 x2 y2 }y2 y2 Sz2 z2 /{2 {2 |2 |2 }2 }2 ~2 ~2 -2 2 52 2 :2 2 <2 2 A2 Ń2 ?2 2 32 2 K2 ׆2 Y2 ۇ2 ]2 ߈2 d2 2 k2 2 o2 2 {2 2 2 2 2 2 2 +2 2 ܑ2 2 2 j2 F2 2 2 D2 2 ؚ2 "2 o2 2 2 S2 2 2 2 &2 !2 .. |q! . 6. . C. ץ. ~. M. . m. . . ެ. . . $. . (. .  . . . . . t. V. E. 3. !. . . . . . 	. . . }. . . . . . . . . . . . . . . . . . . . . . . N. . . . . i. . A. . ;. . . . . f. . >. . 8. . . q. . M. . ). . . `. . . t. . V. . 
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2 2 2 2 2 2 w2 2 a2 ӳ2 E2 2 2 2 j2 T2 θ2 H2 ¹2 <2 2 $2 2 2 2 2 2 q2 c2 2 P2 12 2 12 #2 2 2 2 2 L2 2 2 2 2 2 2 e2 2 V2 2 -2 2 2 2 J2 2 2 s2 2 G2 2 2 z2 2 J2 2 
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}1 z~1 f1 1 ك1 1 z1 /1 1 1 1 51 c1 u1 1 Ó1 1 l1 1 ܘ1 !1 Z1 1 Ӝ1 1 A1 1 Ο1 1 1 1 |1 91 1 01 1 1 o1 01 1 1 1 1 ?1 /1 )1 1 ʰ1 1 m1 Z1 Q1 1 01 ϶1 f1 1 1 1 1 61 1 1 1 K1 H1 O1 ,1 1 1  1 1 1 \1 1 1 1 1 1 I1 1 n1 61 1 a1 1 1 )1 1 L1 1 1 61 1 1 ^1 /1 1 1 1 ^1 1 1 1 i1 1  2 2 p2 2 2 V	2 
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, , ., , , +, K, , , , , e, k, ', , , , 0, , , , , k, a, , , _, F, , , , $, , , v, , , , , , {, , , , 
, U- - 3- S- i- - I- 	- 	- 
- "- B- +- - '- - - $- - - $- - - /- - , , - U- : - !- !- "- $- $- %- )- C+- &- e(- /- 1- ,- #.- u2- 
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 !             f 8    %+ &+          ? G   , u	 e
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 e
 [      4 c      :  W   7      % #' ( 	) * D+ y, - . / 3 6 5 ]8 j* b* * U 9 ; 3= > ? A 3B aC UU M # c% ' ( }* 0, - / D1 2 Xi     9! s"   * * * * ]* * œ* m* c* w e* :* * i* * I* * U ;U ؝* * * U ̡* Ο* * * d* * u* * * 4* * * * ,* J* T* *  + * j* * + \* * ھ* s* K+ F+ + + a+ 8U C* * * * Y+ ?+ *U * H* 5+ * gQ * + + 4+   n  [ j F Z* *   * ?*  ͥ F L   q  ^  + + + + +  + z!+ s    X          <"+ #+ $+  e   )  l  '+   	 
 x      C    Z   U   RR         Y *^ SY Y &Y Y S+^ {Y ._ /_ o0_ F[ G[ 2H[ I[ {J[ 1K[ K[ L[ aM[ N[ N[ GO[ O[ P[ Q[ tQ[ [ S[ B[ T[ T[ KU[ U[ ;m[ m[ 3_ 6_ 6_ 7_ 8_ _9_ t[ Ou[ jv[ Ca ^a a >^e ^e p_e y[ z[ h{[ |[ d :_ >\ \ o\ 8\ \ \ q\ >	\ 	\ s
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ce 
\ [ j4^ 7^ :^ >^ I^ (Q^ Tf e ]e %e .d U Z e Oe ?e e z^ ~^ ^ ΅^ }e e e ^ ^ _^ ^ ExZ ݭ^ 5Wf Ҍe o^ ^ @^ ^ ̴^ vZ Z ^ =^ &Z e ܷ^ \^ ^ -e Xf e R^ e Ve e e i^ e 4e _ _ e             ԡ b  r 9 R9 9 ~9      8 9 ʦ V 9 9  9 T9   "9 %                             6J  J J 9   J J 5J                             M M }M 3B M B9 B9 HC9 C9 pD9 D9 xE9 F9 F9 DG9 G9 {H9 nM M 0U M U uU :U U M hM O9 M XP9 `2 P9 Q9 M /R9 6 R9 M M fU U U nU I>9 J ;M aJ M M J ZM ^M M G J M UK $M \M M M M M nM hM M M NP P 3P P P .J DP P tJ M 8 cM M UM J sJ ̴M ,J M M 8 MM MM ܾM nM M 8 eM M hM 9 M vU :9  9 M M a 6M M 7J g M (J j j 'M *J M M M M M M Gc M ^P P sP xJ  P M M 'M M M 9 BM ¥8 = OJ XPJ PJ M 3M  8 8 B8 8 RJ RJ eSJ ژM KM M M yM M <M M XJ +M M cZJ )M a[J M [J B\J M 8 8 K]J 8 y8 8 F8 eM oM Cd U M xM M -M dM M ΞM LM m ;n n +o p M Wt9 |U tU OU 0U U U U U @U J FJ ߟJ yJ M J DJ ܢJ pM U mU UU U YU ŎU eU 8M M DM U -M M \lJ (M 	nJ oJ pJ ߰M }M =M U )uJ U J \vJ vJ xJ wJ yJ U J jU &U U 0U ]U U AU J J J U {U ՙU }U {U }U U CU zU J <U !U UU U J U <|J $U U |J *U U U 
U U U U ~J 8J ?U 5U J GU J )U J YJ OJ aJ U J U U J $U ņJ ӇJ 0U U U J J ȯU jU U 'U YJ KU (U lU U U U J J 'J kJ U rU HU /U _U U U 2U U U U fJ U U ܽU 'U mU )U ( K J PK K SU U U U U :U 9U #J .J ҶM zJ M J U DM U oM YU M ( N  N .N N x9 ^y9 ]N N qN N N N N N M XM 8 J P N \N N 4J EN oJ N [	N 	N  J 
N mJ N J  K   1 N 9 @9  U -N U 9 J     Y Y SY Y &Y Y S+^ Y `d {Y B[ C[ E[ F[ G[ 2H[ H[ I[ {J[ 1K[ K[ L[ aM[ N[ N[ GO[ O[ P[ Q[ tQ[ 3^ R[ S[ S[ T[ T[ KU[ U[ [V[ a X[ Y[ a G\[ ][ Ba _[ T`[ ia b[ a aa a Ba a <a c[ a f[ f[ 	a 3i[ i[ ?Rc a ;m[ m[ an[ p[ q[ hr[ :s[ t[ t[ u[ jv[ w[ Zx[ x[ y[ z[ h{[ |[ |[ }[ }[ '~[ ~[ [ T[ [ Á[ [ 2[ Ń[ \[ N[ [ _d [ ?`d 	[ [ [ [ \[ [ /[ e[  [ K[ [ [ [ 
\ [ +^ bad bd fd Y M>` ?` A` jd od wd {d Rd Єd Jd` f` i` d Dd n` X] {t` Y 1b Y `w` x` z` d Y Md ` ` 8d ` 0` d +Ib 8d {Pb @Y d ad U Z d gd d d ͭd d d mb d wb Xd {b |b }b ~b ^ ` ` yd Ƚd ` ` pb b Åb 1Z b ΅^ ` dd y^ ^ d mb A` bd ` 4^ `  ` d ^ ^ ^ ގ^ ^ b^ ` 8^ ^ ^ ^ d ` 5d K` ` d VZ /WZ WZ }XZ E` H^ %` ` ^ L^ ^ ` w^ 9^ b 2` ^ ` ^ ˥^ b ` b }` ` ȥb W` =` d ` ` O` d b Y` b b ^ ExZ ݭ^ \yZ jd o^ ^ @^ Sf ԀZ ^ Z 6d d d b vZ Z ^ =^ &Z Ŷ^ ܷ^ b b \b 4d Z Q
a _ d d `a Ca d a Z d Z !a b b Yb 4b Zd Z 3a e8a d d d Rd b d VGa d ,d 	c d Ic c >d d d d |d e he 
e >'c 0c e e o;c wa e h|a !_ e Cc d-[ a fEc Gc Ic 4Lc e ҍa ZA_ B_ B_ C_ .                 gY; xU  cyU RzU ]{U Y; G|U ; ; x;  dQ ; ; ; `; ; ;  ; Q!; !; w"; c$; %; %&; &; 2(; !); *; ; #; 9   ) +; 0;   e  U7     1; M p: : : Z; h[; 4( o\; ]; $_; z`; a; Mb; ( Lc; d; f; ig;     0 X   $  * * * :   : $: : ~: Z: B: ): {: 3: : 0: : : : 2: : : E: : : : : W: : /: : : q: : *:   j: ? G :  : a: Q: zT7 : .: 92; = 4; b6; 78; 8; S:; ;; $=; T<; l>; ?; gh; `i; ( M ) ) j; # )  de:   &5 f: g: 	i:  y9 x	 ۈ* e
 [   _; wU JxU c    D> r@;  A; B;  7 D;     j: l: l: m: n: o: p: q: s: `t: u:  w: ?x: y: {: |: ~: : : ': c% ' ( }* 0, - / D1 E; F; ;: : : : : 7: ?: J: : X: 3: #: Ή: : : {: V: 4: : ^: : : ۏ: ;: : x: : ѕ: : : ݖ: : : : Ù:  ; x; ݚ: R; : : : : :  : ; ; : ; Z: P: 1: X: N: G: P; ; : ; ; : : : : ; H; U; 		; Ҭ: 	; >
; f : S b 
; : : ^: : l; : : L  G; FI; G; + + + +  + z!+ 0: : : d: : : [: ) k) J;   ; ; <"+ #+ $+ ; *; F; ; ; L; L; M; N; O; P; vQ; dR; '+   	 
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 3,U [-U R0U n1U v2U 3U 6U T9U ;U =U  >U O?U o@U AU aDU EU oGU JU ^KU LU OU OQU SU TU VU XU YU    
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\ [                     ,T T T WT ƂT -T T T `T  ԄT 7T T 
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S pS OS +S S S xS 3S S S S [S %S S S S uS PS S S S S S zS (S S S 2S S  S :!S !S "S F#S #S $S             Q Q Q R R -R R fR R R xR R R eR R R [R R R R 8R _P  R y!
  R D#R #R uP xQ Q sQ &R 'R S(R nP P LP P (R Q Q +)R P P >S iP P P P 9P lQ )R *R +R r-R B.R P HP Q bQ 9Q P |P P 8P ZP P P P P P Q Q Q P P Q Q Q P 3P P P &P UP P P P P eQ KQ GQ P P -Q Q P P 6P bP eP n Q sQ SQ 3Q Q `Q 6Q Q CQ Q Q ^Q Q /Q |Q 	Q 
Q Q Q Q [Q 6Q Q Q Q Q <Q [Q Q Q Q "Q lQ Q Q Q Q aQ 9Q Q Q pQ (Q Q Q Q Q vQ <Q lQ Q $!Q ^"Q o#Q $Q %Q &Q u'Q c(Q Q Q Q Q)Q *Q Q KQ Q G+Q ,Q -Q 3/Q B0Q W1Q h2Q T3Q @4Q ,5Q Q Q Q 6Q T7Q PQ #Q Q 8Q |9Q :Q ,<Q H=Q j>Q ?Q @Q zAQ sBQ Q Q Q lCQ DQ iQ CQ Q EQ FQ ?HQ hIQ JQ KQ LQ MQ Q Q Q NQ OQ Q nQ .Q PQ QQ =SQ qTQ |UQ VQ WQ XQ jYQ RZQ Q Q Q :[Q r\Q P]Q _Q RQ CQ 5^Q _Q CaQ bQ cQ &eQ dfQ }gQ hQ iQ 7Q 0Q ?Q 8Q jQ 1lQ mQ YQ AQ mQ koQ pQ IrQ |sQ tQ uQ vQ 
xQ yQ ,Q Q "Q *zQ Q Q Q zQ (|Q ~}Q ~Q Q Q ˁQ Q Q wQ KQ %Q [Q Q Q  R cR ?Q Q Q Q Q 'Q 0Q Q "R R Q ,Q R R vR Q nQ Q Q Q 3Q 5Q 7Q 9Q SR 5R -R 	R ;Q 
R 
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\ [ j4^ 7^ :^ >^ I^ (Q^ oe e ]e %e .d U Z e Oe ?e e z^ ~^ ^ ΅^ }e e e ^ ^ _^ ^ ExZ ݭ^ Oe Ҍe o^ ^ @^ M` ` ^ ̴^ |_ Z ^ Z =^ &Z e ܷ^ \^ ^ -e )e e R^ e Ve e e i^ e 4e _ _ e `L g L pL GL L h \i %j j V& ^P _P n`P k aP l jaP 	bP bP IcP cP  q q  O O O 
O aO O O $O 6O HO O O 7O O O $O oO O P \P P P L P P p
P -P P P ^P P P \P P P ZP P vP  P !P &#P $P 'P *P -P 0P 3P 6P D:P =P gAP DP HP 8L 9L :L LP 3OP LRP hUP XP [P     xr dP fP hP jP lP nP ppP rP tP vP +xP ryP zP {P ;}P ~P P P KP P ӄP P #M P ͉P P EP ܍P sP 
P P ƒP P WP 
P                 -O I /O 1O 2O 4O _ c ha e 6O 8O L:O x;O <O =O >O +@O z #{ ZAO FO JO oOO ITO YO ]O bO xgO DlO qO uO zO O ]O 6O : rL uL 3wL [yL {L }L  L ,L L ކL 7L L O O AO ڏO sO O O MO ,9 6 8; גO O ? O GO O ¢O O vO PO O O ǿO O lO JO /O O O  ܖ                   |Z: MP P P cP P ǹP yP +P ߻P wP P P ?P ׾P oP P [: ]: ?`: b: M    P tP P y iP P 9P O v P эM M M hM     O O O >O O ]O 3O O W!O x"O #O \%O _8 6HL I HL IL K JL KL O LL ML uR NL 'O (O (O *O D,O dc Hd 'e e gf *\L                 P 1P P 7P P 9P P IP P  j  q 1P FP _P rP  ) j j j j j m p s v  P -  w   l   P IP ,P [P 3l( T W  P s\ P P ŰP a d                     $N uN  N 'N 	 \
 
 N N z rN N ' ( 1+ ], / / 1 :2 g3 4 N N N N <N N ƞN N `N N N 8N N ʧN N ZN N N >N bN N N N N TN N N N fN ,N N N ~N BN N N N N jN N 2N N N \N N N N N IN N 	N mN N -N N N WN N %N LN N N vN PN (N N WN N N {N N IN N N sN N 6N N N O O O O 2
O cO O                 / k ^N N N N N / g )K HN K*K -N N 9 N N N !N D$N x'N *N -N 1N L4N 7N :N =N $AN AN :BN BN DN EN REN EN K EN FN GN wHN =L L _IN JN JN KN LN MN NN zON Y PPN PN 4QN QN RN RN SN BUN w VN "  XN XN SYN [N ]N _N bN adN fN hN .kN kmN oN qN sN =vN ~xN zN }N `N N N WN N ɈN N ^N (N N N N RN ;N                             M M }M 3B M B9 B9 HC9 C9 pD9 D9 xE9 F9 F9 DG9 G9 {H9 nM M ԫJ M J $J J M hM O9 M XP9 `2 P9 Q9 M /R9 6 R9 M M 7U9 BM M pM I>9 J ;M aJ M M J ZM ^M M G J M UK $M \M M M M M nM hM M M NP P 3P P P .J DP P tJ M 8 cM M UM J sJ ̴M ,J M M 8 MM MM ܾM nM M 8 eM M hM 9 M qM :9  9 M M a 6M M 7J g M (J j j 'M *J M M M M M M Gc M ^P P sP xJ  P M M 'M M M 9 BM ¥8 = OJ XPJ PJ M 3M  8 8 B8 8 RJ RJ eSJ ژM KM M M yM M <M M XJ +M M cZJ )M a[J M [J B\J M 8 8 K]J 8 y8 8 F8 eM oM Cd M M xM M -M dM M ΞM LM m ;n n +o p M Wt9 ֟M M M cM M M vcJ `dJ eJ @M @M J FJ ߟJ yJ M J DJ ܢJ pM ͨM M :M M M 2M M 8M M DM M -M M \lJ (M 	nJ oJ pJ ߰M }M =M \vJ xJ wJ yJ +J >M 'M M J J J J J zJ J J J J J {J ~J ~J 8J ^
K K K K K J J YJ OJ aJ J K XK K K K K J J J YJ gK  J J J 'J kJ ^K LK K K K K fJ K 4J ( K J PK K 4M #J .J ҶM zJ M J DM M oM M M ( N  N .N N x9 ^y9 ]N N qN N N N N N M XM 8 J P N \N N 4J EN oJ N [	N 	N  J 
N mJ N J  K   1 N 9 @9 N -N N 9 J                         Y *^ SY Y &Y Y S+^ {Y ._ /_ o0_ F[ G[ 2H[ H[ I[ {J[ 1K[ K[ L[ aM[ N[ N[ GO[ O[ P[ Q[ tQ[ [ S[ B[ ?_ _ :_ T[ T[ KU[ U[ ;m[ m[ 3_ 6_ 6_ 7_ 8_ _9_ t[ Ou[ jv[ Ca ӵa a ]e ^e p_e y[ z[ h{[ |[ d :_ >\ \ o\ 8\ \ \ q\ >	\ 	\ s
\ >_ _ c_ _ _ G_ _ j_ _ \[ Z;_ `e <_ `e <_ 9ae =_ ae Z>_ obe ?_ 
ce 
\ [ +^ ce D0^ j4^ 7^ :^ >^ X] ӫe I^ *e (Q^ oe U^ X^ !re 5ve _ f^ @j^ .d U Z |e e e ee z^ ~^ "e O^ ^ ^ ΅^ }e ^ z^ 4^ ^ ^ ^ e ^ ^ ^ \^ ^ VZ /WZ }XZ H^ ^ ^ Ǡ^ ^ ^ 3e ^ ˥^ ^ k^ c^ 2d ^ _^ ^ ExZ ݭ^ {_ Ҍe o^ ^ @^ M` ` ^ *e ̴^ |_ Z ^ Z =^ &Z Ŷ^ ܷ^ \^ ^ ^ -e $6d x:d )e e ^ R^ Ee e ^ $^ ?d )^ ,e i^ ^ e ^ |^ ^ c^ )^ ^ pe Od 	_ J_ _ e ve _ e _ _ _ !_ M%_ (_ ɩe         `L g L pL GL L h \i %j j V& k L l m Jn n o ]p  q q             )L L L ]L L ܕL L NL L L vL .L L L _L  L ŝL pL *L L L BL L L UL L L TL L L dL L ȨL fL L ĪL sL %L ׬L L 'L ֮L L 4L L L JL L 0L ޵L L ɸL hL L LL L L L L  L hL L L L L <L `L L L L    
 W    Q L IL L L 5L L yL L eL L PL L 6 9 W= @ 4D G K kO vS W u[ k_ ~c 9g j @n q t cx |     8L 9L :L Ɛ ]  ͛ a  U ԩ     xr ;u w y =L 7| ~  =L {L L L gL L AL L hL  L L L wM M M cM M .	M 
M XM M +M M pM M M M M M M EM _M !M #M S$M %M   Z  ث _   Z J : %M !&M &M 	'M s'M 'M             ]L I ,K M AP R :U W Z 
] _ )^L b^L ^L ^L 0_L x_L _L  `L N`L `L `L $aL faL aL aL ,bL mbL bL bL 4cL ycL cL dL CdL dL dL eL OeL eL eL 'fL ffL fL c ha e g 4/: j kk l n do p r cs t 	v \w x z #{ } Y  ΃ 	 D    0 k  fL  mL         ;    z : rL 7 r uL   3wL ' d [yL   {L  X }L     L L  ,L (
  L  r ކL  N 7L  * L    t" # n% & h( ) h+ , - ./ 0 *2 3 )5 ,9 6 8; < = ? q@ F L Q W ] b Th n s x ~ ; m 7  ܖ   ˚  / < I {   ţ  - L L  L L #    % B h \ P m  ~ r    |Z: \M ]M c^M _M _M `M GaM aM bM lcM #dM dM eM HfM fM gM hM BjM kM lM nM boM pM qM 6sM |tM uM wM NxM yM zM t{M |M |M F}M }M ~~M M M NM M M M M PM [: ]: ?`: b: M    M jM M y eM M M UM M M  4  O v #M эM M M hM                         2L 3L @5L c8L :L <L ?L BAL 5 ^6 CL EL _8 6HL I HL IL K JL KL O LL ML uR NL PL RL 7TL UL WL YL dc Hd 'e e gf *\L                  p     ,  u Y    j  q  &  W  ) j j j j j m p s v G(M   -  w   l   t $	 
 x "    0   (M (M H)M )M *M q*M *M ;+M +M ,M d,M ,M (-M -M -M W.M .M /M /M /M D0M 0M 1M s1M 1M :2M 2M 2M `3M 3M *4M 4M 4M V5M 5M 6M |6M 6M F7M 7M 8M r8M 8M 69M 9M 9M b:M :M ,;M ;M ;M R<M <M =M ~=M =M H>M >M ?M n?M ?M 5@M @M @M T W Y Y cZ Z [ [ s\ ^ dAM a d DM uDM DM 9EM EM  FM eFM FM /GM GM GM UHM HM IM IM IM KJM JM KM qKM KM 8LM LM MM gMM MM +NM NM NM TOM OM PM PM PM GQM QM RM pRM RM :SM SM TM cTM TM 'UM UM UM VVM VM WM WM WM CXM XM YM rYM YM 9ZM ZM ZM _[M [M )\M \M jf         
K   zK *K ܹK K K K xK iK A P _ m \K K  mK K K FK 	 \
 
  K  K sK * aK RK CK 4K 9K z  >K @K BK GK  IK K K OK ' ( 1+ ], . / / 1 :2 g3 4 K WK K 7K K K Y; E< )> ? @ A B C D F _G H hJ L ?M N K K K &K K {K K PK K K K aK 
K K \K K @K K qK K K K K : L L L L dL L 	L 2L L L L y | + w 6 P   p t 
L { J  k  *: &         ~ i U A * L   D     r   UL L  L Y	 	 
 $  c   M !L !L      I  { )  i  c"L "L e#L $L 'L +L .L ' * U. 1 / k |K K c!K f$K &K / g )K > K*K   9   ;  	 p   "+K W.K 1K 4K 28K ;K <?K BK EK gIK LK ePK SK WK @ZK i]K `K ldK gK ukK nK rK uK yK |K K K K K K K K DK K ;K K 8K K /K K @K = ʧK YK K K >K K ȬK K ?K 5I TJ _K =L L yM K K jO P Q T V X Y ] ` xb Rd f g m p Qs w x K "  Z ,K ǴK   5  o  Ș ? ߝ  ̣ F Ũ W ڭ L ܲ l .   ( [ ) 
 B "   
   6  [  \  j $ l   R   0   	 9 {             }J J U8 sA9 B9 B9 HC9 C9 pD9 D9 xE9 F9 F9 DG9 G9 {H9 I9 I9 ԫJ ZJ J wJ $J J MN9 N9 O9 XP9 `2 P9 Q9 /R9 6 R9 S9  J 7U9 J I>9 J W?9 aJ J ܱJ J GJ ĳJ J ]J J \9 UK K ѵJ J 'J J 5P J Q a9 tJ J J V dW nJ J J M zM J 6J KJ BJ cJ 89 .J J J tJ 8 8 18 8 }8 J sJ +J ,J J 8 J )J 8 8 ^8  J 8 8 J *9 9 9 DJ :9  9 9 L9 a J J 7J g (J j j c9 *J J J J iJ Gc J {J CJ J J xJ J ?OJ 9 8 ¥8 = OJ XPJ PJ ^QJ ,RJ 8 B8 8 RJ RJ eSJ SJ tTJ UJ UJ ,VJ VJ 3WJ WJ XJ YJ YJ cZJ ZJ a[J [J B\J \J 8 8 K]J 8 y8 8 F8 J UJ 6J p9 }q9 8 @9 ]J ^J m ;n n +o J J J _J E`J `J aJ J oJ ?J J vcJ `dJ dJ eJ "fJ fJ ggJ J FJ ߟJ yJ J J DJ ܢJ rJ hJ yhJ hJ tiJ jJ jJ 1kJ  9 "J r \s ; < 8 >8 kJ 8 \lJ lJ 	nJ nJ oJ pJ bqJ yrJ  usJ K SK /K xJ wJ yJ +J K J J J J J J J J J J K K p	K kK ~J 8J ^
K K K K K J YJ OJ aJ J K XK K K K K ņJ lK J J YJ gK  J J J 'J kJ ^K LK K K K K fJ K 4J ( K J PK K K #J .J J TJ zJ J LJ x9 ^y9 J z9 J #| J J 8 J J J 4J J oJ J J cJ  J J mJ J J >J  K   1 ̈ ^   J J J 9 J ͓9 DJ @9 J 9 8J 9 J                 Y *^ SY Y &Y Y S+^ {Y ._ /_ o0_ F[ G[ 2H[ H[ I[ {J[ 1K[ K[ L[ aM[ N[ N[ GO[ O[ P[ Q[ tQ[ [ S[ B[ T[ T[ KU[ U[ ;m[ m[ 3_ 6_ 6_ 7_ 8_ _9_ t[ Ou[ jv[ Ca ӵa a ]e ^e p_e y[ z[ h{[ |[ d :_ >\ \ o\ 8\ \ \ q\ >	\ 	\ s
\ \[ Z;_ `e <_ `e <_ 9ae =_ ae Z>_ obe ?_ 
ce 
\ [ +^ ce D0^ j4^ 7^ :^ >^ X] de I^ 0ke (Q^ oe U^ X^ !re 5ve ye f^ @j^ .d U Z |e e e ee z^ ~^ "e O^ ^ ^ ΅^ }e ^ z^ 4^ ^ ^ ^ e ^ ^ ^ \^ ^ VZ /WZ }XZ H^ ^ ^ Ǡ^ ^ ^ 3e ^ ˥^ ^ k^ c^ 2d ^ _^ ^ ExZ ݭ^ P^ Ҍe o^ ^ @^ ^ e ̴^ vZ Z ^ =^ &Z Ŷ^ ܷ^ \^ ^ ^ -e $6d x:d )e e ^ R^ Ee ^ $^ ?d )^ ,e i^ ^ e ^ |^ ^ c^ )^ ^ pe Od 	_ J_ _ _ e _ _ _ !_ M%_ (_ ɩe                 ԡ b  r 9 R9 9 ~9      8 9 ʦ V 9 9  9 T9   "9 %                             6J  J J 9   J J 5J                             }J J U8 sA9 B9 B9 HC9 C9 pD9 D9 xE9 F9 F9 DG9 G9 {H9 I9 I9 ԫJ ZJ J wJ $J J MN9 N9 O9 XP9 `2 P9 Q9 /R9 6 R9 S9  J 7U9 J I>9 J W?9 aJ J ܱJ J GJ ĳJ J ]J J \9 UK K ѵJ J 'J J 5P J Q a9 tJ J J V dW nJ J J J 6J KJ BJ cJ 89 .J J J tJ 8 8 18 8 }8 J sJ +J ,J J 8 J )J 8 8 ^8  J 8 8 J *9 9 9 DJ :9  9 9 L9 a J J 7J g (J j j c9 *J J J J iJ Gc J {J CJ J J xJ J ?OJ 9 8 ¥8 = OJ XPJ PJ ^QJ ,RJ 8 B8 8 RJ RJ eSJ SJ tTJ UJ UJ ,VJ VJ 3WJ WJ XJ YJ YJ cZJ ZJ a[J [J B\J \J 8 8 K]J 8 y8 8 F8 J UJ 6J p9 }q9 8 @9 ]J ^J m ;n n +o J J J _J E`J `J aJ rbJ vcJ `dJ dJ eJ "fJ fJ ggJ J FJ ߟJ yJ J J DJ ܢJ rJ hJ yhJ hJ tiJ jJ jJ 1kJ  9 "J r \s ; < 8 >8 kJ 8 \lJ lJ 	nJ nJ oJ pJ bqJ yrJ  usJ stJ )uJ J \vJ vJ xJ wJ yJ J zJ J {J <|J |J ~J YJ ~J 8J J J J J YJ OJ aJ J J J ņJ ӇJ J #J .J J TJ zJ J oJ LJ x9 ^y9 J z9 J #| J J 8 J J J 4J J oJ J J cJ  J J mJ J J >J  K   1 ̈ ^   J J J 9 J ͓9 DJ @9 J 9 8J 9 J         Y Y Y &Y {Y _ _ (_ Ha 9a a e Xa Ja *a e a a a Wc Yc "Zc a a }_ ` J_ _ ` d ` e_ \c Za a a a a e /(` (` )` *` k+` 2B[ C[ E[ F[ G[ 2H[ H[ I[ {J[ 1K[ K[ L[ aM[ N[ N[ GO[ O[ P[ Q[ tQ[ 3^ R[ S[ S[ a ia 3a T[ T[ KU[ U[ a a a a Ja [V[ a X[ Y[ a G\[ ][ Ba _[ T`[ ia b[ a aa a Ba a <a c[ a f[ f[ 	a 3i[ i[ ?Rc a ;m[ m[ an[ p[ q[ hr[ :s[ t[ t[ Ou[ jv[ w[ Zx[ x[ y[ z[ h{[ |[ |[ }[ }[ '~[ ~[ [ T[ [ Á[ [ 2[ Ń[ >_ _ c_ 5a a ca a a Na  a e Tc #Uc \[ N[ [ _d [ ?`d 	[ [ [ [ \[ [ /[ e[  [ K[ [ [ [ za a s_ _ r_ a a ya .` 0` '1` 2` 2` {3` 
\ [ #4` +^ bad bd fd Y M>` ?` A` D`  e wd {d )e d-e Jd` f` i` d Dd n` X] {t` Y 1b Y `w` x` z` 2e Y E` 7e ` ` ` ` 0` d +Ib }<e {Pb @Y d ad U Z d gd d d ͭd d d mb d wb Xd {b |b }b ~b ^ ` ` '@e lBe ` ` pb b Åb 1Z b ΅^ ` dd y^ ^ d mb A` bd ` 4^ `  ` ^ ^ ^ ގ^ ^ b^ ` 8^ ^ ^ ^ d ` 5d K` ` d VZ /WZ m` =` WZ }XZ E` H^ %` ` ^ ^ ` _d 9^ b 2` ^ ` ^ ˥^ b ` b }` ` ȥb W` =` d ` ` O` b Y` b b ^ ExZ ݭ^ 3` ` ` jd b De o^ ^ @^ Fe b qHe Ie Ra ^ p` 6d d d b 	a Z ^ Z =^ &Z Ŷ^ ܷ^ b b \b 4d Z Q
a _ d d aKe Ca BNe a Z d Z !a b b Yb Re 4b Z 3a e8a d d d Rd b d VGa d ,d 	c d Ic c >d d d d |d e he 
e >'c Te Ye 0c e [e o;c wa e h|a !_ e Cc d-[ a fEc Gc Ic 4Lc e ҍa ZA_ Y B_ C_ ͏a la a             YE H0 E0 % >% % ,% %  % % % B0 9% % %% % #% % % h% % x% % % 
% |% ,0 0 % % z% % 0 0 0 0 _0 0 E E E E GE E E _E E  E E CE 0 ª0 ɬ0 Ю0 E 0 0 EE Q0 xE {0 iE 0 Ƹ0 ̹0 0 0 0 0 0 0 C0 0 0 C0 0 7%& %& && && && e'& 0 '& H(& (& $)& )& *& w*& *& ?0 ,& /-& 80 0 0 20 VE خE E WE E E ~E !E vE E E E 0 E |E 0 P0 0 50 30 0 J0 `0 S0 F0 90 50 Q& 00     3& #0 0 0 0 0 gE F0 0 <0 0 20 0 B0 0 R0 0 >0 0 H0 0 >0 0 0 1  1 1 W& X& tX& 1         VGJ ( a( 3 y3 3 3 &3 w3 3 3 3 3 3 G3 3 HJ 3 63 JJ KJ MJ 83 r3 3                          >C AC DC GC JC PC VC \C bC hC kC nC rC vC zC ~C C  C !C "C #C $C %C &C 'C (C )C *C +C ,C -C .C /C 0C 1C 2C 3C 4C 5C 6C 7C 9C :C ;C <C =C >C ?C  @C &AC ,BC 2CC 8DC >EC AFC DGC HHC LIC PJC TKC [LC bMC iNC pOC wPC {QC RC SC TC UC VC WC XC YC ZC [C \C ]C ^C _C `C aC bC cC dC eC fC gC W/ 7/ / / hC # 
/ %/ rjC kC lC "nC oC pC 'rC sC / / tC RxC {C ZC 
C C C C ނC iC C C C C C C C [C / / / {/ 7/ / "/ / C AC / / / / / / C C 	C C +C 6C mC qC C C ]C ؽC sC C iC C qC C vC C / 	/ F/ =/ / u / !/ )#/ M$/ %/ &/ '/ (/ )/ m+/ c,/ Y-/ h./ // 0/ 1/ 3/ 4/ }5/ 6/ +8/ 9/ :/ V</ >/ l?/ @/ B/ C/ D/ EF/ G/ OI/ J/ K/ gM/ N/ O/ Q/ R/ XT/ U/ W/ X/ Y/ 0[/ x\/ ]/ ^/ `/ a/ b/ b/ qc/ {d/ de/ .f/ g/ g/ i/ i/ j/ pk/ Wl/ n/ q/ s/ v/ x/ {/ XC C C C C C C ~/ / / s/ / / / m/ ٗ/ @/ _/ |/ / / Ξ/ / / 
/ ك/ =/ ʄ/ / / J/ [/ ./ / / / O/ ɍ/ / / / / ֒/ / / / 9/ 0/ / / X/ / ߤ/ / K/ Ħ/ >/ / װ/ Ǳ/ / {/ X/ C C {C C [C C C C TC C 4C C C C xC C KC {C D %D D KD 
D D ND D D mD 5/ / ȸ/ X/ B/ ½/ / / e/ ;/ / / 5/ 
/ / / / u/ N/ +/ / / / / Z/ / / / D D {D "D D !D &#D 
$D $D %D ]&D 5'D (D (D )D l*D 1,D -D /D $1D 2D 4D J6D 7D 9D 	;D 8<D R=D o>D l?D @D AD BD CD DD 'FD GGD jHD mID JD KD LD ND OD \PD QD RD =TD UD VD 'XD uYD ZD \D V]D ^D _D =aD bD cD $eD ofD gD iD SjD kD lD =nD oD pD rD isD tD vD SwD xD yD :{D |D }D "D oD D D YD D D R/ "/ / / / b/ 5/ / / / / / / / / \/ 0/ 
/ / / / _/ )/ / / / T/ !/ / / / / / / $ $ / c/ 3/ / / / v 0 I0 0 0 0 0 r0 L0 &0  0 0 
0 i0 30 0 0 0 a0 -0 0 '0 0 0 0 0 0 0 0 "0 0 *0 0 CD aD iD tD D D D D ÐD ʑD D D ؔD ܕD D ʗD ED D D ZD ȞD CD D D XD D RD ǨD D D D D D [D ²D D gD D D \D D D 5D 6D "D D D D D D D D D 6D D D D {D D D QD D KD D D D D jD gD gD dD dD WD MD @D 6D )D D D 
D D D D pD D D D {D ]D -D D D D SD 9E E E E E g
E E E 'E E E ;E E E E rE TE 9E E  E E E E [!E #E $E *&E 'E )E M+E -E .E $0E 1E 2E A4E 5E 6E G8E 9E ;E 60 0 0  0 !0 "0 #0 O$0 X%0 ]&0 a'0 m(0 u)0 |*0 c+0 c<E ?E ZCE FE OXE [E F_E bE IJE ME PQE TE 5fE iE (mE pE tE HvE yxE {E E E ,0 00 40 80 =0 A0 3E0 F0 G0 I0 :J0 (K0 ZL0 P0 
U0 !Y0 Q]0 ;a0 ie0 f0 !h0 <i0 pj0 ^k0 l0 4m0 m0 |n0  o0 o0 hp0 p0 }q0 r0 r0 s0 t0 u0 s0 t0 u0 v0 zv0 v0 sw0 x0 x0 +y0 y0 ^z0 E                         YG PG GG >G 5G /G )G #G G G G G G G G G G G G G G G G G G G G G G G G zG qG hG `G XG PG HG CG >G 9G 4G /G 'G G G G G G G G G G G G G G G G G G G  H H H H H yH pH gH ^H X	H R
H LH FH @H 7H .H &H H H H 	H H H H H H H K.2 ]H |H H H @ H y!H "H $$H .2 /2 Y%H (H F,H /H 5AH DH HH KH 93H 6H 4:H =H OH RH UH rYH \H _H 02 F32 52 z82 ;2 =2 N@2 B2 D2 F2 I2 SL2 	O2 Q2 xT2 1W2 W2 AX2 X2 QY2 Y2 gZ2 Z2 }[2 \2 \2 ]2 ]2 )^2 ^2 A_2 _2 \`2 NaH aH 	b2 b2 !c2 c2 9d2 d2 )e2 e2 +f2 f2 ?g2 g2 Vh2 h2 ii2 i2 uj2 j2 k2 l2 l2 m2 m2 +n2 n2 7o2 o2 Kp2 p2 _q2 q2 yr2 s2 s2 t2 t2 1u2 lbH cH u2 v2 v2 v2 \w2 w2 .x2 x2 y2 }y2 y2 Sz2 z2 /{2 {2 |2 |2 }2 }2 ~2 ~2 -2 2 52 2 :2 2 <2 2 A2 Ń2 ?2 2 32 2 K2 ׆2 Y2 ۇ2 ]2 ߈2 d2 2 k2 2 o2 2 {2 2 2 2 2 2 2 cH dH eH fH gH hH iH jH kH /mH mH nH nH oH zoH oH jpH pH WqH qH +2 2 ܑ2 2 2 j2 F2 2 2 D2 2 ؚ2 "2 o2 2 2 !rH sH fuH wH xH FzH {H |H |}H B~H ~H H H OH H H tH H H CH H H EH H mH H H H "H H *H MH [H lH ]H H H H H šH H H H H OH H ͩH H NH H ҮH H SH H ѳH H RH H ָH H WH H սH H VH H H H [H H H H ZH H H  H bH H H $H eH H H +H lH H H S2 2 2H >H MH YH hH tH 2 2 H qH bH PH AH /H &2 !2  H H [H H H :H H H H H H H H  I  I I I I I I I I 	I t
I I I nI I 6I I I JI I I bI I MI I I e I !I #I M$I u%I &I (I c)I *I +I ,I -I .I N/I 70I ,1I 2I 2I 3I 5I P6I 7I 8I :I e;I <I =I ?I @I AI BCI DI *FI GI HI II JI KI LI MI wNI ^OI HPI /QI RI  SI SI TI VI aXI "ZI [I {]I H_I `I bI dI sfI 2hI iI kI gmI =oI pI rI tI YvI wI yI zI |I Q~I I I =I I I I I qI JI I I I uI I I  I ՒI I I ٗI I ҚI &I wI ˞I I pI I I UI I I I I 1I I I }I [I ԷI JI I I VI I -I I I I \I I GI         0R@ 1S@ 2T@ 3U@ 4V@ 8W@ <X@ @Y@ DZ@ H[@ I\@ J]@ L^@ N_@ P`@ Ra@ Wb@ \c@ ad@ fe@ kf@ mg@ oh@ pi@ qj@ rk@ sl@ wm@ {n@ o@ p@ q@ r@ s@ t@ u@ v@ w@ x@ y@ z@ {@ |@ }@ ~@ @ @ @ @ @ @ @ @ Ƈ@ ǈ@ ȉ@ ʊ@ ̋@ Ό@ Ѝ@ Վ@ ڏ@ ߐ@ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ 	@ @ @ @ @ @ @ #@ (@ *@ ,@ @ @ x@ @ |q! @@ ԭ@ K@ ֮@ l@ ݯ@ @ @ @  @ |@ @ h@ ޳@ T@ ޴@ j@ @ @  @ ~@ @ z@ @ j@ @ Z@ @ :@ g@ @ @ _@ @ @ ]@ @ @ *@ A@ @ B@ @ m@ @ j@ @ I@ @ X@ @ m@ @ l@ @ q A A A yA A ~A A A A A c	A 	A h
A 
A iA A rA MA A HA A SA A fA A _A A JA A TA A >A A JA A WA CA A .A A 8A A "A A .A A ;A 'A A 'A A (A A 2 A  A U!A !A T"A "A #A #A L$A $A (%A %A %A p&A &A X'A 'A K(A (A 9)A )A *A *A *A a+A +A B,A ,A -A -A -A J.A .A </A /A .0A 0A &1A 1A 22A 2A 3A 4A ^5A .6A 6A 7A :8A 8A H9A 9A P:A :A V;A ;A M<A <A I=A =A H>A >A S?A ?A Y@A @A VAA AA NBA BA JCA CA XDA DA `EA EA fFA FA ]GA GA YHA HA CIA IA %JA JA 
KA ~KA KA zLA LA _MA MA ?NA NA NA OOA OA PA PA PA QA RA dRA RA SA TA UA WA XA AYA CZA t[A \A )]A ]A ;^A ^A -_A _A 1`A `A 2aA aA bA bA cA cA dA dA eA eA fA ! ! fA `! fA _gA ! ! t! ! gA riA kA lA pnA pA qA rA fsA 6tA tA uA vA kwA ;xA xA zA [|A ~A A ^A A A gA A tA A A ԌA ύA A A 5A PA KA ~A A A A A A 6A WA XA ǝA 6A A A ZA A 
A bA A A =A A ҦA A jA A A HA A گA &A rA A 
A SA A A .A zA ƼA A ^A A A 9A A A A fA A A GA A A )A tA A A XA A A <A GA RA kA A " " A 2A A A iA A 7A A A xA A NA K#" "" #" $" k$" $" 5%" %" A :A A A &A A A A A rA A JA A "A A A A A {A A XA A iA A LA A (A A aA A A A A ,A A A A sA A qA A A A A 
A A A A A ~A A A ,A A nA A /A 5 B >B ZB `B iB B B B mB x	B 
B B B |B B XB B B pB B LB B B ~B B aB B -!B "B #$B %B &B N(B )B *B !,B y-B .B -0B 1B 2B 3B 4B 5B T6B G7B F8B 09B :B :B N<B =B >B @B uAB BB 'DB xEB FB ,HB IB JB kLB MB aOB PB QB RB SB TB UB VB |WB pXB aYB UZB F[B <\B 2]B _B `B bB ,dB fB gB iB }kB KmB 1oB pB rB itB MvB -xB yB {B }B qB B B +B B B 9B B B B hB HB +B B B B B B AB B B 
B ɜB B 'B B B B VB B B jB ȫB B mB ˯B %B B B B B |B B kB B B B B B XB B CB B B B B B B B pB B &B B $B B "B B  B B   C  C C C C bC C BC C &C C C C C cC C mC C {C 	C 	C 
C u
C 
C [C C >C C :C C :C C                             'A@ B@ v. C@ FD@ K! ! E@ J! ! ! t ! . . . . . :. Ώ. =. . <. ͑. ^. %. . ߔ. . . . E@ 5F@ F@ G@ G@ H@ H@ H@ ]I@ I@ .! /! 0! 1! 2! k. Ϙ. -. . . L. . UJ@ NL@ ?! NN@ @! NA! A! A! SB! B! C! XC! C! D! P@ I. Q. Y. V. . Ƞ. vI                         I qI 9I I I I I 1I I I I =Z: I I RI I I I @ J  J  J J J 
J gJ J `J &J J J J DJ J J J J nJ ( ( J 	J 
J \J ( Q( )J rJ J uJ BJ J u3 v3 z3 5}3 X3 {3 3 h3 3 3 J J J J J J &J rJ J J J J =J 3 3 $3 ף3 d!J 3 M3 !J ;"J 3 -3 "J "J 3 
3 ^#J ˩3 ;3 3 3 >3 3 3 #J j$J %J h3 3 %J *&J 3 y( y( _3 έ3 >3 3 3 p3 ʯ3 =3 3 !3 3 3 T3 &J 3 3 .'J 3 f3 ʹ3 >3 3 x3 3 p3 Ϸ3 'J F(J (J (3 3 ])J )J ۸3 53 3 o*J *J +J 3 L3 ,J ,J 3 3 U3 5-J -J D.J 3 3 .J N/J X( ( ( X( ( ( r( Ɉ( /J 60J 0J $1J 1J 2J 3J 5J _9J b3 A3  3 3 =J ?J 2BJ DJ                             1 /1 1 1 61 1 1 =1 E                             E E XE @E E E E hE E E OE E bE .E \E E E E E HE yE E )E E ~E 	E E BE E E ZE E dE E E ;E E n F DF F }F F ~F 	F F CF F jF :F F gF F _F F F F F < F 	"F #F 0%F &F N(F )F +F -F P/F 0F 2F 4F g6F 8F 9F :F <F I>F ?F nAF =CF DF hFF GF IF 8KF 5MF NF PF nRF nTF #VF WF YF S[F \F ^F `F qbF  dF fF gF iF VkF lF @nF pF qF 1sF tF vF xF yF 0{F |F V1 X1 &Z1 [1 ]1 z_1 a1 b1 Z~F F 2F F mF F F FF F _F ڍF CF F lF F yF F F )F ěF <F F ȟF eF F ,F ~F F sF F @F F F F GF F ԵF ׷F F jF "F ȾF nF kF F F F F YF 1F 1 1 51 c1 u1 1 Ó1 1 l1 1 ܘ1 !1 Z1 1 Ӝ1 F 1 A1 1 F F F F WF F F 1 01 F TF %F 'F )F F F F 1 1 1 1 ?1 /1 )1 1 ʰ1 1 m1 Z1 tF F F F F F F F ]F 0F F YF 1 01 ϶1 f1 1 1 1 1 F 1 1 F F F F IF rF F F F F F \1 1 1 1 F EF F AF G G MG G G <	G 
G yG G oG AG G rG G G XG G G G yG E!G "G j$G %G 'G >)G *G i,G -G M/G 1G 2G 54G 5G 7G  9G :G %<G =G ?G @G dBG 
DG EG ^GG HG JG LG MG NG PG FRG SG iUG 7WG XG `ZG [G ]G -_G )aG bG dG _fG ^hG jG kG mG 1 1 ^1 /1 1 1 1 ^1 ?oG pG /rG sG uG )wG xG zG |G }G 7G πG 1 1 1 i1 1  2 2 p2 gG ΃G 5G G fG G oG 0G G ?G G G }G 8G G ;G G iG ܝG rG G .G wG G lG G 9G ܪG 4G G G G _G bG G G G G nG LG G G <2 <!2 "2 $2 ~&2 (2 9*2 ,2     t; ; ; G; ; ; ; ; f; `; Z; T; N; K; H; E; B; ?; 9; 3; .; ); $; ; ; ; ;  < < < < < < < < < < 	< 
< < < < < < < < < < < < < < < < < < < < < <  < !< "< }#< x$< s%< n&< i'< g(< e)< c*< a+< _,< Z-< U.< O/< I0< C1< =2< :3< 74< 45< 16< .7< (8< "9< :< ;< << =< >< 
?< @< A< B< B<  (+ *+ `,+ C< X .+ 1+ x4+ j7+ V:+ ?=+ "@+ C+ F+ I+ `D< MF< H< I< 2K< L+ jL+ L+ M+ cM+ M+ N+ YN+ N+ O+ UO+ "M< O+ DN< O< P< 'R< {S< T< P+ Q+ 0 V< GW< W< X< 	Z< @[< \< ]< W+ X+ Y+ Z+ [+ ^< Fb< e< <i< z< 8~< < *< l< 9p< s< =w< < < < < < < /f \+ < ]+ ^+ _+ `+ < 4< < < < < < < ƪ< Q< < b< < Q< < < < < 1< ҽ< < ~+ < a< < < < < {< < /< < < < -< < "< )< < < < K< < !< < 8< m< < + < y+ <  <  = = G= = = 
= T= F= = = = Z+ = = = + = + = = = U+ = '+ + +  3+ |+ &= = + + + + + /+ `= = `= = c= = m =  = != "= "= #= #=  $= $= -%= %= .&= &= 0'= ?(= '= (= P)= )= c*= *= o+= += n,= ,= q-= -= m.= b+ + H+ .= @0= 1= , J, , J, , s, , , -, , , 2= 3, , 3= 75= 6= c8= g
, , , 8, 9= ;= 3== >= W@= A= GC= D= E= F= H= 7I= tJ= K= L= M= N= O= P= Q= R= T= GU= U= +V= V= /W= W= X= X= Y= Y= Z= , , , , Z, 4, 
, , , , , s, M, 6 , !, ", ", h#, #, $, W%, R&, 5', ', (, ), j*, D+, ,, -, -, ., Z/, 90, 0, 1,  (2, 3, 3, K5, 7, 8, :, @<, >, ?, A, OC, E, F, H, @J, L, M, O, EQ, R, yT, U, ZZ= V, W, dX, Y, Z, (\, [], ^, _, a, Qb, dc, d, e, f, g, Ni, j, k, xl, am, In, #o, o, p, q, r, 9s, t, t, u, v, w, w, ax, y, z, {, |, }, ~, , 6, &, ;, , B, ., _, x, [, w, , , , ̎, , ,  , ,  , , ", , :, Q, 1, G, ^, t, |, , , , Ƣ, , , , , , , ͩ, )[= \= t^= `= a= ]c= d= e= f= eg= h= h= i= ~j= Gk= k= m= Ro= p= r= @t= u= w= 4y= z= 3|= Y}= j~= ~= r= = = Ã= ׄ= ˅= = = (= "= B= n= = = = W= = , , , = p= = = , , , , , }, i, t= , 	, ,  , ,  , , , ϔ= = 9= k= = Κ= <= ~= = = D= = Ϋ= = X= = ܰ= = `= = = /= t= = = := |= = = K= = = = V= = = "= g= = = 3= u= =  = D= = = = Z= = = 
= 1= = := ]= = = {= , = != = = k, P= = D= = E= = ^= k, = Z= = = #= = Z= = [> > ?> > > > 	> j> > > > > > 1> > Y> > > > %>  > h"> #> %> &> _(> <*> +> ,> .> 0> 22> 4> , 5> 6> n7> %8> 8> 9> :> a;> 7<> <> => M?> @> yB> G> mI> D> E> 6K> L> L> M> dN> )O>  P> P> Q> pR> V> X> HS> U> Z> \> ]> 8_> `> b> Nd> e> [g> m> Qo> h> bj> l> p> lr> s> !u> I- v> x> M- y> {> t|> }> $> > > W- > > > H> > > > s> :> > g- G> ڔ> ^> ė> u> '> ~> ޝ> > <> w> ֣> N> Ŧ> > 0> > ߪ> 
> 7> k> > ǰ> g> > > .> P> r> > P> > - r- > - ]> > ;> > "- 7> > W> > > > > - I- g> > > S> > )- - > > ~> > > Ŷ- (> S- - - > c> !> - - > }> .> > - - - {- n- ;- - - > 3- - - P> !> > > > > ]> - 9> > > T- 3- - r- :> > > > > u> S> - - - - 1 ? ? ? (? ? ? 
? . =	. . . 
. p. ,. Z.  ? ? {. . e. . ? . p? ? ". ? =? ? (. @? ? S-. y? "? ? 8 ? b>. !? "? /$? %? (? )? &+? &? ,? D.? /? 0? 2? P3? 4? 5? 7? 8? >:? ;? <? =? >? ?? @? A? B? C? D? E? F? G? H? I? J? L? `M? N? O? cQ? R? 1T? U? V? NX? Y? #[? o\? ]? `_? `? 5b? c? d? 'f? rg? h? i? Lk? l? m? 
o? p? p? q? r? }s? ut? Xu? >v? w? ax? y? z? |? l}? ~? ? Z? ?  ? l? ? *? ? ? ^? R? I? =? 4? ? ? ? ? ̔? ? ? ? ? W? ? ԝ? _? 3? ? ? ? [? :? ? ɭ? ]? :? ? Դ? ? ? ;? ӻ? v? ? ? B? ? ? 7? ? ? ? ? z? V? ? ? ? ? *? ? A? ? ? I? ? ? ? \? ? ? [? ? ? I? ? ? g? ? H? @ 
@ |@ @ ? 1? ? "@ Y@ @ :@ @ "@ ?$@ g&@ )@ \-@ 0@ `. a. b. nd. I4@ 5@ 7@ 9@ f. g. Ki. j. :@ W<@ =@ ?@ l. um. ]n. Fo. 1p. p.     ; ; x;  dQ ; ; ; `; ; ;  ; Q!; !; w"; c$; %; %&; &; ; !); *; ; #; 9 k; m; [o; q; r; s; vu;   ) +; 0;   e      1; M p: : : Z; h[; 4( o\; ]; $_; z`; a; Mb; ( Lc; d; f; ig;     0 X   $  * * * :   : $: : ~: Z: B: ): {: 3: : 0: : : : 2: : : E: /: : : q: : *:   j: ? G :  a: Q: zT7 : .: 92; = 4; b6; 78; 8; ;; $=; T<; l>; ?; gh; `i; ( M ) ) j; # )  de:   &5 bw; g: 	i:  y9 x	 e
 [   _; c    D> r@;  A; W   7 D;     j: l: l: m: n: o: p: q: x; y; z; u: g{;  w: |; }; {P ~; u; ?x: y: {: |: ~: : : ': R; c% ' ( }* 0, - / D1 E; F; ;: @; $; ; ; ; ; ; /; b; 3: ; ; ; u; ; ; ; ; s; ; D; 3; ; n; G; !; ; ; t; ; d; ; ; ; ; ; 4; ; ; ; T; ; ; [; l; g; ; c; ; ; ; ; ; ; }; ; ; m; h; x; S; ; U; ʧ; 	; ; u; ; ; ; i; @; ; ; ޮ; ; D; ; ; C; ; X; ; z; U; Ѹ; w; $; ; f : ; S b 
; : : ^: : l; _; : ; ; L  G; FI; G; + + + +  + z!+ 0: : : d: : : [: ) k) J;   ; ; <"+ #+ $+ L; L; M; N; O; P; vQ; dR;   	 
 x     C  aS; 'T; FU; U W; nX;                     Y Y SY Y &Y Y S+^ Y `d {Y B[ D[ E[ F[ G[ 2H[ H[ I[ {J[ 1K[ K[ L[ aM[ N[ N[ GO[ O[ P[ Q[ tQ[ 3^ R[ S[ S[ T[ T[ KU[ U[ [V[ a X[ Y[ a G\[ ][ Ba _[ T`[ ia b[ a aa a Ba a <a c[ a f[ f[ 	a 3i[ i[ ?Rc a ;m[ m[ an[ p[ q[ hr[ :s[ t[ t[ u[ jv[ w[ Zx[ x[ y[ 3z[ h{[ |[ |[ }[ }[ '~[ ~[ [ T[ [ Á[ [ 2[ Ń[ \[ N[ [ _d [ ?`d 	[ [ [ [ \[ [ /[ e[  [ K[ [ [ [ 
\ [ +^ bad bd fd Y M>` ?` A` jd od wd {d Rd Єd Jd` f` i` d Dd n` X] {t` Y 1b Y `w` x` z` d Y Md ` ` 8d ` 0` d +Ib 8d {Pb @Y d ad U Z d gd d d ͭd d d mb d wb Xd {b |b }b ~b ^ ` ` yd Ƚd ` ` pb b Åb 1Z b ΅^ ` dd y^ ^ d mb A` bd ` 4^ `  ` d ^ ^ ^ ގ^ ^ b^ ` 8^ ^ ^ ^ d ` 5d K` ` d VZ /WZ WZ }XZ E` H^ %` ` ^ ^ ` _d 9^ b 2` ^ ` ^ ˥^ b ` b }` ` ȥb W` =` d ` ` O` d b Y` b b ^ ExZ ݭ^ \yZ jd o^ ^ @^ ^ Z 6d d d b vZ Z ^ =^ &Z Ŷ^ ܷ^ b b \b 4d Z Q
a _ d d `a Ca d a Z d Z !a b b Yb 4b Zd Z 3a e8a d d d Rd b d VGa d ,d 	c d Ic c >d d d d |d e he 
e >'c 0c e e o;c wa e h|a !_ e Cc d-[ a fEc Gc Ic 4Lc e ҍa ZA_ B_ B_ C_ .     gY; Y;                 ; ; x;  dQ ; ; ; `; ; ;  ; Q!; !; w"; c$; %; %&; &; 2(; !); *; ; #; 9   ) +; 0;   e  U7     1; M p: : : Z; h[; 4( o\; ]; $_; z`; a; Mb; ( Lc; d; f; ig;     0 X   $  * * * :   : $: : ~: Z: B: ): {: 3: : 0: : : : 2: : : E: : : : : W: : /: : : q: : *:   j: ? G :  : a: Q: zT7 : .: 92; = 4; b6; 78; 8; S:; ;; $=; T<; l>; ?; gh; `i; ( M ) ) j; # )  de:   &5 f: g: 	i:  y9 x	 ۈ* e
 [   _; 9j: j: c    D> r@;  A; B;  7 D;     j: l: l: m: n: o: p: q: s: `t: u:  w: ?x: y: {: |: ~: : : ': c% ' ( }* 0, - / D1 E; F; ;: : : : : 7: ?: J: : X: 3: #: Ή: : : {: V: 4: : ^: : : ۏ: ;: : x: : ѕ: : : ݖ: : : : Ù:  ; x; ݚ: R; : : : : :  : ; ; : ; Z: P: 1: X: N: G: P; ; : ; ; : : : : ; H; U; 		; Ҭ: 	; >
; f : S b 
; : : ^: : l; : : L  G; FI; G; + + + +  + z!+ 0: : : d: : : [: ) k) J;   ; ; <"+ #+ $+ ; *; F; ; ; L; L; M; N; O; P; vQ; dR; '+   	 
 x     C  aS; 'T; FU; U W; nX;     Y *^ SY Y &Y Y S+^ {Y _ _ (_ _ >_ _ ]d _ _ }_ s_ J_ _ _ _ e_ %_ w_ _ _ j_ _ ._ /_ o0_ F[ G[ 2H[ H[ I[ {J[ 1K[ K[ L[ aM[ N[ N[ GO[ O[ P[ Q[ tQ[ 1_ [ S[ B[ ?_ _ :_ T[ T[ KU[ U[ ;m[ m[ 3_ 6_ 6_ 7_ 8_ _9_ t[ Ou[ jv[ w[ Zx[ x[ y[ 3z[ h{[ |[ d :_ >\ \ o\ 8\ \ \ q\ >	\ 	\ s
\ >_ _ c_ _ _ G_ _ _ j_ _ \[ Z;_ <_ <_ =_ Z>_ ?_ ?_ @_ s_ _ r_ _ q_ _ _ ^d _ q_ 
\ [ _ +^ .^ D0^ j4^ 7^ :^ >^ X] _ I^ _ d d U^ X^ H d \$d _ +d @j^ .d z^ ~^ ^ O^ ^ ^ ΅^ .1d z^ 4^ ^ ^ ^ ^ ^ ^ \^ ^ VZ /WZ }XZ H^ ^ ^ Ǡ^ ^ ^ h^ ^ ˥^ ^ k^ c^ 2d _^ ^ ExZ ݭ^ {_ o^ ^ @^ M` ` ^ p` ̴^ |_ Z ^ Z =^ &Z ܷ^ \^ ^ ^ (4d $6d x:d <d ` ^ R^ ^ 
` ^ $^ ?d )^ 
Dd i^ ^ B^ ^ |^ ^ c^ )^ ^ #^  _ Id Od Rd gWd [d ` ` _ )_ _ _ _ !_ M%_ (_ ZA_ B_ B_ C_ `         Y: g h \i %j j k bl l m Jn n o ]p  q q | ƭ 	  +1: 4:   8: e;: . >: 3B: 1 E: H: N _L: O: Q 2S: V: @  L  s   	 u  M  -      X  <   ?  	  j   W !    s Q $     c   Y     V -    ! s" c# S$ C%     M  ú  ?   u :   b    K    \   +      1   A   C   Y   [   Z 	  j     z  A  t  H    B     [   Q    T 4     
 W    Q    ~ P   ! `# % & ( + P, J* * V. / , - / 0 p1 Q2 23 3 ,4 4 &5 5 6 9 W= @ 4D G K kO vS W u[ k_ ~c 9g j @n q t cx |     Ɛ ]  ͛ a  U ԩ                     xr s &t t t ;u w y 7| ~  f  &  ى M  a 4 q  t     |  /   F    Z  ث  a y   ڰ   _   Z J : *     s                     .: I ,K M AP R :U W Z 
] _ c ha e g 4/: j kk l n do p r cs t 	v \w x z #{ } Y  ΃ 	 D    0 k           ;    z : 7 r   ' d    X     L  (
   r  N  *    t" # n% & h( ) h+ , - ./ 0 *2 3 )5 ,9 6 8; < = ? q@ F L Q W ] b Th n s x ~ ; m 7  ܖ   ˚  / < I {   ţ  -  #    % B h \ P m  ~ r                |Z:  T 
  v ,   N   n # ص  B   a   * û \   '  Y   !  Q   [: ]: ?`: b:    9  y      M z  4  O v  d: .          5 ^6 _8 8 i9 : : R; ; < == = > ? u@ 	A A oB AC -D D nE &F F G 8H H I jJ K L M O $P LQ uR S T <U U $V V W W 	X Y [ ] a +: dc Hd 'e e gf     & '      p     ,  u Y  =Z:   j  q  &  W  ) j j j j j m p s v    -  w   l   t $	 
 x "    0   n  v       "  &  *  .  2   2  n  j  x         ! ! " " "# # N$ $ % R& & Z' ' V( ( d) ) r* * + , , - - 
. . / / :0 0 1 >2 2 F3 3 O4 4 ]5 5 k6 6 t7 7 x8 8 |9 9 : ; ; V< = = >> > :? ? H@ @ VA A dB B hC C lD D pE E tF G G tH "I I *J J 3K K AL L OM M XN N \O O `P P dQ Q R :S S T W Y Y cZ Z [ [ s\ ^ a d f Mg g Ih h Wi i ej j sk k wl l {m m n o o -p p q 1r r 9s s Bt t Pu u ^v v gw w kx x oy y sz z { I| | } 1~ ~ -  ;  I Ё W ق [ ݃ _  c  g   g     &  4  B ɍ K ͎ O я S Ր W ّ  - ٓ        -  ;  ?  C ś G ɜ K   K     
    &  /  3  7  ;  g   jf               A P _ m {   	 \
 
   * z   ~  l  T  ;   (  K  >  f   } 8   3    K! ! K" " L# 	$ $ `% & & +' ' ( * 1+ ], - . / / 1 :2 g3 4 5 6 i6 6 c7 7 S8 8 M9 Y; E< -= )> ? ? @ A B C D F _G H hJ L ?M N O -Q R :T rU V Y Z `\ ] _ ` Ac d f g h Aj k .o r v y | + w   Æ h  C U   ܎ Ï  # yE P   s< ? ':   { J  k  *: &    k D        ~ i U A *      k   j   e    D     r   Y	 	 
 $  c   M      I  { )  i        $ ' * U. 1                           H !   w I    X F 1     / k @ "      /   %  > 9     9   ;  	 p   9 9 9 A9 9 9 $9 9 , 9  : / f: : 
: 3 B: : 06 : _: U< < 7= = : : :  : ": O#: #: $: }G H 5I TJ `K =L L yM $N N jO P Q S T V X Y Z \ ] ` xb Rd e f g j k l m p Qs u w x f{ 9} ,~  "  Z  \ 2     5 `$: o  Ș ? ߝ  ̣ F Ũ W ڭ L ܲ l .   R9 ( [ ) 
 B "   
   6  [  \  j $ l   R   0   	 9 Z {                 @9 8 U8 sA9 B9 B9 HC9 C9 pD9 D9 xE9 F9 F9 DG9 G9 {H9 I9 I9 ;J9 K9 K9 *L9 L9 M9 MN9 N9 O9 XP9 `2 P9 Q9 /R9 6 R9 S9 9T9 7U9 U9 I>9 >9 W?9 = V9 > x? W9 Y9 F Z9 J \9 UK c]9 0^9 5_9 _9 a9 a9 b9 8 9 9 f9 C9 M9 W9 m9 
9 /9 K9 89 9 n 9 Ϯ9 ޯ9 а9 r9 s9 k9 \9 8 8 18 8 }8 9 d9 9 9 K9 9 9 $9 8 8 b8 8 8 8 ^8 8 8 8 y 9 *9 9 9 ^9 :9  9 9 L9 a d	9 9 b9 ]9 09 89 9 c9 [d9 Be9 g9 h9 yi9 ]k9 Gc Դ9 9 Z9 .9 շ9 |9 89 ӹ9 9 9 8 9 8 ¥8 = ?8 8  8 8 B8 8 fB 8 v8 8 ī8 M8 լ8 a8 ݭ8 8 58 F8 $8 8 a8 8 8 U8 8 8 8 o8 8 y8 8 F8 ( l9 o9 p9 }q9 8 @9 /8 8 m ;n cr9 +o r9 ~s9 9 Wt9 8 8 8 8 8 !9 &9 	9 8 8 8 8 8 8 8 \9 J9 79 %9 9 9 9 9 (8 8 8 l8 ?8 8 8  9 }!9 }u9 ]v9 !8 8 8 >8 8 8 8 8 z8 {8 8 z8 8 18 #8 C ? | 9 ] M  9 9 9 f  k ; w9 V9 79    > 8 > /9 9 9 9 9 9 9 t9 9 9   9 b 9 9 9 9 9 A9  D <9 9   Iw9 8 8 i9 "9 ս9 9 9 @9 9 9 B9 9 9 G9 9 9 a9 C9 x9 x9 ^y9 y9 z9 {9 #| 19 ?29 29 39 Q49 49 59 )69 8 9 9  69 j79 89 D 89 t99 +:9 ;9 ;9 <9 =9 '}9 }9 +~9 ~9 /9 9 99 9 C9 !9 ނ9 9 X9 9 ˅9 9 59 n9 &9 9  9 r e9  9  ׍9  9  O9 - 9  ǐ9 9 9 ͓9 9 @9 9 9 p9 9 +9                         Y *^ SY Y &Y Y S+^ {Y ._ /_ o0_ F[ G[ 2H[ H[ I[ {J[ 1K[ K[ L[ aM[ N[ N[ GO[ O[ P[ Q[ tQ[ 1_ [ S[ B[ T[ T[ KU[ U[ ;m[ m[ 3_ 6_ 6_ 7_ 8_ _9_ t[ Ou[ jv[ w[ Zx[ x[ y[ z[ h{[ |[ d :_ >\ \ o\ 8\ \ \ q\ >	\ 	\ s
\ \[ Z;_ <_ <_ =_ Z>_ ?_ ?_ @_ 
\ [ +^ .^ D0^ j4^ 7^ :^ >^ X] C^ I^ L^ d d U^ X^ H d \$d 'd +d @j^ .d z^ ~^ ^ O^ ^ ^ ΅^ .1d z^ 4^ ^ ^ ^ ^ ^ ^ \^ ^ VZ /WZ }XZ H^ ^ ^ Ǡ^ ^ ^ h^ ^ ˥^ ^ k^ c^ 2d _^ ^ ExZ ݭ^ P^ o^ ^ @^ ^ Z ̴^ vZ Z ^ =^ &Z ܷ^ \^ ^ ^ (4d $6d x:d <d ^ ^ R^ ^ ^ $^ ?d )^ 
Dd i^ ^ B^ ^ |^ ^ c^ )^ ^ #^  _ Id Od Rd gWd [d _ )_ _ _ _ !_ M%_ (_ ZA_ B_ B_ C_                          ԡ b  r 9 R9 9 ~9      8 9 ʦ V 9 9  9 T9   "9 %             9 T  9 ]                          @9 8 U8 sA9 B9 B9 HC9 C9 pD9 D9 xE9 F9 F9 DG9 G9 {H9 I9 I9 ;J9 K9 K9 *L9 L9 M9 MN9 N9 O9 XP9 `2 P9 Q9 /R9 6 R9 S9 9T9 7U9 U9 I>9 >9 W?9 = V9 > x? W9 Y9 F Z9 J \9 UK c]9 0^9 5_9 _9 a9 a9 b9 8 9 9 f9 C9 M9 W9 m9 
9 /9 K9 89 9 n 9 Ϯ9 ޯ9 а9 r9 s9 k9 \9 8 8 18 8 }8 9 d9 9 9 K9 9 9 $9 8 8 b8 8 8 8 ^8 8 8 8 y 9 *9 9 9 ^9 :9  9 9 L9 a d	9 9 b9 ]9 09 89 9 c9 [d9 Be9 g9 h9 yi9 ]k9 Gc Դ9 9 Z9 .9 շ9 |9 89 ӹ9 9 9 8 9 8 ¥8 = ?8 8  8 8 B8 8 fB 8 v8 8 ī8 M8 լ8 a8 ݭ8 8 58 F8 $8 8 a8 8 8 U8 8 8 8 o8 8 y8 8 F8 ( l9 o9 p9 }q9 8 @9 /8 8 m ;n cr9 +o r9 ~s9 9 Wt9 8 8 8 8 8 8 8 8 8 8 8 8 \9 J9 79 %9 9 9 9 9 (8 8 8 l8 ?8 8 8  9 }!9 }u9 ]v9 !8 8 8 >8 8 8 8 8 z8 {8 8 z8 8 18 #8 C e8 A"9 "9 8 r8 #9 z$9 s8 8 O%9 %9 V8 &9 8 8 !'9 '9 8 8 (9 >)9 	8 8 *9 *9 8 
8 z+9 (,9 8 ,9 8 -9 8 .9 V8 :/9 8 /9 8 09 Iw9 8 8 i9 "9 ս9 9 9 @9 9 9 B9 9 9 G9 9 9 a9 C9 x9 x9 ^y9 y9 z9 {9 #| 19 ?29 29 39 Q49 49 59 )69 8 9 9  69 j79 89 D 89 t99 +:9 ;9 ;9 <9 =9 '}9 }9 +~9 ~9 /9 9 99 9 C9 !9 ނ9 9 X9 9 ˅9 9 59 n9 &9 9  9 r e9  9  ׍9  9  O9 - 9  ǐ9 9 9 ͓9 9 @9 9 9 p9 9 +9 Y Y Y &Y {Y _ Yc (c _ (_ 9a a c c a Xa Ja *a a a a a Wc <Xc Yc "Zc a }_ ` J_ _ ` d ` e_ Za Za a a a a /(` (` )` *` k+` 2B[ C[ E[ F[ G[ 2H[ H[ I[ {J[ 1K[ K[ L[ aM[ N[ N[ GO[ O[ P[ Q[ tQ[ Q[ R[ S[ S[ T[ T[ KU[ U[ [V[ a X[ Y[ a G\[ ][ Ba _[ T`[ ia b[ a aa a Ba a <a c[ a f[ f[ 	a 3i[ i[ ?Rc a ;m[ m[ an[ p[ q[ hr[ :s[ t[ t[ u[ jv[ w[ Zx[ x[ y[ z[ h{[ |[ |[ }[ }[ '~[ ~[ [ T[ [ Á[ [ 2[ Ń[ a a Na  a Tc #Uc \[ N[ [ [ [ G[ 	[ [ [ [ \[ [ /[ e[  [ K[ [ [ [ za a _c #`c `c a ya .` 0` '1` 
\ [ #4` Ja a a b )b Y Y ?` b c Oc b b c Rc Y Y &b (b n` ,b -b X] :/b c <c Ѹc c [c c c 8c c 8b Zc c ` n@b c ` 0` Bc c Lb {Pb Sb uWb Y U Z Zb m\b ]b Y`b fcb fb ib mb qb tb wb Nc c |yb {b |b }b ~b ^ ` &Z b ށb ,Z ` pb b Åb 1Z b ΅^ ` c lb ^ b mb Uc A` c ` 4^ `  ` "c ^ "b fc ^ ^ pb Zb `b `b 8^ ^b ^ ^ ^ c ` wb K` ` 1b VZ /WZ m` =` WZ }XZ E` H^ %` ` ^ L^ ^ ` w^ 9^ b 2` ^ ` Nb ˥^ b b b b b գb פb }` ` ȥb æb b Vb W` Xc =` b c ` ` O` b b b xb fb ^ ExZ ݭ^ c c c bc b b o^ ^ @^ b z` ^ p` b b Z ^ Z 8b =^ &Z Ŷ^ ܷ^ b b \b b Z -Z b b Q
a b b b c b c a Yb ?b ] !a b b Yb oc c b cb c e8a b zb b 1b xb b Wb b Sc c 	c >Z Ic c c qd d I	d c d c D#c >'c rd d .d 0c 4c j7c 9c d d >=c h|a !_ @c Cc ^ a fEc Gc Ic 4Lc Oc ҍa ZA_ B_ C_ ͏a la a                 ?8 ?8 aA8 A8 B8 C8 C8 1D8 E8 kF8 
G8 G8 D8 TE8 >H8 H8 HI8 I8 ZJ8 J8 K8 L8 pM8 N8 uO8 P8 JQ8 BR8  S8 S8 T8 V8 Y8 3[8 [8 \8 \8 ,& /-& \8 ^]8 ]8 ^8 +_8 _8 Za8 a8 b8 c8 ;`8 `8 c8 7d8 d8 He8 e8 tf8 f8 h8 h8 i8 j8 k8 l8 m8 |n8 Vo8     #0 0 0 0 0                             v
7 3 3 3 3 3 3 3 3 83 r3                     =.8 .8 .8 t/8 /8 ^08 08 K18 18 28 +38 38 t48 58 58 58 j68 68 U78 78 )88 88 88 P98 98 :8 :8 :8 X;8 ;8 7<8 <8 =8 p=8 =8 8>8 >8             6 6 96 j. Ώ. =. 6 -8 a6 ǎ6 *6 6 6             o6 6 6 h6 6 6 i8 8 Z8 6 b6 8 6 @6 6 (6 6 ]8 Տ8 N8  6 n6 א8 6 L6 6 46 6 Q8 ܑ8 g8 8 }8 8 s8 8 i8 8 ]8 ז8 -8 8 _8 6 c6 	8 v8 Q8 ˗8 E8 8 98 8 38 8 6 ?6 6 6 %6 6 %6 6 6 L6 c6 z6 6 6 	6 6  7  7 7 ֝8 8 8 8 8 8 8 8 8 8 7 7 b7 7 n7 7 z7 7 x	7 	7         Ð6 6 6 v6 .6 6 6 Y6 6 ϖ6 6 !6 6 ;6 ș6 U6 6 {6 6 6 Z6 6 6 p6 "6 נ6 6 A6 6 6 96 פ6 u6 6 6 U6 6 0p8 p8 q8 6 26 ͩ6 h6 6 6 ?6 ݬ6 tr8 {6 6 6 I6 6 6 6 6 Bs8 s8 t8 du8 v8 v8 w8 Ex8 x8 W6 6 6 v6 +6 6 6 S6 6 b6 6 y8 
6 d6 Ĺ6 6 y6 
z8 yz8 6 b6 z8 ٻ6 V{8 {8 -|8 ~|8 |8 D}8 }8 $~8 ~8 ~8 8 ڀ8 \8 8 s8 8 f8 M6 6 6 6 6 G6 ؃8 6 61 6 ?8 K6 6 6 R6 6 6 _6 6 8 6 k6 6 6 o6 6 6 |6 8 r8 +6 6 m6 6 6 S6 6 6 ?6 6 6 6 6 b6 6 6 =8 8 ň8 8 M8 8 ۋ8 8 K6 6 6 6 W6 6 6 6 . }. s~7 ~7 5             5 >7 &7 7 7 #5 5 5 5 5 q5 M5 j7 .5 5 5 5 i5 5 5 5 5 5 5 )5 5 *5 5 25 )5 7 J7 7 ]7 7 5 5 M5 7 5 5 5 5 g5 a5 [5 U5 ȋ7 7 7 7 O5 )5 5 5  6 6 }6 7 k6 7 7 a7 Б7 27 7 7 ^7 7 7 7 7 p6 t6 K7 X6 A6 *7 /6 	6 7 
6 
6 	7 7 l7 d6 7 7 ?7 מ7 c7 7 7 7 7 -7 7 O7 7 q7  7 7  7 7 6 k6 6 P6 67 w7 7 `6 &6 6 , 7 7 ĩ7 (6 6 6 6 v6 06 6 6 M6 6 6 j6 56 6 6 6 e7 M7 ,  7 7 7 ԰7 7 7 7 7 +- d7 V7 ~7 7 7 7 ǻ7 7 7 7 7 ֭7 j$6 (%6 &6 !- &6 $- (6 7 '6 7 !7 -7 7 7 )6 
4- *6 +6 7- \,6 :7 :7 Y-6 .6 06 7 .6 /6 '7 {16 626 26 m36 46 46 56 [66 66 76 M86 86 {96 :6 :6 ;6 <6 g=6 >6 y7 7 >6 7 >7 ?6 o@6 =A6 UB6 C6 C6 7 7 D6 E6 E6 tF6 G6 G6 7 ]7  H6 7 7 P7 7 7 @7 7 7 ,7 7 o7 7 7 ^7 7 7 I7 7 |H6 /I6 J6 jK6 7 7 :7 M6 N6 O6 - 7 7 7 R6 R6 S6 T6 U6 V6 sW6 )X6 X6 Y6 Z6 b[6 C\6 ]6 ]6 ^6 b7 `7 - I7 - 7 7 7 7 7 
7 - 7 7 7 7 =7 E7 :7 i7 7 |7 7 7 a6 eb6 Zc6 U- Od6 o- mf6 7 Ke6 7 @7 b7 7 7 g6 O- ah6 Li6 . 4j6 7  8 2k6 	l6 n6 w8 l6 m6 r8 o6 p6 Oq6 r6 r6 s6 =t6 t6 u6 Jv6 !w6 w6 y6 y6 z6 t{6 u|6 Q}6 8 8 5~6 y8 8 c6 8 8 A6 "6 ԁ6 x6 '6 σ6 b6 	8 
8 .-8 ,8 e8 6 8 d6 6 Z8 8 8 8 w8 8 8 !8 8 8 8 8 |8 8 l8 &8 8 8 8 *8 8 '8 8 8 8 	8 8 8 M8 8 8 8 8 8 w8 8 a 8  8 k!8 !8 5"8 "8 #8 6 6 #8 }6 6 j6 #8 W$8 Ո6 $8 F6 9%8 6 %8 "6 Ǌ6 )&8 &8 '8 '8  (8 u(8 (8 e)8 )8 r*8 +8 +8 ,8 96 6 6     T 17 W Y  H K F  \\ e^ "_ `  b {c f 1h fi o h7 3r j7 
s l7 t @o7 v Yx q7 s7 { %v7 | `x7        ) &    e  U7     M , 7  )/ / 2 3 L5 6 8 9 9 ]< = ? @ A &+  ͨ     0 -  I   "  X   $  * * * O    * X* * k* * * J* B27 "37 B47 57 67 77 6L7 87 J:7 <7 =7 V?7 +A7 7C7 D7 F7 H7 sJ7 [M7 !N7 N7 O7 %+ &+          ? G   , u	 	 P7   zT7    " е  z7  A  ; &'+ U    M   a  /  bD [E H }I J <L  # )      ?     7 g  L x	 ۈ* 
 e
 [    7   4 c      :  W   7      % #' ( [7 o7 7 7 7 y, - . A7 7 -7 5 7 87 7 7 7 9 ; 3= > 7 A 7 aC 9 7 M dV7 7X7 Z7 [7 ]7 {_7 Ka7 c7 d7 f7 2 Xi     9! s"   * * * * ]* * w !7 e* :* * i* * I* "7 * ؝* * $7 * ̡* Ο* * a%7 d* * u* * '7 * )7 j* * *7 + \* s* K+ F+ + ,7 + a+ C* * * * .7 Y+ ?+ * H* * gQ 4+ 3	 n 4	 [ j F 07 Q5	   a !	 ?*  ͥ C9	 F L   q B]
 + + + + +  + z!+ s    X   !{7       <"+ #+ $+ 
 e   )  l  '+   	 
 x     C    Z   
  RR                     Y Y Y SY Y &Y Y Y _ _ Wc Ha 9a a a a Wc <Xc Yc "Zc a a Zc s_ _ _ [c \c ]c 
_c [ w[ @[ F[ G[ 2H[ H[ I[ {J[ 1K[ K[ L[ aM[ N[ N[ GO[ O[ P[ Q[ tQ[ [ S[ B[ T[ T[ KU[ U[ ;m[ m[ [  \ m\ )\ \ \ >\ \ o\ 8\ \ \ q\ >	\ 	\ s
\ ˽a a _c #`c `c 
\ [ ac "Y bc cc fgc }jc kc :mc lnc oc qc rc sc tc evc wc rxc ,yc yc [ |zc |c 
[ I[ 0}c {[ [ \[ [ [ 8[ [ d[ [ [ [ V[ }c [ ?~c ~c lc lc ?c #c c 5c #c [ #c [ b[ [ [ c y[ M[ [ [ [ 2[ [ R[ [ o[ ևc \c V[ c [ J[ [ *c c 9c Ƌc Ic c =c c ~c ֓c !c Vc c xY 
c ͙c ͏a 0 v
7             6 6 96 j. Ώ. =. 6 a6 ǎ6 *6 6 6                 o6 6 6 h6 6 6 6 b6 6 @6 6 (6 6  6 n6 6 L6 6 46 6 Q6 6 I6 6 A6 6 76 6 6 6 E6 6 c6 6 D6 -6 6 #6 6 6 6 6 6 6 ?6 6 6 %6 6 %6 6 6 L6 c6 z6 6 6 	6 6  7  7 7 7 7 7 7 7 7 7 7 7 7 b7 7 n7 7 z7 7 x	7 	7 Ð6 6 6 v6 .6 6 6 Y6 6 ϖ6 6 !6 6 ;6 ș6 U6 6 {6 6 6 Z6 6 6 p6 "6 נ6 6 A6 6 6 96 פ6 u6 6 6 U6 6 6 26 ͩ6 h6 6 6 ?6 ݬ6 {6 6 6 I6 6 6 6 6 W6 6 6 v6 +6 6 6 S6 6 b6 6 
6 d6 Ĺ6 6 y6 6 b6 ٻ6 M6 6 6 6 6 G6 6 	6 6 K6 6 6 R6 6 6 _6 6 6 k6 6 6 o6 6 6 |6 +6 6 m6 6 6 S6 6 6 ?6 6 6 6 6 b6 6 6 K6 6 6 6 W6 6 6 6     5 5                 5 #5 5 5 5 5 q5 M5 .5 5 5 5 i5 5 5 5 5 5 5 )5 5 *5 5 25 )5 5 5 M5 5 5 5 5 g5 a5 [5 U5 O5 )5 5 5  6 6 }6 k6 p6 t6 X6 A6 /6 	6 
6 
6 d6 6 k6 6 6 P6 #6 6 `6 &6 6 6 X6 (6 6 6 6 v6 06 6 6 M6 6 6 j6 56 6 6 6 i 6 *!6 U"6 *#6 j$6 (%6 &6 &6 (6 '6 )6 *6 +6 \,6 Y-6 .6 06 .6 /6 {16 626 26 m36 46 46 56 [66 66 76 M86 86 {96 :6 :6 ;6 <6 g=6 >6 >6 ?6 o@6 =A6 UB6 C6 C6 D6 E6 E6 tF6 G6 G6  H6 |H6 /I6 I6 J6 jK6 SL6 M6 M6 N6 O6 aP6 4Q6 R6 R6 S6 T6 U6 V6 sW6 )X6 X6 Y6 Z6 b[6 C\6 ]6 ]6 ^6 _6 `6 a6 eb6 Zc6 Od6 mf6 Ke6 g6 ah6 Li6 4j6 2k6 	l6 n6 l6 m6 o6 p6 Oq6 r6 r6 s6 =t6 t6 u6 Jv6 !w6 w6 y6 y6 z6 t{6 u|6 Q}6 5~6 c6 A6 "6 ԁ6 x6 '6 σ6 b6             6 d6 6 6 6 }6 6 j6 Ո6 F6 6 "6 Ǌ6 96 6 6 T m;	 {	 Z ] _ Ta e b d 	 Bf g h j 7	 ul q 1t u w M
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\ [     h4 4 h4 4 4 p4 A4 `4 G4 4 4 4 d4 4 4 4 -5 S4 4 5 4 4 5 4 4 y4 ]4 4 5 C5 5 5 {5 5 L5 5 5 h5 4 3 5 4 4 4 4 m4 V4 5 4 w5 4 4 4 4 K5 5 5 85 3 4 4 p4 4 !4 93 3 ת5 J5 5 05 ׬5 5 3 3 g3 3 3 3 3 3 3 3 4 4 4 3 4 d4 4 4 4 S4 4 5 5 	5 5 x5 A5 5 I5 M5 :5 "5 5 5 5  5 C"5 #5 %5 &5 (5 *5 Y,5 -5 /5 15 35 Q55 65 t85 D:5 <5 =5 s?5 A5 C5 E5 G5 I5 K5 7N5 yP5 .R5 S5 U5 W5 xY5 w[5  ]5 t_5 a5 c5 5f5 +h5 j5 Vm5 o5 q5 As5 tu5 w5 y5 y{5 |5 5 ,5 75 5 y5 5 5 5 5 5 K5 j5 5 N5 5 5 5 5 4 4 '4 N5 s5 4                 a a Sa F[ G[ 2H[ a I[ {J[ }Vc K[ L[ aM[ N[ N[ GO[ O[ a Q[ tQ[ [ S[ B[ T[ T[ KU[ U[ ;m[ m[ [  \ m\ )\ \ \ >\ \ La a a a Na a 	\ s
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4 '4 4 4 L4 4 4 4 4 x4 p4 "4 4 !4 "4 %4 #4 '4 )4 %+4 .4 ,4 04 24 ~44 64 94 74 +<4 P>4 @4 A4 ED4 F4 H4 SJ4 M4 K4 O4 Q4 S4 U4 Y4 aW4 )\4 p^4 `4 b4 lg4 d4 #j4 l4 n4 cp4 t4 %r4 v4 Ly4 {4 x}4 N4 4 4 4 C4 4 Ј4 >4 X4 ؐ4 4 _4 4 ՘4 j4 4 4 24 	4 g4  5 5 5 4 4 '4 4 4 4                             Y Y Y &Y {Y _ a a _ (_ Ha 9a a a Xa Ja *a a a a a 	a a a a a }_ ` J_ _ ` d ` e_ Za Za a a a a k+` B[ D[ E[ F[ G[ 2H[ H[ I[ {J[ 1K[ K[ L[ aM[ N[ N[ GO[ O[ P[ Q[ tQ[ Q[ R[ S[ S[ T[ T[ KU[ U[ a a a a Ja [V[ a X[ Y[ a G\[ ][ Ba _[ T`[ ia b[ a aa a Ba a <a c[ a f[ f[ 	a 3i[ i[ ?Rc a ;m[ m[ an[ p[ q[ hr[ :s[ t[ t[ u[ jv[ w[ Zx[ x[ y[ z[ h{[ |[ |[ }[ }[ '~[ ~[ [ T[ [ Á[ [ 2[ Ń[ >_ _ c_ 5a a ca a a Na  a Tc #Uc \[ N[ [ [ [ G[ 	[ [ [ [ \[ [ /[ e[  [ K[ [ [ [ za a s_ _ r_ a a ya .` 0` '1` cY Y #4` Ja a a b )b Y Y ?` b Vb b b b Y !b Y Y &b (b n` ,b -b X] :/b Y 1b Y `w` x` z` 3b 8b ;b ` n@b Bb ` 0` Db +Ib Lb {Pb Sb uWb Y U Z Zb m\b ]b Y`b fcb fb ib mb qb tb wb |yb {b |b }b ~b ^ ` &Z b ށb ,Z ` pb b Åb 1Z b ΅^ ` fb lb ^ b mb A` rb ` 4^ `  ` ^ "b ^ ^ pb Zb `b `b 8^ ^b ^ ^ ^ b ` wb K` ` 1b VZ /WZ m` =` WZ }XZ E` H^ %` ` ^ L^ ^ ` w^ 9^ b 2` ^ ` Nb ˥^ b b b b b գb פb }` ` ȥb æb b Vb W` =` b ` ` O` b b b xb fb ^ ExZ ݭ^ 3` ` ` sb b b o^ ^ @^ b b z` Ra ^ p` b b Z ^ Z 8b =^ &Z Ŷ^ ܷ^ b b \b b Z -Z b b Q
a b b b )b b b a Yb ?b Z !a b b Yb b 4b b cb 3a e8a b zb b 1b xb b Wb b Sc c 	c >Z Ic c c c c c c c c D#c >'c )c ".c 0c 4c j7c 9c o;c wa >=c h|a !_ @c Cc d-[ a fEc Gc Ic 4Lc Oc ҍa ZA_ B_ C_ ͏a a                             ʉ0 H0 E0 % >% % ,% %  % % % B0 9% % %% % #% % % h% % x% % % 
% |% ,0 0 % % z% % 0 0 Ś0 *0 0  0 h0 ֜0 =0 0 0 0 _0 0 0 ª0 ɬ0 Ю0 0 0 0 & Q0 0 {0 Ѷ0 0 Ƹ0 ̹0 0 0 0 0 0 0 C0 0 0 C0 0 7%& %& && && && e'& 0 '& H(& (& $)& )& *& w*& *& ?0 ,& /-& 0 W0 0 -0 0 0 j0 0 80 0 0 20 0 0 a0 $0 0 :0 0 P0 0 50 30 0 J0 `0 S0 F0 90 50 Q& 00                         #0 0 0 0 0 F0 0 <0 0 20 0 B0 0 R0 0 >0 0 H0 0 >0 0 0 1  1 1 W& X& tX& 1                 n3 ( a( 3 y3 3 3 &3 w3 3 3 3 3 3 G3 3 3 63 3 3 3 83 r3 3                              {0 |0 }0 ~0 0 q0 ^0 80 J0 \0 t0 0 0 0         d3 3 3 03 3 	3 3 3 .3 3 {3 3 E3 3 '3 3 3 3 3 [3 3 K3 3 3 {3 3 3 !3 3 "3 ~3 x3 83 3 (3 }3 3 3  3 "!3 !3 "3 9#3 #3 o$3 %3 %3 &3 ('3 (3 }(3 (3 7)3 )3 +3 .3 03 33 [63 593 >3 }D3 F3 yI3 L3 vN3 Q3                     W/ 7/ / / 	/ _
/ 
/ %/ / / / / / {/ 7/ / "/ / / / / / / / / 	/ F/ =/ / u / !/ )#/ M$/ %/ &/ '/ (/ )/ m+/ c,/ Y-/ h./ // 0/ 1/ 3/ 4/ }5/ 6/ +8/ 9/ :/ V</ >/ l?/ @/ B/ C/ D/ EF/ G/ OI/ J/ K/ gM/ N/ O/ Q/ R/ XT/ U/ W/ X/ Y/ 0[/ x\/ ]/ ^/ `/ a/ b/ b/ qc/ {d/ de/ .f/ g/ g/ i/ i/ j/ pk/ Wl/ n/ q/ s/ v/ x/ {/ ~/ / / s/ / / / m/ ٗ/ @/ _/ |/ / / Ξ/ / / 
/ ك/ =/ ʄ/ / / J/ [/ ./ / / / O/ ɍ/ / / / / ֒/ / / / 9/ 0/ / / X/ / ߤ/ / K/ Ħ/ >/ / װ/ Ǳ/ / {/ X/ 5/ / ȸ/ X/ B/ ½/ / / e/ ;/ / / 5/ 
/ / / / u/ N/ +/ / / / / Z/ / / / R/ "/ / / / b/ 5/ / / / / / / / / / \/ 0/ 
/ / / / _/ )/ / / / T/ !/ / / / / / / $ $ / c/ 3/ / / / v 0 I0 0 0 0 0 r0 L0 &0  0 0 
0 i0 30 0 0 0 a0 -0 0 '0 0 0 0 0 0 0 0 "0 0 *0 0 60 0 0  0 !0 "0 #0 O$0 X%0 ]&0 a'0 m(0 u)0 |*0 c+0 ,0 00 40 80 =0 A0 3E0 F0 G0 I0 :J0 (K0 ZL0 P0 
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}1 z~1 f1 1 ك1 1 z1 /1 1 1 1 51 c1 u1 1 Ó1 1 l1 1 ܘ1 !1 Z1 1 Ӝ1 1 A1 1 Ο1 1 1 1 |1 91 1 01 1 1 o1 01 1 1 1 1 ?1 /1 )1 1 ʰ1 1 m1 Z1 Q1 1 01 ϶1 f1 1 1 1 1 61 1 1 1 K1 H1 O1 ,1 1 1  1 1 1 \1 1 1 1 1 1 I1 1 n1 61 1 a1 1 1 )1 1 L1 1 1 61 1 1 ^1 /1 1 1 1 ^1 1 1 1 i1 1  2 2 p2 2 2 V	2 
2 s2 -2 2 <2 2 r2 2 2 	2 2 32 2 <2 <!2 "2 $2 ~&2 (2 9*2 ,2         . . ^. ʈ. 5. . 
.     uq. q. ?r. r. "s. s. t. |t. t. Vu. u. *v. v. w. nw. w. Gx. x. y. yy. y. Vz. z. F{. {. 6|. |. 8}. }. 9~. ~. <. . F. ̀. M. . . . . P. . . . . . . . .                              (+ *+ `,+  .+ X .+ 1+ x4+ j7+ V:+ ?=+ "@+ C+ F+ I+ '' O( g) * L+ jL+ L+ M+ cM+ M+ N+ YN+ N+ O+ UO+ O+ P+ Q+ 0 R+ S+ S+ T+ OU+ U+ V+ CW+ W+ X+ Y+ Z+ [+ /f \+ h ]+ ^+ _+ `+ c+ e+ h+ |j+ l+ Go+ q+ s+ u+ @x+ gz+ |+ ~+ + + Ą+ + ;+ ͎+ r+ 	+ + + a+ + + ++ å+ `+ -+ + + 	+ + Y+ ߸+ _+ + + + ]+ + + y+ + + *+ A+ z+ + + [+ Z+ Z+ L+ >+ =+ B+ A+ E+ &+ + + + + + + u+ U+ G+ '+ '+ + + + +  3+ |+ + + + + + /+ b+ + H+ + +  , , J, , J, , s, , , -, , , , 3, , g
, , , 8, , ڤ , (,  " ,   , , , , Z, 4, 
, , , , , s, M, 6 , !, ", ", h#, #, $, W%, R&, 5', ', (, ), j*, D+, ,, -, -, ., Z/, 90, 0, 1,  (2, 3, 3, K5, 7, 8, :, @<, >, ?, A, OC, E, F, H, @J, L, M, O, EQ, R, yT, U, V, W, dX, Y, Z, (\, [], ^, _, a, Qb, dc, d, e, f, g, Ni, j, k, xl, am, In, #o, o, p, q, r, 9s, t, t, u, v, w, w, ax, y, z, {, |, }, ~, , 6, &, ;, , B, ., _, x, [, w, , , , ̎, , ,  , ,  , , ", , :, Q, 1, G, ^, t, |, , , , Ƣ, , , , , , , ͩ, , , , BT U I, Z , , , , , }, i, 2, , 	, ,  , ,  , , , 9, , , 5, , , (, 
, , ., , , +, K, , , , , e, k, ', , , , 0, , , , , k, a, , , _, F, , , , $, , , v, , , , , , {, , , , 
, U- - - 3- S- i- - I- 	- 	- 
- "- B- +- - - '- - - $- - - $- - - /- - , , - U- : - !- !- "- e#- $- $- %- X&- )- C+- &- e(- /- 1- ,- #.- u2- 
4- 4- P5- 5- 6- 7- I8- 8- {9- \:- >;- 93- <- L=- B- C- >- ?- 3A- =E- }F- 5G-  H- I- J- 0L- M- :O- P- Q- S- ?T- uU- V- W- Y- $[- Q\- a- c- \- ]- _- d- e- g- h- j- k- l- n- |o- p- q- r- s- t- v- w- x- u- z- `{- B|- '}- 	~- ~- - π- - - 	- - I- - - j- g- b- [- V- ]- }- Y- T- G- - - - r- - - m- - y- M- "- - - H- - ֢- _- ץ- - z- - I- ө- - - - Q- )- - - ۱- - - - Ŷ- - S- - - ޵- - j- - - |- - - - - - - - 8- - - - - - D- - - - {- n- ;- - - - 3- - - - - - }- j- U- 7- - }- o- N- - T- 3- - r- - - - - - O-  .  . @. . . . l. 	. . . j- . =	. . . 
. p. ,. Z. . . {. . e. . >. . .  . ". $. %. '. (. M*. +. 2. 4. S-. K/. 0. s5. 7. 8. 9. ;. <. b>. ?. @. A. B. D. 8F. G. C. H. J. K. L. M. N. O. P. Q. R. S. U. "W. T. X. tY. uZ. t[. q\. p]. {^. _. `. a. b. nd. f. g. Ki. j. l. um. ]n. Fo. 1p. p.             T yS V í W 2Y Y  K F  \\ e^ "_ `  b {c f 1h fi o 3r 
s t v Yx { | @}* * ڀ* * * K* *        ) &    e      M , 7  )/ / 2 3 L5 6 8 9 9 ]< = ? @ A &+  ͨ     0 -  I   "  X   $  * * * O    * X* * k* * * J* 
 !             f 8    %+ &+          ? G   , u	 e
    %    " е    A  ; &'+ U    M   a  /  bD [E H }I J <L  # )       ?       L x	 ۈ* 
 e
 [      4 c      :  W   7      % #' ( 	) * D+ y, - . / 3 6 5 ]8 j* b* * 9 ; 3= > ? A 3B aC M # c% ' ( }* 0, - / D1 2 Xi     9! s"   * * * * ]* * œ* m* c* w e* :* * i* * I* * ؝* * * ̡* Ο* * * d* * u* * * 4* * * * ,* J* T* *  + * j* * + \* * ھ* s* K+ F+ + + a+ C* * * * Y+ ?+ * H* 5+ * gQ * + + 4+   n  [ j F Z* *   * ?*  ͥ F L   q  ^  + + + + +  + z!+ s    X          <"+ #+ $+  e   )  l  '+   	 
 x      C    Z   U   RR     Sa a wa a  a 3a a a Ra a a a a Sa F[ G[ 2H[ a I[ {J[ 1K[ K[ L[ aM[ N[ N[ GO[ O[ a Q[ tQ[ [ S[ B[ T[ T[ KU[ U[ ;m[ m[ [  \ m\ )\ \ \ >\ \ La a a a Na a 	\ s
\ 
\ [                         {	 }	 ~	 ~	 ~	 3* T5* P6* 7* 8* s:* ;* <* =* >* FB* rC* D* F* %G* vH* $* *  * X!* !* "* @$* $* b%* 3) <  <I* I  K* `) cK* |	 } b* Uc*  1 `d* ƨ
 `
 e* g* Gh* Qi* j* 
 
 Il* m* &o* lp* q* s* %* >'* ** e )  JL* ,N* 
 C 
 F t* 
 .
 Iv* 6)   O 8) $P* R* .T* w* U* :) ;) W*     Y      h" )# # $ =) e>) ?) A) B) @D) E) F) H) I) J) y* mz* {* K) $M) [N) ~O) ) ) W+* ) P) S) T) Q) +V) zW) ) ) ) =,* X) Z) l) ) 1[) m ) o Fr (t ]p ]) ^) ) x) ) `) ) (b) f) `h) c) j) l) ) r) 1) n) Iq) ) sr) t) v) s) rw) x) ) ) ?) y) ڀ h)  Ɖ  t 0{) }) ) p) ) ) M M) ) ) ) ) *) () ) ӊ) ) ݈) ǎ) ) s) ) G) U) c) ) ) ) ) )  ) ) ) J) ) )  * ԡ) ) ) !) ۨ) ) C* * * I) G) ) 8* * ð)  ) * 	* -* h
* * &O ?) * .* .* * ) * 3) ) G) ַ) ) ) I* * * ) |P  ) @* <* 
0* >* ) y) ) ) ) ) $* %* ,* 0* 2* g) * * W*  G[*  j\* ^       
]*    1  k     t]* a Z^* \) "_* `* a*                             2H[ I[ {J[ K[ L[ aM[ N[ N[ GO[ O[ Q[ tQ[ [ S[ B[ T[ T[ KU[ U[ ;m[ m[ [  \ m\ )\ \ \ >\ \ o\ 8\ \ \ q\ >	\ 	\ s
\ 
\ [     =#) $) K
 () () 9)) -
 /+) .) 0) ) ) C5
 +) 2) 0) ) 	) 
) b) ) ) m) ) ) y) $) ) ) +)  v  ) 3) !) ,) t-) 6.) 1{
 )
     ^a %a a a a sa         Y *^ SY Y &Y Y S+^ {Y _ _ (_ <` _ >_ #` m` _ _ }_ ` J_ _ ` d ` e_ *!` @"` #` k%` '` /(` (` )` *` k+` [ 	a @[ F[ G[ 2H[ H[ I[ {J[ 1K[ K[ L[ aM[ N[ N[ GO[ O[ P[ Q[ tQ[ ْa R[ S[ S[ a ia 3a T[ T[ KU[ U[ a a a a Ja [V[ a X[ Y[ a G\[ ][ Ba _[ T`[ ia b[ a aa a Ba a <a c[ a f[ f[ 	a 3i[ 1_ a a ;m[ m[ 3_ 6_ 6_ 7_ 8_ _9_ t[ Ou[ jv[ ҳa a Ca ӵa a a w[ Zx[ x[ y[ z[ h{[ |[ |[ :_ }[ '~[ ~[ [ T[ [ Á[ [ 2[ Ń[ >_ _ c_ 5a a ca a a Na  a a ˽a a \[ Z;_ <_ <_ =_ Z>_ ?_ ?_ @_ [ [ \[ [ /[ e[  [ K[ [ [ [ za a s_ _ r_ ",` -` .` 0` '1` 2` 2` {3` cY Y #4` +^ 4` I6` w:` 7^ M>` ?` A` D` H` Q` V` [` &_` Jd` f` i` uk` n` q` {t` Y `w` x` z` |` I^ E` ` ` ` ` ` 0` )` ` \` ` ` p_ ` ı` ` o^ ` t^ w^ `` r_ 3` ` ` ` O^ ^ ` ` ` ;` ` ` 2` ` ` ^ ΅^ ` ` 7` ^ j` Z` A` ` ` 4^ `  ` ^ ^ ^ ` ^ b^ ` 8^ ^ ^ ^ [` ` ` K` ` ` VZ /WZ m` =` WZ }XZ E` H^ %` ` ^ L^ ^ ` w^ 9^ ^ 2` ^ ` ^ ˥^ ^ ` }` ` W` =` -` ` ` O` ` Y` ` _^ ^ ExZ ݭ^ 3` ` ` e` 1` $` o^ ^ @^ ` z`  a Ra ^ p` a a a ̴^ 	a Z ^ Z =^ &Z Ŷ^ ܷ^ \^ ^ ^ Q
a _ Ha La `a Ca a a R^ =a B a !a c#a %a 'a *a ,a 0a 3a e8a ;a \?a @a Da _ VGa Ia Na Qa \Sa Ua ^Wa ^ |^ ^ c^ )^ ^ #^  _ Xa I]a _a Pda Sha Jja na _ hqa sa ua wa rya h|a !_ Ta (_ d-[ a qa a a ?a ҍa BY Y  Y h!Y ͏a la a                         % h% 8% % % >% % ,% %  % % % % 9% % %% % #% % % h% % x% % % 
% |% % % % % z% % % P% % X%  % % N% % % K% % % % % H% % % % % & & & & & & 
& & E& & & & & Q& ^& & & & m& & & *& & W& & & & 5&  & "& 7%& %& && && && e'& -& '& H(& (& $)& )& *& w*& *& S+& ,& /-& /& ]0& 1& 1& V2& 2& 4& X5&  6& 6& 3& *4& X7& 7& 8& -9& 9& ;& <& =& >& @& $A& B& #C& D& C& 1E& F& F& G& H& mH& H& YI& I& NJ& J& 8K& K& zL& L& mM&  N& O& Q& 4R&                     3& R& S& 6T& T& U& V& "W& W& X& tX& bl                 v ( a( ( ( ( (   9  ( y     M ( )( ( F( O v  (                             " e" 2" " " " l" 9" " " " p" @" " " " t" D" " " " {" H" " " "  # O# # # # # V# ## # # # ]	# *
# 
# # # d# 5# # # # |# P# # # # C# # # L# # # {# k# Y# # "# ^%# (# 
,# ]/# 2# 	6# _9# <# @# aC# zE# G# vH# I# I# PJ# J# K# }L# VM# /N# O# O# P# Q# tR# OS# *T# U# U# V# W# X# Y# Y# 2Z# Z# &[# [# ,\# \# I]# ]# ^# _# `# a# b# c# d# e# g# g# i# i# j# Ul# m# n# n# o# p# q# r# s# 7u# @v# w# x# y# u{# |# }# # f# _# # 8# p# # ̇# 1# ,# |# 	# A# # # # # M# ڕ# # # # # 6# # # # ڟ# $# # ݣ# (# -# # # ˩# R# # # ŭ# # I# '# ΰ# z# D# 
# X# # # [# l# # u# # *# K# # # =# # # S# # # # # # # # # <# # # # # # # # # :# # n# # v# # # # *# # # # ?# # 3# # # t# %# # }# f# E# # # # b# # # # q# 8# q#  $ $ 5$ 1$ 	$ $ S$ $ $ 5$ ;$ $ .$ R$  $ "$ $$ &$ ($ s+$ -$ /$ 1$ 4$ 6$ ?8$ :$ D<$ =$ H?$ A$ PB$ C$ E$ aG$ I$ eJ$ L$ mM$ O$ P$ lQ$ Q$ SR$ S$ S$ (T$ T$ U$ <V$ V$ W$ X$ aZ$ [$ <]$ ]$ y^$ _$ _$ S`$ `$ gb$ c$ Xe$ f$ Ih$ i$ 8k$ l$ m$ m$ n$ o$ p$ {q$ ir$ Ts$ ?t$ -u$ v$ #w$ .x$ 9y$ Dz$ R{$ `|$ k}$ v~$ $ $ $ $ $ $ Ʌ$ Ԇ$ $ $ $ $ $ $ *$ 8$ $ $ 0$ ֑$ $ ,$ ד$ $ t$ h$ \$ T$ $ $ [$ $ $ f$ $ ĝ$ f$ $ $ J$ $ $ 9$ $ 1$ $ '$ $ %$ $ $ $ ï$ ̰$ Ʊ$ $ $ $ ĵ$ $ b$ 6$ !$ $ $ $ Ѽ$ $ $ $ j$ R$ :$  $ 1$ B$ S$ b$ v$ $ $ $ $ `$ $ $ X$ $ $ T$ $ $ U$ $ $ Z$ 
$ $ j$ $ $ [$ $ $ C$ $ $ 0$ $ ($ $ $ $ $ $ $ $ $ $ $ $ z$ $ $ $ $ $ $ "$ :$ $ $ $ $ x$ I$ $ $ $ $ d$  % % % % % 6% `% % 	% 
% % 8% S% q% % % % % % S% % % ~% 6% N% i% % % % % % *!% Y"% #% ]$% 5%% 
&% &% '% (% Z)% (*% *% +% ,% Z-% .% /% >1% 2% %4% 5% a7% 8% }:% <% =% >% @% 9B% C% AE% F% .H% qI% J% L% M% N% TO% 	P% P% vQ% .R% R% jT% U% eW% X% BZ% [% :]% [^% _% `% a% b% 	d% e% e% f% >g% g% h% ii% j% j% k% l% |m% Xn% 3o% o% q% qt% w% {% _~% % % Q% % % =% % ט% % % I% n% f% w% B% Q% % ̷% ȸ% ݹ% % % % 0% '% 7% % % a% % % % j%                 H! }I! HJ! K! K! L! zM! EN! O! O! P! tQ! BR! S! S! T! nU! <V! 
W! W! X! kY! 6Z! [! [! \! h]! 3^! ^! _! `! ea! 0b! b! c! d! be! -f! f! g! h! \i! *j! j! k! l! fm! 8n! 
o! o! Zp! p! 4q! |q! q! r! \s! Mt! mu! iv! 3w! <x! x! 2y! y! (z! z! {! {! {! }! ! ! ! l! ! f! ! Z! х! H! ! ! ! ! ! ! ! x! \! >! ,! ! m! ! ! l! ! ! e! ! ! ^! ! ! ! 8! ! j! ܾ! ! ! e! ! e! ! Z! _! ! ! ! ! ! ! &! ! :! !  ! ! ! >! ! o! H! !! ! ! ! ! ! 	! ! ! ! 	! ! ! ! $! r! ! ! m! ! }! ! ! ! ! ! W! `! ! ! t! ! .! ! ! o! ! w! ! ! K! ! ! ! q! ! [! ! I! ! ! ! d! E! )! 
! ! ! ! ! !  " " " " " " " " " 	" 
" " " " " " "" ." :" C" L" U" ^" j" v" `" *" " " " u" " Q" " 0" "  " x "  " D!" !" "" "" K#" "" #" $" k$" $" 5%" %" &" &" )(" ("  '" '" V)" )" F*" *" H+" +" L," ," Q-" -" A." ." P/" /" U0" 0" G1" 1" V2" 2" e3" 3" n4" 
5" 5" J6" 6" \7" 7" k8" 8" p9" 9" Z:" :" ?;" ;" `=" =" 7<" <" >" >" }?" @" o@" @" ~A" A" tB" B" C" 2D" D" {E" E" qF" F" G" H" }I" SJ" ,K" K" L" M" kN" =O" P" ,Q" OR" oS" T" U" V" W" %Y" MZ" u[" \" ]" ^" _" a" /b" Kc" dd" e" e" f" ?g" g" h" i" j" k" 	m" "n" 8o" ep" q" r" s" t" u" hv" >w" x" x" y" |z" E{" |" |" }" a~" " " " g" " " " " >" Ѝ" )" ː" i" " m" ܖ" V" " !" " " " p" #" ٠" " B" " z" " q" " J" ׫" >" ]" " " " ߲" " " b" " " J" " " 6" " " " h" " " " y"  " " M" " Y" " g" " h" " \" " V" " E" " )" " " }%         l! ! ! ! ! ! X! ! ! K! ! ! J! ! ! t !  ! D!! !! O"! "! l#! #! A$! $! W%! %! R&! 
'! '! j(! )! )! *! *! C+! +! #,! ,! -! -! -! .! .! /! 0! 1! 2! l3! 3! ,4! 4! 4! H5! 5! 6! 7! 9! ;! ?! m=! @! NA! A! A! SB! B! C! XC! C! D! _D! DE! $F! F! dG!                 ' ' t'  '   p ~' ( ( ( ( l( 	( 	( 8( ( ( ( (  q ( q( ( 6(  &  W ( L( ( ( "( ( ( m( ( O( ( ( ( ( r( ( 5( ( ( q( ( .( ( ( ( ( p( ( ( ( Q( ( @( ( 9 (  (  (  .!( j j j j j m p s v  "(  -  w   l   t $	 .%( &( '(    0   C(( (( )( j)( )( 6*( *( +( h+( +( 0,( ,( ,( V-( -( .( |.( .( V/( /( G0( 0( ,1( 1( 1( N2( 2( 3( 3( 3( L4( 4( 5( r5( 5( 66( 6( 6( \7( 7( L8( 8( ?9( 9( :( f:( :( 2;( ;( ;( d<( <( ,=( =( =( R>( >( ?( x?( ?( R@( @( CA( A( (B( B( B( JC( C( D( |D( D( HE( E( F( nF( F( 2G( G( G( XH( H( HI( I( ;J( J(  K( bK( K( .L( L( L( `M( M( (N( N( N( NO( O( P( tP( P( NQ( Q( ?R( R( $S( ~S( S( FT( T( U( xU( U( DV( V( W( jW( W( .X( X( X( TY( Y( DZ( Z( 7[( [( [( ^\( \( *]( ]( ]( \^( ^( $_( _( _( J`( `( a( pa( a( Jb( b( ;c( c(  d( zd( d( Be( e( f( tf( f( @g( g( h( fh( h( *i( i( i( Pj( j( @k( k( 3l( T n( p( s( t( wt( t( \u( u( ,v( v( w( Pw( w( w( Vx( x( y( Yy( y( y( 9z( z( {( {( {( h|( |( ,}( }( }( j~( ~( <( ( ( e( ( ( <( ( ( R( ( ( e( ń(  ( m( ( 	( X( ( ( X( ( ( r( Ɉ( "( ( .( Z [ [ ( m( ( m( a d ( ( ܘ( >( ( 
( p( ֚( <( ( ( f( Ȝ( *( ( ( P( ( *( ( ( (  ( Z( ( "( ( ( T( (  ( ( ( F( ( 
( l( Φ( 0( (  ( ( ( ~( ة( :( ( ( l( ҫ( 8( (  ( b( ĭ( &( ( ( L( ( &( ( ( ( ( V( ( ( ( ( P( ( ( ~( ( B( ( ( h( ʷ( ,( ( ( ( ( z( Ժ( 6( ( ( h( μ( 4( ( ( ^( ( "( ( ( H( ( "( ( ( ( ( R( ( ( ( ( L( ( ( z( ( >( ( ( d( ( (( ( ( ( ( v( ( 2( ( ( d( ( 0( ( ( Z( ( ( ( ( D( ( ( ( ( ( ( N( ( ( |( ( H( ( ( v( ( :( ( ( `( ( $( ( ( ( jf             X& [[& ]& x^& _& _& W`& `& a& b& b& c& c& ,d& d& Ze& e& f& g& 
i& Lj& kk& yl& m& n& p& Hq& fr& ss& t& u& v& 5x& Oy& Xz& a{& |& }& & ,& 4& <& Ʉ& & & 6& ?& H& ֏& & $& G& O& W& & b& & & 1& Q& & a& & & 2& Q& & & & & & & M& l& & ͻ& &  & & & & & & & & & & & & & & & & & '& )& :& ?& V& m& & & & & & '& z& & !& & ]& & & M& & w& & & W& & & & & `& & & }& 2& & & `& & & & 9& & & Z&  '  ' ' 6' ' ' T' ' ' ^' ' ' s' *	' 	' 
' P' ' ' z' 3' ' ' `' ' ' ' D' ' ' s' .' ' ' `' ' ' ' A' ' ' h' !' ' ' L ' !' !' v"' ,#' #' $' O%' &' &' v'' .(' (' )' X*' +' +' ,' 8-' -' .' d/' 0' 0' 1' M2' 3' 3' !4' 4' 5' t5' 5' Z6' 6' B7' 7' *8' 8' 
9' z9' 9' \:' :' z;' &<' <' ~=' +>' >' F?' ?' "@' @'  A' pA' A' RB' B' 4C' C' D' D' D' pE' E' VF' F' xG' &H' H' I' 1J' J' K' @L' L' M' QN' N' O' UP' Q' Q' [R' 	S' S' eT' U' U' qV' W' W' rX' Y' Y' uZ' "[' [' |\' )]' ]' ^' 2_' _' `' 9a' a' b' Dc' c' d' Qe' f' f' 'h' Yi' j' k' m' "n' o' p' r' Ms' mt' u' v' +x' {y' z' {' |' P~' |' ˀ' ' ' -' ' ,' ' ύ' ' ' ' ' `' ' Ț' ' ˞' D' ̣' I' |' ' ' ' ' ' K' }' ' ' _' ' ' ' 6' p' ' ' ' ' ' ' ' ' |' ' ' ' ' ' >' N' ' ' ' '  ' B' s' ' ' ' ' '  ' 1' b' ' ' H' ' ' K' ' ' Z'                         7  9  |   n  v     -  C  \  w  w    =  O  <  L  W  s  /   K  `  G  1  U  A  Y  q '   s 7    M    c '   s :    M    c '   v =    M    c '   y A 	   d /     X   a  # v : 	  j #   T   " P% '' O( g) * , g- B. )/ 0 1 =2 2 M3 4 4 H5 5 6 77 68 8 9 q: = A [D G J ?N Q T &X q[ ^ b d /f $g h i .j ]k l m 
o o Vp q q ,r r <s s v x { O}       ˅   w   w ] C )   u N '     ޓ  <    ܙ Ӛ  l  g  ` ڤ  8  " ,   6  ڮ  ~ L 0   j ۴ l ݵ N  B ŷ M  ?   P   ^ Խ J Ⱦ A  0  "   b 
 }  e  V  d  p  t    f        U  )   d  0   p  :    T    P    p \ C *      f | ] B !         )              I   z 1   U	 	 
  V 
  { ;    I    @    ]    D    :   n  ! ! " c# $ $ % & N( ) + + B, , j- . . 0 t1 2 P4 5 07 8 x9 U: /; 	< < = > ? i@ KA 0B C D F P\ {^ O GQ BT U W Z j l ` b bd e g 9i <H H I J L 5M wN n o p q r s t u v w x y z { | } ~  À Ł ǂ Ƀ ˄ Ѕ Ն  s v P r ׌ ڍ  6  @ ǒ ]  \  p      y U   j .     Ӫ   W   y     5  ɶ  R  v   F 9  y   F     I    R   )    { J    ~ F        $ = ^     	  0 B T i { *   :         ! G m   _ .    d &   r	 4
 
  F  I  .  .  K  (  Z   P" # +% e& ' g) * l+ , , v- ". . o/ 0 j2 3 %5 6 58 9 : ; < = ? .@ V Y ] :` ac f i l 8A C F UI 
L N sQ T o /s vv y } K  ن  e   2 < D * .  .  4   0  ު >   a  #   R      \  ,   .  X     M  ~   B  l   3  a   ,  V         G    u      @    n      6    m  
	  	  D
  
        A    8    P    _    s          9    W    k    z          !    E    ]    v      5    g   !  !  6"  "  `#  #  $  =%  %  y&  '  '  X(  (  )  5*  *  a+  +  ,  -  -  Q.  .  /  -0  0  A1  1  T2  2  j3  3  4  5  5  6  6  +7  7  %8  8  V9  9  :  ;  ;  D<  <  =  o=  =  7>  >  /?  ?  I@  @  cA  A  }B  
C  C  8D  D  qE  F  F  6G  G  dH  H  jI  I  {J  	K  K  L  L  GM  M  N  O  O  IP  P  cQ  R  R  6S  S  aT  T  U  /V  V  dW  W  X  -Y  Y  XZ  Z  [   \  \  O]  ]  ^  &_  _  Z`  `  a  (b  b  ]c  c  d  e  e  (f  f  6g  g  Jh  h  i  j  j  Wk  k  l  m  m  In  n  ~o  p  p  Fq  q  {r  s  s  Gt  t  ru  u  v  6w  w  ex  x  y  /z  z  k{  |  |  ;}  }  T~  ~    -  ƀ  \      *  ƃ  _      !    L    }      A  ڊ  v      B  ܍  m      1  ɐ  `          F  ͔  W  ޕ  e    v      ,    Q  ߚ  p          #    9  ɟ  V    s           H        !    -    !    F  ܥ  s    T    ԫ  q      .      1  ر    &  г  z  !  ȵ  o      j      _      Z      O      J    w      9    ^          @    y      M    ~      F    p      ,    U    r          @    q      9    _          G    t      1    V    {      A    z      J    {      C    p      ,    U    z      $    A    V          O    |      8    a          Q          R     ! !! ! K! ! a! ! ! ! ! P! ! 	! ~! ! ! D	! ! r
! ! ! >! ! p! ! ! B! ! x! ! ! >!                     ={ dQ | | 
~  H w b t U D f/ `2   ": , X  i  9  
* {* * Z+ + 7, , 6  o  Ɏ  1 ڕ Ж J  UK K }M   Q S - t dW US U W ( @( ( 4( ( ( F( ( ( )( ( ( ( ( B( ( (       # >& f) |, / r4 8 < A D rG 05 XJ UL SN QP C[ ]\ ] ^ _ 4` a b d e f h i +k l n &o ?p r Ĕ  Y   C    s (t t u Wv - - w x Kz { V} ~ Y  < w م  A a     g g  Ē  =   . Ƥ æ  D  4 )( H( z( 	( ( ( M ) ) ) . / 1 x4 = &5 5 Q7 98 8  y9 D D : e
 [  H _; mK 9< == K c  D> (   @ > y@  7 6 i +o r  *B tC aD `E 
F ?G wH I J K L vM KN O {P <Q Q S T V X NY Z Z [ ]   ğ  s F   M _ ` a _ b c #d d |e f g .f h Vi i sj k l %k m Mn n jo p q p r Ds s at u v u xw ;x x Ū  s  s  [ ٰ  :  ٴ  ͵  S C  ٹ      X   z Z  ! " ! # $ % % Xy  { | 0z "} ~ ~ h   z ؀ X $  M Ն    T  }  ڌ 8     5 
 h   I        i #      ~ ( !        x J& ' ' ( * h+ ) U, 0- - m. ݔ  p  g F ߙ  2  k  =     O Š !  n  j 3   Ũ R ީ N     6 -     a  '   0  P 	   w        v . / 0 o1 2 3 -2 4 5 6 6 ® b I  <   U  e +    B ̹ 6  x ˼      I  Y  n    m *  #     @    X    #   O 9       v " B7 8 8 9 1; < d: < = E> > ?     l   @  ^  '  e  I 	        < } 4  A  _  (  f  g K   ;   y   ^ =	  %
 
  {        8 e? %@ @ A 6C D oB D E 4F   7 " T    7  T     (  "  d  k     2 | 9  N     J         h   >     `    f! C" # $ # % & ='    r   .   ]  |      p   P	 
 w 	 <  |  j )    .    b  Y  f    R   ' ) w* ( k+ , M, - g. / 0 y1 / S2 !3 3 4 5 5 7 ~8 6 d9 >: :    b     v! 9" " P# # % ~& $ n' L( ( ) <* + o, * 8- - . / 0 E1 / 2 2 Z3 3 X5 6 4 6 7 08 8 .: : p9 ; w< = m; != > ><  ? @ ? WA B B RD *E C F F tG OH H I wK [L J EM #N N = W> ? ? nA ;B @ C C iD F D tF AG E H H `I I J K L .K 9M M `N N $P P {O Q .R R +S qT U S U {V V xW X lY X  Z Z G[ bO P Q P R S US T <U U GW 
X V X Y Z Z i[ 1\ ] ^ \ ]_ &` ` OG G H fI J xK J 6L L lM M [ ] ^ \ ` %a a b c re ef d ^g Kh i i k l j ~m kn 'o o q r p s t Gu v w x v y z g{ Ea _c }d Ib e g f h oi Oj Il Qm Fk _n ao (p 3q q s u ,v 	t Fw Tx !y N O P Q S ~T R U xV 9W W "| } ~ }    ^     k < ܇ {   A ǋ  8 ׍ o F  #   3 ˔    P  y { | z }  ~ r 7    ւ   ,  ň      x ) X |Y SZ 7[ \ ] \ ^ _ +` `  M = e 6   u ,  }  P   J Υ   n 5 Ϩ h   $  S   
 װ B  q  ُ     9 {   y ' 	 J  ͛ r W       r  ua Bb c c e Xf d 5g h h Ci       Z &   ~  e @   ?   c    5      .   d  K &  Ǥ  ɧ  ި    a /        I D 2 4 5 < 8  i j k l in To m Ep *q q r y C 9 U 8 %   F     O     P   7  f 9         Z '    y  | 1 m    = % Z     5 "       3s t t u ]w :x v y y z f   S b 1 <          F  Y *  u J  %  	 
 R     y B 
    ^ 1   ^ 7     z   B    j!      p  B   t : ( Q        }  } q [ 2" # # $ }& `' % I( &) ) * + (- . R, . / 0 _1 )2 3 4 2 5 n6 =7 8 9 : 8 w; P< = = ? t@ > YA 2B C C wE VF D ;G H H D     U  3       | ` X ; 5   $ %    I J qK ^L N O 6M O P Q R ;S T U S wV DW X X Y 4[ \ bZ \ ] ^ F_ ` a ` b cc *d d f _g e <h i i j 2l 	m `k m n ~o    j  F    { @ 
 
 	     m _ 9 1 F / ! 	 Dp q q r t fu s Mv (w w x |y { { <z | {} L~   a 6     i  ҇ -  | A   n ɋ I  ݏ  5 
 e   y   V  0    ]       ! " v# d$ =% -& ( ( ' ) * + =   ̘ t S  8    ]     H  Ҥ    N ¨  N   k Ϋ B  ί    N ³  N   k ζ B  κ , :. 
/ o- / m1 0 =2 2 3 r5 X6 4 D7 $8 8 9 : ; s= e> < ]? I@ +A  ` 2    ۾ m B    4  ^    k 5     z I      \ +     e >    b  G    B C D B tE G LF G H I hK \L yJ VM DN (O  P Q Q S T R U V W   } j &  B     O      [ &   w  \ 5   z Y  >    \  ;       >  d   	 X lZ J[ Y .\ ] ] ^ _ P` "b c 3a d d e f g h j k i l m n x
 X 8 %      u M   e  >    c   )   G   ! |"   Y# *$ $ % O' &( }& ) ) * a+ , - ', . ~/ E0 o q q Ep r at s 7u u v x py w bz H{ $| } } ~       1 1 2 3 L5 -6 p4 7 7 8 9 ;: ; < : O= > > ? L@ A B A pC 7D D E 4G H lF H I XJ K L eM K 8N N O xP Q R 4Q S cT  U r   -   X   Z   + ҏ   f 7   Ӗ  Ǘ   U V xW SX Y Z Y [ p\ 7] ] ^ T` -a _ b b c d Ie f g f h i Qj k l m k n Xo %p p r rs q Ut ,u u v ix Fy w )z  { { j   5 ʝ o  K     â   h ^ ? 7   $    | w} U~ @  ߁  ̂   Z    ݆ i <  ދ  J ' r 
   z   F ޕ   N  Ϛ    V " Ɵ    ] *   p  R  ( Ӷ  j 8 * K "    ǿ         Ԥ   U < s ) 
   j  ǯ *  i :   O $   η  W     j /   \  7    #  S   g z   =  O  #   h R  B &          o U +    b A  &    W     ~ W     i  L #   ` =       4  \    d   0   l :     ? p     r  j V 8 .         8     ~  k L #   8 	 l   | =     f  A    - 	 ] 	 
 q 5    y H   e :      T (     k /      n H  6         m C      h A    Ķ M    i 	 u
 '  x 
  I    B! ! ," " ) k)     D      W  ѽ Ҿ ӿ        K    ̈ ^    1      K   > Y *^ SY Y &Y Y S+^ {Y _ _ (_ _ >_ _ _ _ _ }_ s_ J_ _ _ _ e_ %_ w_ _ _ j_ _ ._ /_ o0_ F[ G[ 2H[ H[ I[ {J[ 1K[ K[ L[ aM[ N[ N[ GO[ O[ P[ Q[ tQ[ 1_ [ S[ B[ ?_ _ :_ T[ T[ KU[ U[ [V[ ,W[ X[ Y[ Z[ G\[ ][ ][ _[ T`[ %a[ b[ c[ dd[ f[ f[ g[ 3i[ 1_ 12_ k[ ;m[ m[ 3_ 6_ 6_ 7_ 8_ _9_ t[ Ou[ jv[ w[ Zx[ x[ y[ z[ h{[ |[ :_ :_ >\ \ o\ 8\ \ \ q\ >	\ 	\ s
\ >_ _ c_ _ _ G_ _ _ j_ _ \[ Z;_ <_ <_ =_ Z>_ ?_ ?_ @_ s_ _ r_ _ q_ _ _ _ _ q_ cY Y _ +^ .^ D0^ j4^ 7^ :^ >^ X] A^ _ I^ _ (Q^ WS^ U^ X^ [^ _^ _ f^ @j^ m^ U Z o^ r^ t^ w^ z^ ~^ ^ O^ ^ ^ ΅^ s^ y^ ^ z^ 4^ ^ ^ ^ ގ^ ^ b^ 8^ ^ ^ ^ J^ ^ \^ ^ VZ /WZ }XZ H^ ^ ^ L^ ^ Ǡ^ w^ 9^ ^ ^ h^ ^ ˥^ ^ k^ c^  ` ^ _^ ^ ExZ ݭ^ {_ ȯ^ o^ ^ @^ M` ` ^ p` ̴^ |_ Z ^ Z =^ &Z Ŷ^ ܷ^ \^ ^ ^ -^ Y^ ^ ^ ` ^ R^ ^ 
` ^ $^ ^ )^ 7^ i^ ^ ^ B^ ^ |^ ^ c^ )^ ^ #^  _ +_ _ 	_ J_ _ ` ` _ )_ _ _ _ !_ M%_ (_ )_ ,_ ZA_ B_ B_ C_ `                     3& g h \i %j j k bl l m Jn n o ]p  q q | ƭ 	 ٮ  9   9    . ^  1 [    N ~  Q {  @  L  s   	 u  M  -      X  <   ?  	  j   W !    s Q $     c   Y     V -    ! s" c# S$ C%                         M  ú  ?   u :   b    K    \   +      1   A   C   Y   [   Z 	  j   l   z  A  : t  H     B     [   Q    T 4     
 W    Q    ~ P   ! `# % & ( + P, J* * V. / , - / 0 p1 Q2 23 3 ,4 4 &5 5 6 9 W= @ 4D G K kO vS W u[ k_ ~c 9g j @n q t cx |     Ɛ ]  ͛ a  U ԩ         xr s &t t t ;u w y 7| ~  6 f  &  ى M  a  4 q  t      |  /   F    Z  ث  a y   ڰ   _   Z J : *     s         H I ,K M AP R :U W Z 
] _ c ha e g i j kk l n do p r cs t 	v \w x z #{ } Y  ΃ 	 D    0 k           ;    z : 7 r   ' d    X     L  (
   r  N  *    t" # n% & h( ) h+ , - ./ 0 *2 3 )5 ,9 6 8; < = ? q@ F L Q W ] b Th n s x ~ ; m 7  ܖ   ˚  / < I {   ţ  -  #    % B h \ P m  ~ r                v  T 
  v ,   N   n # ص  B   a   * û \   '  Y   !  Q      9  y      M z  4  O v  .                              5 ^6 _8 8 i9 : : R; ; < == = > ? u@ 	A A oB AC -D D nE &F F G 8H H I jJ K L M O $P LQ uR S T <U U $V V W W 	X Y [ ] a h_ dc Hd 'e e gf     & '      p     ,  u Y  ( ) )  j  q  &  W  ) j j j j j m p s v    -  w   l   t $	 
 x "    0   n  v       "  &  *  .  2   2  n  j  x         ! ! " " "# # N$ $ % R& & Z' ' V( ( d) ) r* * + , , - - 
. . / / :0 0 1 >2 2 F3 3 O4 4 ]5 5 k6 6 t7 7 x8 8 |9 9 : ; ; V< = = >> > :? ? H@ @ VA A dB B hC C lD D pE E tF G G tH "I I *J J 3K K AL L OM M XN N \O O `P P dQ Q R :S S T W Y Y cZ Z [ [ s\ ^ a d f Mg g Ih h Wi i ej j sk k wl l {m m n o o -p p q 1r r 9s s Bt t Pu u ^v v gw w kx x oy y sz z { I| | } 1~ ~ -  ;  I Ё W ق [ ݃ _  c  g   g     &  4  B ɍ K ͎ O я S Ր W ّ  - ٓ        -  ;  ?  C ś G ɜ K   K     
    &  /  3  7  ;  g   jf           A P _ m {   	 \
 
   * z   ~  l  T  ;   (  K  >  f   } 8   3    K! ! K" " L# 	$ $ `% & & +' ' ( * 1+ ], - . / / 1 :2 g3 4 5 6 i6 6 c7 7 S8 8 M9 Y; E< -= )> ? ? @ A B C D F _G H hJ L ?M N O -Q R :T rU V aX Y Z `\ ] _ ` b Ac d f g h Aj k .o r v y | + w   Æ h  C U   ܎ Ï  # yE P   s< ? B   { J  k   &    k D        ~ i U A *      k   j   e    D     r   Y	 	 
 $  c   M      I  { )  i        $ ' * U. 1                   H !   w I    X F 1     / k @ "      /   %  >     9   ;  	 p    q&  p )  /  ,  [ /  " o% 3 . A2 06 5 8 U< < 7= = 5> C@ PB fD qF F F :G }G H 5I TJ `K =L L yM $N N jO P Q S T V X Y Z \ ] ` xb Rd e f g j k l m p Qs u w x f{ 9} ,~  "  Z  \ 2     5  o  Ș ? ߝ  ̣ F Ũ W ڭ L ܲ l .   R9 ( [ ) 
 B "   
   6  [  \  j $ l   R   0   	 9 Z {                      3B 8       	! ! " # $ % & ' P( ) l* 5+ , >- - . f/ X0 _1 `2 _3 f4 b5 6 7 -8 8 ": ; < { Q 4 = = > x? @ MF F G J  UK K L }M N O 5P P Q TR S "T U V dW 1C A \   %  Z  Z M n "  B  K     =   " # % ' + `/ E3 05 5 6 ,8 9 : Yk k  m m n Uo [p p pG H I J  L iM N QP Q S T #V gW X Z L\ ] _ a a ec Df g h j j W Y x\ ] _ X` b Gc       >   D 8 9 #: = = |> ,? ? @ A fB B dC D D ^E F G G H H I J mK K #L L L M gN  O O P $Q Q Cd e Ci j k bR  OS T m ;n n +o o p q r U W 3Y Z \ 1 /   ^ ` >c d f g (i (s t v w y vz { a}  j 2k l Xm n Ip r ~  r \s ; < s u v v w x z | ~  ! 1 j @ C ? | / ] M    L f  k ;       > 8 >  B   b  D   s C= f> 4  m   L  t ,u v Ex y z #|     	 E
 J  c  \     D     { K  ? } ~         K   1 ̈ ^    1   s r         + -   I J `   G x 0      Y *^ SY Y &Y Y S+^ {Y ._ /_ o0_ F[ G[ 2H[ H[ I[ {J[ 1K[ K[ L[ aM[ N[ N[ GO[ O[ P[ Q[ tQ[ 1_ [ S[ B[ ?_ _ :_ T[ T[ KU[ U[ [V[ ,W[ X[ Y[ Z[ G\[ ][ ][ _[ T`[ %a[ b[ c[ dd[ f[ f[ g[ 3i[ 1_ 12_ k[ ;m[ m[ 3_ 6_ 6_ 7_ 8_ _9_ t[ Ou[ jv[ w[ Zx[ x[ y[ z[ h{[ |[ :_ :_ >\ \ o\ 8\ \ \ q\ >	\ 	\ s
\ >_ _ c_ _ _ G_ _ _ j_ _ \[ Z;_ <_ <_ =_ Z>_ ?_ ?_ @_ cY Y +^ .^ ND_ nH_ 7^ L_ >^ X] ;O_  R_ I^ "X_ \_ ^_ U^ *a_ d_ +i_ f^ l_ p_ U Z o^ r^ t^ w^ r_ w_ y_ O^ ^ ^ ΅^ s^ y^ ^ z^ 4^ ^ ^ ^ ގ^ ^ b^ 8^ ^ ^ ^ J^ ^ \^ ^ VZ /WZ }XZ H^ ^ ^ L^ ^ Ǡ^ w^ 9^ ^ ^ h^ ^ ˥^ ^ k^ c^ ^ ^ _^ ^ ExZ ݭ^ {_ ȯ^ o^ ^ @^ ^ Z ̴^ |_ Z ^ =^ &Z Ŷ^ ܷ^ \^ ^ ^ w}_ _ _ *_ _ ^ R^ 0_ 8_ $^ ^ )^ 7^ =_ _ _ B^ r_ _ _ Π_ _ U_ _ ϧ_ +_ _ ר_ _  _ _ _ j_ _ [_ !_ M%_ =_ _ ,_ ZA_ B_ B_ C_                         g h \i %j j k bl l m Jn n o ]p  q q     xr s &t t t ;u w y 7| ~  6 f  &  ى M  a  4 q  t      |  /   F    Z  ث  a y   ڰ   _   Z J : *     s         v  T 
  v ,   N   n # ص  B   a   * û \   '  Y   !  Q      9  y      M z  4  O v  .                              5 ^6 _8 8 i9 : : R; ; < == = > ? u@ 	A A oB AC -D D nE &F F G 8H H I jJ K L M O $P LQ uR S T <U U $V V W W 	X Y [ ] a h_ dc Hd 'e e gf          p     ,  u Y    j  q  &  W  ) j j j j j m p s v    -  w   l   t $	 
 x "    0   n  v       "  &  *  .  2   2  n  j  x         ! ! " " "# # N$ $ % R& & Z' ' V( ( d) ) r* * + , , - - 
. . / / :0 0 1 >2 2 F3 3 O4 4 ]5 5 k6 6 t7 7 x8 8 |9 9 : ; ; V< = = >> > :? ? H@ @ VA A dB B hC C lD D pE E tF G G tH "I I *J J 3K K AL L OM M XN N \O O `P P dQ Q R :S S T W Y Y cZ Z [ [ s\ ^ a d f Mg g Ih h Wi i ej j sk k wl l {m m n o o -p p q 1r r 9s s Bt t Pu u ^v v gw w kx x oy y sz z { I| | } 1~ ~ -  ;  I Ё W ق [ ݃ _  c  g   g     &  4  B ɍ K ͎ O я S Ր W ّ  - ٓ        -  ;  ?  C ś G ɜ K   K     
    &  /  3  7  ;  g   jf                           A P _ m {   	 \
 
   * z   ~  l  T  ;   (  K  >  f   } 8   3    K! ! K" " L# 	$ $ `% & & +' ' ( * 1+ ], - . / / 1 :2 g3 4 5 6 i6 6 c7 7 S8 8 M9 Y; E< -= )> ? ? @ A B C D F _G H hJ L ?M N O -Q R :T rU V aX Y Z `\ ] _ ` b Ac d f g h Aj k .o r v y | + w   Æ h  C U   ܎ Ï  # 6 P   p t X   { J  k   &    k D        ~ i U A *      k   j   e    D     r   Y	 	 
 $  c   M      I  { )  i        $ ' * U. 1                  / k @       /   g  >     9   ;  	 p       p  /     [  " o% ( + . A2 5 8 U< < 7= = 5> C@ PB fD qF F F :G }G H 5I TJ `K =L L yM $N N jO P Q S T V X Y Z \ ] ` xb Rd e f g j k l m p Qs u w x f{ 9} ,~  "  Z  \ 2     5  o  Ș ? ߝ  ̣ F Ũ W ڭ L ܲ l .   ( [ ) 
 B "   
   6  [  \  j $ l   R   0   	 9 Z {                          3B 8       	! ! " # $ % & ' P( ) l* 5+ , >- - . f/ X0 _1 `2 _3 f4 b5 6 7 -8 8 ": ; < { Q 4 = = > x? @ MF F G J  UK K L }M N O 5P P Q TR S "T U V dW 1C A \   %  Z  Z M n "  B  K     =   " # % ' + `/ E3 05 5 6 ,8 9 : Yk k  m m n Uo [p p pG H I J  L iM N QP Q S T #V gW X Z L\ ] _ a a ec Df g h j j W Y x\ ] _ X` b Gc       >   D 8 9 #: = = |> ,? ? @ A fB B dC D D ^E F G G H H I J mK K #L L L M gN  O O P $Q Q Cd e Ci j k bR  OS T m ;n n +o o p q r U W 3Y Z \ 1 /   ^ ` >c d f g (i (s t v w y vz { a}  j 2k l Xm n Ip r ~  r \s ; < s u v v w x z | ~  ! 1 j @ C s C= f> 4  m   L  t ,u v Ex y z #|     	 E
 J  c  \     D     { K  ? } ~         K   1 ̈ ^    1   s r         + -   I J `   G x 0  Y *^ SY Y &Y Y S+^ {Y ._ /_ o0_ F[ G[ 2H[ H[ I[ {J[ 1K[ K[ L[ aM[ N[ N[ GO[ O[ P[ Q[ tQ[ 1_ [ S[ B[ T[ T[ KU[ U[ [V[ ,W[ X[ Y[ Z[ G\[ ][ ][ _[ T`[ %a[ b[ c[ dd[ f[ f[ g[ 3i[ 1_ 12_ k[ ;m[ m[ 3_ 6_ 6_ 7_ 8_ _9_ t[ Ou[ jv[ w[ Zx[ x[ y[ 3z[ h{[ |[ :_ :_ >\ \ o\ 8\ \ \ q\ >	\ 	\ s
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	 	 R	 	 	 	 	 D	 s	 	 ,d  	 d!	 "	 d "	 F#	 #	 %	 &	 	 	 CV
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 	 	 J	 	                 n\ ̽\ \ \ \ \ \ Y\ ]\  \ \ \ έ\ :\ \ ȥ\ \ \ x\ 9\ \ \ e\ \ \ ,\ \ \ \ \ \ !\ g\ Է\ !\ c\ ״\ %\ 6\ t\ u\ \ $\ \ \ \ \ w\ )U\ U\ C\ \ \ [\ 3\ \ r\ N[ \ Q[ tQ[ \ S[ 9\ T[ T[ KU[ U[ ;m[ 6Y\ Y\ Z\ 7[\ h/\ _\ `\ pa\ \ 8\ \ l\ \ \ \ \ \  \ \ w\ [\ \ g\ \ B\ `\ \ x\ \ \  \ z\ \ \ \ %\ !\ \ \                   Ž ' v  x k Q  Ƹ  d  n  GB  )    F  i   c 1      T  7 N7 6  LJ "     W . -  } kC    g   \D n  P 4Q B 8F  1C M $N   7  % js r q q q nr W4 1 3 2  
     6   ^   z  M x p   & <  N    W       K  ,  ( L1 ! ) ' % $ % # ( # & " ( & $ " ) ~+ 0 f, , / * - * N0 + ^- U. * \/ i C u #  |   N      	      S   8  M B c H 4!  / 	   P  2
 h <  
  _ z  x   	  y     q  !      a  + ;     J  *   f    +    - 1 e  k  a     D $ p >    `      T U 5 	5 06 > b> < I< F: = : 8 G8 7 9 ; N N L G IM H dE (F D F EH K bJ &K I LT S tR Q P S =Q wO P !k k rj fm ;n l o p o _ |@ YB Z z? @ B @ A bA ZD C WC X T V ;V ~U W dX V` p [{ z Gy x v y ?w Bu t t u w e h h $g g s r q p n 8r ko bm l /l n p  r  ;   ȍ   n m z ɣ  ^ \  W # ~  ~ a | { @} f 4f k j Zj ֝ r  Q ٠ 5  H  ܂ *i i  ։ =    x  x Ȃ 9 8 E  g7 6 7                  , u Ҕ :  ږ 5    0 { ڕ             u ru )u ^ AZ lY ] \ [ [ d X` _ c b b ,a                             n\ ̽\ \ \ \ \ \ Y\ ]\  \ p\ ]\ έ\ \ ;\ \ h\ \ L\ #\ \ \ e\ :\ \ ȥ\ v\ \ \ x\ 9\ \ \ e\ \ \ ,\ \ \ °\ \ \ !\ g\ Է\ !\ c\ ״\ b\ 6\ t\ u\ \ $\ \ \ L\ \ w\ )U\ U\ C\ \ \ [\ jV\ \ r\ N[ \ Q[ tQ[ |\ S[ \ T[ T[ KU[ U[ ;m[ 6Y\ Y\ Z\ 7[\ h/\ _\ `\ pa\ @2\ 2\ f3\ 4\ 4\ 5\ 6\ 7\ 8\ 9\ :\ ];\ [\ \ g\ *v\ B\ `\ \ x\ \ \  \ z\ \ \ \ %\ !\ \ \ \ \ \ \                      / v  x  Q   >  Ԗ   o  GB 7 w8 T< 8 9 : {; = 5= > ? @ S@ A N6 7 N7 6 I LJ uM J L IK K WL kC aE >G D \D E I 4Q UI B jH H H iN 8F F 1C M $N nO N P O )P js r q q q nr -G ?; ? > > > = < &< j? = ; f@ F 4D DC C PB E A SA /F D B @ : i8 M9 9 N: 8 7 b T E[ X W FX V BZ RV U Z 8Y OW ^U [ ?b _ ^ 7_ ] :a 7] \ a /` :^ =\ 1 <T Q 2 &3 /2 S R S Q / F1 0 a0 T U U IV V W X X X i Di h ac h d ca b ` b c gg e f @e t Ot s r s q r !k k rj fm ;n l o p o _ ] ^ +\ Z )[ \ [ n] ] _ Y_ V` p  m  G _           " (   $  ތ  L {    E %  h ǰ  
      _ Q ɣ   \  u # ԛ  3 a  ۗ > '  8  ֝ r   ٠ 5  H  ܂ &   $   E T    |    > Z jY Y p 3c e j Sf e i d 3g d i h se f g c j -p dl 6o k Nm mk o n l m j sT G L 6I K H  J _H )L YK I cJ G M N S <P O S hN  Q M }S R XO P Q ~M [                             (t {t t rv v &w R  6  Ju u v             u ru )u A{ v 7v hz y x w ΀ | {  ( C~ `}                                w B    d -    Q   n  9! \( )) ) * + ], " " # e$ 0% % & ' B  n (  g  ֣  F      O     Z +    o @   C ʿ    n (   V      b    L   k     ? *- - . p/ 20 0 >  d    H   c    ?   1 z2 >3 4 4 5 B   s .   _    Q    E   Z  , Ѫ v  ¬ h    q   R   } (   M    r ) 6  p +   \  	 a
    E     | 9   p -   h '   d #  Q 6    F   >                   y\ \n\ r\ p\ \ d\ nk\ |j\ uc\ h\ ~i\ m\ \ \ Ԃ\ X\ b\ 2g\ f\ v\ [y\ w\ Tx\ x\ |\ d}\ Qz\ m{\ |\ z\ ~\ ~\ o\ n\ 'p\ s\ Vs\ Kt\ q\ ^q\ Zr\ 0\ |~\ t\ u\ u\ \ 0\ ,\ \ \ \ L\ \ w\ )U\ U\ C\ \ \ [\ jV\ \ r\ N[ \ Q[ tQ[ |\ S[ \ T[ T[ KU[ U[ ;m[ 6Y\ Y\ Z\ 7[\ h/\ _\ `\ pa\ @2\ 2\ f3\ 4\ 4\ 5\ 6\ 7\ 8\ 9\ :\ ];\ [\ \ g\ *v\ ~\ ̗\ Ƌ\ ،\ e\ kl\ m\ d\ \ b\ \ \ \ \ \ %\ !\ \ +\      yt s  6   ق L O   Q s ^    \  }   ; ْ w     	 C  P (   D        t v x u u v y  y  *z w x  `  ){ z  @ js r q q q nr -G ?; ? > > > = < &< j? = ; f@ F 4D DC C PB E A SA /F D B @ : i8 M9 9 N: 8 7 b T E[ X W FX V BZ RV U Z 8Y OW ^U [ ?b _ ^ 7_ ] :a 7] \ a /` :^ =\ 1 4 3 2 &3 /2 / F1 0 a0 7 6 Y6 5 4  [  ׿ 6 S    ! /   \ h    8 ϡ     4    ^ N     E h   ^  D  m ŷ  E     C     I }   -     % F   c   N x ~y |z y   \ +  } } ~     : n   U  t ] |  } F /}  { ~ e| ~ D | 1| { 8 ؁   4  e    - F{ {   K #        f p 3c e j Sf e i d 3g d i h se f g c j -p dl 6o k Nm mk o n l m j # sT G L 6I K H  J _H )L YK I cJ G M N S <P O S hN  Q M }S R XO P Q ~M (t {t t rv v &w w w cx s Ju u v              g !   & H t    w     4                                   P     R $  8  Z   ,  d    | .   D     Z  R	 
 
 t *     p "   8  L   n $   F * b+ , , T- - . F/ ,  r   ]   t   &  E  |   P   a     8  t   N   d    4  <    d! " " # D$  P   l     $ % l& $' ' ( L) * L   ;   .  =\ 5?\ :>\ ^A\ <\ ^\ ^\ =\ l\\ \\ \ L\ \ w\ )U\ U\ C\ \ \ [\ jV\ \ r\ N[ \ Q[ tQ[ |\ S[ \ T[ T[ KU[ U[ D\ F\ \ O\ X\ d\ o\ y\ \ H\ J\ NK\ M\ .P\ Q\ (\ ])\ ;m[ W\ ,X\ ,\ 6Y\ Y\ Z\ 7[\ h/\ /\ 0\ 1\ @2\ 2\ f3\ 4\ 4\ 5\ 6\ 7\ 8\ 9\ :\ ];\ [\ %_\ iB\ r]\     [n r " V"   n# 
$ $ + P + , - w. ` U  ^ 8^ ^_ a ` g  0f d c j |m l k j Bi    u 8y 4 D4 =z w x v (9 7 t j 6  *8 { | 3 . i  -  A      >  Q; v9 = V@ @ |A     H  ) n* yY UX 8V W V Q R B  Y/ 0 / r r p /q q / n  Ao  o  " Sm n m ' Ak S( & g % I% i w o  d ap p *) _ x\ ] ,_ ?^ [ ] Z w[ c c _ }a b l` ` b g e ,e ff \ M L IN N "M K   D =C 6D KJ  I J tK I H XZ !Y Z [ Y }X g z E RO 
 O 
 XP  Q R P 
B M 2  F R VG G   R S 4 0 0T  S   wB B E DF 
 V U `W W %V T B   4   ] Hs &1 ,2 1 i     p r Gs 2 ap )r 3 s   D   1 ֋ {  ( ņ b                 =\ 5?\ :>\ ^A\ <\  T\ T\ =\ >\ ?\ \ C\ L\ \ w\ \ \ C\ \ \ [\ \ \ r\ N[ \ Q[ tQ[ |\ S[ \ T[ T[ KU[ U[ D\ F\ \ O\ X\ d\ o\ y\ \ H\ J\ NK\ M\ .P\ Q\ (\ ])\ ;m[ *\ +\ ,\ ,\ -\ ).\ .\ h/\ /\ 0\ 1\ @2\ 2\ f3\ 4\ 4\ 5\ 6\ 7\ 8\ 9\ :\ ];\ ;\ iB\           "Q P   @  p T P   , ` U     ) !   F     ^  m y   O 7    u 8y  } v =z w x v    t j ~}  { | . i  -  A             o     H  S S yY UX 8V W V Q R B  /   z    " Sm n m k Ak l j g "i xh i w o  d ap p q _ x\ ] ,_ ?^ [ ] Z w[ c c _ }a b l` ` b g e ,e ff    /     6 \  g z ~   
  
   	 * 	  M 2  R    4 0   N   K  (  c   B  - 
   = ?  B   4    i       I r Gs r  )r ,t s   D   1 ֋ {  ( ņ b                 =\ 5?\ :>\ ^A\ <\ =@\ A\ =\ >\ ?\ \ L\ \ w\ \ \ C\ \ \ [\ \ \ r\ N[ \ Q[ tQ[ |\ S[ \ T[ T[ KU[ U[ h\ +\ \ O\ X\ d\ o\ y\ \  \ 4!\ !\ #\ %\ &\ (\ ])\ ;m[ *\ +\ ,\ ,\ -\ ).\ .\ h/\ /\ 0\ 1\ @2\ 2\ f3\ 4\ 4\ 5\ 6\ 7\ 8\ 9\ :\ ];\ ;\ iB\               "Q P  Q T T  U Z   )  e  I   u 8y  } v =z w x v t ׄ t j ~}  { | . i  T 6 	 ޶ >    & ׬   4 ߱ #  @  e    8          M   S S yY UX 8V W V Q R  s /   z    " Sm n m k Ak l j g "i xh i w o  d ap p q _ x\ ] ,_ ?^ [ ] Z w[ c c _ }a b l` ` b g e ,e ff @  k  g z    9     _ Ӽ  ^   4   ` 
 B   4   i                       I r Gs r  )r ,t s   D   1 ֋ {  ( ņ b                 Y Y Y SY Y &Y Y Y [ w[ @[ F[ G[ 2H[ H[ I[ {J[ 1K[ K[ L[ aM[ N[ N[ GO[ O[ P[ Q[ tQ[ [ S[ B[ T[ T[ KU[ U[ ;m[ m[ [  \ m\ )\ \ \ >\ \ o\ 8\ \ \ q\ >	\ 	\ s
\ cY Y "Y [ [ [ [ 8[ [ [ [[ [ D[ F[ [ [ [ ^[ [ 
[ I[ [ {[ [ \[ [ [ 8[ [ d[ [ [ [ V[ [ [ c[ 1[ -[ [ [ [ [ [ [ [ [ z[ b[ I[ ,[ [ [ [ y[ M[ [ [ [ 2[ [ R[ [ o[ [ [ V[ [ J[ [ [ [ [  [ [ [ [ [ [ %[ p[ [ [ xY Y[ 3[     $ % _" a# <' ' ' M( ( ( 2) ) * m* * <+ + + , - C, - - . k. .          7   1       !                     T U )V + * W 3X X  Z ] ] _ Ta e b d e Bf g h j j Ik k ul q 1t Yy u w y }z !| } }~ <   I  4 ̠  1 : e  _  B C F   O WM   t  pM           T   Y      h" )# # $ D :E AF F G NH H I J XK L L DM BN  O @N N O P R U W Z \ &_ a ,d d |e Cf f g Y 
j m 4 o Fr (t ]p 56  v 7 w | } x W9 W; ڀ <  Ɖ  t > PA M &O |P  1C a   Ԓ D i  b     ^          1    k      a  1 $  (         Y Y Y SY Y &Y Y Y 2B[ C[ E[ F[ G[ 2H[ H[ I[ {J[ 1K[ K[ L[ aM[ N[ N[ GO[ O[ P[ Q[ tQ[ Q[ R[ S[ S[ T[ T[ KU[ U[ [V[ ,W[ X[ Y[ Z[ G\[ ][ ][ _[ T`[ %a[ b[ c[ dd[ f[ f[ g[ 3i[ i[ Cj[ k[ ;m[ m[ an[ p[ q[ hr[ :s[ t[ t[ Ou[ jv[ w[ Zx[ x[ y[ 3z[ h{[ |[ |[ }[ }[ '~[ ~[ [ T[ [ Á[ [ 2[ Ń[ \[ N[ [ [ [ G[ 	[ [ [ [ \[ [ /[ e[  [ K[ [ [ [ cY Y BY Y  Y h!Y {Y |Y }Y Y ̂Y Y Y bY lY Y +Y |Y [Y Y Y Y Y _Y dY ۷Y ٺY qY Y Y Y 7Y Y rY 	Y /Y MY Y Y Y Y Y Y %Y (Y Y Y Y @Y Y Y U Z JZ &Z WZ Z 
Z $Z OZ AZ Z "Z Z C Z d!Z ~"Z #Z $Z %Z &Z 'Z 1*Z ,Z .Z Y/Z 0Z 0Z 1Z 2Z 3Z g4Z 4Z 6Z P8Z K9Z 2;Z F<Z <Z =Z >Z ?Z 5@Z @Z AZ $BZ CZ +DZ DZ FZ HZ JZ LZ SNZ 2OZ PZ QZ eRZ )SZ SZ  UZ VZ /WZ WZ }XZ YZ ZZ ZZ [Z V\Z ]Z ]Z ^Z w_Z M`Z +aZ aZ bZ scZ  dZ dZ eZ fZ gZ hZ iZ iZ kZ 7lZ 1mZ 5nZ oZ pZ qZ (rZ rZ YsZ tZ duZ avZ xwZ ExZ xZ \yZ  {Z |Z ~Z ~Z Z ԀZ AZ Z Z vZ Z UZ Z Z &Z Z Z LZ Z ŊZ kZ Z -Z <Z PZ Z Z ˛Z Z WZ VZ Z ҪZ Z ZZ Z Z ;Z Z Z TZ Z Z BZ Z FZ Z Z Z Z Z Z JZ Z XZ Z >Z Z sZ Z Z Z Z Z 3[ q[ [ [ w[ [ -[ v[ F[ [ [  [ #[ '[ +[ d-[ .[ 0[ 2[ [5[ 7[ &;[ =[                         "Y ,#Y >%Y E)Y p,Y -Y U/Y 0Y 2Y Z3Y .5Y D6Y 7Y #9Y :Y ;Y c=Y >Y ?Y @Y 7AY YBY ICY DY DY aEY EY FY GY NHY &IY IY gJY JY @KY "LY <MY NY OY PY OQY MRY ]SY YTY cUY QVY MWY HXY ?YY ,ZY [Y 
\Y \Y ]Y ^Y |_Y 3`Y `Y aY AbY bY cY AdY dY eY (fY fY gY =hY hY hiY jY jY kY mY 1oY qY rY sY (uY vY xY xY yY $ % _" a# <' ' ' M( ( ( 2) ) * m* * <+ + + , - C, - - . k. .          7   1       !                     T yS V í W 2Y Y  H K F  \\ e^ "_ `  b {c f 1h fi o 3r 
s t v Yx { | LL L L        ) &    e      M , 7  )/ / 2 3 L5 6 8 9 9 ]< = ? @ A  ͨ     0 -  I   "  X   $  O    
 !             f 8            ? G   , u	 e
    %    " е    A  ; U    M   a  /  bD [E H }I J <L  # )       ?       L x	 
 e
 [      4 c      :  W   7      % #' ( 	) * D+ y, - . / 41 2 3 6 5 ]8 9 ; 3= > ? A 3B aC M # c% ' ( }* 0, - / D1 2 Xi     9! s"   -k sl w s8 8 z W: [  ?  gQ   n  [ j F D    a [  ͥ F L   q  ^  s    X           e   )  l    	 
 x      C    Z   U   RR                         T U )V + * W 3X X  Z ] ] _ Ta e b d e Bf g h j j Ik k ul q 1t Yy u w y }z !| } }~ <   I  4 ̠  1 : e  _  B C F   O WM   t  pM           T   Y      h" )# # $ D :E AF F G NH H I J XK L L DM BN  O @N N O P R U W Z \ &_ a ,d d |e Cf f g Y 
j m 4 o Fr (t ]p 56  v 7 w | } x W9 W; ڀ <  Ɖ  t > PA M &O |P  1C a   Ԓ D i  b     ^          1    k      a  1 $  (  E                              
Y Y Y 4Y Y AY aY !Y Y Y Y Y Y Y IY  2      3 c {          ?          Y Y :Y Y ;Y Y Y )Y Y Y vY VY /Y Y $Y (Y Y                               f  C   k  / "  o            $    R n  / , ;        x  ̳ C     % i   E  " ö s  a   H  ' Ĺ f   Ȟ 	   W  6 ӟ u  4   ֢ r  è d  ] ԥ  4 w   S    T J ͋  0 m     O  "  Y ݓ  $  8   ؐ r  Ò g   = ȕ  - f     \  )  \ f  E ę O     "     a t   K  + ͩ   R  . ʬ k   	  ,   ϯ l   R :    { h4 N 4 5 6 K6 5 O5 4 6 D8 8 8 7 7 G7 9O N KN B QD E D C C 3C oE F G PG F *F E I9 : <; : ?: 9 9 M M J vL FM L L K @K H I yJ J DI H sH ; < = K= < =< ; = `? @ ? ? > Q> o@ A B (B wA A @ O j O (Q Q Q P zP %P 3R S >T S 5S R R ?k j Hj }^  ` ` c` _ :_ ^ 'a b |c c Pb a a T U V BV U =U T i i f dh :i h g g %g c e Xf e e d Cd V aX Y X X W LW vY Z [ C[ Z )Z Y [ h] "^ ] ] \ S\  x3    p  w &  c     i 4 3 -3 ' M) * ) ( ( 2( h* + , D, + !+ * e  R   X   2 2 / ]1 +2 1 0 0 *0 - . e/ . 3. - d-   " " [" ! P!   # j$ % $ $ # ^# v% & ' *' {& & % Cu ~ u v w Pw v ?v u x sy /z y y x ax ~ ]~ } z { | K| { :{ z [} } o A  ͈ h   X  )  (    T    - p  z H ߆   M    k >t k @m m m l l 4l Tn o qp p _o o n t t s p -r r r q yq !q s As e  .<    !!  !  ~!     g      >"  #  m$  $  R#  "  "  <  <  ;  Z/  0  1  ^1  0  #0  /  .2  3  4  <4  i3  2  2  $  8&  &  &  %  ~%  #%  ~;  (;  8  9  :  H:  i9  8  8  5  6  7  <7  ]6  5  z5  U'  (  )  ;)  x(  (  '  )  +  N,  +  %+  *  \*  ,  3.  .  .  -  m-  -  Z  mx  [  \  U]  \  4\  [  s[  ]  2_  _  _  ^  p^  ^  'y  x  x  <k  l  m  Om  zl  l  k  %n  o  p  Bp  io  n  n  [`  a  b  2b  ua  a  `  w  ^w  =t  v  v  xv  u  u  t  q  r  s  Ws  rr  q  q  b  d  Se  d  $d  c  Wc  e  Jg  h  g  f  |f  f  }h  j  j  rj  i  @i  h     H  c       D             [    1    j            d        @      g        9    ?        {      3        I  `    s          1    D  k  
  
  j
  	  2	    8      <  m          s    >    m    -  N  Փ    9  t          `    0  ȕ  e      ѧ    7      ʛ  W      D  (    ՞  `    Ǘ  N          $  o    գ      $  7    F    o  _        	  y  Đ  y  |{  R|  {  {  z  Cz  |  \~  4  ~  }  }   }    (  c  |  G  1    Ճ  ]      w  e            ;      Հ  i        :  %        +    ڈ  Ŋ    B  K  ˉ  P  r        c        ;      h        ;    $  U        1  @    K  #  
                h        @                  z  |  {        w    <=  Y  =  >  ?  O?  >  ;>  =  @  xA  6B  A  A  @  c@  mZ  Z  gY  M  N  mO  O  8N  M  gM  O  rQ  FR  Q  Q  P  6P  B  C  D  XD  C  DC  B  Y  X  U  jW  JX  W  V  V  V  R  eT  EU  T  S  S  S  E  F  YG  F  6F  E  qE  G  <I  J  I  H  vH  H  cJ  K  L  DL  K  K  J  P  R    *      ʪ  d    Y      D              ı  w  U        ,  ´  }  _        ,      _    5  ϯ  n    :    ׼  Ž  N  c    t  η        -    >    U M      e        E      b        )   	 l ^  
 z
 
    3 @  I D      \                  ' " $      <    r     V     5  w :  	   T      J    a    R             {    j      <    p      e    3    /      .  a      7    N    ?      =        ~    7    Z          @    c    !        a    ?    |    \        R          4  н   n   ſ   k y   ( {     /   F      m   ]  .   1     . 9      B  k %   3 `   <  a  M    +    o  C  h  T              perf event selector list object.                                perf event selector list object.                perf counts values object.                      perf Performance Monitoring Unit (PMU) object.  thread map object.              cpu map object. perf context_switch event object.               perf sample event object.       perf read event object.         perf lost event object.         perf throttle event object.     perf comm event object.                         perf task (fork/exit) event object.             perf mmap event object. ;d    q  8r  8r  r  ,r  @r  _r( ir sr, }r  rp r 7rh cr mr wr r r  r r0[ Xr\ rc rL r r8 rL r rP r r &r@ /r, 9r| Cr Mr Xr4" r" rs rs r{ r r  r  r0 8r( Arخ  r  r  r8  crX  rx  Pr  r  /rد  cr  r  ~r8  rX  rx  r  )r  grܰ  r  r  r<  r\  Ur|  jr  r  rܱ  r  r  Br<  r\  r|  r  r  3rܲ  nr  r  r<  r\  !r|  6r  Vr  rܳ  [r  r  r@  r`  r  r  rĴ  ~ s  Bs  ps$  sD  sd  ts  :s  sĵ  ,s  Zs  s$  sD  Rsd  
	s  	s  
sĶ  Q
s  
s  
s$  
sD  [sd  zs  s  sķ  Ws  s  s$  sD  Ksd  /s  ps  sȸ  hs  (s  s0  sP  sx  s  s  s  Hs  s,  (sX  xs|  s  ( s  h s   s   !s   H!s@  !sd  H"s  "s  (#s̻  #s  #s  $s<  h'sh  )s  H*sļ  *s  *s  +s4  +sT  X,sx  X-s  -sȽ  -s  x.s  8/s0  0sT  x0sx  0s  1sȾ  2s  2s  3sD  (7st  7s  9s̿  ;s  ;s   8<sD  @st  @s  As  Bs  XCs   HDsH  8Esx  xEs  Es  Es  Fs  HGs$  GsD  Hsh  Is  XJs  Js  Ks   (Ls(  xLsH  (Msl  xMs  Qs  Qs  Rs  Ss0  xSsX  Ts  hTs  Ts  Us  hUs  (Vs8  Wsh  ]s  ^s  8_s  _s,  _sL  `st  as  js  8ks  ks8  ls\  xls  ms  ms  ms  ns  ns@  hosl  os  ps  ps  hqs  8ss4  ssT  us  xvs  vs  ws  ws$  wsD  (xsd  xs  xys  zs  zs  H{s0  }sx  (~s  ~s  hs  s  s  sL  s  Xs  xs  s  s,  sH  xs  hs  ȉs   ؊s`  s  8s0  Xs  Ȑs  s  s  s4  (sH  8s\  Hs  Xs  s  s  sH  sl  8s  xs  ؞s  s(  sD  جsh  Ȯs  s  s(  (s<  s  s  (s  s8  s  s  s  s  hs  s8  sT  Hs  s  s  s  s  Ss8  sX  sx  s  	s  Hs  xs  s  s8  sX  sx  s  s  "s  s  s  s8  sX  sx  <s  ]s  ~s  s  s  s8  sX  #sx  ls  s  s  s  s  s8  2sX  Ssx  s  s  s  #s  5s  Gs<  Ys\  s|  s   s  ]s  os  s  s<  s\  s|  s  s  s  ;s  ss  s<  5s\  Vs|  ts  s  s  s   s   s@  Ss`  s  s  s  *s  Is   js   vs@  1s`  ?s  Qs  `s  os  s   4s   s@  rs`  s  s  s  3s  s   Gs   s@  s`  s  @s  s  7s  s   ut   It@  t`  t  
t  
t  t  Ht   mt   t@  t`  t  lt  t  Vt  Yt   t   t@  t`  t  `t  t  	t  Vt   9t   t@  1t`  	"t  #t  e%t  L&t  &t   b't   )t@  )t`  +t  ,t  H-t  .t  $=t   =t   =t@  :At`  At  Gt  It  Lt  rMt  Mt$  NtD  Otd  <Tt  Tt  Tt  Xt  BXt  p[t,  +\tL  \tl  \t  ]t  ^t  bt  mct  ct,  zdtL  etl  et  oft  6gt  gt  gt  	ht<  it\  it|  Jtt  tt  !ut  Avt  wt  yt<  yt\  `zt|  {t  t  It  ܈t  $t  Et<  t\  t|  t  t  t  xt  4t  t<  t\  t|  Nt  t  t  &t  ;t  |t<  t\  :t  #t  t  t  dt   Dt$  :tD  Ltd  t  t  't  .t  t  t(  (tH  ?tl  t  t  /t  mt  t  t,  [tL  tl  ft  t  rt  
t  t  t0  tP  tp  )t  t  ?t  t  t  >t0  tP  tp  t  t  t  t  t  t0  ;tP  tp  +t  t  u  u  	u  &
u8  uX  ux  u  5u  u  u  u  u8  ' uX  !ux  "u  L#u  5(u  (u  (u  X)u8  *uX  <+ux  ,u  X.u  .u  /u  2u  -5u<  =6u\  :u|  ;u  H<u  <u  >u  ?u  Bu<  9Bu\  aBu|  Cu  fDu  Eu  YFu  eIu   KuD  |Kud  Ku  Ku  Ku  Mu  Ou  QQu$  RuD   Sud  kSu  aUu  0Yu  YYu  |Yu  Yu$  YuD  Zud  HZu  [u  7\u  \u  \u  ]u$  #]uD  9]ud  O]u  ]u  ]u  ]u  ]u  ]u$  ^uD  _ud   _u  _u  _u  _u  `u  O`u$  d`uD  `ud  `u  Xau  au  au  au au$ EduD  fuh gu gu %iu iu (ju Xju, juL jul ^ku ou pu Hqu qu [ru, 2tuL vul wu xu yu yu yu yu, %zuL :zul zzu zu zu zu .{u C{u, {uL {ul ~u u u @u u u0 uP ʁup 
u ҂u ju u u u0 RuP Fup wu u u u iu ފu0 JuP ut 5u Lu  u u +u	 Ru4	 >uT	 rut	 u	 9u	 u	 Zu	 u
 u4
 uT
 <ut
 ku
 u
 ɘu
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 ̜u u4 ;uT ^ut u u ǝu u !u vu@ %ud ru u ȣu u u u$ uD ud ܮu "u Du wu úu Լu$ 0uD "ud u u u u u u0 !uP 2up <u u u u u u0 4uP ,up u u u u u &u0 uP 8up [u u u u u Ou0 uP up u u u Mu u u0 uP - vp Pv Pv v v v 	v0 
vP jvp bv 'v }v v v sv0 vP `vp wv v cv v v v0 UvP !vp `#v X%v J&v 'v (v +v4 +vT ,vt /v 0v 1v 1v 1v _2v8 2vX 2vx 2v Y3v g3v 3v 3v 4v8 5vX 5vx 6v \:v 
;v `Dv KEv !Fv8 GvX Gvx Hv Iv TJv *Kv Kv Mv8 NvX \Nvx Nv Ov iPv Pv Pv Rv8 RvX Uvx ^Wv Wv Wv gv Mhv jv8 'kvX mvx 6ov \sv  tv Ktv vtv tv8 tvX uvx vv wv >wv xv xv yv8 yvX zvx zv ${v R{v {v |v  j}v8  vX  vx  v  v  لv  v  -v! ?v8! VvX! vx! ؇v! v! Nv! av! v" v<" Zv\" lv|" zv" v" v" v" v# v<# v\# 3v|# Tv# uv# v# эv# v$ v<$ 4v\$ }v|$ v$ v$ v$ v$ /v% Av<% Sv\% ev|% v% ԏv% v% v% 
v& v<& v\& ݐv|& }v& v& v& v& v' v<' v`' Dv' v' v' v' fv ( v ( v@( v`( v( v( mv( v( v) Tv() vH)  vh) Bv) v) ٧v) v) dv* v(* ֩vH* !vh* lv* v* v* v* nv+ v(+ vH+ vh+ ?v+ v+ v+ ˲v+ v, v(, GvH, xvh, v, v, ϶v, v, v- ޸v(- vH- Lvh- v- v- v- *v- `v. bv(. vH. vh. Pv. v. v. Cv. ^v/ v(/ vH/ vh/ v/ v/ v/ v/ 3v0 v,0 vP0 vp0 v0 uv0 Rv0 v0 v1 v01 VvT1 vt1 v1 hv1 v1 *v1 v2 v42 vT2 vt2 v2 
v2 v2 #v2 Tv3 v43 vX3  vx3 7v3 v3 @v3 v3 v4 v<4 v\4 Ov|4 v4 v4 +v4 v4 v5 v<5 cv\5 Mv|5 v5 v5 v5 ,v5 ov6 ;v<6 5v\6 `v|6 Rv6  w6  w6 w 7 zw 7 w@7 w`7 w7 bw7 w7 w7 w 8 Jw 8 w@8 w`8 	w8 '	w8 w8 w8 w 9 w 9 Mw@9 w`9 	w9 Lw9 w9 w9 w : w : Ow@: w`: w: w: 'w: w: ew ; w ; ^wD; wd; w; Vw; Uw; 
w; lw< w(< wH<  wh<  w< &w< -w< .w< .w= /w8= f1w\= 1w|= 8w= h9w= q:w= ;w > <w > Z?w@> ?w`> Aw>  Dw> sDw> Ew> NHw ? Jw ? Mw@? Nw`? ^Qw? tQw? Qw? Rw? Rw@ Ww$@ WwD@ Xwd@ $Xw@ EXw@ ]Xw@ Yw@ `wA `w(A .awHA mwlA 0pwA hpwA qwA *qwA <qwB Yqw,B vqwLB qwlB qwB qwB qwB rwB swC Fsw0C twPC twpC 	uwC fuwC OxwC GywC ywD zw0D |wPD Z}wpD }wD ^~wD wD wD =wE w0E wPE wpE IwE wE wE +wE SwF ݊w0F wPF wtF wF wF UwF wF wG [w@G 
w`G qwG wG NwG wG =w H -w H w@H ڧw`H wH wH wH wH zw I w I xw@I w`I ĸwI  wI -wI [wI ɹw J "w J w@J #w`J 9wJ OwJ wJ wJ սwK w(K wLK wpK wK wK "wK 9wK JwL aw0L wPL wpL wL wL  wL AwL wM w0M wPM wpM wM 
wM wM PwM bwN w0N  wPN 2wpN DwN VwN wN wN wO w0O gwPO wpO wO wO wO 7wO `wP Cw0P wPP wpP wP }wP TwP wP wQ w0Q wPQ wpQ wQ wQ wQ TwQ wR Aw8R w\R w|R wR RwR wR wR wS w<S w\S Xw|S wS wS wS [wS w T w@T w`T @wT mwT wT 5wT } x U x U xDU yxdU xU xU 	xU xU xV x0V xTV xxV xV (xV gxV x W x W  x@W 
#x`W #xW #xW [$xW }$xW %x X *x X *x@X +x`X +xX ?1xX 1xX 2xX q3x Y 3x Y 3x@Y 4x`Y 5xY 5xY 5xY 5xY N6x Z q6x Z 6x@Z K7x`Z y:xZ ;xZ <xZ H<xZ w<x [ ?x [ @x@[ Ax`[ Ax[ Ax[ Ax[ <Bx[ xBx \ Bx \ oDx@\ Dx`\ Dx\ Dx\ 6Ex\ Ex\ Fx ] Fx ] Gx@] #Gx`] 4Gx] KGx] lGx] Gx] Gx ^ Gx ^ Gx@^ Hx`^ #Hx^ 5Hx^ GHx^ YHx^ kHx _ Hx _ Ix@_ #Ix`_ [Ix_ Ix_ Jx_ Jx_ Jx ` Kx ` }Lx@` Nx`` Ox` Qx` 8Rx` Wx` pYx a rZx a Y[x@a 2]x`a d]xa ^xa _xa fxa jx b ]nx b Qrx@b rx`b rxb 0txb txb vxb Dwx c Vxx c xx@c !yx`c ryxc {xc |xc a|xc x~x d x d 3x@d x`d `xd xd ̎xd xd xe xx$e  xDe xde xe xe Pxe xe Axf Ux$f nxDf ئxdf xf 9xf xf xf Ӻxg Ծx$g xDg 2xdg Dxg Rxg cxg xg Qxh x$h xDh Jxdh xh xh xh xh  xi ax$i xPi xpi xi |xi xi xi x j xDj rxpj xj xj ;xj Xxk Hx,k HxXk (xxk xk xk wxk #x l x$l IxDl =xdl xl xl xl 5xl x(m xHm xhm Sxm 9xm wym yn *y8n PyXn E
yn 
yn 7yn yn yo Ky(o 3yHo yto yo  yo 1"yo H"y p Y"y p p"y@p "y`p "yp "yp #yp /#yp P#y q #y q #yDq $ydq #$yq 5$yq G$yq Y$yq $yr $y$r  %yDr ]%ydr o%yr %yr %yr $&yr 'ys 'y(s 'yHs 'yhs =+ys 1ys 3ys 6ys ;yt ZAy,t DByLt 8Cylt zFyt Fyt RGyt Gyt Myu "Ty4u [yXu _\yxu ]yu <_yu ]dyu kdyu ydyv dy<v dy\v Pey|v eyv eyv .fyv Igyv gyw iy<w Ejy\w jy|w lyw qyw }qyw qyw s|y x ~yDx a~ydx ~yx ~yx yx yx yy y(y yHy yhy yy 9yy Ayy ͕yy Jyz y(z җyHz ;yhz yz ͛yz yz yz ͟y{ y({ yH{ yh{ y{ y{ Iy{ y{ ɬy| 7y,| yL| yl| y| qy| ay| ۵y| y} ?y,} yL} yl} 2y} y} y} y} y~ 9y,~ yL~ yl~ #y~ 2y~ y~ y~ y |y, yL yl y Ey y y y y, yL .yl y dy ỳ y y y0 yT yx y yȁ Hy y (y0 hyP yp y (y hyЂ y y y< Hy\ y Xy yȃ xy y XyD yh y xy yЄ Xy y y0 yP Xyp y y yЅ Xy y y0  zP X zp  z  z 8zІ z hz z8 z\ 	z 	z 
z؇ Hz z, z\ z z zȈ !z %z *z4 .zX 2z| 6z :zĉ >z >z 8?z4 ?zT ?zt (@z x@z @zԊ Az hAz Az4 BzT XBzt Bz Bz HCzԋ Cz Cz 8Dz4 Dz\ (Ez| xEz Ez Fz܌ Gz 8Hz, HzL Hzl (Iz xIz Iz̍ Jz hJz Jz, KzL 8Mz| Mz Mz HNz܎ Qz Sz< Tzh Uz Wz (Xz Xz YzD Zzp X[z ]zȐ (_z (`z( hbzX Xez hz mz (tz hzH 8z| z zܒ (z Xz< z` z z zؓ بz (z xzL zl z z 8zܔ z z, zL Hzl z z z z Xz( ȲzL 8z| z zЖ z z zD zp z z z Xz z@ zt z zĘ z Xz z$ zD zh (z hz z̙ z z@ (zl z z z xz xzH Hzx z z  zL Xz| Hz zԜ 8z  zP z| Xz xzН 
{  
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~h 
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! H" 4" H\" " h" (" X # ,# P# p# 8# x# # H$ 4$ X$ $ h$ $ % h,% T% t% X% 8% x%  & #0& X#X& #x& h$& X%& '& 0' (5L' 89|' 9' =' A ( B0( CX( (D|( (J( xJ( J( J) 8K$) KL) Kl) HL) hQ) Q) R* XS8* Sd* XV* 8W* W* X + \,+ Ha\+ a|+ b+ c+ Hd+ d, f<, 8g`, g, hi, k, Xk- k,- HlL- hmx- n- 8p- xq. rD. hsh. s. Xt. t. t. u/ w</ Xw\/ (y/ y/ z/ xz/ {0 h{<0 8|d0 |0 }0 (0 1 H,1 L1 ؀l1 1 1 ؃1 H2 腀@2 ht2 82 ؈2 (2 3 ,3 T3 x3 ،3 ؍3 4 菀84 h4 ؐ4 84 4 ؑ4 85 05 \5 ȓ|5 5 蔀5 ȕ5 ȗ,6 L6 Hl6 6 86 6 (7 47 h\7 7 7 x7 7 (,8 ت\8 (8 x8 8 x8  9 @9 Ȯ`9 9 H9 9 H9 X: (L: p: h: غ: 8: ؿ0; P; ; ; h؀; ؀< xـ8< ـX< ߀< < X< < X = D= l= 8= x= = X= > <> d> > X> x> (? 0? HT? x? ? ? h? x@ 4@ h`@ @ X@ (@ @ X0A `A A A HA B x0B PB X|B HB B B ((C !XC "C #C x#C #C '$D X'DD 'dD 'D *D X+D (-E -4E H.XE .|E /E /E 80E 0F 0,F 3dF 3F 84F 4F 4F X5G 50G 5PG H6pG 6G X7G 8G H9H x:DH x;pH <H 8>H x?H H@(I AXI XBI BI (DI 8EI HG0J GPJ hHtJ IJ xJJ JJ LK XOHK OhK XUK WK WK XL Y<L h[`L xaL bL 8cL cM d0M dXM dM heM (gM iN 8l8N xnhN oN qN sN HvO w,O z\O (~O O O XP HDP 薁tP XP XP Q 8Q XQ XxQ Q ئQ XQ R 訁<R ȩhR ȪR hR R ȭS X8S xdS S hS ȹS T 8T hT T HT T (U 8XU |U XÁU āU āU 8Ɓ$V XȁPV Xˁ|V ́V ́V ΁V hρW ρ<W XЁdW ҁW (ՁW ؁W hہ X ܁DX H܁dX ܁X ݁X ߁X Y (,Y XY Y Y Y HY h,Z TZ Z Z Z  [ (P[ h|[ [ [ 8[   \  H\ x\ h\ 8\ 0] h] ] ] (] ^ #<^ X#\^ #|^ ($^ 8%^ 8'^ x'_ (@_ H)l_ *_ +_ (-_ -` 3@` H4h` 4` 7` X8` 8a h94a 9\a :a h;a (<a <b 8=(b 8>Xb 8?b H@b Ab HDc KLc 8Mc xMc Mc hNd O$d XPLd (Qpd Qd HSd 8Td (U e U(e hVLe Vpe XWe XYe Ye 8Zf Z,f [Lf H[lf X\f \f \f 8]f ]$g ^Pg `g eg eg fg g(h jXh hlh (uh hh i ,i Pi xi hi Ȑi i Xj Hj pj hj hj j k 8@k ؚhk 8k k xk l X(l ȞLl (ll l 蟂l xl  m ,m (Tm htm m m m 訂(n (Hn ȩpn n 誂n (n ثo X8o \o |o ho 豂o p 0p x`p p xp p p ظ$q Tq q q q (q hr 轂@r H`r (r r 迂r ւr (؂8s ؂`s ڂs (ۂs ۂs ܂s X܂t (Tt ht t xt `u u (u hu u 8v Hv Xtv v hv v v H w Hw hw xw w Xw x (0x Tx xx (x x Hx H y  Dy hhy y y y 8y z 4z hTz xz Hz z z X{ 4{ T{ H|{ H{ x{ | 4| 8d| | | H| | $} H} |} (} } } 8~ (@~ x~ x~ ~ 8 ~ " #@ $h 8% h( h) h* X.D .h (/ h/ /̀ 0 1 1< 1\ (2 x2 2ā 83 3 4, X4L 4l 4 5 6܂ 6 7 :P 8<| = >Ѓ @ 8A  AH XBp B C hD E XE0 G` J K xK K xL0 MX O QȆ 8S S Xl Y (Zȇ ^ _ h`D `d a a i؈ p, (r\ r| t t u 8v( xX y | ~ (  $ T x x (ȋ h  H4 Ȕ\ h ȕ x، h 蚃0 (P   ؝č  X $ ؞D d X  ؟Ď  X $ ؠD d X  ءď  X $ آD d X  أĐ  X $ ؤD d X  إđ  X $ ئD d X  اĒ  X $ D xd 詃 H ԓ (  4 xT 讃t X  (ܔ  $ 8D hh   ̕ h  0 T  8 x  ( hăX X҃ HԃЗ Ճ ׃  ׃D ؃h ك 8ڃ ۃ x܃ 8 X   Xę  H @ (p x ( hԚ    @ (` h   h  X4 (\ h|  Ԝ ( ( H xl    hD t  X ؞  8 @ l  8 ğ (  D Hl  h   @ hp  	С   , T x  (Ģ h  h8 xh  ģ   L l  ̤  8 D p 8 8 Х x! H"( "L X#x # H$ $ئ $ H% %8 %X &x H& & &ا H' ' '8 (X H(x ( )Ĩ ) * H*$ *D +t , -ȩ - . 0X T HV 8Wت X HY( ([L h[l \ \ ] c$ XdL |  膄 ؇ X ؉L X|  Hȭ  h Ȏ< \   萄Ȯ ؒ X h< (`  薄 H̯ h $ 蚄H 8h ț ؞İ ȟ H$ P x 8 б  h, P 8x  xв h H x h 资 x h 跄0 \ ( x (ÄԴ ń HƄ, Ǆh Є Є Hׄ ؄( ۄT x܄| ܄ ̶݄ (  0 ` X  hط h 0 \   Ը  h$ L |  X x  8 xh ( ĺ   , (L x H  ػ X	 	 H
8 
X 
x H  ؼ  H 8 X Hx   ؽ H  8 X   (ܾ h H l X H  h H( H 8t   8 , 2< 5l 7 > > H? HK@ K` K xL N HN xO$ PP Pp 8Q V V  W  hW@ W` Z x` b c HoL ol p r s x  {p X} ~ h ȃ< \ H|   膅 ( x, L hx    ` H  藅  , ؚL (l  H  蝅   (X ( ( 8  , h`  8   8Å8 ƅh x˅ ԅ hׅ م< ۅh ݅ h X  h@ Xp  (  H hH l H   (     4 HT t   8 $ xT     (, \  ( (  $ 8L p     h@ `  ! # $ X-4 -T -t h. . / H/ / /8 0X X0x 0 0 (1 1 (2  2D 2h X3 3 X4 4 5 H58 5X 5| X6 6 6 h7 7, 8L 8p 9 9 9 X: : ;D x<t < (= = = H> >4 >T H?t ? 8@ @ @ 8A A8 AX HBx (C C hD D E@ E` HF 8G G H H  ID xId hJ J K M  N0 HO\ O P Q 8R  xR  (S@ Sl T V (W W (X@ Xl (Y Y Z Z [H h\l ] h] 8^ ` c0 XcP 8d d e hf  h$ jL Xjl j Xk k xl  l$ XmH ml n p 8q xq q( hsX 8t 8v v w w( hxP xt xy z z H{  {  |D }h   H X h, T Hx X h 8  < ` 茆  ( x L  ș $ H 螆p  (  衆 H( L p 裆 (  8 4 X h| Ȧ (  视 H0 T x ȩ  x  H8 (\  X x hĆ$ (ƆH hƆh X҆ ҆ 8Ն xՆ Ն, ՆL چ| Hۆ ۆ ܆ ݆ ݆4 ކd ߆    H, L h| H      X@ l 8   ($ P Hx  ( x  X0 T X   	 X
 
4 d    8 <  h (! ! % (( (0 (P H)p ) * * , x-0 .` / 0 1 2  (3@ h3` 3 X4 85 5 60 6P 87p 8 (; ; >0 ?\ @| XA A F HG  G@  xHh  H  HI  I  K  hL L@ 8M` xM M xN N P (RL Rl R S S T U( XUH Up V (W W X Z8 Z` [ ] ] ^ 8_ _@ dt hd d e Xe e e4 HfT ft 8i xk k m( nH nh (o xo p q  (r( rP sx 8t t 8u u	 Xv<	 wd	 w	 x	 xy	 (~
 @
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  x8 d X H H  4 X H  X  0 h` x Ț 8 ț h< Ȟh (    8 8` x   x إ H4 T x 8 x    X( P x ة X   4 H` Ȱ  X ر X < ز\  س x ش h < h  8  0 ȼ\  Ç Ƈ (ȇ ȇ@ (ɇd ʇ ͇ 8· Ӈ ԇD Շh XՇ և ׇ ؇ ڇ< ڇ` ۇ 8އ h    8  \    8 8 	h 
 8 x  ( 8 H x h   " H# $ %@ ('p h( ) * H,( -T . 0 X0 0 0 10 1T 2x 2 3 5 h7  8<  9d  =  H>  ?  ?! x@<! (Bh! HD! HE! E! E" GX" xGx" (H" I" I# J@# (K`# K# P# (Q# Q$ HT4$ U`$ xY$ Z$ |$ X}% @% 聈l% % % % x$& 8\& Ȗ& (& 8& x' X4' hd' ؤ' ' x' ( 8D( t( ( 諈( ( ) 0) ȷ`) ) x) ع) * h@* Hp* * 8* h* (+ 8ÈT+ ň+ Ȉ+ ʈ+ ˈ, H͈@, xΈh, , H, , 8- @- p- x	- 	- 
- 
. x@. l. (. . h. / 0/ X/ x|/ / / / 80 <0 l0 0 0 0 h1 (1 H1 Hp1 1 1 1 2 x"@2 $l2 x%2 x'2 h+2 , 3 H.P3 (0x3 h23 33 73 8(4 8P4 K4 K4 L4 8M 5 xM 5 M@5 N`5 HN5 N5 N5 O5 XO 6 Q,6 RX6 xU6 V6 X6 X7 hY47 Zd7 [7 [7 H]7 ^ 8 _D8 x_p8 8`8 `8 `8 a8 a 9 HbH9 c9 d9 f,: f\: hg: g: g: 8h: xh; h,; iP; j|; Hj; j; j; k < Xk < xlP< 8mt< xm< n< hn< n= 8p<= xp\= p|= p= q= q= 8r> xr,> rL> rl> Xs> s> t> Xu> u ? v@? Xv`? v? v? Xw? w? w@ x0@ 8yX@ y@ 8z@ z@ {@ H}(A }HA }hA ~A A XA A ؀ B PB pB B B B ؆ C xPC xC XC C D 4D HdD D D hD D ȕ E HE ȖhE 藉E 8E xE ؙE H$F LF tF hF țF (F G DG HlG XG G ȦH $H xLH pH ةH H H I (8I خ`I XI ȯI I I 8J HJ صtJ J xJ xJ ȸK DK hK (K (K hK L HÉ(L ÉTL 8ĉtL ĉL ŉL HŉL ŉL XƉ,M ƉLM ƉlM ȉM hɉM ɉM hʉN ʉ4N Hˉ`N ΉN ։N x։N ։O H׉8O ׉`O ؉O h؉O ډO ډ P Hۉ$P HP 8P P P  Q 8 Q LQ hlQ Q hQ Q  R h R @R `R R R R S (S XPS tS hS S 	 T H(T XLT xT T hT H!T "U 'TU H*|U h/U (7U h= V C0V ^pV bV XbV cV hc W 80W 8`W XW W 蓊W xW X <X `X X ؚX ȞX HX Y h<Y \Y |Y hY Y hY xZ x<Z xlZ Z 8Z 8Z [ (8[ h[ h[ [ [ HĊ\ ƊH\ Ȋx\ HɊ\ ʊ\ h͊\ Ί] ъL] ӊp] H܊] ފ]  ^ ,^ X^ H^ ^ ^ _ 4_ `_ _ _ H_ ` @` Xp` ` !` H%a 8I0a IPa (J|a Ja Ma XNb O,b W\b Xb Zb H[b ]c ^@c xclc cc dc hec Xgd i<d k`d nd pd qd re Ht4e ude we ye e 舋$f Tf Xf Hf hf f  g رPg Htg g g Xg  h ظ h @h h`h (h Hh 8h xi 0i Pi Hpi Xi HËi (ċi Hŋj 8̋Hj h֋j 8ًj xًj ًj ڋk (݋Dk ݋pk 8k 8k k ((l Pl pl 8l l l 8 m 0m Tm Xxm m Hm  n  n H@n hhn n n n o ,o \o 8	o 
o (o  p ,p Tp p Hp Hp p 8q 4q Xq X|q q q r 8r xdr (r X!r !r "s $Ls (ts )s +s .t .4t (/\t x/|t /t X0t 81t 82u 28u h3\u 3u 4u 6u x8u :$v @Tv XA|v Av hBv Fv XFw F8w XGXw XHw Jw Jw Kw Kx 8L4x LTx Ltx Mx XMx Mx Mx 8Ny N4y NTy Oty XOy Oy Oy Py XPz XQDz XRlz xSz Sz Tz U({ WL{ Xp{ XZ{ Z{ \{ \| x]0| H^T| 8_x| x_| o| p| x } D} 8d} } X} ȇ} ~ X(~ XT~ t~ ~ ~ ~ ( 8 H`  菌  x 4 T (| h Ѐ Ȗ x < Hl X 8ԁ  ج( H l     < d   Ѓ   (D h (  8Ԅ   ( P 8| ( Xą Č ƌ ƌ8 Ȍ` ̌ Ќ ь Xӌ ӌ0 ӌP ٌ ڌ ی܇ ܌ ݌8 Hd     HL l  ( hЉ     HP  h (؊ 8  8#4 x#T ) * 8+ԋ x+ .$ 0T 1| 3 5Ќ H8 9( X;X ;x < =̍ ? @$ 8AP A| B HD؎ E HH8 Oh (S Tȏ V V  8W@ xW` W W 8X Y Z [@ \l b 8c Hd e  gL ix l mВ p  s0 HtX tx u w̓ (} h} }H hx ؂ H ( ȓ  H p x ̕ x $ ȟP h h Ԗ X x4 Ȱd 豍 ( (  (@ h Í (č 8   P |  ̙  h( HP | h Hؚ  0 H	T 
  Л   0 ` h h   ! (%H X&p x' 'ȝ h( ( x)@ 8*l * 8+ +ܞ +  ,( X-X -| (. .П 0 (1  2H x4t < <Ƞ (= = H>8 ?` @ A Bܡ C D0 E` xF F XG I XJ@ J` XK K XLԣ Q R$ hRD (Sl S hUԤ (V Y4 ZX xZ| Z [ h\ (] _< x_` ` 8a Xc g( iL Xil i j jا (k hk k< Hl` l l Hm m n n0 HoP px r xr̩ 8t Xu, vT y ({ } x} < Hp ؄ Ы  苎 8H l  Ĭ  蒎 L Ǝ| ǎ Ɏح Ў 8Ҏ4 ҎX xӎ 8Վ h׎ (َ ێH xێp ێ 8ގį ގ 8$ L xx  ԰  ( T     4 d  ( ̲ ( X D Xt H 8̳ H X( X  H  ( < H!l H" #ĵ & h(, *\ (, h. 0 X34 H8` = G [ hd@ f h hiԸ l 8m0 mT 8nt n pȹ r rs$ sD hup (z X{̺ } ~ (8 X  8 ؑػ ( h  薏H (p h ر̼  80 ŏX hˏ ˏ ˏн (Ϗ я( (ҏH hҏh ׏ 8؏ y   ! e0 T XH x  (# #  8$  %L %t & ( ) h*( +X h, (- 3 5 60 x=` > @ 8E F F( GT H| K L L M N8 Ph R HR S T U0 Zl x\ ] h] ] x^$ _P a| hb c Hd xe XfP fp f hg (h i  jD mx m o q  w, xX (y y z (| 8}@ Xh    8 ȁ$ hH 肐p  h  ( X Ȥ 8  ئ  4 詐d x   Ȭ 4 H\   ص x  D l  	 ) P$ D Jd   Ŀ d  ( ʼH 꼐h Ľ <x  Ⱦ    ̿< \ h|   @   F@ f`    Ð ~Ð Ð  Ð  Đ@ `Đ` Đ Đ Ő DŐ jŐ  Ő  Ő@ Ő` bƐ Ɛ Ɛ ǐ &ǐ 6ǐ$ ǐD ǐd  Ȑ 0Ȑ FȐ Ȑ Ȑ Ȑ( ȐH 
ɐh Fɐ Vɐ ɐ ɐ ɐ ɐ( LʐH ʐh ʐ ʐ 
ː Zː ː ː( ːH ːh :̐ ̐ ̐ ̐ ̐ ̐( ͐H Z͐h ͐ ͐ ͐ ΐ  ΐ Mΐ( lΐH ΐh ΐ ΐ ϐ ,ϐ Bϐ Tϐ( hϐ А Ґ  Ӑ0 hՐ` Hؐ ِ Hڐ 8ݐ hސH ސh ސ 8ߐ ߐ X  , 8X |  8  X 0 P | h  ( x 0 HP t  h  X  $ HD h 8    H@ d (    X @ H`  h    X0 T x 8    4 x\ |  8 	 
  
H p   8  < h  ( H 8  P  (!            zR x  $      0pP   FJw ?9*3$"       D   Xq              \   q@             t   a;rL    ECC        ;r+   EC"       <rg    EC^        <rD    EC{         =r+    ECb        =r    EC     4  =r    EC     T  P>r   EC    t  O?r4    ECk        c?r    EC       ?r_    ACZ       >@r@   AC;      ^ArW    ACR        Ar   ACH     8  `Dr%    EC\      X  eDr>    ECu      x  Dr;    ECr        Dr    ECL        Dr%    EC\        Dr>    ECu        Dr;    ECr        Dr    ECL      8  Dr%    EC\      X  Dr>    ECu      x  Dr;    ECr        Er    ECL        Dr%    EC\        Dr>    ECu        Er;    ECr        7Er    ECL      8  ,Er%    EC\      X  1Er>    ECu      x  OEr;    ECr        jEr    ECL        _Er%    EC\        dEr>    ECu        Er;    ECr        Er    ECL      8  Er    EC    X  Fr|    ECs     x  Fr    EC       WGrD    EC{         {Grp   ECEb       Hr    EC       WIr    ECM         MIr6   ECE(     @  _Jr    EC     `  Kr    EC       Kr    EC       6Lr.    ECe        DLr.    ECe        RLr   EC       QMr    EC        Mr    EC     @  Nr    EC     `  2Or.    ECe        @Or.    ECe        NOr    EC       Or    EC       Prz   ECq       Qr    EC        ~Rr    EC     @  !SrB    ECy      `  CSrB    ECy        eSrB    ECy        Sr1    ECh        Sr)    EC`        Srn    ECe      	  Sr    ECV       	  Srn    ECe     @	  <Tr    ECV      `	  ;TrP    ECG     	  kTrr    ECi     	  Tr,   EC#    	  Vr   EC    	  SZr    EC      
  Zr    EC      
  [rA    ECx       @
  [rm    ECd         d
  H\rJ    ECx
E    
  x\r    EC
A       
  ]rQ    ECE~
A    
  `]r9    ECk
A$   
  ]r    ACI
I     X^r4    ECf
A    4  x^rc    ECEP
A    X  ^rQ    ECC
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8A0A(B BBBA      xr~    ATb
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8A0A(B BBBHO8I0I(B BBB`     pr   QBB B(D0A8D`
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8F0A(B BBBI\   P$  r   FEE B(A0D8G
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(A BBBCp(A BBBA   d   ,%  0r    REE E(D0A8G@|
8A0A(B BBBEJ8A0A(B BBBA     %  r    A]]
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(A ABBA    ,'  rh    K E
A (   H'  r    EAG 
IAE    t'  r.    ACi      '  r.    ACi      '  r_    ACZ     '  r@   AC;    '  3rW    ACR     (  jr    AC     4(  -r<    ECs      T(  Ir?    ECv      t(  hr0    ECg      (  xr   EC    (  hr    ACM      (  Zr    ACI      (  Hr    ACI      )  6r    ACI      4)  $r     AC[      T)  $r>    ACy      t)  Br    AC     )  r    AC     )  r    ACR      )  r    ACL      )  r    ACR      *  r     AC[      4*  r!    AC\      T*  r!    AC\      t*  r!    AC\      *  r!    AC\      *  r!    AC\      *  r!    AC\      *  r!    AC\      +  rI    ACD     4+  r!    AC\      T+  r!    AC\      t+  r!    AC\      +  r!    AC\      +  r!    AC\      +  r!    AC\      +  r!    AC\      ,  r=    ACx       4,  re    ACE[      X,  1 s    ACU      x,  + s    ACO      ,   s    ACM      ,   s    ACM      ,   s    ACM      ,  r4    ACo      -  	 s    ACM      8-  ra    AC\     X-  < s]    ACX     x-  y s    ACM      -  k s    ACM      -  ] s    ACM      -  O s    ACM      -  A si    ACd     .   sy    ACt     8.   su    ACp     X.  8s    ACX      x.  5s"    AC]      .  7s8    ACs      .  Os    AC     .  s"    AC]      .  s!    AC\      /  s    ACY       8/  sW    ACEM      \/  s+    ACf      |/  s    ACQ      /  s    AC     /  ts1    ACl      /  s    AC     /  s-    ACh      0  s*    ACe      <0  sO    ACJ     \0  1s1    ACl      |0  Bs   EC    0  As!    ECX      0  Bs   EC    0  .s   EC    0  s    ACI      1  s    ECI      <1  s    ECF      \1  s    ECF      |1  s    ECH      1  xs    EC     1  s    EC     1  s    ECx     1  
s    ECQ      2  s@    ECw      <2  $s   EC    \2  
sX   ECO    |2  Ks    EC     2  sl    ECc     2  s    EC|     2  s   EC    2  Ws    ECR      3  Rsf    EC]     <3  s~   ECu    \3  sy	   ECp	    |3  Os    EC     3  s   EC    3  M!s    EC     3  "sk   ECb    3  L#s    EC     4  *$s   EC    <4  's    ECU      \4  's    EC     |4  (s    EC     4  @)s%    EC\      4  E)sy    ECp     4  )s&   EC    4  *s    EC     5  +s    EC     <5  +s    EC     \5  -,sa    ECX     |5  n,s   EC     5  Q-s|   ECs    5  .s    EC     5  /s   EC    5  y2s   EC    6  X4s    ECw     <6  4s    EC     \6  F5s    EC     |6  !6sM   ECD    6  N7s    EC     6  8s}    ECt     6  n8s{   ECr    6  9s   EC    7  <s   EC    <7  A>s|   ECs    \7  ?s    EC     |7  d@s    EC     7  @s    EC|     7  :As#   EC    7  =Cs(    EC_      7  ECsn   ECe    8  Ds   EC    <8  .Fsr    ECi     \8  Fs    EC     |8   Gs   EC    8  Vs    EC     8  Vs5    ECl      8  Vs=   EC4    8  YsI    EC@      9  Ysn   ECH]     @9  E`s'   EC    `9  Laso   ECf    9  ds    EC     9  fes`    ECW     9  es/    ECf      9  es   EC      :  fs"   ECE     $:  ksH    EC      D:  ks    ECP      d:  ksq   ECh    :  os4    ECk       :  2os.   ECE      :  <rs    EC     :  rs\    ECS     ;  ss    ECU      (;  ssS   ECJ    H;  Dts    EC     h;  ts   EC    ;  xs    EC     ;  Yys    EC     ;  ys    ECx     ;  &zs    EC      <  zs    ECG     ,<  {s    ECG $   P<  {s    ECI      x<  R|sd    EC[     <  |s=    ECt      <  |s2    ECi      <  |s   EC
    <  }s{    ECr     =  ~s
   EC
    8=  sY    ECP     X=  ߈s~    ECu     x=  =s    EC    =  =s    EC     =  ߊs   EC    =  Ìs    EC     =  su    ECl     >  ܍s3   EC*    8>  s   EC    X>  Ys,    ECc      x>  es    EC     >  ؛sH    EC      >   s!    ECX      >  sz    ECq     >  [s7   EC.    ?  rs   EC    8?  sH    EC      X?  @s   EC    x?  +si   EC`    ?  ts    EC     ?  s   ECx    ?  qs:    ECq      ?  s    ECP      @  sF    EC}      8@  sI    EC@     X@  ӯs    ECP      x@  ̯sv   ECm    @  "s    ECL      @  sA    ECx      @  8sj    ECa      @  sT   ECEF     A  s   EC    <A  {sc    ECZ     \A  s   ECx    |A  s]   ECT     A  \s   ECE     A  s   EC    A  s   EC	     B  s   EC     B  vs    EC     @B  s    EC      `B  [s   ECG   B  >sd    EC[     B  s_    ECV     B  s7    ECn       B  s   ECE	     C  sc   ECZ    (C  sU   ECL    HC  Cs8    ECo      hC  [s>    ECu      C  ys    ECM      C  os!    ECX      C  ps    EC     C  ss    ECj      D  Zs   ECH     ,D  sN   ECE    LD  s    EC     lD  s    EC     D  s    EC     D  s    EC     D  QsY    ECP     D  s   EC    E  :sw   ECn    ,E  s   EC    LE  sq   ECh    lE  gsV    ECM     E  sU    ECL     E  sT   ECK    E  s    EC     E  s   EC    F  -s?   EC6    ,F  Ls    EC     LF  sv    ECm     lF  &s    EC~     F  s    EC}     F  s   EC    F  ls   EC    F  s   EC    G  xs;   EC2     ,G  ti   ECE[      PG  to   ECH^     tG  #t   EC    G  t    EC{     G  t   EC    G  t   EC    G  t	   EC	    H  +tW    ECN     4H  bt3   EC*    TH  u t   EC    tH  "t   EC    H  #t   EC    H  $t   EC    H  &t   EC	    H  (tm   ECd    I  *to    ECf     4I  c*tI   EC@    TI  +t   EC    tI  U0tS    ECJ     I  0t#    ECZ      I  0t    EC     I  1tW   ECN    I  O2t    EC     J  2t   EC    4J  94t   ECv    TJ  5t(    EC_      tJ  5t   EC     J  6tw   ECGg   J  8t'   EC    J  ;t   EC    J  <t   EC    K  tAt    EC     8K  Bt    EC     XK  Bt    EC     xK  Ct   EC    K  Ct   EC    K  Et<   EC3    K  Gt*    ECa      K  Gt(    EC_      L  Gt    EC     8L  sHtO   ECF    XL  It/   EC&    xL  Jt    EC      L  UKt   ECE      L  =Nt   ECE     L  Otu    ECl      M  Pt    ECP       M  	Pt    ECP      @M  Pt4    ECk      `M  Pt   EC    M  Rt   EC{    M  wSt   EC    M  %Ut1   EC(    M  6Vt~    ECu      N  Vtk    ECb      N  Vt   EC    @N  Xt   EC    `N  d\t)    EC`      N  m\t#    ECZ      N  p\t-    ECd      N  }\t'    EC^      N  \t<    ECs       O  \t<    ECs       O  \t    EC     @O  j]t!   EC    `O  k^t\    ECS     O  ^t\    ECS     O  ^t    ECV      O  ^t    ECL      O  ^t    ECM       P  ^t    ECM       P  ^tC    ECz      @P  ^t    ECM      `P  ^t    ECV      P  ^t    ECM      P  ^t    ECM      P  ^t    EC     P  y_tC    ECz       Q  _t    ECO       Q  _ty    ECp     @Q  _t    ECO      `Q  _tC    ECz      Q  `t    ECO      Q   `tC    ECz      Q  #`t    ECL      Q  `t@    ECw       R  8`t)    EC`       R  A`t    EC     @R  `t8    ECo      `R  `t    ECO      R  `t8    ECo      R  `t    ECO      R  `tM   ECD     R  bt   ECE     S  dt   EC	    $S  et    EC      DS  0ftE   ECE7     hS  Qgt    EC     S  ht0    ECg      S  ht0    ECg      S  $ht0    ECg      S  4ht0    ECg      T  Dht    EC     (T  ht   ECx    HT  +mt    EC     hT  mt    EC     T  Tntf    ACa     T  nt    EC     T  'ot   EC    T  pt   EC    U  rt   EC    (U  =tt    EC     HU  utF    EC}      hU  Auty    ECp     U  utB    ECy      U  ut    ECL      U  ut@    ECw      U  ut    ECL      V  ut@    ECw      (V  ut    ECP      HV  utF    EC}      hV  vt    ECL      V  ut@    ECw      V  vt    ECL      V  vt@    ECw      V  /vt    ECL      W  $vt   EC     (W  xtm   ECE_     LW  Bzt#    ECZ      lW  Ezt#    ECZ      W  Hzt    EC     W  zt    EC     W  c{t    ECQ      W  ]{t    ECL      X  R{t@    ECw      ,X  r{t    EC     LX  |t    EC     lX  |t    ECP      X  |t   EC    X  }tF    EC}      X  }tr    ECi     X  }t    EC     Y  ~t1    ECh      ,Y  ~t   EC    LY  Ztu    ECl     lY  tu    ECl     Y  tm    ECd     Y  Qtu    ECl     Y  tl    ECc      Y  te    ECEW      Z  3t    EC}     0Z  t    ECN      PZ  t    EC     pZ  $t    ECL      Z  t    ECM      Z  t'    EC^      Z  t    EC     Z  t4    ECk      [  t-   EC$    0[  t    EC     P[  }t    EC     p[  ?t?    ECv      [  ^t`   ECW    [  t+    ECb      [  t(   EC    [  t/    ECf      \  t/    ECf      0\  ύt/    ECf      P\  ލt/    ECf      p\  t   ECw    \  Mt   ECz    \  tL    ECC     \  ܑt#    ECZ      \  ߑt#    ECZ      ]  t#    ECZ      0]  t#    ECZ      P]  t#    ECZ       p]  t    ECE       ]  t    ECG~     ]  tU    ECEG       ]  .t    ECH       ^  tM   ECD     ^  t    ECH      @^  וtE   EC<    `^  t   EC    ^  t    EC     ^  zt   EC    ^  at    EC     ^  <t/    ECf       _  Kt%   EC     _  PtF   EC=    @_  vt"    ECY      `_  xt3   EC*    _  tL   ECC    _  t   EC    _  t\   ECS    _  t   EC     `  t   EC     `  1tN   ECE     @`  _t    ACG~     d`  ŵtQ    ACEG       `  t    ECH      `  }tM   ECD    `  t?   EC6    `  ɺt    ECH      a  t
   EC    ,a  tq   ECh    La  t   EC    la  tX   ECO    a  t    EC     a  t   EC    a  tS   ECJ    a  t    EC     b  t   EC    ,b  *t   EC    Lb  t3    ECj      lb  tA   EC8    b  t   EC    b  t.    ECe      b  tr   ECi    b  @t   EC    c  t#    ECZ      ,c  t)    EC`      Lc  t#    ECZ      lc  t<    ECs      c  t<    ECs      c  t0   EC'    c  t0    ECg      c  't0    ECg      d  7t0    ECg      ,d  Gt0    ECg      Ld  Wt   ECw    ld  t   EC    d  Ut   EC    d  t   EC
    d  t   EC    d  tA    ECx      e  t#   EC    ,e  t    EC     Le  t|    ECs     le  t   EC    e  t;   EC2    e  t   EC    e  }t    EC     e  ,t    EC     f  t   EC    ,f  t   EC    Lf  otV   ECM    lf  tR   ECI    f  u3   EC*    f  uq    ECh     f  ;u    ECL      f  0u    EC     g  u    ECN      ,g  ue    EC\     Lg  $u    EC~     lg  uq    ECh     g  u    EC     g  gu   EC    g  u=   EC4    g  uG   EC>    h  $u   EC    ,h  u   EC    Lh  u    EC     lh  ru    EC     h  u   EC     h  u   ECE     h  EuX    ECO     h  }u   EC
     i  pu   ECE     4i   u    EC     Ti  ut    ECk     ti  2uu    ACp     i  u8    ACs      i  u    AC     i  u"    AC]      i  !u!    AC\      j  "u1    ACl      4j  3u    AC     Tj  u    ACI      tj  u/    ACj      j  u5    ACp      j  uN    ECE     j  u   EC    j  Cu9    ECp      k  \u    EC     4k  u   EC    Tk   u    EC     tk  *!uV	   ECM	    k  `*u    EC     k  ++u    EC     k  +u    EC     k  ,u    EC     l  b-u    EC     4l  -.u    EC     Tl  .u    EC     tl  t/u    EC     l  *0u    EC     l  0u   EC    l  {2uM    ECD     l  2uT    ECK     m  2uT    ECK     4m  3uR    ECI     Tm  B3ug   EC^    tm  4u+    ECb      m  4u#    ECZ      m  4uU   ECL    m  5u    EC     m  M6uq   ECh    n  8u@   EC7    4n  :u+    ECb      Tn  :u,    ECc      tn  :u   EC    n  Ju    EC     n  -Ku>   EC5    n  KMu    EC     n  Mu   EC    o  iPuM   ECD    4o  Qu&   EC    To  Uu    EC     to  @Vu+    ECb      o  KVu+    ECb      o  VVu+    ECb      o  aVu+    ECb      o  lVu   EC    p  eWu     ECW      4p  eWu   EC    Tp  ^Xu     ECW      tp  ^XuJ   ECA    p  Yu     ECW      p  Yu   EC    p  Zu     ECW      p  Zu    EC     q  H[u.    ECe      4q  V[u.    ECe      Tq  d[u.    ECe      tq  r[u.    ECe      q  [uV   ECM    q  \u    EC     q  *]u%   EC    q  /`uj   ECa    r  yau    EC     4r  au+   EC"    Tr   cu   EC    tr  cu)   EC     r  eu+   EC"    r  fu    ACM      r  eu    ACR      r  euC    ECz      s  fu?    ECv      4s  8fu    ECS      Ts  4fuZ   ECQ    ts  ngu    ACN      s  aguL   ECC     s  huW    ECEI      s  huV   ECM    s  iu    ACM      t  iu    ACI      8t  iu    ACI      Xt  iu    ACI      xt  iu     AC[      t  iu>    ACy      t  iu    ACR      t  iu    ACL      t  iu    ACR      u  iu!    AC\      8u  iu!    AC\      Xu  iu;    ACv      xu  iu!    AC\      u  iu!    AC\      u  iu!    AC\      u  iu!    AC\      u  iuI    ACD     v  iu!    AC\      8v  iu!    AC\      Xv  iu!    AC\      xv  iu=    ACx      v  ju    ACM      v  ju    ACM      v  iu    ACM      v  iu    ACM      w  iu]    ACX     8w  ju    ACM      Xw  ju    ACM      xw  ju    ACM      w  iu    ACM      w  iuy    ACt     w  ?ju"    AC]      w  Aju8    ACs      x  Yju    AC     8x  ju;    ECr      Xx  jue    EC\     xx  9kue    EC\     x  ~ku"    AC]      x  ku    ACY       x  ~kuW    ACEM      x  ku+    ACf      y  ku<    ACw      <y  ku    ACI      \y  kuY   ECP    |y  lu    ECv     y  ^muI    EC@     y  muF    EC}      y  mu    EC      y  !nu9   ECE+      z  6pu    EC     @z  pu   EC    `z  ruP    ECG      z  ru+   ECG   z  vul   ECc    z  $xul    ECc     z  pxu`    ECW     {  xu"   EC    ${  }uw    ECn     D{  	~u     ECW      d{  	~u    ECM      {  }uu    ECl     {  T~uO    ECF     {  ~u#   EC    {  uK    ECB     |  uK    ECB     $|  uB    ECy      D|  u    ECF      d|  u6    ECm      |  u{    ECr     |  ^u>    ECu      |  |u8    ECo      |  u   EC    }  Qu~   ECu    $}  u    EC     D}  Su   EC     d}  5u    EC     }  ۆu   EC    }  Ԉu0    ECg      }  u3    ECj      }  u1    ECh      ~  u#    ECZ      $~  u^    ECU     D~  Iu    EC     d~  u   EC    ~  u    ECS      ~  u&    EC]      ~  u8   EC/    ~  ƍu6    ECm        ܍u9    ECp      $  uz   ECq    D  Ou   EC    d  'u3    ECj        :u6    ECm        Pu   EC      2u+    ECb        =u1    ECh        Nu   EC    $  u    EC     D  *u3    ECj      d  =u6    ECm        Su   EC      Nu3    ECj      Ā  au    ECL        Vu    ECS        Ru9    ECp       $  ku   ECE     H  u    EC     h  u    EC       u&    EC]        u   EC     ȁ  u    ECE        su+    ECb        ~u     ECW      ,  ~u_    ECV     L  u   EC    l  zu    EC       u    EC       uM    ECD      ̂  ua    ECGQ      u    EC       yu&   EC    0  uM   ECD    P  um    ECd     p  uU   ECL      .uX   ECO      fu    EC    Ѓ  fu%    EC\        ku   EC       Ru6    ECm      0  hu   EC     P  Nu    EC     p  u1    ECh        'u1    ECh        8u/    ECf       Є  Guc   ECGS     u   EC      u7    ECn       4  u   ECE     X  Au;    ECr      x  \uy   ECp      u    EC       luS    ECJ     ؅  u6    ECm        u6    ECm        ˸u6    ECm      8  uS    ECJ     X  uS    ECJ     x  Gu    EC       ޹u    EC       u|   ECs    ؆  ۻuD   EC;      u    EC       ɽuJ   ECA    8  u%   EC    X  u8    ECo      x  u8    ECo        (uC   EC:      Ku   EC    ؇  u    EC       u+   EC"      u    EC      8  u.   ECE      \  u    ECw     |  u    EC       u    EC       Ru]    ECT     ܈  u6    ECm        u{    ECr        u   EC    <  u*    ECa      \  uA    ECx      |  u   EC      uq    ECh       "u    EC     ܉  u    ECM        u    ECN        ~u!    ECX      <  um   ECd    \  u,   EC#    |  u    EC       uU   ECL      uK    ECB     ܊  ug    EC^       LuU    ECL       uC    ECz      <  uF    EC}      \  uT    ECK     |  u/    ECf        u    EC       u    EC     ܋  uq    ECh       Xu>    ACy        vu    EC     <  u    EC     \  _u    EC     |  u    EC       ]u    EC        u_    ECEQ        u    EC        u    EC        u    EC     @  u   EC     `  u   ECG     ub    ECY       \u&    ACa      č  bu[    ACV       u    EC       0u*    ACe   $   $  :u   ECL  $   L  uW   ECIE     t  3u   EC      u5    ACp        uG    ACB      Ԏ  uM   ECG=     ub    ECY        Du"   ECG   <  Bu~    ECu     \  u	   EC     |  uN   ECE      u    EC       eu   EC    ܏  vh    EC_       ZvJ   ECA      v   EC    <  Xvs    ECj     \  vx   ECo    |  vc   ECZ      F	v   EC      
v   EC    ܐ  v    EC        vG   ECH6        v    ECM      @  vU    ECL     `  vI    EC@       &v    EC       v?   EC6      v    ACI        v    ACL         v"    AC]         v!    AC\      @  v    ACS      `  vb   ECY       v   ECG     vD    AC      Ē  vK    ACF        vi   ECJV     #,v   EC    (  .v8    ACs      H  .v    AC     h  4/v"    AC]        6/v    ACM        (/v    ACX      ȓ  %/v    ACX        "/v    ACW        /v    ACX      (  /v    ACM      H  /v"    AC]       h  /v    ACE        /vN    ACI       0v,    ACg      ̔  0vF   EC=      41v    ECS        01va    ECX     ,  q1v]    ECT     L  1v   EC    l  w4v    EC       O5v    EC       5v    EC     ̕  6v   EC      T8v    EC       8v.    ECe      ,  8v    EC     L  9v|   ECs    l  ;v.   EC%      <v5   EC,      %@v_   ECV    ̖  dAvI    EC@       Av    EC       %Bv    EC     ,  Bvp    ECg     L  CvJ   ECA    l  +Dv(    EC_        3Dv(    EC_        ;Dv    EC     ̗  Dv   EC        Ev   ECH       4Gv    EC     0  Gv_   ECV     P  +Ivn   ECH]      t  uNvE   ECH4       RvN    ECE        Rvs   ECHb     ܘ  Wv   EC      Xvg    EC^       Xv   EC    <  ^[vH   EC?    \  \v    EC     |  3]v"    AC]        5]v    EC       ^v    EC     ܙ  ^v    EC       r_v   EC      hdv    EC     <  ev   EC    \  fv   EC    |  gv   EC      rmv?    ECv        mv   EC    ܚ  0ov    ACI        ov>    ACy        <ov<    ACw      <  Xov-    ECd      \  eov.    ECe      |  sovn    ECe       ovY    ECP       ov    EC     ܛ  pv=    ECt        pv    ECM        pv    ECM      <  pvW    ECN      \  pvb   ECET       rv    EC        rv   ECE      Ĝ  tv    ECE         Yuv	   ECE        >vv    ACI      ,  ,vv     AC[      L  ,vv>    ACy      l  Jvv    ACR        Avv    ACL        2vv    ACR      ̝  )vv!    AC\        *vv!    AC\        +vv!    AC\      ,  ,vv;    ACv      L  Gvv!    AC\      l  Hvv!    AC\        IvvI    ACD       rvv!    AC\      ̞  svv!    AC\        tvv    ACU        nvv    ACM      ,  `vv    ACM      L  Rvv    ACM      l  Dvv4    ACo        Xvv    ACM        Jvva    AC\     ̟  vv]    ACX       vv    ACM        vv    ACM      ,  vv    ACM      L  vvK    ACF     l  vvy    ACt       "wvu    ACp       wwv8    ACs      ̠  wv    AC       xv"    AC]        xv    ACY      ,  xv<    ECs      L  +xv"    ECY      l  -xv2    ECi        ?xv)    EC`        Hxv    EC     ̡  yv   EC      zv    EC       {v    ECz     ,  {v    EC     L  |v    EC     l  |}v   EC      v    EC       рv   EC    ̢  svl    ECc       vw   ECn      v   EC     ,  vt   ECHc      P  bv    ECG    t  Ώv   EC      Tv    EC       ؓvI    EC@      ԣ  v\   ECEN       9va   ECX      zv   EC    8  /v    ECv     X  v    EC     x  v    EC       v   EC      ߚv   EC    ؤ  v    EC       rv    ECy       ԝvz    ECq     8  .v   EC    X  ϥv    EC     x  v    EC        WvL   ECE>       v.    ECe      ܥ  v.    ECe        v=    ECt        v-    ECd      <  ũv    ECw     \  %vH    EC      |  MvH   EC?      uv    EC        v    ECE        v    EC        vX    ECO         EvI   ECE;      D  jv   ECE     h   v   EC      v~   ECu       xvH   ECE:      ̧  v   ECE        %v[   ECEM       \v   EC     4  v   ECG    X  dv?   ECG/   |  v   ECy      v   EC      iv   EC	    ܨ  [vg   EC^      vy    ACt       v8    ACs      <  v    AC     \  v"    AC]      |  v    EC       v   EC      v    EC     ܩ  dv2   EC)      vv    ACY        tvC   EC:    <  v    EC     \  v    EC     |  v    EC       iv    ECL        ^vH    EC      ܪ  v    EC       Iv    EC       v:    ECq      <  &v    ECQ      \   v    ECL      |  vQ    ECH       Fv#    ECZ        Iv    EC     ܫ  vM    ECD       v.   EC%      v$   EC    <  v|    ECs     \  Qv/    ECf      |  `v/    ECf        ovH   EC?      v^    ECU     ܬ  vh   EC_      v    ACI        v     AC[      <  v>    ACy      \  )vK    ACF     |  Tv<    ECs        pv^    ECU       v   EC    ܭ  'vP    ECG       Wv    ECM        Mv    ECL      <  BvL    ECC     \  nv    EC     |  v    EC       v    ACM        v    ACI      ܮ  v    ACR        v    ACL        v    ACR      <  v!    AC\      \  v!    AC\      |  v!    AC\        v!    AC\        v!    AC\      ܯ  v!    AC\        v    ACM        v    ACM      <  v    ACM      \  v    ACM      |  qv    ACM        cvy    ACt       v    ACX      ܰ  v"    AC]        v8    ACs        v    AC     <  Sv"    AC]      \  Uv    AC     |  v*    ACe        v1    ACl        vu   ECl    ܱ  5v   EC      v   EC      9vD   EC;    <  ]v3   EC*    \  pv   EC    |  v   EC      hv   EC       Jv    EC     ܲ  v   EC      v2    ECi        v,   EC#    <  v    EC     \  v   EC    |  w   EC      w   EC      5w   EC    ܳ  	wE    ECEw     .wI    EC@       WwQ   ECH    <  w    EC     \  w   EC    |  ww    ECn       <w   EC	      .wp    ECg     ܴ  ~w[    ECR       wQ    ECH       w@   EC7    <  
wj    ECa     \  TwE    EC|      |  yw   EC      pw]   ECT      w^    ECU     ܵ  w    EC       Uw    EC        w	   ECG	   @  i&w   EC    `   *w   EC      ,w   EC      	.wc    ECZ       L.w   EC      0wm    ECd        !1wd   EC[       e2w.    ECe      @  s2w1    ECh      `  2w>    ECu        2w   EC      59w   EC      )=w   EC      ">wj   ECa       l@w   EC       Iw    EC     @  Iw   EC    `  Pw   EC      RwJ   ECA      Sw   EC      Ww    EC       TXw   EC       ]w    ACM         ]w    ACI      @  ]w    ACL      `  ]wy    ACt       ]wu    ACp       E^w7    ACr        \^wa    AC\       ^wa    AC\        ^w    AC        N_w%    EC\      @  S_w    EC     `  `w    EC       `wQ    ECH       awA    ECx   (     5awH   ECM2       Qew   EC       7fw_    ECV     ,  vfwn    ECe     L  fwT    ECK  $   l  fw6   ECI$  $     hw   ECK      iw/   ECG(     jw   ECM  $     kwK   ECK7    4  mw    ECG (   X  mw   ECM       Kow    ECT         How    ECG (   ȼ  pw    ECP       rw    EC       sw    EC      4  ktw   ECG   X  Xuw[    ECR      x  uw    ECE         vw   ECG     xwH    EC        xw    EC         ywk   ECHZ  $   $  |wE   ECN.(   L  5w   ECM     x  w    EC  (     1w{   ECMe     ľ  w    EC       ?w   EC (     w;   ECM%  (   0  w   ECM  (   \  qw>   ECP%        w   ECG$     w   ECK
   Կ  w&    EC]   (     w   ECM        w    EC      @  0w[   ECGK   d  gw`    ECW       wG    EC~        Νwm   ECd      w    EC  (     w
   ECP
  (     w   ECP     <  w+   EC"    \  *w?   EC6    |  Iw    ACR        @w    ACL        1w    ACR        (w!    AC\        )w!    AC\        *w!    AC\      <  +w;    ACv      \  Fw!    AC\      |  Gw!    AC\        Hw=    ACx         ewe    ACE[        w    ACU         w    ACR         w    ACM      @  w    ACM      `  {w    ACM        mw4    ACo        w    ACM        swa    AC\       w]    ACX        w    ACM         w+    ACf      @  w    ACQ       `  wt    ECEf        4wc   ECZ      ww    ECV        vw-    ECd        w$    EC[         wF   ECG6   (  w   EC    H  w   EC    h   w   EC      w   EC      ~w   EC      &w    EC       w    EC        wB   ECG2   ,  w}    ECt     L  ?w[    ECR     l  zwT    ECK       w/   EC&       wM   ECG=      w}   ECJj     ?w    EC       w   EC    4  SwI   EC@     T  |w!   ECG   x  yw    ACI        gw    ACI        Uw     AC[        Uw>    ACy        swy    ACt       wu    ACp     8  !w    ACY      X  wK    ACF     x  Jw   EC      EwA    ECx        fw   EC      w.   EC%      wA    ECx        w2   EC)    8  wd   EC[    X  Xwa    ECX     x  wx    ECo        w~
   ECJk
      Kx   ECE       xO    ECF        x"    ECY         x2    ECi       @  	x4   ECE&     d  x
   EC
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A        L; p7                    GNU                \   ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"7.0.0-30.30","architecture":"amd64"}     \   ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"7.0.0-30.30","architecture":"amd64"}     \   ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"7.0.0-30.30","architecture":"amd64"}     \   ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"7.0.0-30.30","architecture":"amd64"}     \   ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"7.0.0-30.30","architecture":"amd64"}     \   ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"7.0.0-30.30","architecture":"amd64"}     \   ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"7.0.0-30.30","architecture":"amd64"}     \   ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"7.0.0-30.30","architecture":"amd64"}     \   ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"7.0.0-30.30","architecture":"amd64"}     \   ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"7.0.0-30.30","architecture":"amd64"}     \   ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"7.0.0-30.30","architecture":"amd64"}     \   ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"7.0.0-30.30","architecture":"amd64"}     \   ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"7.0.0-30.30","architecture":"amd64"}     \   ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"7.0.0-30.30","architecture":"amd64"}     \   ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"7.0.0-30.30","architecture":"amd64"}     \   ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"7.0.0-30.30","architecture":"amd64"}     \   ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"7.0.0-30.30","architecture":"amd64"}     \   ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"7.0.0-30.30","architecture":"amd64"}     \   ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"7.0.0-30.30","architecture":"amd64"}     \   ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"7.0.0-30.30","architecture":"amd64"}     \   ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"7.0.0-30.30","architecture":"amd64"}     \   ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"7.0.0-30.30","architecture":"amd64"}     \   ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"7.0.0-30.30","architecture":"amd64"}     \   ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"7.0.0-30.30","architecture":"amd64"}     \   ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"7.0.0-30.30","architecture":"amd64"}     \   ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"7.0.0-30.30","architecture":"amd64"}     \   ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"7.0.0-30.30","architecture":"amd64"}     \   ~FDO {"type":"deb","os":"ubuntu","name":"linux","version":"7.0.0-30.30","architecture":"amd64"}                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   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       R&            &            &            &            W&            &            &            &            \&            ʕ&            ĕ&            &            a&            ܕ&            ֕&            Е&            f&            &            &            &            3'            3'            3'            3'            3'            4'            4'            4'            4'            4'            4'            "4'            (4'            .4'            44'            :4'             @4'     !       D4'     "       H4'     #       L4'     $       P4'     %       T4'     &       X4'     '       \4'     (       3'     )       3'     *       3'     +       3'     ,       3'     -       4'     .       	4'     /       4'     0       `4'     1       g4'     1       }&     1       ?'     2       O'     3       r '     4       O'     5       $&     6       &     7       n4'     :       v4'     ;       d&     >       )'     ?       ~4'     @       4'     A       4'     B       4'          4'          '                          O&             ˔&             Ԕ&             &            &             &            &            &            &            ܔ&            &            &            `&            \&            2'            D&            I&            &            #&            1&            6&            g4'     	       }&     	       @4'            D4'            H4'            L4'            P4'            T4'            X4'            \4'            3'            3'            3'            3'            3'            4'            4'            4'            3'            3'            3'            3'             3'     !       4'     "       	4'     #       4'     $       ~4'     '       ?'     (       O'     )       r '     *       O'     +       $&     ,       &     -       d&     0       )'     1       n4'     \       v4'     ]       4'          '          #             #     #                                             @'     ,'     @'             @'                     7&     @'                                                                     #@'                                                     )@'                     B'     C'     *C'     :C'     LC'     eC'     |C'             C'     C'     C'     C'     C'     C'     	D'     D'     1D'     CD'                     SD'     lD'     D'             D'     D'                     D'     D'                     D'     D'     E'             $E'     ?E'     VE'             iE'     E'     E'     E'     E'             E'     E'                                     
F'     F'     +F'     >F'     UF'     pF'     F'     F'                                     F'     F'     F'             1H'     BH'     TH'     fH'     %      %     %     Ы%     0%      %     %      %     J'                                                                                         8&     8&                             K'     !K'                              bd&     `t(     `                         bd&     )K'                             bd&     ;K'     `     	                    bd&     t(                              bd&     PK'                             bd&     gK'                              bd&     yK'     `ߙ            @ߙ            bd&     t(     ޙ     
       `ޙ            bd&     K'     @ޙ            0ޙ            bd&     K'      ޙ            ޙ            bd&     K'      ݙ            ܙ            bd&     K'     ܙ            ܙ            bd&     K'     ܙ            ܙ            bd&     K'      ܙ     	        ܙ            bd&     NG'      ۙ            ڙ            bd&     K'     ڙ            ڙ            bd&     L'     ٙ            ٙ            bd&     )L'     ٙ            ٙ            bd&     >L'     ؙ            ؙ            bd&     SL'     ؙ            `ؙ            bd&     eL'     י     
       י            bd&     wL'      י     
       ֙            bd&     L'     ֙            `֙            bd&     L'      ֙            ՙ            bd&     L'     @ՙ     	        ՙ            bd&     L'     ԙ            ԙ            bd&     L'     ԙ            ԙ            bd&     L'     ԙ            pԙ            bd&     M'     @ԙ            0ԙ            bd&     M'      ԙ            ә            bd&     *M'     ҙ            ҙ            bd&     <M'     љ            љ            bd&     t(     љ            љ            bd&     t(     @љ             љ            bd&     NM'     Й     
       @Й            bd&     hM'     ϙ            @ϙ            bd&     zM'     Ι            Ι            bd&     M'     Ι            Ι            bd&     M'     Ι            Ι            bd&     M'     Ι            pΙ            bd&     u(                 p            bd&     M'     @            0            bd&     0u(                              bd&     M'                             bd&     hu(     @            0            bd&     N'                                                                                                C      @                 @                  @                [      Ǒ     	      `Ǒ         LǑ        . @Ǒ        E" 0Ǒ        $                 ˑ     8       ˑ        X& ˑ        '                      1      `       ,        X&      	   j1      >   '          `ߑ     I   5 Ց     b  H! ͑       -2 @͑        k ̑        g                                    X&         '                 4           !       ,        X&         '      L   5         H! @     l  "         k         g           
% ;     E                      `A     4      @A          A        W @         @J     /        K             M                            \            [     O   6 |[        X8 x[        ,8 t[        !-8 @V     M  , (V        5 $V        hq.  V        . S        X&  R     Z   ' Q        5 Q        {0 Q        k PQ        g @P     C   
% _                                             ,      1   hq.         . `|        X&  |        j1 `y        ' x     6   5 u        2 r        H! `p        -2 @k     D  "  j     C   W3 i        {0 `i        k h        g f     z   
%                             	             W @     [      ࠒ     W                       . @     F       ଒        !Y      W  {Y X        '                   )                  @     .                      ǒ     W   !Y Ò        {Y       l                       Β        !Y ɒ     A  {Y |ɒ         xɒ        
 `ɒ        
 Pɒ        
  ɒ        ' ɒ        E"  ɒ        $                 @ג     W   !Y Ӓ        {Y ђ     a                       ݒ     /  !Y ؒ     G  {Y ؒ        ' ؒ        bS      2                            x      @       ,         +:S          5S         E=S         Z>S         -2                   b      `     a   W      l          3   '       $   5      '   k       T   H      $   jr      ?             g                                   d              W                   '      %   5      J   k         H      =   jr                   g                                  >           	             W $           `j     k       Y     W  , R       X& `R     	   j1 `O        ' DO          N     I   5 B       H!  :     &  -2 .       "  .        k -        g +        
%  p     X      u     W      u         u        .  {                               W                  E  '       7   5       >   k         H      ;   jr `               O   p ~        g             `     x      0                 W          @                                           O   6 |        X8 x        ,8 t        !-8      m  ,         5         hq.         .          X&      ^   ' @        5      %   {0 `        k 0        g       C   
%                              Ǔ            Ǔ        6 @ē        , (ē        5 @     y   X&       P   '         5         k         g ʓ     /       `˓            @Γ     /        ϓ            ѓ                      `       ,      1   hq. `        .          X&      	   j1          ' @     6   5         2         H!          -2  ݓ     D  " ۓ     C   W3 ۓ        {0  ۓ        k ړ        g ؓ     z   
%      :            1      	     '       @
     '                                   
        X& 
        '                 G     (	       5       , .       X& &       ' %     L   5        H!      l  " @        k          g         
% l     #                           w               W           `z     F  ' y     7   5 x     9   k  v        H  u     >   jr r         `q     R   p  q        g                   X              W                 B  '       7   5       9   k       >   jr         g                                                 @        W 8         @     )                        [   !Y ๔        {Y @     c                       ǔ       !Y `     E  {Y L        
         
         
 p        
 @        '          E"         $  ̔     l       Ԕ        "r `Ԕ        s ͔            Ք     {        ݔ         ܔ        "r ܔ        s  ה     Y      `     w                                         "r         s @     P      @     O                                          "r             `     N                        "r                   M                          "r `            `            @                              .         '         E"         $      T   !Y         {Y       p                       
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3     03     @3     P3     `3     p3     3     3     3     3     3     3     3     3      4     4      4     04     @4     P4     `4     p4     4     4     4     4     4     4     4     4      5     5      5     05     @5     P5     `5     p5     5     5     5     5     5     5     5     5      6     6      6     06     @6     P6     `6     p6     6     6     6     6     6     6     6     6      7     7      7     07     @7     P7     `7     p7     7     7     7     7     7     7     7     7      8     8      8     08     @8     P8     `8     p8     8     8     8     8     8     8     8     8      9     9      9     09     @9     P9     `9     p9     9     9     9     9     9     9     9     9      :     :      :     0:     @:     P:     `:     p:     :     :     :     :     :     :     :     :      ;     ;      ;     0;     @;     P;     `;     p;     ;     ;     ;     ;     ;     ;     ;     ;      <     <      <     0<     @<     P<     `<     p<     <     <     <     <     <     <     <     <      =     =      =     0=     @=     P=     `=     p=     =     =     =     =     =     =     =     =      >     >      >     0>     @>     P>     `>     p>     >     >     >     >     >     >     >     >      ?     ?      ?     0?     @?     P?     `?     p?     ?     ?     ?     ?     ?     ?     ?     ?      @     @      @     0@     @@     P@     `@     p@     @     @     @     @     @     @     @     @      A     A      A     0A     @A     PA     `A     pA     A     A     A     A     A     A     A     A      B     B      B     0B     @B     PB     `B     pB     B     B     B     B     B     B     B     B      C     C      C     0C     @C     PC     `C     pC     C     C     C     C     C     C     C     C      D     D      D     0D     @D     PD     `D     pD     D     D     D     D     D     D     D     D      E     E      E     0E     @E     PE     `E     pE     E     E     E     E     E     E     E     E      F     F      F     0F     @F     PF     `F     pF     F     F     F     F     F     F     F     F      G     G      G     0G     @G     PG     `G     pG     G     G     G     G     G     G     G     G      H     H      H     0H     @H     PH     `H     pH     H     H     H     H     H     H     H     H      I     I      I     0I     @I     PI     `I     pI     I     I     I     I     I     I     I     I      J     J      J     0J     @J     PJ     `J     pJ     J     J     J     J     J     J     J     J      K     K      K     0K     @K     PK     `K     pK     K     K     K     K     K     K     K     K      L     L      L     0L     @L     PL     `L     pL     L     L     L     L     L     L     L     L      M     M      M     0M     @M     PM     `M     pM     M     M     M     M     M     M     M     M      N     N      N     0N     @N     PN     `N     pN     N     N     N     N     N     N     N     N      O     O      O     0O     @O     PO     `O     pO     O     O     O     O     O     O     O     O      P     P      P     0P     @P     PP     `P     pP     P     P     P     P     P     P     P     P      Q     Q      Q     0Q     @Q     PQ     `Q     pQ     Q     Q     Q     Q     Q     Q     Q     Q      R     R      R     0R     @R     PR     `R     pR     R     R     R     R     R     R     R     R      S     S      S     0S     @S     PS     `S     pS     S     S     S     S     S     S     S     S      T     T      T     0T     @T     PT     `T     pT     T     T     T     T     T     T     T     T      U     U      U     0U     @U     PU     `U     pU     U     U     U     U     U     U     U     U      V     V      V     0V     @V     PV     `V     pV     V     V     V     V     V     V     V     V      W     W      W     0W     @W     PW     `W     pW     W     W     W     W     W     W     W     W      X     X      X     0X     @X     PX     `X     pX     X     X     X     X     X     X     X     X      Y     Y      Y     0Y     @Y     PY     `Y     pY     Y     Y     Y     Y     Y     Y     Y     Y      Z     Z      Z     0Z     @Z     PZ     `Z     pZ     Z     Z     Z     Z     Z     Z     Z     Z      [     [      [     0[     @[     P[     `[     p[     [     [     [     [     [     [     [     [      \     \      \     0\     @\     P\     `\      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gbd                            P&      #                                                     cart                            P&     P&                                                     X                            P&     0#                                                     J    7     7     9      t&     U&                     H['     H['     H['     H['     H['                                           	                                    (            (     	       (            (            (            (            (            (     
       (            (            (            (             .(            9(            M(            M(            (            (            e(            s(            }(            (            (            (            (     X)             !)     !)     !)     !)     !)     ")             ")     ?")     O")     h")     ")     ")     ")                     =))     G))     U))     `))     o))     z))     ))     ))     Xf)                             f)     f)     5d)     5d)            f)     f)     f)     f)     P       f)     f)     f)     f)     (       f)     f)     f)     f)     X       f)     f)     f)     f)     `       f)     f)     f)     f)     h       f)     f)     f)     f)     p       f)     f)     f)     f)              g)     g)     g)     g)            g)     g)     g)     g)     H       g)     !g)     %g)     )g)     @       -g)     1g)     6g)     ;g)     8       @g)     Dg)     Ig)     Ng)     0       Sg)     Wg)     \g)     ag)            fg)     jg)     og)     tg)            yg)     }g)     g)     g)            g)     g)     g)     g)                                     l)     N     l)          0l)          <l)     C     Jl)          hl)          |l)          l)          l)          l)          l)     X     m)     '     #m)     ;     9m)          Sm)     L     mm)     X     m)          m)          m)     
     m)          m)          n)     g     4n)                                                                                                  P             @          Y&      4      &             Ph      h      %      %     P5     @%                                                                     &      4      &             g     `g      %      %     ^     @%                                                                    Y&      4      &             g     f      %      %     Z     @%                                                                    'Y&      4      &             pf      f      %      %     V     @%                                                                    Y&      4      &             e     e      %      %     R     @%                                                                    !Y&      4      &             0e     d      %      %     N     @%                                                                    +Y&      4      &             0j     i      %      %     .     @%                                                                    &      4      &             i     @i      %      %     0.     @%                                                                    4Y&      4      &                     d      %      %      J     @%                                                                    <Y&      4      &                     @d      %      %      F     @%                                                         	           CY&      4      &                     c      %      %      B     @%                                                         
           KY&      4      &                     c      %      %      >     @%                                                                    SY&      4      &                     Pc      %      %     9     @%                                                                    [Y&     `(      &              o     n      %      %     !     %                                                                     '     `(      &             n     0n      %      %     !     %                                                                    &     `(      &             m     m      %      %     !     %                                                                    bY&     `(      &             @m     l      %      %     !     %                                                                    hY&     `(      &             l     Pl      %      %     !     %                                                                    X&     >'     ^Z&     2       fZ&     mZ&     ^Z&     3       sZ&     ^Z&     ^Z&     4       zZ&     Z&     Z&     5       l&     Z&     ^Z&     6        U'     Z&     ^Z&     7       m&     Z&     Z&     8                                            @                            P                                                                                                                                    B      K      M      G      @                                                         ?                                                            ?                                                                            -               	         
                                                                                            .text .shstrtab .symtab .strtab .note.gnu.build-id .debug_line .debug_info .debug_abbrev .eh_frame_hdr .eh_frame                                   if&            of&            vf&            |f&            f&            f&            f&            f&     	       f&     
       f&            f&     (       f&     I       f&     K       f&            g&            g&            3g&            Hg&            Yg&            hg&            yg&            g&     
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&     (      &     )      &     *      &&     +      0&     ,      :&     .      B&     /      L&     0      W&     1      a&     2      k&     3      u&     4      &     5      &     6      &     7      &     8      &     9      &     :      &     ;      &     <      &     @      &     H      &     L      &     P      &     T       &     V      
&     X      &     Z      &     _      '&     t      1&     v      ;&     x      E&     |      P&     }      [&           e&           p&           z&           &           &           &     (      &     *      &     +      &     -      &     .      &     /      &     >      &     ?      &           &           &           &           &           &           %&           .&           8&           B&           L&           V&     %      `&            k&           u&     `      &     a      &     %      &     /      &     `      &     a      &     b      &           &           &     
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               T'     T'            $               T'     T'            (               T'     U'            0               U'     %U'            8               /U'     8U'            @               IU'     ӆ&            H               YU'     fU'            p               qU'     &            X              {U'     59'            `              '     &            h              /U'     ?U'            p              IU'                                                                                   V'                                                           &                                                                                    #                                                             	                                                                                                                                                                             T'                           T'     T'                            T'     T'            $               T'     T'            (               T'     U'            0               U'     %U'            8               /U'     8U'            @               IU'     ӆ&            H               YU'     fU'            p               qU'     &            X              {U'     T'            `              T'     T'            d              T'     &            h              *V'                                                                                   7V'                                                            &                                                                                     $                                                                                                                                                                                                                                          T'                           T'     T'                            T'     T'            $               T'     T'            (               T'     U'            0               U'     %U'            8               /U'     8U'            @               IU'     ӆ&            H               YU'     fU'            p               qU'     &            X              {U'     T'            `              T'     MV'            d              GV'     T'            h              T'     XV'            l              RV'     59'            p              '                                                                   ]V'                                                           &                                                                                    P$                                                                                                                                                                                                                                          T'                           T'     T'                            T'     T'            $               T'     T'            (               T'     U'            0               U'     %U'            8               /U'     8U'            @               IU'     ӆ&            H               YU'     fU'            p               qU'     &            X              {U'     sV'            \              mV'     T'            `              T'     T'            d              T'     L&            h              xV'     O'            p              V'     >'            x              V'     V'                          V'                                             GCC: (Ubuntu 15.2.0-16ubuntu1) 15.2.0 ,                                        ,                                      ,    "       5.     (                      ,    ;(       ]3                           ,    -       7                            ,    .       7     %                      ,    3       8     m                       ,    O4       9     a                      ,    2?        ;                           ,    s        N                           ,           R     s                      <    D       `n     #      	     (                       ,                                     ,    h                                  ,    =j      p                           ,    "m                                 ,    s           ,	                      <               m      	                            ,          0                           ,                -                      ,    0            	                      ,                0                          G+                      ,    +                                         N                            	mE  >     }        ׵  int }  	+K  ->   	  q   	e  q             3]  <  5j    I  8	     9	   <g  :	   k  ;	    6  <	   (   =	   0  >	   8rh  ?	   @C  B	   H  C	   PY  D	   X1  Fv  `Y+  H{  hn  Jj   p  Kj     M  w3  N   x  QU   N  R\   /F  S    U  U ]   t  _    `    a{    b	L   6p  c   dj     fj     hx     m   	[     -  -+p  q          >     i  t        {       >       ]    idx j   ptr L    1	  		     =  E       V  nr j   G  j     j   wD   1	     G $  fd &	j   $: 'c     (c    V    ]4  E   !  V   L  	   	y  !>     F  T  lj          BG 6j         j      	L   +  >   >    6 
AL   K  L   j   >      	^  L    /7 	L   z  L   >    T  j                 fda &  Xfp 1  P
fd j   h[  
j   l 	  Q  j        4         fda #  h/2  ,j   d $  lj   x             fda l%  X  l0c   T_  m  Harg nL   @
fd pj   h
nr p
j   l      j   L        [j                 fda [-  Xpos [6j   T  [K  HM@ ]  hݶ  ^j   d   Lj               r  fda L"  Xfd L+j   T  L5c   P=  LQ  L
pos Nj   l +  F     +         fda F&  h 8  ?     D         fda ?$  h 
  /        g         G  /"j   \  /0j   X
fda 1  h Q  j        +        fda #  nr ,j   1	    hG  j   Lj  	2   PT  	2   XwD   ` !V       L       fda $  h  -j   d       &N                    Y      }      ׵  'int }  c   	+K  -G   	  c   	e  c   (         \      
G    	     )		  G   	   G   	 c   	  c             	  	  	mE  G     3  <  5\    I  8	     9	   <g  :	   k  ;	    6  <	   (   =	   0  >	   8rh  ?	   @C  B	   H  C	   PY  D	   X1  F  `Y+  H  hn  J\   p*  K\     M  w3  N{   x  Q9   N  RN   /F  S    U  U ]   t  _    `    a    b	   6p  c    d\     f\     ho     m%   	[  $  +-  -+p    $       
G       t             5  
G    	  R       F  z  3|    5#|   H 6#|   T  	  7T    (	    	\    l  	@     	\    	@     	 \   , 	"	U   A  	#	U   r 	$   	  
5\   ,(
C	:  n  E  R  F:    Gc       J  
G   ' 	  
H  [  -	 x              #     $    %    "  &   (  '   0  )   8 *   @  +   H;  ,   Pz  -  X      
G    .@   0U  i        Ի      w       U  	y  !G   G $  fd &	\    $: 'U     (U     io (  fd \    x @   buf    end    P    :  \    eof   $      
G       1  	"     c  6  	"       ]  
G    M  !  ?]  	"         
G    x    J  	 #         
G       : R  	P&       V  	0#      fs H[1  L{ \   @  ];  rm ^
     _J    `j   @     6     	@v         	v     w   	 w        	`w         	w        	 x     	3 z5    \   V     ~ t\        	   BG 6\   "  "  _  \    k  /7    C     G    /  V       M  v    Z  \    X= f\     \      m\     	   8 s5    \         0R  %  \   !VB Լ  \     	  \     C\   	  	   J  3 \   ;	  	  	  	  G   V   e  \   R	  	   tw \   t	     G   	   1  a	  	  	  @   	       	  	   2 /   	     V  G    5    	  	   s }\   	  \    !	 #  \   
  	  
   \  "  \   <
  A  	   ;  \   R
  A   $     h
  	    \   
  	  	   "    A  
         \   
  
  
     
  21  \   r-            +  M@ "	  _˿ -\   _rm +  _ 	  _    <  #G     \   ,                "	  _˿ /  _rm +  _  	  _   \   @+     z      .  M@ "	  _˿ /.  _io   _bf 3  _ret \   _rm +  _ 	  _      C  
G    Ⱥ  \   z*              M@ !	  _buf /U  _(  <  _rm +  _ 	  _    \   )              M@ !	  _˿ -  _rm +  _ 	  _   \   )     .       \  M@ !	  h˿ <\  ` M  7  \   f)     .         M@ !	  h˿ <\  `   \   (              M@ -	  _˿ \  _Eg  $\   _rm +  _ 	  _   \   '              M@ "	  _buf 0U  _(  =  _rm +  _  	  _ n  q\   %'                q%	  ˿ q3\   fd s\   err s%\   buf t        
G   ?  \\   &               \$	  ~buf \5U  ~(  \B  ~io ^  ~bf _  ~err `\   ~      
G    K W\   %     .           W$	  h˿ WB\  `   M\   %     .           M$	  h˿ MB\  `   6\   $                60	  ˿ 7\  Eg  7'\   ~V 9  fd :\   err :%\     %\   ;$            
    %$	  ˿ %3  V '  fd (\   err (%\    / 	  s#            [  fs )[  Xq 	  h3out  %$          	  ="     6        fs .[  K  	  @   P      $G   H 4m 	  '"              fs 4  h 1   w!            9  fs &[  h5 I  	0Q&        I  
G    9  p         p        fs )[  g     PK  	     H      $G   @ z       D         f    hlen )  ` ý    :            <  fs )[  Xptr 6  h   \        |         fs (	  ~  1c   ~T  \  ~ 7                  fs ([  ^%   ^fp A  ^rm   _      
G   c      #G     M                + 	  N     ;       j  q 	  `fs [  h i 	       >            	     fs [  h        %         fs [  h m                  	       ;       5  q 	  `fs [  h  	  ]     >       z     	     fs [  h   8     %         fs [  h Z    #            .  	       ;          q 	  `fs [  h a  	       >       E     	     fs [  h        %       q  fs [  h "    p            o 	  5     ;         q 	  `fs [  h c  	       >            	     fs [  h ^      %       <  fs [  h B                 	       ;         q 	  `fs [  h \  	  D     >            	     fs [  h        %         fs [  h L   
            U 	       ;       a  q 	  `fs [  h   	       >            	     fs [  h W  l     %         fs [  h  5  }             io /  ~|  :U  ~  L  ~ ^\   ~buf   ~r  \   ~V    ~     ~! 	  ~ch \   ~6}            V\   &     W         io V+  X%G            ret Y\   l    /\        @      Y  io /.  Hn 1
5  X%&              7Y  `  k  i  
G     7  "     _       io "(  hfd "0\   dbuf #   Xx # @   `       N  X     5.     (          
mE  >     }        ׵  int }  
) >   
e  q                   F        C(   + x    "    ! U   }%  N   -! !
         #  >    DIR /  %    E  >    ( 4  	@f     ! !   z  j      2      j           >    	Z  $   	"  #  s% L<$ j              % 	9( j        
    -              j   -     2  j   F       "* \  \      #    
t  L    } j            	o #   	.  $   tw j        >         j   11     ,      N  err (j   ^buf 3   ^T  ?2   ^sys    ^L{ %   ^% N  ^  4  _    ^  >    [% oj   0     r         ! o8  Xrm q   hret rj   d * b\  o0     P         dir d\  `rm e   h x& ]P0              y( ]   h ! S   /     n       Q  L{ S#   Xy( U   ` ! N/            |  y( N   h m( D   U/     n         L{ D$   Xy( F   ` # ?,/     )         4 ?#   h  2   .     1         mnt 4   h P %   .     B       D  mnt '   h     w.     B       s  mnt    h # 5.     B       K ,   hq A   `  N     N       ]3             l      }      ׵  int }  +K  -G     c   e  c     c           mE  G   F          G          G      3  <  5\    I  8	     9	   <g  :	   k  ;	    6  <	   (   =	   0  >	   8rh  ?	   @C  B	   H  C	   PY  D	   X1  F  `Y+  H  hn  J\   p  K\     M  w3  Nv   x  Q9   N  RN   /F  S    U  U ]   t  _    `    a    b	   6p  c   d\     f\     hj     m    [     -  -+p            G       t             	    	     	  E-  /  >-     q /       @  G    
- %U  	       6-    z       G           G   G    ;  \                a-                	  i- y            \   &      G    Z-    B    \          b           }        5           \          , \   ]3           buf $   _p- 0   _>- D  _fp   _
V    _len 	   _p    _
rm    _
q /  _  B   	  N       7                  }        ׵  int }  o     o   v     8\      {          F  tw \      j   2   {   	  7\      {       \   
- \   7            8  @ +   _M@ 	8  _cpu 
\   _ o   2     ?   	  N       7     %            - (E   . N   	^   ^   
2     -     ..     -    8.    J.     }        ׵  int }  +K  -2        e               3  <  5    I  8	     9	   <g  :	   k  ;	    6  <	   (   =	   0  >	   8rh  ?	   @C  B	   H  C	   PY  D	   X1  F  `Y+  H  hn  J   p  K     M  w3  N   x  Q   N  R   /F  S    U  U ]   t  _    `    a    b	   6p  c   d     f     h     m   [     -  -+p       	     
2       t          	     
2       	  99     P    -         0     - 	  - 	  - 	  0  	hx     <  	px     H  	     / {            ^   i. 8     A         U )  hKQ   `-   X -    7            G "  ~V  	
  ~err 
   ~  5     N       8     m         P  mE  >       int _     X   }      ׵  }  X     F  	tw L         >   S   
 )/ #/ L      L      2    !    8     m       / L   \buf %   P@/ 12   Herr L   l  
   `  0     9     a      Y    - (A   . J   
Z   Z   .     -     	..     	-    	8.    	J.     }        ׵  int }  +K  -.        e               3  <  5    I  8	     9	   <g  :	   k  ;	    6  <	   (   =	   0  >	   8rh  ?	   @C  B	   H  C	   PY  D	   X1  F  `Y+  H  hn  J   p  K     M  w3  N   x  Q   N  R   /F  S    U  U ]   t  _    `    a    b	   6p  c   d     f     h     m   [     -  -+p       
     .       t          
     .         	  95       P       H:     |    j  .  {  (  F[  آ  I  	,d  
LA  d  >           ك  c  e  ?  q  U    K  [    -  :W      TV   |  !UE  "i  #{  $[X  %  &  '\  (h  )  *	  +3  ,T]  -  .|  /c  0  1  2f  3t}  47J  5  6M  78  8l  9t  :WK  ;  <G  <  =  >P  ?.C  @/E  AQ  B  Cn  D  EN  F.~  Gy  Hp  IE3  J̎  K\,  Lr  ME  N%6  O  PBr  Q  RmD  Sv  T@  UЬ  V74  W  X"  Y,  Zo  [,  \׋  ]O  ^  _[k  `  aV  b*,  c8  d_  e}~  fׁ  gaT  h  i3  j\  k_9  l  m  n1  oz  p2  qJ  rj  s؜  t#  ueO  v  w^  x  yF  z  {>  |Y  }  ~'  x  h   8  =  *  uJ  WR  M  c    =  c&  `  '    b  >  }  Up  +  *^    K/  N  t  3k  F)  <  IZ        Z  @  4  z	       ,  2  /  9    {  !t  E  3  
  N  R=    S  GI  "  >  c  N        -a    `    -  u     @  ݛ  {  m    _  e  V    Bs    #      e  Uj  e  e^  E-  !       / F  /    	  {/  A1 / G/ / /  U/ 	         O       Z   N1 
   h/   	xx      {1          !0 5   	            / ":     Q       f	  "fn "&        #:       X	  UN :     
   / 9            	  / -O  =   9   G @  R   N   $V  
  ~%q:     	  Q~ :     
   &-    9     J       
  / /O  k   c   G Q        V          '
  9        	
        
        
      (9       
  T1QTRQ 9     
    )/    
  /   u/   0 1   */ /  4     F0 	     ;             3     3   Gint ?     }  H%Y   I/ R      {/  A1 / G/ / /  :   %            4 '   ׵  }  +K  -K        e     4    -K  	   *L5 
,  0cpu 
       mE  
K        F  13   `  8K    J1 m  r  K?     	  	     %  L&  / 1    1    1 R   +u64 !  &  +u32 $  &  +u16 '  &  +u8 *  &  MO	  Q P?     $6 Q     z4 /   -3 .   42 .R   5 .I  *  3  <  5?    I  8	.     9	.   <g  :	.   k  ;	.    6  <	.   (   =	.   0  >	.   8rh  ?	.   @C  B	.   H  C	.   PY  D	.   X1  F!  `Y+  H&  hn  J?   pN  K?     M+  w3  N   x  Q   N  R   /F  S+    U;  U ]   t  _E    `O    a&    b	Y   6p  cT   d?     f?     h     mP   [  X  O-  -2+p    X  13   ;  8K       2t  @  2  J  &    %Y  PP  Y  *3 4  4 5     2 6o    *1   B4    0nr ?   0map      1    QK    .   %  9R   H
     |    j  .  {  (  F[  آ  I  	,d  
LA  d  >           ك  c  e  ?  q  U    K  [    -  :W      TV   |  !UE  "i  #{  $[X  %  &  '\  (h  )  *	  +3  ,T]  -  .|  /c  0  1  2f  3t}  47J  5  6M  78  8l  9t  :WK  ;  <G  <  =  >P  ?.C  @/E  AQ  B  Cn  D  EN  F.~  Gy  Hp  IE3  J̎  K\,  Lr  ME  N%6  O  PBr  Q  RmD  Sv  T@  UЬ  V74  W  X"  Y,  Zo  [,  \׋  ]O  ^  _[k  `  aV  b*,  c8  d_  e}~  fׁ  gaT  h  i3  j\  k_9  l  m  n1  oz  p2  qJ  rj  s؜  t#  ueO  v  w^  x  yF  z  {>  |Y  }  ~'  x  h   8  =  *  uJ  WR  M  c    =  c&  `  '    b  >  }  Up  +  *^    K/  N  t  3k  F)  <  IZ        Z  @  4  z	       ,  2  /  9    {  !t  E  3  
  N  R=    S  GI  "  >  c  N        -a    `    -  u     @  ݛ  {  m    _  e  V    Bs    #      e  Uj  e  e^  E-  !     9R   /m
  q3  =5  4  5  g3  4   B2  @X1  4 3 2 3  :4 
  	Y   	1  	1  	`   3/7 Y   
  	Y   	K    R1 1 K   
  	   	  	?    S3 O#
  D  T/ 
  	`   	   4 3{1      	?    ;Ⱥ  :?   -  	   	  	-   1  ;2 1?   S  	Y  	?   	   4 :  d  	Y    3A7 Y   {  	K    1   K     L         1 C  W  C   2        i ?       j 	?   W  G  k ?       !-2         K     K     s       Q              '   L       L              8       '  L     L            $  8         L     O       	  #  !    0  ,  #  9L     9L               #  #   "#  9L     9L            '#  B  @  #  L  J       L       !    X  T    k  g    L     9       	  |  z        #  L     L               #  #   "#  L     L            '#      #         #  =M       U  #      #       #  HM       *  #      #       -  wM       N  .      .      .      /  M       "-  /      /      0  M       <0      0  '  %    M     d  UL $ &1$#  #  M         #  2  0  #  <  :   #  M       *  #  F  D  #  P  N   <L     *    UU <M     *    UT N     4     2 ?    I              1 /  d  X   2 J      !3       !2 ?   >  6  i ?   y  k  j 	?       k ?       !-2   C  ?    #I      #I     m           T  R    `  \  '  <I      <I            )  8  q  o   '  @I     @I            $\  8  {  y     MI     C       	            #  qI     qI               #  #   "#  qI     qI            '#      #           I     W                  K     A       	        	    #  5K     5K               #  #   "#  5K     5K            '#  #  !  #  -  +     '  I     b    8  ;  5   #  6J     w  $  #  U  S  #  _  ]   #  ?J     ?J     	       ,d  #  i  g  #  s  q   '  cJ         8    {   #  J     J              #      #       
I     d    U| " $ &1$ 
J     4  D  U $ &1$} "T $ &1$~ "#Q | "1$# 
J     !  \  T}  
J     S  t  U}  J     ,'  YK     ,'  
aK     *    U~  
K     d    U| " $ &1$ K     4       =t6 |    5a |9&  5b |W&  #,i ?   ,j ?        T4 m  H     D         map m>&      !o o      '  5H     5H             x"  8       #  5H     5H     	       x	  #      #       TH     4   5 _  G     z         map _>&      cpu a      !o a  4  0  idx d?   O  I  
G     H    U| T}  
G     H    U| T}  
G         U|  
H     4   Z6 Z  PG     >       N  map Z;&  j  f  #  pG      pG             \@  #  ~  |  #       G     4   5 E  F              lhs E5&      rhs EU&      nr G?       UF     7       Q  idx S?       #  	G     	G             T  #  	  	  #   	  	   "#  	G     	G             T,#  .	  ,	  #  8	  6	    '  F     F            O  8  F	  D	   '  F     F             P  8  P	  N	   IG     4   "4 @  0F     z          ; @3&  \	  X	  cpu @I  r	  n	    KF     A  B	    	  	    	  	    	  	  +  	  	  '  SF     SF            /	  8  	  	   >7  L  8  	  	  $D  "#  lF     lF            2 #  
  
  #  #
  !
     F     4   =5 '?   R  V; '2&  5cpu 'H  ,low )?   ?Q2 )?   #,idx 1?   ?5 2    -6 "  pE     7         map "8&  /
  +
  E     4   5    E     L       M  map F&  E
  A
  '  @E     @E             	  8  Y
  W
   #  FE      FE             )?  #  c
  a
  #  m
  k
   lE     4   U5   D     C         map G&  z
  v
  #  D      D               #  
  
  #  
  
   E     4   1 ?   D     >       H   ; 1&  
  
  '  D      D            :  8  
  
   D     4   2   @D     O       '   ; >&  
  
  idx H?   
  
  !o       '  `D      `D             
  8       #  D     D            
  #  )  '  #  3  1   D     4   1 ?   E  ; :&   'z3   C     S       Q  (cpu 0?   C  ;  ;   e  c  -  C       C  .  o  m  .  z  x  .      /  D        "/  /      /      0  D        <0      0        D     d  U:  3D     4   '5   >           !  65 4       ;   I  3  3 K       6 K       Wp .   -i ?   ,  (  1 	?   M  =  3       -tmp %      2 ?       Xout Y4 a?     @     A4 ?   	     3 ?   J  F  Z/@     8       u2 ?       /  b@        /      /      g@     2  T1Q	V'     R
     @      !3 K       '3 K        >     
  
?     
  H   TQ0 
m?     S  `   U~  
?     
  ~   TQ0 
@     !     U T~  
@     
     U~ T
s  $ &1$ A     j$  
^A     
     U1T	V'      cA     j$  mA     ,  wA     4   B2   @;            #  61 3?       63 S#  3  )  V2 	1  h  ^  ;       -i ?       -j 	?       -  \;     "   g"  .  :  4  .  T  P  .  h  b  /  ;     9   "N"  /    }  /      0  ;     9   <0      0        x;     d  U} 1$#  Q.  ;     I   "  `.      l.      x.      ;     4  UsTQ} 1$  #  ;     ;            #  #      #       #  ;     ;             L#  #      #       +.  ;     ;            #  8.  #  !  D.  -  +   
;     m
  #  T} Q2R	 ;      8<     4   ,  2   #  ; G&  idx Q?    B1 ?    ;     9       j$  (a    9  5  (b /  K  G  3 #  ]  Y  3 %#  o  k  9;     4   'I3 u  A     F      &  ; w    }  &  A        w%  &      C&  HC&  P
A       $  U	T&     THQP A     Q  A     S   &  B     B           |	&  &      '      '      -  9B        ]	+&  .      .  
    .      /  nB        "	&  /  '  %  /  1  /  0  nB        <0  <  :  0  F  D    SB     d  U $ &1$#  7'    F&   '  W  O   
B     
  ^&  UT 
*B     
  v&  US C     
  U1T	HW'     Qs X  C     4   4 h  &  ; j  buf k.   x l	1   n1 N  ,'  ; P  1 Q?   a1 Q?   #i _?     [c2 D=            *  (map D-    v  .  =     Y   G(  .      .  =     Y   	.      .      .      .      /      0  =     i   L(  0  *  (  >0  i   $0  0  =     	t   		1  4  2  1  >  <  1  M  K     /  =     =            	/  X  V  /  b  `  /  l  j  0  =            $0  0  |  t  0      N0  =            S0           ,  >        H|*  ,      7,     n*  ,      f/  >     >            4)  w/      0  >     >            F	0  &  $  0  >            $0  0  >     >            		1  0  .  1  :  8  1  I  G      ,  3>     .       ,  T  R  /  Y>        4/  n  l  /  y  w  a>     4  U	T&     T1QJ    \3>     S   v>     4   '3 :  P=     X       ,  (map :=      o <      /  p=     p=            ?,  /      &/  p=     p=            r7/      A/      M/      Y/      0  p=     p=            S+  0      0  p=            $0  0  p=     	p=            		1      1    	  1         /  {=      {=            ^	/  %  #  /  /  -  /  9  7  0  {=            $0  0  C  A  0  M  K  N0  {=            S0  W  U       =     4   )2 1,  map 12  #A4 4?   	     3 4?   #u2 4?      '4 '  <     Q       -  ; )  a  _  ]-  <     &       )-  .  .  k  i  .  u  s  /  =     =     
       "-  /    }  /      0  =     =     
       <0      0        =     d  U:  A=     4   ^f4   +.  1 .?   ;   o    _5 Q.  map 0  1 9?    D2 Y   .  {5 [   F5   6 1   44 .  .  map E     D6   .  r (.   6 ~  /  i ~)R   r ~8.  old R   new R   val R    )3 p&/  r p-.   4 Q  f/  r Q(.  old SR   new SR   val SR    ;3 DR   /  r D</     )*5 :/  r :-.  n :=R    DT  m?   /  / m^  u/ m<   4 4 E?   p0  v E5p0  old E<?   new EE?   #K2 G	?   75 G	?   : G	?   .<0  ; G	u0   .N0  ; G	z0   .`0  ; G	0   #; G	0               )I4 '0  v ')p0  i '0?    3 ?   0  v /0  .0  __u 	0   `	a 	F   b__c 	+    #  )2 ,1  p C,1  res LY   T  U?      /+.  @<     4       t1  8.      D.      t<     4   /-  <     c       b2  .      .      .      /  <     <            "22  /      /      0  <     <            <0      0  '  %    
<     d  T2  Us  $ &1$# <     4   /  E     z       K3    4  0    R  F        +      '  E     E            /	2  8       77  +  =3  8      D      c#  E     6  2 #      #        *F     4   /  `H            4      	    #    '  H      H            3  8  7  5   '  H     H            $3  8  A  ?   d  H     6       4  	  S  I        #  H     H             Y4  #      #       "#  H     H            '#      #        H     4   e/ / E2 2 E3 2       ,0 
     N           J/    }  -.int >   [   %J     T         ׵  }  +K  -.     |   e  |   7 >   T   7 a   mE  	.   F     T      &.    /   / -K  
   1 `   1 g   1 5   u64 !   +  u32 $  ;  u16 '  K  u8 *  [  0O	  Q P>     $6 Qj    z4 /`   -3 .g   42 .5   5 .     3r  <  5>    I  8	     9	   <g  :	   k  ;	    6  <	   (   =	   0  >	   8rh  ?	   @C  B	   H  C	   PY  D	   X1  F  `Y+  H  hn  J>   p1  K>     M  w3  N   x  Qg   N  Rn   /F  S    U  U ]   t  _    `    a    b	<   6p  c   d>     f>     h     m    [    2-  -!+p       T     &.     ~  !t    !      r  %  3P    3 4  4 5     2 6    6 	,  "pid 
	    6     6 k  B4    "nr >   6 >   "map k      z  4.    52 1>       >   J   ' 6    <    7/7 <     <   .    7 l>   PR     q       F  K< l2F      pid lA   +  '  8pR            8  (i q>   A  =   	R        ,  	7 b    R     H         map b4F  U  Q  idx b=>   o  g  	HR         8 ]>   Q     >         K< ]1F      	Q        )7 WP            	  map W3F        P       Y          P     &  	      &  .  (  0  H  D  <  [  W  H  n  j    P     6         }  *	  6    ?  P     	A  	L      V      b           P     P            	'      1      =      I  P            J  V      b        P                         ,Q     L  Zz	        *  \    H  >  9  l  8	    s  o    ,Q     ,Q            H          ,Q     	,Q            F	      	  ,Q              ?  ,Q     ,Q            	L      V      b            |Q     *               Q     w  H      	      Q       U	T&     T1QM    #OQ     {  V	  Us T| 	WQ       :|Q       UU   	Q        7 PF  `P     X         map PFF  
    U  P     P            S}  b      m  P     P            r}  (  &    2  0    >  :    S  Q    P     P            S
    ]  [  	  P              ?  P     	P            	L  g  e  V  q  o  b    ~       P      P            ^	'      1      =      I  P            J  V      b        P                       	P        6 C  K< C=F  i F>   ;4 H>   	     
3 H>   
u2 H>       x7 >F   P     <       .  <WP     .     U1T0 	\P        7 -F  0O            v  7 -8>       7 -Kv      =K< /F      (i 0>   :  (  3  aO       /$  D      P      [      g      t  O                                    O                     #    O       UsT0Q| 4$   fO       U|4$    O     O            9&    8  6    B  @    O     O            <  M  K    W  U    #O       D  Us T #P       h  Us T|Q	 	 P           6 (   N     =         map (5F  d  `  idx (>>   z  v  	-O        )_7 #N     <       3  map #7F      idx #@>       pid #K       	N        >7 F  t  map JF  nr S>   
T  	   
5O >    H7 
  map 
<F  5O 
E>   nr 
P>   
T  	    +6 9<     {5 9<   6 9>   6 9    D6       r (      6 ~   U  i ~)5   r ~8  old 5   new 5   val 5    3 pm  r p-   4 Q     r Q(  old S5   new S5   val S5    ;3 D5     r D<      *5 :  r :-  n :=5    +T  m>     / m  u/ m<O   ' 4 E>     v E5  old E<>   new EE>   
K2 G	>   
75 G	>   
: G	>     
; G	     
; G	     
; G	   
; G	       e  V  F  6  I4 '  v ')  i '0>    3 >   :  v /:    __u 	   ?	@ 	E   A__c 	      2 o  p Co  res L<   T  U>       B3   N              D      P      [  !    g  G  C  t  cN     cN     '           Y  U    f  d    n  l    x  t    cN                         N       Us  $ &#4$} "T0   	[N       	N        C/ / $3 2 $6 6 $A7 77  A     Q0 %
    R     s      5  3     63   Rint     }      4 'u   ׵  }  +K  -[   7 ?   S  |        mE  	[   T7    4 
i   -K     :     / tC b   1 M   @ ?   1 T   : *5  F  <u64 !   <u32 $  <s8 +   UO	s  Q P?     $6 Q\  @ c  H d     d   6    @ g  /G h    A k  H l   9 l   6      V(M  val     ena    run    id    N      E(g  F  7RC g   -   w  =[    FC (  &M    L5 
  cpu 
     z4 /F   -3 .M   42 .T   5 .5  -3     =[     W9 T     < > 4? @ S< <  < @< !>  !A  !B  !9  !?  !?   !r;  @!@  ?    :    8    2>    v9    ;     +:   @ >    A    B     X> T   m  ; @8 = l: C w?   1  Z; 
)  @ 
)   15  : 
  = 
   1n  ? 
)  &A 
)  z< 
)  ; 
)   1  {A 
)  > 
)  _8 
)  ; 
)   Y  8= 
   8
?   8pA   8C    1  B 	  F   ZC s  % 
   T  
  j 
)  &  B 
)  G 
)   q< 
)  @7< )  AA )  Bh; )  C@ )  D> )  E8 )  FtB )  G9 )  H6 )  I@ )  J8 )  K= )  LO )  M= )  N; )  O*? )  Q= )  RA )  S_> )  T[B )  U@ )  VK )  W8 )  X9 )  Y< )  ZB )  [4P )  \}K )  ]:L )  ^B )  _R )  `> )  aI )  b3@ )  c; )  d C )  e6C )  f9 )  g8 )  h&  0(B 
  4&5  8&n  @B )  H[: )  P^=   X9   \[? )  `
A   h=   lyC   n8   p&  t)> ")  x; $)   < %)   3 4  4 5s     2 6s  1   B4    nr ?   map    6  -    >[    AA 0$	  A    @   PA <   tid G  ( EME	  7PA R	<  7C WE	   -  U	  =[    p= ,	  A -   id .	<  ? /
  idx 7	?    cpu 8  $tid 9   (: <   ,.@ =  0&$	  8 [? [
  A \   N9 ]  ; _
  1; f
  K< g  fd hv  9 iv  u= jv  id k	{  ids l	G  F m
  C q  < t	?   F {
  C 
  9 
  H> 
  \idx 	?     	    6   B4    nr ?   6 ?   map    
  ]? (v  8 		    A 
	   wD 	   : 	   bC 	    ^.<   (   <   -3     >[    =     _  	     : `z  Eg  
     	?   fd 	?   cpu   B4     	<  5O 	<   end  	<  (H !
  0 "	<  8: #  @l? $
   HB %   PH &  X B )  ? *?     +?    6 	  pid 
	    6 .    -    >[    `N1 T   .E?   	      "@ *?     	?   	[   G ?     4  	[   	[    "U 		   T  	?   	   	    "9 :?   o  	  	o   w  "@ 2?     	  	  	?   	   z  .8 0  	  	  	  	   .; 4  	   .&C   	v   ?X= f?     	?    ? C|     	|   G @R  %  ?   "2 4  >  	>  	?      "1 <?   Y  	>   @x7 
%  @4 "
  "d< v    	?   	?   	    a    	    .7   	   .c2 /  	
   "8      	    H: Wm     C      Y  n  W;o      : X      A XY  3  /  A ZR  O  E  Sn     A      S9 7{   l             Isid @    x  Itid IG      F 7S      !I 9      res :         bG ;?         ''  8  ; C        b@l            A C  !  !    JMl     	       q  ; C  !  !  (A C    
8  (l       @	  8  "!   !  8  ,!  *!  8  (l       D	8  7!  5!    
8  l     2  N  8  A!  ?!   
7  l      B  R0  7  K!  I!  7  U!  S!  7  z!  x!   
A8  l      W  Q  N8  !  !  Z8  !  !  g8  l      g  Mt8  !  !  8  !  !  8  !  !    zl         U0 m     A   U	        :; 0  k     P         ? 0G
  !  !   l     A   H: ! k              ? !-
  "  "  pos #   ="  7"  n #&  ["  S"  '    A *  {"  y"   '    A *  "  "   '    A *  "  "   97  pk     pk            +  7  7  pk     pk            7  7  tk      tk            f7  "  "  8  "  "  28  xk            :8  8  xk     xk            Z9  "  "  9  "  "  9  "  "       -k       Mk         U|h k       k     A     F: ?   `j              ? -
  "  "  !8 8?   #  #  A C?   P#  D#  j     q    ULTHQ j         ULH $ &3$ j        k     A   B9 	   j     5         ? 	=
  #  #  Uj     A     ?<   i     6       \  ? @
  #  #  j     A   ; 
  i     6         ? :
  #  #  i     A   '8 ?   h              ? 1
  #  #  '$  D   #  #  err ?   !$  $  i ?   U$  M$  3     k                 |$  t$  
7  i        g  7  $  $   )        $  $  4   Yi          	!  $  $  !  #!  $  $  /!  $  $  ;!  %  %  
#7  Yi       K  47  %%  !%  ?7  8%  4%  I7  [%  W%  T7  i       	e7  l%  j%  p7  v%  t%  z7  %  ~%    >i       T$@Q}     h     C  i     A   f@ ?   g              ? ,
  %  %  i ?   %  %  err ?   %  %  
6  g      /  	  6  &  &   3   D  q                 6&  ,&  
7  g     T  `  7  d&  ^&   )   n     &  ~&  4   ah     y     &  &  	!  &  &  !  &  &  #!  &  &  /!  &  &  ;!  &  &  
#7  ah       T  47  '  '  ?7  "'  '  I7  E'  A'  T7  h       	e7  V'  T'  p7  `'  ^'  z7  j'  h'    Eh       T
$Q0    h     A   z@ ?    g            7  ? 0
  z'  r'  hC ;?   '  '  3     )                 '  '  
7  -g           7  '  '   )        '  '  4   g     	     	!  '  '  !  (  (  #!  &(  "(  /!  9(  5(  ;!  J(  H(  
#7  g         47  h(  d(  ?7  {(  w(  I7  (  (  T7  Eg     $  	e7  (  (  p7  (  (  z7  (  (    mg       T
$Q0    g     A   #= ?   f            0  ? +
  (  (  i ?   	)  (  err ?   5)  /)  
6  5f      s    6  U)  O)   3     "                 y)  o)  
7  Kf         7  )  )   )        )  )  4   f          )  )  	!  )  )  !  )  )  #!  *  *  /!  #*  *  ;!  4*  2*  
#7  f         47  R*  N*  ?7  e*  a*  I7  *  *  T7  mf       	e7  *  *  p7  *  *  z7  *  *    f       T
 $Q0    f     A   < ?   0e              ? 2
  *  *  < =?   *  *  *cpu   idx ?   +  *  err ?   $+  "+  
   e      H  	     0+  ,+  	!  C+  ?+  !  \+  X+  #!  q+  m+  /!  :;!  
#7  e     X  s  47  +  +  ?7  +  +  I7  T7  ve     h  	e7  +  +  p7  +  +  z7    e       T
 $Q0  de     #    Ts  e     #    Ts  e     C  f     A   A ?   pd               ? /
  +  +  hC :?   +  +  3                       ,  ,  
7  d        z  7  #,  ,   )        4,  2,  4   d     "     	!  @,  <,  !  Y,  U,  #!  n,  j,  /!  ,  },  ;!  ,  ,  
#7  d     -  f   47  ,  ,  ?7  ,  ,  I7  ,  ,  T7  d     =  	e7  ,  ,  p7  -  ,  z7  -  	-    d       T
 $Q0    )e     A   A6= ?      ? 5
  +ioc 
?   +arg    hC 
?   < ?   (*err ?     A@ ?   G!  ? 1
  +ioc <?   +arg G   hC ?   < ?   *fd    8 ?   `           2&  ? )
  !-  -  hC 4?   f-  \-  < E?   -  -  n  #o  -  -  T  	   -  -  fd   N.  B.  G <  .  |.  Kbuf w  
&  `     L  _"  '  .  .  '  .  .  &'  .  .  3'  .  .  @'  /  /   
#7  a      a  "  47  6/  4/  ?7  @/  >/  I7  J/  H/  T7  +a     q  	e7  \/  Z/  p7  f/  d/  z7  p/  n/    
6  [a       #  6  |/  x/  6  /  /  6  /  /   
#7  |a        #  47  /  /  ?7  /  /  I7  /  /  T7  a       	e7  /  /  p7  /  /  z7  /  /    
2&  a        #  @&  /  /  L&  0  0  Y&  +0  '0  e&  >0  :0  r&  S0  M0   
}&  b       
%  &  v0  l0  &  0  0  &  0  0  &  0  0  &  1  	1  &  l1  b1  &  82  42  &  T2  L2  &  2  u2  
&  b       Q$  '  2  2  '  2  2  &'  2  2  3'  3  
3  @'  -3  '3   
#7  b        R^%  47  I3  G3  ?7  S3  Q3  I7  ]3  [3  T7  b       	e7  p3  n3  p7  z3  x3  z7  3  3    *c       {%  U1Ts  Ec     4  %  U~TQs  c       %  U Hd       %  U Md        a     4  %  T %b       c     T  $&  T|  [d     A   L0B {}&  ? {:
  +buf {F{  n  |&o  G ~<  *n ?    AB N?   &  ? N6
  hC NA?   < O?   n  O.o  T  Q	   *fd R  G S<  P T{  *idx U?    cw8 1?   L'  ? 1.
  G 3<  M@ 4?   T  5?   *nr 6?    ? '   p_            (  ? '0
  3  3  hC ';?   3  3  < 'L?   3  3  fd )  3  3  
#7  _        );(  47  p4  n4  ?7  z4  x4  I7  4  4  T7  _     +  	e7  4  4  p7  4  4  z7  4  4    
#7  _      6  +(  47  4  4  ?7  4  4  I7  4  4  T7  _     A  	e7  4  4  p7  4  4  z7  4  4    `     A   9 ?   ]           f,  ? )
  5  4  ; 4?   75  35  ret ?   O5  I5  idx ?   s5  g5  < ?   5  5  Kmp z  '  C+  fd 	  5  5  map   6  	6  cpu   '6  %6  
#7  ^       *  47  46  06  ?7  G6  C6  I7  j6  f6  T7  I^       	e7  6  6  p7  6  6  z7  6  6    
#7  z^        
*  47  6  6  ?7  6  6  I7  6  6  T7  ^     ^            	e7  7  7  p7  7  7  z7  !7  7    h^     #  *  T ^       *  U~ T0Q0R0 ^     t  +  U~ TR ^     #  .+  T ;_     f,  U}   97  ]     ]             v+  7  +7  )7   96  ]     ]             +  6  57  37   94  ]     ]             
,  .4  C7  =7  :4  [7  Y7  F4  f7  d7  ]     q  Q`  
6  ^        1,  6  q7  o7   
7  "^       X,  7  {7  y7   o_     A   /S@ ,  ? ,
  #idx ?   5< ?   (#fd 	    M@ [            .  ,? /
  7  7  ,hC :?   7  7  Bb.  [     ^       .  o.  {.  .  7  7  7  [     @  ;-  7  7  7   2.  [     @       .  7  7  0#7  [     [     "       -  47  7  7  ?7  	8  8  I7  8  8  T7  [     [            	e7  %8  #8  p7  /8  -8  z7  98  78    [         ;\     A   /L= &.  ? +
   /9 =.  ? -
   /< b.  ? .
  (#idx ?     $WA .  ? 9
  hC D?   5< ?   (#fd     NJB ~?   PX     >      w3  ,? ~)
  W8  A8  ,; ~E
  8  8  ,K<    9  	9  ;cpu   ^9  T9  ;idx ?   9  9  O< ?   9  9  ;err ?   4:  (:  dout j[     '0  /  C49 
  	     E[     e   J [     0       /  C ; "  	     [     Y   'M  1  ;fd ?   l:  f:  C< ?   X5A   3  Y     {  	b0  3  3  :  :  3  4  :  :  4  :  :  Y       U
*TRY0  #7  X        0  47  :  :  ?7  :  :  I7  :  :  T7  Y       	e7  ;   ;  p7  ;  
;  z7  ;  ;    w3  Y       
1  3  $;  ;  3  @;  :;  3  \;  V;  3  x;  r;  3  ;  ;  3  ;  ;  #7  -Y       u47  <  <  ?7  (<  &<  I7  :<  8<  T7  AY       	e7  L<  J<  p7  V<  T<  z7  `<  ^<     h[        S4  [Z        2  d4  j<  h<  p4  v<  r<  |4  <  <  D4    2  4  <  <  4  <  <  )4    4  <  <  #7  Z       J47  <  <  ?7  =  =  I7  5=  1=  T7  Z     %  	e7  V=  T=  p7  `=  ^=  z7  j=  h=      `Z     q  U~ Ts Q4  X     #  3  U~ T0 X     C  3  U~  Y     #  93  U~ T|  Y     .  Q3  U|  OZ     C  i3  U}  [     A    < d?   3  ? d,
  hC d7?   < dH?   < dU  5F f
  #fd g    B ]?   4  N9 ]-  pid ^   cpu ^"  < ^+?   =  _[     < U?   S4  ? U6
  !8 UA?   A UL?    e9 A?   4  ? A-
  !8 A8?   A AC?   (#idx F?   5< F?   (#fd J
     M? 5T     b       ^5  ,? 5,
  |=  r=  0^5  T     T     $       775  h5  =  =  	U       U       !U        f=U       P5  UU BU     A   /> +u5  ? +*
   N: !
  S            6  ,N9 !<  =  =  O? #
  =  =  06  S     S            &]6  6  =  =  6  =  =  6  =  =  8  S       -6  8  	>  >   8  S      S            8  >  >    S       v6  U
 wT     A   /= 6  ? *
  N9 I  idx ?    g6 9   6  {5 9   6 9?   6 9     : &?   7  xy &2v    YC !?   #7  xy !2v    D@    T7  xy 4v  x ?   y I     B@    7  xy 6v  x >?   y E?    L2A 7  +n 6  +h L  /G    $m> 7  M@ 4   $> d7  M@ d7   $? WA8    W2  H WK  h"8  #__u Z"8   iZ7 Z  j__c Z    $M? Kg8  new K4  !I KK   $l8 &8  new &1    '  H (   $~: 8  t 5    : AG  8  val AG  ԓ A1T     {> <G  8  val <)G   $= +9  p >+9  res G   T  P?    09  k%6  R            9  6  >  >  6  4>  0>  6  I>  E>  8  S       9  8  \>  Z>   08  S      S            9  8  d>  b>   S     A   %^5  T     Z       6:  h5  r>  j>  T       T       lT       T     A   %S4  PU            b;  d4  >  >  p4  >  >  |4  >  >  D4    1;  4  ?  ?  4  C?  ;?  )4    4  e?  c?  #7  U       J47  ?  ?  ?7  ?  ?  I7  ?  ?  T7  U       	e7  ?  ?  p7  ?  ?  z7  ?  ?      U     q  T;  U| T} Q4 1V     A   %=.  @V            <  G.  ?  ?  mS.  SV            <  T.  @  @  6  gV        ;  6  >@  <@   Pb.    o.  {.  .  P@  F@  7  yV       <  7   2.  V     6       .  z@  x@  0#7  V     V     !       <  47  @  @  ?7  @  @  I7  @  @  T7  V     V            	e7  @  @  p7  @  @  z7  @  @    V          W     A   %&.  W     N       -=  0.  @  @  9W       ^W     A   %.  `W            /?  .  @  @  B.  W            !?  .  B=.  W            >  G.  2S.  W            T.   A  A  6  W       =  6  IA  GA   Pb.  #  o.  {.  .  [A  QA  7  W     3  >  7   2.  W     8       .  A  A  0#7  W     W     !       >  47  A  A  ?7  A  A  I7  A  A  T7  W     W            	e7  A  A  p7  A  A  z7  A  A    W           &.  X     X            0.  A  A  $X         PX     A   %f,  @\     9      A  p,  A  A  :|,  :,  nf,  P  A  p,  |,  B  B  ,  UB  IB  6  \     [  ?  6  B  B   7  \     k  ?  7   D,    A  ,  B  B  #7  \       k@  47  B  B  ?7  B  B  I7  B  B  T7  \       	e7  B  B  p7  B  B  z7  B  B    #7  \        @  47  B  B  ?7  C  
C  I7  1C  -C  T7  \     \            	e7  BC  @C  p7  LC  JC  z7  VC  TC    ]        G]        y]     A   %&  `            A  '  bC  ^C  '  |C  tC  &'  C  C  3'  C  C  @'  C  C  `     A   o/ /  BQ     ]0 
    <          T    }  ^P/ 1   n   {/  A1 / G/ / /  _int 
     4z         4 '   ׵  }  +K  -*   7 n        
z   4    -K     mE  *     / 1    @ n   1 1   : *@  F  Qu64 !   Qu32 $(  `O	t  Q Pn     $6 Q]  @ c  H d     d   4  
  @ g  /G h    A k  H l   9 l   
  
  z4 /   -3 .   42 .1   5 .@  &z   ?  ,*       R   7 a   R
y  Bidx 
n   Bptr 
8    1	  
	  -W   =  
1       
  nr 
n    G  
n     
n   wD 
  1	  
!   G $  fd &	n    $: '     (    
  
y  P]4  1   
!H  V   L  	   3 4c  4 5t     2 6H  L5 
  cpu 
     1   B4 c   nr n   map    4  &o    C*    a> 1   m
  ; @8 = l: C w?   5+  Z; 
4  @ 
4   5L  : 
(  = 
(   5  ? 
4  &A 
4  z< 
4  ; 
4   5  {A 
4  > 
4  _8 
4  ; 
4   b  ;= 
(   ;
? (  ;pA (  ;C (   5  B 	(  c   dC   % 
(   T  
(  j 
4  -
  B 
4  G 
4   q< 
4  @7< 4  AA 4  Bh; 4  C@ 4  D> 4  E8 4  FtB 4  G9 4  H6 4  I@ 4  J8 4  K= 4  LO 4  M= 4  N; 4  O*? 4  Q= 4  RA 4  S_> 4  T[B 4  U@ 4  VK 4  W8 4  X9 4  Y< 4  ZB 4  [4P 4  \}K 4  ]:L 4  ^B 4  _R 4  `> 4  aI 4  b3@ 4  c; 4  d C 4  e6C 4  f9 4  g8 4  h-+  0(B 
(  4-L  8-  @B 4  H[: 4  P^= (  X9   \[? 4  `
A (  h=   lyC   n8 (  p-  t)> "4  x; $4   < %4   RM  DPA R	G  DC W   &    ,*    p= ,7	  A -   id .	G  ? /.
  idx 7	n    cpu 8o  $tid 9K  (: <K  ,.@ =o  0-  8 S? [.
  A \   N9 ]  ; _3
  1; f3
  K< gy
  fd h
  9 i
  u= j
  id k	
  ids l	R  F m.
  C q  < t	n   F {

  C 

  9 

  H> 

  eidx 	n     
7	  
  6 y
  B4 c   nr n   6 n   map    
8
  f? (
  8 		    A 
	   wD 	   : 	   bC 	    g.< }  ( 
~
  
G   SG   wD    D 	n   E 

  PF 

  GD 3
  [D 3
   K< y
  (G 	n   01R    8G    @D !  `<9 "  `<D #  h<E $  p<fH %  x &    ,*    : `  Eg  
8     	n   fd 	n   cpu o  B4 c    	G  5O 	G   end  	G  (H !

  0 "	G  8: #  @l? $
8   HB %   PH &  X 
  D )  
  E    .
    n    

  
  B )  ? *n     +n    ;H ,  
   T      
  n    wE .%  
*  Tn   H      n   o   ;F 0}  idx 1   get 2  9 3   &z     C*    =   
  E     6 	  pid 
	K   6     &    C*    hN1 $1   E?      
8   ; 4     8 05      
     @ 2n   Z      n   o   	7 K  u  y
  n    hE 5     5 n       o   
  /   :   u   F U5 @
       F: n     .
  n   n    Q  
/n       n    
  {H 6'     $  
0n   L       L  8    
Q  Ef    n   8    GuH E n     n   n   F   
-n       n      &   Q  
3n       n     8 n     y
   GG ?    n   8          GVH  GG ?  *  n   8          GD 8 ?  N  n   8       HR  #%Z  
n   @  *n   {  n   *   F f@ !*n     .
   #= !'n     .
   L= !   .
   JB !n     .
  3
  y
   ? !  .
   i  "  8    8  
(     8 8   &      2 +n   A  A  3
   
3
  7 %y
  \  y
   Hx7 
%y
  7 z  y
   z3 )"3
    n    2 4o      n    1 <n        1 -"3
    3
  3
   t6 
         5 S
         c2 /$  3
   Z6 X
  :     3 *"3
  P  3
   HI3 !"3
  -6 I
  r     V  
'    n    .E A     b         G A6  !D  D  ? AQ.
  MD  ED  Iݑ     E@       <Q   /E 0n                 G 00  yD  qD  ? 2.
  D  D  E 3n   D  D       <  d  Us T0       <  |  Us  H     <    Us  z     <Q   .F &p     i         G &2  D  D  =  }  /G ).
  E  E                A )  +E  'E   J          ,  CE  ?E    [E  WE    wE  oE    E  E  U  ,    E  E     ِ     <Q   
  KF   t 2  F K.
  	? .
  n n   !  	A    "	A     /F        V       Y  G ,  E  E  #map F  E  E  H 
  F  E       <Q   .H 0              G .  1F  'F  >i  n   mF  aF         ˄       ݄         Us 0          UU#      <Q   /)F n         u         G +  F  F  ; 7n   F  F  Lmp   HLops H  P         UUTPQH      <Q   jD n     J#  G /  F  F  #ops #J#  G  G  #mp   G  G  ;   aH  [H  ? .
  H  H              7  A   H  H               a  A   H  H   O#  x          _#  H  H  k#  H  H                        :$  (        
   J$  'I  I  V$  I  {I  c$  I  I  o$  7J  1J  |$  bJ  VJ  $  J  J  $  J  J  $  J  J  )$  V$  ׈     6$       :         )$  )$  ψ     '%  UTQ RX0Y   $  2  C   )$  )%  J'%        O  u%  EK  ;K  7%  K  {K  C%  P%  K  K  ]%  i%  %  K  K  %  eL  [L  %  L  L  1%  %  L  L  %  OM  EM  %  u    %  M  M   %    	   %  M  M  %  $N  N  %  lN  VN  
&  N  N  &  O  N  "&  cO  UO  "-  ӊ        i  1-  =-  O  O  I-  O  O  V-  O  O  b-  %P  P  n-  ]P  WP         _  U~T|  1     f    U| T4Q
  _         U~T|       f  U| T4Q
   mC  E         =D  }C  |P  xP  C  P  P  C  P  P  'C  ^        	C  P  P  C  P  P  C  
Q  Q    C          O  D  )Q  %Q  D  JQ  FQ  'D          <,D  iQ  eQ  6D  Q  Q    *  X      '  r  *  Q  Q  +  Q  Q  +  Q  Q  !+  R  R  -+  RR  LR  mC  _       C    }C  yR  uR  C  R  R  C  R  R  'C  x      ]  	C  R  R  C   S  R  C  S  S             T~       Z    T0          T~       Z  T0  (  .      w  \  
)  )  6S  2S  #)  PS  LS          5  T       [  U Ts Q         U T} QR          U3T	W'     QR|   Ǌ       U~ TQ| R          U~  O     -  +  U T} Q~ R0X|  M       g  U3T	W'     QR| X _     _    U| T
$Q o     u    U~          U T} QR0          U3T	W'     Q0R|   "     (  U~ TQ| R        C  T  ҍ     e  U Ts Q0          U3T	W'     Q0R| X~ ,     _    U| T
$Q~ <     u    U~  _     -  U T} Q~ R0X|   (    $   (  lS  fS          T~"   -       9       c       U3T	 X'     Q	`T&     R| X  y#          	"  #  S  S  #  S  S  #  S  S  #  .T   T  #  zT  jT  )#  #  T  T  #  U  U  V$       $    {!  )	$  )$       '%  U TQs RXs Y|          #       N       !  U3T	X'     Q	PT&     Rs X~  ȇ     Y  !  U         U0T	`X'       {-          (#  -  TU  PU  -  pU  jU  -  U  U  -  U  U  -  U  U  6-              "  -  U  U   -    "  -  V  V   *FD  7      7            "  VD  #V  !V                 P       U   ݆       $#  Us         <#  U|       <Q   
H  7F n   y#  G 6  	G n    7G n   %$  G "  ops GJ#  mp   	7 n   	1 n   	G n   cpu n   	< n   WH 5$  	PT&     X^E "	9 n   	H n     &   5$  ,*    4%$  7F zn   %  G z%  ops zJJ#  mp {  	7 }n   	1 ~n   cpu n   	< n   idx n   	G n   WH "%  	`T&     X^E !$  	9 n   	H n    "	9 n   	H n     &   "%  ,*    4%  78D n   (  G $  ops IJ#  idx n   mp *  H 2n   < n   9 Z  H (Z  G @Z  	F  o  	? !.
  	G "n   !%  	A $   !(  	H %
  	D &&  map '  	9 (Z  fd (n   cpu (n   |       I&  T  
}     k&  U} Ts Q0  }     &  U} T~ QR0 }       &  U3T	W'     Q0  }     &  U TR 2~       &  U        #'  U} T~ QR *       P'  U3T	W'     Q  F     u'  U TR        '  T       '  U} Ts Q `     -  '  U} T~ QRX|         (  U3T	W'     Q0R|  8     _  :(  U| T
$ H     u  R(  U  p       (  U3T	W'     QR|       _  (  U| T
$      u  (  U       -  U} T~ Q RX|   "	A $    ?E 0)  G =  map W  H 
   YC n   n     5       )  #map -  ;V  3V  #mp J  gV  _V  9 
n   V  V  #cpu "o  V  V  0n     5  )  UUTTQQ n     <Q   YF    o            *  G .  V  V  H ;
  W  W  #idx Jn   <W  4W  I   gW  aW  ?+  o        
*  O+  W  W  [+  W  W  g+  W  W  q+  W  W  }+    *  ~+  W  W  o       Us QR0  o        o     <Q   ?H :+  ? 8.
  idx Cn   cpu Ln   < Un   sid :+   
  7C   +  G F  H S
  i n   map   "	      /5G n        9       ,  G +  W  W  /2  7n   (X   X  0$       +  UU#@TT )     <Q   /F n        E       ,  G 4  VX  LX  D B   X  X  0     '  ,  UU#@T	T0$0&Q	`n     R0      <Q   kG `n     ^       "-  #fda :  X  X  #fd Cn   X  X  #arg 8   X  X  >map   Y  Y  In       n     <Q   MC n   {-  G 1  fd =n   ptr 8   G    =  4&  pos n    MG n   -  G 3  	1 n   	7 n   	D n   	? .
  !-  	A    "	A     /GE nn   z           2  G n0  -Y  'Y  ? o.
  RY  LY  hC pn   wY  qY  < pn   Y  Y  #fd p(n   Y  Y  lzF r2  H sn   Y  Y  Lid tG  >ret un   1Z  /Z  madd h{     mC  z      
  w/  }C  BZ  >Z  C  ZZ  XZ  C  iZ  gZ   *3  {      {            /  3  Z  ~Z  3  Z  Z  2C  {      {             GC  Z  Z  NC  {             1C     *7C  ,{       ,{            0  HC  Z  Z  TC  Z  Z  `C  Z  Z  ={     *  U TQ   *
3  h{      h{            2  3  Z  Z  !3  [  [  -3  [  [  93  1[  -[  E3  K[  I[  *mC  o{       o{            g0  }C  ^[  Z[  C  x[  t[  C  [  [   2
3  {{      {{     l       c3  [  [  !3  [  [  -3  [  [  93  [  [  E3  \  \  2t3  {{      {{     P       j3  %\  #\  3  4\  2\  3  E\  A\  3  `\  \\  3  y\  w\  3  \  \  3  \  \  *mC  {{      {{            S52  }C  \  \  C  \  \  C  \  \  8C  {{     	 {{            	C  ]  \  C  ]  ]  C  -]  )]    cD  {      
  W	j2  sD  F]  D]  D  W]  U]   2D  {      {     "       XD  g]  e]  D  v]  t]  D  ]  ]      z     _  2  U T$Q 
{     N  |     <Q   &G  
3  ,*    KE cR3  G c.  ? d.
  hC e	n   < en   id e&G   K{G [t3  G [5  i ]n    ?RG N3  G N6  ? O.
  hC P
n   < Pn   id P'G  	bG Rn   sid S:+   MG EG  4  G E2  	/G G.
   .G =x     ]       4  G =/  ]  ]  ? ?.
  ]  ]  x            p4  A A  ]  ]   y            4  A A  ]  ]   y     {  4  Us  -y     <Q   .fF 5px     ]       5  G 5.  ^   ^  ? 7.
  (^  "^  x            /5  A 9  C^  A^   x            Y5  A 9  R^  P^   x       q5  Us  x     <Q   .D -w     ^       >6  G --  e^  _^  ? /.
  ^  ^  w            5  A 1  ^  ^   w            6  A 1  ^  ^   w       06  Us  w     <Q   /C n   w            ?7  G +  ^  ^  ? .
  ^  ^  >err n   _   _  nD (8x     w            6  A    "_   _   x            7  A    1_  /_   .x       7  Us  =x     5  17  U|  gx     <Q   . H pv           8  G 0  F_  >_  ; 3
  r_  l_  K< y
  _  _  ?  v      ^	  8  ?  _  _  ?  r	  {8  ?  _  _  U?  	  ?  `  _  @  O`  7`  @  	  8  @  `  `   "@  	  28  '@  `  `   4@  	  M8  5@  `  `   w     E@  e8  Us  Sw     E@  Us    v        v       v     :  8  UH v     h  v     F  8  U|  uw     <Q   O$D             ;  (G .  a  `  3;  I      I     G       :  ;  <a  :a  ;  Oa  Ia  ;  pa  ha  6;  I            9  ;  a  a   ;    9  ;  a  a   3D  `      `            :  D  a  a  9D  `        :  D  a  a  'D  d         fE  a  a  E  a  a  NE  q            1!E  8E  q      q            ZE  a  a  E  a  a  E  b  b      'E  t        E   b  b    <    :  <  /b  -b   |        3;             ;       K;  ;  >b  <b                     h  ˅       U|   A     Y  c;  U|  I     5  {;  U|  0       ;  UU      <Q   Z$E ;  G ,   $E <  G 4  @pos .
  @n .
  !;  %A    !<  %A    "%A     [H .
  q     D       <  (G '  Ob  Kb  (  B.
  jb  fb  AH .
  b  b  =  <  oA 
  P !<  %A 
   q     <Q   [F   p            =  AG   b  b  3 C  q      q     W       =  *C  b  b  9E  q        :=  E  b  b   3R3  3q      3q     2       !z=  ]3  b  b  i3  b  b   3q     r  UH#@T@  q       =  U
 q     <Q   OgG p     M       ?  (G .  c  c  (? .
  #c  c  pD    >  D  9E  p        5>  E   qD  p            D  8D  p       p            fE  <c  :c  E  Kc  Ic  NE  p            1!E  8E  p      p            ZE  Zc  Xc  E  ic  gc  E  }c  {c       p     <Q   O6E u     z       ?  (G +  c  c  (? .
  c  c  9ME  u      >	  ?  ZE  c  c  fE  c  c  'sE  u       N	  ME  d  d  E  d  d  E  !d  d    Iu     E@  u     <Q   $H E@  G =  "%RO n   "%? .
  @n .
  !"@  %A    !4@  %A    "%A       rH $q           C  (G $?  <d  .d  (? %.
  d  |d  =  @  \tmp U3
  d  d  s       %s        =	  %A  %G oC  s$	  \i t   d  d  is       ts       A  UHT0 |s     z    s     ?       A  AH .
  e  e  s            vA  AA   1e  /e   s     <  A  U| Ts  s     =  U| Ts   
r     \  @r     $  zr     \  r     h  r     F  0r     &  B  UU#  r     h  r     \  r       @s       s     \  t     $  t       %t     :  Dt     \  mt     :  t       t       t     :  t       t     :  u     P  Ju     $  au       ku     :  |u     <Q   &3
   C  ,*    ZD 7C  G ,   t8 ?  mC  6H n   E 8   H H    :D@ 8   C  xy 4
  x ?   y I    :B@ 8   C  xy 6
  x >n   y En    :"G s".
  C  G sI  "%A u	    $*5 :D  r :-D  n :=1    
c  $I4 	'AD  v 	')AD  i 	'0n    
t  :dD 
6n   cD  fda 
6>   :H JR  D  val J0G  ԓ JB1    ?2A D  n 6  h LD  	/G    
  $m> D  M@ 4   $> dD  M@ d7   $? WME    W2  H WK  !.E  @__u Z.E   uZD Z  B__c Z/    $M? KsE  new K4  !I KK   $l8 &E  new &1    '  H (   $~: E  t 5   $= E  p >E  res G8   T  Pn    
E  v+ C   p            F  *C  De  >e  9E  4p        <F  E   3R3  Dp      Dp     ,       !|F  ]3  ee  ae  i3  ~e  |e   Dp     r  F  Us T@ p     <Q   +;   v     j       !G  ;  e  e  &v       /v       8v     h  0ev       G  UU#@ jv     <Q   +3  0y     6       \G  3  e  e  13  fy     <Q   +R3  py     ]       G  ]3  e  e  i3  e  e  y     <Q   +
3  y            HJ  3  f  f  !3  -f  )f  -3  Kf  Gf  93  gf  cf  E3  f  f  mC  y       	  g=H  }C  f  f  C  f  f  C  f  f   *
3  z      z     j       c:J  3  g  g  !3  g  g  -3  #g  g  93  >g  :g  E3  Wg  Ug  2t3  z      z     P       j3  fg  dg  3  ug  sg  3  g  g  3  g  g  3  g  g  3  g  g  3  g  g  *mC  z      z            SI  }C  g  g  C  g  g  C  h  h  8C  z     	 z            	C  @h  >h  C  Qh  Mh  C  lh  hh    cD  +z      	  W	I  sD  h  h  D  h  h   2D  2z      2z     "       XD  h  h  D  h  h  D  h  h     z     <Q   w'%  .
  N  7%  h  h  C%  $i  i  P%  li  Zi  ]%  i  i  i%  j  j  u%  Dj  4j  %  j  j  %  j  j  %  j  j  1%  %  !k  k  %  xk  lk  %  D
  K  %  k  k   %  T
  N  %  k  k  %   l  l  %  jl  Rl  
&  l  l  &  :m  .m  "&  m  rm  "-   ~      {
  iFL  1-  =-  m  m  I-  n  m  V-  (n  n  b-  }n  un  n-  n  n  "~       K  U~T|  z       L  U~T|       f  %L  U| T4Q
  A     f  U| T4Q
   mC  8}       
  =L  }C  n  n  C  n  n  C  o  o  'C  T}      
  	C  1o  -o  C  No  Jo  C    C  }}      
  O$M  D  oo  ko  D  o  o  'D  }}      
  <,D  o  o  6D  o  o    (  }      
  \VM  
)  )  o  o  #)   J*  i      
  r*  p  o  +  ,p  *p  +  >p  :p  !+  -+  \p  Vp  mC  p       &  N  }C  p  p  C  p  p  C  'C        @  	C  p  p  C  p  p  C  q  q           8N  T ʀ     Z  SN  T        kN  T        Z  T   (  Z  N  (  &q  "q   |       N  TX O     <Q   +{-  P            O  -  Dq  <q  -  pq  jq  -  q  q  -  q  q  -  q  q  6-              IO  -  q  q   -  l  dO  -  r  r   FD        |  O  VD  ,r  (r   x                     O  Us       <Q   +"-              P  1-  Sr  Kr  =-  r  wr  I-  r  r  V-  r  r  b-  r  r  n-  s  s  H       kP  U| Ts QRH!0$0&RX r     f  P  Us T4Q
       <Q   +        n       <Q    ,s  (s    Gs  Cs    bs  ^s    zs  vs  6              Q    s  s       .Q    s  s   n     <Q   x/ /  1N   '  Y0 #               u      }      4 	']   ׵  Zint 3d   }  +K  	-C     	p   e  	p   7 	d   [7        3   mE  
C   4 Q   -K  w     / 1 .   1 5   @ d   1 <   O ,   : *9  F  8u64 !   4@  8u32 $  4P  8u16 '   4`  8u8 *   4p  \O	  Q Pd     $6 Q  3  z4 /.   -3 .5   42 .<   5 .9       C      3  <  5d    I  8	     9	   <g  :	   k  ;	    6  <	   (   =	   0  >	   8rh  ?	   @C  B	   H  C	   PY  D	   X1  F  `Y+  H  hn  Jd   p]  Kd     M  w3  N   x  Q5   N  RJ   /F  S    U  U ]   t  _    `    a    b	   6p  c   dd     fd     hw     m   [    ^-  -=+p           C       =t    =           C       7    7  IP    !<  Z; 
-  @ 
-   !`  : 
  = 
   !  ? 
-  &A 
-  z< 
-  ; 
-   !  {A 
-  > 
-  _8 
-  ; 
-   9  "= 
   "
?   "pA   "C    !:  B 	  -   C   % 
   T  
  j 
-    B 
-  G 
-   q< 
-  @7< -  AA -  Bh; -  C@ -  D> -  E8 -  FtB -  G9 -  H6 -  I@ -  J8 -  K= -  LO -  M= -  N; -  O*? -  Q= -  RA -  S_> -  T[B -  U@ -  VK -  W8 -  X9 -  Y< -  ZB -  [4P -  \}K -  ]:L -  ^B -  _R -  `> -  aI -  b3@ -  c; -  d C -  e6C -  f9 -  g8 -  h<  0(B 
  4`  8  @B -  H[: -  P^=   X9 	  \[? -  `
A   h=    lyC    n8   p  t)> "-  x; $-   < %-       $C    95	  "T 
-   "iS -  "M -  "S -  "?P -  "0I -  "L -  : !Q	  K 	-  -   >EK @T
  oL U   hL V    {  S |  U }!  J ~-  RS -   5	  (T    0FU    2JL   4I -  8HP -  @T    H8   L}N -  PN -  XP 
  `%I 
-   %P -  %hN -  %_J -  %qU -   %O -  (%`R -  0%I  -  8    
  ?C    I H  % I   S J   T  K    PQ N?  	dev O-   	ino P-   _/ <   "v  /{/  /A1 // /G/ // //       $C         C         C         C    -    C    7 a   :M (9  J 
   pid   tid   5O -  len -  I -     
9  (    J  ?C    @  maj    min   ino  -  QR !-   @#  DI $
    8 %
   yC &   I '
        C    A  -J  -   :K Ho  J 
   pid   tid   5O -  len -  I -     (? *  @=  +  D  ,
9  H T  /  J 0
   pid 1  tid 1  6 2
   (P 5   J 6
   pid 7  tid 7  J 8-  XQ 9        $C     O  <k  J =
   pid >  dS >  tid ?  K ?  S @-   M C  J D
   id E-  N F-   L K  J L
   N M-   zU 8Y<  J Z
   pid [  tid [  ˿ \-  J ]-  RS ^-   id _-  (N `-  0 RP  c}  J d
   S e-  id f-  S g-   :qK n  J o
   $> p-  len q  NT r   =  s   L{ t
        ?C    .L w7  J x
   % y   =  z   
id {  tag ~
   :R j  J 
   id -  rm 
9   S   J 
   $> 
-  M 
   M 
   H 	v   <N   J 
   7    -    $C    P %  J 
   O   S    EM f  J 
   R -  nr -  ips    J   J 
   N9 :   >T   nr     cpu         $C    S   nr     ON        T 9  nr     ON    R       Q {  l6     R    3    6     A  )M   )P %  ) Q %  )K $9   #N 
  %     {   TL   J  
   P #   ]I 
  ; #    L 7  : 7    / !|  : )  O |  L{   ; (        JC         JC    M (  J 
   % -  	id -  >   T H%  tN &-   L{ '
        C   ? L P*;  J +
   T ,    QU /s  J 0
   T  1  	pad 2   9<  P =
   T  >
   N ?
   9K @    !:  I ;
  -s        C    I $7  J 8
   	pid 9      C
  $    .  $C    7U  Fs  	id G-   	idx H-  	cpu I-  	tid J-   S R  J S
   	nr T-  wD U   .    $C    6Q X  J Y
   % Z  *T [  1	  \   N 0_}  J `
   T  a-  U b-  T c-  	idx d   	tid e  $	cpu f  (*T g  , P xl2  J m
   % n  cN o  	cpu p  	pid q  	tid r  	fmt s  	ip t-   S u-  (	msg v
  0: w  p.@ x  t R  {x  J |
   `R }-  I ~-  =  -   "O   J 
   	pid   	tid    U   J 
   1U 
-   BJ   	pid -   6 
   P ;  J 
   	nr -  wD ';     J  $C    N t  	tag -   	val -   L   J 
   	nr -  P (   J    $C    9  	val -   	ena -  	run -   !
  -  RC    T 0U  J 
   	id -  	cpu   <      AO   J 
   % -  S -   oT 8  J 
   FU -  JL -  HP -  }N -   N -  (?P 
   00I 
   1P 
  2 R Q  J 
   K -  P 
   ZK {  J 
   P 
   N   J 
   _J -  P 
   >kR @  	key    ˿   @      C    >M 7  J !
   L   %D -  %wD (7     F  $C    J 0  S    &I   O   O 
  J   O   M -  uO -   vP -  ( J 0L  S    &I   O   O 
  J   O   M -  uO -   vP -  ( K 0  S    &I   O   O 
  J   O   M -  uO -   vP -  ( !0   v15 (F  v16 (  v17 (L    U HZ  J 
   J -  	cpu   oL 	   R 
Z        j  C    O L  Q    K   Q    Q "  I $  L &  I (  ~I *  	N 8   Q :  $Q <  ( M >  ,gP @  0J B  4rQ D  8bQ F  <Q T  @K V  DQ X  HQ Z  LI \  PL ^  TI `  X{I b  \YN q  `RI s  dK u  hN z  lJ |  pI ~  t,Q   xwL   |I   P   S   @S    R .!  	N    Q   Q     M "  gP $  J &  rQ (  bQ *  Q 8   K :  $Q <  (Q >  ,I @  0L B  4I D  8~I F  <Q T  @K V  DQ X  HQ Z  LI \  PL ^  TI `  X{I b  \YN q  `RI s  dK u  hN z  lJ |  pI ~  t,Q   xwL   |I   P   S   @S    R #  	N    Q   Q    XT "  S $  :R &  P (  gP *  J ,   rQ .  $bQ 0  (Q >  ,K @  0Q B  4R D  8Q F  <O H  @K J  DI L  HL N  LI P  P~I R  TQ `  XK b  \Q d  `R f  dQ h  hO j  lK l  pI n  tL p  xI r  |{I t  YN   RI   K   N   J   I   ,Q   wL   I   P   S   @S    !-#  v15 .+j  v16 /+L  v17 0+.!   XO '$  J (
   J )-  	cpu *  oL +   nO ,   #   `	  HP5&  J Q
  9 R  K S  6 To  4P U!  R V7  O W  N Xk  L Y#  8 Z  ^P [<  HN \  QM ](%  bpf ^   }K _}  > `%j  N9 a"f  M b#  T c'  dU d);  I e%  S fs  BQ g#  N h  P i$}  aux j2  .O k#x  &U l&  < m  P n!  `L o  L p"t  T q
  MO r!U  {T s   _S t$  M u!Q  I v"{  M w#  U x#   dO y&#   @(~&  val     ena    run    id    N      A(&  -5&  )RC &      &  C    FC (&  ~&    &  7&  a4&  3 4&  4 5     2 6&  3&  L5 
'  cpu 
     = '  $'  b/'  /'   4'  : `'  Eg  
     	d   fd 	d   cpu &  B4 &    	@  5O 	@   end  	@  (H !
'  0 "	@  8: #'  @l? $
   HB %   PH &/'  X  B )&(  ? *d     +d    IN1 <   c/7    N(     C    K/ e(  ?    B L2 1d   (    d     B L_@ Ld   (         KE?  (  (      d9 =J    (        d   d   d       M9 d   p     n      1  Nmap ,/'  s  s  en  L1  s  s  pc 1  s  s  seq P  t  
t  idx P  ,t  &t  &JL P  Ht  Dt  &FU P  \t  Xt  cnt @  pt  lt  cyc @  t  t  &I @  t  t  &}N %@  t  t  &N 6@  t  t  '            m*  __u 	m*  t  t  *H                   	*H  t  t  4H  u  u  @H  u  u    	*   	  __c 	   '            +  __u +  !u  u  *H                   *H  .u  ,u  4H  :u  8u  @H  Iu  Gu    (+   -  __c    '            +  __u +  Tu  Ru  *H                   *H  au  _u  4H  mu  ku  @H  |u  zu    +   -  __c    5y  ,  __u ,  u  u  0H  !     y  *H  u  u  4H  u  u  @H  u  u    >,     __c    5  ,  __u ,  u  u  0H  !       *H  u  u  4H  u  u  @H  u  u    ,      __c    5  -  __u -  u  u  0H  !       *H  u  u  4H  v  v  @H  v  v    <-   -  __c    ''            -  __u -   v  v  *H  '     '            *H  -v  +v  4H  :v  8v  @H  Iv  Gv    -   -  __c    '+            F.  __u F.  Tv  Rv  *H  +     +            *H  av  _v  4H  nv  lv  @H  }v  {v    j.   -  __c    5  .  __u 	.  v  v  0H  0       	*H  v  v  4H  v  v  @H  v  v    	.   	  __c 	   '7            \/  __u 	\/  v  v  *H  7     7            	*H  v  v  4H  v  v  @H  v  v    	/   	!  __c 	   50  R0  &%S @  v  v  &T  `  w  w  'љ            $0  __u  R0  w  w  *H  љ     љ             *H  w  w  4H  w  w  @H  w  w    01  ̙     J  1  w  w  2  2     v0       __c     '֙            0  __u 	0  w  w  *H  ֙     ֙            	*H  w  w  4H  w  w  @H  	x  x    	1   	  __c 	   '     3       t1  &DL @  x  x  0|D         D  x  x  D  -x  +x  D  7x  5x    C1       i  
1  1  Ax  ?x  1  Kx  Ix   ޚ     N   &  Q	  OJ 0@  1  Plow 2<   QQ2 2<    OP '@  2  fQ '+<   Plow )<   QQ2 )<    MiJ (5       y      (5  Nmap ;/'  ax  Sx  &yJ (5  x  x  gpE              2  E  +F              F	F  F              F  +H              	*H  4H  @H      C-5  2       
=4  >5  x  x  J5  x  x  V5  x  x  b5  n5  y  x  z5  (y  $y  R5    5  =y  7y  5       k       5  [y  Uy  5  y  {y  5  y  y  5  y  y  S5    3  5  z  z  5  Dz  Bz   G                    &4  G  Nz  Lz  G  G  Xz  Vz  6     "N  Q|   6     2(  T~     C<  ;     %  5  <  bz  `z  0G  ;     ;            Z	AG  lz  jz  MG  ;            RG  xz  tz  ^G  ;            _G  H  ;     ;            ;	*H  z  z  4H  z  z  @H  z  z       i     N   $   M (5  5  
map </'  M 5  
end @  P 5  yJ (5  {M d   #T  
   #U <   len <   cpy <   dst 
   #J <   J <       @  .   D+S Ơ     D       7  (map -/'  z  z  ;pE              6  E  +F              F	F  F              F  +H              	*H  4H  @H      <            
       7  <  z  z  0G  ×      ×            Z	AG  z  z  MG  ×            RG  z  z  ^G  ×            _G  H  ×     ×            ;	*H  z  z  4H  {  	{  @H  {  {            N   T0M d   Е           I;  (map ,/'  5{  #{  ;pE              J8  E  +F              F	F  F              F  +H              	*H  4H  @H      ,I;         	;;  Z;  {  {{  e;  {  {  q;  {  {  };  |  |  ;  s|  e|  ,<         9  <  |  |  0G                   Z	AG  |  |  MG              RG  |  |  ^G              _G  H       
            ;	*H  |  |  4H  }   }  @H  }  }       ,;  c       :  ;  }  }  ;  6}  0}  ;  V}  P}  ;  x}  r}  	<  }  }  <  }  }  !<  }  }  1     N(  /:  U4T	X'     Q	pT&     R} Xs  1     N(  Y:  U5T	T&     Qs  1     N(  }:  U3T	PY'      63     N(  U3T	Y'       S;    &;  ;  }  }  R;    ;  ~  }  EG  n       G  C~  A~  G  N~  L~  6     +N  U	X'     T1Q3    6g     <  U~        N    .M d   ;  
md 5/'  !I @  old @  P 5  T  C   #h4 d   	     3 d   #u2 d       N pd   i<  
buf p*    p3d   5O p>5  
end pJ5  Q ri<  5T s@  T  td   iH ~<  	pT&     #4 d   3 d   #u2 d      
     ~<  C    3n<  U}P d<  
map d+/'  #old g@     T ]'  <  
map ]0/'  pc _1   VK X@  <  
map X,/'   .O S=  
md S</'  
P SD@   j{H K             @  (map K'/'  m~  _~  pE  B      B            M>  E  ~  ~  F  B     B            F	F  ~  ~  F  B            F  H  B     B            	*H  ~  ~  4H  ~  ~  @H  ~  ~      ,D  E     ~  O?  D  ~  ~  ED  E     	~  	D      D  "    D  B  >   E  U  Q  E  h  d  F  E     E            ?  F  y  w  F  E            F  H  E     E            	*H      4H      @H         E  W     W            	E      E      E      E  W            E  E      E      .F  W            3F           ,B         P@  B      EB         5B      nC                   =7@  }C  9  7   E  ̔     ̔            @@  E  C  A  E  O  M  iF  ̔     ̔            <uF  Z  X  F  f  d    1     (  @  UX#H      (         N   DhE FГ     N       B  (map F'/'  s  o  ;E  ܓ     ,       HB  %E  +0E  ܓ     ,       rAE  KE      WE      cE      ;F  ܓ            SA  F  F  ܓ            F  +H  ܓ            	*H  4H  @H     E                    ^	E  E      E      E              E  E  ƀ  Ā  E  Ѐ  ΀  .F              3F  ڀ  ؀            N   U; 5B  
map 5*/'   T@ $d               iC  (map $'/'      (mp $DiC      (fd %d   ,  "  (cpu %&  Y  S  ,nC  ƒ     ^  )4C  }C  s  q   1ؒ     (  [C  U0R1X} Y0      N   '  V&R    C  
map ./'   D8      O       |D  (map (/'    {  F  ?/'      FH '      F: +'      E                   nD  E  Ł  Á  E  ρ  ́  iF                   <uF  ؁  ց  F        ?     N    T @  D  
a '@  
b .P  KU ><     D6 '  D  
r (D   &   6 ~'  E  
i ~)<   
r ~8D  old <   new <   val <    .3 p0E  
r p-D    4 Q'  pE  
r Q(D  old S<   new S<   val S<     ;3 D<   E  
r D<E   &  .*5 :E  
r :-D  
n :=<     4 Ed   PF  
v E5PF  
old E<d   
new EEd   #K2 G	d   75 G	d   : G	d   2F  ; G	UF   2.F  ; G	ZF   2@F  ; G	_F   #; G	dF       z  k  [  K  .I4 'F  
v ')PF  
i '0d     3 d   F  
v /F  2F  __u 	F   G	) 	k   H__c 	      .dM D0G  Eg  DH1  
P E@  2G  __u GG   GG) G-  H__c G     ,J 3@  G  Eg  3F1  2mG  ;O ;	-  #__u ;	mG    G;	) ;	-  H__c ;	    W2    G  {5    F5 &  6     WT  md   G  / m  u/ m<  B .= H  
p >H  
res G   T  Pd    H  k.2 MH  
p CMH  
res L   T  Ud    &  <nC  @     ?       H  }C           N   <B               I  B      ,B  D      s  5I  B  .  &  nC  ]     ]            =I  }C  P  N   E                   @I  E  Z  X  E  f  d  iF                   <uF  q  o  F  }  {    1M     (  I  Us  r     (  l     UU  ʓ     N   <<        9       J  <      0G                    Z	J  AG      MG              RG      ^G              _G  H                   ;	*H      4H  ؂  ւ  @H          9     N   <<  @            N  <      m<  a            K  <      <  e     e     
       i<  '  %  =  1  /  F  h      h            UF  ;  9  F  E  C  F  h            G  G  h     h            GG  O  M  G  \  Z  H  k  i       pE  o     o            lL  E  v  t  F  o     	o            F	F      F  o            F  H  o     o            	*H      4H      @H          ,<          dN  <      <                   l*M  <  ʃ  ȃ  <  ԃ  ҃  <                   a	<  ރ  ܃  0G                   Z	AG      MG              RG      ^G              _G  H                   ;	*H      4H  	    @H            n     =  UU  ĕ     N   o/ / X2 2 X3 2  z   R.  0 x                	  mE  :     int }          }    ׵  F  / 	         
        :   :    E?       F         ptr   5  -  E        f     t      8         =       t  T  .   Z  P          f  U1TU      t   / /     [/  0     p             }  mE  A     int   /     }    ׵    F  ? (   8 	5    A 
5   wD 5   : 5   bC 5    .<    (       A            8      5    	&C P     5       q  
xy &q              c  UU            	U       B         
xy %q      n 	5             =         UU#(T0 B         d< q  p              r- "H   ؄  ҄  U ,H       A 95       8 		5        xy 
q  E  C           U}  #(         6 9     {5    6 H   6 5    / / 6 6      H1  0                φ      }      ׵  int }  	e  _   	  _     	  t   	mE  C   	  f     / F     N1 <      	     U *     X   r      f       
U :U    8  X   r      f       
U 1U    _  X   r      f    GG      X   r          
VH  GG      X   r          
D 8      X   r       R  %  X   	3 z     X          U @                 fd @X   ^  X  buf @$   {  w  n @0                C          Ѕ  ʅ                3  /    M  E        u  o  0         U~ T} Q|  =         r        U )   0            E  fd )X       buf )r       n )*     ݆  U )3       U +	   $      7   ret .   L  F    }     }            .)    d  b  $  n  l  0  x  v  <           8  U~ T| Qs R}           ӝ        U $                 fd $X       buf $r       n $)                &      ܇            
    2  ,    H  D    _  W          y  I  Ҝ     Ҝ              Z      f      r             U~ T} Q|            "        !ion 
     U 
  fd &X   buf 0r   n <   V r   U 	   "#ret       $U 4U    I  6H 4X   E 4r   H 5   U 5#f    %8      6H X   E r   H H    &/ /  a   3  3y          ,	      ψ  k  }  mE  E     4int     }    ׵  +K  -E   q E   ^ a   ]v a   Kx E   Y a   }g E     2   e  2   j 2   5k 2   _ 2   Z !2   
#  *      *#    F  
*  =  h n        s    #  ~  E    T 	N  zt 	    w 	$   Z 	,   g 	-   Y 	/   rZ 	0    s 	2	L   $mt 	4   (RY 	9   0Y 	=   8v 	?   @J^ 	JG  Hz 	KG  XZ 	LG  hq 	YN  x   ^  E    
  ^  - 
(t  6. }      E     7-    .. a    - a   8.    J.       3q  <  5L    I  8	    9	  <g  :	  k  ;	   6  <	  (   =	  0  >	  8rh  ?	  @C  B	  H  C	  PY  D	  X1  F  `Y+  H  hn  JL   p8  KL     M  w3  N   x  QZ   N  Rh   /F  S    U  U ]   t  _    `    a    b	   6p  c   dL     fL     hv     mn   [    9-  -$+p  
  
  #    E     
}  $t  
  $  
  
  	  9h  
q    +P    j (2  =w =    =  rh =  z 	=  W 
=    +j   mh =  	     lm =  	     A7      E    l WL     =     
  iV f      9   9    n jiV       9   9    ` hev       9    T i L   $  B  )   
~  $   L   I  =  =   l e 9   m    =  9    ] 9       =  9   9         =   i     =  E    5  9     =   2 1L       L   =   :> 
  L    ba EL   0  c  L   B   ;  C      $    Y  =    .L   z  =  =  L    w L               q  ,cmd =      ut L        q  }arg =  B 
  }       )  J    5  1    G  E         T2Q	Y'     RU  	2       c  U}      C   =    E     W L   P            \	   \	  b  X  v \	      a	  T       )	  p	      |	    Ӊ  	  +  '       j       j  U@  	       G	  U} T|       0  U|   
=  w \	  	   3\	   ut L    v \	   %!p `              qa =  @  :  q   P-tmp   Z  V    ٤       
    k  i    w  u          ٤     ٤            E
                     UPT2Q	\&       .  6      6            A            !  D       U	W&        <    @  "  "  !  =  Ƥ            E+  "  "        0  Uv   	       _  U	7"'           >  	         UPTv  	         UP 	     0    Uv  	     Y    U	7"'     Q1      0  I     C   &f -  out ^  rm .=  /buf 	-    #  >  0E    >ih w  \  env y   %b_ lУ     #         rh l%=  Ċ    '     Y  TUQ1  dm Y=  0            $  yZ Y,=    ݊  q [=  $    	K         Us         Us Ths   \g M              g  rm M=  X  N  ?buf O  `@    -tmp T                  +       T                     U`T2Q	 U&     R	l:'     YU  ,       U	W&                           QL     ̋  ʋ   (     C       C   g 9=    buf 90  sz 9<9   rm 9L=  /cwd ?=    Pg '=    buf '&  sz '29   pwd )   Gw *~   X *~   y "L     rm ")=   %,p `     +         =w  =  ڋ  ԋ   7=      rh =    
  z )=  .  *  '     Y  U	U&     TTQ1  &x A  out A#^  add A4=  tmp C   Adie              O  ,err /=  D  @  bh 
  ~	       :  T~B\  	T&             U  &Hm 
   
'=  err 
;=  bh 
H  msg    
  #    0E    } L     ; c  u/ B   T  mL     / m  u/ m<B   sw ]L   5  __s ]  __n ]9   u/ ]B  0 ]   ev o  ]  E o  R  o9    e 9     {5   F5 B  __n 9    x     {5   F5 B   )O       ~         h  \  V  t  u  o  #  wC\  
T&                                  (  Ό  Ȍ       L  UwT
 Q2R
 XUYT         !                ݞ       T2Q	&'     R	T&     Xw       C   )                       V  H  D  (    #  _g       =  O        v  э      Q  E  E  =               R  ?9          ʎ      )  #  #  ]#  ^5       	            +P  D  E  ?  P  c  a         U_T
   ]                   3  l  t  n  x                 I  U_T~ Q
   	(         U	U&      	D     .    U~ T_ 	¡         U_T] ҡ       U~ T^         ]  Gm                      h  H    ŏ  Ï    ҏ  Џ       [  U ]"
/T]R
]  	a         U_ 	o         U] 	4       $  U	Y'      ]       U	U&     T<Q]   1       x    ߏ  ݏ                Π        E    	                0  U]                &  $    0  .    :  8            Ei    D  B    N  L         Us T2Q   .  9      9            A  a  _    k  i  !  G       U	W&                     x  v        1                       Ɛ              E    ِ  א        (       Us T2Q R]l:'     ]0.( X	@'       ']     0  U]   9     C   )>        Y       C  O      >  6        w(  !O  (J     $   (     C  ,        F/ / 2vv lv G/ 2>n 4n   !   7  :y                 q  	mE  	:     	- 
(M   ;. V   f   f   :     <-     ..     -    8.    J.     }  =         ׵  >int }  	+K  -:   	q :   	^    	]v    	Kx :   	) :   	Y    	}g :   	     	e     	j    	k    	_    	Z !     {    *    3A  <  5    I  8	{    9	{  <g  :	{  k  ;	{   6  <	{  (   =	{  0  >	{  8rh  ?	{  @C  B	{  H  C	{  PY  D	{  X1  FZ  `Y+  H_  hn  J   p?  K     Md  w3  N3  x  Q   N  R   /F  Sd    Ut  U ]?  t  _~    `    a_    b	   6p  c   d     f     h     m   	[    @-  -+p  U      t  :     M  t  y      _      :        		  9A   A    +s    +P      h     K   s o   F  A1     B   2  2  2   <  2  C̂            *          T P  zt     w $  Z ,'  g -  Y /   rZ 0    s 2	   $mt 4   (RY 93  0Y =W  8v ?c  @J^ J  Hz K  XZ L  hq YP  x o  `  :    {  `  DC(   +    " ?  !    }%     -! !
       :    EDIR   % Q} 	  ,len 
.    L{        F:     E  t4 		.    ,cnt 
	.    E   J     h   k        $} }        e      @ *        :    | 4           1| K     2  2  :    $T i                    0      :    ba E   Q  e        چ    g  g     $w      g   j  5  .        "* g       Z- {          $  {       -4 
     .   .      Gih {   {  -     H  aN                i       -  z      2 1             I> 
      /7         :    A7      :    J %        m       J	  .c $J	      .s 3  4  .  /i '   X  P       N  Us     K              %v      w  %P~ 8J	  ϑ  Ñ  %{ J	      /i    `  R  0        Lس              0rh 	{  ޒ  Ғ  1X         J
  g             U2T	U&     Q} R   X                   
  g  )  '         U2T	W&       J  $      $     /         W  C  ?  a  i  ]  2  @     @                  M     O  U-     S     S            `        `     O  U:    j     j                ȓ  Ɠ  w     O  U:  ݳ     
           U}  $         U  j     g     U| Ts       i  U  X  J     J            o  g  ؓ  ֓  `       U2T	Y'     Q}   X  `     `              g      s       U2T	С'       J  ~      ~     %       @  W      a  !    2                     N  L       O  U-                          _  ]       O  U:  1         !    o  m  &ճ     O  U:  {         U}       g  Uv Ts   '>~                $    }  P~ J	      { J	      b       rh {  B  :   t  .   	{  m  e  rm {      Ѕ {  ޕ  Е           Us       N    Us Tv           U| Ts Q}         &  Us T: Ա     N  D  Us Tv         h  U| Ts Q}       i    U          Q8R          U|  E         Us  e         U| Q}  r         U T:        U| T Q}   '       M  U	7"'      /     
  I       ~  U~ Tv Q}  i         Q8R q         U~       i    Uv  &1       UQTT  3{              } 3J	      rm   8  .     r  h  4    dir g      de   Ж  ʖ  5buf {  ~   /  tmp {      /  B     B     "         >      J  2  0  d     0  U~T2Q	wU&     R	l:'     Xs   ȭ       U	W&          j  ~    J  H  >           O  Y  W  6[  ~       T}                j  h    {  w           Uv         Us Tv   n            =         {              ŗ  ×  /  ֬        E  >  ֗  җ  J      ۬     0  U~T2Q	\&     R l:'      0.( Xs        i  U     -     -            )              &  *  (  2  9  7   (       A  Us  V       U~T~ $ &s "           Us  ;         Uv       l    U|  ^     l    U|  o     Q    U|  y     i  ͭ         !    >    &  
ext <  len 	.   4\ 	.    !݃    g  L{ &  st    3~            X  } 7J	  O  G   A   y  u  s            ʘ  Ę  4        5win =  o        i    7  1  j 	   e  ]   f    n        T         MX  !       g      G       U2T	Z&        X       @    e  ͙  ř  p                         v  !      &     k  T0Q:    <     <            y^  !       K     k  T0Q:         }  U	EU&      7         U	KU&             U1T
TQ  X       V    g  /  -         U2T	A&         U     U            J    G  E  i     O  U:           " q{  
ws q1{  s s{   =  7} I  } I$J	   I;J	  ci K	.   cj K.   ei K.   cmp L   N   	P(          :    *  7= 1#  } 1J	  i 3   j 3    OZ~ *                 #a_ *!2  Y  U  #b_ *12  t  p  a ,J      b -J      Pק     N   ' Э     _         } &J	  ՚  Ϛ  i !            i       i   'M}              J  } #J	      L{ 5  C  ?  #len B.   a  Y  ent J        P     P     "                 כ  ՛        r        U|THQ}            5                #           ޫ       U	SU&       E       Us   "~ n  
c #  
num 3    "x A  
out A#`  
add A4  tmp C{   !| 1     
ptr 1$   T  10.   ret 3    Qdie p            V  #err /  ;  7  Rbh 
  ~       A  T~Sc  	T&             U  "Hm 
   
'  
err 
;  bh 
H  msg    f       T:    !B *    
str **   *;    2      {5    F5 7  6 .    U     /  V6    }    X  ; e  u/    T  t   u  u/ t    T  m     / m  u/ m<   sw ]     
__s ]  
__n ].   u/ ]  0 ]   W| R     
__c R    8V       ~       D  o  [  U  {  }  w  6  wXc  
T&                              ֜  М        &        UwT
 Q2R
 XUYT  u  &       6          /  -  M     z  T2Q	&'     R	T&     Xw  n         8  0               O  E      9    1(            ڝ       N    T Ю     i    U  &6        T0   Y  A         	    V  H          9  W  I(  (          ,            ֟  П  ί     N     Uv `     i     Uv  	     -  U	U&     T	}U&     QmR	P(        Z.exe [/ / )>n 4n )vv lv )6 6     =  y     0             x      }      ׵   int }  +K  -G     c   e  c   7 \   j c    c   !                        1c   ";	  Г @         G    v F        2  2  7 a   F     d  G      3  <  5\    I  8	     9	   <g  :	   k  ;	    6  <	   (   =	   0  >	   8rh  ?	   @C  B	   H  C	   PY  D	   X1  F,  `Y+  H1  hn  J\   p
  K\     M6  w3  Nv   x  Q9   N  RN   /F  S6    UF  U ]   t  _P    `Z    a1    b	   6p  c_   d\     f\     hj     mT   [  d  #-  -+p  '  d     F  G       t  K    U  1    s  	d  P  	d    $  \    %       ̂ 
   
9     
9   * 
9    
 9    3 @      pid A  in '\   out (\   err )\   dir *2  env +   h ,\   (
( -@   `
 .@   a
V /@   b
w 0@   c
t 1@   d
 2@   e 3	  0 5  8 2  7  &\               j (A  =w 2    2  rh 2  z 	2  W 
2    j    \   	L     S \   	H     9 2  	@     2    G    z 3  	x      4  	      '} } c     <    \     .\     2  2  \     f\   5  \   :  :  :  D     5     ?  b c   _  c     c   u  c     {\     \     \     \     :\         	\     d    \        ( 	     X= f\     \    Ț +\   )  \   \     8\   ?      \   Z  2  2    \   v  2  \    @ *\     \   G   ) Ɗ )\     \          2   *Q x\        L       Z  s z       +                   ~
>  ,             T0Q:  Ը       U	KU&       -V s\                G           
  @ I2  *    sz J  P	ɶ                U1      v    U1T
TQP      ?  !	  Us T	U&      a     )  @	  U	              W	  U1      v  {	  U1T
TQP ٷ       	  U	U&           Z  	  U	U&     T1         	  T1 *       	  U2 	9       E       
  U	       Q       7
  U	0      q     Z  [
  U	U&     T1        r
  T2 	     z    @      T       [  ./ @'\   l  d  /[  $       B-  	6       	E       O       
  U1 Y         U2 e       U	        l       E  Us  t     u  UU  0 6Ȕ !              in '	  }q (	  ~1    __i *@       e *5       2ǵ              __i +@   3e +5   	  __d ,c      __d -c           H  U1T}Q0R~X0        y  U	U&     T	U&     Q0 	     z   ̘               @ 2  U ̍               W 2  U 4  \     56 2   6[  0     J       z  	G       	V       `       G  U1 j       ^  U2 z       U	        7/ /  K   A  Ty           -        ~  }  mE  E     Uint !L       }    ׵   	)L   !{   +K  	-E     	2   e  	2   V"      "     !   -K  
    P2     F  Wu64 !      "   !   - (  X. #  '3  3  )E     Y-  h  *.. f    *- f   *8.    *J.     +  3  <  5L    I  8	     9	   <g  :	   k  ;	    6  <	   (   =	   0  >	   8rh  ?	   @C  B	   H  C	   PY  D	   X1  F0  `Y+  H5  hn  JL   pZ  KL     M:  w3  N   x  Q_   N  Rm   /F  S:    UJ  U ]   t  _T    `^    a5    b	   6p  cc   dL     fL     h     mh   [  h  [-  -4+p  +  h  '   J  )E     #  4t  O  4  Y  5  '   x  )E    	  9    "  5s    5P    \1     BL            "  ]6 f   	@  	  	 	 	[ 	ϣ 	K 	, 	 	 	 		7 
	 	 	 	λ  6 f   m  	( 	 	i 	v 	i  6 f   &  	f 	- 	 	 	d 	٤  	 @	 CU  C   Ư 4  BL          L      + `a  % b    cL    d   ˿ e   J f    g    8 h   (=  jL   0[ k  8ߥ l   @7set m  HP n   PE o  X !       ^L     _ 	L  	 	~ 	  +` 0B   G   7out G  ut L    L   7opt        =  L   ( !     +j (  =w         rh    z 	   W 
     5j L  `'    	P      HL       L           "  3  ba EL       L      # hL   -  L      | 4L   I  L       #Z-    e     L    #             a	 Q       D4      9   9      #/7         E    # gL     L      b 8 w          L    81 1 E   =      L    8} } 2   `      L    2 1L       L         L           E    #5  9          L            $           c> 
  L    D  	      E+ 0            
  
 (
  ɠ  à  
 2L       
    +    
8    h  \  
K 	      opt 
  á     
  4          ӡ  ˡ        (  +  !         	  T|         T|      EЪ             
  
 %
  X  R  
 /L   }  q  
 E       
۪ L       opt 
  *  (   
            :  2    a  W  (             
  T|         T|     
  6   
   &L    <    ,޵ L   `     .         dopt 1  U-arg        
 L   ӣ  ϣ  9ǻ        L   , L   @             
W -      
   8  ,  
    n  f  
       Fopt ;  q        u  ;      ;           `  T2Q	ZV&       ;             ;  ͤ  ˤ  ;  ؤ  ֤       `  T2Q	gV&       ;             ;      ;      	     `  T2Q	&'       o<  7      7              <  	    <      ?       w  U|  P       U} T| Qs   o<  X        +  <      <  0  .  v         U	W&     T| Q!s 4s #,(         U|   o<  z       z              <  <  8  <  V  L           U|        T|           U:      e    Uv T0      e    Uv T0      e  UvT0  	  G P              
W 1      
       -fmt /       Hap 
x  ~tmp        5;            G;  ȥ  ƥ  T;  ݥ  ٥  a;             U	P     T2QQR~                      z                                 _D  Us T| Q0R0           Uv  %         U 3     J:  U	W&       G8       "         
W -  (  $  
   >  :    &            T  P    j  f    ~  |    ~  |    8     _D  UUTTQ0R0  B       U   qL     W q<   r!   r+L   ctx s$  d u
     x R  0  opt R2  ctx RU0  i TL   :arg W     B   '
     ';   )L   ( )L   B )!L   len )0L   o *  p *"  opt +
  d +
  "B +(
  Fout N e[ L                e  -va $      -vb 4  Ӧ  Ŧ  a       b    O  A  sa L       sb #L       ret @L   ۧ  ѧ      9L L     	  I  __c L     ;  .        (;  '  #           "  +  9L (L   ;  3  I  __c (L     ;  E      A  ((;  _  W  \         fX  la      ~  lb         J         ;    4   >L   pos 	9   pad L    ,е L   @            _  
ut L       
 *G      
ֵ E  ¨    
W   ڨ  Ԩ  
=  (L       $Q     _  UUTTQQR0XRYX  ,[ xL   0           @(  
ut x"L   (    
 x5G      
ֵ xP       
 y    ]  
W y1G      
=  yAL   E  7  ctx {      S  \  Hbuf 	   ~^    tmp        o;        n    ~;  
    ;             U| T2Q	W&     R	l:'            J:  U	W&       y  }  i L   2  ,  :  0          %:  K  I  1:  U  S  =:  e  c  o;  U         E  ~;  o  m  ;  y  w  \       U| T2Q	\&     Rs l:'     s 0.(   q       Us    :          %:      1:      =:      o;           Eg  ~;      ;             U| T2Q	\&     Rs l:'     s 0.( X	 &              Us    K:             @       %:  к  κ  1:  ں  غ  =:      o;  0         EF  ~;      ;      7       U| T2Q	\&     R} l:'     } 0.( X	Ό&       D       U}    L`     ,         i L        ;  l        ;  G  E       -  U2T	\&          C  tmp    Z  X  Ko;                    ~;  l  j  ;    }         T2Q	W&        L     (         tmp        o;                      ~;      ;             U	P     T2Q	X&     Rs l:'     s 0.(          Us   (  z          (  Ļ    (  ݻ  ٻ  (      )      <  z          <      <  !    <  ,  *   q     J:  U	Z'       ](          
&  m(  x  6  y(  Ľ    (  I  1  (  ܾ    (  @  $  (      .(       /(  <)  @  p  )  )      /)       *  U~Q1  8)  >      U  Qf!  H)  *    R)      ^)    u  k)      w)      )      )      )    }  .)  c     .)  1     /)  g)       )  x  T  )  5    9             -       }
  9      9      9               U|         U~T| Q}   o<  :      :            7  <      <      G         U~ W       U| T~  o<  C      C            x  <      <       9  k           9  -  +  9  ;  7  9  P  L  x         U~        U~T~Q~  o<  x      x     '       x  <  c  a  <  v  t         T  U~        U	W&     T~  9             9      9      9             U~T| Q}   o<  S      S            	U   <      <      ]       6   U~ o       U~T~  p          U| T~Q	~~      I  T	V&     Q0  ;  (        "!  ;      ;      X     `  T2Q	['     R~Xl:'     W&     ~0)(   M     I  B!  U~T=      *  C       U~  )  1        &"  )      *)      o<  M      M            !  <  *  (  <  6  4   o<                    6"  <  I  G  <  S  Q         T| Q~   ;             "       "  ;  a  ]  ;  s  q       `  T2Q	Z'     R~  6       "  U~        U  <)  #  +#  )  )      /)  y     *  U~Q1    }      }     ]       L#                                 _D  T}Q0R  h(       +       #  M(  ~,       U0T}Q~R1               ;       =$                               	      	     `       J$                             d     _D  U}T}Q1R               ]       )R%    >  <    J  H    V  T    a  _         _D  U}T}Q0R~         y%  U~T	W&      6       %  U~T	W&             %  U}T}Q~R0 0       %  U0T}R0        &  U}T}Q~ >       <&  T	W&      k       c&  U~T	_&             &  U}T}Q~R1        &  U~ ;       U}T}R1  @(        8  	Q'  P(  m  k   =        C  s=  ~  x  =      (=       @K  U}  $ &3$v "T|    S<                    '  b<             U:  ;          '  ;      +     -  U2T	W&       :       '  U        (  U}T}        2(  U      IK   f qL   ](  ctx q6    L   (  ctx 7  ֵ   W    L    L   arg    % ]%h; e:opt i     ;G )  ctx 9  ut 	L    G  =  &L    ; 8)  arg %   ֵ ?    kL   )  p k3  arg kB   ֵ l0  Ѥ n    o  Π o.    pL   K pL   % u% % : w   =  xL      YL   *  p Y4  ֵ YL  % [ iǿ EL   @           9  =p E.  V    =opt F    b  j=  F&L       Ns H   ~>arg H     b  O IS   	    >err JL         -  Nmsg U	9  ~<          Y6+  -<    
  9<  !    E<  -  +       RK  U~TQ2RX	Z'       9          _,  9  D  >  9  ^  Z  :  u  q  9          ,  9  :      9      ;             "       ;  ;           `  T2Q	sV&        ;  )      #  Y,  ;      ;      ?     `  T2Q	V&       ;                    ;  ;           `  T2Q	V&        &<  {      .  \-<      9<      E<  	         RK  U~TQ2RX	!W&          !1  P1 9  ~O!   *    <  '         	-  -<    }  9<      E<      3     RK  U~TQ2R  .9          
.  ?9      I9      U9      a9      m9   z9  P        \/  9      9  9  3  9  [  U  ;  a        +.  ;  u  q  ;           `  T2Q	bW&     X~  ;  	        -/  ;      ;      -     `  T2Q	~W&     X~  &;          );      ;           `  T2Q	IW&     X~   9  ~        0  9      9  )  #  :  K  E  9           20  9  :  c  a  9  m  k  ;             (       ;  ;  y  w       `  T2Q	sV&     X~   ;        (  0  ;      ;           `  T2Q	V&     X~  ;                    ;  ;           `  T2Q	V&        &<  A       3  <      <      <          >1  >val         9        >  oU2  9  '  !  9  D  @  :  i  e  (;                    1  ;  z  x  ;           `  T2Q	V&     X	V&       ;  H      H     (       ;      ;      b     `  T2Q	V&     X	V&        9        N  M
2  9      9      :      &;        ^  ;      ;        .9  G      i  D3  ?9      I9      U9  7  1  a9  S  M  m9  z  x       I  T	8W&     Qs   .9        ~  H3  ?9      I9      U9      a9      m9       .9  Z        3  ?9      I9  -  '  U9  I  C  a9  e  _  m9       .9          X4  ?9      I9      U9      a9      m9       .9          (4  ?9  #    I9  ?  9  U9  [  U  a9  w  q  m9       .9  A        85  ?9      I9      U9      a9       m9  '  %   9        9  Q
6  9  ?  /  9      :      (;             *       5  ;      ;           `  T2Q	V&     X	W&       (9  M      M     "       k6  9  :      9  !    ;  M      M     "       ;  4  2  ;  ?  =  j     `  T2Q	sV&     X	W&        &;  o      N  ;  T  P  ;  f  d       `  T2Q	V&     X	W&        .9        Y  
N7  ?9    w  I9      U9      a9      m9  +  %       I  U~T	8W&     Qs   (9             -       O
7  9  G  A  9  b  `  :  w  s  &;          ;      ;           `  T2Q	V&     X	W&        Q     8  UTQ0 2       08  T~Q: ^     I  U8  T	W&     Qs       =  s8  T~Q:      =  8  T~Q: A       8  T~Q: Qm     8  UTT0      IK       J:  8  U	`Z'           I  UTT	8Z'     Qs   '   .9  )E    0% 0L   z9  p 0,  opt 0D  =  1
L   arg 1G  1res 3    ?[ &9  opt &-  1 &>   =  &JL    0     9  str  ,     =   1len "	9    0î L   :  opt *  1 ;   =  GL    ?x AJ:  out A#  add A4   1tmp C    kdie             :  =err /       Pbh 
x  ~     C  :  T~l:  	T&             U  ?Hm 
;   
'   err 
;   bh 
H  1msg ;   '   ;  mE    R L   5;  __c L    n| L   o;  ;   u/   0    } L   ;  ;   u/    T  tL   ;  u/ t    T  mL   ;  / m  u/ m<   sw ]L   <  __s ]   __n ]9   u/ ]  0 ]   tw AL   S<  __s A   __n A9   u/ A   R| RL   o<  __c RL    0B *  <  str **    *;    6- l   <  {5 l   F5 l  6 l9    6 9   =  {5 9   6 9L   6 99    C "   5=  {5 "   F5 "  6 "9    2    i=  {5    F5   6 9    2e        A      C  p      }  !        e  P       c  B  }  [  U  p    w              ;  P        K>  ;  3  1  ;  >  <  n     `  T2Q	&       ;                    
>  ;  Q  O  ;  [  Y       `  T2Q	&       ;          
?  ;  n  l  ;  y  w  ɺ     `  T2Q	U&       @;              (?  ;  ;   ;  U        s?  ;      A;  
#V&     &     `  T2  ;  B      B     "       ?  ;      ;      d     `  T2Q	(V&     X	l:'       ;  n        H@  ;      ;      $     `  T2Q	/V&     RJX	l:'       ;                    
@  ;      ;           `  T2Q	U&       @;  J            @  ;  ;   ;  %        A  ;      ;      _     `  T2  ;          
mA  ;      ;           `  T2Q	:'       ;  м      м            A  ;  -  +  ;  8  6   ;                    A  ;  K  I  ;  V  T   @;              B  ;  ;   ;                    WB  ;  i  g  ;  t  r   ;  =      =            B  ;      ;       λ       U:  ;          C  ;      ;      $!     `  T2Q	y'              U:  2:  p     ~       _D  :      :      M:  wA:  
T&     ;          C  ;      ;  ,  *  <  =  7  <  \  V       K  UwT
 Q2R
 XUYT  ;          QD  ;  y  u  ;      ͽ     `  T2Q	&'     R	T&     Xw       IK   2       :      I                4  0    I  E    h  Z  ;  ھ      ھ            }E  ;      ;           `  T2Q	MV&       ;           qE  ;      ;           `  T2Q	ZV&       ;  ;       	  E  ;      ;      N     `  T2Q	gV&       ;           F  ;      ;           `  T2Q	&'       <5  )  VH  E  R      ^  Q  A  j      v              Q  E                    .       5=  >       9  ;}G  D=  U  O  P=      \=      `     K  U}  $ &35$~ "TQ }  $ &35$RI}  $ &35$#}  $ &35$#*( }  $ &35$  5=  w      N  @G  D=      P=      \=              G  Uv T 
       H  Q`R	              )H  Q`R	              U~ T0Q`R	          *       ^   H                    o!  n  "  )  #         H  T       e  H  T  n       T   ľ                     $I  U:        ;I  U: J            e  fI  U~ Ts       e  I  U~Ts  #     e  U~T  29       ^       @K  9  M  ?  9      :      9  (      ~  J  9  :  '  #  9  ?  9  ;  (      (            ;  Z  X  A;  
sV&     $>     `  T2Q	sV&     XT   (;                    J  ;  e  c  ;  o  m  $     `  T2Q	V&     XT  ;                    ;  ;      $#     `  T2Q	V&        3C 9 p/ / 3Х ƥ Sis not available Sis being ignored 3vv lv 3>n 4n     H  5y %          	              9   }      ׵  6int }  +K  -L     h   e  h   7 a   a      L    7   "           mE  L   87    F         L    (E   /`  q3  =5  4  5  g3  4   B2  @X1  4 3 2 3  @      e  "e  9t  - 	(  :.       L     ;- 
   .. E    - E   8.    J.     	  	gz  )  3  <  5a    I  8	     9	   <g  :	   k  ;	    6  <	   (   =	   0  >	   8rh  ?	   @C  B	   H  C	   PY  D	   X1  F  `Y+  H  hn  Ja   p  Ka     M  w3  N{   x  Q9   N  RS   /F  S    U  U ]   t  _    `    a    b	   6p  c   da     fa     ho     m    [    <-  -#+p           L       #t    #        "  =P    (E   4  o '  ' ' ' ' ' ' )3 @      pid    in 'a   out (a   err )a   dir *e  env +   h ,a   (( -E   ` .E   aV /E   bw 0E   ct 1E   d 2E   e 3	u  0 54  8 e  j  >a   /  /   4      j   Y     Y  a    a   V j           a       dV            a       `         a      *3 O#  `  ;  a          a     e  e  L    ?      7  o  o   2 1a   X    a   e       a   x  e  a     y a     e  a    + '+ %l Wa     e        W a        @> 
  a     2a     e    (a         Z-    7  e  a    ! !   W  a          *R  %Y   a   z  e   Ț +a     a   a    AO 
    a        X= fa     a     a     Y   $K $a   P     {         B $$      %opt $.a       Ccmd &4  ,  o        '        	      	       DY  o        h  =  9  t  Q  O    \  Z          	    U         EC  	  cmd =/  -   opt a    $ a         !       	  %cmd '/  r  f  FcN a       -       	  Us  GA     	  UU  $ a                  %cmd */      ,  A        	  ,             8      D  C  =  HP    Q  ~]  b  ^  i  z  t  Iu  k     4       
  v  ~  z         
              	     7  T2Q	jX&       	z     7  T~Q  Y     9  
  Tv Q0 d     W            J a                 .cmd 5/          }O   }        Ks     h         /p 	                Uv          0  5      |  '  ?      K  #  !  	=       U}T2QIR	SX&         X      X            	    :  4    X  V    e  c    o  m  	j       U}T
 Qv   L         U}T	ls&               Uv               L         L    L* a     cmd 0/  
 :     o a   0 a   cN a    	   0% 	           L    M a   @             .cmd )/    z    !a         !a         !a        "   ~s "   ~M "   ~% #  ~NP  q  /err a                                
                                                  	                                     I    $  "  )       2             W  <       F                            l    1  /                                %       V    >  <    K  G           /  R    \  Z    o  m  	3     X  U	IX&     T2  >     z  o  Uv T0 	E       Uv     Q      Q     (       `J    z  x          Q      :                	d     X  U	IX&     T2  r     z  5  Uv T2 	y       Uv                3       g                      E                	     X  U	IX&     T2       z    Uv T1 	       Uv           [  cR                               f  Y                               q  :      
  x                                   J#                                           Fp    &  $                          U0             z    T1        .     c  U       {         Uv T=          Uv         !  U~ 2       :  U~ Z       S  U~                           z    T0             z    T1 O       Us                         U 9       Y       o     z  1  U2T1      z  H  T2      z  _  T0                           W       7    T~Q 	       U	+X&       &l   to $a   1fd a    &8   fd #Y   Pdie .  err /e  bh 
   &Hm 
j  
 
'e  err 
;e  
bh 
Hj  1msg o          QL    R 1     __s 1   __n 1Da   -/ 2  S 7
    !T  ma     
/ m  
u/ m<o   !sw ]a   0  __s ]   __n ]   
u/ ]o  
0 ]j   !~ a   Y  __s    
u/ o   !6 9     
{5 9   
6 9a   
6 9    TVB +  a     
 +e  
S +a    2.                 Q  7  1  ]  w'E  
+X&     '9  
T&       2      !      Q  K    i  g    t  r  #      	:       UwT
 Q2R
 X	+X&     YU    :      (                	a     7  T2Q	&'     R	T&     Xw          2                      !  ~'  
+X&     +         U~39  	T&     3E  	+X&      	5       U  U/ / 4x n 4vv lv  Z
   QM  y          0               }      ׵   int }  +K  -G     c   e  c   !        "   y H      #   \    mE  G     F        G    - (   $.       G     %-  F  .. @    - @   8.    J.     	  g      R    	3  <  	5\    I  	8	     	9	   <g  	:	   k  	;	    6  	<	   (   	=	   0  	>	   8rh  	?	   @C  	B	   H  	C	   PY  	D	   X1  	F$  `Y+  	H)  hn  	J\   p&  	K\     	M.  w3  	Nv   x  	Q9   N  	RN   /F  	S.    	U>  U 	]   t  	_H    	`R    	a)    	b	   6p  	cW   	d\     	f\     	hj     	m    [  
\  '-  	-+p    \     >  G       t  C    M  )    \  (P  \      i   old 	   n 
\   t4 \    r  ~    G    ;   	`     )/7         G    2 1\     \  \   R   *> 
)  \    r X   D  \       + /               f /(r        )        15          +  %    E  A    `           h  f    v  p        l               U	SU&            )  U2Ts        	  R  U1Ts       	  o  U?Ts       	    U3Ts  ,     	  U=TU  - "\        h       |  sig "\       .s $|               %f        /                                 U	X&     TU        )  UU  ~  C \     	sig \   	f 0r  s |      	sig \    | 1     	ptr 1$   
T  10   ret 3    0die P              err /R      bh 
F  ~     >  n  T~1  	T&             U  Hm 
  
 
'R  	err 
;R  
bh 
H  msg           2G    T  m\     
/ ma  
u/ m<W   sw ]\   >  	__s ]   	__n ]   
u/ ]W  
0 ]          ~       	          4  .  3  w4  
T&              	    M  G    e  c  %  t  n  1           I
  UwT
 Q2R
 XUYT           v	              -       T2Q	&'     R	T&     Xw  N     T
                  I
                      G       .
    R  P    a  [        S              U	SU&       q     )  U| Tv   5vv lv  6/ /      {P  y     e    j (g   =w g     g   rh g   z 	g   W 
g     t     m   j "   y   	x         P  V                       2     }      ׵  int }  +K  -L     h           -K  o   mE  L     / 1 2   : *   F  u64 !   u8 *   9              y  	!L   G 	$P  fd 	&	a    $: 	'Z     	(Z      
l}      io (  fd a    x E   buf    end    P    :  a    eof   $  X= fa     a    VB   a     \  a    8 sP  %  a   {       R  %1  a   BG 	6a   V  V    a       a              9  	  !\  arg 1{   	  W  io #a  bf $\  err %a   3  
5O 0	   ch 1a   i 2
   
` 3   
7 4m  л  a   W  {   \         9     m  L       ~  L      9      0         io $  Xch a   l a  K   q     ?         	` !   l ڣ    5     <          	%    l  fa   R              io f*  Xhex f5  P
B h  kq            ch la   l      Va        W         io V+  X            ret Ya   l    /a        @      ?  io /.  Hn 1
P  X            
  7?  `    O  !L     "  "\     _         io "(  hfd "0a   dbuf #   X	x # E   ` #q 92   .     .         c 952   l $ 22         .       c 252   l   :;9I8   I   :!;9I   !I  $ >   :!;9I  4 :!;9I  .?:!;9'I@|  	 :;9I  
4 :!;9I  :;9   <  (   .?:;9'I<  I  ! I/   :!;9I   :;9I8!   .?:;9'I<  .?:!;9!'@|  %y     $ >  & I   :;9Ik   :;9  :;9   I8  >I:;9     .?:;9'<   '  !.?:;9'@z    :;9I8   I  4 :;9I   :!;9I   !I  4 :;9I  I  4 :!;9I  	 :;9I  
! I/   :;9I  .?:!;9!'I@|  4 :!;9I  .?:;9'I<  .?:!;9!'I@|  $ >  & I  (   .?:;9'I<  .:!;9'@|  .:;9'I@|  . ?:!;9!'I@|  :;9   :;9I8   :!;9I   :;9I     .:!;9'I@|   <   :!
;9I  7 I   :;9!  !.?:;9!n'I<  ".?:!;9n'I<  #! I/  $! I/  %  &%y  '$ >  (:;9  )   * :;9Ik  + :;9  ,:;9  -&   .>I:;9  /.?:;9'<  0. ?:;9'I<  1.?:;9'<  2 '  3
 :;9  4.:;9'I@z  54 I4  6
 :;9  7.:;9'@z    I  $ >   !I   :!;9I  4 :!;9I  .?:!;9'I@|   :!;9I8  4 :!;9I  	. ?:!;9!'I<  
 :;9I  7 I  I  .?:;9'I<   :!;9I  .?:!;9!'@|  & I  ! I/  .?:!;9!n'I<  'I  .?:!	;9!'I<     .:!;9!'I@|  %y     $ >  :;9   :;9I   <  ! I/  .?:;9'<  .:;9'@|    :;9I8   I   !I  $ >   :;9I  .?:;9'I<  .?:;9'I<  I  	7 I  
4 :!;9I  ! I/   <  4 :!;9I   :!;!9I  %y  $ >     & I  :;9   :;9Ik   :;9  :;9  ! I/  .?:;9'<  .?:;9n'I<  .?:;9'I@|   :;9I   $ >   I   !I  .?:!;9!'I<  %y  $ >  & I  .?:;9'I<  	   
.?:;9'I@|   :;9I  4 :;9I  4 :;9I  I  ! I/    :!;9I8   !I  $ >   :;9I   :!;! I8  4 :;9I?<   I   :!;9I  	I  
! I/   <  4 G:!;9!     %y   I  :;     $ >  & I  :;9   :;9Ik   :;9  'I  .?:;9'I<  .?:;9'@z  .:;9'I@|  4 :;9I  4 :;9I   $ >   I   !I   :!;!9I  %y   :;9I  $ >  & I  	.?:;9'I<  
   .?:;9n'I<  .?:;9'I@|   :;9I  4 :;9I   (    :!;9I8  $ >   !I   I   :;9I  I ~   :!;9IB  	 :!;! I8  
I  ! I/   <  H }   1B   :!;9I  7 I  4 :;9I?<  4 :!;9I  .?:!;9!'@z  %   I  :;     $ >  & I  :;9   :;9Ik   :;9  >I:;9  >I:;9  'I   .?:;9'I<  !.?:;9'I<  " :;9IB  #H}  $   %H}  &.:;9'I@z  '1RBUXYW  (H}  ).?:;9'I 4  *. ?<n   (    1B  I ~  4 1B   :;9I8  H }   !I  1RBX!YW  	 I  
H}   :;9I  4 :!;9IB   :;9I  4 :;9I  $ >  .?:!;9'I@z  1RBUXYW  1  1RBUX!YW  .:;9'I   4 :!;9IB   :!;9IB   :;9I   1  H}  1RBXYW  4 :;9I  (   1RBUXYW  1RBXYW  & I    :!;9IB  !4 :!;9IB  "1RBX!YW  #  $4 1  %7 I  &5 I  '.?:!;9!'I@z  ( :!;9IB  ).:;9'   *:;9  + :!;9I  ,4 :!;9I  -4 :!;9IB  .  /.1@z  0 :;9I8  1I  2 <  3.?:;9'I<  4   5 :!;9I  6 :!;9IB  71U  8! I/  9>!!I:;9  :.?:!;9!'<  ;.?:;9'I<  <H}  =.?:!;9'I !  >1U  ?4 :!;9I  @U  A4 :!;9!I  B.:!;9'I@z  C4 1  D.?:;9!'I !4  E. ?<n:!;!   F%  G$ >  H   I>I:;9  J :;9I  K'I  L&   M:;9  N :;9Ik  O :;9  P4 :;9I?<  Q! I  R.?:;9n'I<  S. ?:;9'I<  T.?:;9'<  U  V :;9I  W4 :;9I  X
 :;9  Y
 :;9  Z  [.?:;9'@z  \H }  ]1XYW  ^.?:;9'I   _.?:;9'   `:;9  a :;9I  b :;9I  c1RBUXYW  d1  e. ?<n    1B   :;9I8  4 1B   !I   :;9I  I ~   :;9I  $ >  	H }  
4 :;9I   :!;9IB   :;9I  4 :;9I  .?:!;9'I@z  1RBXYW  1   I  .:;9'   .:;9'I !  5 I  1RBUXYW  1RBUXYW  4 1  1RBXYW    & I   :!;9I  :;9   :!;9IB  H}     I  ! <  " :!;9I8  #H}  $. ?<n:!;!   %7 I  &! I/  '   (4 :!;9IB  ).?:!;9!'@z  *1U  +.?:;9!'I !4  ,%  -   .$ >  /&   0:;9  1 :;9Ik  2 :;9  34 :;9I?<  4! I  5.?:;9'I<  6.?:;9'<  7.?:;9'I<  8  91U  :H}  ;4 :;9I  <H}  =4 :;9IB  >.?:;9'I   ?:;9  @ :;9I  A :;9I  B.1@z  C. ?<n    1B  I ~  4 1B   :;9I8  H }   1   :!;9Ik   :;9I  	 I  
1RBUX!YW   :!;9IB   !I  H}  1RBUXYW   :;9I8   :;9I   :!;9I8  4 :!;9IB   :;9I  .?:!;9'I@z  1RBUX!YW  (   :;9   :!;9I  $ >  4 :!;9IB   :!;9I  (   4 :;9I  1RBXYW  H}   .:;9'I   !(   ".?:;9'I<  #4 :;9I  $.:;9'   %.1@z  & I8  'U  (  )1U  *4 :!;9I  + :;9I  , :!;9IB  -I  ..?:;9'<  /.?:!;9!' !  01RBX!YW  1:!;9!  21  31UX!YW!	  41RBUX!Y!W!  54 :!;9I  6& I  7 :;9I  8 :!;9Ik  91RBX!YW  :4 1  ;4 :!;9IB  < :!;9I  =! I/  >! I  ?.?:;9'I<  @. ?:;9'I<  A.:!;9!'I !  B1X!YW  C4 :!;9I  D1U  E:;9!  F I  G   H.?:!;9!'@z  I :!;!9IB  J  K4 :!;9I  L.:;9'   M.?:!;9!'@z  N.?:!;9'I@z  O4 :!;9IB  P1UX!YW!  Q%  R$ >  S   T :;9I  U:;9  V:;9  W>I:;9  X>I:;9  Y:;9  Z:;9  [:;9  \ :;9I8  ]:;9  ^ :;9I8  _'  `4 :;9I?<  a.?:;9'<  b  c.?:;9'I   d
 :;9  e.?:;9'I   fH}  g.?:;9'I 4  h  i:;9  j :;9I  k5   lH }  m1  n1UXYW  o. ?<n   I ~   1B   I  H }  4 1B   :;9I8  H}   :!;9Ik  	4 :;9I  
 !I   :!;9I   :!;9IB  .?:;9'I<   :;9I  4 :!;9IB  1RBUX!YW   :;9I8   :!;9I8  H}  1U   :;9I   :;9I   :;9I  (   :;9   1   :!;9I    4 :!;9I  $ >  .?:;9'<   H}  !  "  # :!;9IB  $.:;9'   %4 :;9I  &I  '1RBUXYW  ( :!;9IB  )4 1  *1RBX!YW  +.1@z  ,! I/  - I8  ..?:!;9!'@z  /.?:!;9'I@z  0H}  14 1  21RBX!YW  31RBX!YW  4& I  5:!;9!  61  7.:!;9'I !  81RBXYW  91RBUXYW!  :.:;9'I !  ; :!;9Ik  < :!;9!I8  =U  >4 :!;9IB  ?.:;9'   @4 :;9I  A4 :!;9IB  B :;9I  C! I  D :;9I  E'  F   G.?:;9n'I<  H. ?:;9'I<  IH }  J1RBUX!YW  K.?:!;9!' !  L4 :!;9I  M.?:!;9!'I !  N1  O.?:!;9!'@z  P>!!I:;9!  Q :!;9I  R:;9  S:;9!  T'I  U1U  V
 1  W4 I4  X
 :!;9!  Y.:!;9!'I@z  Z.?:!;9!' !  [.?:!;9'I@z  \4 :!;9IB  ]%U  ^   _$ >  `:;9  a>I:;9  b:;9  c I  d:;9  e :;9I8  f:;9  g :;9I8  h4 :;9I?<  i.?:;9'<  j.?:;9'IU@z  k.:;9'@z  l4 :;9I  m
 :;9  n
 :;9  o4 :;9I  p1UXYW  q1XYW  r.:;9'@z  sU  t.?:;9'I 4  u:;9  v5   w.1U@z  x. ?<n    :;9I8   1B   :;9I8   :;9I   :!;9Ik  4 1B   :;9I8  :;9!  	 :;9I8  
 :;9I   !I  I  I ~  4 :;9I  :;9   :;9I   1  1  1RBXYW   :;9I  4 1   I  4 :!;9IB   :;9I  4 :;9I  ! I/   I8  H }  $ >  :!;9  1RBXYW   .:;9'I   !:;9!  " :!;9Ik  #  $! I  % :;9I8  &4 :!;9IB  '  ( :!;9IB  ) :;9I  *1RBX!YW  +1XYW  ,1RBUX!YW  - I  ..:;9' !  /(   01RBUX!YW  1H}  2  3& I  45 I  5U  6H}  77 I  8 :!;9I  9:;9!  ::!;9!  ;1XYW  <.1@z  = <  >:;9!  ?! I/  @:;9!  A:;9!  B   C1RBUX!YW  D.?:!;9!'@z  E1RBUXYW  F :!;9IB  G:;9  H :;9I  I4 :;9I?<  J! I7!   K.?:;9!'<  L.?:;9!'I<  M.?:!;9'I@z  N :!;9IB  O.:!;9!'I !  P4 :!;9!I  Q4 :!;9!I  R1U  S1U  T.?:!;9!'I@z  U.?:!;9!' !  V.?:!;9'I !  W.?:;9!'I !4  X. ?<n:!!;!   Y%  Z$ >  [   \:;9  ] :;9Ik  ^ :;9  _>I:;9  `:;9  a&   b'  c.?:;9'I<  d.?:;9n'I<  e :;9IB  f :;9I  g1XYW  h4 :;9I  i4 I4  j.?:;9'@  k5   lH}  m1  nH}  o. ?<n   $ >   I  H }  I ~  %   :;9I  $ >     	.?:;9'<  
.?:;9'I<  .?:;9'@z   :;9IB   I  .?:;9'I@z   :;9IB  H}  . ?<n   $ >   :!;9!	I8  I ~  H }   1   :!;!9IB   :!;!99!I   I  	.?:!;9!'@z  
 :!;9IB  H}  %   :;9I  $ >     :;9   :;9I8  I  ! I  .?:;9'<  .?:;9'I<   I  4 :;9I  1UXYW  .?:;9'I@z  4 :;9IB  4 :;9IB  H}  .?:;9'I 4  . ?<n  . ?<n:;    I   1B  $ >  I ~   :!;9IB   :;9I  4 1B  H }  	 :;9I  
.?:!;9!n'I<  .?:!;9!	'I@z   :!;!
9I   !I  .?:!;9!'I<  1RBUX!YW!	  1U  1RBX!YW  H}  4 :!;9I  %  $ >     &   4 :;9I?<  4 G:;9  . ?:;9'I<  .?:;9'I<  H}   :;9IB  4 :;9IB  U   4 :;9IB  !.:;9'I   "  #4 :;9I  $.?:;9n'I 4  %.?:;9'I 4  &. ?<n   I ~   :;9I8   1B   I  H}   :;9I   :;9I  1RBUXYW  	H}  
 !I   :;9I  $ >  H }  4 1B   :!;9IB  I  .?:;9'I<  4 :;9I  4 :;9I     .?:;9!'I !4  7 I  ! I/  .?:;9'I<  1RBXYW  :;9!   :!;! I8  .?:;9n'I<  .?:!;9'I@z  4 :!;9IB  .:!;9'I !   4 :!;9I  !4 1  " 1  #4 1  $ <  %.?:!;9!'@z  &.:;9'   'H}  (H }  ).1@z  *& I  +4 :;9I?<  , :;9IB  -4 :!;9IB  .1RBX!YW!  /  0! I/  11RBUX!YW  2. ?<n:!;!   3%y  4$ >  5   6 I  7:;  8 :;9Ik  9 :;9  :.?:;9'<  ;.?:;9'<  <1UXYW  =1XYW  >.?:;9'I   ?4 :;9I  @U  A.:;9'@z  BI ~  C 1  D1U  E1U  F. ?<n  G6    I ~   :;9I8   I   1B  H}  H}   !I   :;9I  	 :;9I  
 :;9I  4 :;9I  $ >   :!;9IB  4 :!;9IB  4 1B  .?:;9'I<  4 :!;9IB  H }  I     1RBX!YW!  1RBUXYW  7 I  1RBX!YW  ! I/  :;9  .?:;9'I<  4 1  .?:;9!'I !4   :!;! I8   <   U  !.:;9'I   ".:;9'   # :;9IB  $.?:;9n'I<  % :!;9IB  &H}  '.?:!;9!'@z  ( 1  ). ?<n:!;!   *& I  +4 :!;9!I?<  , :!;9I8  -.?:!;9!'<  . :!;!9IB  /4 :!;9!IB  04 :!;9IB  11RBUX!YW!  21RBX!Y!W!  3.:!;9!'@z  44 :!;9I  54 :!;9I  64 1  7.?:!;9!' !  8.1@z  91UX!YW!  :%Uy  ; I  <:;  =   >$ >  ? :;9Ik  @ :;9  A :;9I  B'I  C&   D:;9  E :;9I  F! I  G. ?:;9'I<  H.?:;9'<  I.?:;9'<  J.?:;9'I@z  K.?:;9'@z  L  M1RBUXYW  N4 I4  O.?:;9'I@z  PH }  Q.:;9'@z  R4 :;9I  SI ~  T! I/  U.?:;9'I   V :;9I  W.?:;9'I   X 1  Y.1U@z  Z6   [. ?<n    :;9I8  I ~   I  H}   !I   :;9I  $ >  .?:;9'I<  	H }  
 :;9Ik  .?:;9'I<   :!;9I8  4 :!;9I  :;9!  I  ! I/  7 I   <  4 :;9I?<  H}  .?:!;9!'@z  4 :!;9!I  & I  4 :!;9IB  4 :!;9IB  4 :!;9I  .:!;9!'@z  H}     :!;9I  %y   $ >  !   ":;9  # :;9  $'  % '  &'I  '.?:;9n'I<  (.?:;9'<  )   *.?:;9'I@z  +1RBXYW  , 1B  -. ?:;9'I@z  . :;9IB  /1RBUXYW  0. :;9'   1U  2  34 :;9I  4.?:;9'I   5 :;9I  6.1@z  7. ?<n   I ~   1B  H}   :;9I8   I  H}  1RBUX!YW  4 1B  	(   
 :!;9IB   :;9I  1RBX!YW   !I  1RBUXYW   :;9I   1  4 :!;9IB   :;9I  4 :!;9I  4 :!;9I  $ >   :;9I   :!;9I     4 1  U  .?:;9!'I !4  .:!;9'I !  H }  1RBX!YW!  .?:;9'I<   1RBUX!YW  !& I  "7 I  #.?:;9'I<  $H}  %
 :!;9!  &1RBUX!YW  'I  (1RBX!YW  )! I/  * :!;! I8  +:;9!  ,.?:!;9!'I@z  - :!;9IB  .
 1  /
 1  0.:;9'I   14 :;9I  2.1@z  3. ?<n:!;!   4 <  54 :;9I?<  6>!!I:!;9!  7 :!;9I8  8.?:!;9n'I<  94 :!;9IB  :  ;.:!;9!' !  <1UX!YW  = :;9IB  >4 :!;9IB  ?.:;9'   @1X!YW  A 1  B'I  C(   D.?:!;9!'<  E.?:!;9!'@z  F
 :!;9!  G.?:!;9!'@z  H4 :!;9I  I  JH }  K1RBX!YW  L  M4 1  N4 :!;9I  O4 :!;9IB  P4 :;9I  QH}  R.?:;9!'I !  S6   T%y  U$ >  V   W :;9I  X I  Y:;  Z :;9Ik  [ :;9  \ :;9I  ]&   ^>I:;9  _(   `4 :;9I?  a. ?:;9'I<  b. ?:;9'<  c.?:;9'<  d :;9I  e.:;9'I@z  fU  g1U  h1  i.:;9'I@z  j :;9IB  k.:;9'@z  lI ~  m! I/  n.?:;9'I 4  o1U  p. ?<n   I ~   I  H }   1B   :;9I8  H}   !I  (   	H}  
 :;9I  $ >  1RBUXYW  1RBX!YW   :;9I  I  .?:;9'I<  .?:;9'I<  4 1B   :;9I  ! I/   :;9Ik     4 :;9I   :!;9I8  4 :!;9I  & I  (    :!
;! I8  .?:;9n'I<   :;9I  4 1   4 :!;9IB  !.?:;9!'I !4  "7 I  # <  $.?:!;9!'I@z  % :!;9IB  &.:;9!' !  ' 1  (>!!I:;9  ):;9!  *. ?:;9'I<  +. ?:!;9!'<  ,1RBUX!YW  - :;9I  . :!;9IB  /4 :!;9IB  0  14 :;9I  2.1@z  3I ~  4. ?<n:!
;!   5%y  6$ >  7   8 :;9I  9 '  : I  ;:;  < :;9  =4 :;9I?<  >'I  ?.?:;9n'I<  @.?:;9'<  A. ?:;9'I<  B :;9IB  C4 :;9I  D1RBUXYW  E.:;9'   F4 :;9IB  GH}  H1U  I1  J.?:;9'I@z  K  L.:;9'I   M.?:;9'I@|  NU  OH}  P.:;9'   Q! I/  R.?:;9'I 4  S4 :;9I  T.?:;9n'I 4  U. ?<n    :;9I8  I ~   1B   !I  $ >   :;9I   I  H}  	 :;9I  
 :;9I  1RBUXYW!  I  ! I/   :!;! I8  4 1B  H}  7 I   <      :;9IB  H }  4 :;9I  :;9!   :!;9I8  4 :;9I  .?:;9'I<  .:;9'I   .:;9'   .?:!;9!'I !4  .1@z  %y   $ >  !   "& I  #'  $ I  %:;  & :;9Ik  ' :;9  (4 :;9I?<  ).?:;9'I<  *.?:;9'<  +.?:;9'@z  ,H}  -.?:;9'I@z  .4 :;9IB  /1RBXYW  0.:;9'@z  1I ~  2! I/  34 1  4 1  5. ?<n:;  6. ?<n    :!;9!I8  %y  :;9   I  $ >  & I  4 :;9I?<  4 G:;9    I  $ >   :;9I  4 :;9I   :;9I   !I   :;9I8   :;9I8  	 :;9I  
4 :;9I  I  & I  .?:!;9'I@|  .:!;9!'I@|     :!;9I  .?:!;9'I<  ! I/  %y  $ >     !   4 :;9I?<  :;9  :;9  .?:;9n'I<     . ?:;9'I<  .?:;9'I<  U  'I   .:;9'@|  !! I/  ".:;9'@z  #.:;9'I@z  $.:;9'I@z                  	  T   }                 -  O  R      h    q  [  
                                '    3  >  L  Y  b  z              	  
  
                      	      "  ,  8  B    P  [  l  l  w  u                  
    "  .  =  H  W  e  t  r     	     tg?0t&	X'	X&0
u	/u
;X	t7Xt	ttʟ	Y1!0u K	K1

??	ftK I
LvtYttg	f=1jf
Y9v?D+<	ug	=3
	vf
KtYJ
JJYu"h+7f/JK1<<Kuf  J f	=1/	f1=
$t5/>   t  ; J f[ Y 	               	    }   T                 -  O      F          h  q  [                                                    '        t  r      	  
                  	      #    3  >  L  Y  b  z      	      "  ,    8  B    P  [  l  l  w  u              
    -            3  3  ;  P  Z  Z  a  m      "  .  =  H  W  e                  
    	  
    	  
      
        	    
       
.  
         ?   P    	     #	!

@
Ktd tgu
 Xg t" J JK
 Xguwt.>u
v
t	Y\YgZ	g:.'	!YL"	fq@  	.	!.=	o
<	 	uQ $.   J .. Xf/ $.   J .. Xf/ $.   J .. Xf/ $.   J .. Xf/ $.   J .. Xf/ $.   J .. Xf1"
  K  	z)	Y[ X
Ku
J	vY[/  K  Yuv	yX
Y1=/t Y	UyRLt}t/	/
uv 	
Y	u  <K  ;L ;L % %?1Kt$:}t"	0 " X gw t $K6 L y	<!	K1<% vg X
 ..0 XY
 gw	=\f% vg X
 ..0 XY
 <utgw	=_	=u6	=u1$
 gfK X
 ..Y "g!	g[.% wg X
 ..0 Xgv	=[-
v	7\,
v	7[	=u1	=u1&
v	7[-
v	7[&

7 gfK X
 ..Z
 
2
20	gZ&
v	7[%
v 7
u	vg     R           	  T   }   F              -  O        f[  [  h    j        j                            '    3  >  L  Y  [  q  b  z      	    t  r    "  ,    8  B        P  [  l  l  w  u                    s  
      #              	  
  
  	       	.  	   
        	  
  
    "  .  =  H  W  e                 	5.     =+?
uv	Zu1
uv	Zu1
uh	K1Y?  "
K	vK[?  "
K	vK[?0	u	K11u
w%	=2=2t X t- X  J X	 KKS3Z)0 30 "	#Y             	   	  }   T         F        L      h  q  [                              '    "  ,    8  B        P  [  l  l  w  u                                  3  >  L  Y  b  z      	      
  t  r      #    "  .  =  H  W  e   	]3     -	t X   K !

|ZY ? L\ </ X.    <[`.BB<@	_ " &tY
 vtYg#t J 
	vY 1                	     }         T      &                              h      '    3  >  L  Y  [  q  b  z         #    "  .  =  H  W  e   	7      
Kv	+                 T   }                            q  [    P   ?                       h  '    3  >  L  Y  b  z       	7     ]$-	)g	= z    J             T      }            F  -  O      2    h                          t  r        '    3  >  L  Y  [  q  b  z          #        B        	  
  
  	       	.  	   
 	8     gug	2K )    ~           }   T         L                   q  [    ^      	  =   	9     
	~
tfX<~
 XX 	9     ~Of[Ks)/X Xu..                F  	  }   T      O  L       	  	   	   	  	  	  	      B    h        
  q  [  
  	=    E       
	       ^   	 ;     9</X 	@;       <t	XX=kX
 tX JJ	 JX 
  X 
  < Z  XZ!qX w'<'< T  J`~<
~%  Kt~=X 	<     MX	XYYkJ'	wgYk#X 	P=     Y1_H	
#B.	 ~  f xo<	 f  Ms. ? Xf<X 	=     # XX e	
B	 ~   =O	 t   Mr.  XI f KiU	
#B<	 ~    Jj     f J
;tX EJ 9
<X 
E 
   J XJ < 	 eX=t# 0 J ?     Sf .tXM `"X)sJ ) JpLZ>! f J, <9 ?     
t   
X    
  
 
 J	V -
qs =)<<YS<
XxX.:X	 XJ(J	 XJ*	V  t /<K t
XZ
X^sXxX|xJJq XK

IKZR
 /Y I/	YRxKk5 $GX$9 I$  XK$ ;$K  $$ >  ;$= W  $= W $ W  x֞J
9T
8.t ~	XYYk#t~J<..X 	@D     uX 	[	YU~!<X
1X 	D     )XmX<X 	D     5X~X5 X 	 E     [`& ~f& 
wX 	pE     gX 	E     P</0<!~<=~!<w	/.x
FfT<.X 	0F     eP</0<~!fw	/.xJ.& I fx.<.	X 	F     [ffMJ    [ t J!   JY~  f
rtJX 	PG     ~X X 	G     ^z.^z<tX X f J  . S	Xt..
W]!X 	`H     ffL~XJJ	   [ 5    JY~! < /= 
wXX 	 I     4[~JJ	    .5   ~! < /=  
#.^&Y	  
 )
 ;K<'~' .=;Y!}<'b~J'  X XK}!! k~fJ'z<~' \A~  X }!X<W~  JZ Y(;=Y=	_XY	  #  X5   ~! < /=  X	 =
 [
 ;K<Ys=.~ v<<. 
.v <.t
gXX ~JJ	    .5   ~! < /=  < 
#.
]J#<
] Y	  X&  
.^	  #  X5   ~! < /=  X 
!.
_J!<
_ & &:  XY}!!f h8@tJ&xJ X|<	J=f|Kk&I<.w&:  }!!f h ;i& f&J G             
  }   F  	     T   O          
   
   	  	  	  	        h        q  [  
  	    	  	    	 N     	JK X>X@Yn+	S:
 /<	S.H	>HL
 -< XTfJ.Y<ItKX 	N     Y<It YX 	0O     f<	XJJcX@	qX
 /<	Qf
 /Jan+
  XTt    K W [kt	y   K W {[		JY_H	
#B.	 ~  f xo<	 f  Ms. ? Xy<X 	P     # XXce	
B	 ~   =O	 f   Mr.  XX8
 FKiU	
#B.	 ~  +  J 	! e	K X!  hqJ< q< T   f J % Y
't<X 	Y 	  X X=X 	 R     ]<JK
xX 	PR      [  t f# < <J	zX              
  F    }      T   O  L  -
     %
   %
     
  	  	  
      h  B        
  
  
  	  
  
  
  
    	    
    
   	R     Ztt<VRgruX 	S     XZqXttVRru
..X 	T     tYYJXttY!JX
./;JX< Xv  xt6P thw5J,<J,J
6J<.  YPf! ,  J
X /<.. -u < /~<J ~J ~  t~ w,<J,J	J 
 JKY }~tJ7  ~  J~ J J8  ~  J t~  J#tY..w.t t~J ~t ~  ~ w,<J,J	J 
 JKu }~tJ7  ~  J~ J J8  ~8  J t~  JtY
tJX/X	.X<J r  	@t  <u~t wu	t w ,<J,J  J < X 	k J< tJ	 <0J	X ~,J JJ<0 jX  J  e  X  .	(
k<X@3 < X  6J.P fhw5J,<J,J
6J<.  YPf! ,  J
X8 upt Xu=*< X/	 xJ . XWt
 X&t/< _X~J u~ w,<J,J	J 
 JKY }~tJ7  ~  J J%&<   t ~J ~t ~  ~ w~,<J,J J <<~X w,<J,J	J   z~J>  ~ ~J J4 I ~  X ~ 
Y
~..Jrv<it ~-f v!  ~tJ ~
t u~   ~Xw,<J~<,J	JZ i
~ hw,<J,J	J<Z
!zJ> z  ~t ~JJ JY~~t
~<X4  ~   K~ 	zfY<
fwX.iY;t}tf }<hw},<J,J J <  t}X fhw},JX) 
1X 	`     f?vXi</q?0	tXtX 	`       J<<?X>vX19Mg? } w,<
 $J\ 
 $J,\f	J}  <t|X fhw'  <	 nt< X[SJvKKKXX
	f 
 XNk}
  
 } t`K@8N8v<XKq?}t w},JX  < Xr.	 w	<	  	<XYJ.Y=u.JZ
/| J,|t	X <;W<	XJ

 XJX 
XX  u|<J  |Zw|,<J,J J < JM	= G  | |JJ Kn|  fX	X.	zPb#<)A)Jt |hw,|J,<J J tM	     KY|f\<..	sK? |<J, | |  J |Zw|,<J,J J < JM	= G  | |JJ JKn|  XX6 , |6 , |,  J ]|  !2	/ W|<J  |Zw|,<J,J J < JM	= G  | |JJ Kn|  fX'X.	\$J |<J, | |  J |Zw|,<J,J J < JM	= G  | |JJ JKn|  XX6 ., |6 , |,  J N|  02	/9/;0 . 0  E | |.J  |tZw|,<J,J J < JM	<= G  | |JJ Kn|  ff: 7  J	Lt9....w =X 	i      =X 	 j      	`j     <X.X u[&J Xu
yX.zJ
z
t[tY qYH X|SqJK 
(B<  8 V   f <  2X6I6/ X 	 l     
I|x{ftJX .  J 
JXXY{ >{J{J<> {JYt{tu XJ{>< J J
;K/KWKJ	K
sJxYJYs`Y/
x JY*J7  W7t*(X                F    }   	  
  T   O        L  -
  %
   
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  
      	  	  
    B    h          	  	^  

  

  
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  
  
  
  
  
E         	
  
       	`n     #Y<IuI>YX 	n      		XX 	 o     gJ ?9 ?X	=N*'tT JJX= [JuX< t< % tJX% t  f$g
o'|tV]SLGJpJY }~XtJqK 
(B<  8<KX 	p     YWY~\uOE<Y  ~+
=J	w.<
wX 	q     ~s X< t	 	 X5/ sf  sY zIY .yYA. 0. rhrLY.' $ 
.$ vtg
\ tY(  u KdLZ  X s  <   Xt. tY sY te   t sY t= JF t<y X
 .]-  	x-  .n808rh 5~XXugYJK<LhsYX 	 v     4JY/JX(xJY! MJYY M Mz< < X<      X Jf      X <&   X<      X J < <      X <J    J  Z<Jit    <  Y	YQzfY	3<J    <  Z<J    <  Z<J KX 	py     Ft Y;t}tf }< fd}w,J	X}
KK}tY
==YKY}ftJX 	z     YIz<Jo} }<JX<.}<YeJM X	"~	 >J}
  J 2 J>:>tMM}t f fd}w,J	X}
KK}tY
==YKY}ttJ	,/
`' t;=I.\FK  ~X   	`x	DxXD	=	JIXQf{t{J  Jw,X :oJ<{	k<w  Mt ~>~~.lX F~.IXQf{t{J w,X{< JoJ<{	k<Xuw  ~>~~./ Juw   <    a	`x	DxXD	=[	JIX~f/ Juw <~|t w,XJJ	|<u;K  f 3  <  	 DIX& X  X J <~|t wJ,|<	Xg;K  < 'XX X 	P     ~J< \yJ.	f r <	 :    _
} f	N/<.b9 
L
}<
.
} <kY;It<0K/  <=t?X...		<JX 	     		JXX 	0     t YKt IK&  jt Y/t IK&  jIu ;X{YbJ XSqJB>K 
(B<  8< V   f <  3mMWhXI=<;fJg  tzJP*dJYI/ X L<  t   <  Y2 f:t L  JYIg\Yu X uv   J/  Jg #
	X/" . <uv  fJYI=\=,v     0 f.  Juv fJX}I/Y< y<.	X r <	 :    _
} 9   J t X  u Jv\ <FK f 	`x	DxX=	=	JYJPf{t{J wJ :Z	{J<{	k<  JL~0~~<J~/ JuwuJ .~|t wJ	|<Xg-K   3  J   $  )  J	J<J	#2. DX tU "  <" J "  <J<JK	t~YJ%t<   ~YJPf{t{J wJ :Z	{J<{	k<Y< t JL ~>~t~./ Juw   J  	`x	DxX=	=[	JYJ%.  J<J .~|t wJ	|<Xu-K  < 3  J   t  t}t
 X 	      _y<v	{yJ!o!O7O!	0!HL	YYMs, J X 	      Z,x  Xu  < :    \gȐ 	p     u<n X:.#u  < :    \fotJX 	     \* X   <^ yC yf X <
Xft<	/uidZX  		     .  .  	 y               F  	  }   T   O     -
     L       ##   #   	  	  	  *    	  8    h  B        q  [  
    
  	A  	Q  	a  	
  	
  	
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    
  	  q  E   
     ^  	 	     
u=K ktrYKX 	@     X 	      [9 9}ty<5=v  .x.J  >kK	-Y<..y.u
4JY	;Yb Yuuzkt	JY!J# B	 ~  J xo<	 t  Ms. ?nXX 	      wfU	
#B<	 ~ 0 e	
#B<	 ~   =O	 t   Mr.  XN f Ke	K;Yb Yuzkt	JYr X"Y	 
#Bt	   X 	@     
gLjo< 
(Bt  %XU	
#B<	 ~   Zvy>wY	 
#Bt	  0 & f XX 	Е      #HB	 ~ " fVCY	 
#Bt	   !sKG!</# < .
 LtJJ'<Ju<BfG X0Kf= Xnt`:t>fY 	K	,.7"
J .tYf=.
>ht    f J K
w y J 4
Lt<X 4  
 
	f#mB	 ~ M"Y<	 
#Bt	   KX 	      #JB	 ~ 
 JJ0>"2{-Jy<-5y<2C	<JyOJL$ >'1<9<<Y
Lg=KFL	=Ft<J~<
    <0
JJJJ"u"~&<~Y	 
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8..t=
 6%t<.;< K~&~<0}
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B  }
B  g}
#BJ  }
#BJ   	}
 #}JB<	  	}
#BJ	   
i.4X~&<~X.~XJ~<<
w	<
xX=CY*|<,<>|%|J*<	 >	uX      @             T          h     	     		XX 	      <Yu.. +    \           }     T      F        	  
  h    
      	p     1Z:	Yu1*JJZK=KGKHuX.J.X 	      
 #X J]	u
 "Xa
   td.XX     ]           }      T     	            h         	     $Jd		1	u<.w<	
  t X X Xvt	</1	i9J=	1	v<	.=w<
  <v X X X	g&JG		1	u<.w< X X X0Yt	<%/ 
              }   T            F     -  O        q             	  h             q  [    
             	    	    +  G    #                        '      B          	  	    
     .     	  t  r    V    "  ,    8        P  [  l  l  w  u    j  t                          "  .  =  H  W  e    	            s  
    3  >  L  Y  b  z        	     	
  Jt> 
  < X X 
 tX#];Y Jt/  f h 
   X X s= X 
 X J XJ X" X X" J X 
   
 6  Jt Xw> 
t ~t ~ J
 ~X=>
 ~
t ~t ~
Jt ~ J w(> 
t ~tt ~ jY  */0 
XJ XQKpNSKMX 	     1Q -[ 
  X	Ka

E] U&K[ ZZ<tI X[^
tX.%<%< Xu! X\! FN?KpxAX 	      Kt
]zP
 XxX	tK	I
?=Zd>Y L
t ~t tY
< ~X[ Lt  "Ko "y p@ 8 ! t  t(< <
JZ
>  g! I  J XZJo
XZ
> <xX6
W!g< KV.WJ <K[]	=;	Yt KVYz 
t .X 
y     &             }   F  T            -  O                       	       h         q  [          j    	      j                           '    3  >  L  Y  b  z      	    t  r    "  ,    8  B        P  [  l  l  w  u    j  t                  s  
      V    #                	  	    
     .     	             2  D  T  f  w            	      	      	              "  .  =  H  W      e              	    +  G   	     *K	<<JJX 	      0:itKbZY} sYYY }Y t  J. Xh  <]
#]<#  V
=W XFS$+
UJ #
]J #f
]< # YJX
<    tJ<f dX$ vX<~X
  Jt> 
  < X X 
 tX#];YzJK2J;JYY=
    h J  . hJX=Zf IKIJKfJ t<Z:=Y J<
t b.  	~<~J	 X  M~Z
 ~<
t ~t
X ~U K  # Y\ f  >Ȑr 
it [ ~K yJ 	 .u   fv X HYJ
.KJ) s	X X2J0JJ  I f\	. .KJY;MH% + f  V X f   \ XU.YLI<eX 	@     KX
<
Gv X6X	KWKH\WKt;yX < g"  JZׂn KKt.!JKKz^E\KzXJ 	       KsX=X>  <i=  K	xJ Z  KvIg....-lY Xi=	FZ	x ZK  i JU	0 . .$J$.=# d f [  J	I . .%J%.=$ d f\~
X~
. }<!>
J.~
~
<
~JX  J
~J
~X Y~
~<.X~
." <" <}X<>
J.~
~
f.. i E 3  tK   JY	s < t tY MHZ X	I/   		                         }            T     -  O      y            l    q  [            
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 |.#<RKg/ =;JF{
 {<<
 {X X#<7 ~, XQ W ~  .- JJX<%JK;YftYz*	 J J3WX X ~=i< u  < 
J   <J}	=	X* .   <t
/   Y4 I$~|	    -Jh$  .$ K%$ ~ ~t  X <i|	      J  JZ|	   - -J J   J~ f-W -< JY$ $ WKA ~  f 
|t<X	|
<t     <[{ 
t ~t
t ~ <{JX$    J{X{
 ~
t ~t
t ~[{J|
f   ]  J{
 ~
t ~t
t ~[XX6X.X ; s Kt <s|
f   ft t X "X  X!6XX };X.&  uȺ~
}	  f }X	* f X* }X Xp:XJ]J. VK=& 1~  .)X2	2<	< X|	    t	|Xf|J	*   J
	   < t X XZtXXX~}	    -X   0O-K/JYOsX 
XvX 
-N    t X    t J J} 2
}J t
}XJ XY-M   J J-5Ȃ-K;}KJXJXX  Y  <{
 
{JX%    J X{
<~JX -K   5-KJ XtJ
6T-Pt5J}tXJ\<XXAX|.Jd XX~JY{

{JX?G-}   5J-K<5J L.J֐~X}
tXX\dtXXJfK	f.X 	`     KL.M3S37.XKr 	<w	JvJ	# 'H '< JJ <..q<JX	Y# 'H '< JK  fKJ.. Kf k-J	# 'H '< J JX<...bXJX	Y# 'H '< JK  f-K-I JJ.  W    S          }   T            F       -  O      %        %   3  	    h         q  [       <  	                                 "  .  '    =  H  W      e      "  ,    8  B        P  [  l  l  w  u      j  t                          #                	  
  
  	       	.  	   
      t  r        C  R  [  [  e    V  	    +  G        	  
  
                  &    <  I  [  g  t  ~              	    {          s  
    3  >  L  Y  b  z     	      	
   Xt> 
  < X 
 tX/];YR 
v.
vJ= J
 ; < Ju X=J
<
<YM
J X X
J V JJ 	 ;[f
<
<	/   wJ	f?  sJf\  yJ_?  u 
JY/
J XVBd...dut Jd.X.dut Jd.X.duu ;2 X=<<  t
wfNyt J  Jt  ~ X 	L<L	Z<dJ<hJY.#	L< fXH.2rL.$Xf W  <  
 ~X
 ~J0~
  < X>:X> 1
 X< XL
 Y
I 	z%
pt=	 J X .[  
t<X XK>6t
W
ZKW.f
ZW[	=`X?K =YM e	=	X 	P     z
 ~.Jr~
 ~< < 
 ~K)A/);-<		Y a              }      T              F  -  O      y               h       q  [       	                      '          w  u                  &    <  I  [  g  t  ~        "  .  =  H  W      e                          	        t  r    "  ,  8  B    P  [  l  l    j  t      s  
    3  >  L  Y  b  z    	    +  G    #              	  
  
  	       	.  	   
 	     	
  Jt> 
  < X X 
 tX#];YG0r&J=O t< J J <   g <JX=Z d
=IJJ ;K<vgX .<nKj<nJ&X<&tJ>JM  h
4
UetX 	      KeXjJ t J J <   g <JX=Z d
usJt sK<vI X @     8                 
            f          F     }   T   O           -           j              h                                             '      B    	    +  G  #    	    	  
     	.  	         	          	        "  ,    8        P  [  l  l  w  u                    
    t  r    "  .  =  H  W  e      3  >  L  Y  [  q  b  z             	      2fK	KK1fK	KKf.	!

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t	Y\YgZ	g6Lg fgtt	< fgt#t	< fgt#t	<gvYqJX.	 1= f1 fX .Y1 = f fX . X=1 fe0"3<
 hf
K_ YZ g Y
Z	/K )  	>/g	t#	g _SC_MAPPED_FILES _SC_MAPPED_FILES __S_TYPEISSEM(buf) ((buf)->st_mode - (buf)->st_mode) _SC_XOPEN_LEGACY _SC_XOPEN_LEGACY __ldiv_t_defined 1 _POSIX_THREADS 200809L __S_IFDIR 0040000 __FLT64X_HAS_QUIET_NAN__ 1 __FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__ __UINT16_MAX__ 0xffff __SIZEOF_PTHREAD_CONDATTR_T 4 __ILP32_OFF32_CFLAGS "-m32" __OPEN_NEEDS_MODE(oflag) (((oflag) & O_CREAT) != 0 || ((oflag) & __O_TMPFILE) == __O_TMPFILE) __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 _unused2 _unused3 _SC_SIGSTKSZ _SC_SIGSTKSZ _SC_LINE_MAX _SC_LINE_MAX _SC_XOPEN_XCU_VERSION _SC_XOPEN_XCU_VERSION __FLT32_DIG__ 6 _WCHAR_T_DEFINED  ESPIPE 29 _fileno __glibc_has_attribute(attr) __has_attribute (attr) _SC_CLK_TCK _SC_CLK_TCK _SC_ARG_MAX _SC_ARG_MAX _SC_V7_ILP32_OFFBIG _SC_V7_ILP32_OFFBIG __ASMNAME(cname) __ASMNAME2 (__USER_LABEL_PREFIX__, cname) EMEDIUMTYPE 124 __FLT64_MANT_DIG__ 53 __GLIBC_INTERNAL_STARTING_HEADER_IMPLEMENTATION  _SC_BC_SCALE_MAX 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(((__cpu_mask *) ((cpusetp)->__bits))[__CPUELT (__cpu)] |= __CPUMASK (__cpu)) : 0; })) f_ffree __align N_PROFIBUS_FDL 10 FIOGETOWN 0x8903 TIOCM_CD TIOCM_CAR SIOCGSTAMPNS SIOCGSTAMPNS_OLD SIOCBONDCHANGEACTIVE 0x8995 __pthread_mutex_s SHRT_MAX __SHRT_MAX__ _POSIX_LOGIN_NAME_MAX 9 sysfs__read_str TCSETX 0x5433 INT_LEAST8_MAX (127) STATMOUNT_MNT_ROOT 0x00000008U MOVE_MOUNT_F_AUTOMOUNTS 0x00000002 MS_RDONLY 1 TIOCSLCKTRMIOS 0x5457 __isprint_l(c,l) __isctype_l((c), _ISprint, (l)) SIOCSPGRP 0x8902 TIOCPKT_START 8 FSPICK_SYMLINK_NOFOLLOW 0x00000002 PTHREAD_MUTEX_NORMAL SIOCGSTAMPNS_NEW _IOR(SOCK_IOC_TYPE, 0x07, long long[2]) _POSIX_THREAD_KEYS_MAX 128 _POSIX_THREAD_DESTRUCTOR_ITERATIONS 4 TIOCGSOFTCAR 0x5419 _BITS_POSIX1_LIM_H 1 XATTR_SIZE_MAX 65536 UCHAR_MAX (SCHAR_MAX * 2 + 1) _BITS_POSIX2_LIM_H 1 ispunct(c) __isctype((c), _ISpunct) _LINUX_LIMITS_H  __CPU_SETSIZE 1024 CLOCK_REALTIME_COARSE 5 __BITS_PER_LONG 64 N_SLIP 1 MS_MGC_VAL 0xc0ed0000 TIMER_ABSTIME 1 N_R3964 9 isalnum_l(c,l) __isalnum_l ((c), (l)) MOUNT_ATTR_NOSUID 0x00000002 fs__check_mounts _POSIX2_LINE_MAX 2048 _GCC_NEXT_LIMITS_H  MS_SILENT 32768 MS_RDONLY MS_RDONLY CWERASE CTRL('w') MOUNT_ATTR_RDONLY 0x00000001 _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1) PIPE_BUF 4096 _POSIX2_BC_BASE_MAX 99 _STDBOOL_H  SCHAR_MAX __SCHAR_MAX__ UINT_MAX (INT_MAX * 2U + 1U) SIOCSIFMEM 0x8920 MNT_FORCE MNT_FORCE SIOCGIFENCAP 0x8925 MS_RMT_MASK _POSIX_TIMER_MAX 32 N_HCI 15 __CPU_ZERO_S(setsize,cpusetp) do __builtin_memset (cpusetp, '\0', setsize); while (0) INT_MIN (-INT_MAX - 1) fs__hugetlbfs MS_KERNMOUNT MS_KERNMOUNT __isupper_l(c,l) __isctype_l((c), _ISupper, (l)) PTHREAD_KEYS_MAX 1024 __isctype(c,type) ((*__ctype_b_loc ())[(int) (c)] & (unsigned short int) type) SIOCGIFMTU 0x8921 INT_LEAST16_MIN (-32767-1) _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1) sysfs__read_ull BLKRASET _IO(0x12, 98) FSOPEN_CLOEXEC 0x00000001 __fsid_t INT32_MIN (-2147483647-1) MS_UNBINDABLE (1<<17) UINT64_MAX (__UINT64_C(18446744073709551615)) __user  WCHAR_MIN __WCHAR_MIN MS_REMOUNT MS_REMOUNT bpf_fs_init_once procfs__mount _IOW_BAD(type,nr,argtype) _IOC(_IOC_WRITE,(type),(nr),sizeof(argtype)) _BITS_TYPES_STRUCT_SCHED_PARAM 1 SIOCBRADDBR 0x89a0 BLKSECTGET TTYDEF_OFLAG (OPOST | ONLCR | XTABS) LLONG_MIN (-LLONG_MAX-1) _POSIX_STREAM_MAX 8 MNT_ID_REQ_SIZE_VER0 24 INT16_MAX (32767) _POSIX_ARG_MAX 4096 __ispunct_l(c,l) __isctype_l((c), _ISpunct, (l)) _POSIX2_EXPR_NEST_MAX 32 BLKFLSBUF _IO(0x12, 97) _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) PTHREAD_MUTEX_TIMED_NP XATTR_NAME_MAX 255 TIOCSERSETMULTI 0x545B atoi f_frsize CLNEXT CTRL('v') _T_PTRDIFF_  MS_LAZYTIME MS_LAZYTIME _SYS_MOUNT_H 1 ACCESSPERMS (S_IRWXU|S_IRWXG|S_IRWXO) SIOCDARP 0x8953 UINT_FAST8_MAX (255) STATMOUNT_MNT_NS_ID 0x00000040U _POSIX_THREAD_THREADS_MAX 64 SEM_VALUE_MAX (2147483647) filename__read_xll _POSIX_PATH_MAX 256 SIOCGIFBR 0x8940 SIOCSIFSLAVE 0x8930 _IOC_NRSHIFT 0 _POSIX_LINK_MAX 8 MS_NOEXEC MS_NOEXEC N_SYNC_PPP 14 INT_FAST64_MAX (__INT64_C(9223372036854775807)) LINK_MAX 127 TIOCM_CAR 0x040 TIOCM_DTR 0x002 pthread_once FSPICK_EMPTY_PATH 0x00000008 PTHREAD_DESTRUCTOR_ITERATIONS _POSIX_THREAD_DESTRUCTOR_ITERATIONS MS_REC MS_REC sysctl __BITS_PER_LONG_LONG 64 BLKSECTSET MS_NOATIME MS_NOATIME _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK) _GCC_NEXT_LIMITS_H CSUSP CTRL('z') BLKBSZSET _IOW(0x12,113,size_t) __owner LLONG_MIN (-LLONG_MAX - 1LL) __isspace_l(c,l) __isctype_l((c), _ISspace, (l)) __isxdigit_l(c,l) __isctype_l((c), _ISxdigit, (l)) name_len st_fs tracefs__configured filename__write_int S_ISCHR(mode) __S_ISTYPE((mode), __S_IFCHR) _SYS_TTYDEFAULTS_H_  SCHED_RR 2 __struct_tm_defined 1 TIOCSCTTY 0x540E SIOCSIFNAME 0x8923 _POSIX_NAME_MAX 14 STATMOUNT_MNT_BASIC 0x00000002U _ISbit(bit) ((bit) < 8 ? ((1 << (bit)) << 8) : ((1 << (bit)) >> 8)) _IOC_TYPECHECK(t) (sizeof(t)) __CPUMASK(cpu) ((__cpu_mask) 1 << ((cpu) % __NCPUBITS)) SIOCBONDSETHWADDR 0x8992 __lock sysfs__mountpoint MS_MANDLOCK MS_MANDLOCK UINT_FAST32_MAX (18446744073709551615UL) COLL_WEIGHTS_MAX 255 offsetof __undef_OPEN_MAX PTHREAD_MUTEX_DEFAULT __pthread_list_t fopen STATMOUNT_MNT_UIDMAP 0x00002000U SIOCSIFBR 0x8941 MS_NOSYMFOLLOW MS_NOSYMFOLLOW TIOCM_DSR 0x100 __fsfilcnt64_t procfs_init_once strdup _POSIX2_BC_STRING_MAX 1000 TIOCCBRK 0x5428 TIOCSERCONFIG 0x5453 TIOCGEXCL _IOR('T', 0x40, int) SIOCBONDINFOQUERY 0x8994 BPF_FS_MAGIC 0xcafe4a11 _SYS_STATFS_H 1 ULLONG_MAX __WCHAR_MAX __WCHAR_MAX__ TIOCSSERIAL 0x541F MOVE_MOUNT_T_SYMLINKS 0x00000010 _IOC_DIRBITS 2 isprint(c) __isctype((c), _ISprint) __CPU_FREE(cpuset) __sched_cpufree (cpuset) MS_NODIRATIME 2048 __toascii(c) ((c) & 0x7f) BLKROSET SIOCSIFMAP 0x8971 DEBUGFS_MAGIC 0x64626720 CQUIT 034 CLOCK_BOOTTIME 7 __API_DEBUG_H__  MS_ACTIVE MS_ACTIVE _IOC_SIZEBITS 14 strlen __S_ISTYPE(mode,mask) (((mode) & __S_IFMT) == (mask)) _POSIX_NGROUPS_MAX 8 UINT_FAST16_MAX (18446744073709551615UL) XATTR_LIST_MAX 65536 MS_SYNCHRONOUS MS_SYNCHRONOUS MS_LAZYTIME (1<<25) RE_DUP_MAX (0x7fff) FIOSETOWN 0x8901 CHAR_BIT __CHAR_BIT__ false 0 timeout_ms CLOCK_REALTIME 0 PTHREAD_MUTEX_INITIALIZER { { __PTHREAD_MUTEX_INITIALIZER (PTHREAD_MUTEX_TIMED_NP) } } FIONBIO 0x5421 SIOCSIFBRDADDR 0x891a temp SIOCGPGRP 0x8904 TIOCPKT_NOSTOP 16 BLKGETSIZE64 _IOR(0x12,114,size_t) N_STRIP 4 pr_warn(fmt,...) __pr(__pr_warn, fmt, ##__VA_ARGS__) SIOCWANDEV 0x894A __data MOUNT_ATTR_NOEXEC 0x00000008 FSPICK_NO_AUTOMOUNT 0x00000004 TIOCMBIC 0x5417 MS_STRICTATIME (1<<24) TIOCGSID 0x5429 __isdigit_l(c,l) __isctype_l((c), _ISdigit, (l)) isblank_l(c,l) __isblank_l ((c), (l)) OPEN_TREE_CLONE (1 << 0) INT_FAST8_MIN (-128) hugetlbfs__configured SIOCSIFPFLAGS 0x8934 CLOCK_PROCESS_CPUTIME_ID 2 __isblank_l(c,l) __isctype_l((c), _ISblank, (l)) tracefs_init_once PTHREAD_CANCEL_ASYNCHRONOUS PTHREAD_CANCEL_ASYNCHRONOUS _BITS_STDINT_UINTN_H 1 BLKRRPART INT_FAST16_MIN (-9223372036854775807L-1) MS_SLAVE (1<<19) ALLPERMS (S_ISUID|S_ISGID|S_ISVTX|S_IRWXU|S_IRWXG|S_IRWXO) ARG_MAX 131072 CREPRINT CTRL('r') CRPRNT CREPRINT _PTRDIFF_T_DECLARED  pthread_mutex_t MS_SHARED (1<<20) _LINUX_IOCTL_H  SIOCSIFVLAN 0x8983 N_PPP 3 _IOC_NONE 0U pthread_mutex_lock PTHREAD_CANCEL_ENABLE PTHREAD_CANCEL_ENABLE SIOCDELRT 0x890C iscntrl_l(c,l) __iscntrl_l ((c), (l)) __aligned_le64 __le64 __attribute__((aligned(8))) TIOCPKT_STOP 4 __API_IO__  SIOCGIFBRDADDR 0x8919 TIOCSERGWILD 0x5454 SHRT_MIN (-SHRT_MAX - 1) _GCC_PTRDIFF_T  STATMOUNT_PROPAGATE_FROM 0x00000004U SIOCDIFADDR 0x8936 BC_BASE_MAX _POSIX2_BC_BASE_MAX SIOCSIFENCAP 0x8926 SIOCDRARP 0x8960 HOST_NAME_MAX 64 PTHREAD_EXPLICIT_SCHED PTHREAD_EXPLICIT_SCHED _SYS_IOCTL_H 1 UINT_LEAST8_MAX (255) procfs__mountpoint SIOCBONDRELEASE 0x8991 MNT_ID_REQ_SIZE_VER1 32 FS(lower_name,fs_name,upper_name) static struct fs fs__ ##lower_name = { .name = #fs_name, .mounts = lower_name ##__known_mountpoints, .magic = upper_name ##_MAGIC, .mount_mutex = PTHREAD_MUTEX_INITIALIZER, }; static void lower_name ##_init_once(void) { struct fs *fs = &fs__ ##lower_name; fs__init_once(fs); } const char *lower_name ##__mountpoint(void) { static pthread_once_t init_once = PTHREAD_ONCE_INIT; struct fs *fs = &fs__ ##lower_name; pthread_once(&init_once, lower_name ##_init_once); return fs__mountpoint(fs); } const char *lower_name ##__mount(void) { const char *mountpoint = lower_name ##__mountpoint(); struct fs *fs = &fs__ ##lower_name; if (mountpoint) return mountpoint; return fs__mount(fs); } bool lower_name ##__configured(void) { return lower_name ##__mountpoint() != NULL; } __kind SIOCBRADDIF 0x89a2 PTHREAD_SCOPE_PROCESS PTHREAD_SCOPE_PROCESS TCSETSW2 _IOW('T', 0x2C, struct termios2) MS_NOEXEC 8 f_flags __ASM_GENERIC_IOCTLS_H  SIOCGSTAMP SIOCGSTAMP_OLD MOUNT_ATTR_NOATIME 0x00000010 CEOL _POSIX_VDISABLE TIOCSWINSZ 0x5414 AIO_PRIO_DELTA_MAX 20 INT_LEAST32_MAX (2147483647) STATMOUNT_MNT_OPTS 0x00000080U TIOCGPKT _IOR('T', 0x38, int) _POSIX_CHILD_MAX 25 TTYDEF_IFLAG (BRKINT | ISTRIP | ICRNL | IMAXBEL | IXON | IXANY) _toupper(c) ((int) (*__ctype_toupper_loc ())[(int) (c)]) SIOCGSTAMP_NEW _IOR(SOCK_IOC_TYPE, 0x06, long long[2]) SIOCGIFHWADDR 0x8927 __cold  TIOCPKT_DATA 0 fs__procfs SIOCDELMULTI 0x8932 S_TYPEISSEM(buf) __S_TYPEISSEM(buf) UINT_FAST64_MAX (__UINT64_C(18446744073709551615)) STR(x) _STR(x) CDISCARD CTRL('o') INT_FAST8_MAX (127) INT64_MAX (__INT64_C(9223372036854775807)) INTPTR_MIN (-9223372036854775807L-1) HUGETLBFS_MAGIC 0x958458f6 sysfs__write_int MS_I_VERSION (1<<23) TIOCGETD 0x5424 isxdigit_l(c,l) __isxdigit_l ((c), (l)) CLOCKS_PER_SEC ((__clock_t) 1000000) TIOCOUTQ 0x5411 _IOC_NRBITS 8 __ASSERT_VOID_CAST (void) TCSBRK 0x5409 bpf_fs__known_mountpoints S_BLKSIZE 512 f_files _PTHREAD_H 1 fs__read_mounts isalpha_l(c,l) __isalpha_l ((c), (l)) MS_BIND MS_BIND pr_debug(fmt,...) __pr(__pr_debug, fmt, ##__VA_ARGS__) MS_POSIXACL (1<<16) CHARCLASS_NAME_MAX 2048 CEOF CTRL('d') procfs__read_str MS_REC 16384 __UINT64_C EXPR_NEST_MAX _POSIX2_EXPR_NEST_MAX STATMOUNT_MNT_POINT 0x00000010U BLKGETSIZE INT_FAST32_MAX (9223372036854775807L) TCSETSF2 _IOW('T', 0x2D, struct termios2) tracefs__known_mountpoints _IOR(type,nr,argtype) _IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(argtype))) ULONG_MAX (LONG_MAX * 2UL + 1UL) SIOCGMIIPHY 0x8947 __size MOVE_MOUNT_BENEATH 0x00000200 isspace_l(c,l) __isspace_l ((c), (l)) BC_DIM_MAX _POSIX2_BC_DIM_MAX f_bfree fs__valid_mount DEFFILEMODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH|S_IWOTH) MS_DIRSYNC 128 PTHREAD_MUTEX_ERRORCHECK_NP TCGETX 0x5432 __bool_true_false_are_defined 1 MS_NOUSER (1<<31) line_out _POSIX_SEM_NSEMS_MAX 256 _IOC_READ 2U PTHREAD_MUTEX_RECURSIVE CLOCK_REALTIME_ALARM 8 assert(expr) ((void) sizeof ((expr) ? 1 : 0), __extension__ ({ if (expr) ; else __assert_fail (#expr, __FILE__, __LINE__, __ASSERT_FUNCTION); })) __count SIOCBONDENSLAVE 0x8990 TCSETXW 0x5435 SIOCSHWTSTAMP 0x89b0 MS_MOVE MS_MOVE _LIBC_LIMITS_H_ 1 isprint_l(c,l) __isprint_l ((c), (l)) MS_NOSUID 2 TIOCSERGETMULTI 0x545A _POSIX_CLOCKRES_MIN 20000000 sysfs__read_xll SOCK_IOC_TYPE 0x89 MS_NOSUID MS_NOSUID S_ISFIFO(mode) __S_ISTYPE((mode), __S_IFIFO) NR_OPEN 1024 __kernel_old_dev_t __kernel_old_dev_t STATMOUNT_OPT_ARRAY 0x00000400U _POSIX_PIPE_BUF 512 _UAPI__ASM_GENERIC_BITS_PER_LONG  LSMT_ROOT 0xffffffffffffffff __unused OPEN_TREE_CLOEXEC O_CLOEXEC MOUNT_ATTR_IDMAP 0x00100000 TIOCM_ST 0x008 TIOCGWINSZ 0x5413 hugetlbfs_init_once STATMOUNT_OPT_SEC_ARRAY 0x00000800U _IOC_WRITE 1U __need_ptrdiff_t SIOCGIFNETMASK 0x891b MOUNT_ATTR_NODEV 0x00000004 TIOCSBRK 0x5427 INT_MAX __INT_MAX__ TIOCLINUX 0x541C IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT) PROC_SUPER_MAGIC 0x9fa0 PTHREAD_ONCE_INIT 0 SIOCSIFLINK 0x8911 _GCC_WRAP_STDINT_H  STATMOUNT_BY_FD 0x00000001U __isascii(c) (((c) & ~0x7f) == 0) debugfs__known_mountpoints MOVE_MOUNT_SET_GROUP 0x00000100 BLKSSZGET BLKROSET _IO(0x12, 93) __undef_LINK_MAX  _ASM_GENERIC_TYPES_H  _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS) PTHREAD_THREADS_MAX SIOCGIFMEM 0x891f __isgraph_l(c,l) __isctype_l((c), _ISgraph, (l)) SIOCADDRT 0x890B __aligned_be64 __be64 __attribute__((aligned(8))) __undef_LINK_MAX __pthread_internal_list INT_LEAST8_MIN (-128) BLKBSZSET __prev TIOCPKT_FLUSHREAD 1 MS_NOSYMFOLLOW 256 CKILL CTRL('u') _ASM_X86_POSIX_TYPES_64_H  pthread_cleanup_push(routine,arg) do { __pthread_unwind_buf_t __cancel_buf; void (*__cancel_routine) (void *) = (routine); void *__cancel_arg = (arg); int __not_first_call = __sigsetjmp_cancel (__cancel_buf.__cancel_jmp_buf, 0); if (__glibc_unlikely (__not_first_call)) { __cancel_routine (__cancel_arg); __pthread_unwind_next (&__cancel_buf); } __pthread_register_cancel (&__cancel_buf); do { TCSETS2 _IOW('T', 0x2B, struct termios2) TIOCSERSWILD 0x5455 mount_mutex hugetlbfs__mount N_6PACK 7 __isalpha_l(c,l) __isctype_l((c), _ISalpha, (l)) ULLONG_MAX (LLONG_MAX * 2ULL + 1) CLOCK_MONOTONIC_COARSE 6 _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS) SCHED_OTHER 0 _POSIX2_COLL_WEIGHTS_MAX 2 fopen64 TIOCPKT_DOSTOP 32 SIOCGIFNAME 0x8910 __aligned_u64 __u64 __attribute__((aligned(8))) TIOCMSET 0x5418 sizep tracefs__mount _BITS_WCHAR_H 1 bpf_fs__configured CTIME 0 isgraph_l(c,l) __isgraph_l ((c), (l)) __ssize_t islower_l(c,l) __islower_l ((c), (l)) IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT) LONG_MIN (-LONG_MAX - 1L) CHAR_MIN SCHAR_MIN TIOCGSERIAL 0x541E __kernel_old_uid_t __kernel_old_uid_t TIOCMBIS 0x5416 _STATFS_F_FRSIZE  f_spare __undef_ARG_MAX MS_KERNMOUNT (1<<22) MQ_PRIO_MAX 32768 DEBUGFS_DEFAULT_PATH "/sys/kernel/debug" _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1) TCGETA 0x5405 BLKGETSIZE64 debugfs__configured LISTMOUNT_REVERSE (1 << 0) MS_DIRSYNC MS_DIRSYNC OPEN_TREE_NAMESPACE (1 << 1) MS_MOVE 8192 S_IEXEC S_IXUSR SIOCGIFPFLAGS 0x8935 N_MOUSE 2 line_len_out _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0) LLONG_MIN _POSIX2_RE_DUP_MAX 255 INTMAX_MIN (-__INT64_C(9223372036854775807)-1) _POSIX2_BC_SCALE_MAX 99 INT32_MAX (2147483647) SIOCETHTOOL 0x8946 __undef_OPEN_MAX  S_ISDIR(mode) __S_ISTYPE((mode), __S_IFDIR) __INT64_C CLOCK_BOOTTIME_ALARM 9 BLKBSZGET _IOR(0x12,112,size_t) SIOCSARP 0x8955 MS_POSIXACL MS_POSIXACL MS_I_VERSION MS_I_VERSION TIOCSERGSTRUCT 0x5458 _POSIX_AIO_MAX 1 buf_pos mem_toupper magic islower(c) __isctype((c), _ISlower) f_bsize NGROUPS_MAX 65536 isdigit_l(c,l) __isdigit_l ((c), (l)) _POSIX_OPEN_MAX 20 LONG_MAX __LONG_MAX__ PTRDIFF_MIN (-9223372036854775807L-1) __CPU_ALLOC_SIZE(count) ((((count) + __NCPUBITS - 1) / __NCPUBITS) * sizeof (__cpu_mask)) MOVE_MOUNT__MASK 0x00000377 PTHREAD_PROCESS_PRIVATE PTHREAD_PROCESS_PRIVATE __pr(func,fmt,...) do { if ((func)) (func)("libapi: " fmt, ##__VA_ARGS__); } while (0) S_ISBLK(mode) __S_ISTYPE((mode), __S_IFBLK) TIOCGRS485 0x542E _POSIX_AIO_LISTIO_MAX 2 PTRDIFF_MAX (9223372036854775807L) INT8_MAX (127) TTYDEF_LFLAG (ECHO | ICANON | ISIG | IEXTEN | ECHOE|ECHOKE|ECHOCTL) __assert_fail __ASM_GENERIC_POSIX_TYPES_H  offsetof(TYPE,MEMBER) __builtin_offsetof (TYPE, MEMBER) isspace(c) __isctype((c), _ISspace) mount_overload INT_LEAST32_MIN (-2147483647-1) TRACEFS_MAGIC 0x74726163 TIOCGLCKTRMIOS 0x5456 TIOCEXCL 0x540C N_MASC 8 INT64_MIN (-__INT64_C(9223372036854775807)-1) S_TYPEISMQ(buf) __S_TYPEISMQ(buf) _POSIX_MAX_CANON 255 CLOCK_MONOTONIC 1 err_out pthread_once_t UINT_LEAST32_MAX (4294967295U) CSTATUS _POSIX_VDISABLE TIOCSRS485 0x542F N_HDLC 13 f_fsid _BITS_CPU_SET_H 1 __NCPUBITS (8 * sizeof (__cpu_mask)) _IOC_NRMASK ((1 << _IOC_NRBITS)-1) TIOCSTI 0x5412 sysfs_init_once override_path BC_SCALE_MAX _POSIX2_BC_SCALE_MAX CERASE 0177 TIOCSSOFTCAR 0x541A MS_NOATIME 1024 _POSIX_TZNAME_MAX 6 IOC_OUT (_IOC_READ << _IOC_DIRSHIFT) PTHREAD_SCOPE_SYSTEM PTHREAD_SCOPE_SYSTEM BITS_PER_LONG (__CHAR_BIT__ * __SIZEOF_LONG__) __SANE_USERSPACE_TYPES__  __force  MS_RELATIME (1<<21) _LINUX_SOCKIOS_H  filename__read_ull_base MS_RELATIME MS_RELATIME filename CSTART CTRL('q') INTMAX_MAX (__INT64_C(9223372036854775807)) TIOCGPTPEER _IO('T', 0x41) PTHREAD_CANCEL_DEFERRED PTHREAD_CANCEL_DEFERRED procfs__known_mountpoints __cleanup_fct_attribute  MOUNT_ATTR__ATIME 0x00000070 TCSBRKP 0x5425 BLKROGET _IO(0x12, 94) TIOCSER_TEMT 0x01 pfds TCSETAW 0x5407 SIOCGIFADDR 0x8915 __isleap(year) ((year) % 4 == 0 && ((year) % 100 != 0 || (year) % 400 == 0)) TCSETSF 0x5404 CLOCK_MONOTONIC_RAW 4 SIOCSIFDSTADDR 0x8918 _ASM_GENERIC_INT_LL64_H  MOVE_MOUNT_F_SYMLINKS 0x00000001 CSTOP CTRL('s') IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT) pthread_cleanup_pop(execute) do { } while (0); } while (0); __pthread_unregister_cancel (&__cancel_buf); if (execute) __cancel_routine (__cancel_arg); } while (0) isdigit(c) __isctype((c), _ISdigit) _ANSI_STDDEF_H  statfs64 _IOC(dir,type,nr,size) (((dir) << _IOC_DIRSHIFT) | ((type) << _IOC_TYPESHIFT) | ((nr) << _IOC_NRSHIFT) | ((size) << _IOC_SIZESHIFT)) RTSIG_MAX 32 MOUNT_ATTR_NOSYMFOLLOW 0x00200000 PTHREAD_PROCESS_SHARED PTHREAD_PROCESS_SHARED TIOCM_RNG 0x080 _POSIX_MQ_OPEN_MAX 8 TIOCPKT_IOCTL 64 MS_SYNCHRONOUS 16 BLKSECTSET _IO(0x12,102) __undef_NR_OPEN  INT_FAST64_MIN (-__INT64_C(9223372036854775807)-1) TCGETS2 _IOR('T', 0x2A, struct termios2) TIOCNOTTY 0x5422 TIOCSETD 0x5423 isupper(c) __isctype((c), _ISupper) SIOCADDDLCI 0x8980 isascii(c) __isascii (c) SIOCGMIIREG 0x8948 isupper_l(c,l) __isupper_l ((c), (l)) TIOCSISO7816 _IOWR('T', 0x43, struct serial_iso7816) MS_NOSEC (1<<28) _POSIX_SSIZE_MAX 32767 TCSETS 0x5402 __CPU_CLR_S(cpu,setsize,cpusetp) (__extension__ ({ size_t __cpu = (cpu); __cpu / 8 < (setsize) ? (((__cpu_mask *) ((cpusetp)->__bits))[__CPUELT (__cpu)] &= ~__CPUMASK (__cpu)) : 0; })) UINTPTR_MAX (18446744073709551615UL) __API_FS__  PTHREAD_CREATE_JOINABLE PTHREAD_CREATE_JOINABLE __exctype_l(name) extern int name (int, locale_t) __THROW BLOCK_SIZE (1<<BLOCK_SIZE_BITS) _POSIX2_CHARCLASS_NAME_MAX 14 UINT32_MAX (4294967295U) N_X25 6 tracefs__mountpoint SIOCRTMSG 0x890D CFLUSH CDISCARD N_SMSBLOCK 12 INT8_MIN (-128) UINT8_MAX (255) BLKFRAGET _IO(0x12,101) SCHED_FIFO 1 _STATFS_F_FLAGS  __CPU_OP_S(setsize,destset,srcset1,srcset2,op) (__extension__ ({ cpu_set_t *__dest = (destset); const __cpu_mask *__arr1 = (srcset1)->__bits; const __cpu_mask *__arr2 = (srcset2)->__bits; size_t __imax = (setsize) / sizeof (__cpu_mask); size_t __i; for (__i = 0; __i < __imax; ++__i) ((__cpu_mask *) __dest->__bits)[__i] = __arr1[__i] op __arr2[__i]; __dest; })) __bitwise  SIOCDELDLCI 0x8981 __CPU_EQUAL_S(setsize,cpusetp1,cpusetp2) (__builtin_memcmp (cpusetp1, cpusetp2, setsize) == 0) _IOC_TYPEBITS 8 TCSETXF 0x5434 sysfs__read_bool _POSIX_RTSIG_MAX 8 __jmp_buf_tag_defined 1 TIOCINQ FIONREAD SIOCGIFINDEX 0x8933 BLKRAGET MS_VERBOSE 32768 CDSUSP CTRL('y') MS_NOUSER MS_NOUSER S_TYPEISSHM(buf) __S_TYPEISSHM(buf) CBRK CEOL TTY_NAME_MAX 32 _GCC_LIMITS_H_  FIONCLEX 0x5450 TCSETA 0x5406 PTHREAD_RWLOCK_INITIALIZER { { __PTHREAD_RWLOCK_INITIALIZER (PTHREAD_RWLOCK_DEFAULT_NP) } } iscntrl(c) __isctype((c), _IScntrl) BLKFRASET _IO(0x12,100) FIOCLEX 0x5451 TIOCMIWAIT 0x545C sysfs__read_ull_base f_blocks TIOCCONS 0x541D BLOCK_SIZE_BITS 10 TIOCM_RI TIOCM_RNG __undef_ARG_MAX  CLOCK_THREAD_CPUTIME_ID 3 UINT_LEAST16_MAX (65535) SIOCATMARK 0x8905 MS_REMOUNT 32 TCGETS 0x5401 CTRL(x) (x&037) STATMOUNT_MNT_GIDMAP 0x00004000U MOVE_MOUNT_T_EMPTY_PATH 0x00000040 S_ISLNK(mode) __S_ISTYPE((mode), __S_IFLNK) SIOCSMIIREG 0x8949 __undef_NR_OPEN FIOASYNC 0x5452 LOGIN_NAME_MAX 256 __errno_location debugfs__mountpoint isblank(c) __isctype((c), _ISblank) INT_FAST16_MAX (9223372036854775807L) io__init io__fill_buffer TIOCSPTLCK _IOW('T', 0x31, int) _LINUX_MOUNT_H  SIOCGIFMETRIC 0x891d __PTRDIFF_T  __spins __isalnum_l(c,l) __isctype_l((c), _ISalnum, (l)) isalnum(c) __isctype((c), _ISalnum) __nusers hugetlbfs__mountpoint __WCHAR_MIN __WCHAR_MIN__ _CTYPE_H 1 TIOCGDEV _IOR('T', 0x32, unsigned int) true 1 f_bavail filename__read_int PTHREAD_CANCELED ((void *) -1) SIOCGIFDSTADDR 0x8917 sysfs__configured debugfs_init_once fs__env_override MOUNT_ATTR_RELATIME 0x00000000 N_TTY 0 SIOCSIFMTU 0x8922 CLOCK_TAI 11 io__get_char TTYDEF_SPEED (B9600) TRACEFS_DEFAULT_PATH "/sys/kernel/tracing" __CPU_COUNT_S(setsize,cpusetp) __sched_cpucount (setsize, cpusetp) WCHAR_MAX __WCHAR_MAX N_IRDA 11 fs__debugfs SIOCGIFSLAVE 0x8929 BLKBSZGET MS_MANDLOCK 64 INTPTR_MAX (9223372036854775807L) _T_PTRDIFF  BLKSSZGET _IO(0x12,104) _BITS_SETJMP_H 1 STATMOUNT_FS_SUBTYPE 0x00000100U __API_DEBUG_INTERNAL_H__  _IOWR_BAD(type,nr,argtype) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(argtype)) BLKRASET __exctype(name) extern int name (int) __THROW MOUNT_ATTR_STRICTATIME 0x00000020 SIOCGIFVLAN 0x8982 SIOCGRARP 0x8961 FSPICK_CLOEXEC 0x00000001 bpf_fs__mount SIOCBONDSLAVEINFOQUERY 0x8993 __itimerspec_defined 1 __tobody(c,f,a,args) (__extension__ ({ int __res; if (sizeof (c) > 1) { if (__builtin_constant_p (c)) { int __c = (c); __res = __c < -128 || __c > 255 ? __c : (a)[__c]; } else __res = f args; } else __res = (a)[(int) (c)]; __res; })) CINTR CTRL('c') BLKRRPART _IO(0x12, 95) __islower_l(c,l) __isctype_l((c), _ISlower, (l)) PTHREAD_INHERIT_SCHED PTHREAD_INHERIT_SCHED SIZE_MAX (18446744073709551615UL) PTHREAD_MUTEX_RECURSIVE_NP FIONREAD 0x541B TIOCMGET 0x5415 SIG_ATOMIC_MIN (-2147483647-1) SIOCPROTOPRIVATE 0x89E0 _IOW(type,nr,argtype) _IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(argtype))) SIOCGSKNS 0x894C filename__read_str SSIZE_MAX LONG_MAX f_namelen io__getdelim _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK) isgraph(c) __isctype((c), _ISgraph) TIOCVHANGUP 0x5437 _IOR_BAD(type,nr,argtype) _IOC(_IOC_READ,(type),(nr),sizeof(argtype)) __isoc99_fscanf isascii_l(c,l) __isascii_l ((c), (l)) _POSIX_SIGQUEUE_MAX 32 _IOWR(type,nr,argtype) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(argtype))) TIOCGICOUNT 0x545D UMOUNT_NOFOLLOW UMOUNT_NOFOLLOW TIOCPKT_FLUSHWRITE 2 _POSIX2_BC_DIM_MAX 2048 MS_NODIRATIME MS_NODIRATIME statfs __fsblkcnt64_t TIOCM_LE 0x001 _ASSERT_H 1 UINT_LEAST64_MAX (__UINT64_C(18446744073709551615)) _POSIX_HOST_NAME_MAX 255 _LIMITS_H___  _tolower(c) ((int) (*__ctype_tolower_loc ())[(int) (c)]) SIOCGIFTXQLEN 0x8942 MNT_EXPIRE MNT_EXPIRE pr_info(fmt,...) __pr(__pr_info, fmt, ##__VA_ARGS__) fs__init_once S_IWRITE S_IWUSR line_len TIOCSERGETLSR 0x5459 SIOCSIFHWBROADCAST 0x8937 _POSIX_MAX_INPUT 255 _BITS_SCHED_H 1 _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK) __toascii_l(c,l) ((l), __toascii (c)) SIOCBRDELBR 0x89a1 TIOCNXCL 0x540D __ASM_GENERIC_SOCKIOS_H  UINT16_MAX (65535) INT_LEAST16_MAX (32767) TIOCGISO7816 _IOR('T', 0x42, struct serial_iso7816) _STDDEF_H_  __must_check  CMIN 1 _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS) _POSIX_RE_DUP_MAX 255 SIOCADDMULTI 0x8931 MS_PRIVATE (1<<18) SIOCSIFHWADDR 0x8924 _BITS_STDINT_LEAST_H 1 MS_SLAVE MS_SLAVE procfs__configured sysfs__mount PTHREAD_COND_INITIALIZER { { {0}, {0}, {0, 0}, 0, 0, {0, 0}, 0, 0 } } __isascii_l(c,l) ((l), __isascii (c)) small_const_nbits(nbits) (__builtin_constant_p(nbits) && (nbits) <= BITS_PER_LONG && (nbits) > 0) PATH_MAX 4096 MS_BIND 4096 filename__read_ull _BSD_PTRDIFF_T_  debugfs__mount TIOCSIG _IOW('T', 0x36, int) __CPUELT(cpu) ((cpu) / __NCPUBITS) BLKFRAGET MS_SHARED MS_SHARED CHAR_MAX SCHAR_MAX SIOCOUTQNSD 0x894B TIOCGPGRP 0x540F FSMOUNT_CLOEXEC 0x00000001 SIOCDEVPRIVATE 0x89F0 PTHREAD_CANCEL_DISABLE PTHREAD_CANCEL_DISABLE __list SYSFS_MAGIC 0x62656572 PTHREAD_STACK_MIN 16384 _STDINT_H 1 ULLONG_MAX (LLONG_MAX * 2ULL + 1ULL) _STR(x) #x S_ISREG(mode) __S_ISTYPE((mode), __S_IFREG) _ASSERT_H_DECLS  isalpha(c) __isctype((c), _ISalpha) MS_PRIVATE MS_PRIVATE TCSETAF 0x5408 PTHREAD_CREATE_DETACHED PTHREAD_CREATE_DETACHED toascii(c) __toascii (c) CEOT CEOF __ASSERT_VARIADIC 0 TIOCSPGRP 0x5410 SIOCSIFFLAGS 0x8914 INT_FAST32_MIN (-9223372036854775807L-1) PTHREAD_MUTEX_ERRORCHECK SIOCGHWTSTAMP 0x89b1 TIOCGPTLCK _IOR('T', 0x39, int) _POSIX_DELAYTIMER_MAX 32 BLKRAGET _IO(0x12, 99) getenv fs__sysfs SIOCSIFMETRIC 0x891e _BITS_TIME_H 1 pthread_mutex_unlock TIOCGPTN _IOR('T', 0x30, unsigned int) STATMOUNT_FS_TYPE 0x00000020U SIOCGIFCOUNT 0x8938 SIOCBRDELIF 0x89a3 __CPU_ALLOC(count) __sched_cpualloc (count) __ASSERT_FUNCTION __extension__ __PRETTY_FUNCTION__ MS_NOREMOTELOCK (1<<27) UINTMAX_MAX (__UINT64_C(18446744073709551615)) bool _Bool ___int_ptrdiff_t_h  STATMOUNT_SUPPORTED_MASK 0x00001000U FS(name) const char *name ##__mountpoint(void); const char *name ##__mount(void); bool name ##__configured(void); __isctype_l(c,type,locale) ((locale)->__ctype_b[(int) (c)] & (unsigned short int) type) SIOCSIFADDR 0x8916 SIOCGIFCONF 0x8912 MOUNT_ATTR_NODIRATIME 0x00000080 BLKFRASET MS_NODEV 4 __CPU_ISSET_S(cpu,setsize,cpusetp) (__extension__ ({ size_t __cpu = (cpu); __cpu / 8 < (setsize) ? ((((const __cpu_mask *) ((cpusetp)->__bits))[__CPUELT (__cpu)] & __CPUMASK (__cpu))) != 0 : 0; })) FIOQSIZE 0x5460 hugetlbfs__known_mountpoints SIOCOUTQ TIOCOUTQ bpf_fs__mountpoint WINT_MIN (0u) TCFLSH 0x540B SIOCINQ FIONREAD isxdigit(c) __isctype((c), _ISxdigit) _ASM_GENERIC_IOCTL_H  SIOGIFINDEX SIOCGIFINDEX TTYDEF_CFLAG (CREAD | CS7 | PARENB | HUPCL) __iscntrl_l(c,l) __isctype_l((c), _IScntrl, (l)) MS_UNBINDABLE MS_UNBINDABLE MS_MGC_VAL MS_STRICTATIME MS_STRICTATIME MS_RMT_MASK (MS_RDONLY|MS_SYNCHRONOUS|MS_MANDLOCK|MS_I_VERSION |MS_LAZYTIME) _POSIX_SYMLOOP_MAX 8 SIG_ATOMIC_MAX (2147483647) ispunct_l(c,l) __ispunct_l ((c), (l)) LLONG_MAX __LONG_LONG_MAX__ _SYS_STAT_H 1 MOVE_MOUNT_T_AUTOMOUNTS 0x00000020 SCHAR_MIN (-SCHAR_MAX - 1) BLKFLSBUF toascii_l(c,l) __toascii_l ((c), (l)) LINE_MAX _POSIX2_LINE_MAX MS_ACTIVE (1<<30) MOUNT_ATTR_SIZE_VER0 32 STATMOUNT_SB_SOURCE 0x00000200U WINT_MAX (4294967295u) PTHREAD_BARRIER_SERIAL_THREAD -1 buf_len MS_SILENT MS_SILENT INT16_MIN (-32767-1) fs__tracefs SIOCGSTAMP_OLD 0x8906 sysfs__read_int TIOCPKT 0x5420 MS_BORN (1<<29) __sched_priority sched_priority PTHREAD_MUTEX_ADAPTIVE_NP MS_SUBMOUNT (1<<26) _POSIX_SYMLINK_MAX 255 TCSETSW 0x5403 _POSIX_TTY_NAME_MAX 9 S_ISSOCK(mode) __S_ISTYPE((mode), __S_IFSOCK) __val fs__bpf_fs SIOCSRARP 0x8962 TIOCM_SR 0x010 MOVE_MOUNT_F_EMPTY_PATH 0x00000004 BLKGETSIZE _IO(0x12, 96) BLKROGET N_AX25 5 USHRT_MAX (SHRT_MAX * 2 + 1) MNT_DETACH MNT_DETACH S_IREAD S_IRUSR MS_NODEV MS_NODEV strcmp _POSIX_MQ_PRIO_MAX 32 _POSIX_SEM_VALUE_MAX 32767 INT_LEAST64_MIN (-__INT64_C(9223372036854775807)-1) MS_MGC_MSK 0xffff0000 MS_MGC_VAL 0xC0ED0000 __fsword_t IOCSIZE_SHIFT (_IOC_SIZESHIFT) INT_LEAST64_MAX (__INT64_C(9223372036854775807)) __ASM_X86_BITSPERLONG_H  DELAYTIMER_MAX 2147483647 _TOOLS_LINUX_TYPES_H_  upper_name SIOCGIFFLAGS 0x8913 SIOCGIFMAP 0x8970 TIOCM_CTS 0x020 STATMOUNT_SB_BASIC 0x00000001U _STATFS_F_NAMELEN  __DEFINED_ptrdiff_t  BC_STRING_MAX _POSIX2_BC_STRING_MAX SIOCGSTAMPNS_OLD 0x8907 sysctl__read_int BLKSECTGET _IO(0x12,103) TCXONC 0x540A SIOCSIFTXQLEN 0x8943 SIOCGARP 0x8954 sysfs__known_mountpoints tracing_path_mount _DYNAMIC_STACK_SIZE_SOURCE 1 CLOSE_RANGE_UNSHARE (1U << 1) tracing _ISOC95_SOURCE RENAME_WHITEOUT (1 << 2) __GLIBC_USE_IEC_60559_BFP_EXT_C23 1 __once_flag_defined 1 IFTODT(mode) (((mode) & 0170000) >> 12) RENAME_NOREPLACE (1 << 0) DT_UNKNOWN DT_UNKNOWN _DIRENT_HAVE_D_NAMLEN UINTMAX_WIDTH 64 mntpt _LINUX_CLOSE_RANGE_H  tracing_path_debugfs_mount __STDC_VERSION_STDIO_H__ 202311L _POSIX_FD_SETSIZE _POSIX_OPEN_MAX _ISOC99_SOURCE strscpy strcpy AT_RENAME_NOREPLACE 0x0001 strrchr(S,C) __glibc_const_generic (S, const char *, strrchr (S, C)) _PRINTF_NAN_LEN_MAX 4 __GLIBC_USE_LIB_EXT2 1 _DIRENT_HAVE_D_RECLEN  __GLIBC_USE_C23_STRTOL 1 AT_RENAME_WHITEOUT 0x0004 DT_CHR DT_CHR tracing_path_tracefs_mount _ISOC2Y_SOURCE 1 memchr(S,C,N) __glibc_const_generic (S, const void *, memchr (S, C, N)) strpbrk(S,ACCEPT) __glibc_const_generic (S, const char *, strpbrk (S, ACCEPT)) MAXNAMLEN NAME_MAX __GLIBC_USE_ISOC23 1 strncmp DT_WHT DT_WHT tracing_path__strerror_open_tp _GNU_SOURCE  DT_SOCK DT_SOCK UINT_LEAST16_WIDTH 16 str_error_r put_tracing_file SEEK_DATA 3 d_name _DIRENT_MATCHES_DIRENT64 1 __USE_DYNAMIC_STACK_SIZE 1 __FDS_BITS(set) ((set)->fds_bits) _ISOC23_SOURCE 1 d_reclen namelist get_events_file __USE_XOPEN2K8XSI 1 __GLIBC_USE_IEC_60559_FUNCS_EXT_C23 1 _ISOC99_SOURCE 1 PTHREAD_STACK_MIN __sysconf (__SC_THREAD_STACK_MIN_VALUE) __USE_XOPEN2KXSI 1 __STDC_VERSION_STDINT_H__ 202311L strchr(S,C) __glibc_const_generic (S, const char *, strchr (S, C)) UINT_FAST16_WIDTH __WORDSIZE DT_BLK DT_BLK __USE_GNU 1 d_off strstr(HAYSTACK,NEEDLE) __glibc_const_generic (HAYSTACK, const char *, strstr (HAYSTACK, NEEDLE)) __GLIBC_USE_IEC_60559_EXT 1 _POSIX_HIWAT _POSIX_PIPE_BUF _DIRENT_H 1 UINT32_WIDTH 32 __tracing_path_set DTTOIF(dirtype) ((dirtype) << 12) _XOPEN_SOURCE_EXTENDED 1 WINT_WIDTH 32 __STDC_VERSION_STDLIB_H__ 202311L DT_DIR DT_DIR alphasort64 _ISOC11_SOURCE TEMP_FAILURE_RETRY(expression) (__extension__ ({ long int __result; do __result = (long int) (expression); while (__result == -1L && errno == EINTR); __result; })) _XOPEN_SOURCE_EXTENDED UINT8_WIDTH 8 __GLIBC_USE_IEC_60559_TYPES_EXT 1 __API_FS_TRACING_PATH_H  tracing_events__scandir_alphasort d_type __error_t_defined 1 _ISOC23_SOURCE sbuf __dirstream SEEK_HOLE 4 UINT_LEAST8_WIDTH 8 scandir _ISOC2Y_SOURCE UINT64_WIDTH 64 bsearch(KEY,BASE,NMEMB,SIZE,COMPAR) __glibc_const_generic (BASE, const void *, bsearch (KEY, BASE, NMEMB, SIZE, COMPAR)) put_events_file _TOOLS_LINUX_STRING_H_  UINT_FAST8_WIDTH 8 _XOPEN_SOURCE 800 PTRDIFF_WIDTH __WORDSIZE __USE_XOPEN_EXTENDED 1 UINT_LEAST32_WIDTH 32 __GLIBC_USE_DEPRECATED_GETS 0 UINT_FAST64_WIDTH 64 _DYNAMIC_STACK_SIZE_SOURCE _D_EXACT_NAMLEN(d) (strlen ((d)->d_name)) __SC_THREAD_STACK_MIN_VALUE 75 __STDC_VERSION_STRING_H__ 202311L __USE_LARGEFILE 1 __GLIBC_USE_IEC_60559_BFP_EXT 1 _LARGEFILE64_SOURCE __USE_ISOC11 1 DT_REG DT_REG _LARGEFILE_SOURCE scandir64 dirent _XOPEN_SOURCE _DIRENT_HAVE_D_TYPE  get_tracing_file DT_LNK DT_LNK RENAME_EXCHANGE (1 << 1) tracing_path L_cuserid 9 _POSIX_QLIMIT 1 UINT16_WIDTH 16 _LARGEFILE_SOURCE 1 UINT_LEAST64_WIDTH 64 __ino64_t strdupa(s) (__extension__ ({ const char *__old = (s); size_t __len = strlen (__old) + 1; char *__new = (char *) __builtin_alloca (__len); (char *) memcpy (__new, __old, __len); })) CLOSE_RANGE_CLOEXEC (1U << 2) UINTPTR_WIDTH __WORDSIZE _DIRENT_HAVE_D_OFF  tracing_events__opendir SIG_ATOMIC_WIDTH 32 _ISOC11_SOURCE 1 strndupa(s,n) (__extension__ ({ const char *__old = (s); size_t __len = strnlen (__old, (n)); char *__new = (char *) __builtin_alloca (__len + 1); __new[__len] = '\0'; (char *) memcpy (__new, __old, __len); })) __USE_XOPEN2K24XSI 1 zput_events_file(ptr) ({ free(*ptr); *ptr = NULL; }) DT_FIFO DT_FIFO _POSIX_UIO_MAXIOV 16 AT_RENAME_EXCHANGE 0x0002 WCHAR_WIDTH 32 __GLIBC_USE_ISOC2Y 1 __GLIBC_USE_IEC_60559_FUNCS_EXT 1 d_fileno d_ino SIZE_WIDTH __WORDSIZE __USE_UNIX98 1 __USE_XOPEN 1 UINT_FAST32_WIDTH __WORDSIZE _ISOC95_SOURCE 1 _D_ALLOC_NAMLEN(d) (((char *) (d) + (d)->d_reclen) - &(d)->d_name[0]) ONCE_FLAG_INIT __ONCE_FLAG_INIT cgroupfs_find_mountpoint __stringify_1(x...) #x __stringify(x...) __stringify_1(x) cached __LINUX_STRINGIFY_H  strncpy subsys cgroupfs_cache_entry strchr getline strstr maxlen __API_CPU__  cpu__get_max_freq __base_pr __pr_debug __pr_warn __gnuc_va_list __pr_info fp_offset libapi_print_fn_t __va_list_tag _VA_LIST_  _STDARG_H  _VA_LIST_T_H  __builtin_va_list gp_offset overflow_arg_area reg_save_area _ANSI_STDARG_H_  libapi_set_print __va_copy(d,s) __builtin_va_copy(d,s) va_arg(v,l) __builtin_va_arg(v,l) va_end(v) __builtin_va_end(v) __va_list__  va_start(v,l) __builtin_va_start(v,l) vfprintf errnum __xpg_strerror_r _GNU_SOURCE buflen LIBPERF_DEBUG libperf_print_fn_t __libperf_pr __fmt LIBPERF_ERR LIBPERF_DEBUG2 LIBPERF_DEBUG3 __stream libperf_init long double libperf_print LIBPERF_INFO libperf_print_level __stack_chk_fail __vfprintf_chk __ap GNU C11 15.2.0 -U _FORTIFY_SOURCE -D _FORTIFY_SOURCE=2 -mtune=generic -march=x86-64 -g -O3 -std=gnu11 -fno-strict-aliasing -fno-omit-frame-pointer -fstack-protector-all -fPIC -fvisibility=hidden -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -fzero-init-padding-bits=all LIBPERF_WARN page_size _ISgraph nr_cpus_conf cpu_map__new_sysconf __u16 __u8 orig __perf_cpu_map__nr cmp_cpu perf_cpu_map__intersect __compar_fn_t __isoc23_strtoul __u32 nr_cpus perf_cpu_map refcount_t perf_cpu_map__merge __fprintf_chk merged __u32_alias_t _ISprint __ret high payload_size perf_cpu_map__put __ret_warn_on cpu_map__delete cpu_map__trim_new other __builtin_memcpy __read_once_size _ISpunct tmp_len max_entries __perf_cpu_map__cpu __builtin_fwrite _ISalnum tmp_cpus _max1 _max2 __u16_alias_t refcount_read perf_cpu_map__new_online_cpus _ISxdigit _ISupper perf_cpu_map__new_int __ctype_b_loc _IScntrl perf_cpu_map__get __ret_warn_once refcount_inc cpu_a cpu_b atomic_read refcount_struct start_cpu cpu_map__new_sysfs_online perf_cpu_map__has perf_cpu_map__refcnt atomic_set perf_cpu_map__max perf_cpu_map__alloc __u8_alias_t qsort invalid perf_cpu_map__new_any_cpu _ISalpha __warned refcount_inc_not_zero _ISblank atomic_cmpxchg _ISspace refs __int16_t __u64_alias_t perf_cpu_map__set_nr refcount_set __old _ISlower __src perf_cpu perf_cpu_map__has_any_cpu_or_is_empty __dest perf_cpu_map__min perf_cpu_map__equal cpu_at_idx perf_cpu_map__idx cpu_list _ISdigit perf_cpu_map__is_any_cpu_or_is_empty perf_cpu_map__new refcount_sub_and_test atomic_t perf_cpu_map__is_empty refcount_dec_and_test perf_cpu_map__has_any_cpu perf_cpu_map__is_subset __len end_cpu perf_thread_map__comm thread_map_data perf_thread_map __ch __builtin_memset perf_thread_map__delete err_thread perf_thread_map__pid perf_thread_map__realloc __builtin_malloc perf_thread_map__reset perf_thread_map__set_pid perf_thread_map__new_dummy nr_threads __pid_t perf_thread_map__new_array perf_thread_map__put perf_thread_map__idx perf_thread_map__get perf_thread_map__nr inherit_stat ncpus perf_evsel__apply_filter PERF_FORMAT_TOTAL_TIME_RUNNING probe_offset __list_add perf_evsel__read_size row_size perf_evsel__read __reserved_1 exclude_hv comm_exec zalloc perf_mmap__init aux_sample_size PERF_SAMPLE_REGS_INTR perf_evsel__alloc_fd perf_event_sample_format empty_cpu_map perf_evsel__attr perf_sample_id__get_period_storage PERF_SAMPLE_AUX perf_evsel__mmap pprev use_clockid is_pmu_core PERF_SAMPLE_BRANCH_STACK perf_mmap__read_self perf_evsel__free_fd defer_output unmap_cb perf_evsel__new wakeup_events PERF_SAMPLE_DATA_PAGE_SIZE perf_evsel__alloc_id sample_regs_user PERF_FORMAT_GROUP INIT_LIST_HEAD perf_counts_values__scale hash_32 __u64 machine_pid perf_mmap PERF_SAMPLE_TRANSACTION xyarray__max_x perf_evsel__free_id precise_ip remove_on_exec empty_thread_map pmu_cpus perf_evsel__attr_has_per_thread_sample_period exclusive PERF_SAMPLE_WEIGHT pages PERF_FORMAT_TOTAL_TIME_ENABLED perf_evsel__cpus ____ptr PERF_SAMPLE_CGROUP perf_mmap__munmap config1 config2 config3 config4 PERF_SAMPLE_CALLCHAIN PERF_SAMPLE_CPU contents inherit perf_evsel__threads PERF_SAMPLE_READ xyarray__new disabled uprobe_path context_switch PERF_SAMPLE_ID nr_members PERF_SAMPLE_IP perf_evsel__alloc_mmap perf_evsel__enable_thread get_group_fd perf_evsel__close_fd __write_once_size perf_evsel__enable perf_evsel__run_ioctl perf_evsel__close sample_stack_user perf_sample_id sample_id_all perf_evsel__init PERF_FORMAT_ID libperf_unmap_cb_t enable_on_exec aux_start_paused sample_max_stack wakeup_watermark PERF_SAMPLE_CODE_PAGE_SIZE kprobe_addr sig_data PERF_SAMPLE_PHYS_ADDR reads_only_on_cpu_idx0 exclude_guest list_del_init __hash_32_generic perf_event_read_format __list_del_entry PERF_SAMPLE_PERIOD PERF_SAMPLE_TID perf_evsel__exit exclude_kernel text_poke xyarray aux_pause perf_evsel__mmap_base mmap_data PERF_SAMPLE_TIME __zfree list_add_tail sample_regs_intr event_copy PERF_FORMAT_MAX prot PERF_SAMPLE_STACK_USER PERF_SAMPLE_IDENTIFIER bp_addr perf_evsel__delete perf_evsel PERF_SAMPLE_REGS_USER __list_del perf_evsel__ioctl hlist_head perf_mmap__mmap vcpu inherit_thread __xyarray__entry perf_evsel__munmap perf_evsel__disable perf_evsel__disable_cpu PERF_SAMPLE_ADDR __s32 PERF_SAMPLE_DATA_SRC hnode perf_evsel__close_cpu exclude_user sample_freq exclude_callchain_user aux_watermark __mptr pinned kprobe_func hlist_add_head perf_sample_id_period perf_evsel__close_fd_cpu aux_resume bp_len hlist_node PERF_SAMPLE_WEIGHT_STRUCT exclude_host entry_size evsel_fd perf_evsel__enable_cpu nthreads PERF_SAMPLE_STREAM_ID pscaled aux_action perf_evsel__read_group bp_type perf_evsel__adjust_values perf_evsel__open exclude_callchain_kernel exclude_idle sys_perf_event_open PERF_SAMPLE_MAX write_backward PERF_SAMPLE_RAW event_copy_sz branch_sample_type aux_output perf_mmap_param sigtrap PERF_FORMAT_LOST requires_cpu xyarray__delete defer_callchain perf_counts_values xyarray__max_y cpu_map_idx __s8 __reserved_2 __reserved_3 per_stream_periods perf_event_attr perf_evlist__alloc_mmap perf_evlist__open perf_evlist__mmap_cb_mmap perf_evlist__add_pollfd perf_evlist__init perf_evlist__delete mmap_per_evsel user_requested_cpus all_cpus fdarray__available_entries revents_and_mask flgs heads perf_evlist__mmap_ops nfds nr_entries mmap_ovw perf_evlist_mmap__cb_idx_t out_err __read_alias perf_evlist__close perf_evlist__nr_groups perf_evlist__exit perf_evlist__add perf_evlist__id_add_fd out_unmap perf_mmap__get perf_evlist_mmap__cb_mmap_t perf_evlist__purge __buf perf_evlist__set_mmap_first has_user_cpus perf_evlist__id_add fcntl64 perf_evlist__go_system_wide perf_evlist__filter_pollfd perf_evlist__mmap perf_evlist_mmap_ops needs_map_propagation perf_evlist__enable read_data perf_evlist__new perf_evlist__mmap_cb_get __perf_evlist__set_leader evlist_cpu mmap_per_thread perf_evlist__next_mmap perf_evlist__nr_mmaps mmap_per_cpu srcs perf_evlist__first perf_evlist__poll __read_chk perf_evlist__id_hash perf_evlist__remove perf_evlist__reset_id_hash perf_evlist perf_evlist__alloc_pollfd revent perf_evlist__disable perf_evlist__read_format perf_evlist__munmap_filtered perf_evlist__next perf_evlist__set_maps __fd perf_evlist_mmap__cb_get_t __read_chk_warn mmap_ovw_first fcntl perf_mmap__put cpu_idx hash_64_generic perf_evsel__set_sid_idx _output_overwrite __func__ __nbytes perf_evlist__munmap __perf_evlist__propagate_maps time_offset data_head array_exp cap_user_time_short build_id_size alb_failed perf_record_event_update_cpus newidle_lb_nobusyg perf_record_header_build_id newidle_lb_nobusyq pgoff newidle_lb_gained pack2 sbe_pushed sbf_pushed aux_size perf_event_header busy_lb_hot_gained sbe_balanced ring_buffer_read_head perf_record_thread_map_entry data_size perf_mmap__read_event nr_namespaces perf_record_header_attr time_enabled read_timestamp mmap64 _min1 _min2 ttwu_count perf_record_schedstat_cpu_v15 perf_record_schedstat_cpu_v16 perf_record_schedstat_cpu_v17 reserved2__ perf_event_mmap_page perf_record_compressed perf_record_ksymbol feat_id alb_pushed newidle_lb_balanced perf_mmap__read_head ptid capabilities perf_record_mmap2 range_cpu_data newidle_lb_imbalance_misfit perf_record_header_event_type perf_record_bpf_event delta time_mult perf_record_cpu_map compat_version sbf_balanced newidle_lb_hot_gained perf_record_lost_samples prog_name cap_____res perf_record_stat_config perf_record_event_update_scale busy_lb_imbalance pack new_len cap_user_rdpmc __perf_mmap__read_init perf_record_callchain_deferred ring_buffer_write_tail diff rq_cpu_time old_len startp perf_record_bpf_metadata perf_mmap__read perf_record_event_update cpus_data perf_record_mmap perf_record_lost busy_lb_count reserved1__ perf_record_cpu_map_data perf_record_sample long_size alb_count code data_offset event_id time_cycles sbe_count perf_record_auxtrace overwrite_rb_find_range time_mask perf_record_compressed2 perf_record_stat_config_entry perf_record_fork __s64 ttwu_local perf_record_itrace_start ___p1 perf_record_stat_round perf_record_schedstat_domain run_delay sched_count perf_mmap__write_tail newidle_lb_imbalance_task next_prev_pid perf_record_schedstat_domain_v15 unit aux_tail sched_goidle data_tail busy_lb_imbalance_misfit perf_record_namespaces cap_user_time_zero perf_record_throttle busy_lb_gained pcount perf_mmap__consume perf_record_thread_map mask32_data perf_record_auxtrace_error __reserved perf_record_switch ttwu_wake_remote read_perf_counter busy_lb_balanced mask64_data sbf_count perf_record_auxtrace_info perf_ns_link_info busy_lb_nobusyg busy_lb_nobusyq newidle_lb_imbalance_util newidle_lb_count busy_lb_failed newidle_lb_imbalance pheader newidle_lb_failed perf_record_range_cpu_map newidle_lb_imbalance_load cookie perf_mmap__mmap_len busy_lb_imbalance_task ino_generation aux_offset perf_record_bpf_metadata_entry perf_record_aux perf_record_header_feature perf_record_cgroup __pad perf_record_schedstat_domain_v16 perf_record_schedstat_domain_v17 perf_record_id_index evcnt perf_mmap__read_done ttwu_move_balance time_running feat ppid cap_bit0_is_deprecated busy_lb_imbalance_util ttwu_move_affine perf_record_mask_cpu_map32 misc next_prev_tid yld_count stream_id cap_user_time perf_record_text_poke_event perf_trace_event_type reserved__ evt_head cpu_map_entries ksym_type busy_lb_imbalance_load perf_record_time_conv mul_u64_u32_shr perf_record_comm perf_mmap__empty cap_bit0 perf_record_stat pmc_width perf_record_mask_cpu_map64 reference perf_record_schedstat_cpu perf_record_aux_output_hw_id id_index_entry time_shift perf_record_header_tracing_data aux_head perf_record_read ylen xyarray__reset is_read left writen __pread64_chk pread __offset offs __pread64_chk_warn preadn __pread64_alias pread64 buf_start __glibc_objsize(__o) __builtin_dynamic_object_size (__o, 1) STATX__RESERVED 0x80000000U __getcwd_chk STATX_UID 0x00000008U __releases_shared(...)  __must_hold_shared(...)  _TOOLS_LINUX_COMPILER_H_  _compiletime_assert(condition,msg,prefix,suffix) __compiletime_assert(condition, msg, prefix, suffix) __SUBCMD_UTIL_H  __glibc_unsigned_or_positive(__l) ((__typeof (__l)) 0 < (__typeof (__l)) -1 || (__builtin_constant_p (__l) && (__l) > 0)) pager_env execv_cmd __aligned(x) __attribute__((aligned(x))) pwd_stat __glibc_fortify_n(f,__l,__s,__osz,...) (__glibc_safe_or_unknown_len (__l, __s, __osz) ? __ ## f ## _alias (__VA_ARGS__) : (__glibc_unsafe_len (__l, __s, __osz) ? __ ## f ## _chk_warn (__VA_ARGS__, (__osz) / (__s)) : __ ## f ## _chk (__VA_ARGS__, (__osz) / (__s)))) st_uid __cond_acquires(ret,x)  __acquire_shared(x) (void)0 st_size __always_inline inline __attribute__((always_inline)) __mode_t __statx_defined 1 st_blksize STATX_MODE 0x00000002U __guarded_by(...)  WRITE_ONCE(x,val) ({ union { typeof(x) __val; char __c[1]; } __u = { .__val = (val) }; __write_once_size(&(x), __u.__c, sizeof(x)); __u.__val; }) st_gid argv0 __syscall_slong_t __must_hold(...)  st_nlink __PERF_SUBCMD_CONFIG_H  __fortify_clang_warning(__c,__msg)  st_ctim STATX_BLOCKS 0x00000400U _BITS_STDIO2_DEC_H 1 __scanf(a,b) __attribute__((format(scanf, a, b))) fread_unlocked(ptr,size,n,stream) (__extension__ ((__builtin_constant_p (size) && __builtin_constant_p (n) && (size_t) (size) * (size_t) (n) <= 8 && (size_t) (size) != 0) ? ({ char *__ptr = (char *) (ptr); FILE *__stream = (stream); size_t __cnt; for (__cnt = (size_t) (size) * (size_t) (n); __cnt > 0; --__cnt) { int __c = getc_unlocked (__stream); if (__c == EOF) break; *__ptr++ = __c; } ((size_t) (size) * (size_t) (n) - __cnt) / (size_t) (size); }) : (((__builtin_constant_p (size) && (size_t) (size) == 0) || (__builtin_constant_p (n) && (size_t) (n) == 0)) ? ((void) (ptr), (void) (stream), (void) (size), (void) (n), (size_t) 0) : fread_unlocked (ptr, size, n, stream)))) __strlcpy_chk STATX_WRITE_ATOMIC 0x00010000U __rcu  STATX_BASIC_STATS 0x000007ffU st_atim __compiletime_error(message) __attribute__((error(message))) STATX_ATTR_APPEND 0x00000020 __uid_t ALLOC_GROW(x,nr,alloc) do { if ((nr) > alloc) { if (alloc_nr(alloc) < (nr)) alloc = (nr); else alloc = alloc_nr(alloc); x = xrealloc((x), alloc * sizeof(*(x))); } } while(0) set_argv_exec_path __fortify_clang_warn_if_src_too_large(__dest,__src)  __blkcnt_t __glibc_fortify(f,__l,__s,__osz,...) (__glibc_safe_or_unknown_len (__l, __s, __osz) ? __ ## f ## _alias (__VA_ARGS__) : (__glibc_unsafe_len (__l, __s, __osz) ? __ ## f ## _chk_warn (__VA_ARGS__, __osz) : __ ## f ## _chk (__VA_ARGS__, __osz))) __getcwd_alias READ_ONCE(x) ({ union { typeof(x) __val; char __c[1]; } __u = { .__c = { 0 } }; __read_once_size(&(x), __u.__c, sizeof(x)); __u.__val; }) STATX_DIO_READ_ALIGN 0x00020000U __asprintf_chk old_path fwrite_unlocked(ptr,size,n,stream) (__extension__ ((__builtin_constant_p (size) && __builtin_constant_p (n) && (size_t) (size) * (size_t) (n) <= 8 && (size_t) (size) != 0) ? ({ const char *__ptr = (const char *) (ptr); FILE *__stream = (stream); size_t __cnt; for (__cnt = (size_t) (size) * (size_t) (n); __cnt > 0; --__cnt) if (putc_unlocked (*__ptr++, __stream) == EOF) break; ((size_t) (size) * (size_t) (n) - __cnt) / (size_t) (size); }) : (((__builtin_constant_p (size) && (size_t) (size) == 0) || (__builtin_constant_p (n) && (size_t) (n) == 0)) ? ((void) (ptr), (void) (stream), (void) (size), (void) (n), (size_t) 0) : fwrite_unlocked (ptr, size, n, stream)))) __fortify_clang_warning_only_if_bos_lt2(__n,__buf,div,__complaint)  __wur __attribute_warn_unused_result__ __cond_acquires_shared(ret,x)  __glibc_objsize0(__o) __builtin_dynamic_object_size (__o, 0) __SUBCMD_EXEC_CMD_H  STATX_ATTR_ENCRYPTED 0x00000800 __FD_ELT noinline __attribute__((noinline)) __maybe_unused __attribute__((unused)) STATX_ATTR_AUTOMOUNT 0x00001000 _TOOLS_LINUX_COMPILER_CONTEXT_ANALYSIS_H  __releases(...)  STATX_BTIME 0x00000800U strlcpy STATX_SIZE 0x00000200U __acquires_shared(...)  __nocf_check __attribute__((nocf_check)) __acquires_shared_ret  GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__) add_path __fortify_clang_warning_only_if_bos0_lt(__n,__buf,__complaint)  fallthrough __attribute__((__fallthrough__)) make_nonrelative_path _BITS_STDIO2_H 1 STATX_TYPE 0x00000001U get_pwd_cwd system_path __acquire(x) (void)0 __nlink_t st_mode STATX_ATTR_MOUNT_ROOT 0x00002000 _BITS_SELECT_DECL_H 1 STATX_SUBVOL 0x00008000U STATX_MNT_ID 0x00001000U __fortify_clang_overload_arg0(__type,__attr,__name) __fortify_clang_overload_arg (__type, __attr, __name) params get_argv_exec_path __iomem  __noreturn __attribute__((noreturn)) timespec STATX_ATTR_NODUMP 0x00000040 __context_unsafe(comment)  OPTIMIZER_HIDE_VAR(var) __asm__ ("" : "=r" (var) : "0" (var)) is_dir_sep(c) ((c) == '/') __glibc_safe_len_cond(__l,__s,__osz) ((__l) <= (__osz) / (__s)) strndup STATX_ATTR_IMMUTABLE 0x00000010 asm_goto_output(x...) asm goto(x) __statx_timestamp_defined 1 stat64 __FD_ELT(d) __extension__ ({ long int __d = (d); (__builtin_constant_p (__d) ? (0 <= __d && __d < __FD_SETSIZE ? (__d / __NFDBITS) : __fdelt_warn (__d)) : __fdelt_chk (__d)); }) subcmd_config __time_t astrcatf(out,fmt,...) ({ char *tmp = *(out); if (asprintf((out), "%s" fmt, tmp ?: "", ## __VA_ARGS__) == -1) die("asprintf failed"); free(tmp); }) __release_shared(x) (void)0 STATX_MNT_ID_UNIQUE 0x00004000U _GNU_SOURCE 1 likely(x) __builtin_expect(!!(x), 1) __blksize_t STATX_NLINK 0x00000004U __read_mostly  __scalar_type_to_expr_cases(type) unsigned type: (unsigned type)0, signed type: (signed type)0 compiletime_assert(condition,msg) _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) MAX_ARGS 32 execvp __acquire_ret(call,expr) (call) __strlcpy_alias __fortify_clang_warn_if_dest_too_small(__dest,__len)  __USE_EXTERN_INLINES 1 report __attribute_const__  extract_argv0_path _FORTIFY_SOURCE 3 _BITS_STDIO_H 1 _LINUX_STAT_H  const_true(x) __builtin_choose_expr(__is_constexpr(x), x, false) unreachable() __builtin_unreachable() __STDIO_INLINE __must_not_hold(...)  __builtin___memcpy_chk STATX_ALL 0x00000fffU STATX_INO 0x00000100U __must_be_array(a) BUILD_BUG_ON_ZERO(__same_type((a), &(a)[0])) __getcwd_chk_warn __BUILD_BUG_ON_ZERO_MSG(e,msg,...) ((int)sizeof(struct {_Static_assert(!(e), msg);})) __unqual_scalar_typeof(x) typeof( _Generic((x), char: (char)0, __scalar_type_to_expr_cases(char), __scalar_type_to_expr_cases(short), __scalar_type_to_expr_cases(int), __scalar_type_to_expr_cases(long), __scalar_type_to_expr_cases(long long), default: (x))) setup_path exec_cmd_init __fortified_attr_access(a,o,s)  __acquire_shared_ret(call,expr) (call) __printf(a,b) __attribute__((format(printf, a, b))) __STRINGS_FORTIFIED 1 STATX_GID 0x00000010U unlikely(x) __builtin_expect(!!(x), 0) new_path __LINUX_COMPILER_TYPES_H  ___PASTE(a,b) a ##b zfree(ptr) ({ free(*ptr); *ptr = NULL; }) fread_unlocked __is_constexpr(x) (sizeof(int) == sizeof(*(8 ? ((void *)((long)(x) * 0l)) : (int *)8))) __dev_t __glibc_reserved slash __acquires(...)  __weak __attribute__((weak)) __glibc_safe_or_unknown_len(__l,__s,__osz) ((__builtin_constant_p (__osz) && (__osz) == (__SIZE_TYPE__) -1) || (__glibc_unsigned_or_positive (__l) && __builtin_constant_p (__glibc_safe_len_cond ((__SIZE_TYPE__) (__l), (__s), (__osz))) && __glibc_safe_len_cond ((__SIZE_TYPE__) (__l), (__s), (__osz)))) enable_context_analysis()  disable_context_analysis()  __pad0 tv_nsec barrier() __asm__ __volatile__("": : :"memory") STATX_ATIME 0x00000020U STATX_DIOALIGN 0x00002000U context_unsafe(...) ({ __VA_ARGS__; }) alloc_nr(x) (((x)+16)*3/2) STATX_CTIME 0x00000080U __STDIO_INLINE __extern_inline st_rdev argc st_dev __OPTIMIZE__ 1 __fortify_clang_warn_if_dest_too_small0(__dest,__len)  __fortify_clang_warning_only_if_bos_lt(__n,__buf,__complaint)  __pure __attribute__((pure)) __same_type(a,b) __builtin_types_compatible_p(typeof(a), typeof(b)) __glibc_unsafe_len(__l,__s,__osz) (__glibc_unsigned_or_positive (__l) && __builtin_constant_p (__glibc_safe_len_cond ((__SIZE_TYPE__) (__l), __s, __osz)) && !__glibc_safe_len_cond ((__SIZE_TYPE__) (__l), __s, __osz)) STATX_ATTR_VERITY 0x00100000 __gid_t getcwd __builtin___vsnprintf_chk __fortify_use_clang 0 nargv __no_context_analysis  st_blocks STATX_ATTR_COMPRESSED 0x00000004 __STDLIB_MB_LEN_MAX 16 _BITS_UNISTD_DECL_H 1 __always_unused __attribute__((__unused__)) exec_name cwd_stat __used __attribute__((__unused__)) vsnprintf __fortify_clang_warning_only_if_bos0_lt2(__n,__buf,__div,complaint)  prepare_exec_cmd __packed __attribute__((packed)) st_ino execl_cmd STATX_ATTR_WRITE_ATOMIC 0x00400000 __naked __attribute__((__naked__)) __ino_t __compiletime_assert(condition,msg,prefix,suffix) do { extern void prefix ## suffix(void) __compiletime_error(msg); if (!(condition)) prefix ## suffix(); } while (0) astrcat __release(x) (void)0 __acquires_ret  context_unsafe_alias(p)  __PASTE(a,b) ___PASTE(a, b) __fortify_clang_overload_arg(__type,__attr,__name) __type __attr __name is_absolute_path GNU C99 15.2.0 -D_FORTIFY_SOURCE=3 -mtune=generic -march=x86-64 -ggdb3 -O3 -std=gnu99 -fPIC -fasynchronous-unwind-tables -fstack-protector-strong -fstack-clash-protection -fcf-protection -fzero-init-padding-bits=all __USE_FORTIFY_LEVEL 3 STATX_ATTR_DAX 0x00200000 __pt_guarded_by(...)  st_mtim STATX_MTIME 0x00000040U exec_path_env _BITS_STRING_FORTIFIED_H 1 context_lock_struct(name,...) struct __VA_ARGS__ name __B1200 0000011 __EXTB __B38400 B200 200U CR0 0000000 other_cmds B4000000 4000000U ONLCR 0000004 ECHOPRT 0002000 IEXTEN 0100000 NCCS 32 FF1 0100000 list_commands_in_dir B150 150U TCSADRAIN 1 B2000000 2000000U FLUSHO 0010000 memcmp __BOTHER 0010000 INLCR 0000100 ECHOKE 0004000 XTABS 0014000 NL0 0000000 IUTF8 0040000 putchar B500000 500000U __printf_chk __B500000 0010005 B307200 307200U B14400 14400U B600 600U ONLRET 0000040 B2500000 2500000U __isoc23_strtol __B75 0000002 TCIFLUSH 0 TCIOFF 2 ECHO 0000010 add_cmdname VMIN 6 CSTATUS '\0' __B200 0000006 __SUBCMD_HELP_H  IXANY 0004000 PARENB 0000400 __B150 0000005 __B921600 0010007 B28800 28800U static_assert exclude_cmds OFILL 0000100 VT1 0040000 VEOL2 16 TCSAFLUSH 2 ISIG 0000001 ICRNL 0000400 load_command_list main_cmds cmdname_compare __B0 0000000 _HAVE_STRUCT_TERMIOS_C_ISPEED 1 __B57600 0010001 ICANON 0000002 CMSPAR 010000000000 entlen mput_char pretty_print_string_list VQUIT 1 __B19200 0000016 CEOL '\0' ECHOE 0000020 __B134 0000004 _TERMIOS_H 1 strstarts B576000 576000U __B460800 0010004 TCOON 1 title xrealloc assert_perror(errnum) (!(errnum) ? __ASSERT_VOID_CAST (0) : __assert_perror_fail ((errnum), __FILE__, __LINE__, __ASSERT_FUNCTION)) B5000000 5000000U get_term_dimensions TCOOFF 0 __B3000000 0010015 __B2400 0000013 CREAD 0000200 BS0 0000000 ECHOK 0000040 B134 134U VEOF 4 HUPCL 0002000 B4800 4800U OPOST 0000001 B230400 230400U __B3500000 0010016 B1152000 1152000U B1000000 1000000U ws_row B57600 57600U TCIOFLUSH 2 VERASE 2 B1200 1200U VLNEXT 15 VKILL 3 __B38400 0000017 extlen ECHONL 0000100 __B600 0000010 B33600 33600U rows CIBAUD 002003600000 OFDEL 0000200 ECHOCTL 0001000 TAB0 0000000 TCION 3 TABDLY 0014000 PENDIN 0040000 NLDLY 0000400 __B4800 0000014 B76800 76800U VSTOP 9 IMAXBEL 0020000 CBAUD 000000010017 __B1800 0000012 IXOFF 0010000 OCRNL 0000010 BSDLY 0020000 B115200 115200U longest CR3 0003000 __B2000000 0010013 VWERASE 14 winsize EXTA B19200 __EXTA __B19200 NL1 0000400 B921600 921600U IBSHIFT 16 VEOL 11 CLOCAL 0004000 B50 50U __nptr uniq NOFLSH 0000200 B300 300U __B2500000 0010014 __B9600 0000015 B2400 2400U BRKINT 0000002 static_assert _Static_assert __B4000000 0010017 XCASE 0000004 B0 0U is_executable is_in_cmdlist __B300 0000007 FF0 0000000 B19200 19200U assert(...) ((void) sizeof (__assert_single_arg (__VA_ARGS__)), __extension__ ({ if (__VA_ARGS__) ; else __assert_fail (#__VA_ARGS__, __FILE__, __LINE__, __ASSERT_FUNCTION); })) __B1000000 0010010 VSUSP 10 ISTRIP 0000040 readdir64 B110 110U FFDLY 0100000 INPCK 0000020 BOTHER __BOTHER PARODD 0001000 TAB3 0014000 IGNBRK 0000001 __B230400 0010003 VTDLY 0040000 PARMRK 0000010 B1500000 1500000U paths __B1500000 0010012 CR1 0001000 colon EXTPROC 0200000 B460800 460800U TAB1 0004000 excludes B38400 38400U TAB2 0010000 TCOFLUSH 1 __B576000 0010006 __STDC_VERSION_ASSERT_H__ 202311L VSTART 8 max_cols IUCLC 0001000 B75 75U CRTSCTS 020000000000 CS5 0000000 list_commands __B50 0000001 CSTOPB 0000100 closedir clean_cmdnames BAUD_MAX SPEED_MAX CBAUDEX 000000010000 CS6 0000020 B3000000 3000000U _HAVE_STRUCT_TERMIOS_C_OSPEED 1 ONOCR 0000020 ADDRB 04000000000 B7200 7200U VREPRINT 12 IGNPAR 0000004 __MAX_BAUD 4294967295U EXTB B38400 CCEQ(val,c) ((c) == (val) && (val) != _POSIX_VDISABLE) ws_ypixel __B1152000 0010011 __ASSERT_VARIADIC 1 ws_xpixel CS8 0000060 CS7 0000040 SPEED_MAX 4294967295U CRDLY 0003000 B614400 614400U __B110 0000003 ws_col B9600 9600U has_extension __B115200 0010002 B3500000 3500000U TCSANOW 0 IXON 0002000 VSWTC 7 B153600 153600U BS1 0020000 VTIME 5 VT0 0000000 IGNCR 0000200 OLCUC 0000002 B10000000 10000000U TOSTOP 0000400 env_path VDISCARD 13 readdir prefix_len CSIZE 0000060 VINTR 0 CR2 0002000 B1800 1800U sigchain_fun si_status _sifields._sigchld.si_status SIGALRM 14 __stack_t_defined 1 si_call_addr _sifields._sigsys._call_addr POLL_OUT POLL_OUT SIGCLD SIGCHLD BUS_MCEERR_AR BUS_MCEERR_AR SIGRTMIN (__libc_current_sigrtmin ()) __SUBCMD_RUN_COMMAND_H  ILL_PRVOPC ILL_PRVOPC isatty si_lower _sifields._sigfault._bounds._addr_bnd._lower _BITS_SIGINFO_CONSTS_ARCH_H 1 POLL_PRI POLL_PRI SA_NOCLDWAIT 2 SEGV_MTEAERR SEGV_MTEAERR SEGV_ACCADI SEGV_ACCADI SI_QUEUE SI_QUEUE si_syscall _sifields._sigsys._syscall BUS_MCEERR_AO BUS_MCEERR_AO SEGV_ACCERR SEGV_ACCERR si_upper _sifields._sigfault._bounds._addr_bnd._upper SIGEV_NONE SIGEV_NONE _BITS_SIGSTACK_H 1 SIGINT 2 _NSIG (__SIGRTMAX + 1) REG_CR2 REG_CR2 SIGPROF 27 REG_RDI REG_RDI SA_STACK SA_ONSTACK REG_RIP REG_RIP _BITS_SS_FLAGS_H 1 spawned_pager sa_sigaction __sigaction_handler.sa_sigaction sigev_notify_function _sigev_un._sigev_thread._function _SIGNAL_H  FPE_INTDIV FPE_INTDIV no_stderr __SI_ASYNCIO_AFTER_SIGIO 1 __SI_CLOCK_T __clock_t SEGV_MAPERR SEGV_MAPERR REG_RDX REG_RDX __SUBCMD_PAGER_H  pager_init SI_USER SI_USER FPE_INTOVF FPE_INTOVF SIGURG 23 SIGBUS 7 SIGCHLD 17 SA_ONSTACK 0x08000000 REG_R11 REG_R11 FPE_FLTUNK FPE_FLTUNK REG_R12 REG_R12 si_addr _sifields._sigfault.si_addr REG_R14 REG_R14 atexit SIGSYS 31 REG_R15 REG_R15 pager_process SEGV_PKUERR SEGV_PKUERR access __fd_mask sigmask(sig) __glibc_macro_warning ("sigmask is deprecated") ((int)(1u << ((sig) - 1))) __sigevent_t_defined 1 __fdelt_chk REG_R10 REG_R10 SIGIOT SIGABRT FPE_FLTINV FPE_FLTINV TRAP_HWBKPT TRAP_HWBKPT sigchain_push_common SI_KERNEL SI_KERNEL _BITS_SIGNUM_ARCH_H 1 fflush __SI_ERRNO_THEN_CODE 1 tv_usec MINSIGSTKSZ 2048 ILL_PRVREG ILL_PRVREG __SIGRTMIN 32 si_ptr _sifields._rt.si_sigval.sival_ptr REG_TRAPNO REG_TRAPNO _SYS_UCONTEXT_H 1 __suseconds_t SEGV_ADIPERR SEGV_ADIPERR ILL_ILLTRP ILL_ILLTRP wait_for_pager SIGXCPU 24 __SI_MAX_SIZE 128 SI_TKILL SI_TKILL SA_RESETHAND 0x80000000 REG_RSI REG_RSI si_stime _sifields._sigchld.si_stime si_timerid _sifields._timer.si_tid SEGV_ADIDERR SEGV_ADIDERR SIGILL 4 SIGTTIN 21 TRAP_BRKPT TRAP_BRKPT _BITS_SIGCONTEXT_H 1 _BITS_SIGNUM_GENERIC_H 1 no_stdout FPE_CONDTRAP FPE_CONDTRAP no_stdin SA_SIGINFO 4 __SUBCMD_SIGCHAIN_H  si_overrun _sifields._timer.si_overrun __SIGEV_MAX_SIZE 64 SIGSEGV 11 preexec_cb select __SI_BAND_TYPE long int MINSIGSTKSZ SIGSTKSZ _BITS_SIGINFO_CONSTS_H 1 SA_INTERRUPT 0x20000000 SI_ASYNCIO SI_ASYNCIO si_uid _sifields._kill.si_uid _BITS_SIGACTION_H 1 pager_get_columns REG_OLDMASK REG_OLDMASK CLD_CONTINUED CLD_CONTINUED _BITS_SIGTHREAD_H 1 REG_CSGSFS REG_CSGSFS __ctx(fld) fld fds_bits IS_RUN_COMMAND_ERR(x) (-(x) >= ERR_RUN_COMMAND_FORK) si_value _sifields._rt.si_sigval REG_R9 REG_R9 FPE_FLTUND FPE_FLTUND pager_columns __NGREG 23 FPE_FLTRES FPE_FLTRES CLD_EXITED CLD_EXITED SEGV_MTESERR SEGV_MTESERR CLD_DUMPED CLD_DUMPED pager_preexec ____sigval_t_defined  __SIGEV_PAD_SIZE ((__SIGEV_MAX_SIZE / sizeof (int)) - 4) FPE_FLTSUB FPE_FLTSUB si_band _sifields._sigpoll.si_band SIGUSR1 10 SIGUSR2 12 stdout_to_stderr __sig_atomic_t_defined 1 __fdelt_warn SIG_ERR ((__sighandler_t) -1) SS_DISABLE SS_DISABLE SA_ONESHOT SA_RESETHAND SIGKILL 9 SI_MESGQ SI_MESGQ SA_NOCLDSTOP 1 REG_RAX REG_RAX si_pid _sifields._kill.si_pid SIGXFSZ 25 __SI_SIGFAULT_ADDL  FP_XSTATE_MAGIC2 0x46505845U POLL_HUP POLL_HUP ILL_COPROC ILL_COPROC timeval SEGV_BNDERR SEGV_BNDERR SIGTTOU 22 SIGSTKSZ 8192 ILL_ILLOPN ILL_ILLOPN SIG_IGN ((__sighandler_t) 1) SIG_BLOCK 0 __siginfo_t_defined 1 SIGRTMAX (__libc_current_sigrtmax ()) finish_result fd_set __sigstack_defined 1 SIGTRAP 5 CLD_KILLED CLD_KILLED REG_RSP REG_RSP __SIGRTMAX 64 FP_XSTATE_MAGIC2_SIZE sizeof (FP_XSTATE_MAGIC2) ILL_ILLADR ILL_ILLADR SIGFPE 8 finish_command SIGPOLL 29 forced_pager si_fd _sifields._sigpoll.si_fd __arr SIGWINCH 28 SIGQUIT 3 SIGPWR 30 TRAP_UNK TRAP_UNK SIGTERM 15 REG_ERR REG_ERR TRAP_PERF TRAP_PERF force_pager SIGIO SIGPOLL NSIG _NSIG SA_NODEFER 0x40000000 SI_SIGIO SI_SIGIO SEGV_CPERR SEGV_CPERR signo si_utime _sifields._sigchld.si_utime __SI_ALIGNMENT  REG_RBP REG_RBP pager_argv ILL_BADSTK ILL_BADSTK SIGHUP 1 SIGSTKFLT 16 REG_RBX REG_RBX REG_EFL REG_EFL SIGTSTP 20 TRAP_BRANCH TRAP_BRANCH ILL_BADIADDR ILL_BADIADDR no_exec_cmd SIG_DFL ((__sighandler_t) 0) SI_ASYNCNL SI_ASYNCNL SIGEV_THREAD SIGEV_THREAD SA_NOMASK SA_NODEFER sa_handler __sigaction_handler.sa_handler _BITS_SIGINFO_ARCH_H 1 SIGPIPE 13 dup2 SIG_HOLD ((__sighandler_t) 2) FPE_FLTDIV FPE_FLTDIV SIGEV_SIGNAL SIGEV_SIGNAL raise __SI_HAVE_SIGSYS 1 SYS_USER_DISPATCH SYS_USER_DISPATCH si_int _sifields._rt.si_sigval.sival_int setup_pager FPE_FLTOVF FPE_FLTOVF POLL_IN POLL_IN RUN_COMMAND_NO_STDIN 1 RUN_COMMAND_STDOUT_TO_STDERR 4 sigchain_pop SIGEV_THREAD_ID SIGEV_THREAD_ID FP_XSTATE_MAGIC1 0x46505853U child_process REG_R8 REG_R8 SYS_SECCOMP SYS_SECCOMP SIGABRT 6 exception SIG_SETMASK 2 TRAP_TRACE TRAP_TRACE BUS_ADRERR BUS_ADRERR sigev_notify_attributes _sigev_un._sigev_thread._attribute SIGSTKSZ sysconf (_SC_SIGSTKSZ) _BITS_SIGEVENT_CONSTS_H 1 si_addr_lsb _sifields._sigfault.si_addr_lsb pager_in_use BUS_OBJERR BUS_OBJERR __ctx start_command CLD_STOPPED CLD_STOPPED SIG_UNBLOCK 1 POLL_MSG POLL_MSG SIGCONT 18 REG_R13 REG_R13 RUN_EXEC_CMD 2 BUS_ADRALN BUS_ADRALN wait_for_pager_signal SA_RESTART 0x10000000 SI_DETHREAD SI_DETHREAD SS_ONSTACK SS_ONSTACK SIGVTALRM 26 si_pkey _sifields._sigfault._bounds._pkey POLL_ERR POLL_ERR ILL_ILLOPC ILL_ILLOPC SI_TIMER SI_TIMER REG_RCX REG_RCX si_arch _sifields._sigsys._arch SIGSTOP 19 __SI_PAD_SIZE ((__SI_MAX_SIZE / sizeof (int)) - 4) CLD_TRAPPED CLD_TRAPPED NGREG __NGREG PARSE_OPT_LASTARG_DEFAULT PARSE_OPT_LIST_SUBCMDS cpu_to_le16  max(x,y) ({ typeof(x) _max1 = (x); typeof(y) _max2 = (y); (void) (&_max1 == &_max2); _max1 > _max2 ? _max1 : _max2; }) is_abbreviated PARSE_OPT_KEEP_DASHDASH roundup(x,y) ( { const typeof(y) __y = y; (((x) + (__y - 1)) / __y) * __y; } ) toupper(c) __tobody (c, toupper, *__ctype_toupper_loc (), (c)) ambiguous_option __PERF_ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) unknown options__order error_buf OPT_CALLBACK_OPTARG(s,l,v,d,a,h,f) { .type = OPTION_CALLBACK, .short_name = (s), .long_name = (l), .value = (v), .argh = (a), .help = (h), .callback = (f), .flags = PARSE_OPT_OPTARG, .data = (d) } BUILD_BUG_ON_INVALID(e) ((void)(sizeof((__force long)(e)))) OPT_INCR(s,l,v,h) { .type = OPTION_INCR, .short_name = (s), .long_name = (l), .value = check_vtype(v, int *), .help = (h) } parse_opt_type excl_opt be64_to_cpu bswap_64 check_vtype(v,type) ( BUILD_BUG_ON_ZERO(!__builtin_types_compatible_p(typeof(v), type)) + v ) __builtin_memmove ambiguous_flags optwarning PARSE_OPT_OPTARG __SUBCMD_PARSE_OPTIONS_H  PARSE_OPT_NOEMPTY subcommands strcasestr match OPTION_SET_PTR OPTION_BOOLEAN OPT__VERBOSITY(var) { OPTION_CALLBACK, 'v', "verbose", (var), NULL, "be more verbose", PARSE_OPT_NOARG, &parse_opt_verbosity_cb, 0 }, { OPTION_CALLBACK, 'q', "quiet", (var), NULL, "be more quiet", PARSE_OPT_NOARG, &parse_opt_verbosity_cb, 0 } arg_end PARSE_OPT_DISABLED OPT_ULONG(s,l,v,h) { .type = OPTION_ULONG, .short_name = (s), .long_name = (l), .value = check_vtype(v, unsigned long *), .help = (h) } cpu_to_le32  PARSE_OPT_NONEG shortopt round_down(x,y) ((x) & ~__round_mask(x, y)) __builtin___snprintf_chk defval internal_help PARSE_OPT_EXCLUSIVE parse_short_opt OPTION_GROUP get_arg PARSE_OPT_NOARG __TOOLS_LINUX_KERNEL_H  PARSE_OPT_NOBUILD _TOOLS_MATH_H  PARSE_OPT_KEEP_UNKNOWN OPT_CALLBACK_DEFAULT_NOOPT(s,l,v,a,h,f,d) { .type = OPTION_CALLBACK, .short_name = (s), .long_name = (l), .value = (v), .arg = (a), .help = (h), .callback = (f), .defval = (intptr_t)d, .flags = PARSE_OPT_LASTARG_DEFAULT | PARSE_OPT_NOARG} toupper_l(c,locale) __toupper_l ((c), (locale)) le64_to_cpu  BUILD_BUG_ON(condition) BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition) check_typos bswap_64(x) __bswap_64 (x) usage_with_options can_skip be16_to_cpu bswap_16 PARSE_OPT_KEEP_ARGV0 _LINUX_BUILD_BUG_H  parse_options_usage cpu_to_be64 bswap_64 _TOOLS_LINUX_CONTAINER_OF_H  BUG_ON(cond) assert(!(cond)) __vasprintf_chk usage_with_options_internal min_t(type,x,y) min((type)x, (type)y) parse_options_start option__cmp BUG() BUG_ON(1) OPT_BOOLEAN(s,l,v,h) { .type = OPTION_BOOLEAN, .short_name = (s), .long_name = (l), .value = check_vtype(v, bool *), .help = (h) } rest ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]) + __must_be_array(arr)) USAGE_OPTS_WIDTH 24 OPTION_BIT parse_options_end option__in_argv PARSE_OPT_STOP_AT_NON_OPTION __round_mask(x,y) ((__typeof__(x))((y)-1)) set_option_flag parse_long_opt bswap_16(x) __bswap_16 (x) be32_to_cpu bswap_32 OPT_STRING_OPTARG(s,l,v,a,h,d) { .type = OPTION_STRING, .short_name = (s), .long_name = (l), .value = check_vtype(v, const char **), .argh =(a), .help = (h), .flags = PARSE_OPT_OPTARG, .defval = (intptr_t)(d) } OPT_SHORT 1 OPT_CALLBACK(s,l,v,a,h,f) { .type = OPTION_CALLBACK, .short_name = (s), .long_name = (l), .value = (v), .argh = (a), .help = (h), .callback = (f) } OPTION_STRING max_t(type,x,y) max((type)x, (type)y) cpu_to_le64  OPT__QUIET(var) OPT_BOOLEAN('q', "quiet", (var), "be quiet") ASSERT_STRUCT_OFFSET(type,field,expected_offset) BUILD_BUG_ON_MSG(offsetof(type, field) != (expected_offset), "Offset of " #field " in " #type " has changed.") PARSE_OPT_HIDDEN clamp(val,lo,hi) min((typeof(val))max(val, lo), hi) tolower_l(c,locale) __tolower_l ((c), (locale)) container_of(ptr,type,member) ({ const typeof(((type *)0)->member) * __mptr = (ptr); (type *)((char *)__mptr - offsetof(type, member)); }) synchronize_rcu()  opterror OPT_STRING_OPTARG_SET(s,l,v,os,a,h,d) { .type = OPTION_STRING, .short_name = (s), .long_name = (l), .value = check_vtype(v, const char **), .argh = (a), .help = (h), .flags = PARSE_OPT_OPTARG, .defval = (intptr_t)(d), .set = check_vtype(os, bool *)} parse_opt_cb OPT_UINTEGER_OPTARG(s,l,v,d,h) { .type = OPTION_UINTEGER, .short_name = (s), .long_name = (l), .value = check_vtype(v, unsigned int *), .help = (h), .flags = PARSE_OPT_OPTARG, .defval = (intptr_t)(d) } OPTION_END BUILD_BUG_ON_MSG(cond,msg) compiletime_assert(!(cond), msg) min(x,y) ({ typeof(x) _min1 = (x); typeof(y) _min2 = (y); (void) (&_min1 == &_min2); _min1 < _min2 ? _min1 : _min2; }) parse_options_subcommand OPT_SET_UINT(s,l,v,h,i) { .type = OPTION_SET_UINT, .short_name = (s), .long_name = (l), .value = check_vtype(v, unsigned int *), .help = (h), .defval = (i) } PARSE_OPT_HELP OPT_LONG(s,l,v,h) { .type = OPTION_LONG, .short_name = (s), .long_name = (l), .value = check_vtype(v, long *), .help = (h) } OPT_CALLBACK_DEFAULT(s,l,v,a,h,f,d) { .type = OPTION_CALLBACK, .short_name = (s), .long_name = (l), .value = (v), .argh = (a), .help = (h), .callback = (f), .defval = (intptr_t)d, .flags = PARSE_OPT_LASTARG_DEFAULT } __isoc23_strtoull parse_options_step parse_opt_option_flags longopt full __toupper_l(c,locale) __tobody (c, __toupper_l, (locale)->__ctype_toupper, (c, locale)) OPTION_CALLBACK nr_group reason build_opt nr_parent PARSE_OPT_DONE callback ordered OPT_GROUP(h) { .type = OPTION_GROUP, .help = (h) } OPT_BOOLEAN_FLAG(s,l,v,h,f) { .type = OPTION_BOOLEAN, .short_name = (s), .long_name = (l), .value = check_vtype(v, bool *), .help = (h), .flags = (f) } OPTION_LONG OPT_UINTEGER(s,l,v,h) { .type = OPTION_UINTEGER, .short_name = (s), .long_name = (l), .value = check_vtype(v, unsigned int *), .help = (h) } parse_options parse_opt_verbosity_cb DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) OPTION_ULONG OPT_CALLBACK_SET(s,l,v,os,a,h,f) { .type = OPTION_CALLBACK, .short_name = (s), .long_name = (l), .value = (v), .argh = (a), .help = (h), .callback = (f), .set = check_vtype(os, bool *)} fputc OPT_UNSET 2 intptr_t OPTION_U64 tolower(c) __tobody (c, tolower, *__ctype_tolower_loc (), (c)) BUILD_BUG_ON_ZERO(e,...) __BUILD_BUG_ON_ZERO_MSG(e, ##__VA_ARGS__, #e " is true") excl_short_opt cpidx cpu_to_be32 bswap_32 round_up(x,y) ((((x)-1) | __round_mask(x, y))+1) nr_opts abbrev_flags OPT_SET_PTR(s,l,v,h,p) { .type = OPTION_SET_PTR, .short_name = (s), .long_name = (l), .value = (v), .help = (h), .defval = (p) } usage_with_options_msg _RET_IP_ ((unsigned long)__builtin_return_address(0)) OPT_CALLBACK_NOOPT(s,l,v,a,h,f) { .type = OPTION_CALLBACK, .short_name = (s), .long_name = (l), .value = (v), .argh = (a), .help = (h), .callback = (f), .flags = PARSE_OPT_NOARG } short_name OPT_INTEGER(s,l,v,h) { .type = OPTION_INTEGER, .short_name = (s), .long_name = (l), .value = check_vtype(v, int *), .help = (h) } cpu_to_be16 bswap_16 current_gfp_context(k) 0 argh BUILD_BUG_ON_NOT_POWER_OF_2(n) BUILD_BUG_ON((n) == 0 || (((n) & ((n) - 1)) != 0)) __int32_t unset PARSE_OPT_CANSKIP _TOOLS_LINUX_PANIC_H  OPT_STRING_NOEMPTY(s,l,v,a,h) { .type = OPTION_STRING, .short_name = (s), .long_name = (l), .value = check_vtype(v, const char **), .argh = (a), .help = (h), .flags = PARSE_OPT_NOEMPTY} print_option_help parse_opt_flags skip_prefix retry target OPTION_UINTEGER le16_to_cpu  bswap_32(x) __bswap_32 (x) OPT_BIT(s,l,v,h,b) { .type = OPTION_BIT, .short_name = (s), .long_name = (l), .value = check_vtype(v, int *), .help = (h), .defval = (b) } find_option PARSE_OPT_LIST_OPTS OPT_U64(s,l,v,h) { .type = OPTION_U64, .short_name = (s), .long_name = (l), .value = check_vtype(v, u64 *), .help = (h) } set_option_nobuild le32_to_cpu  OPTION_INCR usagestr parse_opt_ctx_t PERF_ALIGN(x,a) __PERF_ALIGN_MASK(x, (typeof(x))(a)-1) OPTION_ARGUMENT PARSE_OPT_UNKNOWN OPT__DRY_RUN(var) OPT_BOOLEAN('n', "dry-run", (var), "dry run") __ctype_tolower_loc UINT_MAX (~0U) OPTION_SET_UINT OPT_PARENT(p) { .type = OPTION_END, .parent = (p) } OPT_END() { .type = OPTION_END } OPT_ARGUMENT(l,h) { .type = OPTION_ARGUMENT, .long_name = (l), .help = (h) } OPT__VERBOSE(var) OPT_BOOLEAN('v', "verbose", (var), "be verbose") noarg USAGE_GAP 2 OPT__ABBREV(var) { OPTION_CALLBACK, 0, "abbrev", (var), "n", "use <n> digits to display SHA-1s", PARSE_OPT_OPTARG, &parse_opt_abbrev_cb, 0 } optstr get_value OPT_STRING(s,l,v,a,h) { .type = OPTION_STRING, .short_name = (s), .long_name = (l), .value = check_vtype(v, const char **), .argh = (a), .help = (h) } OPT_BOOLEAN_SET(s,l,v,os,h) { .type = OPTION_BOOLEAN, .short_name = (s), .long_name = (l), .value = check_vtype(v, bool *), .help = (h), .set = check_vtype(os, bool *)} __tolower_l(c,locale) __tobody (c, __tolower_l, (locale)->__ctype_tolower, (c, locale)) PARSE_OPT_NO_INTERNAL_HELP __BUILD_BUG_ON_NOT_POWER_OF_2(n) BUILD_BUG_ON(((n) & ((n) - 1)) != 0) abbrev_option OPT_DATE(s,l,v,h) { .type = OPTION_CALLBACK, .short_name = (s), .long_name = (l), .value = (v), .argh = "time", .help = (h), .callback = parse_opt_approxidate_cb } vasprintf long_name OPTION_INTEGER BUILD_BUG() BUILD_BUG_ON_MSG(1, "BUILD_BUG failed") O_DIRECT __O_DIRECT __path WAIT_ANY (-1) AT_NO_AUTOMOUNT 0x800 block waitpid RWH_WRITE_LIFE_MEDIUM 3 close_pair prepare_run_command_v_opt _LINUX_OPENAT2_H  ERR_RUN_COMMAND_FORK putenv O_NOATIME __O_NOATIME STRERR_BUFSIZE 128 SPLICE_F_MOVE 1 F_SEAL_WRITE 0x0008 LOCK_MAND 32 RWH_WRITE_LIFE_NOT_SET 0 F_CREATED_QUERY 1028 F_OFD_SETLK 37 WCOREFLAG __WCOREFLAG LOCK_READ 64 RWH_WRITE_LIFE_SHORT 2 SPLICE_F_MORE 4 dup_devnull MAX_HANDLE_SZ 128 ERR_RUN_COMMAND_WAITPID_SIGNAL DN_MODIFY 0x00000002 __sz fgets FALLOC_FL_WRITE_ZEROES 0x80 AT_STATX_FORCE_SYNC 0x2000 ERR_RUN_COMMAND_EXEC __open_2 RWF_WRITE_LIFE_NOT_SET RWH_WRITE_LIFE_NOT_SET FALLOC_FL_COLLAPSE_RANGE 0x08 F_SETPIPE_SZ 1031 W_STOPCODE(sig) __W_STOPCODE (sig) LOCK_WRITE 128 AT_STATX_SYNC_TYPE 0x6000 __iovec_defined 1 __open_alias SYNC_FILE_RANGE_WAIT_BEFORE 1 run_command ERR_RUN_COMMAND_PIPE F_SEAL_SHRINK 0x0002 FALLOC_FL_ALLOCATE_RANGE 0x00 FALLOC_FL_KEEP_SIZE 0x01 __idtype_t_defined  AT_RECURSIVE 0x8000 pipe DN_CREATE 0x00000004 F_GETLEASE 1025 SPLICE_F_GIFT 8 AT_EXECVE_CHECK 0x10000 __fgets_chk_warn AT_STATX_DONT_SYNC 0x4000 F_SETSIG __F_SETSIG F_SET_FILE_RW_HINT 1038 MAX_STRLEN_TYPE(type) (sizeof(type) * 8 / 3 + (is_signed_type(type) ? 1 : 0)) FALLOC_FL_UNSHARE_RANGE 0x40 ERR_RUN_COMMAND_WAITPID_NOEXIT F_ADD_SEALS 1033 WAIT_MYPGRP 0 F_OFD_SETLKW 38 O_PATH __O_PATH ERR_RUN_COMMAND_WAITPID is_signed_type(type) (((type)(-1)) < (type)1) LOCK_RW 192 DN_MULTISHOT 0x80000000 AT_HANDLE_CONNECTABLE 2 waiting RWH_WRITE_LIFE_NONE 1 need_in chdir need_err DN_ACCESS 0x00000001 need_out DN_DELETE 0x00000008 O_TMPFILE __O_TMPFILE AT_STATX_SYNC_AS_STAT 0x0000 F_SET_RW_HINT 1036 SYNC_FILE_RANGE_WAIT_AFTER 4 F_GET_SEALS 1034 RESOLVE_NO_MAGICLINKS 0x02 __open_missing_mode __open_too_many_args DN_RENAME 0x00000010 check_if_command_finished AT_EMPTY_PATH 0x1000 __fgets_alias RWH_WRITE_LIFE_LONG 4 F_GETSIG __F_GETSIG wait_or_whine FD_PIDFS_ROOT -10002 fderr __oflag SYNC_FILE_RANGE_WRITE 2 fdout __open64_2 RESOLVE_NO_XDEV 0x01 F_SETOWN_EX __F_SETOWN_EX _SYS_WAIT_H 1 __glibc_has_open_how 1 F_OFD_GETLK 36 ERR_RUN_COMMAND_WAITPID_WRONG_PID DN_ATTRIB 0x00000020 F_GET_RW_HINT 1035 RESOLVE_IN_ROOT 0x10 F_SETLEASE 1024 __fgets_chk _FALLOC_H_  __builtin___sprintf_chk WCOREDUMP(status) __WCOREDUMP (status) AT_HANDLE_MNT_ID_UNIQUE 1 F_SEAL_SEAL 0x0001 RWH_WRITE_LIFE_EXTREME 5 FALLOC_FL_ZERO_RANGE 0x10 F_SEAL_GROW 0x0004 FALLOC_FL_INSERT_RANGE 0x20 F_SEAL_EXEC 0x0020 status_line RESOLVE_NO_SYMLINKS 0x04 FALLOC_FL_NO_HIDE_STALE 0x04 F_SEAL_FUTURE_WRITE 0x0010 fdin unsetenv status_file F_GET_FILE_RW_HINT 1037 F_NOTIFY 1026 FALLOC_FL_PUNCH_HOLE 0x02 AT_HANDLE_FID AT_REMOVEDIR W_EXITCODE(ret,sig) __W_EXITCODE (ret, sig) F_DUPFD_QUERY 1027 F_GETOWN_EX __F_GETOWN_EX SYNC_FILE_RANGE_WRITE_AND_WAIT (SYNC_FILE_RANGE_WRITE | SYNC_FILE_RANGE_WAIT_BEFORE | SYNC_FILE_RANGE_WAIT_AFTER) SPLICE_F_NONBLOCK 2 RESOLVE_CACHED 0x20 F_GETPIPE_SZ 1032 RESOLVE_BENEATH 0x08 signals sigchain_push SIGCHAIN_MAX_SIGNALS 32 sigchain_signal __sighandler_t check_signum UNDEFINED "SUBCMD_HAS_NOT_BEEN_INITIALIZED" LL_DELTA (1 << 5) ET_CORE 4 EF_SPARCV9_MM 3 R_MIPS_CALL16 11 R_TILEGX_HW0 9 DT_PPC_NUM 2 AT_SYSINFO 32 EM_SLE9X 179 isascii(c) (((unsigned char)(c))<=0x7f) R_386_TLS_LDM_CALL 30 R_MN10300_NUM 35 R_TILEGX_IMM8_Y0_TLS_GD_ADD 115 EF_ARM_HASENTRY 0x02 R_METAG_LO16_GOTOFF 33 R_TILEGX_IMM16_X1_HW0_LAST_GOT 73 R_SPARC_16 2 R_SH_CODE 30 DT_MIPS_RLD_MAP_REL 0x70000035 ELF_NOTE_OS_FREEBSD 3 _X 0x40 R_MICROBLAZE_TLS 22 MIPS_AFL_ASE_MASK 0x00001fff R_RISCV_TLSDESC_CALL 65 PF_IA_64_NORECOV 0x80000000 MIPS_AFL_EXT_XLR 1 R_68K_TLS_GD8 27 R_68K_32 1 R_TILEGX_TLS_TPOFF32 111 NT_GNU_PROPERTY_TYPE_0 5 R_PPC64_JMP_SLOT R_PPC_JMP_SLOT R_PARISC_LTOFF_TP14WR 227 DT_PROCNUM DT_MIPS_NUM islower(c) ((__ismask(c)&(_L)) != 0) EF_ARM_VFP_FLOAT 0x400 R_TILEPRO_IMM8_Y1 20 R_IA64_DTPMOD64LSB 0xa7 R_X86_64_GOT32 3 R_PPC64_PLT16_HI R_PPC_PLT16_HI AT_EUID 12 GNU_PROPERTY_HIUSER 0xffffffff STT_NOTYPE 0 R_PPC_NONE 0 R_PPC_EMB_NADDR16_HI 104 R_SPARC_GOTDATA_OP_HIX22 82 R_386_GOTOFF 9 PPC64_OPT_MULTI_TOC 2 R_METAG_RELBRANCH 4 R_TILEGX_IMM16_X1_HW2_PCREL 55 SHT_HIUSER 0x8fffffff R_SPARC_GOTDATA_OP_LOX10 83 R_RISCV_RVC_JUMP 45 DT_GNU_LIBLISTSZ 0x6ffffdf7 DF_1_NODELETE 0x00000008 R_SPARC_TLS_LDM_CALL 63 R_PPC64_GOT_TLSGD16_LO 80 R_386_GOT32 3 R_TILEPRO_TLS_TPOFF32 84 EM_ARC 45 R_TILEPRO_DEST_IMM8_X1 55 SHF_ARM_COMDEF 0x80000000 DT_AUDIT 0x6ffffefc DT_MIPS_INTERFACE 0x7000002a EM_NORC 218 EM_R32C 162 R_AARCH64_LDST16_ABS_LO12_NC 284 GNU_PROPERTY_X86_ISA_1_USED 0xc0010002 EF_MIPS_ABI_EABI32 0x00003000 EM_PDP10 64 MIPS_AFL_ASE_EVA 0x00000004 R_AARCH64_TLS_DTPREL 1029 EM_M16C 117 R_ARM_ME_TOO 128 DT_MIPS_TIME_STAMP 0x70000002 R_AARCH64_TLSLE_MOVW_TPREL_G1_NC 546 NT_ARM_HW_BREAK 0x402 SHN_HIPROC 0xff1f R_METAG_HIADDR16 0 R_IA64_DTPREL64LSB 0xb7 R_TILEPRO_IMM16_X0_TLS_GD_HI 70 R_CKCORE_TLS_LE32 51 EF_CSKY_ABIV2 0X20000000 SHF_LINK_ORDER (1 << 7) R_MIPS16_TLS_DTPREL_HI16 108 R_TILEGX_IMM16_X1_HW2_LAST_PCREL 63 R_CKCORE_PCREL_IMM26BY2 19 EM_UNICORE 110 PN_XNUM 0xffff EM_SPARC32PLUS 18 R_390_JMP_SLOT 11 R_LARCH_TLS_IE_HI20 91 R_MIPS_HI16 5 R_PARISC_LORESERVE 128 R_ARC_S21H_PCREL_PLT 0x4D R_ARC_24 0x3 R_PPC64_SECTOFF_LO_DS 62 R_MIPS_26 4 R_PARISC_GNU_VTINHERIT 233 R_PPC64_NONE R_PPC_NONE R_SPARC_HI22 9 NT_LOONGARCH_LSX 0xa02 R_CKCORE_TLS_TPOFF32 58 R_LARCH_ADD6 105 R_OR1K_TLS_IE_HI16 28 ispunct(c) ((__ismask(c)&(_P)) != 0) R_CKCORE_GOTPC_HI16 26 R_BPF_64_64 1 R_PPC_SDAREL16 32 R_LARCH_SOP_PUSH_PLT_PCREL 29 DT_BIND_NOW 24 MIPS_AFL_ASE_DSP 0x00000001 R_SPARC_SIZE64 87 EM_INTELGT 205 R_TILEPRO_IMM16_X1_HI 28 R_68K_TLS_DTPMOD32 40 R_MN10300_TLS_LE 29 EM_ECOG16 176 R_AARCH64_RELATIVE 1027 R_IA64_DTPREL14 0xb1 R_BPF_64_32 10 R_MIPS_CALL_HI16 30 SHT_REL 9 R_AARCH64_ABS32 258 R_ARM_THM_JUMP24 30 AT_UCACHEBSIZE 21 R_ARM_ALU_SB_G1_NC 72 R_IA64_SUB 0x85 EF_MIPS_MACH_IAMR2 0x00930000 R_IA64_SECREL64MSB 0x66 NT_PPC_SPE 0x101 R_PARISC_TPREL14R 158 R_PARISC_PCREL17R 11 R_ARC_SDA16_LD1 0x17 R_X86_64_GOTPC32 26 PT_PARISC_UNWIND 0x70000001 R_MICROMIPS_HIGHER 151 EM_68HC16 69 NT_PSINFO 13 R_PARISC_PLTOFF16DF 119 R_TILEGX_IMM16_X0_HW0_LAST_GOT 72 EM_H8_300H 47 OHW_R8KPFETCH 0x2 R_ARM_ABS12 6 _GCC_MAX_ALIGN_T  DF_1_GLOBAUDIT 0x01000000 R_386_TLS_LDO_32 32 R_PARISC_TPREL64 216 R_ARM_ALU_SB_G1 73 R_ARC_PLT32 0x34 R_390_TLS_GDCALL 38 EM_KM32 210 R_MICROMIPS_HI0_LO16 157 EF_SPARCV9_TSO 0 AT_NOTELF 10 R_OR1K_TLS_GD_HI16 22 SHN_XINDEX 0xffff R_TILEGX_IMM16_X1_HW1_LAST_TLS_GD 89 R_METAG_TLS_GD 47 R_ALPHA_DTPREL64 33 EF_PPC_RELOCATABLE_LIB 0x00008000 R_M32R_RELA_GNU_VTENTRY 44 EI_ABIVERSION 8 R_PPC64_TPREL16_HIGHESTA 100 EM_ST9PLUS 67 toascii(c) (((unsigned char)(c))&0x7f) R_IA64_FPTR64LSB 0x47 LL_DELAY_LOAD (1 << 4) R_AARCH64_NONE 0 DT_PLTGOT 3 R_CKCORE_GLOB_DAT 11 R_AARCH64_MOVW_SABS_G1 271 R_IA64_PCREL64I 0x7b symbol_name R_X86_64_GOTTPOFF 22 R_SPARC_WDISP10 88 VER_DEF_CURRENT 1 MIPS_AFL_REG_32 0x01 R_IA64_LTOFF22 0x32 R_TILEPRO_IMM16_X1_TLS_GD_LO 69 R_TILEGX_IMM16_X1_HW0_GOT 65 R_ARM_RSBREL32 250 R_TILEGX_IMM16_X1_HW0 37 EF_MIPS_XGOT 8 R_PPC_GOT_DTPREL16_HI 93 R_PPC_ADDR16_LO 4 NT_VMCOREDD 0x700 NT_ARM_FPMR 0x40e R_M32R_NONE 0 R_ARM_THM_MOVT_BREL 88 R_MN10300_PCREL8 6 R_AARCH64_MOVW_GOTOFF_G3 306 R_PARISC_TLS_DTPOFF64 245 R_PPC64_TPREL16_LO_DS 96 R_MICROMIPS_GOT_HI16 148 ELF64_R_SYM(i) ((i) >> 32) DF_STATIC_TLS 0x00000010 R_SPARC_TLS_LDO_ADD 66 EF_ARM_EABI_VER1 0x01000000 EM_M32 1 R_RISCV_BRANCH 16 R_68K_GOT16O 11 MIPS_AFL_EXT_3900 10 NT_PPC_TM_CTAR 0x10d DF_1_EDITED 0x00200000 R_68K_PLT8 15 R_386_TLS_DESC_CALL 40 R_TILEPRO_IMM8_Y0_TLS_GD_ADD 63 EM_XIMO16 170 R_PARISC_PCREL14DR 76 NT_ARM_PACG_KEYS 0x408 R_PARISC_SEGREL32 49 R_TILEGX_IMM16_X0_HW0_PCREL 50 DT_GNU_HASH 0x6ffffef5 R_TILEPRO_IMM16_X1_PCREL 32 PPC64_LOCAL_ENTRY_OFFSET(other) (((1 << (((other) & STO_PPC64_LOCAL_MASK) >> STO_PPC64_LOCAL_BIT)) >> 2) << 2) NT_X86_XSTATE 0x202 R_PPC_EMB_RELST_HI 113 R_NDS32_32_RELA 20 EM_XTENSA 94 ELFOSABI_NONE 0 R_LARCH_PCALA64_LO20 73 R_OR1K_TLS_TPOFF 32 DT_MIPS_OPTIONS 0x70000029 ELF64_ST_BIND(val) ELF32_ST_BIND (val) R_M32R_SDA16 10 R_TILEGX_HW3 12 R_ARC_S21W_PCREL 0xF R_AARCH64_TLSLE_LDST64_TPREL_LO12 558 R_PPC_RELATIVE 22 R_PARISC_DIR16F 85 R_PPC_GOT_TLSGD16_HA 82 R_MIPS_HIGHEST 29 R_PPC_GOT_TLSGD16 79 R_ALPHA_DTPMOD64 31 R_PPC_EMB_MRKREF 110 tolower(c) __tolower(c) SHT_PARISC_DOC 0x70000002 EF_ARM_NEW_ABI 0x80 R_NIOS2_TLS_DTPREL 34 R_AARCH64_TLSLE_ADD_TPREL_HI12 549 R_LARCH_JUMP_SLOT 5 EM_SE_C33 107 R_NIOS2_IMM6 7 DT_MIPS_DELTA_SYM 0x7000001d R_PPC64_PLT64 45 STT_OBJECT 1 R_68K_GOT32O 10 R_AARCH64_TLSLD_LDST8_DTPREL_LO12 531 AT_L1I_CACHESIZE 40 SHF_ARM_ENTRYSECT 0x10000000 MIPS_AFL_FLAGS1_ODDSPREG 1 R_M32R_GOTPC_HI_SLO 60 GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS (1U << 0) R_BPF_NONE 0 SHF_PARISC_SHORT 0x20000000 R_PPC64_PLTREL64 46 R_RISCV_SET16 55 R_ARC_S25H_PCREL_PLT 0x3D ODK_HWOR 8 R_ARM_TLS_LDO12 109 R_MICROBLAZE_NONE 0 SHT_GNU_ATTRIBUTES 0x6ffffff5 R_ARM_GOT_ABS 95 R_TILEGX_IMM16_X1_HW0_TLS_GD 79 EM_XCORE 203 R_RISCV_PLT32 59 R_PARISC_PLABEL14R 70 DT_FILTER 0x7fffffff R_NIOS2_CALL26 4 R_SPARC_TLS_LDM_HI22 60 R_ARC_S21H_PCREL 0xE R_TILEGX_NUM 130 EF_MIPS_ARCH_32R2 0x70000000 R_ARM_TLS_DTPMOD32 17 R_AARCH64_MOVW_PREL_G0_NC 288 EM_SE_C17 139 PT_HP_CORE_LOADABLE (PT_LOOS + 0x6) R_X86_64_TLSGD 19 R_TILEPRO_IMM8_X1 19 R_PPC64_GOT_TLSGD16_HI 81 EM_AARCH64 183 R_TILEGX_DEST_IMM8_X1 27 R_LARCH_SOP_SL 33 R_IA64_SECREL32LSB 0x65 EF_SH3E 0x8 LL_EXPORTS (1 << 3) R_ARM_ALU_SB_G0_NC 70 R_PPC_REL14 11 DT_MIPS_ICHECKSUM 0x70000003 R_PPC_ADDR32 1 PT_GNU_RELRO 0x6474e552 R_IA64_FPTR64I 0x43 R_RISCV_TLS_DTPREL32 8 R_ARM_ABS32_NOI 55 R_RISCV_32 1 R_PPC64_DTPREL64 78 EM_SPARCV9 43 R_TILEPRO_IMM16_X1 24 EF_ARM_ALIGN8 0x40 DT_PPC64_OPT (DT_LOPROC + 3) VER_DEF_NONE 0 NT_PPC_DEXCR 0x111 R_ARM_THM_PC22 10 MIPS_AFL_ASE_XPA 0x00001000 DT_MIPS_NUM 0x37 NT_S390_VXRS_LOW 0x309 R_ARM_MOVW_ABS_NC 43 R_LARCH_SUB32 55 OEX_FPU_DIV0 0x08 R_M32R_26_PCREL 6 R_MIPS16_TLS_TPREL_LO16 112 NT_LOONGARCH_HW_WATCH 0xa06 __toupper OHW_R4KEOP 0x1 R_PARISC_LTOFF_TP16F 229 R_CRIS_16 2 R_SPARC_NUM 253 DT_SYMINENT 0x6ffffdff EF_MIPS_MACH_4100 0x00830000 EF_RISCV_FLOAT_ABI_SOFT 0x0000 R_X86_64_PC8 15 R_PARISC_GPREL21L 26 R_X86_64_TLSDESC 36 kallsyms__is_function OEX_FPU_MAX 0x1f00 R_MIPS16_PC16_S1 113 R_ARM_SWI24 13 R_MN10300_PCREL32 4 R_MIPS16_HI16 104 R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC 525 R_PPC64_REL32 R_PPC_REL32 DT_MIPS_LOCALPAGE_GOTIDX 0x70000025 R_PPC_REL14_BRNTAKEN 13 R_MICROBLAZE_TLSTPREL32 29 RHF_PIXIE (1 << 8) R_ARC_NONE 0x0 R_390_TLS_GOTIE12 42 DT_ALPHA_PLTRO (DT_LOPROC + 0) STT_PARISC_MILLICODE 13 R_MICROMIPS_TLS_TPREL_HI16 169 R_CKCORE_ADDR_LO16 25 EV_NONE 0 R_CKCORE_DOFFSET_IMM18 44 R_PARISC_TPREL21L 154 PF_HP_NEAR_SHARED 0x00400000 DT_MIPS_DELTA_CLASS_NO 0x70000018 R_MICROBLAZE_64_PCREL 3 kallsyms__parse ELFCOMPRESS_ZSTD 2 R_PPC64_DTPREL16_HIGHERA 104 EM_VPP500 17 _L 0x02 R_METAG_GETSET_GOT 35 R_PPC64_GOT16_LO_DS 59 STT_NUM 7 R_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL 98 EM_FT32 222 AT_L2_CACHESIZE 44 R_ARM_MOVW_PREL_NC 45 R_AARCH64_TLSLD_MOVW_DTPREL_G1 524 OEX_FPU_MIN 0x1f R_MICROMIPS_GOT_PAGE 146 R_MIPS_TLS_DTPREL64 41 R_AARCH64_LD64_GOTPAGE_LO15 313 R_PPC_REL14_BRTAKEN 12 R_CRIS_8 1 SHF_MIPS_ADDR 0x40000000 NT_ARM_SVE 0x405 R_IA64_TPREL64LSB 0x97 R_ARC_NPS_CMEM16 0x4E PF_PARISC_SBP 0x08000000 EM_OPEN8 196 R_IA64_PLTOFF22 0x3a EF_ARM_EABI_VER3 0x03000000 EF_SPARC_SUN_US1 0x000200 AT_HWCAP 16 R_TILEPRO_IMM16_X0_LO_PCREL 33 R_METAG_TLS_IENONPIC 53 STB_GLOBAL 1 R_PARISC_PCREL21L 10 ELFCOMPRESS_LOPROC 0x70000000 R_AARCH64_TLSIE_LD_GOTTPREL_PREL19 543 R_390_GOTPLT16 30 R_IA64_PCREL21B 0x49 SHF_OS_NONCONFORMING (1 << 8) AT_FPUCW 18 DT_MIPS_DELTA_CLASSSYM 0x70000020 R_PPC64_ADDR16_LO_DS 57 R_TILEPRO_TLS_GD_CALL 60 R_CRIS_16_GOT 13 R_390_GOT64 24 NT_ARM_HW_WATCH 0x403 R_ARM_ALU_PC_G1 60 R_AC_SECTOFF_U8_2 0x25 R_IA64_LTOFF_FPTR64LSB 0x57 R_MIPS_PJUMP 35 R_TILEGX_COPY 16 NT_GWINDOWS 7 SHT_LOPROC 0x70000000 EM_MAX 102 R_PPC64_REL14 R_PPC_REL14 R_SPARC_PLT64 47 R_AARCH64_CONDBR19 280 R_TILEPRO_MMEND_X0 48 R_MICROBLAZE_JUMP_SLOT 17 R_RISCV_CALL_PLT 19 R_ARC_TLS_GD_GOT 0x45 R_ARM_BASE_ABS 31 R_LARCH_GOT64_PC_LO20 77 ELFOSABI_GNU 3 R_ARM_THM_MOVW_ABS_NC 47 STT_SECTION 3 R_X86_64_GOTPLT64 30 R_SH_DATA 31 R_68K_8 3 MIPS_AFL_EXT_4650 7 SHT_ALPHA_DEBUG 0x70000001 RHF_GUARANTEE_INIT (1 << 5) R_TILEGX_32_PCREL 6 R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 539 EF_MIPS_ARCH_ASE_M16 0x04000000 R_ARM_TARGET1 38 DT_VALRNGHI 0x6ffffdff SHT_SHLIB 10 EM_88K 5 R_M32R_GOTPC_LO 61 R_ARM_ALU_PCREL_15_8 33 DF_1_SINGLETON 0x02000000 R_PPC_TPREL16 69 R_OR1K_TLS_DTPMOD 34 EM_OPENRISC 92 NT_PRXFPREG 0x46e62b7f R_CKCORE_TLS_GD32 53 R_M32R_24 3 NT_PPC_PMU 0x107 R_X86_64_NUM 43 MIPS_AFL_ASE_MIPS3D 0x00000020 NT_X86_SHSTK 0x204 R_TILEPRO_IMM16_X1_TLS_GD 67 R_PPC_DTPREL16_HA 77 R_CKCORE_PCREL32 5 R_68K_TLS_LE8 39 R_68K_RELATIVE 22 R_ARM_XPC25 15 R_PPC64_TPREL16_LO 70 R_ARM_AMP_VCALL9 12 R_PPC64_DTPREL16_HA 77 EF_SH2 0x2 R_SH_TLS_DTPMOD32 149 R_CKCORE_TLS_LDM32 54 SHT_X86_64_UNWIND 0x70000001 R_PPC_GOT16 14 R_ARM_TLS_LE32 108 R_LARCH_SUB8 52 R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC 536 R_PARISC_LTOFF16F 101 R_MICROBLAZE_TLSLD 24 DT_PREINIT_ARRAYSZ 33 R_TILEPRO_IMM16_X1_TLS_IE 75 R_ALPHA_SREL64 11 EM_CLOUDSHIELD 192 R_METAG_GLOB_DAT 46 R_M32R_GOTOFF_HI_SLO 63 SHF_STRINGS (1 << 5) R_MIPS16_CALL16 103 R_68K_GOT8O 12 R_386_TLS_TPOFF 14 AT_L1I_CACHESHAPE 34 R_TILEPRO_IMM16_X1_GOT 40 MIPS_AFL_EXT_SB1 12 R_ARC_COPY 0x35 R_NIOS2_GOTOFF_HA 25 R_ARM_THM_GOT_BREL12 131 EM_VAX 75 SHT_GNU_verneed 0x6ffffffe R_MICROBLAZE_GOT_64 14 R_PARISC_GPREL64 88 R_PPC64_TPREL16_HIGHERA 98 R_AC_SECTOFF_S9_2 0x28 DF_P1_GROUPPERM 0x00000002 R_LARCH_64_PCREL 109 R_TILEGX_JMP_SLOT 18 SHT_MIPS_DWARF 0x7000001e SHT_GNU_LIBLIST 0x6ffffff7 R_ARM_LDC_SB_G1 82 R_MIPS_GNU_VTINHERIT 253 R_TILEGX_IMM16_X0_HW0_PLT_PCREL 66 R_LARCH_TLS_GD_PC_HI20 97 R_TILEGX_IMM8_Y1_TLS_GD_ADD 116 EM_VIDEOCORE 95 R_PPC64_ADDR16_HIGHER 39 R_CRIS_RELATIVE 12 STT_FILE 4 R_MN10300_TLS_TPOFF 32 R_ARM_ALU_PCREL_23_15 34 NT_S390_TIMER 0x301 R_TILEGX_HW1_LAST 14 NT_VERSION 1 R_LARCH_SOP_POP_32_S_0_10_10_16_S2 45 R_PARISC_EPLT 130 PT_HP_CORE_KERNEL (PT_LOOS + 0x3) R_PPC_DIAB_RELSDA_LO 183 R_68K_PC8 6 R_PPC64_TOC16_LO_DS 64 EF_SH2A_SH4_NOFPU 0x15 R_AARCH64_TLSLE_MOVW_TPREL_G1 545 R_TILEPRO_RELATIVE 13 R_390_TLS_TPOFF 56 R_MICROBLAZE_64 5 EF_MIPS_MACH_3900 0x00810000 SHT_MIPS_LOCSTR 0x70000018 R_ARC_H30_ME 0x20 R_PARISC_DPREL21L 18 STN_UNDEF 0 R_ARM_CALL 28 ELF64_ST_INFO(bind,type) ELF32_ST_INFO ((bind), (type)) _LINUX_CTYPE_H  PT_AARCH64_MEMTAG_MTE (PT_LOPROC + 2) R_ARC_SDA32 0x12 R_LARCH_ABS64_HI12 70 EF_SH2A 0xd R_METAG_TLS_IENONPIC_LO16 55 R_PPC_DTPREL16 74 EF_ARM_EABI_VER5 0x05000000 R_PPC_REL16_HA 252 R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC 542 EI_MAG3 3 R_LARCH_GOT_PC_LO12 76 R_RISCV_RELAX 51 R_IA64_DTPREL64I 0xb3 SHN_UNDEF 0 STT_COMMON 5 R_68K_PC32 4 EM_56800EX 200 R_PPC64_GOT_TPREL16_HA 90 EF_MIPS_MACH_OCTEON 0x008b0000 EF_CSKY_OTHER 0X0FFF0000 NT_PRPSINFO 3 R_TILEGX_IMM16_X1_HW0_PLT_PCREL 67 R_PPC_GOT_TLSLD16_HA 86 R_PPC_TLSGD 95 EM_68HC05 72 SHT_MIPS_PACKAGE 0x70000007 R_AARCH64_PREL16 262 R_CKCORE_ADDRPLT_LO16 39 EF_MIPS_MACH_SB1 0x008a0000 R_68K_TLS_LDO16 32 PT_HP_HSL_ANNOT (PT_LOOS + 0x13) EM_MAXQ30 169 R_METAG_LO16_GOTPC 37 GNU_PROPERTY_HIPROC 0xdfffffff R_AARCH64_MOVW_PREL_G0 287 R_PARISC_LTOFF14DR 100 R_CKCORE_PCRELJSR_IMM11BY2 6 GNU_PROPERTY_X86_ISA_1_V3 (1U << 2) DT_PLTREL 20 R_PARISC_PLTOFF16F 117 R_LARCH_32 1 PPC_OPT_TLS 1 R_MICROMIPS_CALL_LO16 154 R_MN10300_ALIGN 34 R_LARCH_TLS_DTPREL64 9 EM_NUM 259 MIPS_AFL_ASE_VIRT 0x00000100 R_ARM_JUMP_SLOT 22 R_PPC_EMB_NADDR16_LO 103 EM_SNP1K 99 NT_ARM_PACA_KEYS 0x407 DT_MIPS_SYMTABNO 0x70000011 EF_PPC64_ABI 3 LL_EXACT_MATCH (1 << 0) EF_MIPS_ABI_ON32 64 EM_RX 173 R_LARCH_ADD_ULEB128 107 EF_PARISC_TRAPNIL 0x00010000 R_IA64_PLTOFF64LSB 0x3f R_X86_64_SIZE64 33 R_390_GOT20 58 RHF_NOTPOT (1 << 1) R_PPC64_TOC16_LO 48 R_AARCH64_MOVW_UABS_G2_NC 268 R_LARCH_CFA 104 R_MIPS_SHIFT5 16 R_AARCH64_PREL32 261 R_RISCV_64 2 DF_1_NORELOC 0x00400000 R_CKCORE_ADDRPLT 18 R_SPARC_WDISP22 8 SHT_INIT_ARRAY 14 EF_ARM_DYNSYMSUSESEGIDX 0x08 R_PPC_TLS 67 R_CKCORE_PCREL_IMM16BY4 21 EF_MIPS_FP64 512 R_SPARC_PC22 17 R_ALPHA_NONE 0 AT_MINSIGSTKSZ 51 R_TILEPRO_8 3 R_PPC_GOT_DTPREL16 91 R_ALPHA_GOTTPREL 37 R_ARC_GOTPC32 0x33 DT_GNU_PRELINKED 0x6ffffdf5 R_AARCH64_MOVW_GOTOFF_G1_NC 303 DF_SYMBOLIC 0x00000002 R_ARM_LDR_SB_G2 77 R_NIOS2_TLS_LDM16 29 R_PARISC_LTOFF_TP21L 162 ODK_NULL 0 R_SPARC_GOTDATA_OP 84 R_NIOS2_GOT_LO 42 DT_MIPS_RLD_VERSION 0x70000001 R_PPC64_TPREL16_HIGH 112 DT_FINI_ARRAY 26 R_MN10300_GOTOFF32 12 R_OR1K_32_PCREL 9 SHT_MIPS_DENSE 0x70000013 PT_HIPROC 0x7fffffff EI_NIDENT (16) ODK_HWPATCH 4 SHT_MIPS_PDR_EXCEPTION 0x70000029 EF_RISCV_RVC 0x0001 R_MIPS_LO16 6 R_AARCH64_LD64_GOT_LO12_NC 312 SHN_BEFORE 0xff00 EM_ARM 40 R_X86_64_DTPOFF64 17 R_M32R_COPY 50 ELFMAG "\177ELF" SHT_IA_64_EXT (SHT_LOPROC + 0) R_TILEGX_HW2_LAST 15 R_TILEPRO_TLS_DTPMOD32 82 DF_1_NOW 0x00000001 R_RISCV_ADD16 34 R_ARM_TARGET2 41 R_PPC64_TOCSAVE 109 R_SPARC_L44 52 EM_METAG 174 R_MIPS_TLS_DTPREL32 39 LL_NONE 0 R_RISCV_SUB32 39 PT_GNU_EH_FRAME 0x6474e550 R_ARM_TLS_IE32 107 NT_ARM_ZT 0x40d RHF_NO_LIBRARY_REPLACEMENT (1 << 2) EF_PARISC_LSB 0x00040000 R_ALPHA_DTPRELLO 35 R_MIPS_PC16 10 DT_PLTPAD 0x6ffffefd R_68K_NONE 0 R_X86_64_TLSDESC_CALL 35 R_IA64_PCREL64MSB 0x4e R_MICROBLAZE_GOTPC_64 13 R_390_GOTPLT64 32 DT_VALNUM 12 R_MN10300_TLS_GOTIE 27 EM_ARC_A5 EM_ARC_COMPACT R_SPARC_PLT32 24 R_IA64_REL64MSB 0x6e R_METAG_JMP_SLOT 44 R_LARCH_TLS_DTPMOD32 6 GNU_PROPERTY_AARCH64_FEATURE_1_GCS (1U << 2) R_LARCH_ADD16 48 R_PPC64_TPREL16_HI 71 R_PPC64_ADDR30 37 EM_CRX 114 VER_FLG_BASE 0x1 R_PPC_TPREL16_LO 70 R_SPARC_TLS_LDM_LO10 61 DT_CONFIG 0x6ffffefa PF_HP_SBP 0x08000000 DF_1_IGNMULDEF 0x00040000 SHT_MIPS_CONFLICT 0x70000002 R_ARM_THM_TLS_CALL 93 R_M32R_GOTPC24 55 R_TILEGX_IMM16_X1_HW3 43 R_TILEGX_IMM8_X1 25 R_TILEPRO_IMM16_X1_GOT_LO 42 R_68K_GOT8 9 DF_1_NODIRECT 0x00020000 EM_STM8 186 R_ARC_N24 0xA R_IA64_SEGREL64LSB 0x5f R_RISCV_SET6 53 R_ALPHA_GPRELHIGH 17 EM_FX66 66 NT_PPC_PPR 0x104 R_TILEPRO_IMM8_X1_TLS_GD_ADD 62 STO_MIPS_DEFAULT 0x0 R_TILEPRO_32_PCREL 4 R_PPC64_SECTOFF_DS 61 R_IA64_LTOFF_TPREL22 0x9a R_PARISC_TLS_TPREL64 R_PARISC_TPREL64 R_TILEGX_IMM16_X0_HW2 40 EF_SH4_NOFPU 0x10 NT_S390_PV_CPU_DATA 0x30e R_SPARC_UA64 54 SHF_EXECINSTR (1 << 2) R_LARCH_TLS_IE64_LO20 93 OEX_FPU_INVAL 0x10 R_MIPS_COPY 126 R_TILEPRO_JOFFLONG_X1_PLT 16 R_ARC_TLS_DTPOFF_S9 0x49 R_390_PLTOFF64 36 R_PPC_DIAB_RELSDA_HA 185 EF_SPARCV9_RMO 2 NT_386_IOPERM 0x201 EF_PPC_EMB 0x80000000 DT_RELA 7 R_IA64_IMM64 0x23 R_LARCH_GOT_LO12 80 R_X86_64_PC32 2 DT_NUM 38 R_TILEGX_IMM16_X1_HW1_LAST 47 R_TILEPRO_IMM16_X1_LO 26 SYMINFO_FLG_DIRECT 0x0001 EF_SPARCV9_PSO 1 R_MICROBLAZE_64_NONE 9 R_RISCV_LO12_I 27 SHT_GNU_versym 0x6fffffff R_TILEPRO_IMM16_X0_GOT_HA 45 DT_MIPS_DELTA_INSTANCE_NO 0x7000001a R_390_12 2 MIPS_AFL_REG_64 0x02 R_MIPS_GPREL16 7 EM_AMDGPU 224 R_CKCORE_PCREL_JSR_IMM26BY2 40 R_M32R_GOT16_HI_ULO 56 DT_VERSYM 0x6ffffff0 R_ARM_ABS16 5 R_386_TLS_TPOFF32 37 R_X86_64_COPY 5 EF_RISCV_FLOAT_ABI 0x0006 R_PPC_EMB_RELSEC16 111 R_MIPS_GLOB_DAT 51 R_PPC64_GOT16 R_PPC_GOT16 DT_TLSDESC_GOT 0x6ffffef7 R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC 534 R_CKCORE_GOTOFF_HI16 28 R_X86_64_PLTOFF64 31 R_ARM_LDC_PC_G1 68 R_SH_NONE 0 R_METAG_GNU_VTENTRY 31 PF_HP_PAGE_SIZE 0x00100000 R_390_GOTPLT12 29 R_PPC_GOT_TPREL16_LO 88 R_ALPHA_SREL16 9 R_TILEPRO_32 1 R_ARC_SECTOFF_ME_1 0x29 EM_MICROBLAZE 189 ODK_TAGS 6 EF_ARM_MAPSYMSFIRST 0x10 DT_RELAENT 9 R_CKCORE_GOT32 15 R_PPC_REL24 10 DT_AARCH64_PAC_PLT (DT_LOPROC + 3) R_PPC_EMB_SDA21 109 R_LARCH_NONE 0 EM_TMM_GPP 96 R_TILEGX_TLS_TPOFF64 108 R_MN10300_PLT16 16 R_PPC64_DTPREL16_HIGHESTA 106 EM_SPU 23 R_ARM_LDC_PC_G2 69 __TOOLS_KALLSYMS_H_ 1 R_CKCORE_PLT_IMM18BY4 49 R_68K_GOT16 8 R_RISCV_TLSDESC_LOAD_LO12 63 EM_IP2K 101 EM_CDP 215 AT_NULL 0 R_ARC_SECTOFF_1 0x2B EI_VERSION 6 R_PPC_GLOB_DAT 20 R_METAG_REG16OP1 9 R_TILEPRO_IMM16_X1_LO_PCREL 34 R_ARC_TLS_GD_CALL 0x47 EF_MIPS_ABI_EABI64 0x00004000 R_RISCV_RELATIVE 3 R_PPC64_REL24 R_PPC_REL24 R_ALPHA_SREL32 10 R_TILEGX_IMM16_X1_HW0_LAST 45 R_AARCH64_TLSLD_ADD_LO12_NC 519 R_PPC64_GOT_TPREL16_HI 89 R_ARM_THM_MOVT_ABS 48 R_ARM_TLS_DESCSEQ 92 EF_MIPS_CPIC 4 R_CKCORE_DOFFSET_LO16 42 R_AC_SECTOFF_U8_1 0x24 R_TILEPRO_JOFFLONG_X1 15 AT_HWCAP2 26 R_TILEGX_NONE 0 EM_ST19 74 R_TILEPRO_IMM16_X0_GOT 39 R_LARCH_TLS_DESC_PC_HI20 111 R_RISCV_JUMP_SLOT 5 R_CRIS_COPY 9 R_390_TLS_DTPMOD 54 R_ARM_THM_ALU_PREL_11_0 53 R_MICROMIPS_LO16 135 R_MIPS_GOT_LO16 23 NT_S390_SYSTEM_CALL 0x307 R_PPC64_ADDR16_DS 56 STV_HIDDEN 2 EM_NCPU 56 R_PARISC_IPLT 129 R_TILEGX_GNU_VTENTRY 129 R_CKCORE_PCRELIMM8BY4 2 R_PARISC_TLS_LDM14R 238 R_PPC64_REL16 249 R_386_TLS_DESC 41 ELFOSABI_AIX 7 R_LARCH_TLS_DESC_LO12 116 R_PPC64_TOC16_HI 49 R_IA64_REL32LSB 0x6d NT_SIGINFO 0x53494749 SHF_ALLOC (1 << 1) R_AARCH64_TLSLD_LDST128_DTPREL_LO12_NC 573 R_LARCH_ADD32 50 SHT_MIPS_EXTSYM 0x70000012 R_ARC_S25W_PCREL 0x11 R_SH_IND12W 4 R_MN10300_GNU_VTINHERIT 7 R_AARCH64_TLSLE_LDST16_TPREL_LO12 554 R_ARM_MOVT_PREL 46 R_X86_64_DTPMOD64 16 R_TILEGX_IMM16_X0_HW0_TLS_GD 78 PT_GNU_PROPERTY 0x6474e553 R_CKCORE_PCREL_IMM10BY2 22 PT_SHLIB 5 KSYM_NAME_LEN 512 NT_PPC_EBB 0x106 R_AARCH64_TLSLD_MOVW_DTPREL_G2 523 R_MIPS_TLS_GOTTPREL 46 R_LARCH_TLS_IE64_PC_HI12 90 R_ARC_GOTOFF 0x39 R_AC_SECTOFF_U8 0x23 R_ARM_GOTOFF12 98 R_LARCH_SOP_ASSERT 30 EM_C166 116 MIPS_AFL_EXT_10000 11 R_PPC64_ADDR14 R_PPC_ADDR14 R_PARISC_TLS_GDCALL 236 R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO R_OR1K_NONE 0 R_M32R_16 1 EM_PDSP 63 R_TILEGX_IMM16_X0_HW1_PLT_PCREL 68 R_SH_SWITCH8 33 EF_MIPS_MACH 0x00FF0000 R_TILEPRO_SHAMT_X0 51 R_TILEPRO_IMM16_X0_TLS_GD_HA 72 NT_FILE 0x46494c45 SHF_EXCLUDE (1U << 31) R_390_20 57 R_MN10300_GOTPC32 10 R_CKCORE_ADDRGOT_LO16 37 isgraph(c) ((__ismask(c)&(_P|_U|_L|_D)) != 0) R_RISCV_COPY 4 OPAD_PREFIX 0x1 R_68K_TLS_LDM8 30 R_METAG_TLS_IENONPIC_HI16 54 R_68K_TLS_LE32 37 R_ARM_LDR_PC_G2 63 SHF_ORDERED (1 << 30) R_CKCORE_TLS_IE32 52 EM_ALPHA 0x9026 R_CKCORE_JUMP_SLOT 12 R_ARM_THM_TLS_DESCSEQ16 129 R_TILEPRO_16_PCREL 5 R_ARC_TLS_DTPOFF 0x43 R_AC_SECTOFF_S9_1 0x27 R_MICROMIPS_TLS_GOTTPREL 166 R_AARCH64_GOTREL64 307 STO_PPC64_LOCAL_BIT 5 OEX_FPU_OFLO 0x04 __ismask(x) (_ctype[(int)(unsigned char)(x)]) R_ARM_THM_MOVW_BREL 89 R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI ELFDATANUM 3 R_PPC64_TOC16 47 R_PPC64_PLTREL32 R_PPC_PLTREL32 EF_MIPS_ARCH_5 0x40000000 DT_FLAGS_1 0x6ffffffb R_CKCORE_DOFFSET_IMM18BY4 46 DT_REL 17 R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC 553 R_TILEGX_IMM16_X1_HW0_LAST_TLS_GD 87 NT_PLATFORM 5 R_ARC_JMP_SLOT 0x37 R_IA64_DTPMOD64MSB 0xa6 R_PARISC_TPREL32 153 R_TILEPRO_HA16 9 R_X86_64_PLT32 4 GNU_PROPERTY_AARCH64_FEATURE_1_PAC (1U << 1) R_LARCH_TLS_LE64_LO20 85 DF_1_SYMINTPOSE 0x00800000 R_ALPHA_NUM 46 R_PPC64_ADDR16_HIGH 110 R_ARM_GOTOFF 24 R_390_TLS_GD32 40 R_NDS32_GLOB_DAT 40 DT_MIPS_INTERFACE_SIZE 0x7000002c R_PARISC_DIR32 1 EF_MIPS_ARCH_ASE_MDMX 0x08000000 RHF_DEFAULT_DELAY_LOAD (1 << 9) R_MIPS_PC32 248 STB_WEAK 2 R_AARCH64_TLS_DTPMOD 1028 R_LARCH_TLS_DESC64_PC_LO20 113 io__get_hex PF_MASKPROC 0xf0000000 SHT_RELA 4 R_ARM_THM_TLS_DESCSEQ32 130 EF_RISCV_RVE 0x0008 R_OR1K_GOT16 14 SHT_MIPS_FDESC 0x70000011 R_TILEPRO_IMM16_X1_HI_PCREL 36 DT_VALRNGLO 0x6ffffd00 DT_ALPHA_NUM 1 R_SPARC_TLS_IE_LDX 70 PF_ARM_ABS 0x40000000 EM_8051 165 EM_VIDEOCORE3 137 SHT_FINI_ARRAY 15 R_OR1K_LO_16_IN_INSN 4 R_NIOS2_CALL_HA 45 R_SPARC_REGISTER 53 NT_FDO_PACKAGING_METADATA 0xcafe1a7e R_ARM_RREL32 252 R_IA64_DTPREL64MSB 0xb6 R_AARCH64_TSTBR14 279 R_TILEGX_IMM16_X0_HW2_LAST_PCREL 62 R_IA64_DIR64LSB 0x27 R_PPC64_PLTGOT16_LO 53 EF_SH3 0x3 DT_RELRENT 37 R_ARM_MOVW_BREL_NC 84 R_390_PC32 5 EF_MIPS_MACH_5500 0x00980000 R_MICROBLAZE_TLSDTPREL64 27 R_SPARC_UA32 23 SHT_SYMTAB_SHNDX 18 SHT_MIPS_PIXIE 0x70000023 DT_NIOS2_GP 0x70000002 R_CKCORE_DOFFSET_IMM18BY2 45 R_AARCH64_TLSLE_MOVW_TPREL_G2 544 R_TILEGX_IMM16_X0_HW3_PLT_PCREL 76 R_SPARC_JMP_SLOT 21 R_MN10300_24 9 DF_ORIGIN 0x00000001 R_PPC64_TPREL64 73 NT_PPC_TM_CVSX 0x10b R_390_COPY 9 R_LARCH_TLS_LE_LO12 84 PT_INTERP 3 R_PPC_EMB_NADDR16 102 R_SPARC_IRELATIVE 249 R_PARISC_GPREL16F 93 R_SPARC_TLS_TPOFF64 79 R_MICROMIPS_TLS_DTPREL_LO16 165 EM_D10V 85 R_LARCH_SOP_POP_32_S_10_16 41 EF_CSKY_PROCESSOR 0X0000FFFF R_LARCH_SUB16 53 R_RISCV_ADD8 33 R_MIPS_16 1 STB_MIPS_SPLIT_COMMON 13 EF_PARISC_EXT 0x00020000 R_SH_ALIGN 29 R_IA64_PCREL60B 0x48 R_M32R_GNU_VTENTRY 12 R_X86_64_DTPOFF32 21 R_ARM_LDR_SBREL_11_0 35 R_AARCH64_TLSDESC_ADR_PAGE21 562 R_PPC_GOT_TPREL16_HI 89 R_386_TLS_LE 17 NT_ARM_TAGGED_ADDR_CTRL 0x409 DT_INIT_ARRAY 25 EF_MIPS_ARCH_ASE 0x0f000000 NT_PRSTATUS 1 R_M32R_GOT16_LO 58 PT_HP_TLS (PT_LOOS + 0x0) R_386_TLS_GD_32 24 DT_RELR 36 R_390_GOTOFF64 28 R_PARISC_TLS_IE21L R_PARISC_LTOFF_TP21L R_ARM_IRELATIVE 160 R_PARISC_LTOFF_FPTR32 57 R_PPC_PLT32 27 R_PPC_TPREL16_HI 71 R_MIPS_TLS_DTPREL_LO16 45 R_NIOS2_TLS_LE16 32 R_TILEPRO_IMM16_X0_LO 25 R_TILEPRO_IMM16_X0_TLS_LE 85 R_ARC_TLS_LE_32 0x4B MIPS_AFL_EXT_5900 6 R_M32R_JMP_SLOT 52 R_PARISC_LTOFF_TP16WF 230 R_ALPHA_TLS_LDM 30 R_LARCH_B16 64 OEX_PAGE0 0x10000 EM_PPC64 21 R_390_GOTPCDBL 21 ELF64_R_INFO(sym,type) ((((Elf64_Xword) (sym)) << 32) + (type)) VER_DEF_NUM 2 R_MIPS_HIGHER 28 R_ARM_THM_RPC22 251 R_68K_GLOB_DAT 20 R_MICROMIPS_PC23_S2 173 R_PPC_EMB_RELSDA 116 R_SPARC_TLS_GD_CALL 59 R_386_GOTPC 10 R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC 571 STB_LOOS 10 R_SPARC_GOT22 15 EF_ARM_EABI_UNKNOWN 0x00000000 iscntrl(c) ((__ismask(c)&(_C)) != 0) R_SH_TLS_DTPOFF32 150 R_ARC_S25H_PCREL 0x10 R_LARCH_SUB24 54 R_X86_64_GOTOFF64 25 NT_ASRS 8 SHT_MIPS_DEBUG 0x70000005 R_LARCH_TLS_LE_HI20_R 121 R_M32R_HI16_SLO 8 EM_CUDA 190 PF_X (1 << 0) R_IA64_FPTR64MSB 0x46 R_ARM_ALU_SB_G0 71 R_LARCH_PCALA64_HI12 74 LITUSE_ALPHA_BASE 1 R_TILEGX_GNU_VTINHERIT 128 MIPS_AFL_EXT_5400 15 R_RISCV_RVC_BRANCH 44 R_LARCH_TLS_LD_PC_HI20 95 SHT_MIPS_PDESC 0x70000014 R_MIPS_TLS_TPREL64 48 EM_TRIMEDIA 163 R_ARM_LDRS_SB_G2 80 R_TILEGX_IMM8_X1_TLS_ADD 119 R_SH_DIR8WPZ 6 NT_PPC_VMX 0x100 STO_ALPHA_NOPV 0x80 R_MICROMIPS_HIGHEST 152 EF_SH2A_SH3E 0x18 R_386_TLS_LDM_PUSH 29 R_RISCV_TLSDESC_ADD_LO12 64 DT_HIPROC 0x7fffffff SHT_MIPS_LINE 0x70000019 R_386_JMP_SLOT 7 NT_S390_TDB 0x308 EM_ST7 68 R_RISCV_JAL 17 EM_68HC08 71 ELFDATA2LSB 1 R_ARC_TLS_DTPMOD 0x42 R_LARCH_TLS_TPREL64 11 DT_SPARC_REGISTER 0x70000001 R_M32R_10_PCREL_RELA 36 R_PPC_ADDR14_BRNTAKEN 9 R_AARCH64_MOVW_PREL_G1 289 R_NIOS2_CALL16 23 R_390_NONE 0 MIPS_AFL_EXT_4010 8 R_IA64_DTPREL32LSB 0xb5 R_PPC64_GOT_TLSGD16_HA 82 R_MIPS_REL16 33 E_MIPS_ARCH_1 EF_MIPS_ARCH_1 R_CRIS_GLOB_DAT 10 R_68K_NUM 43 R_CKCORE_PLT_HI16 34 R_ARM_PREL31 42 SHF_GNU_RETAIN (1 << 21) R_LARCH_TLS_IE_PC_LO12 88 R_PARISC_PLABEL32 65 R_ARC_GOTPC 0x3A R_MICROBLAZE_32_SYM_OP_SYM 10 NT_ARM_SSVE 0x40b EM_ZSP 79 R_RISCV_TLS_DTPREL64 9 R_NIOS2_ALIGN 21 R_SH_SWITCH16 25 R_SPARC_22 10 R_390_PLTOFF32 35 R_TILEGX_IMM16_X0_HW0_LAST_TLS_LE 82 R_ARC_TLS_TPOFF 0x44 E_MIPS_ARCH_3 EF_MIPS_ARCH_3 AT_L2_CACHEGEOMETRY 45 SHT_HASH 5 R_AARCH64_TLSDESC_OFF_G0_NC 566 R_METAG_GETSETOFF 5 ELFOSABI_FREEBSD 9 PT_NOTE 4 R_PPC64_DTPREL16_HIGHEST 105 ELF_NOTE_ABI NT_GNU_ABI_TAG R_PPC_ADDR16_HI 5 R_ARM_THM_MOVW_PREL_NC 49 R_M32R_SDA16_RELA 42 DT_MIPS_FLAGS 0x70000005 STT_FUNC 2 MIPS_AFL_EXT_4111 13 R_LARCH_TLS_LE_ADD_R 122 STB_HIOS 12 R_LARCH_ALIGN 102 R_TILEGX_HW2 11 AT_EXECFN 31 R_X86_64_64 1 EF_MIPS_MACH_ALLEGREX 0x00840000 R_SPARC_HIPLT22 25 SHT_MIPS_AUXSYM 0x70000016 R_SH_LABEL 32 E_MIPS_ARCH_5 EF_MIPS_ARCH_5 R_ALPHA_REFQUAD 2 STB_LOCAL 0 R_AARCH64_MOVW_PREL_G2_NC 292 R_TILEPRO_LO16 7 SHT_MIPS_DELTADECL 0x7000001f R_PPC64_DTPMOD64 68 DT_JMPREL 23 R_SPARC_LOPLT10 26 R_LARCH_TLS_TPREL32 10 SHN_MIPS_ACOMMON 0xff00 DT_SYMBOLIC 16 R_IA64_SECREL32MSB 0x64 R_TILEGX_IMM8_Y1 26 STO_MIPS_PROTECTED 0x3 R_MICROBLAZE_GNU_VTINHERIT 11 PT_NULL 0 R_SPARC_TLS_DTPOFF64 77 GNU_PROPERTY_X86_ISA_1_NEEDED 0xc0008002 R_SPARC_H44 50 NT_S390_RI_CB 0x30d R_OR1K_HI_16_IN_INSN 5 DT_HASH 4 ELF_NOTE_SOLARIS "SUNW Solaris" R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN R_ARC_32_PCREL 0x31 _P 0x10 R_METAG_TLS_LDO 51 R_M32R_26_PCREL_RELA 38 R_NIOS2_UJMP 18 R_OR1K_PLT26 15 R_OR1K_INSN_REL_26 6 R_TILEGX_IMM16_X1_HW0_LAST_TLS_LE 83 R_SPARC_PCPLT32 27 R_ARM_TLS_TPOFF32 19 R_OR1K_TLS_LDM_HI16 24 R_PARISC_LTOFF21L 34 R_M32R_10_PCREL 4 R_AARCH64_TLSDESC_LD_PREL19 560 R_LARCH_SOP_PUSH_ABSOLUTE 23 R_METAG_NONE 3 EM_SVX 73 R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN R_TILEPRO_IMM16_X1_TLS_LE_LO 88 SHT_MIPS_WHIRL 0x70000026 R_M32R_LO16 9 R_PPC64_UADDR64 43 SHT_MIPS_XLATE_DEBUG 0x70000025 SHT_SUNW_COMDAT 0x6ffffffb EF_PARISC_NO_KABP 0x00100000 R_PPC_GOT_TPREL16 87 PT_IA_64_ARCHEXT (PT_LOPROC + 0) R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN R_RISCV_PCREL_HI20 23 R_PARISC_HIRESERVE 255 ELF32_ST_VISIBILITY(o) ((o) & 0x03) R_AARCH64_TLSGD_ADD_LO12_NC 514 R_AARCH64_TLSLD_MOVW_G0_NC 521 R_MICROMIPS_TLS_GD 162 EF_PARISC_LAZYSWAP 0x00400000 EM_PPC 20 R_RISCV_NONE 0 R_METAG_REG16OP2 10 R_TILEPRO_IMM16_X0 23 R_AARCH64_TLSDESC_OFF_G1 565 R_SPARC_6 45 R_IA64_FPTR32LSB 0x45 R_MICROMIPS_TLS_TPREL_LO16 170 NT_S390_HIGH_GPRS 0x300 PT_HP_CORE_NONE (PT_LOOS + 0x1) R_TILEPRO_NONE 0 R_SPARC_TLS_GD_ADD 58 EF_SH4_NOMMU_NOFPU 0x12 R_PPC64_GOT_DTPREL16_HI 93 R_386_RELATIVE 8 DT_PLTRELSZ 2 R_LARCH_GOT_HI20 79 R_NIOS2_U16 2 R_68K_TLS_GD32 25 R_AARCH64_GOTREL32 308 R_SPARC_LOX10 49 R_IA64_PCREL21F 0x4b R_PPC64_ADDR32 R_PPC_ADDR32 EI_DATA 5 R_PPC64_PLTGOT16 52 R_68K_TLS_TPREL32 42 R_MICROBLAZE_GOTOFF_64 19 NT_PPC_TM_CDSCR 0x10f DT_INIT_ARRAYSZ 27 EM_CRIS 76 R_68K_PLT32 13 R_PARISC_LTOFF64 96 DT_GNU_CONFLICTSZ 0x6ffffdf6 SHF_INFO_LINK (1 << 6) R_M32R_GOTOFF 54 R_ARC_W_ME 0x1F R_METAG_REG32OP2 7 DT_VERNEEDNUM 0x6fffffff R_SPARC_HIX22 48 NT_GNU_GOLD_VERSION 4 R_390_PC16 16 R_X86_64_IRELATIVE 37 R_SH_JMP_SLOT 164 R_TILEPRO_IMM16_X1_TLS_GD_HA 73 R_OR1K_RELATIVE 21 R_RISCV_TLS_GOT_HI20 21 R_TILEGX_IMM16_X1_HW0_LAST_TLS_IE 101 R_ARC_SECTOFF_2 0x2C R_PARISC_LTOFF_TP16DF 231 R_MIPS_REL32 3 R_LARCH_TLS_DESC_HI20 115 R_PPC64_COPY R_PPC_COPY R_TILEPRO_IMM16_X0_HI 27 EF_LARCH_ABI_DOUBLE_FLOAT 0x03 R_ARM_ALU_PC_G1_NC 59 SHT_SUNW_move 0x6ffffffa R_IA64_TPREL64MSB 0x96 NOTE_GNU_PROPERTY_SECTION_NAME ".note.gnu.property" R_ARC_N8 0x8 EM_SH 42 R_AARCH64_TLSDESC_CALL 569 R_LARCH_TLS_DESC64_HI12 118 R_MIPS_TLS_DTPMOD64 40 R_M32R_GOTOFF_LO 64 R_MIPS_NUM 255 SHT_GNU_HASH 0x6ffffff6 R_MN10300_RELATIVE 23 EF_ARM_INTERWORK 0x04 EF_RISCV_FLOAT_ABI_SINGLE 0x0002 DF_1_ORIGIN 0x00000080 GNU_PROPERTY_X86_ISA_1_BASELINE (1U << 0) SYMINFO_NONE 0 ELF32_ST_TYPE(val) ((val) & 0xf) EF_MIPS_ARCH_4 0x30000000 ELFOSABI_NETBSD 2 EM_TSK3000 131 R_MIPS_JALR 37 R_390_8 1 EF_MIPS_ARCH_ASE_MICROMIPS 0x02000000 ELFCLASSNONE 0 NT_FPREGSET 2 R_PARISC_LTOFF_TP14DR 228 PT_HISUNW 0x6fffffff R_PPC_UADDR16 25 EF_MIPS_ABI_O32 0x00001000 R_TILEGX_32 2 EM_FR20 37 DT_SPARC_NUM 2 R_ARM_ALU_PC_G0 58 DT_RELRSZ 35 R_PPC_REL16 249 EF_IA_64_MASKOS 0x0000000f read_to_eol EM_STARCORE 58 ELFMAG1 'E' ELF64_R_TYPE(i) ((i) & 0xffffffff) R_PARISC_DIR14R 6 R_PPC_REL16_HI 251 R_TILEPRO_IMM8_X0 17 EF_SH_DSP 0x4 R_ALPHA_LITUSE 5 EM_HUANY 81 SHT_ARM_ATTRIBUTES (SHT_LOPROC + 3) R_CRIS_32_PCREL 6 R_CRIS_32_PLT_PCREL 19 R_PARISC_DIR16WF 86 R_ARM_THM_XPC22 16 R_LARCH_SOP_SUB 32 PT_IA_64_HP_HSL_ANOT (PT_LOOS + 0x13) R_390_GOTOFF32 13 DT_MIPS_PLTGOT 0x70000032 DT_FINI 13 EM_PJ 91 R_PPC64_TLSLD 108 R_SPARC_TLS_TPOFF32 78 R_PARISC_DIR14WR 83 R_NIOS2_COPY 36 R_PPC64_GOT_TLSLD16 83 R_NIOS2_CALLR 20 EF_MIPS_MACH_LS2F 0x00A10000 R_MIPS_DELETE 27 R_CKCORE_ADDRPLT_HI16 38 R_IA64_LTV64LSB 0x77 STV_INTERNAL 1 EI_CLASS 4 SHT_MIPS_SYMBOL_LIB 0x70000020 R_SPARC_TLS_DTPMOD64 75 R_PPC64_PLTGOT16_LO_DS 66 R_386_TLS_LDM 19 R_MIPS_PC26_S2 61 GNU_PROPERTY_LOUSER 0xe0000000 SHT_MIPS_GPTAB 0x70000003 RHF_RLD_ORDER_SAFE (1 << 14) R_SPARC_64 32 DT_ENCODING 32 R_ARM_TLS_LE12 110 R_LARCH_SOP_POP_32_S_10_12 40 R_RISCV_TLS_DTPMOD32 6 R_LARCH_SOP_POP_32_S_10_16_S2 42 AT_PHDR 3 R_386_PC8 23 EFA_PARISC_1_1 0x0210 PT_IA_64_HP_OPT_ANOT (PT_LOOS + 0x12) R_MIPS_GNU_VTENTRY 254 EM_V850 87 EM_ST100 60 R_PPC64_GOT16_HA R_PPC_GOT16_HA R_PARISC_PCREL17F 12 R_TILEPRO_IMM16_X0_TLS_IE_LO 76 R_SPARC_GNU_VTENTRY 251 SHF_WRITE (1 << 0) EF_MIPS_ABI2 32 R_ARM_ALU_SBREL_19_12 36 R_METAG_ADDR32 2 R_NIOS2_TLS_GD16 28 DT_RELACOUNT 0x6ffffff9 R_RISCV_LO12_S 28 R_NIOS2_GNU_VTENTRY 17 LITUSE_ALPHA_JSR 3 R_X86_64_GOTPC64 29 R_PPC_PLT16_LO 29 R_390_GOT12 6 R_IA64_LTOFF_FPTR64I 0x53 DT_VERDEFNUM 0x6ffffffd R_ARM_THM_JUMP6 52 R_RISCV_TPREL_LO12_I 30 R_TILEPRO_IMM16_X1_GOT_HA 46 SHT_MIPS_DELTASYM 0x7000001b R_PPC64_DTPREL16_DS 101 SHN_ABS 0xfff1 R_SH_DIR8BP 7 AT_BASE_PLATFORM 24 R_390_16 3 EF_MIPS_ARCH_32R6 0x90000000 DT_SYMTAB_SHNDX 34 EM_TI_C6000 140 R_ARM_REL32_NOI 56 R_TILEPRO_SHAMT_Y0 53 R_ARM_THM_TLS_DESCSEQ 129 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC 530 R_LARCH_TLS_DESC_CALL 120 EM_SPARC 2 R_IA64_PCREL22 0x7a R_IA64_LTOFF_DTPREL22 0xba R_LARCH_SOP_PUSH_TLS_GOT 27 EF_ARM_SYMSARESORTED 0x04 ET_REL 1 R_X86_64_32 10 R_NIOS2_HI16 9 ELFOSABI_STANDALONE 255 R_MIPS_TLS_TPREL32 47 EF_MIPS_MACH_OCTEON3 0x008e0000 GNU_PROPERTY_UINT32_AND_LO 0xb0000000 RHF_NO_MOVE (1 << 3) STV_DEFAULT 0 isalnum(c) ((__ismask(c)&(_U|_L|_D)) != 0) R_M32R_HI16_ULO_RELA 39 R_TILEPRO_COPY 10 SHT_MIPS_EH_REGION 0x70000027 R_MICROMIPS_GOT16 138 GNU_PROPERTY_NO_COPY_ON_PROTECTED 2 EF_ARC_OSABI_MSK 0x00000f00 R_MIPS_GOT16 9 R_MICROBLAZE_TLSDTPMOD32 25 STO_AARCH64_VARIANT_PCS 0x80 R_OR1K_TLS_LE_LO16 31 DT_MIPS_HIPAGENO 0x70000014 PT_HP_PARALLEL (PT_LOOS + 0x10) R_IA64_GPREL64LSB 0x2f R_CKCORE_GOT_HI16 31 R_OR1K_16_PCREL 10 R_PARISC_DIR17R 3 R_PARISC_SECREL32 41 R_AARCH64_PREL64 260 R_AARCH64_ADR_PREL_PG_HI21 275 EF_MIPS_MACH_LS2E 0x00A00000 EF_SH3_DSP 0x5 R_AARCH64_MOVW_UABS_G3 269 R_PPC_DIAB_SDA21_HA 182 R_TILEPRO_HI16 8 R_ARC_N16 0x9 R_X86_64_GOTPCREL 9 R_ARM_LDC_SB_G0 81 DT_MOVESZ 0x6ffffdfb EF_ARM_APCS_26 0x08 R_ALPHA_TPREL16 41 R_ARM_GNU_VTENTRY 100 R_RISCV_SUB_ULEB128 61 R_TILEGX_IMM16_X1_HW1_PLT_PCREL 69 R_LARCH_RELATIVE 3 EM_IA_64 50 R_390_NUM 62 R_TILEGX_IMM16_X0_HW0_GOT 64 R_MN10300_PLT32 15 OEX_FPU_INEX 0x01 SHN_MIPS_TEXT 0xff01 R_TILEPRO_IMM16_X1_TLS_LE_HI 90 EM_AVR 83 R_RISCV_SUB6 52 R_ALPHA_GPRELLOW 18 EM_RCE 39 R_PPC64_GOT16_HI R_PPC_GOT16_HI DF_1_GLOBAL 0x00000002 SHT_NOTE 7 R_M32R_32_RELA 34 AT_RSEQ_FEATURE_SIZE 27 R_AARCH64_LDST8_ABS_LO12_NC 278 R_IA64_LTOFF_FPTR32LSB 0x55 R_MN10300_GOTOFF24 13 PT_IA_64_UNWIND (PT_LOPROC + 1) R_MIPS_TLS_GD 42 EM_COOL 217 STT_SPARC_REGISTER 13 ELFCOMPRESS_HIPROC 0x7fffffff R_LARCH_SOP_POP_32_U 46 RHF_CORD (1 << 12) MIPS_AFL_ASE_MIPS16 0x00000400 SHT_STRTAB 3 R_LARCH_TLS_DESC64 14 R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 541 EF_MIPS_MACH_5400 0x00910000 EF_LARCH_ABI_SINGLE_FLOAT 0x02 R_X86_64_GOTPCREL64 28 R_LARCH_ABS_LO12 68 EF_SH4 0x9 LITUSE_ALPHA_TLS_LDM 5 R_CKCORE_PCREL_IMM7BY4 50 R_PARISC_LTOFF14R 38 NT_PSTATUS 10 R_SH_PLT32 161 R_PPC_EMB_RELST_LO 112 R_SPARC_HH22 34 R_TILEGX_RELATIVE 19 R_IA64_PLTOFF64I 0x3b EM_68HC11 70 STO_MIPS_SC_ALIGN_UNUSED 0xff R_SPARC_TLS_DTPOFF32 76 SHT_NULL 0 R_LARCH_PCREL20_S2 103 EM_ECOG2 134 R_PPC_COPY 19 R_LARCH_TLS_GD_PCREL20_S2 125 R_RISCV_PCREL_LO12_S 25 SHT_HIPROC 0x7fffffff R_PPC_DIAB_RELSDA_HI 184 R_NDS32_TLS_DESC 119 AT_L3_CACHESIZE 46 R_TILEGX_JUMPOFF_X1_PLT 22 R_PPC64_GOT_TLSLD16_LO 84 SHT_SYMTAB 2 R_PARISC_TLS_LDMCALL 239 R_IA64_PLTOFF64MSB 0x3e R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC 559 DT_EXTRANUM 3 AT_L3_CACHESHAPE 37 R_LARCH_SOP_AND 36 ELFOSABI_SOLARIS 6 R_MN10300_GLOB_DAT 21 R_LARCH_ABS_HI20 67 DT_MIPS_GOTSYM 0x70000013 DT_MIPS_RLD_MAP 0x70000016 R_MICROMIPS_GOT_OFST 147 R_PPC64_TPREL16_HA 72 R_386_TLS_GD_CALL 26 R_PPC_ADDR24 2 R_X86_64_JUMP_SLOT 7 EF_PARISC_ARCH 0x0000ffff ELFOSABI_LINUX ELFOSABI_GNU EM_L10M 180 R_LARCH_SOP_POP_32_S_5_20 43 MIPS_AFL_ASE_MT 0x00000040 VER_NDX_ELIMINATE 0xff01 DT_VERSIONTAGNUM 16 R_X86_64_NONE 0 DT_NULL 0 R_X86_64_GOT64 27 MIPS_AFL_REG_NONE 0x00 R_PPC64_UADDR16 R_PPC_UADDR16 R_ARM_RPC24 254 R_AARCH64_MOVW_GOTOFF_G2_NC 305 R_LARCH_B26 66 EM_LATTICEMICO32 138 R_M32R_16_RELA 33 R_M32R_GOT24 48 R_TILEGX_IMM16_X1_HW1_PCREL 53 R_LARCH_TLS_LE_LO12_R 123 R_ARM_ALU_PC_G0_NC 57 EM_MN10200 90 R_METAG_LO16_PLT 39 NT_PPC_TM_CFPR 0x109 R_PARISC_GPREL16WF 94 STT_GNU_IFUNC 10 R_LARCH_TLS_LD_HI20 96 STV_PROTECTED 3 EM_F2MC16 104 R_M32R_HI16_SLO_RELA 40 LL_IGNORE_INT_VER (1 << 1) isspace(c) ((__ismask(c)&(_S)) != 0) R_TILEPRO_GNU_VTINHERIT 128 VER_NEED_NONE 0 ELF64_ST_VISIBILITY(o) ELF32_ST_VISIBILITY (o) R_ARM_LDR_SB_G1 76 R_TILEPRO_IMM16_X1_HA 30 R_MIPS_TLS_DTPREL_HI16 44 R_METAG_TLS_LDO_LO16 50 R_ARC_GLOB_DAT 0x36 R_CKCORE_TLS_DTPOFF32 57 R_ARM_ABS32 2 R_PARISC_DIR16DF 87 R_CKCORE_PCRELIMM11BY2 3 R_NIOS2_TLS_TPREL 35 R_SPARC_TLS_IE_ADD 71 R_METAG_RELBRANCH_PLT 40 EM_DSPIC30F 118 R_LARCH_IRELATIVE 12 __compiletime_assert(condition,msg,prefix,suffix) do { } while (0) DT_ADDRRNGLO 0x6ffffe00 SYMINFO_BT_SELF 0xffff DT_VERNEED 0x6ffffffe R_PARISC_DIR14DR 84 DT_X86_64_NUM 4 R_MN10300_GOTPC16 11 DT_FINI_ARRAYSZ 28 R_METAG_TLS_TPOFF 56 R_MIPS_TLS_DTPMOD32 38 SHT_MIPS_SHDR 0x70000010 DT_MIPS_PROTECTED_GOTIDX 0x70000028 R_OR1K_GOTPC_HI16 12 R_ARM_MOVT_BREL 85 R_SPARC_11 31 EM_DSP24 136 ELFDATA2MSB 2 R_MICROBLAZE_GOTOFF_32 20 R_PPC64_GOT_TPREL16_DS 87 AT_GID 13 R_ARC_N32 0xB R_LARCH_TLS_LE_HI20 83 R_68K_GOT32 7 EM_NS32K 97 R_MICROBLAZE_SRO32 7 GNU_PROPERTY_X86_ISA_1_V4 (1U << 3) R_TILEGX_16_PCREL 7 toupper(c) __toupper(c) DT_MIPS_DELTA_SYM_NO 0x7000001e R_NIOS2_GOTOFF_LO 24 STT_LOOS 10 R_NIOS2_PCREL_HA 27 VER_NEED_CURRENT 1 R_MN10300_NONE 0 DT_RELSZ 18 AT_ENTRY 9 R_390_TLS_LDM64 46 R_PPC64_ADDR16 R_PPC_ADDR16 AT_DCACHEBSIZE 19 R_IA64_LTOFF_FPTR64MSB 0x56 R_AARCH64_MOVW_PREL_G2 291 EF_MIPS_32BITMODE 0x00000100 _SP 0x80 R_IA64_SEGREL64MSB 0x5e NT_S390_GS_BC 0x30c R_METAG_HI16_PLT 38 R_NIOS2_S16 1 R_TILEPRO_IMM16_X0_TLS_IE_HI 78 EF_MIPS_MACH_GS264E 0x00A40000 R_AARCH64_TLSLD_MOVW_G1 520 DT_PPC64_GLINK (DT_LOPROC + 0) R_MICROMIPS_LITERAL 137 R_TILEGX_IMM16_X0_HW1 38 SHT_MIPS_LIBLIST 0x70000000 R_MICROBLAZE_32_LO 6 R_PPC_PLT16_HI 30 R_ARM_COPY 20 R_TILEGX_IMM16_X1_HW2 41 R_TILEGX_IMM8_X0 23 R_CRIS_32_PLT_GOTREL 18 R_MIPS_GPREL32 12 R_TILEGX_SHAMT_Y1 35 EM_PRISM 82 R_AARCH64_MOVW_UABS_G0 263 OEX_PRECISEFP OEX_FPDBUG R_PARISC_LTOFF_FPTR21L 58 R_386_8 22 R_PPC64_PLT16_LO R_PPC_PLT16_LO AT_L1D_CACHESIZE 42 SHT_CHECKSUM 0x6ffffff8 R_ARM_THM_ABS5 7 EM_MIPS 8 EM_PDP11 65 GNU C11 15.2.0 -U _FORTIFY_SOURCE -mtune=generic -march=x86-64 -ggdb3 -std=gnu11 -fPIC -fasynchronous-unwind-tables -fstack-protector-strong -fstack-clash-protection -fcf-protection -fzero-init-padding-bits=all EM_X86_64 62 R_AARCH64_TLSDESC_ADD_LO12 564 R_390_GOTENT 26 R_OR1K_GLOB_DAT 19 EF_MIPS_ARCH_3 0x20000000 R_AARCH64_COPY 1024 R_PARISC_TLS_LE14R R_PARISC_TPREL14R EF_SPARC_HAL_R1 0x000400 SHT_MIPS_UCODE 0x70000004 R_TILEGX_IMM16_X0_HW2_LAST 48 R_PPC_GOT16_LO 15 R_X86_64_TPOFF64 18 DT_VERDEF 0x6ffffffc R_LARCH_TLS_IE64_PC_LO20 89 R_PPC_ADDR16_HA 6 EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK) R_ARM_LDRS_PC_G2 66 R_68K_TLS_IE16 35 R_MIPS16_TLS_TPREL_HI16 111 ODK_PAD 3 R_RISCV_SET32 56 MIPS_AFL_EXT_LOONGSON_2F 18 R_SPARC_TLS_DTPMOD32 74 R_ARM_THM_PC8 11 NT_S390_TODCMP 0x302 R_AARCH64_MOVW_PREL_G1_NC 290 STT_TLS 6 R_METAG_TLS_IE 52 R_TILEPRO_GNU_VTENTRY 129 R_PARISC_LTOFF16WF 102 R_SPARC_DISP16 5 R_LARCH_TLS_IE_LO12 92 R_M32R_GNU_VTINHERIT 11 MIPS_AFL_EXT_LOONGSON_2E 17 R_PPC_ADDR14_BRTAKEN 8 R_PPC64_TOC16_HA 50 DT_FEATURE_1 0x6ffffdfc R_ARM_LDC_PC_G0 67 SHN_MIPS_DATA 0xff02 PT_LOAD 1 R_SPARC_M44 51 R_ARM_NONE 0 PT_IA_64_HP_STACK (PT_LOOS + 0x14) OEX_FPDBUG 0x40000 DF_1_INTERPOSE 0x00000400 R_NIOS2_GOT_HA 43 R_LARCH_SOP_POP_32_S_10_5 38 R_AARCH64_JUMP_SLOT 1026 R_NIOS2_NONE 0 R_MIPS_PCLO16 65 SHT_ARC_ATTRIBUTES (SHT_LOPROC + 1) PT_PHDR 6 R_PPC64_PLT32 R_PPC_PLT32 R_CRIS_GNU_VTINHERIT 7 ELFOSABI_TRU64 10 R_RISCV_TLS_TPREL64 11 R_MIPS_RELATIVE 128 STT_LOPROC 13 R_AARCH64_IRELATIVE 1032 ELF_NOTE_OS_GNU 1 EF_MIPS_OPTIONS_FIRST 0x00000080 EF_MIPS_MACH_GS464E 0x00A30000 SHN_HIRESERVE 0xffff EI_MAG0 0 AT_PHNUM 5 R_MICROMIPS_SCN_DISP 155 R_LARCH_TLS_DESC32 13 R_MICROBLAZE_GLOB_DAT 18 R_OR1K_GOTOFF_HI16 16 PT_HP_OPT_ANNOT (PT_LOOS + 0x12) EF_SH_UNKNOWN 0x0 R_SPARC_HM10 35 AT_RANDOM 25 R_TILEPRO_IMM16_X0_TLS_LE_HI 89 STO_ALPHA_STD_GPLOAD 0x88 EF_ARM_EABIMASK 0XFF000000 MIPS_AFL_ASE_DSPR2 0x00000002 R_LARCH_GOT64_LO20 81 DT_MOVEENT 0x6ffffdfa NT_LOONGARCH_CPUCFG 0xa00 EM_960 19 R_PPC64_GOT_TLSLD16_HI 85 ELF32_M_SIZE(info) ((unsigned char) (info)) R_ARM_SBREL31 39 R_CRIS_32_GOT 14 R_IA64_PCREL32MSB 0x4c R_CKCORE_TLS_DTPMOD32 56 EFA_PARISC_2_0 0x0214 R_AARCH64_TLSLD_ADR_PREL21 517 R_IA64_PCREL32LSB 0x4d R_METAG_PLT 42 NT_386_TLS 0x200 R_IA64_REL32MSB 0x6c EM_IAMCU 6 R_PPC64_REL16_HI 251 EF_MIPS_MACH_9000 0x00990000 EM_ARC_COMPACT 93 DT_PREINIT_ARRAY 32 PF_MIPS_LOCAL 0x10000000 R_RISCV_ADD64 36 DT_AUXILIARY 0x7ffffffd SHF_MASKPROC 0xf0000000 R_PPC_TPREL16_HA 72 PT_MIPS_RTPROC 0x70000001 OHWA0_R4KEOP_CHECKED 0x00000001 R_MICROMIPS_PC16_S1 141 R_68K_TLS_IE32 34 EM_MMDSP_PLUS 160 EM_COLDFIRE 52 R_X86_64_PC16 13 symbol_type R_AARCH64_TLSGD_MOVW_G0_NC 516 R_MIPS_RELGOT 36 NT_PPC_PKEY 0x110 SHT_MIPS_MSYM 0x70000001 R_ARM_THM_PC9 103 R_386_COPY 5 R_IA64_SEGREL32LSB 0x5d MIPS_AFL_ASE_MICROMIPS 0x00000800 AT_EXECFD 2 PT_DYNAMIC 2 R_TILEGX_IMM16_X0_HW1_LAST_GOT 74 DT_MIPS_IVERSION 0x70000004 PT_ARM_EXIDX (PT_LOPROC + 1) R_PPC_EMB_SDAI16 106 R_CRIS_32_GOTREL 17 EF_SPARC_EXT_MASK 0xFFFF00 R_TILEPRO_IMM16_X0_GOT_HI 43 R_386_PC16 21 SHN_MIPS_SUNDEFINED 0xff04 EM_78KOR 199 R_CKCORE_NONE 0 R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC 538 R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN DF_1_NOOPEN 0x00000040 SHT_SUNW_syminfo 0x6ffffffc R_CRIS_32 3 STT_HIPROC 15 R_68K_TLS_LDM16 29 DT_MIPS_DYNSTR_ALIGN 0x7000002b SHT_DYNAMIC 6 R_CRIS_NONE 0 EF_SH2A_SH3_NOFPU 0x16 NT_PPC_TM_CPPR 0x10e R_METAG_TLS_LE_LO16 61 R_PPC64_ADDR64 38 R_PARISC_PCREL64 72 STT_ARM_TFUNC STT_LOPROC ET_NONE 0 R_390_GOTPLT32 31 DF_1_DIRECT 0x00000100 SHF_IA_64_SHORT 0x10000000 R_PPC64_ADDR16_HIGHEST 41 SHT_MIPS_XHASH 0x7000002b R_MIPS_32 2 DT_MIPS_LIBLISTNO 0x70000010 EF_ALPHA_CANRELAX 2 EM_H8_500 49 R_ARC_SECTOFF_ME_2 0x2A R_ARM_GOTPC 25 EM_TILEPRO 188 R_RISCV_TLSDESC 12 R_X86_64_REX_GOTPCRELX 42 R_SH_TLS_GD_32 144 R_PPC_DTPREL16_LO 75 R_ARM_LDR_PC_G1 62 R_ARM_TLS_DTPOFF32 18 R_PARISC_GPREL16DF 95 OPAD_SYMBOL 0x4 R_ARM_THM_PC11 102 R_METAG_LOOG 14 R_LARCH_64 2 R_M32R_GOTOFF_HI_ULO 62 PF_HP_CODE 0x01000000 R_CKCORE_COPY 10 R_PPC64_GOT16_LO R_PPC_GOT16_LO EM_MMA 54 R_AARCH64_GOT_LD_PREL19 309 EM_BPF 247 STO_MIPS_PLT 0x8 R_AARCH64_TLSDESC_LD64_LO12 563 RHF_SGI_ONLY (1 << 4) R_SH_DIR8L 9 R_OR1K_TLS_IE_LO16 29 R_TILEPRO_IMM8_X0_TLS_GD_ADD 61 R_CKCORE_GOTPC_LO16 27 R_CKCORE_ADDRGOT 17 AT_SECURE 23 R_IA64_PCREL21M 0x4a R_AARCH64_TLSLD_LD_PREL19 522 R_TILEGX_IMM8_X0_TLS_ADD 118 R_ALPHA_TPRELLO 40 R_PARISC_TLS_LDM21L 237 DT_LOPROC 0x70000000 R_SPARC_PC_LM22 39 LL_REQUIRE_MINOR (1 << 2) ET_EXEC 2 EM_MMIX 80 R_ALPHA_TLS_GD_HI 28 R_PPC64_ADDR16_HA R_PPC_ADDR16_HA ELFCOMPRESS_LOOS 0x60000000 R_IA64_COPY 0x84 R_PPC64_ADDR16_HIGHESTA 42 R_TILEPRO_MMSTART_X0 47 R_PPC_GOT_TPREL16_HA 90 R_LARCH_TLS_DTPMOD64 7 R_M32R_NUM 256 R_MIPS_CALL_LO16 31 R_TILEGX_IMM16_X1_HW2_PLT_PCREL 71 R_MICROMIPS_GOT_DISP 145 SHT_CSKY_ATTRIBUTES (SHT_LOPROC + 1) _ELF_H 1 R_NIOS2_TLS_IE16 31 NT_RISCV_VECTOR 0x901 DF_1_LOADFLTR 0x00000010 R_LARCH_TLS_LD_PCREL20_S2 124 EF_CSKY_ABIV1 0X10000000 R_IA64_DIR64MSB 0x26 R_NIOS2_GOT16 22 R_PARISC_GPREL14R 30 R_390_PC32DBL 19 GNU_PROPERTY_LOPROC 0xc0000000 NT_ARM_TLS 0x401 R_MN10300_COPY 20 R_RISCV_SUB16 38 R_TILEGX_8 4 R_PPC_REL16_LO 250 R_ARC_S21W_PCREL_PLT 0x3C EF_ARM_APCS_FLOAT 0x10 DT_RUNPATH 29 R_MICROBLAZE_COPY 21 ELFCOMPRESS_ZLIB 1 R_ARM_TLS_LDO32 106 R_SH_SWITCH32 26 AT_L3_CACHEGEOMETRY 47 PF_ARM_SB 0x10000000 OEX_SMM 0x20000 R_PPC_TPREL32 73 EF_MIPS_PIC 2 R_PPC_GOT16_HI 16 R_PARISC_PCREL14R 14 R_OR1K_TLS_GD_LO16 23 VER_NEED_NUM 2 EM_KMX32 211 R_ARM_ALU_SBREL_27_20 37 R_390_GOTPLTENT 33 EM_FIREPATH 78 SHT_MIPS_DELTACLASS 0x7000001d R_TILEPRO_IMM16_X0_TLS_LE_HA 91 R_386_NONE 0 R_PPC_PLTREL32 28 R_RISCV_GOT_HI20 20 R_68K_TLS_LDO8 33 R_ARC_JLI_SECTOFF 0x3F R_390_RELATIVE 12 R_RISCV_IRELATIVE 58 R_PPC64_IRELATIVE 248 R_MIPS_GOT_HI16 22 GNU_PROPERTY_1_NEEDED GNU_PROPERTY_UINT32_OR_LO R_PARISC_LTOFF16DF 103 R_PPC_EMB_SDA2REL 108 SHT_MIPS_XLATE 0x70000024 R_68K_JMP_SLOT 21 EF_ALPHA_32BIT 1 R_TILEPRO_BROFF_X1 14 EF_PPC_RELOCATABLE 0x00010000 R_METAG_TLS_DTPMOD 57 R_ARM_LDRS_PC_G0 64 R_390_PLT32DBL 20 R_ARM_V4BX 40 EF_ARM_EABI_VER2 0x02000000 EF_ARC_ALL_MSK (EF_ARC_MACH_MSK | EF_ARC_OSABI_MSK) R_PPC_TOC16 255 EM_AVR32 185 R_IA64_LTV32MSB 0x74 ELFDATANONE 0 EM_FR30 84 R_SH_TLS_LD_32 145 PT_PARISC_ARCHEXT 0x70000000 NT_FDO_DLOPEN_METADATA 0x407c0c0a R_386_TLS_LDM_POP 31 R_PARISC_TPREL16F 221 DF_P1_LAZYLOAD 0x00000001 NT_ARM_SYSTEM_CALL 0x404 R_ARM_PC13 4 R_AARCH64_MOVW_GOTOFF_G0 300 R_AARCH64_TLSLD_ADD_DTPREL_HI12 528 R_390_TLS_IEENT 49 R_ARC_S25W_PCREL_PLT 0x4C EM_K10M 181 EM_M32R 88 RHF_REQUICKSTART (1 << 10) EF_MIPS_ABI 0x0000F000 R_MICROMIPS_CALL_HI16 153 EM_ECOG1X 168 R_TILEGX_IMM16_X1_HW1_LAST_PCREL 61 R_PPC64_GOT_TLSGD16 79 R_OR1K_GNU_VTENTRY 7 R_ARM_PLT32 27 R_TILEPRO_IMM16_X1_TLS_IE_HI 79 R_LARCH_SOP_ADD 35 R_SH_REL32 2 R_SPARC_PC10 16 R_TILEPRO_GLOB_DAT 11 R_TILEPRO_MT_IMM15_X1 21 SHN_HIOS 0xff3f R_PARISC_TLS_DTPOFF32 244 R_PPC_EMB_BIT_FLD 115 R_PPC_DTPREL32 78 R_SPARC_TLS_IE_LD 69 R_SPARC_WDISP16 40 EM_TILEGX 191 R_M32R_GOT16_HI_SLO 57 EM_V800 36 PT_HP_CORE_SHM (PT_LOOS + 0x8) R_SPARC_GLOB_DAT 20 SHF_MIPS_NAMES 0x02000000 EM_M32C 120 R_CKCORE_GOT_IMM18BY4 48 R_TILEPRO_JMP_SLOT 12 R_386_TLS_LE_32 34 R_SH_NUM 256 DT_MIPS_LOCAL_GOTNO 0x7000000a R_TILEPRO_IMM16_X1_TLS_IE_LO 77 R_PARISC_TLS_LE21L R_PARISC_TPREL21L R_METAG_TLS_LE_HI16 60 OHW_R5KEOP 0x4 R_AARCH64_TLSLE_LDST8_TPREL_LO12 552 R_RISCV_TPREL_LO12_S 31 R_IA64_LTOFF_FPTR22 0x52 EF_MIPS_MACH_4111 0x00880000 R_TILEGX_IMM16_X1_HW0_PCREL 51 R_IA64_DTPREL32MSB 0xb4 R_68K_TLS_LDO32 31 R_PPC_SECTOFF 33 R_PPC64_PLT16_LO_DS 60 STO_MIPS_HIDDEN 0x2 R_NIOS2_IMM8 8 R_METAG_LOADDR16 1 EM_BA1 201 R_PARISC_PLABEL21L 66 R_TILEPRO_8_PCREL 6 R_MN10300_GOT16 19 R_LARCH_TLS_DESC_PCREL20_S2 126 R_ARC_SECTOFF_U8 0x21 R_SPARC_PCPLT10 29 DT_MIPS_GP_VALUE 0x70000030 R_X86_64_TPOFF32 23 PF_R (1 << 2) EF_MIPS_ARCH_2 0x10000000 R_AARCH64_LDST32_ABS_LO12_NC 285 R_390_TLS_IE32 47 ELFOSABI_ARM 97 NT_LOONGARCH_HW_BREAK 0xa05 DT_DEBUG 21 R_TILEPRO_IMM16_X1_TLS_LE 86 PF_HP_FAR_SHARED 0x00200000 PT_HP_CORE_PROC (PT_LOOS + 0x5) R_SPARC_LM22 36 AT_BASE 7 EF_ARM_OLD_ABI 0x100 R_MIPS_SUB 24 R_ALPHA_HINT 8 R_IA64_DIR32LSB 0x25 R_386_16 20 R_PPC64_PLTGOT16_HA 55 DT_CHECKSUM 0x6ffffdf8 DT_GNU_CONFLICT 0x6ffffef8 EM_Z80 220 R_TILEGX_8_PCREL 8 R_M32R_18_PCREL 5 R_PPC_SECTOFF_LO 34 NT_MIPS_MSA 0x802 R_NIOS2_CALL26_NOAT 41 EI_MAG2 2 DT_SONAME 14 R_ALPHA_GPDISP 6 R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC 532 R_PARISC_PLTOFF14R 54 NT_PRXREG 4 MIPS_AFL_ASE_MCU 0x00000008 E_MIPS_ARCH_32 EF_MIPS_ARCH_32 ET_LOPROC 0xff00 R_PPC64_GOT_DTPREL16_HA 94 R_TILEGX_TLS_DTPMOD32 109 DF_1_PIE 0x08000000 R_CRIS_NUM 20 R_AARCH64_JUMP26 282 R_386_32 1 R_MIPS_JUMP_SLOT 127 PT_NUM 8 DT_ADDRNUM 11 PT_TLS 7 R_PPC_DTPREL16_HI 76 R_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL 97 R_TILEGX_SHAMT_X0 32 R_TILEGX_IMM16_X0_HW1_LAST_PCREL 60 R_ALPHA_TPRELHI 39 EM_MIPS_RS3_LE 10 EM_NONE 0 ELFCOMPRESS_HIOS 0x6fffffff EF_MIPS_ARCH_64R6 0xa0000000 R_M32R_HI16_ULO 7 DT_ADDRTAGIDX(tag) (DT_ADDRRNGHI - (tag)) R_TILEGX_JUMPOFF_X1 21 R_X86_64_RELATIVE64 38 R_AARCH64_GLOB_DAT 1025 R_LARCH_PCALA_HI20 71 R_TILEGX_64 1 R_MICROBLAZE_GNU_VTENTRY 12 R_ARM_TLS_DESC 13 VER_NDX_GLOBAL 1 SHT_ARM_EXIDX (SHT_LOPROC + 1) R_390_PLT32 8 R_ARM_RABS22 253 R_PPC_GOT_DTPREL16_LO 92 R_MIPS_ADD_IMMEDIATE 34 DT_STRTAB 5 R_TILEGX_IMM16_X0_HW0_TLS_LE 80 SHF_MIPS_STRINGS 0x80000000 EM_SEP 108 R_RISCV_ADD32 35 R_AARCH64_TLSDESC_ADR_PREL21 561 SHN_PARISC_HUGE_COMMON 0xff01 R_390_TLS_LE64 51 R_TILEPRO_IMM16_X0_HA 29 DT_MIPS_LOCAL_GOTIDX 0x70000026 R_MICROBLAZE_TLSGD 23 R_LARCH_GNU_VTENTRY 58 R_RISCV_PCREL_LO12_I 24 R_PPC64_REL16_HA 252 R_AARCH64_ADR_PREL_LO21 274 R_PPC_GOT_TLSGD16_HI 81 EM_CSR_KALIMBA 219 MIPS_AFL_EXT_5500 16 EM_ARCA 109 DT_SYMENT 11 R_OR1K_JMP_SLOT 20 R_SPARC_OLO10 33 PT_MIPS_REGINFO 0x70000000 R_RISCV_TPREL_HI20 29 R_PARISC_DPREL14R 22 EF_ARM_EABI_VER4 0x04000000 DT_MIPS_DELTA_INSTANCE 0x70000019 R_PARISC_TLS_DTPMOD32 242 R_NIOS2_HIADJ16 11 R_MIPS_INSERT_B 26 R_AARCH64_MOVW_UABS_G0_NC 264 AT_EGID 14 R_MICROMIPS_GOT_LO16 149 R_RISCV_SUB64 40 EF_SH2A_NOFPU 0x13 R_SH_TLS_IE_32 147 R_PPC64_RELATIVE R_PPC_RELATIVE R_TILEGX_IMM16_X1_HW0_TLS_LE 81 R_TILEGX_IMM16_X0_HW2_PCREL 54 DT_MIPS_PIXIE_INIT 0x70000023 R_METAG_GETSET_GOTOFF 34 NT_AUXV 6 R_IA64_FPTR32MSB 0x44 R_PPC_IRELATIVE 248 R_ALPHA_RELATIVE 27 R_SPARC_JMP_IREL 248 R_AARCH64_MOVW_PREL_G3 293 R_M32R_18_PCREL_RELA 37 DT_MIPS_AUX_DYNAMIC 0x70000031 EM_VIDEOCORE5 198 R_IA64_DTPREL22 0xb2 R_M32R_GLOB_DAT 51 ELFOSABI_MODESTO 11 PPC64_OPT_TLS 1 R_ARM_TLS_GOTDESC 90 R_390_GOTPLT20 59 R_TILEGX_IMM16_X0_HW2_PLT_PCREL 70 EM_68HC12 53 R_IA64_IMM14 0x21 PF_W (1 << 1) R_SPARC_5 44 R_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL 96 EM_PARISC 15 EF_MIPS_MACH_4650 0x00850000 R_386_32PLT 11 R_SH_GOTPC 167 R_SH_DIR8WPL 5 R_AARCH64_MOVW_UABS_G1 265 R_ARM_ALU_PCREL_7_0 32 R_MIPS_LITERAL 8 R_METAG_REL8 15 R_MICROMIPS_SUB 150 SHT_LOOS 0x60000000 NT_PPC_TM_CVMX 0x10a R_RISCV_SET8 54 DT_MIPS_DELTA_RELOC_NO 0x7000001c R_SPARC_TLS_LDM_ADD 62 R_MICROMIPS_JALR 156 R_AARCH64_ABS16 259 R_ARC_TLS_LE_S9 0x4A ODK_REGINFO 1 NT_PRCRED 14 AT_ICACHEBSIZE 20 EF_MIPS_MACH_OCTEON2 0x008d0000 R_TILEPRO_IMM16_X0_HI_PCREL 35 ODK_HWAND 7 DT_MIPS_UNREFEXTNO 0x70000012 SHT_HISUNW 0x6fffffff R_PARISC_PCREL16F 77 R_MIPS16_TLS_LDM 107 EF_IA_64_ABI64 0x00000010 GNU_PROPERTY_AARCH64_FEATURE_1_AND 0xc0000000 R_RISCV_TLS_DTPMOD64 7 SHT_RISCV_ATTRIBUTES (SHT_LOPROC + 3) DT_MIPS_XHASH 0x70000036 R_MN10300_GNU_VTENTRY 8 R_PPC_DIAB_SDA21_HI 181 R_MICROMIPS_GPREL16 136 R_OR1K_8_PCREL 11 R_AARCH64_TLSDESC 1031 R_AARCH64_LDST64_ABS_LO12_NC 286 R_MICROMIPS_HI16 134 R_390_32 4 R_PARISC_TLS_TPREL32 R_PARISC_TPREL32 R_PARISC_LTOFF14WR 99 EM_S390 22 GNU_PROPERTY_X86_FEATURE_1_SHSTK (1U << 1) R_PPC64_DTPREL16_LO_DS 102 R_ALPHA_GPREL16 19 R_M32R_26_PLTREL 49 ELFCLASS32 1 DT_VALTAGIDX(tag) (DT_VALRNGHI - (tag)) R_PARISC_TLS_GD14R 235 AT_PLATFORM 15 R_386_NUM 44 NT_MIPS_DSP 0x800 R_X86_64_GOTPC32_TLSDESC 34 SHT_PREINIT_ARRAY 16 R_METAG_REG16OP3 11 DT_PLTPADSZ 0x6ffffdf9 DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d DT_RELCOUNT 0x6ffffffa RHF_REQUICKSTARTED (1 << 11) R_PARISC_GPREL14DR 92 R_AARCH64_TLSDESC_ADD 568 R_AARCH64_TLSLD_LDST128_DTPREL_LO12 572 R_ARM_RXPC25 249 R_ARC_S13_PCREL 0x19 R_CKCORE_PLT12 33 R_ARM_TLS_IE12GP 111 EM_TINYJ 61 EF_MIPS_MACH_XLR 0x008c0000 EF_RISCV_TSO 0x0010 EM_TPC 98 SHF_IA_64_NORECOV 0x20000000 R_MN10300_16 2 R_RISCV_SET_ULEB128 60 AT_L1I_CACHEGEOMETRY 41 R_MN10300_TLS_LDO 26 R_TILEGX_IMM16_X1_HW3_PLT_PCREL 77 R_MIPS_PC18_S3 62 R_TILEPRO_IMM8_Y0 18 R_MIPS16_LO16 105 EV_CURRENT 1 R_IA64_LTV64MSB 0x76 R_SPARC_LO10 12 R_IA64_IPLTLSB 0x81 EI_MAG1 1 R_PARISC_PLTOFF21L 50 EM_TRICORE 44 R_390_TLS_LDO32 52 R_TILEGX_IMM16_X1_HW0_LAST_PCREL 59 R_CRIS_32_GOTPLT 16 R_PARISC_SEGBASE 48 EV_NUM 2 SHT_LOUSER 0x80000000 R_ARC_SDA 0xC R_MIPS_EH 249 R_NIOS2_LO16 10 R_RISCV_TPREL_ADD 32 EF_ARM_ABI_FLOAT_HARD 0x400 R_OR1K_TLS_LDM_LO16 25 EF_ARM_SOFT_FLOAT 0x200 R_TILEGX_IMM16_X0_HW0_LAST 44 _U 0x01 R_PPC_SECTOFF_HI 35 R_386_GOT32X 43 R_RISCV_NUM 66 R_TILEPRO_IMM16_X1_TLS_LE_HA 92 NT_UTSNAME 15 DT_X86_64_PLT (DT_LOPROC + 0) R_ARM_RELATIVE 23 R_CRIS_16_GOTPLT 15 DT_PPC_OPT (DT_LOPROC + 1) R_SPARC_8 1 R_SPARC_TLS_IE_LO10 68 ELF64_M_SIZE(info) ELF32_M_SIZE (info) OPAD_POSTFIX 0x2 NT_GNU_HWCAP 2 STT_ARM_16BIT STT_HIPROC R_LARCH_TLS_DESC64_PC_HI12 114 AT_HWCAP4 30 R_TILEGX_64_PCREL 5 R_NIOS2_GNU_VTINHERIT 16 R_SPARC_TLS_GD_LO10 57 R_OR1K_TLS_DTPOFF 33 R_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL 94 R_TILEPRO_MF_IMM15_X1 22 R_SPARC_COPY 19 EM_H8S 48 DT_PPC_GOT (DT_LOPROC + 0) R_AARCH64_LDST128_ABS_LO12_NC 299 SHF_COMPRESSED (1 << 11) EM_ALTERA_NIOS2 113 DT_ADDRRNGHI 0x6ffffeff R_AARCH64_TLSLD_LDST32_DTPREL_LO12 535 R_METAG_REG32OP4 12 E_MIPS_ARCH_64 EF_MIPS_ARCH_64 R_NIOS2_TLS_DTPMOD 33 R_AARCH64_ADD_ABS_LO12_NC 277 EF_CPU32 0x00810000 R_PPC64_REL16_LO 250 R_CKCORE_PCREL_IMM10BY4 23 DT_MIPS_RWPLT 0x70000034 MIPS_AFL_EXT_OCTEON2 2 R_NIOS2_GPREL 15 DT_PPC64_OPDSZ (DT_LOPROC + 2) EM_ARCV2 195 LITUSE_ALPHA_TLS_GD 4 R_386_TLS_GOTDESC 39 R_PPC_LOCAL24PC 23 MIPS_AFL_EXT_OCTEONP 3 AT_CLKTCK 17 R_NDS32_JMP_SLOT 41 DT_EXTRATAGIDX(tag) ((Elf32_Word)-((Elf32_Sword) (tag) <<1>>1)-1) NT_LOONGARCH_LBT 0xa04 RHF_NO_UNRES_UNDEF (1 << 13) STB_HIPROC 15 R_386_GLOB_DAT 6 R_ARM_MOVW_BREL 86 R_IA64_GPREL64MSB 0x2e R_PARISC_COPY 128 DT_MIPS_LIBLIST 0x70000009 R_MICROBLAZE_32_PCREL 2 SELFMAG 4 R_ARM_RBASE 255 R_LARCH_RELAX 100 R_ARM_LDRS_SB_G1 79 ELF32_M_SYM(info) ((info) >> 8) EF_MIPS_ARCH_64 0x60000000 NT_S390_PREFIX 0x305 R_ARC_H30 0x7 R_TILEGX_IMM16_X1_HW3_PCREL 57 R_METAG_HI16_GOTOFF 32 EM_EMX16 212 R_IA64_GPREL32MSB 0x2c R_AARCH64_TLSGD_ADR_PREL21 512 R_M32R_REL32 45 R_LARCH_SOP_PUSH_PCREL 22 R_MN10300_GOT32 17 R_LARCH_ADD8 47 R_ALPHA_DTPREL16 36 EM_NDS32 167 R_TILEGX_GLOB_DAT 17 R_LARCH_CALL36 110 DT_POSFLAG_1 0x6ffffdfd R_TILEGX_IMM16_X0_HW1_LAST 46 ELFMAG3 'F' R_PPC64_GOT_DTPREL16_LO_DS 92 AT_RSEQ_ALIGN 28 DT_MIPS_COMPACT_SIZE 0x7000002f R_390_TLS_DTPOFF 55 EM_CRAYNV2 172 DT_MIPS_DELTA_RELOC 0x7000001b R_IA64_TPREL14 0x91 R_ALPHA_COPY 24 R_IA64_TPREL64I 0x93 R_LARCH_SOP_PUSH_TLS_TPREL 26 EF_PARISC_WIDE 0x00080000 NT_GNU_ABI_TAG 1 ODK_EXCEPTIONS 2 EF_MIPS_ARCH_1 0x00000000 R_MICROMIPS_TLS_DTPREL_HI16 164 SHT_MIPS_IFACE 0x7000000b R_MICROBLAZE_SRW32 8 SHT_HIOS 0x6fffffff OEX_FPU_UFLO 0x02 EM_XGATE 115 R_M32R_RELA_GNU_VTINHERIT 43 R_IA64_LTOFF_FPTR32MSB 0x54 R_SPARC_PCPLT22 28 GNU_PROPERTY_STACK_SIZE 1 R_390_PC64 23 EM_MCHP_PIC 204 R_METAG_COPY 43 R_SH_GOTOFF 166 EM_TI_C5500 142 R_METAG_TLS_LE 59 PT_HP_CORE_COMM (PT_LOOS + 0x4) R_PPC64_ADDR16_HI R_PPC_ADDR16_HI PPC64_OPT_LOCALENTRY 4 R_RISCV_ALIGN 43 R_PPC64_REL64 44 R_MN10300_TLS_LD 25 GNU_PROPERTY_UINT32_AND_HI 0xb0007fff R_PARISC_TLS_GD21L 234 R_PPC_EMB_NADDR32 101 R_ARC_SECTOFF_S9 0x22 EM_QDSP6 164 DT_MIPS_CONFLICTNO 0x7000000b PT_MIPS_OPTIONS 0x70000002 DF_1_INITFIRST 0x00000020 R_TILEPRO_IMM8_Y1_TLS_GD_ADD 64 SHT_MIPS_EVENTS 0x70000021 R_NIOS2_PCREL16 3 NT_GNU_BUILD_ID 3 RHF_GUARANTEE_START_INIT (1 << 7) DT_SYMINSZ 0x6ffffdfe NT_PPC_TAR 0x103 R_IA64_LTV32LSB 0x75 R_ARM_THM_MOVW_BREL_NC 87 NT_PPC_VSX 0x102 R_LARCH_GOT_PC_HI20 75 R_NIOS2_PCREL_LO 26 SHF_MIPS_MERGE 0x20000000 EF_IA_64_ARCH 0xff000000 R_M32R_GOTPC_HI_ULO 59 SHT_LOSUNW 0x6ffffffa R_TILEGX_IMM16_X1_HW1_LAST_TLS_LE 85 R_CRIS_16_PCREL 5 PT_RISCV_ATTRIBUTES (PT_LOPROC + 3) R_CKCORE_GOTOFF 13 R_METAG_TLS_DTPOFF 58 EM_PCP 55 R_390_64 22 PF_MASKOS 0x0ff00000 R_390_TLS_LE32 50 R_SH_COUNT 28 SHF_MIPS_LOCAL 0x04000000 EM_TI_C2000 141 R_390_TLS_GD64 41 R_CKCORE_ADDRGOT_HI16 36 R_SPARC_DISP8 4 R_ARM_TLS_GD32 104 R_MICROMIPS_TLS_LDM 163 R_AARCH64_TLSLD_LDST16_DTPREL_LO12 533 SHT_MIPS_CONTENT 0x7000000c ET_DYN 3 R_SPARC_GOT10 13 R_AARCH64_TLSLE_MOVW_TPREL_G0_NC 548 ELF32_R_TYPE(val) ((val) & 0xff) R_PPC64_ADDR16_HIGHERA 40 R_PARISC_SECREL64 104 MIPS_AFL_ASE_SMARTMIPS 0x00000080 R_OR1K_16 2 R_MN10300_SYM_DIFF 33 R_SH_GLOB_DAT 163 R_TILEPRO_IMM16_X0_TLS_IE_HA 80 R_386_TLS_DTPOFF32 36 STB_GNU_UNIQUE 10 R_ARM_TLS_LDM32 105 PF_ARM_PI 0x20000000 R_IA64_GPREL32LSB 0x2d R_MIPS_GOT_PAGE 20 R_PPC_ADDR14 7 R_TILEGX_IMM8_X1_TLS_GD_ADD 114 EFA_PARISC_1_0 0x020b EF_SH2A_SH4 0x17 EF_MIPS_ABI_O64 0x00002000 EF_RISCV_FLOAT_ABI_DOUBLE 0x0004 R_PPC_PLT16_HA 31 DT_RISCV_VARIANT_CC (DT_LOPROC + 1) isupper(c) ((__ismask(c)&(_U)) != 0) R_CKCORE_ADDR32 1 R_SH_DIR8WPN 3 R_IA64_LTOFF22X 0x86 R_AARCH64_TLSLD_LDST64_DTPREL_LO12 537 SYMINFO_CURRENT 1 R_AC_SECTOFF_S9 0x26 SHN_COMMON 0xfff2 EM_TILE64 187 SHF_MIPS_NOSTRIP 0x08000000 R_CKCORE_PCREL_IMM16BY2 20 R_SPARC_TLS_IE_HI22 67 SHT_MIPS_REGINFO 0x70000006 R_390_GLOB_DAT 10 R_68K_TLS_DTPREL32 41 PT_HP_FASTBIND (PT_LOOS + 0x11) _ctype R_PPC64_DTPREL16 74 R_390_TLS_LDCALL 39 R_LARCH_SOP_POP_32_S_0_5_10_16_S2 44 R_ARM_LDR_SB_G0 75 R_ARC_SDA16_LD 0x16 R_OR1K_TLS_LE_HI16 30 R_ARC_SDA_12 0x2D SHT_MIPS_XLATE_OLD 0x70000028 EM_MANIK 171 R_PPC64_TPREL16 69 R_TILEPRO_SHAMT_Y1 54 MIPS_AFL_EXT_OCTEON 5 R_SPARC_WDISP19 41 R_68K_16 2 R_AARCH64_CALL26 283 ELF32_ST_BIND(val) (((unsigned char) (val)) >> 4) R_SPARC_DISP32 6 R_LARCH_SOP_SR 34 DT_SYMINFO 0x6ffffeff DF_BIND_NOW 0x00000008 R_M32R_32 2 R_PPC64_GOT16_DS 58 R_TILEGX_TLS_IE_LOAD 117 R_ARM_ALU_SB_G2 74 SHN_PARISC_ANSI_COMMON 0xff00 R_IA64_SECREL64LSB 0x67 R_PPC64_DTPREL16_HIGH 114 R_SPARC_TLS_GD_HI22 56 R_AARCH64_TLSLD_ADR_PAGE21 518 EM_CR 103 R_ALPHA_TPREL64 38 R_MN10300_GOTOFF16 14 EF_CSKY_ABIMASK 0XF0000000 DF_1_DISPRELPND 0x00010000 EM_68K 4 R_OR1K_32 1 R_NDS32_TLS_TPOFF 102 EM_BA2 202 R_CKCORE_GOTOFF_LO16 29 R_PARISC_TPREL14DR 220 R_ARC_PC32 0x32 R_PARISC_TLS_DTPMOD64 243 EM_ETPU 178 R_LARCH_MARK_LA 20 MIPS_AFL_EXT_4100 9 DT_MIPS_CXX_FLAGS 0x70000022 R_AARCH64_TLSLE_LDST32_TPREL_LO12 556 R_SPARC_DISP64 46 DT_LOOS 0x6000000d R_MN10300_TLS_DTPOFF 31 R_MIPS16_GOT16 102 R_PPC64_PLT16_HA R_PPC_PLT16_HA NT_LOONGARCH_LASX 0xa03 EM_RL78 197 R_TILEGX_16 3 R_CKCORE_TLS_LDO32 55 R_TILEGX_IMM16_X1_HW1 39 NT_PPC_DSCR 0x105 R_METAG_GOTOFF 41 EF_MIPS_UCODE 16 ELFOSABI_OPENBSD 12 R_OR1K_TLS_LDO_LO16 27 R_SPARC_NONE 0 R_ARC_TLS_GD_LD 0x46 NT_PRFPREG 2 R_TILEGX_BROFF_X1 20 R_TILEPRO_IMM16_X0_PCREL 31 NT_RISCV_TAGGED_ADDR_CTRL 0x902 EM_STXP7X 166 PT_HP_CORE_MMF (PT_LOOS + 0x9) R_PPC_EMB_NADDR16_HA 105 EF_RISCV_FLOAT_ABI_QUAD 0x0006 DF_1_TRANS 0x00000200 R_TILEGX_IMM16_X0_HW0 36 R_386_TLS_IE_32 33 EM_MN10300 89 _D 0x04 SHF_MIPS_GPREL 0x10000000 EM_SHARC 133 R_390_TLS_GOTIE64 44 R_PPC64_GOT_TLSLD16_HA 86 R_MIPS16_26 100 R_TILEGX_SHAMT_Y0 34 R_ALPHA_REFLONG 1 MIPS_AFL_EXT_4120 14 R_390_GOT16 15 PT_LOSUNW 0x6ffffffa SHT_MIPS_LOCSYM 0x70000015 RHF_QUICKSTART (1 << 0) ELFOSABI_IRIX 8 R_PARISC_TLS_IE14R R_PARISC_LTOFF_TP14R EF_SH2E 0xb EF_ARM_LE8 0x00400000 ELFOSABI_HPUX 1 R_ARC_GOT32 0x3B R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC 555 R_RISCV_TLS_GD_HI20 22 LITUSE_ALPHA_ADDR 0 EM_COREA_2ND 194 DT_HIOS 0x6ffff000 R_PARISC_TPREL16WF 222 R_68K_TLS_IE8 36 SHT_NOBITS 8 EF_SH3_NOMMU 0x14 ELF64_M_SYM(info) ELF32_M_SYM (info) kallsyms2elf_type SHT_GNU_verdef 0x6ffffffd R_SPARC_TLS_LDO_LOX10 65 R_ARM_LDRS_PC_G1 65 R_LARCH_SOP_POP_32_U_10_12 39 EF_SH4A 0xc R_LARCH_SOP_PUSH_DUP 24 MIPS_AFL_REG_128 0x03 R_LARCH_32_PCREL 99 R_AARCH64_ADR_PREL_PG_HI21_NC 276 R_TILEPRO_IMM16_X0_TLS_LE_LO 87 SHT_MIPS_DELTAINST 0x7000001c R_TILEGX_IMM8_X0_TLS_GD_ADD 113 EF_ARM_MAVERICK_FLOAT 0x800 GRP_COMDAT 0x1 SHT_ARM_PREEMPTMAP (SHT_LOPROC + 2) R_NIOS2_JUMP_SLOT 38 EM_ST200 100 R_X86_64_GOTPCRELX 41 AT_L2_CACHESHAPE 36 R_ARC_SDA16_LD2 0x18 R_MIPS_64 18 R_SPARC_TLS_LDO_HIX22 64 DT_AARCH64_VARIANT_PCS (DT_LOPROC + 5) R_PARISC_TPREL14WR 219 R_390_IRELATIVE 61 R_PARISC_LTOFF_TP14R 166 R_TILEGX_TLS_DTPMOD64 106 isdigit(c) __builtin_isdigit(c) R_MIPS_SCN_DISP 32 R_OR1K_COPY 18 R_68K_COPY 19 EF_SPARC_32PLUS 0x000100 EF_ARM_ABI_FLOAT_SOFT 0x200 ELF32_M_INFO(sym,size) (((sym) << 8) + (unsigned char) (size)) R_386_TLS_GD_PUSH 25 AT_L1D_CACHEGEOMETRY 43 R_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL 99 EF_MIPS_ARCH_32 0x50000000 R_MN10300_8 3 R_PPC64_TPREL16_DS 95 R_NIOS2_GLOB_DAT 37 EI_PAD 9 PT_GNU_STACK 0x6474e551 DT_GNU_LIBLIST 0x6ffffef9 PF_HP_LAZYSWAP 0x04000000 R_ARM_GNU_VTINHERIT 101 R_390_PLT16DBL 18 R_PARISC_LTOFF_FPTR16WF 126 R_386_IRELATIVE 42 R_TILEPRO_IMM16_X0_HA_PCREL 37 isprint(c) ((__ismask(c)&(_P|_U|_L|_D|_SP)) != 0) R_MN10300_PCREL16 5 R_CRIS_JUMP_SLOT 11 _C 0x08 R_386_TLS_DTPMOD32 35 DF_1_NOCOMMON 0x40000000 R_LARCH_SOP_IF_ELSE 37 DT_IA_64_PLT_RESERVE (DT_LOPROC + 0) R_MICROMIPS_PC7_S1 139 R_AARCH64_MOVW_UABS_G2 267 NT_ARM_PAC_MASK 0x406 R_LARCH_TLS_IE_PC_HI20 87 R_NIOS2_GOTOFF 40 R_MICROMIPS_CALL16 142 R_ARC_16 0x2 R_ALPHA_GPREL32 3 ELF64_ST_TYPE(val) ELF32_ST_TYPE (val) R_MIPS_TLS_TPREL_HI16 49 R_SPARC_WDISP30 7 SYMINFO_BT_LOWRESERVE 0xff00 NT_ARM_GCS 0x410 EF_ARM_PIC 0x20 SHF_TLS (1 << 10) EM_TI_ARP32 143 VER_FLG_WEAK 0x2 DF_1_NODUMP 0x00001000 R_PPC64_JMP_IREL 247 R_386_TLS_GD_POP 27 R_LARCH_TLS_LE64_HI12 86 SHF_GROUP (1 << 9) R_PARISC_TLS_LDO14R 241 R_LARCH_SUB_ULEB128 108 R_PARISC_PCREL22F 74 R_390_TLS_LDO64 53 EM_TI_PRU 144 R_IA64_SEGREL32MSB 0x5c R_METAG_GNU_VTINHERIT 30 MIPS_AFL_EXT_LOONGSON_3A 4 R_MIPS_GNU_REL16_S2 250 DT_DEPAUDIT 0x6ffffefb R_PPC64_DTPREL16_LO 75 SHF_PARISC_HUGE 0x40000000 AT_IGNOREPPC 22 R_AARCH64_LD_PREL_LO19 273 EM_MSP430 105 R_386_TLS_GD 18 DT_RELENT 19 R_SPARC_GOTDATA_LOX10 81 STO_MIPS_INTERNAL 0x1 R_LARCH_GOT64_HI12 82 R_ARM_PLT32_ABS 94 R_PARISC_LTOFF_FPTR14WR 123 R_SH_GNU_VTENTRY 35 R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC 527 R_NIOS2_TLS_LDO16 30 SHT_GROUP 17 R_PARISC_LTOFF_TP64 224 R_ARM_GOTRELAX 99 R_SPARC_H34 85 R_ALPHA_GLOB_DAT 25 R_MN10300_JMP_SLOT 22 __tolower EF_MIPS_ARCH 0xf0000000 R_METAG_REL16 16 R_386_TLS_LDM_32 28 EM_EXCESS 111 R_TILEGX_IMM8_Y0_TLS_ADD 120 R_SPARC_GOTDATA_HIX22 80 R_PPC_GOT16_HA 17 R_PPC_UADDR32 24 R_MICROBLAZE_TLSGOTTPREL32 28 EF_LARCH_ABI_MODIFIER_MASK 0x07 ELF_NOTE_OS_LINUX 0 R_X86_64_32S 11 R_LARCH_TLS_DESC_PC_LO12 112 R_68K_PLT16 14 DF_1_WEAKFILTER 0x20000000 R_LARCH_DELETE 101 R_TILEGX_IMM16_X0_HW0_LAST_TLS_IE 100 NT_LWPSTATUS 16 R_AARCH64_TLSLE_LDST128_TPREL_LO12 570 MIPS_AFL_ASE_MSA 0x00000200 ELFMAG0 0x7f R_METAG_REG32OP1 6 R_ARM_THM_MOVT_PREL 50 R_PPC_EMB_RELST_HA 114 EF_MIPS_MACH_5900 0x00920000 R_RISCV_HI20 26 OHWA1_R4KEOP_CLEAN 0x00000002 R_MIPS_PC21_S2 60 R_MIPS_GOT_DISP 19 R_PPC_JMP_SLOT 21 EM_SCORE7 135 NT_ARM_ZA 0x40c R_ARC_B22_PCREL 0x6 EM_RH32 38 R_PPC64_UADDR32 R_PPC_UADDR32 EF_LARCH_ABI_SOFT_FLOAT 0x01 R_ARC_SDA_LDST1 0x14 R_MIPS_GOT_OFST 21 R_PARISC_DIR64 80 R_PPC_DIAB_SDA21_LO 180 AT_L1D_CACHESHAPE 35 R_PPC64_TLSGD 107 R_TILEGX_IMM16_X1_HW2_LAST 49 R_68K_TLS_LE16 38 SHF_PARISC_SBP 0x80000000 R_MIPS16_GPREL 101 R_ARM_ALU_PC_G2 61 R_PPC_ADDR16 3 SHT_PARISC_EXT 0x70000000 ELFCLASSNUM 3 R_SH_GNU_VTINHERIT 34 R_SH_TLS_LDO_32 146 E_MIPS_ARCH_2 EF_MIPS_ARCH_2 R_TILEGX_TLS_GD_CALL 112 DT_INIT 12 R_METAG_TLS_LDO_HI16 49 R_TILEGX_MT_IMM14_X1 28 R_AARCH64_TLSLE_ADD_TPREL_LO12 550 R_SH_DIR8W 8 R_TILEPRO_IMM16_X0_TLS_IE 74 R_PPC64_SECTOFF R_PPC_SECTOFF EF_ARC_MACH_MSK 0x000000ff DT_PPC64_OPD (DT_LOPROC + 1) R_PPC64_TOC16_DS 63 SHF_ALPHA_GPREL 0x10000000 EM_S370 9 SHT_MIPS_OPTIONS 0x7000000d R_386_PLT32 4 OEX_DISMISS 0x80000 R_386_TLS_IE 15 R_TILEPRO_IMM16_X0_TLS_GD 66 R_RISCV_CALL 18 EM_LOONGARCH 258 first_read DT_TLSDESC_PLT 0x6ffffef6 R_AARCH64_TLSLD_ADD_DTPREL_LO12 529 R_SH_COPY 162 R_TILEGX_IMM16_X1_HW0_TLS_IE 93 NT_S390_GS_CB 0x30b R_LARCH_TLS_IE64_HI12 94 R_PPC64_TOC 51 R_ALPHA_JMP_SLOT 26 R_PPC64_TPREL16_HIGHA 113 E_MIPS_ARCH_4 EF_MIPS_ARCH_4 R_390_PLT64 25 SHT_MIPS_TRANSLATE 0x70000022 AT_FLAGS 8 R_LARCH_SOP_NOT 31 R_NIOS2_RELATIVE 39 R_PPC_GOT_TLSLD16_LO 84 R_ARM_SBREL32 9 R_LARCH_PCALA_LO12 72 R_MIPS_TLS_TPREL_LO16 50 SHT_DYNSYM 11 NT_RISCV_CSR 0x900 R_TILEPRO_MMEND_X1 50 R_MIPS16_TLS_GD 106 GNU_PROPERTY_UINT32_OR_HI 0xb000ffff R_TILEGX_IMM16_X0_HW0_LAST_TLS_GD 86 R_ALPHA_BRADDR 7 ODK_FILL 5 R_IA64_LTOFF_DTPMOD22 0xaa R_TILEPRO_IMM16_X1_TLS_GD_HI 71 R_PARISC_DIR17F 4 R_PPC_PLTREL24 18 R_PARISC_TPREL16DF 223 R_METAG_HIOG 13 EM_386 3 EM_DXP 112 R_390_GOT32 7 DF_1_DISPRELDNE 0x00008000 R_IA64_GPREL22 0x2a R_TILEPRO_IMM16_X1_TLS_IE_HA 81 ET_NUM 5 R_AARCH64_MOVW_GOTOFF_G1 302 ELF_NOTE_PAGESIZE_HINT 1 AT_PAGESZ 6 R_MICROBLAZE_TLSDTPREL32 26 NT_S390_LAST_BREAK 0x306 SHT_MIPS_ABIFLAGS 0x7000002a R_SPARC_RELATIVE 22 AT_UID 11 DT_IA_64_NUM 1 R_ARM_PC24 1 SHT_MIPS_PACKSYM 0x70000008 GNU_PROPERTY_X86_ISA_1_V2 (1U << 1) SYMINFO_FLG_LAZYLOAD 0x0008 R_TILEGX_IMM16_X0_HW1_LAST_TLS_IE 102 SHT_MIPS_OPTSYM 0x70000017 R_RISCV_SUB8 37 DT_MIPS_CONFLICT 0x70000008 ELF32_R_SYM(val) ((val) >> 8) PT_HP_CORE_VERSION (PT_LOOS + 0x2) PT_LOOS 0x60000000 SHF_MIPS_NODUPE 0x01000000 R_SH_TLS_LE_32 148 R_PARISC_PCREL14WR 75 PT_LOPROC 0x70000000 EF_MIPS_NOREORDER 1 R_TILEPRO_IMM16_X0_TLS_GD_LO 68 R_CKCORE_GOT_LO16 32 EM_COGE 216 R_NIOS2_BFD_RELOC_8 14 R_CKCORE_PLT_LO16 35 R_TILEGX_TLS_DTPOFF32 110 EI_OSABI 7 DT_X86_64_PLTENT (DT_LOPROC + 3) DF_1_ENDFILTEE 0x00004000 VER_NDX_LORESERVE 0xff00 SHN_LOPROC 0xff00 DF_1_NODEFLIB 0x00000800 R_PARISC_TLS_LDO21L 240 ET_HIOS 0xfeff R_ARM_GOT32 26 R_ARM_GLOB_DAT 21 R_SH_RELATIVE 165 R_PPC_DTPMOD32 68 LITUSE_ALPHA_BYTOFF 2 R_CKCORE_RELATIVE 9 R_M32R_RELATIVE 53 ELF_NOTE_GNU "GNU" R_SPARC_GNU_VTINHERIT 250 R_390_TLS_LDM32 45 R_PARISC_LTOFF_FPTR64 120 R_ARM_LDC_SB_G2 83 R_NDS32_COPY 39 R_PARISC_LTOFF_FPTR16DF 127 R_CKCORE_TOFFSET_LO16 41 DF_1_CONFALT 0x00002000 isalpha(c) ((__ismask(c)&(_U|_L)) != 0) R_386_SIZE32 38 R_TILEPRO_TLS_DTPOFF32 83 R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA R_TILEGX_IMM16_X0_HW1_LAST_TLS_LE 84 R_68K_PLT8O 18 ET_LOOS 0xfe00 R_PARISC_PLTOFF16WF 118 R_AARCH64_MOVW_SABS_G2 272 ET_HIPROC 0xffff SHN_LOOS 0xff20 DT_SYMTAB 6 R_CKCORE_PCREL_IMM18BY2 43 R_LARCH_ADD64 51 R_MIPS_PC19_S2 63 NT_PPC_TM_CGPR 0x108 NT_LOONGARCH_CSR 0xa01 PT_HP_CORE_STACK (PT_LOOS + 0x7) R_ARC_W 0x1A PT_HP_STACK (PT_LOOS + 0x14) R_X86_64_PC64 24 DF_1_NOHDR 0x00100000 R_390_PC16DBL 17 R_OR1K_GOTOFF_LO16 17 GNU_PROPERTY_AARCH64_FEATURE_1_BTI (1U << 0) EM_CSKY 252 R_LARCH_SOP_PUSH_TLS_GD 28 R_MIPS_NONE 0 SHT_ALPHA_REGINFO 0x70000002 R_ARM_REL32 3 R_390_TLS_IE64 48 R_390_TLS_GOTIE20 60 R_SPARC_GOT13 14 R_TILEPRO_NUM 130 R_ARC_RELATIVE 0x38 EF_MIPS_MACH_GS464 0x00A20000 R_ARC_SECTOFF_ME 0x1D R_TILEGX_IMM16_X0_HW1_LAST_TLS_GD 88 R_ARC_SDA16_ST2 0x30 R_AARCH64_TLSDESC_LDR 567 SYMINFO_NUM 2 R_MIPS16_TLS_DTPREL_LO16 109 DT_X86_64_PLTSZ (DT_LOPROC + 1) PT_MIPS_ABIFLAGS 0x70000003 R_ARM_NUM 256 STO_PPC64_LOCAL_MASK (7 << STO_PPC64_LOCAL_BIT) __STDC_VERSION__ 201112L R_SPARC_7 43 R_ARM_THM_JUMP19 51 R_PARISC_LTOFF_FPTR16F 125 EF_ARM_BE8 0x00800000 DT_VERSIONTAGIDX(tag) (DT_VERNEEDNUM - (tag)) R_PARISC_LTOFF_FPTR14DR 124 R_SPARC_UA16 55 R_PPC64_DTPREL16_HI 76 DT_MIPS_PERF_SUFFIX 0x7000002e EF_ARM_RELEXEC 0x01 R_390_PLTOFF16 34 R_MICROMIPS_PC10_S1 140 R_IA64_TPREL22 0x92 R_LARCH_SUB6 106 R_ARC_SDA_LDST2 0x15 R_IA64_DIR32MSB 0x24 R_IA64_GPREL64I 0x2b EM_MIPS_X 51 STT_HP_STUB (STT_LOOS + 0x2) R_NIOS2_CJMP 19 R_X86_64_GLOB_DAT 6 R_AARCH64_MOVW_SABS_G0 270 R_PPC64_TLS 67 EM_KVARC 214 R_LARCH_TLS_DTPREL32 8 EM_EMX8 213 R_390_GOTPC 14 EF_SPARC_LEDATA 0x800000 EM_COREA_1ST 193 R_SPARC_GLOB_JMP 42 isxdigit(c) ((__ismask(c)&(_D|_X)) != 0) STO_RISCV_VARIANT_CC 0x80 NT_PPC_HASHKEYR 0x112 R_ARM_MOVT_ABS 44 ELF_NOTE_OS_SOLARIS2 2 ELFMAG2 'L' RHF_DELTA_C_PLUS_PLUS (1 << 6) R_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL 95 EM_860 7 DT_FLAGS 30 ELFOSABI_ARM_AEABI 64 EF_LARCH_OBJABI_V1 0x40 R_MICROMIPS_GPREL7_S2 172 R_AARCH64_MOVW_GOTOFF_G2 304 R_SPARC_PC_HM10 38 SYMINFO_FLG_COPY 0x0004 EM_RISCV 243 DT_MIPS_BASE_ADDRESS 0x70000006 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC 551 R_PPC64_ADDR16_HIGHA 111 SYMINFO_BT_PARENT 0xfffe R_NIOS2_BFD_RELOC_16 13 R_SPARC_13 11 R_PARISC_NONE 0 R_CKCORE_ADDR_HI16 24 R_CRIS_GNU_VTENTRY 8 R_68K_PLT16O 17 R_TILEGX_IMM8_Y0 24 R_PPC64_DTPREL16_HIGHER 103 DF_1_KMOD 0x10000000 R_MIPS_SHIFT6 17 R_TILEPRO_IMM16_X0_GOT_LO 41 NT_PPC_TM_SPR 0x10c DF_TEXTREL 0x00000004 R_TILEGX_MMEND_X0 31 DT_TEXTREL 22 R_LARCH_TLS_DESC_LD 119 EM_ME16 59 R_NDS32_NONE 0 EF_MIPS_ARCH_64R2 0x80000000 R_RISCV_GOT32_PCREL 41 DT_MIPS_SYMBOL_LIB 0x70000024 R_ALPHA_DTPRELHI 34 R_NIOS2_CACHE_OPX 6 R_68K_PLT32O 16 R_MICROBLAZE_32 1 R_METAG_TLS_LDM 48 R_IA64_NONE 0x00 DT_AARCH64_BTI_PLT (DT_LOPROC + 1) R_TILEGX_MF_IMM14_X1 29 EF_SH4A_NOFPU 0x11 R_MICROMIPS_26_S1 133 SHN_LORESERVE 0xff00 DT_MIPS_DELTA_CLASS 0x70000017 R_AARCH64_ABS64 257 R_SPARC_32 3 R_PPC_GOT_TLSLD16 83 R_AARCH64_TLSGD_MOVW_G1 515 NT_TASKSTRUCT 4 R_LARCH_MARK_PCREL 21 AT_IGNORE 1 R_AARCH64_MOVW_GOTOFF_G0_NC 301 EF_S390_HIGH_GPRS 0x00000001 R_AARCH64_MOVW_UABS_G1_NC 266 VER_NDX_LOCAL 0 NT_PRFPXREG 20 R_IA64_LDXMOV 0x87 EM_FAKE_ALPHA 41 R_TILEPRO_MMSTART_X1 49 R_CKCORE_GOTPC 14 R_SPARC_WPLT30 18 R_X86_64_RELATIVE 8 ELFCLASS64 2 PT_HIOS 0x6fffffff SYMINFO_FLG_PASSTHRU 0x0002 R_SH_USES 27 R_PPC_EMB_SDA2I16 107 R_MIPS_INSERT_A 25 R_PPC_GOT_TLSLD16_HI 85 R_MN10300_32 1 R_CRIS_8_PCREL 4 EF_SH_MACH_MASK 0x1f DF_1_GROUP 0x00000004 EM_CE 119 EM_D30V 86 R_68K_PC16 5 R_ARM_THM_SWI8 14 ELF32_ST_INFO(bind,type) (((bind) << 4) + ((type) & 0xf)) EM_BLACKFIN 106 R_ARM_GOT_BREL12 97 R_ARM_ABS8 8 R_ARC_32_ME 0x1B R_METAG_REG32OP3 8 R_PPC64_DTPREL16_HIGHA 115 R_PPC64_TPREL16_HIGHER 97 EM_VISIUM 221 EM_H8_300 46 R_ARM_TLS_CALL 91 PT_SUNWSTACK 0x6ffffffb DT_PPC64_NUM 4 R_TILEGX_IMM16_X1_HW1_LAST_TLS_IE 103 R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC 557 SHN_AFTER 0xff01 EM_RS08 132 R_IA64_PCREL64LSB 0x4f ELF32_R_INFO(sym,type) (((sym) << 8) + ((type) & 0xff)) SHT_RELR 19 DTF_1_CONFEXP 0x00000002 DT_RPATH 15 DT_RELASZ 8 R_PPC64_GOT_TPREL16_LO_DS 88 R_LARCH_GOT64_PC_HI12 78 R_PPC64_ADDR24 R_PPC_ADDR24 R_TILEGX_IMM16_X0_HW0_TLS_IE 92 R_IA64_REL64LSB 0x6f R_ARC_SDA32_ME 0x1E R_NIOS2_BFD_RELOC_32 12 R_390_TLS_LOAD 37 R_X86_64_SIZE32 32 R_SPARC_PC_HH22 37 ELF64_M_INFO(sym,size) ELF32_M_INFO (sym, size) R_TILEGX_MMSTART_X0 30 _S 0x20 NT_X86_XSAVE_LAYOUT 0x205 R_PARISC_PCREL16DF 79 EM_CR16 177 SHT_MIPS_RFDESC 0x7000001a R_PARISC_GPREL14WR 91 R_TILEGX_IMM16_X1_HW1_LAST_GOT 75 R_MIPS_TLS_LDM 43 DT_MIPS_MSYM 0x70000007 R_TILEGX_IMM16_X0_HW3 42 R_PARISC_GNU_VTENTRY 232 R_68K_TLS_GD16 26 R_PPC_SECTOFF_HA 36 R_AARCH64_TLSGD_ADR_PAGE21 513 R_RISCV_TLS_TPREL32 10 STT_HP_OPAQUE (STT_LOOS + 0x1) R_PPC_TLSLD 96 R_PPC64_GOT_DTPREL16_DS 91 AT_PHENT 4 R_IA64_IMM22 0x22 ELFOSABI_SYSV 0 R_PARISC_PCREL32 9 R_AARCH64_TLS_TPREL 1030 R_CKCORE_GOT12 30 R_PPC64_PLTGOT16_DS 65 PT_GNU_SFRAME 0x6474e554 R_METAG_HI16_GOTPC 36 EF_SH4AL_DSP 0x6 DT_MIPS_HIDDEN_GOTIDX 0x70000027 PF_HP_MODIFY 0x02000000 R_MIPS16_TLS_GOTTPREL 110 R_LARCH_GNU_VTINHERIT 57 R_PARISC_LTOFF_TP14F 167 R_TILEGX_HW1 10 R_SPARC_REV32 252 R_X86_64_TLSLD 20 R_TILEPRO_TLS_IE_LOAD 65 R_PPC_GOT_TLSGD16_LO 80 R_RISCV_TLSDESC_HI20 62 R_IA64_LTOFF64I 0x33 R_ARM_JUMP24 29 DT_STRSZ 10 R_PPC64_GLOB_DAT R_PPC_GLOB_DAT R_SH_TLS_TPOFF32 151 R_ARC_SDA_LDST 0x13 R_MN10300_TLS_GD 24 R_LARCH_ADD24 49 STB_NUM 3 R_PPC_GOT_DTPREL16_HA 94 R_AARCH64_TLSLD_MOVW_DTPREL_G0 526 R_PPC64_PLTGOT16_HI 54 R_TILEGX_SHAMT_X1 33 R_ARC_8 0x1 STT_HIOS 12 EF_MIPS_MACH_4010 0x00820000 R_MICROBLAZE_32_PCREL_LO 4 R_LARCH_ABS64_LO20 69 R_IA64_IPLTMSB 0x80 R_RISCV_32_PCREL 57 EF_MIPS_NAN2008 1024 R_TILEGX_IMM16_X0_HW0_LAST_PCREL 58 R_AARCH64_ADR_GOT_PAGE 311 R_PPC64_TPREL16_HIGHEST 99 NT_LWPSINFO 17 EM_JAVELIN 77 R_TILEGX_IMM8_Y1_TLS_ADD 121 R_MN10300_GOT24 18 AT_SYSINFO_EHDR 33 R_IA64_PCREL21BI 0x79 R_386_PC32 2 SHT_NUM 20 R_PPC_REL32 26 R_OR1K_GOTPC_LO16 13 R_386_TLS_GOTIE 16 R_PARISC_SEGREL64 112 R_M32R_LO16_RELA 41 R_NIOS2_IMM5 5 R_CKCORE_PLT32 16 R_PARISC_LTOFF_FPTR14R 62 SHT_MIPS_RELD 0x70000009 R_TILEGX_TLS_DTPOFF64 107 R_NDS32_RELATIVE 42 R_METAG_RELATIVE 45 OHW_R5KCVTL 0x8 GNU_PROPERTY_X86_FEATURE_1_AND 0xc0000002 NT_ARM_PAC_ENABLED_KEYS 0x40a AT_HWCAP3 29 DTF_1_PARINIT 0x00000001 R_ALPHA_TLSGD 29 R_ARM_THM_PC12 54 R_PARISC_PLTOFF14DR 116 R_NIOS2_CALL_LO 44 R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC 540 SHF_MERGE (1 << 4) NT_S390_CTRS 0x304 process_symbol R_SH_DIR32 1 R_OR1K_TLS_LDO_HI16 26 R_M32R_24_RELA 35 DT_MOVETAB 0x6ffffefe R_LARCH_TLS_GD_HI20 98 R_ARM_GOT_PREL 96 R_AARCH64_LD64_GOTOFF_LO15 310 NT_ARM_POE 0x40f SHT_PROGBITS 1 R_390_TLS_GOTIE32 43 R_MN10300_TLS_DTPMOD 30 SHT_IA_64_UNWIND (SHT_LOPROC + 1) R_OR1K_8 3 NT_MIPS_FP_MODE 0x801 R_LARCH_B21 65 SHN_MIPS_SCOMMON 0xff03 R_OR1K_GNU_VTINHERIT 8 R_ARC_32 0x4 GNU_PROPERTY_X86_FEATURE_1_IBT (1U << 0) EM_MOXIE 223 R_ARC_TLS_IE_GOT 0x48 R_SPARC_TLS_LE_LOX10 73 GNU_PROPERTY_UINT32_OR_LO 0xb0008000 R_390_GOTOFF16 27 R_ARC_SECTOFF 0xD DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 SHT_PARISC_UNWIND 0x70000001 R_SPARC_SIZE32 86 STB_LOPROC 13 EF_MIPS_MACH_4120 0x00870000 R_LARCH_TLS_DESC64_LO20 117 R_ARC_N32_ME 0x1C R_68K_TLS_LDM32 28 R_TILEPRO_IMM16_X1_HA_PCREL 38 R_X86_64_8 14 R_TILEGX_IMM16_X0_HW1_PCREL 52 R_SH_GOT32 160 R_MN10300_TLS_IE 28 R_ALPHA_LITERAL 4 R_PARISC_PCREL16WF 78 DT_AARCH64_NUM 6 PT_SUNWBSS 0x6ffffffa R_PARISC_DIR21L 2 EM_CYPRESS_M8C 161 EF_SPARC_SUN_US3 0x000800 R_PARISC_FPTR64 64 R_SPARC_TLS_LE_HIX22 72 R_ALPHA_GOTDTPREL 32 ELF_NOTE_FDO "FDO" EM_MCST_ELBRUS 175 R_MICROBLAZE_REL 16 DF_1_NOKSYMS 0x00080000 R_PARISC_PLTOFF14WR 115 R_MIPS_PCHI16 64 R_TILEGX_IMM16_X0_HW3_PCREL 56 EF_SH1 0x1 R_TILEPRO_SHAMT_X1 52 R_TILEPRO_16 2 R_MICROBLAZE_PLT_64 15 DF_1_STUB 0x04000000 R_TILEGX_HW0_LAST 13 R_ARM_LDRS_SB_G0 78 NT_S390_TODPREG 0x303 R_TILEPRO_IMM16_X1_GOT_HI 44 R_PPC64_ADDR16_LO R_PPC_ADDR16_LO R_LARCH_SOP_PUSH_GPREL 25 R_LARCH_SUB64 56 NT_S390_VXRS_HIGH 0x30a RHF_NONE 0 R_SPARC_10 30 R_X86_64_16 12 R_LARCH_COPY 4 R_AARCH64_TLSLE_MOVW_TPREL_G0 547 DT_NEEDED 1 SHF_MASKOS 0x0ff00000 NT_ARM_VFP 0x400 MIPS_AFL_ASE_MDMX 0x00000010 EM_NDR1 57 fd/array.c /build/linux-edvhOs/linux-7.0.0/debian/build/tools-perarch/tools/lib/api /usr/lib/gcc/x86_64-linux-gnu/15/include /usr/include/x86_64-linux-gnu/bits /usr/include/x86_64-linux-gnu/bits/types /usr/include/x86_64-linux-gnu/sys /usr/include /usr/include/x86_64-linux-gnu/gnu /usr/include/linux /usr/include/x86_64-linux-gnu/asm /usr/include/asm-generic stddef.h struct_FILE.h poll.h stdio.h stdlib.h string.h stdc-predef.h libc-header-start.h features.h features-time64.h wordsize.h timesize.h cdefs.h long-double.h stubs.h stubs-64.h stdarg.h typesizes.h __fpos_t.h __mbstate_t.h __fpos64_t.h __FILE.h cookie_io_functions_t.h stdio_lim.h floatn.h floatn-common.h errno.h errno-base.h fcntl.h fcntl-linux.h struct_timespec.h endian.h endianness.h time_t.h struct_stat.h waitflags.h waitstatus.h clock_t.h clockid_t.h timer_t.h stdint-intn.h byteswap.h uintn-identity.h select.h __sigset_t.h struct_timeval.h pthreadtypes.h thread-shared-types.h pthreadtypes-arch.h atomic_wide_counter.h struct_mutex.h struct_rwlock.h alloca.h stdlib-float.h unistd.h posix_opt.h environments.h confname.h getopt_posix.h getopt_core.h unistd_ext.h __locale_t.h strings.h fs/fs.c fs/.. /build/linux-edvhOs/linux-7.0.0/debian/build/tools-perarch/tools/include/asm-generic /build/linux-edvhOs/linux-7.0.0/debian/build/tools-perarch/tools/include/uapi/asm-generic /build/linux-edvhOs/linux-7.0.0/debian/build/tools-perarch/tools/include/linux statfs.h pthread.h mount.h assert.h ctype.h syslimits.h posix1_lim.h local_lim.h pthread_stack_min-dynamic.h pthread_stack_min.h posix2_lim.h stdbool.h vfs.h sched.h struct_sched_param.h cpu-set.h time.h struct_tm.h struct_itimerspec.h setjmp.h struct___jmp_buf_tag.h stdint.h wchar.h stdint-uintn.h stdint-least.h ioctl.h ioctls.h sockios.h bitsperlong.h ioctl-types.h ttydefaults.h int-ll64.h posix_types.h posix_types_64.h debug-internal.h debug.h fs/tracing_path.c dirent.h once_flag.h error_t.h close_range.h tracing_path.h dirent_ext.h fs/cgroup.c stringify.h cpu.c cpu.h debug.c <built-in> ../str_error_r.c core.c /build/linux-edvhOs/linux-7.0.0/debian/build/tools-perarch/tools/lib/perf /build/linux-edvhOs/linux-7.0.0/debian/build/tools-perarch/tools/lib/perf/include/perf /build/linux-edvhOs/linux-7.0.0/debian/build/tools-perarch/tools/lib/perf/include/internal stdio2.h stdio2-decl.h cpumap.c /build/linux-edvhOs/linux-7.0.0/debian/build/tools-perarch/tools/include/asm/../../arch/x86/include/asm /build/linux-edvhOs/linux-7.0.0/debian/build/tools-perarch/tools/lib/api/fs refcount.h atomic.h string_fortified.h compiler.h cpumap.h threadmap.c threadmap.h evsel.c /build/linux-edvhOs/linux-7.0.0/debian/build/tools-perarch/tools/include/uapi/linux xyarray.h hash.h evsel.h perf_event.h mmap.h zalloc.h evlist.c /build/linux-edvhOs/linux-7.0.0/debian/build/tools-perarch/tools/lib/api/fd evlist.h unistd-decl.h mmap.c ring_buffer.h math64.h schedstat-v15.h schedstat-v16.h schedstat-v17.h mman.h ../../lib/zalloc.c ../../lib xyarray.c lib.c exec-cmd.c /build/linux-edvhOs/linux-7.0.0/debian/build/tools-perarch/tools/lib/subcmd subcmd-util.h subcmd-config.h compiler_types.h compiler-context-analysis.h compiler-gcc.h strings_fortified.h select2.h select-decl.h statx-generic.h struct_statx_timestamp.h struct_statx.h stdlib-bsearch.h exec-cmd.h help.c help.h termios.h termios-struct.h termios-c_cc.h termios-c_iflag.h termios-c_oflag.h termios-c_cflag.h termios-cbaud.h termios-c_lflag.h termios-tcflow.h termios-misc.h termios-baud.h pager.c run-command.h sigchain.h signal.h signum-generic.h signum-arch.h sig_atomic_t.h siginfo_t.h __sigval_t.h siginfo-arch.h siginfo-consts.h siginfo-consts-arch.h sigevent_t.h sigevent-consts.h sigaction.h sigcontext.h stack_t.h ucontext.h sigstksz.h ss_flags.h struct_sigstack.h sigthread.h signal_ext.h pager.h parse-options.c parse-options.h kernel.h build_bug.h math.h panic.h container_of.h run-command.c fcntl2.h wait.h struct_iovec.h falloc.h openat2.h fcntl-linux-fortify.h idtype_t.h sigchain.c subcmd-config.c /build/linux-edvhOs/linux-7.0.0/debian/build/tools-perarch/tools/lib/symbol kallsyms.c kallsyms.h elf.h 3                US	xx     S     PUU     PTT          ?U?EUEIUIJU            <T<DQDETEITIJT            7Q7DRDEQEIQIJQ   1Dp           <T<DQDETEITIJT          7Q7DRDEQEIQIJQ                             !"U""Q"#U##Q##U#$Q$$U$%Q%&&&U                   !"T"#T##T##T#$T$$T$%T%&&&T            ##0$$P$$s$$P%%0%&P              ##0$$R$$r$%R%%0%%R%&r&&r             ##0$%[%%L%%0%&[&&{&&[    %%P%&S  !"T    !"U""Q   ""U   ""T   ""0     ""0""R ""Q ""R   ##Q##Q   ##T##T   ##0     ##0##R ##T ##R  $$Q  $$P   $$T   $$R   $%[%%L  %%P    %%P%&S %%P %%1 %%P %%1  %%Q  %%P   %%T   %%R             USU!S!!U!!S                     T^T^ T  ^  T !^!!T!!^               P]!!P!!]!!P!!P!!]       U	| "  U !	| "            0UuUpy!!0           0RR!!0                 0tTtTXX!!0     P\   Q     T^   T   Q   0     0R ^ R     ^ T  T     Q Q  Q       0  0         0  R  0   Q   R  QQ  Q  U   ^   R QQ!!Q  Q  P     UU  	 U  U  u1         U\U\     PP   	S      0]]     UU  U  0     UU     TT     Ru         0q 1%q 1%#q~1%#q 1% U q 1% T q 1%  U T     UU     TX    UU      TXX      0TT     RR  U         PPq|P  U  P     UU     UU U  U  0     UU  U  0     UU   U     UU         TTTT    		  U  U  T         USUS  P  1   P  P  P  1  P  1                         UUUUUUPUQUP                      0P	0P00P0P0              PX		X		x		X	
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Y
00     0		0                0_		_	_0_0_                    0^U^		^	^0^0^   P                  0S		S	SS0S0S   x #+

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     0)  

U  


V'         y x ##  @         @sUs\U\U         @wTwTT        \su  $ &1$s|  $ &1$U $ &1$|  $ &1$U $ &1$     SS        0PpP0        0QqQ0      \sUs\U     {PS     {PSS    PS  1    PS  1    Us    T  |  $ &1$  S  P S p  S  Q      8U89U      8T89T    8U89U    8T89T       0P    PP     PS       PPR    YY  P    PP P 1 P 1    0TQ0             UUUXXU   UU   11   UU   PP    RR   QQ U 	U 	:g    	4 U Q R        QQQr      RRR U          UUUXX    p  $0.p  $0. U U U h    4       0)  p   
T&          UU    UU  U  U  P    qq  Q U 	U 	j    	4  U  Q  R  Q  R U   P   P  P  P  1  P  1     UU     TT       USU   P  P  P  1  P  1     UU             TTYYYY      0TT     RR  U     PP     	q 1$u "	q 1$u "  U  P     UU     TT   T   U         0	u U1%u U1%#u U21%#	u U1%     0Q U 	u U1% T Q                   Uup	U		U		U     	T		T     0P     UU         TTTT     UU                 USUSUUSU      USS   11     USS   PP    RR   QQ U 	U 	z    	4 U Q R        QQQr      RRR U        SUUS         0\T|\    p  $0.p  $0. S 	S S `|    4       0)   p   
T&          UU  U  U  P    qq  Q U 	U 	|~    	4  U  Q  R  Q  R U       U\^U         T]T]   SS               0_T0\T|\     0PS \   U|4$ 0  S  0  \   Q| 4$    Us  0    Q| 4$  S  1  S  1     UU     TT     UU     TT     QQ              :U:>U>aPa]P]        *T*I\IT       .:T:I|4$IT $ &#4$     6SS    CaPaj]  CjS  CI\    CI| s  $ &4$ZaQ    Cas  $ &#4$p "abs  $ &#4$} "  Cb0    CI| s  $ &4$ZaQ '%            46U66U         44T45T55T56T     46Q66Q      44044	44P550561         23U33R34H44U       23T34D44T     22Q24Q          23t GaL%#3$u "#33t GaL%#3$r "#34DGaL%#3$H"#44TGaL%#3$U"#44TGaL%#3$U"#     22P34P        23t GaL%34DGaL%44TGaL%44TGaL%     22P23x8    22P22p   22P 22T 224 22T  33P   34U   34DGaL%#3$r "#  34T   33P         33t33Q33a33t   33P   33U         33t33Q33a33t     12U22U         00U00\01|~11U    01U11S11U      01u 11S11U11S  01U  01u    11S  11P   11u  11P 11"    118           //U//S//U/0S00U             //T//U//L//T/0L00T             //Q//T//H//Q/0H00Q     ..U..U     ..U..U     --U--U         ++U+-\--U--\         ++T+-]--T--]            ++0+,^--^--^--P--^       +-_----_--_       ,,0,,S,,s,-S     ,,P,,P     ,,P,,^    ,,$@,-$@    ,,_,-_    ,,S,-S  ,,p  ps "p "#(   ,,P,,P   ,,	  $ &,,	  $ &   ,,S,,S ,,P ,,_ ,,S         )*U*+\++U++\++U        *+]++]++}++T++]    *+0++	++0   **P++|++|         **0**S**s++S++0   **u**P++|   **P    **\++\    **
$++
$    **0++0    **]++]    **S++S  **p } ps "p "#(   **P++P   **	}  $ &++	}  $ &   **S++S **P **] **S         ((U()\))U))\       ((T()]))T     ()S))s))S     ((P))P   ))P    ()
$))
$    ()0))0    ()]))]    ()S))S  ((p } ps "p "#(   ((P))P   ((	}  $ &))	}  $ &   ((S))S ((P ((] ((S         &&U&'\''U'(\((U        &']'']''}'(T((]    &'0''	'(0   &&P''|''|         &'0''S''s''S((0   &&u''P((|   ''P    ''\''\    ''
 $''
 $    ''0''0    '']'']    ''S''S  ''p } ps "p "#(   ''P''P   ''	}  $ &''	}  $ &   ''S''S ''P ''] ''S         $$U$&\&&U&&\       $$T$&]&&T       $%0%%S%&S&&S   %%P    %%\%%\    %%
 $%%
 $    %%0%%0     %%S%%S   %%P%%P   %%S%%S %%P %%S         ##U#$\$$U$$\       ##T#$]$$T     #$S$$s$$S     ##P$$P   #$P    ##
 $$$
 $    ##0$$0    ##]$$]    ##S$$S  ##p } ps "p "#(   ##P$$P   ##	}  $ &$$	}  $ &   ##S$$S ##P ##] ##S               USU S !U!"S"#U           TRTT#T       QY#Q         R\R#\          q z " $ &q z " $ &q z " $ &!"q z " $ &""~" $ &             X0 X!"X""""X       PPP!"P     USS   PP        8RZ8      0QQ    1u1   T   R   	y  $ &  T  R  Y  \\  00  ((  U  R  	y  $ & U R Y    SS          \\    PP    121           S !U""S""U"#U      !T""T"#T      !Q""Q"#Q      !\""\"#\           q t " $ &  	q  $ & !	s  $ &""	s  $ &"#	s  $ &            p r py "p "#(  T $ &p py "p "#(  !T $ &p Q $ &p"p "#(  )T $ &sQ $ &s#"s"#(  2T $ &U#Q $ &U##"U#"#(      s0  U#0           P !"""#P           1 !2!!t!!P!!p""1"#1   S""S    P""P        8UT""8      0Q""Q    1s""1    P    R    
Q $ &   P   T   Q     UU     TT     QQ        p t pq "p "#(ut u#q "u"#("T $ &uu#q "u"#()T $ &uQ $ &u#"u"#(  P  T  	q  $ & P T Q  P  T  	q  $ & P T Q             U]UU]U     TT       PP           0\|#\\           0__0_         S0SS       U^^   P    SS    	|  $ &	|  $ &    	  $ &	  $ &  S  \  _       ^^}     	|  $ &	|  $ &     	  $ &	  $ &  ^  \  _ P P      U]]  p  p    S   S       U^U       T]T       0SsS  P   \  P  	}  $ &  S  P  ]  S                       
U\]@U@\U\@U                 
T]U^]]TT               
QQQ           PPSSP                   0\]|T\]]]]              0_____          000s S0       Ps ~ "#(P  Q  X  0    SS    	}  $ &	}  $ &    	  $ &	  $ & S ] _      [[[      ]]]      ___                          P{{P{    p } p "p "#('{#} {## "{#"#( P 	}  $ & 	  $ & P ] _   \     P^   S       0RrR       0QqQ  p r pq "p "#(  PP   	r  $ &	r  $ &   	q  $ &	q  $ & P R Q           USUUS    US         USUS   P P S 0  P   R      UU      TT      QQ  $.U   3>P         USUS         USUS           TU\T\         Q]Q]       0RrR       0QqQ  p r pq "p "#(  PP   	r  $ &	r  $ &   	q  $ &	q  $ & P R Q       U]U       ^~T^   P         0SsS0   \  P  	~  $ &  S  P  ^  S         USUS         		U	
]

U

]         		0	
^

~

R

^  		U         		0	
S

s

S

0   

\  	
U  	
	~  $ &  	
S  	
U  	
^  	
S  

]           U]U]U           0\|T\\           0SsS0S  P  p | ps "p "#( P 	|  $ & S P \ S       PPU     	|  $ &	|  $ &     SS  P  \  S     UU         Qu0Qu0        8TR8      0Pp r "P    1u1 /                      \U\]U]aUabU               \T\]T]aTabT               %U%SUS                   PT"P"ATEJPeoP            0O\jt0     p      hUhiU          #R4?R           #R4?R          #U4?U          #R4?R 	            
R
PP4?R 	           
0Q4?0       P           UUUVU           UTUVT               1Q15Q5QQQVQ           0      &U&SuoUS           [      0$\$0|BN0\d\dp|            ^U^uU              TLtLuT                                     QUQ_U__U_U_U_U	     U                         pTpwT	      		T                           XQXlUlwQ	      		Q      <      %u %< u              SFSP`SS        S        S   x      __                PSSs p "S                "      ]_]UU_U	     U              "      	      	              "      	      	       4      P@             N      PR<\<\    k      #12        c      )0)x__0                  N      >0>__ZZ0               00
0

0	     0               __
_

_	     _              Z                       QQ


	                    


	                    


	                       ]]]]
]

]

]	     ]         ӊ      &s  3s  s  	s 1' 	s 1'           ]]                         SSSSs 1'S	s 1'		S	     	S       ӊ      
	}
!R	}R                            P^^P^P^P^		^	     	^           >      PQQQQ	     	Q                j      \\\\\	\		\	     \                     P~~~P	 ӊ      ^\\ ӊ      ^^^     ӊ      &s  3^s  s  	s 1'        ӊ      
	}
!R	}R             P.PP   E      PP   E      RR   E      00 ^      P      P ^      ~       ^      0      0       ~      ~       2      2       ~      ~       2      2       X      S]]]	     ]  h     T0       X      S^^^	     ^       X      S000	     0             'SS	     0     _      %PQ     _      %~~         _      %000	      0   x      PQ   x      ^^   x      00    .      ^^    .      SS             ]]]              __		__              		              		                     PY^Y		^		^                 7      PR<S<~~		S		~S               N      10S		0		R		P		p		R0         d       0 Y\\0		0		0           }__             PnSS           PP              0,1T>CT0           8Q;XQQ             QX Q  2     Q 7                n      /U/0U04U45U         n      /T/0T04T45T         n      /Q/0Q04Q45Q     n      /R04R            o      ?U?sUsU]U          o      ?T?ssT          o      ?Q?ssQ       :o      S9qS\  o     R]  o     R    o      07=^     o      	P	B\     o      ST                 /U/3u@34U48U89U               3T34T48T89T                 2U2?u@?@U@DUDEU               ?T?@T@DTDET     `n      )U)^U     `n      T^T         `n      BQBCQC]Q]^Q     n      U4U       z      cUc\U       z      `T`^T       z      [Q[SQ       z      lRl]R       z      lXl_X        z      1q
p 0.q "#~020.q "#1   z     P   z      +P+.~ z     .S z     .	r  $ & 	{      \  {     )|  {      \   ,{     _       ,{      T   ,{        h{     \  h{     ^    h{      SQ    h{      ]R  h{     L     o{      P/~     o{      Sz
Q $ &     o{      	}  $ &z
R $ &   {{     l\   {{     l^     {{      SlQ     {{      	]	lR   {{     9  {{     P\  {{     P^    {{      SPQ    {{      	]	PR  {{     9   {     "U   {     FP  {{     P    {{      S
Q $ &    {{      		}  $ &	
R $ & 	 {{     P 	   {{      SQ 	   {{      	]	R  {       {     8  {     "P  {     "u  $ &#3$| "   {     T       x      'U'@\@]U     x      S5S9>S   x     S   y     S       px      'U'@\@]U     x      S5S9>S   x     S   x     S       w      (U(A\A^U     w      S5S9>S   w     S   w     S       w      )U)b\bU     w      S_SchS       	x      P%3P39L   w     
S   x     S         pv      USUS       pv      3T3AHAT       pv      3Q3~\~Q      v      SUS  v      ?0?1     	    v      P+\+4P4<\<MTM\\\lTmr\        	       v      p \!| +4Q44\49| <Mt MM\MR| \ePem\mr|     v      P<MT   v      p <Mt      w      | | 16| QV|                    0U0\UUUU  I     G\    M      .U/8S88U      M      u 8S88U8:S   M     U  M     u   U     "U U     U  d     P   d     u  q     P q        q     8  t     U        S       ;\     q      CUCDU     q      "T"DT     q      Pt      	q      )P)<H    q      $P$7H  q      P    3q      H2Q  3q     20     p      LULMU     p      LTLMT  p     P  p     Q p     P p        p     8         u      tUtuUuyUyzU         u      tTtuTuyTyzT  u     T  u     U   u     T   u     P   u     U               q      U\u`U\U\             q      )T)STSTS      s      PH    Ts      	0012        s      PH%P%*P   s     P        p       U aSaU    Dp      S,U  Dp     ,0            v      !U!_S_du@deUejS     0y      5U56U       py      U;Q;]U  y     %0     y      UU     y      TT     y      8Q8Q     y      =R=R     y      XX     y       P 2t     y      Qy
Q $ &     y      	r  $ &y
R $ &   z     jU   z     jT     z      QjQ     z      	R	jR   z     jX  z     PU  z     PT    z      QPQ    z      	R	PR  z     PX   2z     "Y   z     EP  z     P    z      Q
Q $ &    z      		r  $ &	
R $ & 	 z     P 	   z      QQ 	   z      	R	R  +z     X  +z     8  2z     "P  2z     "y  $ &#3$u "   7z     R            |      ,U,]U]	     ]            |      %T%	      		T                    |      ^Q^_Q_
Q
Q	     Q            |      ^R^	      		R        |      ^X^X	     X                  |      ^Y^SS	      		Y        |      	      	          |     	      	        |     	      	                |      .\.^\^^^^^	     ^            ~      s  *	s 1' s  	s 1' 	s 1' 	s 1'     |      .\\   |      6	~;4$7&	~;4$7&        ~      	~!R	~R                        }      P_P_P_P	_

_

P

_	     	_                   1}      oZow~Z~Z~Z~	     	Z             l}      \\\	\		\	     \                   |      PP


   ~      *\\\   ~      *___        ~      s  *	s 1' s  	s 1' 	s 1'         ~      	~!R	~R      "~      PPP   8}      PP     8}      RT   8}      ~ T}      P~      P T}      ~         }}         }}      22   }}         }}      22    }      __       i      d^^^	     ^  i     d0   i      d_             )SS	     0         p      4SSS	      S     p      4         SS         _                    	^^         P      #U#SUS       {      P_\a\           PpwP              0"T/>Tp0             )Q,;QUaQmQ               Q;s Uas mQ       Q       s       s                U}\}U\               7T7{S{TS               0Q0^Q^           RR           7X7X      J      P'R'+            mUmnU            mTmnT         ,P/GP          0"4Q        P  M     P p              UPU       TUT     TT      YYY      RrR  
 0\   0Z   [[          0Qx } "Px } "   0S   0]  	 0 t D   4 0 t 0E   8 0 t  E   8 
0 t4 RF   4 0 t2 F   2 0 t8 PG   8 0 t  G   8  0 t  rH   8 0 t H   4 0 t I   8    q  $p !5q  $p !@ 
$@ 
%5q  $p !@ 
$@ 
%    __ 0 t0 PJ   2   rR 0 t K   4   P x } " \ Z   P   Q               U_UU_UU   U       U_U_   u u      Qu(u(     0UU0     QQ       R^     } s "]} s "          	u
r 
~ 
^~ s ^     SS          UPp | "Up | "      	}  t #S	}  t #  ^   U   \ U P    Qu( p RO   8     UU U    Pu   P   pu # Q   8                   	U	
^

U

^

U

^
U^U              	U	
^

^

U

^
U^      	\

\
\             S	u		~

u
u~         r } "	r u "

r } "
r } "              P	u(s 		~(s 

P

u(s 
u(s ~(s  U P      	\

\
\ 
p 
S   
8  	r u "     	_		

     	u 		~ 

~      	u(		~(

~(    		\		\   	S

S     			#

#   

1
1      

     0)
p  $0)     0)   p   

X'                    URURXw`U  u u u AX   4     urr 	  11 	    urr   PP    TT   QQ u u TY   4 u Q T    QQ    TT u      RXw`      RXw` R  r  0  r  0     UU  P    qq  Q  Q  R  Q  R u         USUS     TT           QX]Q]       R\\ U      NUNOU      NTNOT      NQNOQ      NRNOR  )0u  )00  )0u  )00     PUU         USUU         USUU S  s  0  s  0     UU    Pu   P   pu # d   8         UUUU  Q U Q  P  Q p f   8 u 	u u f   4     UU  U   P U P  Q p ,h   8 U                 @`U`SUS            3U37T78U8<U<=U                  UUUU       UuXU        :U:]U        BTB\T      BQB       6_T $ &_   CP W              U^U     TT         Q_Q_    00      U^U      T]} p "]      Q__    TT      Q\| p \       PPS         U^U^       T\| p "\     Q       R]} p "]      QSs p S       PP_  ^  \  S  ]        5U5b^bU      5T5T          5Q5_Q_    %b11      %5U5b^U      %5T5:]:B} p "Bb]      %5Q5b__    %5T5T      %5Q5:\:=| p =b\       5BPS\P\bS  BS^  BS]  BS\ \                  UUURU             1TQp 1$t "QQ      p U  
Y'                UVUUU    P\         UVUUU           0pq0qQq0    PP       P\\     PV  P  \  V  P  
\&       P  \       

U

T

U             		U		S		P	
U

S

U          		s p "		P		Q

Q

h           UYU	U		U    0		0      `U`  
 U&      U       Up U     TT       QpQ     RR     UU        ,U,5X5~U        1T15Y5~T      ),w,5U56w  )6
       ),U,5X56U      )1T15Y56T     =Xp X\U  6]
&'                    USUUSUS               TX]TT]T     
 
 
                          _U_T_U__U_U__           TX]T]T     _0    
 
                     _U_T__U_U_       P^^ 	     _U_ 	 
       _U_  ^  
   _       _  T  S    _X   Y   S   
\&       S  T   Y   S   
\&       S  T  T     SU    SU  
@'          Y]   S   
\&          PP                   %U%mU             %T%RSRmT        Ĵ      !0!+]+0P0S]                     -U-]U]UU]                   T\T\T\                     1Q1VQVQQV                    /0<QQQVPVk0|QP0                  /0<cS|SS0S                   P	R	@_@_       

U&            
W&          $      /--           $       ~ p " p ~ "1~-^-/~~  8     -  S     :  j     :  J     
Y'       `     
С'        ~     %-       ~       P p|#|~#%|       -       :       :                U]U]                  &T&^TT^                  &Q&\UQ\       *      P`SS         2      PVPV               PP                 P_SP_T_                  P(_8GPGZ_PP           U~                 4T4STST                 4Q4VVQV               %P%\P\             PsmP    B      00      B      
~
!U!"~  B     "
wU&        -     (Q       ~        S           UV             ~ +U+=~       =S        8_     ֬      U~   ֬     
\&       -         -     S  -     P  -     4               )U)_U_           1T11              1S1S             P\\           P          ?
1
1          0#            0<^<N~N\^          :]HQ]   !     %Q  !     &
Z&                   jjxQx           P%8P       P  <     P  ڨ     
A&       U     :           UU           
T
T      ħ      u 
U
ux      ħ      t Ttx       Э      U^\^_U      ԭ      08V8?S                UVUV            $T$H                $Q$]Q]       E      P\\        P      	p	|!U!"|  P     "H  P     "]       U          t 3$T          P$-P     p      UU             ,U,5X5~U             1T15Y5~T            wUw       
             UXU            TYT     -      p U  &     '
&'                0      6U6\U\U                     V      1=V=BPJfRfoQoVP0QT               PT%PMR0aP           @      LULU	                    @      LTL\T\T\	     \                    i      #0]P}]PpPpP	     P               i      #0#{{TQqQq               i      #0#+_+33__	     _             PBOPP              PP  P               PSP^PS0^         USUU  x0      x}T} H              ZZUZ[U[[U             ZZTZ[_[[T[[_[[T[[T             ZZQZZ\Z[Q[[\[[Q[[Q             ZZRZ[^[[R[[^[[R[[R         ZZXZZ]Z[X[[X  [[S        ZZUZZS[[S[[U          ZZTZ[_[[T[[_[[T          ZZQZZ\Z[Q[[\[[Q       XYUYZUZZU             XYTYY^YYTYZ^ZZTZZT             XYQYY\YYQYZ\ZZQZZQ             XYRYY]YYRYZ]ZZRZZR   YYS        XYUYYSYYSZZU          XYTYY^YYTYY^ZZT          XYQYY\YYQYY\ZZQ     XXTXXT     XXQXXQ   XXR         00U00u00s01S11sx11S           00T03V33V33U33v34V         00Q03\33Q34\       00R02]24R  00   00
ZV&        11    11
gV&        11    11
&'       22]  22\  22
W&       22\     22v22U           22|22U22|22T22|     ./U/0S     ./T/0\     ./Q/0Q   /0V  //
P         //Q//Q    //R//~  //S  //\  //0     ..U..U     ..T..T    ..U..U    ..T..T  ..0                ;U;SHSrUrPUUU                ;T;SPSrTrXTTT              ;U;SHSrUrPUUU              ;T;SPSrTrXTTT      %SVV{VV      LSSSSt         v s Pv s PP       %SVVV    %VZV        LSSSSt       %;t;LSX#t   U   T     XXUXXU     XXTXXT     XXQXXQ       XXRXXXXXR       XXXXXYXXX                       44U45_555AUAAUAC_CCUCD_DVUVV_VXU                         44T45V5ATAATACVCCTCDVDKTKKVKVTVVVVXT                 44Q4A}AAQAP}QU}UVSVVsVVSVX}                                   44R45^55~56R6A~AARAC^CC~CCRCD^DK~KK^KV~VV^VW~WWRWX~         44X4A}AAXAX}               44Y4AYABSBC~CCYCC~CXY                                                                                                                                                                                                                                                                        44044044v044vV045"vVs 4 $0.055 \Vs 4 $0.055\V_s 4 $0.055\V_]Z55\V_]Z55\VQ]Z55\V]66\V_]Z66\V_]Q67
\]77\V_]~77\V_]~77\V_]077\V_]Z77\V_}Z77\V_]Z77\V_]Z77\V]Z77\V]Z77\V_]Z78\V_]~89\V~]~99\~~]~9:S~~V::S~~]::\~~]:;\~~]Z;;\~~];;\~~];;\V~];;\V_];;\V_];;\V_]Z;;\V_];<\V_]<<S~~V<<\V_]Q<<\V_]~<=\V_]P==\V_]==\V_]==\V_]==\V_]==\V_]==\V_]=>\V_]Z>>\V_]~>>\V_]Z>>~V_]Z>?~V_]~?@\V_]^@@\V_]P@@\V_]@@\V_]@@\V_]@@\V_]@A\V_]AA\V_]YCC
\ZCC\(DDS~~VDD\V_]ZDD\V_]~DE\V_]ZEE
\ZEE\(EF\V_]ZFF\V_]~FF\V_]ZFF\V_]~FG\V_]ZGG\V_]GG\V_]YGG\V_]GH\V_]HIS~~VIIS~~}II\~~}II\~~IJ\V_]^JJ\V_]JJ\V_]ZJJ\V_]~JKS~~VKK\V_s 4 $0.0KK#\VU1s 4 $0.0KK\V_]ZKK
\]KK\V_]ZKL\V_]YLL\V_]~LL\V_]ZLMS~~VMMS~~]MN\~~]NNS~~VNNS~~]NN\~~]NOS~~VOOS~~VQOOS~~V~OO\V_]QOP\V_]ZPP\V_]ZPP|xV_]ZPPS~~VPPS~~]PP\~~]PP\V_]~QQS~~VQQS~~]QQS~~VQQS~~V~QQS~~]~QR\~~]~RR\~~]RR\V_]~RR\V_]^RSS~~VSSS~~]SSS~~VSSS~~]ST\V_]ZTT\V_]~TTS~~VTTS~~]TT\~~]TU\V_]^VVS~~VVV"vVs 4 $0.0VVS~~VVVS~~]VW\~~]WWV_]~WW\~~]WWS~~VWWS~~]WX\~~]XX\~~]~    AC0CD0    AAUAA\  AA
W&            AB0BB]BC]  BB\  BB} 3$~ "   BBS   BB\   BB
\&       BC\  BC
 &       BCS   CC\   CC
\&       CD\  CD
Ό&        CD]   DD\   DD
\&           PP0PP~ ~83%PP~ ~@3%  PP
\&       CC	P       CC
P       CC
W&       EES  EE
P       EE
X&         45VV    45_VV_    45VVVV    45SVVS  44  440  440                                                                  556::;U;<<===P=A~DDDD~DDFGGGRGGGG~GHHIII~IKKL~LPQRRRURRRR~RTTTRTTTTTU~VVVWWW~WX                        55}6<}<A}DD}FG}GH}HP}QT}TU}VV}VW}WX}                        55}6<}<A}DD}FG}GH}HP}QT}TU}VV}VW}WX}                                      55s @ $0)55p  $0)55~0)6;~0)<A~0)DD~0)FG~0)HJ~0)JK~0)KKs @ $0)KK~0)KL~0)LN~0)NP~0)QS~0)SU~0)VV~0)VW~0)WX~0)                            5516;1;;0<A1DD1FG1GG1HJ1JP1QT1TU1VV1VW1WX1                                                              55^66^66Q77^77^77U7;~;;Q;;~<<~<<Q<?~DD~FFUFG~GG~HI~JK~KK~LN~NN~#NO~OOQOP^PP~QR~RT~TT~VV~VW~WX~    66T<=T                                8::;U;;<<DDHIJKLNNOPPQRRRURSTTVVVWWX                            8;~<<~DD~HI~JK~LN~NN~NO~PP~QR~RS~TT~VV~VW~WX~                                                  99_99_<<_DD_LM MMPMM MMr OO OOPQQ QQr QQ QQPQQ QRr RR RS_TT TTr VV VVPVV VWr WWr WW_XXr               88P89UJJPJJUOO~QR~XX~                                             89099~990<<~DD~JJ0LM_MM~MM_MMROO_QQ_QQRQQ_QRRRR_RS~TT_TTRVV_VV_VWRWWRWX~XXR                                           89099^990<<^DD^JJ0LM~MM^MM[OO~QQ~QQ^QR~RR[RS^SS[TT^VV^VW^WW[WW^WW[WX^XX~                                 89099~<<~DD~JJ0LM2MM0OO0QQ2QQ2QR0RR0RS~TT2VV0VW0WW2WX~XX0                                   89099~<<~DD~JJ0LL~LMQMM~OO~OOQQQ~QQ~QR~RR~RS~TT~VV~VW~WX~XX~                                     :;P<<0HI0IIPII~} "JK0KKPLM0NO0PPPQR0RR0SS~} "TT0VV0VW0WW0XX0                                 9:0<<2HI0JK0KK2LL0LM2MM0NO0QQ2QR0RR0SS0TT2VV0VW0WW2XX0  9:~  9:\     99P9:]  <<\    <<R<<~  HH\  HH
W&       HI~     HHPHI~     HHPHI~  JJ
W&       JJ~     KKRKK~   KK\    KKQKK]  LL~  LL~    NNq NNU  NN
['           >?~LL~WW~     >>}>?S  >>~  >>
W&       ??U  ??~     WWp WWU  WW
Z'         ?@TIIT  FG}  FG}  FG0  FG  OO}  OO}  OO0  OO  ST}  ST}  ST1      STTTRTT  TU}  TU}  TU0  TU~ 55      55}  $ &3$v "55U55}  $ &3$v "  55\  PQ:  UV
W&                                                                                                                                      U[~U[~U[U~U~[UU[U[U[U [  U ![!!U!"[""U""[""U""~"#U##[##U##U##[#$U$$U$$[$$U$$U$%[%%U%%[%%~%*[*+U++[++U++U++[+,U,,[,,U,,U,,[,,U,-[--U--[--U--[--U--[--U                                                                                                                           TZ~TZ~ZT~Z~ZTZTZ~TZ~ Z  T !Z!!~!"Z""~""Z""T""~"#T##T##T##Z#$~$$T$$Z$$~$%T%%Z%%T%%Z%%~%+Z++~++T++Z+,T,,Z,,T,,Z,,T,,Z,,T,-Z--T--Z--T--Z--T--Z--~                                 QSQSQ"S"#Q#$S$%Q%+S++Q+,S,,Q,,S,,Q,-S                                                                                  000U0U 0  0  U !0!!U!"0""U"&0&'U''0''U'(0((U((0((U()0))U)*0**T*,0,,U,,0,,U,,0,,U,,0,,U,,0,,U,-0--T--0--0--U--0                              q 2Vs 2Q2Vs 2Vs 2!V!!s 2!"V""s 2"-V--s 2--V                      P000 0  T##T%&0)*0**0--0--0    ##U##~  ##  ##
Z'           #$Z++Z++Z   #$~++~   #$S++S  ++S   ++~  ++
sV&         $$P$$U  $$
V&       ++
V&         $$U$$~  $$  $$
!W&                  0v  $0.v  $0.v  $0.00""0%%0     U~      X   [[   ZZ   SS   00           Z~Z~Z~     ~~~     SSS     p U  
bW&          p U  
~W&          p U  
IW&                 Z~""Z""~%%Z%%~      ~""~%%~      S""S%%S  %%S   %%~  %%
sV&         PU  
V&       ""
V&          ~~                     P##P      ZZT    
V&     
V&         SS  p   
V&       p   
V&       "#T  "#
V&       "#Q   ##p   "#
V&           [**[,-[      Z**Z,-Z      S**S,-S        **  ,-    T      ['([,,[      Z'(Z,,Z      S'(S,,S        '(  ,,    U      [&&[,,[      Z&&Z,,Z      S&&S,,S        &&  ,,    U        [''[,,[        Z''Z,,Z        S''S,,S          ''  ,,      U      !![()[,,[      !!Z()Z,,Z      !!S()S,,S      !!  ()  ,,    !!U      !"[(([,,[      !"Z((Z,,Z      !"S((S,,S      !"  ((  ,,    !"U               $%T%%Z%%T,,T,,Z,,T,,Z,,T     $%
W&     ,,
W&     ,,
W&                $%Q%%S,,Q,,S,,Q,,S  %%U  %%
V&         ,,Q,,S   ,,
W&       ,,p   ,,
sV&          ,,p ,,U  ,,
V&               &&[)*[--[--[--U          &&Z)*Z--Z--Z--~        &&S)*S--S--S        &&Q)*z--z--z      &&T**T--T     ++T++Z++T ++
W&        ++Q++S     ++p ++U  ++
V&          	
U

U                 USUSUSUS             TTTTTT      TTT         SUSS                           ^XXXXX^XXXXXX   Hx H   v   
&       U  
&       v   
U&       v   v   
(V&       v   
/V&       v   
U&       v   
V&       v   
:'       v   
	V&       v   
U&       v   
V&       v   
U&         v U  
y'            U	X		U       	T		Y		T      w	U		w  	
       U	X		U      	T		Y		T     		p 		U  		
&'              UVvVvxV              T^^U~^^     Q     R            ^VUVV^V  |   
MV&       |   
ZV&        |    
gV&        |    
&'             0]___            0QqQQT00            0]__]_]    s 0)p "`s 0) "`           0ZSsSSS            ZZZ         ^Sss ss ^          0VP^^V^            P^UUSP^       ~ u "U}  $ &35$~ "     T    }  $ &`    $ &`~ "  S  `             ^^^  1       ___               UPUPUPU                   TXTTXTTXT             QQQQQQ    QQ       TXT  r   U  
V&       
V&      <                UPu U       TPT    U      UPu       TPT    U  0  @             USUSUU   P         USUS   11     USS      	u,2$7&01	s,2$7&     u(؟s(     Pq        PPQ     q U   
jX&          UU      PVV    }P      }U}  
SX&           }U}  
   V  
          USUS     11       111       111     	
^^  ~  ~  ~  ~  0     PV  
IX&       2  2     P	V  
IX&       2  		1     		P		V  		
IX&       		2  ~  ~  ~  ~  ~        5U59Y9U      25w59U9:w  2:
   2:
+X&           25U59Y9:U     A\p \`U  :a
&'          UU                   USTUS   22      USS   
     
       U      t  $ &3$      $ &3$T    PP           UUUTU              u  $ &4$`     "q 4$`     "u  $ &4$`     "U $ &4$`     "u  $ &4$`     "t  $ &4$`     "U $ &4$`     "        UUTU       UTU     UU        ,U,5X5~U        1T15Y5~T      ),w,5U56w  )6
       ),U,5X56U      )1T15Y56T     =Xp X\U  6]
&'            U\U         TVTV         S| 4$`     "U $ &4$`     "S  s       t  $ &3$s $ &3$T    PP          %    %  N  !%  '  '  6  %!  '  '  '     )  
9*  m*  *  &*  (a6  )s+  +w  '  '  6  +  +  ,    ,v    -}]  .  /  0f  #'  ,  3
w  )-  -  -  -  YI     .     !  "#$g  %.  _/    &  &r  #'1  =(1  3  K)Zr  *3  #+3  3  ,a  N-  .3  '4  4  /e  05  		b  5  96   O6  $X	  ,16  -2'7  s7  37  ~4Y3  54D  65  C  8  7/  	<  88  #9?8  $:{  [8  ;L  <8  !=  >8  %?$  8  9  @e  AY  ,Bx  '  ?9  .CnA  LD9  YE9  rc  ?sO  F9  8  9  ):  	G
H9  I5:  J'  ;  <  9<  Y<  K<  LĘ  M^  	N
D  5  D  %9<  O=  P  QD  8          %  "
 #%  '  '  6  %!  '  '  '     )  
9*  E   w  '  '  6  +   +  !,    '"3  ##3  3  )E  $=  %  E    &  '()g  *.  _/    &  +  ",  	+-F  .5  F  /w  '  F  0G  &1G  G  Q23 VH   4~H    H  5I  %  .5  *  &*  (a6  )6s+  ,7v  8  -9}]  .:  /  0f  #'  ,  3;
w  )-  <-  -  =-  >YI     .  b  .5  96   O6  $X	  ,?6  -@'7  s7  AJ  ~BY3  C4D  Da  E5  C  8  F/  	<  G8  #H?8  $I{  [8  JL  K8  !L  M8  %N$  'OZr  8  9  
e  Y  ,Px  '  ?9  .QnA  L	9  YR9  rc  ?sO  S9  8  9  ):  	T	D  .5  D  %9<  UD  8  
V  VJ  W` eX  Y3  '4  lJ  r  #Z1  =[1  (M  NX4  *  \K  9<  +]K  ~^  ,_K  L  `#L  9<  %a9L  +b  4cW   d '  '  e%  L  9  f5:  g'  ;  <  9<  Y<  h<  iĘ  j^  	k  lm#M  .5  n3M  '  )o.  -p IM    O  q7  rstC  u-  vwO  hP  x  ypR  z  {R  R  |}R  R  ~sT  $U      
Y    
  .V    DV  xV  X  [    e  5  (   [     y   "  &  *  .  <  G k          %    	%  N  ![  '  '  6  %!  ^  '  '     )  
9*  _  m_  &*  (a6  )s+  +w  '  '  6  +  +  ,    ,v    -}]  .  /  0f  #'  ,  3
w  _  -  _   -  !YI     .  
b  c`  96   O6  `  ,"6  -#'7  s7  $=  %  &J  ~'Y3  (4D  )a  *5  `  8  +/  	<  ,  -3  #.3  3  `  #/?8  $0{  [8  1L  28  !3  48  %5$  '6Zr  a  9  7e  8Y  ,9x  '  ?9  .:nA  L;9  Y<9  rc  ?sO  =9  8  9  La  	>^a  	?D  c`  na  %9<  a  @D  8  	& A BI  O  CD#M  c`  E3M  '   W" )F.  -G a    
Y  HI  J
  KpR  L  MR  R  NO.V  P  DV   
Q  R  STUg  V.  _/    &  0W% X9  Y5:  Z'  ;  <  `d  d  [<  \Ę  ]^  d  	^&_d  e  `B% # =0e  Xe  aw  '  e  bG  &cG  G  Qdf  VH   f  `d  e7+         	%  
f  #  %  '  '  6  %!  '  '  '     )  
9*  w  '  '  6  +  +  ,    f  ~Y3  4D  a  5  C  g  /  	<    3  #3  3  `  #?8  ${  [8   L  !8  !"  #8  %$$  '%Zr  8  9  &e  'Y  ,(x  '  ?9  .)nA  L*9  Y+9  rc  ?sO  ,` e-  .3  '4  lJ  /r  #01  =11  (M  N-4  %  25  *  &9<  (a6  )3s+  ,4v  5  -6}]  .7  /  0f  #'  ,  38
w  g  9-  -  :-  ;YI     .  b  25  96   O6  $X	  ,<6  -='7  s7  >9  8  9  ):  	?D  25  D  %9<  @=  A  BD  8  	C  DI  E9  F5:  G'  ;  <  9<  Y<  H<  IĘ  J^  	Kg          %  %  N  !%  '  	'  6  %!  '  
'  '     )  
9*  m*  *  &*  (a6  )s+  +w  '  	'  6  +  +  ,    ,v    -}]  .  /  0f  #'  ,  3
w  )-  -  -  -  YI     .  w-   I  9   5:  !'  ;  <  9<  h  "<  #Ę  $^  jh  	%g          
%  %  N  !%  '  '  6  %!  '  '  '     )  
9*  m*  *  &*  (a6  )s+  +w  '  '  6  +  +  ,    ,v    -}]  .  /  0f  #'  ,  3
w  )-  -  -  -  YI     .  h    	h          %  4/ D  N  !%  	'  
	'  6  %!  '  '  	'     )  
9*  m*  D  %*  =    D  8  %  5  *  &9<  (a6  )s+  +w  	'  
	'  6  +  +  ,    ,v    -}]  .  /  0f  #	'  ,  3
w  )-  -  -  -  YI     .   & ! "I  h  #$#M  5  %3M  	'  &&/  )'.  -( j    
Y  )*  +
  ,pR  -  .R  R  /0.V  1  DV       #   y   &   q   m   I}   n      &Q         ]   L   =   /V   P   :         W   T   F   ^<      1   U2   ]            /   a   w   d-      H   `7       ,u      iy   O   W            8:   w   :   I      =>      F      w   \   6;         l   t      }   A   1          m      :   Ś         O      W      ,   WA   =   x   r   v&   )   @         BH   s   ;      \|   oq   J   0   O6   !   Q?   o   L   -   J   ]/   @      V   4      P   [       o   :   6   ^          I   ul   +n   :   Q   Ŋ   o   I      +   .   $   ^!   gi   +   U         O      i   g{   %   S    7         X   '      O   $N   )    U   i8   f#   7   5   -   6   %   )      y   |   ʮ      })   1      Q   @G   h   <&   ĸ   \   C   T      >2      +`   ݍ      M   n   
   ī   R   C      D      o   ]   4!         '   (1   -   f=   h   x   A~   7   J   ۙ   u   !   |   D   Qo   h      >   -                !   /   B   #      Jn   g   2   +   ׷   Z         s      d   ;   L         >   &   S   N   W      q   O   ~      w   5   iU      V>   U      A   3      n9   Au      _      R      L   _   x:   7   -      !/      =   @   jR   1   p   $      V      ^   v   +]   H   K   tE   2      NQ   P   S   6   cd   ք   Da       `         7   {c      D   "      t?   R   lz      A         N      [   ^   *G      _'   9   G   %   \h   2   O   ]   m         8   F   /         -      n      +{      2M   n       ip   ~    \         £   1   |   	p   >      Nt   Ji   ?   a   *   x   5   f       D   ~h   s   _   U   zS      ,   A   AX   0   m   `   [Z   m   t   &   m   v   ֕      I      P         =    -   +   *   x   l   z      1               J7   u          &h  'mr  0Q  1zL  >Ʋ     m b     Dd  X  .  .  `n  &      0  A    ~G  0    vZ  5  p  6  [  ;    M        X  :  ܫ      V[  f  >  Xw  o  A  A  m3  x  z  J(    n  (  F  y  9  &  v  \    `  .    .  J(      #  ;         R  B  [       M      t  M#  L  ~  U  D       Ts  #__P $f  -v  2  7l  Ah  B  O4  P  Q0  Rl2  f(  }V  ~p  G  :  +m        cs  V  =5       -*  ,w    ;x  ,  4N    w  ,i  XG      %Y  =  y  \  ^a    e    ;"  ӭ  D  <      72    !<    )  Y    ,T  d      `+      B     4  @  8    D  C  >0  }j  Z_  '  -  x  z  h  EB    %  k  7     
bc  l  @  TH    f  c  E     %  *G!  C;+  G  I  ME  O}  S  ZHP  ^  `  dE  i|#  m&c     $C  %     `  3  ]  FW    u  s  d  d  e    a  !  ީ  ?  Y    
)  fE  1[    *[     "	  'J     m̵  ns<  o}  pN  q9U  rA    5  [  $_  Gm  n  r  [:       !  ")  #H  &  'h  (>l  )k  *-}  +H  -  .3  3^  4qg  5E  6UW  7̟  8t  9p  :A  ;  <d  =  >:  ?$  @^@  AY  B[  C  D  E~  F  G¦  Hu  Is  Jkk  K  QH  T  WJ  Zϖ  ]  g     :       q  u	  z-X  {  }n  ~wt  ~     :  H
T  L  Sw  b5  c*  dM  h  mc  r%  sl  t:  }"  <  N       ]      A  q  :m  p  s  I  ;       >  %  -i  5S  ;۝  H?J  VD     "  #  $>  %g  &w  4~6  5}  669  7  8  9C  ?V  F`  ]k  iRd  q,  }a  1t  v  %  9w     	  gC  ʭ  ^  T  	  
{/  -  `R  #  8    P    <    x  ȗ    U'    V    -  	  ;    ͕   n  !d  "ݒ  #  $  %]  &D@     D6  i  	SU  M  \    	  Ӹ  P  p  j  %F    `    P   |"  !O	  "8  #  $  %'  &,  (G  *r  +yM  ,  -;@  .&  /  0\  1  2Z  3  4o  55  67  7	  8"  9  :A  ;҇  <  =-)  ><  ?p  @&  As6  B  C  D}  E9,  F]U  G͓  H5  Ib1  JjX  K  LQ  MO  NxW  O  PZ  QN@  R  ST  T  Uh>  VC  W%\  Xf  Y6	  Z^  [O  \Y  ]  ^k  _l  `r  aq  b  ca  d&  e։  f  gH  h  i0  j  k  mO  n<  o  pY  q  roC  sy  vi  w  y  {     .$  X         *C  +/  ,z  -+  /%  2  5b.  8G  ;K  >k  A  D3  Fp  H,@  OǶ  R  U9  X#  [~m  ^x'  a  d   m  nA   o%  MC  ]    Z~  k]  h  8H  mt  i<    B  t  ?  i  ΂    4    ֘  1  4  K  T  z    "    I  T    ;  ';  p  n  q  &=    >    g  ;    Z     (M  3+  F#?         I   ߏ     #  	     (  ,Vl     l$  Mئ  N  O  `  .  p.           !D  "S  #@  $l  %  &  *  +"   ,g  0  1Ô  2.  3`  4  5&  8F  94?     P  Q|  R  SM  Tk  VI  Y   \i  a,  by  fpI  i*j  j  kJh  mX  o  po  q7  s  u  v2  w)  y    =E    N  %  l  :  )  y  5  f  i  #  h  1x  )     U.    :      x  !$  "+  /?C  0  1-     N  %  *G!  C;+  G  I  ME  O}  S  ZHP  ^  `  dE  i|#  m&c     C  Ӕ       fE    B	  B  ^y          3  R  &    &  B  5P  v  JD  j  1[    *[     bK  ~  N  O   T  !Z  $y  &  'e     X;  <  "}  %P  (  ,_  12  5  8l  95  :ȍ  ;     0  1#  2H  3Jg  4}  5*  7  Ly   V  [Xz  `c  ar  eE$     #  (  3"  7  <97  A'  K  P7  hƉ  tF  zk     fE  *[       J  0  ?  "       E  ,c  ;a     'J  (l  )  *mT  ,<  -
  .a  /)  1<  2#  3r1  4     Y(   Z  "H  $     7  x     ,Y  4  6  77v  8X  DQ  I  P  UU)  VY  W  Xf     BO  &  RJ  6K     q    p  |  )fV  *K  +  ,/  -k  /P  0:     C  %O  7 #     X  3       C     >$  #ҥ     &  "  5y  C"  F`5  J~  NZm  R8  V{  Z	  d  g,  h  i&  lL  pj  s     1  #  [   2  #  &T8  )2Q  ,k4  /~  2aH  5E  9  <g  ?  BHc  E  H   K  L.  O  R  Ur  X  \g  `T  c!  gO  j<|  mI  n  pC_  ra  u,B  x  yD  zJ  }!    3  ؠ  Ű  @  ;  %    R  ^    .  u  ܀    `  
  "&         җ  v  Xe  Pq     8H  9  :u  =j  >F4  ?]  _1  `3  e6\  f+  hϐ  i#     nj  g  ̀  C       fE  1[    *[     W  4  N    =E    N  @  Ϗ  k       vX    !  #  %hP  '.  )  +  -1  /{  1  3  5P  7|  9g  ;u  =e  ?+o  AU  C@  J  Ln  N  Pi  R.  Tl  V  X6[  Zʢ  \I  ^d  `AA  bd  d+  f  h  j    l  nǃ  pM  rle  t0  vW  xU  z  |K  ~s[    -  .W    d    BV  |  DE  |i  {  LX      \  T  m    3  =]    s|  c      e  d}  /J  z  M  7  k  k  LK    G      ?  C  !E  Q    on    9  ~  y  O  13    E,  q  +  6  ݅  *r    XD  v  1    (4    "    o  s,  ċ  O    Kk  ד  U  ,  8  
_  p~  ʁ  UT    &  ~\  P9      1  z  %  J  j  ˜    WO    ]    F    >  nY    '  b  W   8  "    hJ  NR  :  c  u  1  P&  r`  '    V  x>  t  Ap    ^    9/  ;  e  k  7)  <  7Z        Z  %   4  d	    k        %  9    {  t  E  3  
  ;  >=  ۧ  ?  5I  "  >  c  N        a    `    -  u  
  @  Û  e  l    _  U  V    0s      ߇    S  <j  S  F^  &-       M      0  r  Uv  G  L  $            q  }    I  1  <        io  l  9F  z  F  
  ?  r%    oF  a  o  >L  z  lK  !  |*    4%  ?  h  T  X    )  d  q  if  H    'f    .  B      W  6S    R      W  Ҍ     :^  b     #C  $     2  C     .  @ ]       +;  X  c  d  f n e ! i      ? 3  Լ  k     w     i
 ~        4   *      _      ֿ          G        h     w    g           b      v f  D *      z  #a  &  **  0m 4B
 7  :  =V  AY D  G J  Nr  U  a  d  h k  n  q t w  z  }H  $  n        ,  }    "             	_  
]  `   0 x        n     *'  +  /U  0i  4q  5f  9  :  >"  @  C=  E  Hh  J  N     T W  Z?  ]  `  c         	 !H  $+  (  ,  /Խ  3  7"  ?  B  Eu  HK KH  N  Q T  X     <[
 ?_  @  H  I J K  Nk  R  `  a  b c gJ  hR  ijO  j  miO  q1 u  v  wݜ  x<  {ܜ  |         '          D         $ % &2  1J     #  (  3"  7  <97  A'  F+  K  P7  b#?  hƉ  tF  zk     C# Dh  E     h  i|  j  kM  lk  nI  q   ui  {<  }  ~  <   n     4  9    ,  y  pI  *j    Jh  X  d      o  7      2  )               s C       n            	     # $  .A  :P  A  Hd P T  c  n?  pS qW     / 0     C        "  .E  0k  2  4+  6n  8  :L  <  >  @  B Ef     (  *j ZV  r   	           b x  D 3       W }    	      b     =  "  *    b  c  eo  fU  o  p q
  r  t  u  v`  w  z  { |@  }:    ~       ,   H F  E    
 X  O   =      g  /  3      ]     g           :   p  W | @ +  '  <  q  +  &  ii  W  o  /     '  (x *  o      b ^  k    6   fE  j  1[    *[  ]  3           $  $$  '%  (  )Q  *  ,  -  . /e  :X  >  B  E  K  S  T  Uq V		 Wv X  YB \3  ]~ ^ _F  c  d  e  fa  g)    ~    _ _        [         !  " # $  %H  &  '  (* )X  *  +  ,c  -  . /=  0P  1  2  3  4 5  6  7  8W  9  :,  ;F  <  =p  >  ?  @  Ah  C  E F  G H<  Iغ  J  K  L~ Mc N  OM Pk  Q  RD SC  U  V  W/  XV  Y>  Z  [  \I  ]K  ^* _  `  b  ca	 j* n  o  p	 q  r  s  t  u  w     y 4            *              *  	  
^   o     W G  $  &  *[  +N  4&  5  6u  9  :  ; < = >  ? @6 A  B(  C  D  E  F
 G H  I޾  Jl  K L  M N  O  P  Q R  S T%  UN  V W  X  Y  Z? [, ]  ^  `
 a fw  h?  i
  j  l\  n o s#  t u	  x  y  z ~     p   =  t  o    9   l  #     @   8 . Y    $	 %|  &ݸ  '  ( ) *l  +  ,  -;  .  3 4G  5  6P  7  8( 9Y  :  ;  <v  =  >m ?  @  A!  B8     )  .>  /A  0  1 2 7  8  :  >  ?X A  E  F G  H  I`  J|  K  L  M  N  O"  P  Q S  T  U       2       2e  5s  :h  < =  X  \7  `     =    Y /    p           >      k      $    !x  "  #|  $  %B  &  '  *4 + ,x  - . /j  4  : ; @?  Ag  BJ  G  H  I J  Kn L  M<  NY  O  T  Y Z  [  \  p u4  v  w  xu  y  z {u  | }. ~f  {          {    <   H                $  6       %  &  -  /  0d  2Z  3} 5t 6  8  9  ;  <  >  ?  A  B\  DQ  E  G  H;  J0  K	 M	 Nu  Pm  Q  S  T  V  W Y Z%  \  ]i _[ `P bE c9 e0 f h i  k  lɿ  n  o>  q1  r t u  w  x  z  {  }     w P     f     E  h \         b   O      %    6   \                N 
 t	  4      u     u   . f  {          n   <  Y                > (FS      '  
 }     Dd  X  .  .  `n  &      0  A    ~G  0    vZ  5  p  6  [  ;    M        X  :  ܫ      V[  f  >  Xw  o  A  S P,  ! H$ >* % ! %  (  F  y  9  J( & $ # ' J7  A  m3    #  >'  A  m3  +   
( J(    (  F  y  9  &  v  \    `  .    .  J(      #  ;  %, & , '( (   ! ;  "+ `  D" .    .  J(  '          M  O! "   ' t  p L  ~  U  D       %  (B C;+  E' I  K{ O}  Q[# ZHP  \+ `  b! i|#  k %    !k $C  %     :  H
T  L  Sw  b5  c*  dM  h  mc  r%  sl  t:  v!! w% }"  <  N      A  ( q  :m  , p  s  I    ( + b  ;       N  %  (B C;+  E' I  K{ O}  Q[# ZHP  \+ `  b! i|#  k %    $X	  '$    W  Y  C     J  0  ?  "     4  6  77v  8X  Aj! I  P  UU)  VY  W  Xf     ):  %     ,    ' #C  $     y ) O* y"  %  "    Q4  b  c  eo  fU  o  p q
  r  t  u  v`  w  z  { |@  }:    ~       ,   H F  E    
 X  O   =      g  /  3      ]     g           :   p  W | @ +  '  <  q  +  &  ii  W  o  /  % % ( ( # # % % % %     & & ( ( & & " " 4, 3, *' )' ) ) $ # & **  , + #      fE  j  1[    *[  ]  3     N    =E    N  @  Ϗ  k     #  h  1x  )  W$    : - 	)      0 > (FS    /+ 1 2Y 3) 4X( 84!    UY' Wa, d fl+ h j.$ l" n( p~( r  t  x y#     z  #a  &  **  0m 4B
 7  :  =V  AY D  G J  Nr  U  ] a  d  h k  n  q t w  z  }H  $  n   ( w# |+      ' 
"    t  C     !- 
, ,    (  3"  7  <97  A'  F+  K  P7  Y
T  ]  b#?  hƉ  mw  tF  zk     `  3  ]  FW    u  s  d  d  e    a  !  ީ  ?  Y    
)  fE  *[     :  b5  c*  dM  h  mc  r%  sl  t:  }"  <  N     0 > (FS    '  7  W  #?  4  N    =E    N  @  Ϗ  k     #  h  1x  )     .  X. "	  2. 4. 5. 8|. :z. m- pJ  v. y.    (   '  
 }     '  (x *  o      b ^  k    6   fE    B	  B  ^y          3  R  &    &  B  5P  v  JD  j  1[    *[  ]  3     Q4  b  c  eo  fU  o  p q
  r  t  u  v`  w  z  { |@  }:    ~       ,   H F  E    
 X  O   =      g  /  3      ]     g           :   p  W | @ +  '  <  q  +  &  ii  W  o  /    ψ  ܒ    %  V q v    b  x   I    #M  N  ! [  !"'  #"'  6  %!    $  "'  %   5  1m &
'9*  _  w  "'  #"'  6  +  (+  ),    *3M  "'   W" &+/  ),.  -- a    
Y  ./  0
  1pR  2  3R  R  45.V  6      7& D  c`  na  %`d  y 8=  9    :D  `d  ;p  {  <H  ~=Y3  >4D  ?a  @5  `  `d  	<  A  B3  #C3  3  `  #D?8  $E{  [8  FL  G8  !H  I8  %J$  'Zr  a  KLg   9  Me  NY  ,Ox  "'  ?9  .PnA  LQ9  YR9  rc  ?sO  ` eS  	3  '4  lJ  TU    'VWX9  Y5:  Z"'  ;  <  `d    [<  \Ę  ]^  d  	v 	^&_d  b  c`  96   `d  `  ,`6  -a'7    <b-  cYI  %   .  <  d9  `d  9  ):  e% 	f^a  	g	h`v 	%  c`  m_  &`d  (a6  )
s+  ,iv  j  -k}]  .l  /  0f  #"'  ,  3m
w  d  n-  _    oϥ    
=W 
h    pd Z l 0  )i     ܒ    %  %  N  ![  '   '  6  %!    !  '  "   5  1m #
$9*  _  m_  &	*  (a6  )
s+  +w  '   '  6  +  %+  &,    ,'v  (  -)}]  .*  /  0f  #'  ,  3+
w  _  ,-  _  --  .YI  "   .    ϥ    b  c`  96   	O6  `  ,/6  -0'7  s7  1=  2  3J  ~4Y3  54D  6a  75  `  	8  8/  	<  9  :3  #;3  3  `  #<?8  $={  [8  >L  ?8  !@  A8  %B$  'Zr  a  CDg   9  Ee  FY  ,Gx  '  ?9  .HnA  LI9  YJ9  rc  ?sO  K9  	8  9  ):  L% 	M^a  	N	O`v D  c`  na  %	9<  a  PD  	8  Qp  { & R SI  	O  TU#M  c`  V3M  '   W" )W.  -X a    
Y  YZ  [
  \pR  ]  ^R  R  _`.V  a  DV   b5 'cd!  e7   f  !g  $h    7iy    >j  o  Pk  RlTm  ˪  |n۪  7  opqC  r-  stO  hP  u  vwR  R  pT  $n	` ex  3  '4  lJ  yz    '{|}
~9  5:  '  ;  <  	`d  d  <  Ę  ^  d  	v 	&d  # =0e  Xe  w  '  e  G  &G  G  Qf  VH   f  	`d    =W 
h  V q v    b  ̫    |} d     ܒ    %  L  [  '  '  6  %!      '     5  1m 
9*  w  '  '  6  +  +  ,    8  !   8  $!a  %$  '"Zr  #3  #$3  3  w  %g   b  &c`  96   'ì  `  ,(6  -)'7    <*-  +YI     .  <  ,=  -  H  ~.Y3  /4D  05  ߭  '8  1/  	<  28  #3?8  $4{  [8  9  5e  6Y  ,7x  '  ?9  .8nA  L99  Y:9  rc  ?sO  ;9  '8  9  ):  <% 	=^a  	>	?`v 	%  &c`  m_  &'9<  (a6  )@s+  ,Av  B  -C}]  .D  /  0f  #'  ,  3E
w  d  F-  _  G  Hϥ  I  D  &c`  na  %'9<  a  JD  '8  Kp L { 5 M  LNm  OH  O 9P, '  Q֔   R   :S˯  T >Uؔ BVK '    CW    Xѱ  Y;  C  '8  ZW  '8  [g  \  ]9  ^5:  _'  ;  <  '9<  *  `<  aĘ  b^  d  	cdv 	e&fd  m  g  h} i   j7  klmC  n-  opO  hP  q  rpR  s  tR  R  uvR  R  
lT  $wU  x 	  
> Z     ܒ    %  V q v    b  x   I    #M  N  ! [  !"'  #"'  6  %!    $  "'  %   5  1m &
'9*  _  	w  "'  #"'  6  +  (+  ),    *3M  "'   W" &+/  )
.  -, a    
Y  -.  /
  0pR  1  2R  R  34.V  5      & D  c`  na  %`d  y 6=  7    8D  `d  9p  {  %  c`  m_  &`d  (a6  )s+  ,:v  ;  -<}]  .=  /  0f  #"'  ,  3>
w  _  ?-  _  @-  AYI  %   .    ϥ    b  c`  96   `d  `  ,B6  -C'7  s7  DJ  ~EY3  F4D  Ga  H5  `  `d  	<  I  J3  #K3  3  `  #L?8  $M{  [8  NL  O8  !P  Q8  %R$  'SZr  a  TUg   9  Ve  WY  ,Xx  "'  ?9  .YnA  LZ9  Y[9  rc  ?sO  \9  `d  9  ):  ]% 	^^a  	_	``v 	ӳ  
=W h    w a= b  cn  
d  eú f  Lе  g      Z    G '     ܒ    %  &  [  '  '  6  %!      '     5  1m 
9*  ~   5:  !'  ;    w  '  '  6  +  "+  #,      *    $<  %Ę  &^  d  	'(v 	)&*d  +  ~,Y3  -4D  .a  /5    8  0/  	<  1  23  #33  3  `  #4?8  $5{  [8  6L  78  !8  98  %:$  ';Zr  a  <=g   9  >e  ?Y  ,@x  '  ?9  .AnA  LB9  YC9  rc  ?sO  D` eE  F3  '4  lJ  GHm I JI  h  KL#M  Mc`  N3M  '   W" )O.  -P     
Y  QR  S
  TpR  U  VR  R  WX.V  Y  DV      'Z[\u  ]=  ^  "  _r  #`1  =a&b  `d  $  cz    d   ef(M  NE  D  Mc`  na  %`d  a  gD  `d  hp  { iV jq kv  l  b  ̫  	  
  m  nopg  q.  _/    &  0r%  $s5 t  Lum  OH  v 9w, '  x֔   y   :z˯  { >|ؔ B}K '    C~    ѱ  ;  C  `d  W  `d  g    m    }    16  4'7    Jr \  =W 	l  b  Mc`  96   `d  `  <-  YI     .  <  9  `d  9  ):  % 	^a  		`v %  Mc`  m_  &`d  (a6  ,v    -}]  .  /  0f  #'  ,  3
w    -  _    ϥ        d  $ C      ܒ    %  5 [  '  '  6  %!      '     5  1m 
9*  w  '  '  6  +  +  ,      Lm  OH   #  8    5Zr   3  #!3  3  "a  9#, '  $֔   %   :&˯  ' >(ؔ B)K '  (  C*    +ѱ  ,;  C  g  -W  8  .g  /  019  25:  3'  ;  J  9<  x  4<  5Ę  6^  d  	78v 	9&:d  m  ;  <} =e  >Y  ,?x  '  ?9  .@nA  LA9  YB9  rc  C   D=W l  b  Ec`  96   O6  `  ,F6  -G'7    <H-  IYI     .  <  J=  K  L  ~MY3  N4D  O5    8  P/  	<  Q8  #R?8  $S{  [8  TL  U8  %V$  a  WXg   9  Y9  8  9  ):  Z% 	[^a  	\	]`v %  Ec`  m_  &9<  (a6  ,^v  _  -`}]  .a  /
  0	f  #'  ,  3b
w    c-  _    dϥ    eV fq gv  h  b    i jI  O  kl#M  Ec`  m3M  '   W" )n.  -o     
Y  pq  r
  spR  t  uR  R  vw.V  x        > Q   e  ܒ    %  Z      #   y   &   q   m   I}   n      &Q         ]   L   =   /V   P   :         W   t  T   F   ^<      1   U2   ]            /   a   w   d-      H   `7       ,u      iy   O   W            8:   w   :   I      =>      F      w   \   6;         l   t      }   A   1          m      :   Ś         O      W      ,   WA   =   x   r   v&   )   @         BH   s   ;      \|   oq   J   0   O6   !   Q?   o   L   -   J   ]/   @      V   4      P   [       o   :   6   ^          I   ul   +n   :   Q   Ŋ   o   I      +   .   $   ^!   gi   +   U         O      i   g{   %   S    7         X   '      O   $N   )    U   i8   f#   7   5   -   6   %   )      y   |   ʮ      })   1      Q   @G   h   <&   ĸ   \   C   T      >2      +`   ݍ      M   n   
   ī   R   C      D      o   ]   4!         '   (1   -   f=   h   x   A~   7   J   ۙ   u   !   |   D   Qo   h      >   -                !   /   B   #      Jn   g   2   +   ׷   Z         s      d   ;   L         >   &   S   N   W      q   O   ~      w   5   iU      V>   U      A   3      n9   Au      _      R      L   _   x:   7   -      !/      =   @   jR   1   p   $      V      ^   v   +]   H   K   tE   2      NQ   P   S   6   cd   ք   Da       `         7   {c      D   "      t?   R   lz      A         N      [   ^   *G      _'   9   G   %   \h   2   O   ]   m         8   F   /         -      n      +{      2M   n       ip    \         £   1   |   	p   >      Nt   Ji   ?   a   *   x   5   f       D   ~h   s   _   U   zS      ,   A   AX   0   m   `   [Z   m   t   &   m   v   ֕      I      P         =    -   +   *   x   l   z      1            J7   u   k     wm    e 
Y z { v h s &y fs Ks Z n q Y e hg y V e  d !V "6Y #Mk %l &Zp 'y (9f    
Pf f R^ wn u e !w $h 'W )p *[    i #k 'o    Sx V $Nl )s ,ZY 0w 8m @f D(x I#u Qxq hm uh  v%^ wk zOm ~?e Pw s  |h  r k p    '  (x *  o      b ^  k    6   `  3  ]  FW    u  s  d  d  e    a  !  ީ  ?  Y    
)  fE    B	  B  ^y          3  R  &    &  B  5P  v  JD  j  1[    *[  ]  3       M  O! " z ' t  p L  ~  U  D       Ts  #__P $f  -v  2  7l  Ah  B  O4  P  Q0  Rl2  f(  }V  ~p  G  :  +m        cs  V  d V Di NW r gu v Z f }w t d [y g u_ l t _ X   -*  ,w    ;x  ,  4N    w  ,i  XG      %Y  =  y  \  ^a    e    ;"  ӭ  D  <      [d   !<    )  Y    ,T  d      `+      B     4  @  8    D  C  >0  }j  Z_  '  -  x  z  :p EB    %  k  7     2e  5s  < =  X  \7  `     ` Y +q ?y h n    ) O* y"  %  "    #  (  3"  7  <97  A'  F+  K  P7  Y
T  ]  b#?  hƉ  mw  tF  zk     e i    m 9g Y k vV p s z 6t an e Z ,^ e g s ik g ^ Aa MV Kn v i ^ h d fe g @v z x    !i "Y    N    =E    N  %  l  :  !! % @  Ϗ  k     0  1#  2H  3Jg  4}  5*  7     Ly   V  [Xz  `c  ar  eE$     :  b5  c*  dM  h  mc  r%  sl  t:  v!! w% }"  <  N     	[ iq    m Nt P[ za n    (g iq    ?q t &^ 9j    { %w~ *8     ~ $ C   Y}   f !% " # $ %k & '9 (~    [    !  I| #  0~ !x #ވ $} %` &- (|     1 { n X | }   " #t| $ %b &{{ 'ą ( ) *ہ +Ɓ , - .N /| 0i 1 2 3 4{ 7| 8 9~ <f|       @ 4 ˆ [ }  ? ! " %f &~ '    'j~ ( )} * +& ,} -m} . /r 0Q{ 1P 2K 3 4n 5~ 6K    =     8| !~ " #j $\ %| &2 '} (Ԅ ) * + ,[ -8 .̀ /    9 :a{ ;/    #~ ~ Ƀ @}   u !c "B #S % *{ -W| 0"| 2 6{ 9օ    B  F/ Gn H7} IӁ L,} M' N    Ԉ | ~    ׃ .  	  { q{ Q  | !- " #~ $ % & ' )Ԃ * .x /| 0} 1 2
 3 4 5 6 7| 8 9| :L ;p < = >߀ ? @| A| B& C D{ E	 F? IL K    , C    )  .>  /A  0  1 2 7  8  < >  ?X C`} E  F G  H  I`  J|  K  L  M  N  O"  P  Q S  T  U     "
 'D .  > ] "   }     Sx V $Nl )s 0w 8m @f D(x I#u Qxq hm uh  v%^ wk ~?e Pw |h  r k p ` Y +q ?y h n    ,Y  4  6  77v  8X  Aj! I  P  UU)  VY  W  Xf     `  3  ]  FW    u  s  d  d  e    a  !  ީ  ?  Y    
)  fE    B	  B  ^y          3  R  &    &  B  5P  v  JD  j  1[    *[     W  C         !͚ 0? 1 2g 3 4 5 8 9w : ; < = @ؘ A~ BG       ! " % &  'љ (ŝ ) * +Ԗ ,. -P . /_ 0o 1^ 2i 6k 9ؘ :~ ;G =G >     
    Z  {  ! ![ 2  o S ŉ 5 J  X U g * ͊  l ; F       ؒ ` 77 81 9 : ;	 < = >	 ?t @׍ AЏ J L N  Pΐ R T1 V X Z a@ c e g i= kl m o% qA s z |ȋ ~ ʎ \   B     c V    ܙ       >  {  5   !  O 4    z 
 - .        "M &         = '| (ό 8 93 :1 = @ A C" F Ig Jߕ K O  P Q{    ֑  o З     C       (a *V 5A 7/ 9n ;1 =W ?Н A C Ez G: Ij K M O" QО S U W Y [ ]~ _c a_ y    ,   ߖ    4  N    =E    N  @  Ϗ  k     ϒ  %   Ò     I  ɕ    r B     ٓ = > ?ʛ     +;  X  c  d  f n e ! i      ? 3  Լ  k     w       i
 ~        | 4   *      _      ֿ          G        h     w    g         ~ K  O  ( 2 < X    g 
 Ƿ   @      # &     %      p ߠ  & - .! / 5ب 8g H It JƬ K޻ L> M N O P QT R
 SƢ [ ^1 _    rۢ tp u< v wl x yw z {h 2 t   C ӯ !   ѿ  ̮ ٺ   , ۸   1 ޾ Ӭ ޣ ɽ 3    "  5y  C"  F`5  J~  NZm  R8  V{  Z	  d  g,  h  i&  lL  pj  s     nj  g  ̀     w  C       '  7  
T    W  #?  4  N    =E    N  %  l  :  !! % @  Ϗ  k     #  (  3"  7  <97  F+  K  hƉ  tF  zk     Y  C     b  c  eo  fU  o  p q
  r  t  u  v`  w  z  { |@  }:    ~       ,   H F  E    
 X  O   =      g  /  3      ]     g           :   p  W | @ +  '  <  q  +  &  ii  W  o  /  % % ( ( # # % % % %     & & ( ( & & " " 4, 3, *' )' ) ) $ # & **  , + #    9g Y k vV p s z 6t an e Z ,^ e g s ik g ^ Aa MV Kn v i ^ h d fe g @v z x     +;  X  c  d  f n e ! i      ? 3  Լ  k     w       i
 ~           | 4   *      _      ֿ          G        h     w    g          C     *C  +/  ,z  -+  /%  2  5b.  8G  ;K  >k  A  D3  Fp  H,@  OǶ  R  U9  X#  [~m  ^x'  a  d   m  nA   o%     MC  ]    Z~      k]  h  8H  mt  i<    B  t  ?  i  ΂    4    ֘     ` F   M  j   Y  )  + 1  4  8 K  T  z    "    I  T     8  R      	 ^  &    <    E      ;  ';  p  n  q  &=    >    g  ;    Z   [ < z   \     b ; Y  t L , =  O `    x   v     ]  j [  & #1 &     P  Q|  R  SM  Tk  VI  Y   \i  a,  by  fpI  i*j  j  kJh  mX  o  po  q7  s  u  v2  w)  y  %  l  :  )  y  5  f         i     &     6  7#  8H  9Jg  :}  ;*  =  B" C D! E|    W X    .  X. "	  'J  2. 4. 5. 8|. :z. m- pJ  s  v. y.    b5  c*  dM  h  mc  r%  sl  t:  v!! w% }"  <  N     )#?  /7     z 
 sO  - .    nj  g  ̀  w  C       '  
T    W  4  N    =E    N  %  l  :  !! % @  Ϗ  k     Sx V $Nl )s 0w 8m @f D(x I#u Qxq hm uh  v%^ wk ~?e Pw s  |h  r k p          %   i #M  N  !  '  '  6  %!  p  '  '     )  
9*  m*  w  '  '  6  +  +  ,    3M  '  &/  ).  -  j       !V "q #v  $  b  v+  %I  + 
Y  &'  
  (pR  )  *R  R  +,.V  -      - 
   
  .  /01g  2.  _/    &  3	e  45  5b  5  96   `d  $X	  ,66  -7'7    <8-  9YI     .  <  
H  ~:Y3  ;4D  <a  =5  C  `d  	<  >  ?3  #@3  3  `  #A?8  $B{  [8  CL  D8  !E  F8  %G$  'HZr  8  9  Ie  JY  ,Kx  '  ?9  .LnA  LM9  YN9  rc  ?sO  O9  `d  9  ):  	PQD  5  D  %`d  R=  S  TD  `d  9  U5:  V'  ;  <  `d  ". W<  XĘ  Y^  jh  	Z[%  5  *  &`d  (a6  )\s+  ,]v  ^  -_}]  .`  /a  0bf  #'  ,  3c
w  g  d-  -  e` ef  g3  '4  lJ  r  #h1  =i1  (M  Nfz.     #     &   q   m   I}   n      &Q         ]   L   =   /V   P   :         W   T   F   ^<      1   U2   ]            /   a   w   d-      H   `7       ,u      iy   O   W            8:   w   :   I      =>      F      w   \   6;         l   t      }   A   1          m      :   Ś         O      W      ,   WA   =   x   r   v&   )   @         BH   s   ;      \|   oq   J   0   O6   !   Q?   o   L   -   J   ]/   @      V   4      P   [       o   :   6   ^          I   ul   +n   :   Q   Ŋ   o   I      +   .   $   ^!   gi   +   U         O      i   g{   %   S    7         X   '      O   $N   )    U   i8   f#   7   5   -   6   %   )      y   |   ʮ      })   1      Q   @G   h   <&   ĸ   \   C   T      >2      +`   ݍ      M   n   
   ī   R   C      D      o   ]   4!         '   (1   -   f=   h   x   A~   7   J   ۙ   u   !   |   D   Qo   h      >   -                !   /   B   #      Jn   g   2   +   ׷   Z         s      d   ;   L         >   &   S   N   W      q   O   ~      w   5   iU      V>   U      A   3      n9   Au      _      R      L   _   x:   7   -      !/      =   @   jR   1   p   $      V      ^   v   +]   H   K   tE   2      NQ   P   S   6   cd   ք   Da       `         7   {c      D   "      t?   R   lz      A         N      [   ^   *G      _'   9   G   %   \h   2   O   ]   m         8   F   /         -      n      +{      2M   n       ip   ~    \         £   1   |   	p   >      Nt   Ji   ?   a   *   x   5   f       D   ~h   s   _   U   zS      ,   A   AX   0   m   `   [Z   m   t   &   m   v   ֕      I      P         =    -   +   *   x   l   z      1               J7   u        Dd  X  .  .  `n  &      0  A    ~G  0    vZ  5  p  6  [  ;    M        X  :  ܫ      V[  f  >  Xw  o  A  A  m3  x  z  
( J(    n  (  F  y  9  &  v  \    `  .    .  J(      #  ;           M    ' t  M#  L  ~  U  D       =, g\ hׯ j k: m,w n p qM t uj ww< x9 y~ zu {1 }$4 ~n 	( Q     u բ 8  LL XK  { + ,\ f  3 xu A F  Ld A 1h L   - ( w o 2y u XA -   _  V   y 6  a s^ D2 #   r 9 ٰ F   F7 # ·  P  % e E T `  f . ] Q :  G> V sW   V  s ' D zI '  40 f  4 9 >l * ;h : U WF n /  T <> "p l M ; p _ u s  sR  '  s   N   { { m| C ; 6    n  OP J \r 8   I  Q  yM v @   ˪  `   & ד  Š  yp  & ћ        ( hL p  n 3 P ?e  % q  $ J    , b : \t 8   \ S l >    4 ~G  E| v B = p   f ̾ 1  "   h ;      D  eq X@ >  \ I } J H  * c F           Q   > 7  aV  6 0 Ec   _ :   0J D  > O 	  " 4   E  l  ;` )   &k  }h <y E G ; P / {     f8   P u8 ~  )  , #   $ h , H ܍ $  +     Y  S LN 9 i\ mc  1 O xB h< P tN >    ": # R . Z a  /+  [ x wx     e  3 \ o G9  ֹ  %  u D  ! g 9  w U  }~  r% I Q  _  *  9   '   Δ     ڽ !N  r ,  c q4 9a   p_ `
 7   2  Y     ! '    *T `. q	 # ~j . N o 1  3 J !  )   [ l  I   w  i  Y^  O   u U  L  3  . z  
  0 A y|  ; 6w v -  ]S  P u k G-  !  4 5Q k ' Z= _  @ 9 "  
 $ [ g ' I   4  v = C^ (E Z       P  M  v  : "      y x 0 !? } _ X ? P 05 " L #`  f #K J  @  ) K F 4 - i  .c %8 hd * K[   k  O   d + b      0   x  0 *  ] ho p w k #  ۪  Iz ̺ L O 9S k 	 	{ 	a 	= 	X 	] 	ݷ 	v 	m 	iS 	 	O 	 	6R 	} 	E 	ʄ 	 	 	S 	 	> 	k 	gg 	u@ 	] 	I 	F 	w 	 	n 	3, 	 	w 	m 	q 	 	1K 		 	߆ 	MV 	R 	I 	* 	tJ 	^k 	h 
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 
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 
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C 
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 
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 
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 
 
 
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 
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 <8  , R G   ^    y ?   0  - _  eR H    K 4 !  %    0$ m ` 3    {c ? s f l ` Y  n  O  ښ B4 Q) l Wx  x ҳ va  ' x3 s $ ` Z   s!  < jv b "V = 	" = K  ' `' ] =o  Y r  R S        ل G  x % O
  Zb ɦ  X  C ̉   Ζ (Z  i   @ O* `  U S $ &q I O  .r ' ; p ; o, T- / R t  Q L= | ?I ] 	v f  h q  5   2   I5 3 Q. Z  3 	 l n  /3 o$  " O F ܥ  B  ؉ q   P   Y < I . ;  f  W  d  6 J X ~  ̻ >   D( 9  k    >  \ S 8  ! K  8  } +u W 8 E  ʎ %  @ Xy Hp m9 # n  @ * E  N, C V s J c b с B SH % v 7 _ D <  \ T !) i * # , w  ~- "F Z  b U Ka ~ = .X |%    u T  0  tQ N   & H ,  G '  #@  Ml  - < W O  m 0 0 B  I  d  J  z ^ y Br   ڬ &t - f I   Y  l HY ;      a # k 8[ U  	    F {  2s  /  e ` R    d F6      OC r  U p   ϥ   4 %m  8v  [} )< $   i  ) z  (a 8 ]Q  7  mG W qO "  B & P ݵ  p < / Ƚ [ [ ء  O 7  V - e    S ,Y 9 t 	 bx U\    H T B   `  Ri  K  }  - 6' _p  ] f _ 2     B  2 a B$  h 
  %> 7 | g`  ] _    a +  i " 7 r  d J  K C K  O }  ː -  R   Ϟ F~   {  Q   c  T   t  i;      c   ! cB f R   U l -p  G  /=  u N h G   M }  u . ^  w 4  L ܗ   G a  ]   .   *# # (   z  +  L& X| hZ cY :    E A 1 &2 2L  = _  N{      P ȱ   a n : r (D  E:  0  s> k t | " 9j / H :D ' a  }w u" V :  ) gt  d   4 P 5  G ; P m : O *    6N e 4   r Z hm Ɨ  C P ] < ^   P  d 6  % h F #   @ F    [ Ro n   / -9  Q# ,6      g  J  X .}  uq  r W 9"  ʃ  	 1 ! 2 \ X ߒ u   r Ӡ C  j] y 4 n  o } u 2 :f ;   O m d 7   "' ] Y  ,  # : Cw  Fv  \  u qF W  ʭ  ~ Fh - k#     ^ Ώ   y g QE  6 & | b?  H   t
 m 	 1  L  7 r+ X ͘ Z y( O q  "  fX k   I   [   \9  " l ? <U _  s v    j J  " S` k a e x ' q   -|  $    1  [! h  z    .    >  1b  m    (I K  q Z$ Y 0 D z FJ 6
 ~ 9 j W:  n /    ( 4  S C  [h  c >0 B  U1 .  af F S> o6 M  }  M  [ % -V  b '   ռ  d   d h 0 I    .   Z  .4   vv ;  ޜ  t   }   <  3- ޛ   K _  9 |   p ^  ( ; J }^  R   I = Y ]3 w   ( >  V @@ <   9+   ;     	 T   m  S _ { f T ` Č Z  z  ! v     7 =E j  G  #v Έ     A    ]   X $ Y Pn  | s 3d 6   uk   b Zz J :    { OD    U n}    B  D   T { | dD  ! F  % Bx ; & Eu   X ( Y S , ~ J o    { JM  _ 3 f M    b  1 9 	a +_   T 1 g  r   I o g A  Tw 	   H  b  { +H  c   	  f D ڲ  As      5 J / -{ :! f W 2 *  ǅ O7  $  b W y [     r w\  k ^  K zC [ h O  o E  yV    Y   7z l r ; B e / NU F    0e 7 p  1 *     "! > l  ^ Bn p s)   \    +   ?  >  @ M 9 6 d  e  n  Y Z G  [ % P   d EO    & E    Q   {   ]    \ ;  F  dE : e da ޖ z 9k  %  i= A  @    a" 	  $ l z :M t y b   O <   Pf    = = ( Sg   ( z   h ~   <g  C   D  / ^) W   :< 1  R      u hr / H      ^ O f ם  X  i  ki 9 z d 41 MG = 1; [    d  Z Y Z  c 
 * Uv j  j ? K   C    dI J   ~ 2 %     tg 3 ^ J_   ~s ? 6 G S   a T M - #  < _ $ L   n ߔ u S<  cA "   h f ۙ     6 B 	     >  s ( } i wA  ]    : D 	 ; H  Q 8 _	  E3 }   c  N' Z  q ̙  ~ ' g@  f >* Mk  k     , 0 ? 5 {e n U }    % m   I    5 X  o r  ( 8  @  * ? A yz  Ț s l W;  $ p5 x R Nj 0n # 8  ? @ W  '"   Vd  +l  ]* $
 A ? +   w    tS fu , o Y l{ ܇         > 3 E c   ac  ϕ : \   >)   . ^   Fb U : 4x L @, 
  I h  L a E A   `   0  xX   ! C 	u Q ]%  L H u?  2 S    7 ~5 y  ae   m =  Q LS         ;   Q  7G  E   d t j kK ޭ 7  Z      7  
  s m  Ҝ  / v ' uy % 0   PZ   M F  a( ~ / B N  +  +  M j  S >#  4   q ! } U  "f 
 7 i * 5 R q b  'U R ё 6 ) - z     R ;] W4 R k I {  ^C  T  :  [ RT 3 r     :t A v H} ) H @   K? (/ ~ ; -* (j ( S  6 %S ? + o i "  . P ; ѧ n   w z e[ h   3   z    }t - D 8 B 6q r  m 0 	 j: A   Lq  q2 1 " 
 6 k ~{ XO      h   q    ub & y @ h < %  X  @    g   7   
    ¶ n 5 
  > r `T p 2 ~ 1   " u  l0 ] 7F ll ? N Y d V z 9  j { n R v   #,        OI t y J uU   -  ²   V x   U @  T ʟ F	 \U    n / 
 HX  v s  M '~  l    x p   E     E  /i v  a 5   E m z ~ o* ]/   f      Ԋ   x  j ^ 5 Ѹ  _ m  x l    ܘ  S  g & I G 1& z  k x  8 >  * ~ N2    /    =   *  >\ Ne ~ ' ! l l 5  1 { J B  M  9?  |  ?  fs       _  {  `    j    }    8  a&      aF  e      RY    l    Ȇ  zE    V  v'  z  0  r  ق    q        V  It  >  %0    +    5      ]2  )  ؋    f  Ѐ    ֫  f  '    d~        >T  N  6P    a_    a        G    O  .  Y    Q  D  HQ  n    ͒  s  c    b  &    R    "  _J ! ! !pH !6 !I ! !t !f !E ! !g !u !h ! ! !g- !-( !_P !%] !H ! !e ! !0 !] !e !# !A !ؾ ! !X !x !; ! ! !q !EK !C !w[ !3 !|= !:  != !tL !? !  !G ! ! ! ! ! !8 !u  !L% ! ! !m !{ !~# ! !jM !K !H !} !" !y !ǵ ! !& ! ! ! ! !3 !
 !-^ ! !NR ! ! !, !ǩ !) !X ! ! !9Z !	 !ʹ !w& !]N !9 !$ ! ! !K !, !I !`  !~ ! ! !p ! ! ! ! ! !O !U6 ! !s !j7 !y !>A !% "+ "M "i "I "t "E "3C "ln "[ "h "- "
 " ": "Ű " "97 "D "? "@R "Z " " "  "6% " " " " " "w " " " "' " " " " "5 "b "t " "1 " "w ") "+ "Y " "e " "6 " " ". "r " ". " "O " "v " ") " "j " "l "( " "* " "R " "} "
 " "# "o " "Y " " " " "	 "t. "H/ "p "# " "D "` "Q " "> "8/ "T] " " "W "| "5 " "k "/ " " ", " "g " "C " # #[    tP V $Nl )s 0w 8m @f D(x I#u Qxq hm uh  v%^ wk ~?e Pw s  |h  r k p    '  (x *  o      b ^  k    6   `  3  ]  FW    u  s  d  d  e    a  !  ީ  ?  Y    
)  fE    B	  B  ^y          3  R  &    &  B  5P  v  JD  j  1[    *[  ]  3        z  .  A 	T  B  $  `   !N " #I %5 & )y @ AR    W  N    =E    N  %  l  :  @  Ϗ  k     P  Q|  R  SM  Tk  VI  Y   \i  a,  by  fpI  i*j  j  kJh  mX  o  po  q7  s  u  v2  w)  y  %  l  :  )  y  5  f  i            *1?@J         \dg         



 

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                !! #### $$$$ $$$$ $%%% %%%% %%%% %%%%          CCIK]b                    $$+.         		



 	




 				



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                                    !!!" !!!"  !"""#   ""           #$$$ ##$$$$ #$$$ ##$$ ####$$ #### $$%%%% %%%%%% %%%% &&'''''' &'''(( &&&&''''(( '''' '''' '''''' '''' ())) (()))) ())) ())) (((()) (((( ****++++ ***+++ ********++ **++ **++ ****++ **** ,--- ,,,,,,,, ,,,- ,,,, ,,,,,, ,,,, 0000 0001 1111 2222 2222 2222 333333 33333334 333333 333333         xo      Y o      .27 p      
//6: p      	. p      	+. q        q      	 r      ? Bs      A Bs      A u      "9 u      &9 v      @Fqt v      39dg v      39JJdg v      JJ v       <<AD w       	116:=@QQ y      	 z       z      
.. {        |     	      |       |      	      |       8}       ) T}       }}       }       i      g	      p      ),4                            @CEH M        `       d       	 d      	 |       	      	      x             	
	      z      
	      z      $+/6
	             ɉ      	

	      ɉ       E        ^       x       X      X	      _       % x       .                    			
 V      j		        ,       G             &>B       #;?        `n     G	     ( _             



  	

 


 


 

                       9         %b 8:?b    "        )6 66=]             		                                  8<BENS\ !       &       
%2 &       '        0> B      + m      $ m                    
"' O       @     	      `      	      z              ݳ      !      	                [`x  *        
%ns} %ns} %<FLs} %<FLs}          	 				          ""%%       ""%% %%    "#$$ ""## **,--- '''(,, &&&',,   ##   '''',, !!(((),, !"((((,, #$*+++ #### #$++ ##++ #$$$ $$$$ $$$%,,,, ,,,, &&&&''''(((()*-------- ++++ .... //// 0000 1111 11111111 2233 4555VV 44444455 55556<<ADDFPQUVVVWWX 66<===== 678;<<HIJKLOQRRSTTVVVWWX 9;<<HIJKLLLLMMNOOOQQQQRRRRSSTTVVVVWW HHII KKKK NNNNNN >>>?WW ?AAAIIII 5555 555555 ACCD AAAACC AAAA ACCC BBBB BBBB BBBCCC BBBCCC CCCDDD CCEEEE PPPP UVVV XYYYYYYY ZZZZ[[          2: ::Aa   				 	
          V         )6 66=]              	                                                  9     J            xx                                !      ;     9       )     @;            ;                 F                 Q                    F                 ]                    e                 x                 "                        `n     ^            n     5             o                 q                 |     /          	                PT&            $    `T&            /    	            J                       pT&            ;                 Q                   Z                   ؖ                   d                   o         ~       {                               DZ                                                                o         ~       {   p                               	                P(                                   0     J                 @                                 T       1    @            >    H            L    x             W    L            e                   u                           A      o    p     ~       {                        :               ^           @                              o                                                    o         ~       {   P                                 `                               &                   .                   9         1       K         1       ^         3       q                                            1                                               @     x                           @                P                                   !     7            "     3       &    @"     3       5    "     3       G    "     3       X     #     3       p    @#     3           #     9           #     :            $     5           @$     3           $     3           $     6            %     3           @%     \            4     *          %     X       )     &            7    '            K    `(           c    -     3       u    0.                .                /     f          P5     +          9     {           >                B                F                J     {          N           5    R           R    V           h    Z               ^               Pc     M           c     M           c     M           @d     M           d     M           d     M           0e     M       )    e     M       G    e     M       e     f     M       |    pf     M           f     M           g     M           `g     M           g     M            h     M           Ph     M           @i     M       (    i     M       ?    i     M       W    0j     M       o    Pl     H           l     H           l     H           @m     H           m     H           m     H       	    0n     H       %	    n     H       ?	    n     E       V	     o     E                          m	                	         9      	    І           	         a      	    @            	                	    0           
         w      3
         ?      X
    Я           
                   
                 
                
         N      
                   
                   
    @     4       
         7                E                5       4    P            M                q         5                9                *          @                	     
                u      2         o      Q          U      *    ?             w    `                                                   P          `                0     P          	     
       9                   I                ]    	     
       #         5      v                                                  	                               P                                "           2                   :     /     8       Z    `/     3       x    /     3           /     3            0     3           `0     3           0     3           0     3            1     9           `1     :       $    1     3       4    1     H       I    02     z       o    2                4     H           4     H            5     H           p5     H       6    5     E       Z    6     M           `6     M           6     M            7     M           P7     M           7     M       9    7     Q       Z    P8     C      }    9               :     D           <               =     b           P>     :           >     [           >                ?     5          A     .      B     C            f    C                D               F                               I     T           I                J           8    `M     `      U    T     {      n    @\     c          `               Pc     ]          d               Pi     &	          r               @w            %    `x            9    Py     ~      H    z            W    {     *      v    |               `                                    f                         0     '      "    `     r      8               M         E      g               x         =                                               "           )                )     t          )     I       ?I                       @                                                                                      )     i                          *         ~       <                &                   H         ;       U                 e                q         <       w                ~         q                8                              P     c           @     2           @                            .                            1                           "                     z                              P     a                       2               G                Y                   h                   w                                                                                                                ;                         $    @     m      A                 T                 g               }                                           H                             `     l          5               p7                                              +    :     J       =    :     O       O    @;     Q       e    ;     {           =               >     Q           `     `                           ?                  @                      @                              B            6                   F    pC           ^                  l                 y    `E               pF                                  H                                 M     E                              O                )                "                "            $    X)            $    @)            /                   
                   ?    p     <       M    p     7       \     q     1       t    @q     3           q     3           q     F           #               r                s                s                pt     N          x     Q           z     k          {           (          &      $    )            v    x#            J    p)            U               q    @     	          p#            F    @@                       b          #                                                                           5                                      0    p      X       D          Q      V    0     &      m    `     @                          @     	          P     0          #     @           @     p                                                      E       
                     p            *    P     s       @    9           `    #            q    :                                  #                                   @>     Q           >     j           H9                09                G           $    )                )                Њ)                J     w          P9            %    D9            3    @9            C     8            I     4            U   X           Q    (9            Z     9            "4   89            c    `9     (       x                       c                                                     j     \          l     !          A               o     `                             `{     x            |           q    ~     /          @     c                 N            Ѓ     ;       $                 1          Z      ~          G      <          H       Q     9     @       ]     9            i     9            q                                        В     A                	           )                                          m           P     m                                m      !         y      *!    p           ?!         5       R!    P           q!    p            !     :           !    :            !     :            3                   !                !    P     a       !                !    B           "                        '     5       !    '     5       !     (     @       "     3           4"     5     N      R"    @     (            ]     $      Y"    ;            $     )            _"    
     }       }"    
            F     ;            "                   "     }           ]                    "         3       "         1       "          I       #    p     2      #               "#    
     ,       3#               M#         W      f#                 #         {      #                #    @           #    )     8       #    <            $    
     
       +$    
     
       D$    
     !       ^$     <            l$    ;            }$    ;            $    ;               <            $          	       $    P     q      $    ;            $    ;            $    ;            %               %    ;            -%    ;            B%    	            W%    ;            b%                   r%         /      %         H       %                   %                %                   %                   %                   %                   %    P     Z       g    <            J                   &                   &                   l    d           )&     h           8&     i           T&    0k           e&    @J     0       q&    @I            &    w           &     <            ;     <                |     i      F     <            &                 i              &                &          W      
'    `     J	      &'    @           9'    `     '      T'    0           d'               y'                   '         G       '         y       '    P     }       '               '                   '                   '                   '    <     @       (    @<            (    `<     @       "(                   2(                   C(                   Y(                   j(                   (    <            '    @=     @       (     =     @       ~(                   (                   (                   (    =            (    =     @       (    J     P      n                   (                   (                   (                   (                   (                   )                   )                   )                   !)                   ')    =            0)    =            @)                   I)    0           )                   U)    4     Y      b)                   l)    A     G       )    A     n       )    @B     9       )                   )     H            )    H            )    I           )    K           *    T           *                   *                   #*    n     C       g                   1*     o     W       B*    `o     <       [*    )            d*     N             t*         `           0>            *    {            *    }     j      *    @>            *                   8>            *    ,>            *         #      *    (>            *    M     (       *                   +          :       +    @     e      /+                Q+    P     t      m+    Ы            +                +    @     E       +         t       -                   +         C       +                +         >       +    0            	,         R       ,    P            9,    0           L,    @N     (       J    )            $    ȫ)            ^,    X>            r,                 ,          f      ,    @     M      ,               ,         a      ,     )     H       ,                   -                   -                   -                   (-                   6-         I       G-    0            [-         t       l-    P     o       -                -         i       -                 -         }       -    @            .    0           .    &            ;K   )           F.    `=     *      g.    `>            .    ;     a      .    >                              .    K     3       .    K     3       .     L     4       .    @L           .    @O     w       .    O           /    Q            /    @R     n       +/    R     W       </    S     W       J/    pS            V/    PT     I       a/    T     I       p/    T     I       /    @U           /    W     I       /    @X     S       /    X     P       /    X     P       /    @Y     w       /    Y     P       /    Z     P       /    `Z     P       0    Z     P       0     [            D   [            (0    \     #      ;0    ]     ,      [0    ^            v0    _           0    `           0    b     ;      0    c            0    d     K      0     f                )            /   f     ?       0     g           0    h           1    i           M   k     n       #1     l            $    Ȭ)            21    l           L1    `n            J    )            _1    n     3       j1     o           1    q           _!   s     k       1    0t               )            1    y           1    {            1    P|            1     }     	      	2    0~           2               22         O      A2    0     k       O2         k       _2         k       l2         k       |2         k       2    `     k       2    Љ           2         Z      2               2         6      2                2               3    `           3                &3               83    0           N3    0     _      a3         o      t3          b      3    p     J      3               3               3    P     f      3               3         =      3                	4    @     x       4                *4    p            ;4    P            I4    0            ]4    0            n4         D       |4                4    0            4               4                4    p     Q      4    0     9       $    )            4         X      5     )     @       5                 !5          `      55    `     P      K5         Y      \5         E      o5    `     9      5         g       5                5                5    p            5          q      5               5               5         4      5    a>             6                6    p            6                    `)     !       .6                   :6    @           O6    P           h6    `     #      r6    %            6         ?      6          d       tX   p>            6    ]     e       6    @!           6    @#     ]       6    #     E      6    $     S       6    P%            7    (           57    +     	      *    l>            K7         R       f7    5     |      h7     <           x7     D     ^      7    I           7    h>                P)            7                                      7    o            7                7    >            F     >            7    >            8    t            8    u            08    ՚            ;8                   E8    ~     s       S8          K       a8    p     ;       p8    >            x8    >            8                   8         D       8         @       8    P     E       8         ~       8                 8                9                9         b       &9         8       39    `            \9          [      x9    `           9    `     p      9    А                )            9         =      9    `     h       :    к            ":    >            W%    >            *    >            $     )            ):          \      W:    P           x:                ?I                   :                   :    0)     u       :    )            :    `*            :    +            :    @,     l       ;    ,           ;    /     )      2;    0     Y      F;    @2            U;     3           k;    6           ;                   $    P)                @)            ;                   ;     V     1       ;    @V     N       ;    V     E       ;    V     t       <    `W     :       /<    W     k       E<    X     h       _<    X     7       }<    X     E       <    Y     F       <    `Y            <     Z            <     [     @       =    @[     5       (=    [           H=    0_     i      U=    `     i      g=    b     m       =    b     f      =    d            =    e     u       =     f            =    f            =    `g            >    g            ,>    h            B>    i     1       d>    i     J      q>     T            z>    l           >     o     E       >    po     e       >    o     u       >    `p     u       >    p            ?    pq           +?     t     ;      N?    `v     :      n?     x           ?                ?         R       ?    `     a       x         5      ?    0           @    @     E      !@               0@    @T           E@    p               )            k@    0           ~@                   @          =       @    @     <       @         =       @         @       @          @       @    @     @       @         =       A         =       "A          @       /A    @     =       ?A         =       MA         =       eA          =       sA    @     =       A         =       A         @       A          =       A    @     =       A         =       A         =       A          =       A    @     @       B         @       "B         @       6B          @       NB    @     @       eB         @       {B         @       B          @       B    @     @       B         @       B         @       B          @       B    @     @       B         @       C         @       #C          @       6C    @     @       LC         @       ^C         @       rC    @     ?       C         ?       C         ?       C          i       C    p     i       D         i       6D    P     T      ]D         i       zD          i       D         i       D          i       D    p     i       D         i       D    P     i       "E         ?       9E                 FE                bE          ?       E    `     ?       !                   E                   E                   E    `     4       E         7       E                F    p           F    >             F    >            (F                   9F    >            HF    >            TF    >            _F    >            sF    >            }F    >            F    >            F     X     @       F    @X     h       F    W             F                   F    ?            F    X     H       F     ?             G    v           G     )           7G    g           UG    )           tG     Y           G    @)           G                                 G          #      *    `     0       ;     ?            G                   G    @     J      G         8       ;     ?            F     ?            H                   H         _       H    @?     H       &H         F      ;H     ?            QH    %     
       kH    0            H               H                   H    !     9       H     "     [       H    ?            H    2           I                   %I    P4     4       .I    4     7       8I                        ;     ;       EI    @;           `I    `=           yI                   I    G     ?       Cu   L            I    PR            I    /            I    )     \      I    )           I    )     t      I     )     t      I    )     \      J    @)     4       J    )            J    )            )J                   >J    @           PJ    )            `J     )     ]       gJ    )     `       oJ    )     ]       xJ     )     `       J    `)           J    @)     ]       J    )     8       J    )            J     )     8       J    `)            fO                   J                J         ;       J    P            J    @     z      K         y       K    @     t      0K         O       QK                mK                K    p            K    p     '      K               K                K    p     0      K                K    `     j       L    P           !L                :L               NL         ^      iL                   pL         ]      L                L                %   `            L    P            L         s      L    P     !      L    ?            L    p     S       L               M    ?            M    p*            ?M    ?            cM    ?            xM                M                   I    -     ?       M    6            M    C            I    @)     $       I    )     $       I    @)     D       I     )     $       J    h)            J    )            I    )     D       M                   `J    @)            gJ    )            oJ     )            xJ    )            J    )     
       J    )            J    )     
       J    )            J    `)           M                   M    `W           M     Z     ~      N    [           N    c     M       #N    c           4N         (       LN          (       ^N    W            wN                   N     {     4       N    @{     7       N         X       N    `     `      N    P           N         X       O    @     X       O          X       +O    o            FO    z     	       aO                   lO                ')    ?            uO    ?            O    p     Y      O    Х     Z      O          x       O                O         	       O                   O         7       P         Z      P         E       -P    @     E       ?P                   KP    8E            SP    XE            \&   `E            ]P    @E            jP    D     P       K   HE            qP    PE            y   0E            P    C            P    ?            P                   P               P               P    hE            P               P                   P    #     3       Q    #     1       .Q    0$     T       QQ    $     T       qQ    $     T       Q    P%     T       Q    %     3       Q    @            Q         0       Q                      1     
      Q    E            Q    E            R                   R    6           .R    7           8R    E            AR    E            HR    E            QR    E            XR    E            aR    E            hR    E     !       )               vR                   R    PF           R    E            R    E            R    E            52    pG     }                         R    Q     E       R    R     E       R    `R     o       R    R     E       R     S     E       S    pS     3       1S    S     =       ?S    S     =       US    0T     M       iS    T     =       zS    T     =       S     U     L       S    PU     =       S    U     |       S    V     |       S    PW     i       S    W     q       S    @X     r       T    X     o       T    0Y     =       (T    pY     =       :T    Y     =       PT    Y     i       bT    `Z     V       wT    Z     V       T     [     =       T    `[     l       T    [     l       T    @\     =       T    \     ~       T     ]     v       U    ]            U    ^     F       $U    `^     S       9U    ^     S       JU     _           ZU    @`            vU    `     L       U    0a     V       U    a     V       U    a     L       U    @b     a       V    b     O       'V     c     L       HV    Pc     S       gV    c     P       V     d            V    p            V    d     L       V    d     T       V    Pe     L       W    e     T       5W     f     L       VW    Pf     T       ~W    f            W    g            W    h            W    0h            W    `            W    h            W    `i            X    i     n       6X    `j     P       PX    j            jX    k     l       X    l     e       X    l     l       X    l     q       X    pm     g       X    m            X    n     g       X    @o            Y    0p           4Y    q            VY    r     -      Y    s            Y    `t            Y     u            Y    F            Z    u            Z    v     5       "Z    v            >Z    w            XZ     x            iZ     {            Z    {     v       Z    |     v       Z    |     v       Z    }     v       Z    }     v       [    ~     p       0[    ~     l       T[    ~     5      q[    0            [    Ѐ            [    p     U       [    Ё            [               [    P            [    p     L       [                \                3\    P            O\                _\    Њ     +      \          r      \          }       \         3       \         v       \    @     v       \         f       ]    0            1]         b       K]    P     b       g]         V       ]          Y       ]               ]    `     3       ]         5       ]         5       ]                ]                ^                ^    З            ;^               Z^         e       n^         e       ~^                ^    0            ^    М            ^    `            ^                ^    p            ^                 _    @            0_    0            F_          E      Y_    p            l_    0     r      _         
      _         
      _    Ч           _                _               _         
      _    Ы             `                `    p           /`    p            B`    `            S`    P           g`    p           y`         ?      `         
       `          ?      `         
       `    `           a         
       4a    0                    J      Ra    P            ea                va         e      a    P     [       a                a    `            a         m       a    p     m       a    `֚           a    ۚ     0      b     ښ           *b     ٚ                              Ab         3       Ub         5       fb          <       yb    `           b    P            b    @     d       b         R       b                 b          n       b    p     z       c                3c               Wc    @     3       qc                c                c    p     3       c         3       c                d                'd               =d    @
            Rd    @           qd                d    @     G      d         H      d    "           d    @)     z      d    `-            e    -            &e    .     l       Ce    0/           be    03              F     I      te    `J     .      e     O     <      e     X            e    X            e    Y            e    @Z            f    l     F                          $f     n           4f     p            Ff    p            ')    F            Wf    F                                ff    ~     {       |f                 f               f    F            f    F            f         }       f                 f    F               F            $    *            f    F            f                   f                   f                f               g    F            --                   g                'g               5g                Eg    `            Qg                   Zg         0       lg                   ug                g                   g         D       g          R       g    `     8       g                   g    @     y       g                 h                   o                   h         1       h          8       %h                Gh     G     (       Nh                   \h         f      kh    PG            wh    HG            h                   h         4       h         L      h         =      h    P            h    P     $      h                i                 i                4i          P       Di    *     (       Ui         
      ci    `            qi    0     F      i                i    P     C      i               i    0     	      Zi    @           i    0.     $      i     ,           j    `!           'j    @&     _      5j    XG            Dj         P       Tj                   ej    C     9       j    C     5       j     D     5       j    `D     5       j    D     5       j    D     5       j     E     G      
k                k    pF     <      +k    G     G      Ik     I     <      dk    @J     G      k    K     <      k    L     G      k     N     <      k    `O     G      k    P     <      l    Q     O      -l    @S     <      Hl                   Ql                   V   ]           [l         *       ul                l                   l    G            l                l    `G            l    hG            l                   l    @u     A       l    u            m     v           -m    x     j      Fm     z           km    }     %      wm         "      m               m    `           m    *            m                 
n               ,n               Mn    0     _       gn         	      B                   n    "     /         #     Q      n                   n                   n    8           ;     I            F     I            n    I            l                n                   n                   n                   n     B            o     C           o    F           (o    H     Y      Do                   Lo         @       To                   ^o                   go                   po    s           o    pu           o    0w           o                   o                   q                 o    ચ     `       p         0      .q    Ћ     K       'p                 7p                 Lp    *            ^p          (       jp                   p                 q         x       .q    p     5       'p    `     (       7p                  Lp    *            ^p    `     (       p    @             p    @            p                   p               p          (       'p    I     (       p                
q    @     0      q         <       (q                7p         0       Lp     *            ^p         (       :q         (       Gq         p      Wq                   q    `            hq                .q         K       'p                7p    `             Lp    *            ^p         (       {q                   q    `     Q       q    ක     P      q         Q       q    @            q          Q       q    ບ           r         7      r                'p         8       7p                 Lp                ^p          (       p          P       1r                Br                   Qr          ^       fr    `     ^       ~r         ]       r          5       r    `            r                 r                r    `     5       r                'p          0       7p         P       Lp                ^p    `     (       r         (       s         (       s    @     (       s    Ú           ,s    ʚ            =s                   Os    Κ            as                   ls                vs                s    p     	      s                s                s    @            s                s         2      	t               t               (t               9t               F     I            Gt         '      ]t     Ϛ     @       mt               t                t                 t                   ^                t                   t    
*     0       t                   u         8       u                +u         n      ""   @K            =u    @J            Fu    ,J            au    (J            f    J     (       |u                   u    p%     N      u    &     $      u    '           u    )     n      u    @,           u    @.     c      v    0           v    5           ,v    @;           >v    =           Qv    C           cv    E     h      rv     G     K      v    pK     1      v    N           v    S           v    [     ;      v    a     c       w    @h           w    @     `           *            &w                                      -w                   8w         B       Sw               hw                vw               w                w               w           T      w               w                w               x    `     %      &x         |      ;x                Ox                dx         s       xx                x    *     `       x    *            x    @*            x               x    P           x    P     S       
y         s      *y    0           ?y               n    HK            Uy         d      hy    `           }y          i      y                y    0            y                y    	            z    p            (z    0            Bz                bz           
      z          2      z    P            z                z                z    `            
{    @!      t      {    /      E      7{    1      U      N{    pE      6      ]{                    *            $    *                `*            p{                   |{    m      B       {    m             {    n             {    Po      .      {    q      4      {    r             |    ps            3|    `|             L|    `}            d|                 t|                |    @             |    `     0            *            |                   |          B       |    0             |                 }    Љ            &}          )      8}                \}    `            F     LK            }    @      6      }                }    p      s      }                 }          C      ~           &      "~    0      &      <~    `            P~    @     0       ;     PK            d~           I      {~    P            ~    p      D      ~                  ~         8       ~                 ~    @*            ~    *                *            )                   ?                V         P       j         (       u                       TK                                         3                 3                  1           @      ?                 H                       !    *            3                   J                 ]    P            y                             1                  3           `      B       π                     *                                                              /                R          +
      $     *            l                   }          3                 v           `             ʁ    P      :          !                @!     Z      !                   /                I         `       Z    `     8       k          X       ~                            P                                            Â    !     {      ׂ                                                         
    !     b           0!     ~       6    XK            B                   M    !     e       \    `!     I       k    !           y     !     n           @!!     5          "!                `#!           Ń    %!     h      ڃ    '!               +!                                p3!           *                   7    5!            Q    6!            w         8       4         p                           `     (                 (                
                       ʄ                   Մ                                                              Y!     _      	                       l!     C      I    o!     ?            x!            8                I     *            I    `*           J     *            I     *            I    *           I    @*            J    *     +       J                   W    !            `J     *            gJ    *            oJ    *     C       J    0*            xJ    *            J    *           J    *     C       J    *            J    P*            J    *            a                   %I    !     s       .I    `!     ;       h                   q                   F     `K            |                       @                               υ                       @*                0*                 *                *                 *            $    *                *            J    Ф*     
       $    *                *            ǅ                   ׅ                        !     X           `!     ;          !                K     @       "    @!     )      7    !     #      N    К            \    !     5      q     !     <           K                K     (            !               K                K            Æ     L            F     K            ׆                                          !     I           !     B           `!           0    !     ^      M    P!           X    ` "            `     "                *                0*                *                *            $    *                *            J    *            ~    `#"     P      $    p*                P*                                   O"               R"           ҇    0V"                њ     `           (L                 ^"                            -                   ;    |"           W    P~"           h    `"                 "               @"     4          PN                "           ֈ    `њ                "           	    "           %    P"           A    "           b    0"           }    "               "     h          `L           ȉ    @"                "               "     A           "           $    "     H      =    HL            R    PL            b                   q    	#     p          #               #     i          #           ̊    0#     L           #     r           "#                "#                ##     _      -    &#           B     -#            W    '#            j    (#           }    *#               -#     h           /#               0<#           ؋    >#               J#               A#           #    pD#            A                   M    K#     k       b    PL#     y       }    L#                PM#                M#                PP#            ׌    S#     	          U#     e      
     W#           !    X#           7    b#     y      O    e#     /      k     h#                i#                i#                v#            ȍ    Ѐ#                                   @            
                                2                D    @            U    `           h               x                    @                    @           `                               ͎                   ގ                                       ೙     H      (    *           =                   T                   f                   {     *                                                      *            ͏                   ޏ                   @     0          @*                @*            0                   <    #     J      M                 _    XN            9                   n    #     o      }    0#                #     m          #               #     Z       Ր    #               p#     9          #           
    @#     5      /                       @#     U      M                  (                   7    #     .      G    #           c    #           o    #     U       {    #     s           ` $     7          `N            U    @     0       M                  _    hN                                   $     X            $           Ǒ    $     &          
$            	     $           ,    $           O    0$           r    P$               `$           "    0$                              Ē     "$     3       ؒ    @"$     	           ,$     ?       
    `,$     (           *     
       '    ,$                *            A    P-$     1      J    /$     /       b    *            n    /$     P          O                Q                `*                3$                *                7$            ܓ    8$                9$           
    :$                ;$     F      5    =$     F      M    `>$     F      `    ?$     V      r    A$     v          B$     W          p*                *                C$           ݔ    E$                P     8           R            
    F$           "    PH$           2    0K$           K    N            [     *            g    L$     >          O$     |          0*                P$     1      Ε    R            ݕ    R$     N           U$               W$           &    \$     x      ?     *            K    0b$     
          *            _    '     7       x    Pl$               *            $    @*                `*                *                $               @*                Ј$     *      Ȗ    N     @       $     *                *            ז                   ޖ                                                                                                                  $    Й$                           8                   K    $           V    p$     	      h    $           u    $     f            $     
           $     q           $               @$     L      ї    $     @          й$     z          P$     2      )    $     ?      ;    $     m      O    p$     #
      b    P$     7           $     :           @$     #          $     U      ͘    $     7           $     :       	     $           %    $           A    P$     8      c                   v    *                *                *            ֙    *                *                *            -    *            B    *            \    *            s    *                Ȳ*                в*                ز*            Ԛ    *                *                *            '    *            @     *            ]    *            v    *                *                 *                $*            ۛ    (*                ,*                0*            &    4*            A    8*            X    <*            s    @*                D*                H*            Ȝ    L*                P*                T*                 X*            8    `*            W    R            w    %                x%                %     D                             *                                        r       ,         0            R     $                          %    8            >    Ⱥ*            X    H            o                   |    R                xR                                   J%     @      Ş    PK%           ݞ    L%     q           pM%     ^          P%            1    Q%           E    W%               *            J    @*     "       $     *     $       V                   b    *     l           *            r                   {    @k%               `l%                               n                       t%     u      ')    hS                `S            fO                        x%     ;      ß    S            ҟ    S            ݟ    @y%               S                S                Pz%     ,      8     T     0       G    S     0       V    S            k    S            x    1T                0T            To                   ')    3T                2T            8                       %     p      3                   Р    І%     !      "                   *                   ]                        4T            ^o                       %                 %               8T            )    ę             8    ^     
       as                   -w                   Q    %     5       d     %                %                %                %            ͡    0%            Ox    Ц%     q           P%     !          %     G          Ы%           $    0*            )    %     }      A     %     q      T    %               *            o    HT            }    @T            p{                        %     6           @%     5           %            Ԣ     %     M          P*                P%                %                p%            8     %     /      L    0%     ?      h                   r    %     i            %     5          `%                @%            գ    %                %                 %            #     %            7    `Ӛ     h       C    Ӛ                               R    &     =       c    &     @       {     &     3           @&               P
&     y       ˤ    
&     |       ޤ                    P&     <           &     O           &            '    p            0    p&     <       H    &     O       `     &     <       o    @&                &     l           @&     |           &            ӥ    `&     J           &     j            &     v           &     Q       /     &     E       >    P&           O                X     &           i    `               h                &     f                       ¦     &     f       Ӧ                    &     c            &                @     (            &     c       &    p&     O       9    &            K    P&     R       _    &     R       t    &                &                p&                                 &     R       ǧ    p&     O       ۧ    &     O           &     U           p&     /      (    !&     k      A                J                 [    $&     
      s     %&               0&&                5&               &&     >           `           Ш     '&                                             @+&     ]           ,&     L      3    -&            D                M    .&            [    0=&     ?      l    @/&            ~    /&     h           `0&                                1&            ǩ                ֩    1&                @2&                2&               4&     =       +    P4&     =       F    4&           Y    7&           u                         h                                      Ъ                                
                                 6                L               b         @      r                          P           @"     !                      ī    "     !       ԫ                    @     h          "                `            /          P       I    "     /       W         `       i         P           #                     P           0#            Ѭ    @#     "                          p#            *    `           E    #            Z               s    #                @               #                     0      ׭    #                	     0           $     $                      3    P$            H               a                   l                 n                      `                                 "             ʮ                 ֮    "             \                                               _                @          &     W            }           -    "            F    "            `    "            {     #     (           P&                0#            ͯ    @v     H       ׯ    l     %           w!                               '"               s#                v     H                %                       )     w     H       5         %       G                S    `w     H       _         %       q                }    w     H           8     %                            x     H                %       ǰ                Ӱ                         |           :                     D                 p          0Q&            !    ="     6      0    $            H    (            ]                   l    @f            y    5.     B           w.     B           .     B       --                   k               ±                                           7            ȱ                   ֱ                             .           .     .           \     _                @               W           R                     0                                          !                ,                4                <    ,             C    L     >       R                h    k                E                \                m                                      !                !                !       ʲ         !       ز    (     !           I     !           j     !                I                !                !       *         !       5    7     !       D    X     !       Q    y     !       a         !       q         =                e           ]                w                                                            ǳ         4       س                     	     a           h 	     ]            	                 	            &     	                 	            7    	     i       C    v	     y       W    	     u       f    d	                	     "       w    	     8           	                {	     "           	     !           	            ̴    	     W       ״    3	     +           ^	                t	                	     1           5	                	     -       '    	     *       '   	     O       8    a	     1       D    `#           U    @%     x       d    %           r    &                	           (                    x                 y                	               
	                	            µ    Y	            ׵    	                	     @           4	               C	     X      '    	     d       6    I	            B    	            Y    C	     l       o    	                4	               R
               '	            ƶ    B	     f       ޶    	     ~          &	     y	      "    "	            H    0#	           ]    3	            q    '	                a	                	                (	     k          *	            Ϸ    +	                /	                /	                /	            ,    0	     %       H    0	     y           	            X    ׊	            e    N1	     &      v    t2	                3	                ]4	     a           4	           ¸    5	     |      Ը    =7	                28	               	                I;	           ;    H=	            O    =	            l    v>	                q?	     M          @	                A	     }           B	     {      ƹ    C	               qF	               QH	     |      "    I	            ?    EK	            P    K	     #      _    N	     n      q    O	               >Q	     r           Q	                a	                0b	     5       Ⱥ    eb	     =      ں    e	     I           e	     n          Yl	     '           m	     o      ?    p	            U    q	     `       l    x	            x    :r	     /           ir	               s	     "          x	     H       ˻    x	            ܻ    y	     q          v|	     4           |	     .          	            (    	     \       ?    	            U    	     S      k    `	                1	               	     ,           Շ	            Ƽ    	     =       ռ    ?	     2           q	               	     {           	     
          	     Y       *    	     ~       9    	            L    	            c    k	           r    o	            ~    S	     u           Ȟ	     3          	               D	     H       ׽    	     !           	     z           '	     7      .    ^	           H    $	     H       [    l	           q    w	     i          	               	     :           N	     T      վ    	           J     )                	               o	     ]          	           ;    	           R    	            j    w
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W     1           ;W                W            ^    W     /       W    W     5       b                ]   x            q    ^                .p               ė                                                                   x                     C                ?           @                \     Z                                             °            !    ԰            ,                4                <                 C         >           \                s                                     !                 !       -    ݱ     ;       ز         !           9     !       >    Z     !           {     !                I                !       *         !       5    '     !       q    H     =                                                       س                    ͳ     ]           *                <            &    N                `            C    r     y                "       w         8           E            I         ;       ]          e       q         e                "                       ̴    *     W       ״         +                <                                           ι     I                F           ]                     9          *                               տ     P           %     +      )    P     l      <         l       M    (     `       ]         "      o         w                #           ?     X           >     K                                >                8           )     ~          k               m            2    3           H         #       Z         ^       l    a                7               F     8               z          g                              &                               c               *     9                       #    ~     _       ;               Q                j         M       {    ]     a                           ]     &               M          n-     !           A-                
     %           /           
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     I           
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    J     c          K            6    L     -       N    ;L     $       i    6V               <X               [               _               e                f                g     B          j     }       "    _k     [           k     T       9                N    ǀ           c    [     I      }                   ,    ň            4    ӈ            <                 C         >       C    ?     y       W         u           -                K     K           {                                    .               A                2                d               a                x       	    ]     ~
          e           .    k           >    ۠           S    z     O       i    ɢ     "       w         2                4               9          J                {                              ,    K                Y     H                                               N           :     i                              n            :         =      K    5           ]                m                z         ,                ?                          W         u                           N                              n)                     z           n)                C                n)     	                           n)     	       !                8    n)     	       ?    g            \    n)     
       c    '     s       x    n)                                n)                L                n)                     *                                                   $     o)                X            0    o)            7    ;     P      G               _               u         s            o)                               (o)                               @o)                      `           `~     p                             H                _                                                               -    /     ;           j                                            !    G            3                H    t     }      m         +                               P                             %     m          @%               %     L          T                pT            (    `T            >    @ř     0	      M    PT            _    ę     P       t    `     @               0                0                                 `                           `     p       
          0       !         `       8                P    `            f          0       }                                          @                                                            `ߙ                @ߙ            3    ޙ            L    `ޙ     0       f    @ޙ                0ޙ                 ޙ                ޙ                 ݙ               ܙ                ܙ                ܙ            2    ܙ            K    ܙ            e     ܙ            |     ܙ                 ۙ                ڙ                ڙ     @           ڙ                ٙ                ٙ                ٙ     0       1    ٙ            F    ؙ            [    ؙ            q    ؙ     0           `ؙ                י                י                 י                ֙                ֙     p           `֙            )     ֙     @       ?    ՙ     0       V    @ՙ            m     ՙ     0           ԙ                ԙ                ԙ                ԙ                ԙ     0           pԙ                @ԙ     0       '    0ԙ            ?     ԙ     0       W    ә            p    ҙ               ҙ                љ                љ                љ                љ            	    @љ     @            љ            2    Й            G    @Й     0       ]    ϙ            t    @ϙ     0           Ι     P           Ι                Ι                Ι                Ι                Ι            #    Ι            :    pΙ            R         0       f    p            {    @     0           0                      0                                @                           @     @       
    0                      0       3                H         x       m          	          @     x                 	               x           @     x      /         l      S    Ǒ     $      v    `Ǒ     ,           LǑ                @Ǒ                0Ǒ                ˑ            ?    ˑ            b    ˑ                               `     d               d               $                       >                m    `ߑ     $          Ց     	          ͑               @͑     h           ̑     h                X      >                _                    4     X          !                    (                l               0      "                B    @     	      d         d                0                  T          ;               `A               @A             '     A     8       G    @            i    @J                 K                M               \               [     <      %    |[            K    x[            q    t[                @V     4          (V                $V                 V            .    S           R     R     h      v    Q     4           Q                Q     ,           PQ                @P           +    _           T         X      |         
                                          `|     X           |     D       K    `y           q    x                u               r               `p     `         @k           6    j           ^   i     8          `i     d          h     p          f                   4              \      B        $       e         d          @     l         ࠒ     \                                        @           >   ଒           _        \         X                    l                              l          @           1   ǒ     \      R   Ò           s                  Β     4         ɒ              |ɒ               xɒ               `ɒ            C   Pɒ            i    ɒ     0          ɒ                ɒ               @ג     \         Ӓ           -   ђ           Q   ݒ           p   ؒ              ؒ               ؒ                                         $   @           J               u                                                      `               `      B               d   `                                                                       	         P      $	               G	               i	         `       	        x      	               	        t      	               
              *
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              
         T       
        0                    1        $       R         d       t   $              `j               Y     \         R     \         `R     $       &   `O           F   DO            s    N     $         B     D          :              .               .     h          -     x       9   +           Y    p     `      {   u     \         u               u                {                         !              B         h      a                                                       T                        `     L      &         <      G   ~     @       h                 `              0                    d                         @           4        ,      [        <         |               x               t                                         D               k                                      x         @     4                      &   `     ,       K   0            q                                 Ǔ              Ǔ     @          @ē     4      %   (ē            J   @           l         @              0                                        ʓ               `˓           B   @Γ            e    ϓ              ѓ                   <         `                          "   `            I         X      n        $                         @                                        6         `      ^    ݓ              ۓ              ۓ     8           ۓ     d          ړ     p          ؓ           A               g                 	               @
                              
            -   
            R   G     $      x    5              .     (         &              %     0                    ,        	      R   @     d       v         0               L         l                                        +        p      L   `z           n   y               x                v     T          u               r     X         `q     H      @    q     @       c                       `                             p                                    :                ]                        <                                                     @     <       1   8            U   @            w         8              l         ๔              @              ǔ     p         `           :   L            \                                p               @     0                       !               Q    ̔           s   Ԕ     D          `Ԕ     4          ͔               Ք               ݔ     0          ܔ     D       #    ܔ     4       ?     ה     d      `    `                                     D                4           @     @          @     <      !         0       2!                 M!        |      n!   `     8      !        0       !                !              !         4      	"         0       $"                 ?"   `           `"   `     ,      "   @           "         ,       "               "        T       #               B#               s#        P      #              #               #   
           #              $   `     ,       6$   T            Y$         T       z$               $               $               %   |            2%   x            ^%        <       %                %               %               %               &               C&               t&         D       &         8      &        <       &        8       a                   &   ,                                  &   i            '   ɭ     L      '   P            3'                E'   W     N       Y'   p            f'   3     
      y'         B       '   	     c       '   @V            '               '   '~           '   X            '   E&            '        W       '   h     x      (   `j            *(   5     }      ;(   9            I(   
            T(   Y	     7       h(         9       }(   N     =       (   l     /      (    f             (   1     Y       (        	      (   0y     6       (   "     ,       (        Y       )   h     P       )         n       ')   
     E      B)        !      Y)        A       R    M	     (       k)   @<     4       )               )   ZE     ?      8/               )   "                          )              )               o`  	               )   y            )         F       )   F           *   @     ?        *        	      /*              @*   5     9       J*                Y*        8      b*   ]j            r*   k     P       *   	           *   x     }      *   K            *   =r     M      "    E&             *   h            +        E       +   C     G      3+   PU            H+   pR	           Z+        Z      q+              +   <     c       +   W     u       +        :       +                +   X           +               +   c>           ,               &,   @             /,        n       =,   
     k      O,        O       _,               v,   >g           ,   .            ,   u            ,   Q     
      ,   O           ,   T     Z       ,   py     ]        -               -   Sj     c      '-   'i            9-    v     j       K-   i	     H       Y-    p            k-   l     V      -   u     U       -   R            -   =i            -   p             -   `            -               D)   	     >       -               -    k            .   _L     F      /.              rb         =       D.   	           Q.        H      _.   |     3       z.        A      .   H            .   `H            .   J           .   O            .   G
            /        T      #/   p     =      7/   0            >/   1     n      Z/   P     5       j/              z/   E     z       /   Г     N       /   DZ            /   W            /   /C     +      /    h$             /   =           /   	     _       0        d      %0   3X     N       70   p     n      L0              a0    l           .   _	     8       0   J	            0   z           0        b       0    N            0    X           0   `     M       1   5     0      1        +      &1 "  %     J       Z1   @%            o1   u     @       1   @            1   te           1                    1    U           s   (     R       1        {       1        3       1               2   P     o       2   @*             -2   @L     R      A2                    T2        Y       x2        C      2   |           2   !           2        @       2    X     ]       2   0     T      2   Г     a       2                    3   @     _       '3   0Z           ;3                    K3   d            Z3   *            q3                    3   0<            3        ^       3   @S     O       3   0     A      3   Ј     H       3 "       \       3               4   p           4    \     T      -4                    A4        @       Q4        S       b4                    s4        5       4         @       4   @q!     3       4        5       4   pZ     o       4                    4               4               5               $5 "  %            y5        Z       5   ]3           5         m      5   v#     B       5   p     n      5   :           5                    
6   4            6   @v*            .6        @       >6               Z6                    {6                    6                    6        C       6   V            6   0            6 "  X%            #7                    17   5           ?7   T     j$      P7               c7   !     k       z7              7   03"           7   w           7   0N     6       7   `            7                    8         m       8   >            8   p           28   p
            D8        f       S8        u      i8                    8   0&            8                    8   |            8        i      8   @     @       8 "  %     Z       *9                    89                O9   
            j9                    9   O            9                    9   !     s       9   pA            9   !     s       9   Pg     H       9                9   `     H      :        |      (:   0&     	      C:   &     f       ^:         b      r:   w     J       :   0     m       :         @       :   pj%            :               :   P           :   p!     s       :               ;   0            #;                    <;               ];               q;   L            ;   H
            ;   o            -    =     ?       ;   s           ;   0            ;   @           ;         `      <        ^       1<        P      J<   @	           i<   /            <                    <        o      <               5        5       <        8       <                    <   `            <   	     I       =   T     3      (=   y#            8=               E=   0            T=   С     =       m=   #     <       =   R#     {       =   j#     c       =   ]           =        @       =                    =    #            =        S       >                    8        [       />    p           G>   <@            \>        +      j>        8       > "  %            >                    >                    o   `            ? "              ?               #?   њ     `       =?   0F     z       O?                    i?              z? "  %     /       ?               ?   =     B       ?                    ?   F            ?   $            @   0'     y       @                     @               9@ "  %            @                    @   P#            @    *             @               @    #            @                    A   @p!     Q       'A               :A                    UA               tA   @     V       A    O     1      A                    A                    A        r       A   `B     6       A    p     \       B   P     `       B              0B   i%            BB   \     f       ^B   0     =       yB                    B   %     6       B                    B        ?       B "  %            C   p3            >C                    [C    g           mC                    C "  4%            C                    C   0w     8       C        h      C   0           C         d       D                    +D   1     5       <D              HD   *            kD                    D               D                    D "  %     (       ?E   `X!            VE   @     @       hE    }     i       E   Б     G      E                    E    =           F                    /F    3     l       AF   !           TF               tF               F         8       F   z*            F              F   Q           F         J       F        O      G               #G         8       ;G   pJ     6          pN            QG   d     :       kG                    rG   PQ           G   po     !      G   h     7       G        Q       G   L            G   0G!           G   #           H   P     6       1H        8      NH   F            YH    %     `       uH        Q       H              H   П            H   @     c      H                    I "  %     "       KI                    iI   0     Y       I         >       I   f     `       I "  %     =       I               I   oo
     u       J   P            .J              BJ   p     `       \J   !     s       kJ   v
            }J   I     R      J                    J                    J        3       J        ^       J         M       J   %           K   pG     Z       K         h       .K   PF            HK   p            jK                    K                    K               K   P     ;       K               K   ]            K               L   `      
      L   0             L   8
            .L "  n%            pL    *             L        0       L "  V%     Q       L        g       M   0     \      M   {           (M              8M   b            QM   `     g       hM   /%           {M   W
            M                    M        L       M                    M   @     u       M   0     m      M   @!     T       
N   P(     x       N   0     C       +N                    CN   p     q       aN   '            uN   4           N                    N         U       N   
            N        8       N   Ѯ
     u       O   `           *O   D?            >O "  F%     #       vO "  %     -       O   !           O                    O   0     f       O   E     g      P                    "P   @     @       0P   N     =       FP   I     &      YP                    rP   `     /       P   P            P                    P   5
            P                    P    "     :      Q   p     ]       &Q    #     }       CQ              QQ        r       bQ        d       zQ   0K           Q              Q                        y     w       Q   
     m      Q "  X%            ;R   P5            UR        .       mR    6     4      R               R               R   @     >       R   M     k       R                    R   @X           S   P           5S "  J%            S        @       S        _       S        Y       S   @$           S   M           S        =       S                    S   
            T                    #T        >      3T   P     5       BT                    ҕ   `s%           ZT   D            jT   t           ~T   "           T                    T                    T   x           T   $           T   @     @        U   Y     _       U   =     5       5U         g      DU   
     e       UU                    iU    J     l       U   p           U                    U "  %            V   `r     w       $V   @f*            :V   0     
      LV                    rV        ]      V                    V   0n            V   У     #       V   v           V   s
           V        2       W               W   A            (W    T               	     8       @W         @       LW   >            aW        ;       tW                    W                    Jh   0m     ~       W        X       W                    W   `H           W   L            W   9            W   %           X   P            %X    *             9X   =            T    `     J       CX         T      `X                    lX    \            X        L       X   Е           X   `     /       X               X   A     F      X   `*             Y                    Y   &           "   4     >       %Y "  %     1       Y   `$     =       Y   p     Y       Y   K     6       Y                    Y                    Y   c            Z   z             Z   `"     8       <Z   0            OZ   H
            jZ "  %            Z               Z   p            Z   "     ,      yf    -            q{   `     k       Z         =       Z "  &%     ?        [   @~            [        H       *[   Y            E[   0     6       W[   ?     5       e[   P            o[    %            [                    [        s       [   о            S   )            [        k      [   @            [   P!           \   G     0       *\   {     
      A\   з           W\   *             m\   _            ^-   @(            \   @I!           \               \   *             \               \   `             ]   P            ]   `           #]        *      3]        y       B]   0            Z]                    x]   pA            ]                    ]   i     6       ]   H     P       ]               ]   `     I       ]              ^   p*            ^   }
     -       5^                    M^   js     g      ^^   p     6       x^                    ^    G            ^        D      ^   `F            ^   "            ^ "  P"     1       ^                    _                    _        @       +_   c     
      A_              __   2            k_                    _                    _   0=     5       _   б     9       _   p4            _   0     W       _                    ` "  %            ;`        c      Q`   @     s       h`   "     B      u`        r       `   s     R       `        ;      ` "  %            a   :            a "  v%            ja   7
     F       va                    a   %                P            a   Px            a   P>            a   n     Z       a "  i%            Wb "  %            tb               b   `}     M       b   p!     6       b              b               b                    b               b   (     5       c   h            )c   @     l       :c   p1     v       Fc    f"            Wc         Y       ic                    c                    c                    c   @     q       c   K            c   @            c   p%            d   PE            d                    +d   *             Ad              ^d   pN            rd   Z     #       d                    d                    d   `@     <      d   s     +      d                    e   q     8       e   i     Z       %e              :e   PG     >       Te   @     Z       \e "  %     #       e   P$           e                    e   b            e   !            e   
     u       e   *     	      	f                    (f   R!     d       6f        @       Nf   M           kf               f                    f         i       f   `           f   @B             f   `     F       g   {     ,       g                    @g   a#            Pg    $     
      fg    C     r       zg "  %            g        Y       g                     h   [     u       h        o       1h   q     9       Hh    l            Vh   (T            rh "  V%     s       h   p            h   G            h "  %            +i         [                     >i   q     9       Ui        t       ei   ?     q       i   #            i               i        X       i   Pz!           i               i   p     P      i        O      j   @     U      (j   
            Aj   g            Uj              mj   d            j               j        e       j         D       j   i
            j                    j   @r*            j   !     ~                N       k   W     H       k   0     C       .k               Jk   p2     4       ]k        <       xk        R       k                    k   2     b       k        g       k   #     
      k   ;     n       l   
            5l                    Fl   L
     #       Wl   @<            ml        9       |l   
            l   0?!           l        h       l   PD           l              l                    z   `ę             l   г     R      m        Y       )m   Q     M      8m              Lm                    om                    o        ;       m        O       m                    m              m    #     i       m               m   `     8       m   I     3       n   @            3n                   ?     Z       Nn   Y            an                ~n   h"            n   0W     5       n   k     m       n   `     N      n               n                    o                    #o                    Io        k      Uo   ,            no   !            o   %     D      o                o               o               o        q       o    |"     :       p   05            +p   @     G      >p              Rp   `*             fp "  &%     "       p        X       p        8       p   %     z       p   `[!     z      p               q "  %            Qq                    gq        e       zq                    q                    q                    q                    q                    q        8       r   )           %r   0     6       ;r   P     O      Or   "            gr   @            r         T       r         !      r   Ù             r   `           r        )      r   
            s         <       s   C            6s        6       Hs   r     G      Zs         K      ts   0            s   !            s               s    ,     2       s   0u     a       s   C     S       s        m       s        L      t   0     =       t        e       3t   P2!           Ct   O#     P       Xt        4       ft                    t "  \%            t        <       t   P            t        8       u        @       %u                    7u                    Ou   P           gu   C            {u               u   ̄
     @       u   l"           u                    u   K     =       u         8       v              1v   q     T       Tv   1     6      jv   0           v   ps     K      v         m       v   P     =       v   g     p       v   @     @       v    g#            v    G     L       w   d           w   a%            1w   К     `       Aw   P           Xw               lw   %     )      w   "           w    Ӛ     `       w        S       w   P            w   f            w   &            x   PM!            'x        6       ?x   `c     F       Px   0     H       cx   0     A      sx    n#            x   й     Y       x        h       x                    x   	     A       x   8            y                    y                    +y   &     ]       =y        0      _y    $     6      wy   @Z*            y   ]     >       y                    y   x     8       y   @      i       y              z   (     ]       !z                    6z   
     #       Qz   @!           iz   p     .      uz        F       z   p}           z   
     y       z "  %     ^       z   +            z                    {               '{                    @{   W"     j      Q{         u       _                    c{   >            o{         _       l        ~       {   9     r       {   #           {                    {   P<!           {   p           {        P       |   8     A       |   PI     @       5|   J     4       L|   p            h|   Y            |   `]           |   B            |                    |   gr
           |        8       |         ?       }   N            "}                    8}                    \}   {            r}         ;      }   `j           }         B       }    .            }                    }   `F!            z   hF            }    O     8       ~        H       ~                    /~                    B~   )     j      O~                    f~   C     5       t~                    ~   P           ~   	%     |      ~                    ~                    ~        /      ~   
     8       ~   P1     T                                          7   @#           [   i            p   `x     W      3                                                      0%              B                                                   п     X          @            4              O                    h   µ
     `                        Z%     \              @       ǀ   @     @       ۀ   @                   <          Е     b       )   @L            =    i#            L   pR            j              ~                       Z               e     6      Á        V                             >     e               <       H;    @     h       ,   `            7                    M                b                    v   '     F          I               @               @     Q       ̂   `     6       ߂                   )                                /   l            G   0           S         H       g                    {   2
     @       {    ,/     )                                           ΃   5"     
      ك   
     @          W	               p             "  4%     7       S   ՚            a               o                       (                              G"     v              f           &     D       Ʉ                       @f#                0O                                C    *             Y   	     !       j                       pL     4                =          4     X       ƅ   p                   @          N%     X                    )   p#               4     7       @ "  %     Z          v%     D         p!     Q          `Z"     H      Ɔ   x>            ن   "                     X       
                       `/     >      L<   `
     ?       6   P5            O   E            f   ڗ$     f       w   J     R         %     P                       N     <       ч                  @     [         n#     F        "  D%            R         L       e                    z        E                              o               
            ň        e       ׈   |     y                              `Ù                `            &   w     q      ;   y     ~       U                    c         v       u   *                                    m          J     U       ω        8                              *                0$     n        "  %     D       6        n       U   >            i               ~   P               M               >                    ?       ϊ   H     Q                               P       	   "                *             )   @=           @                J "  %     M                                ~                      ̋    2#     C       ܋        V                          
                   `            1   '           H   @     +      \   `u     3       p                                      P     5          }     i      ь   P                               	                                        9   Ѝ$     $      X                    q         6       {   P     <          P     u                             pw             "  l%     \       ̍    F     @           R     H                       "  %     /                      2 "  r%     P       d    0     i      p                 #                    6       w   Э     G           V     h       ǎ        6       ݎ                       P              M     8       "   0           @   P@     Z       J        G       \   f
     (       m    A     Z       y                       I                     B      Տ   `     \               [      	                        @*            3                    G        a       -        L      W   pH     c       r   и                    Y          D     >       Ȑ                    ِ   h                !     ;        "  V%     Q       R   &     )      n        @       |   L                                                #     <          K            "  l%     c       >                    s                     "  ,%     w                           Ȓ        D       ֒   r-             "  %            9p         :         	     8       9   @     ^        "  ;     6       .        %      B   P           `               s   P/                                   !     3          Q                               ϓ                       `|"     :       	        P       "        @       3        >       G   /     X       U                    q   pd%     '         P     y         P                    @                           ה   p     i                &                      +   0            ?   0f     =       J                    K   \G            a   p=     3       }   N     ;                              `     ?                           ̕   й!               {     <        "  2%            A   0#     \       i   B            {   `     <          )     ~                             p     H       Ö   w            Ֆ "  %            =   p
            S   )     l       i    B               G     2         e"     z               O          r     $      ɗ                 A     )         0              !     U          ?            +   0"           B                    R   p     ~       P   ?            m        @       x   u     H         P     !       "  %               @     ;       ͘   p                                    @)                 @:                                   
     \       4   @     ]       N                    h   $            z                                     #     \          @t"     A      ә   0~     V          @\     9      0^    0"               @     5          pV           -    9     g       ;   :#           L   8     m       X   #     <                            "  %            Qi         ^       Қ   @     d                                           !   0                               H        N       Z        /      s   H
     r                         n            C    x               t           ^                         n        "  %     8       F   )             \   05           q         e           1                                  P               0     4                           ʜ   P            K                    ݜ         @          0              `     ;       K   @     7       *        X       ;   Q     l       S        )       r   !     j                                                  #     B      ԝ                       `               Y            "  %            ,   p           =                    Y                    l                    |   `9     <               @          ;$               &     ]       ƞ    a"            ݞ         |                              0!     E                     <   `            Z   =           P                    u   p     }              h                              P5     w       ɟ "  f%            <                    J   ?     A      Z                    m                     |   @Ϛ     h        "  3%     {       ՠ                                                           @^*            '                    ?               Z              m   %              p9     ,         p5              `     .       ɡ   0S     H      ޡ   j!                              W     D       )        8       A              d        q               6          <                   9       ¢   p     X       ޢ        M         #r     M          p     R               t       0                    L   
     0       d   o#     q       z        3                               2                     3       ɣ   0@     H      ڣ   p	     F                              ^!           +   @*            ?               ]                    v                             @                           Ӥ        @                              k                !                                                B   hw
     k       T   
            i        6                        p     [                         p     `       إ                       =     M       
        2      (         @       1   p@&           =        c      L   P           h                                           `            >-   r     n          @b"           Ŧ   	                     V       ڦ         @          5     ;           R#     i       	   r              |     >      1        7       :   &     R       P   `     ?       e        |
                                                 3	      ϧ                       !     {                               *             .   A     Z       9               I   .     |       [                    o   P     l                                                              Ѩ   U     t                              Pc     f                           kU   J     @       #                    4              J                    ]   #     <        "  %     /          [     {                     ˩        K       ݩ   k!            '   @            %;   -     }        "  %     +       /   0     Q       I   D     S      Y   q!     6       g   @~*            }   `(              }
     )          #     K         p              H%            Ҫ                       @                               
    P
     @          "     q               B       6   Q     >       J              h                    w        r          `     L          @2             "  %     (          _     3          
	               8     G       6R        8      )        !      <   
            N                    a                    y    5!                                   *                P'     L       e        v       ì        d       Ӭ        *              P          ,               
	                           *        6       >                    V   I#     -      x                   f)     .               n      ȭ   ڲ
     -      ֭   '               &     n                        _     c       /   `\            J   `     {       X        S       j   `
     0          p3                !              `3            Ʈ   P&     B       ޮ   x               %                    +      .   {     F       A   @p#            =    U#     h       T        H       n   #     \          _     a          ~     6                     ͯ   P           گ                    G         7                                             P                               .   !     v       ?               M   `     ;       e   "                                        v       Ȱ                  Ѐ#                y"              G            "                ?   @     N       R   `	     8       k   @           z        _         w#              pE     7               u       ձ "  %               A     T       %                    8                    J   @G           ^        P       n   `%     m          ~
     '                               %               o
            ղ        X               a         	     +          0     !      !   =     O       0 "  h%     /       f        5       u   H     2          R              @                             !     5       ȳ    Z%     ]          0
                                               9d        m       9   I                `)             P                    v    k               Ь     P                             +     y                              p              !              \
            /   /     n       ?   o     `      T        q       j                                        T+        +         `                           ĵ   '            յ                   `                     Y          Q           2   M
            G   d
     m       \        X       | "  %            ¶   2            ۶   pr     6          p%     @                          "   `.            2        6           P     ?       N   `            b                    u                                       
     C       ѷ   8!     Q         /!            K                            \                          *    F           :               I              ^    j     5       o                                           @     @          1               >            ϸ    C                                ~|   0     8          v           %   $            3    f!            Q   @      <       i   #     /      x    )     3          0     m          `v     P         H     D           ,            ʹ                    ߹               ̿   `D     9                                             =            #                    :   pG     d       \ "  H%            Ϻ                                      0h     `          
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     )       n   `B             v                       "                               ̻   6X            ߻   !     s                           	   `           $        !      :   J            N   q%           X   y     @      m   2              !     5           '     z          `                                Լ   A
                    y               +       
                                  .               G   З     l       \   z     y       s                       !                               ӽ                                           0     T       
                     }            5   p            R                    `                    |         @          hx               _               P#     \       ̾   d"            ߾        >          P     e               ;          @,     b          .     1       &   v
     ~       6                    G                    W   o
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            J   m     ;       Z                    r                  L
     S          `p     O          &     S           !              8               $     #                           A               )0   r_     V	      [        1       p                    JC                        Z               _              j               Q          p     `         ;             "  %            n   >                                                 H     c          @"*               Pe                                   З     t       )   0           B                    b   =     U      o   @     H         i     6          P                                #z        Q                              p     u          !     
         P     &                     :   N#            K    !            [    y           p   P}     +         L     6          p     r                               `          :     (         "     O                              R           '   `     R      <    "     h       X   
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                               Э     _                        *             (   0.            4   @             K   @     ^      ]    p!     2       l   o     I       w   0     r          p     c                                                  @          -!     {          U     5          K     5       v    r            +   u'     {       C              ]   pK           w                       @*                                   0U"               d"               ~              P     x               X                          +        s       ?        >      P   p     t      n   p               G     \          $               `            D                       /
                     X                          С"                    H                              PO#     P       (                    A   `            L        J      f   
     8       }                       >                    s                     M   }     a           [     7          @     <           }!              ?'     6       &   Ps           X                    .        j       A                    U   G     :       m   `     c                              8          0*     @                          p     L         0A     e                        #            #   0           6               S   @     &      h               x         D       y    W              S     8                                                   l     :         &     F          p               `	           $   0     z      E   _     P       Z                    w   G     z                      t    a     Y                                                                      d>                    8                ~       "                    =   !            J   $     :      j   @J*            {   P/     Q           #     1         	                    `                8                ?       "  %            O                    y   P                                                 @{     #         t
     C          @!     9                              9
               p           5   <     Q       O        ^       k   m                                            @p              a                                   pd     D         P     C       @        @       T   0%     9      a   @            r                            &         %     *               8        "  %     g                           
                       `     6       %    g            =        /      T   P     R       o                       S               pE               5                8                              &                                         g          Z     *      %   8~
     <       8   @%            S   Ù     0       d   P#     \          !     8                                    >          `                                   S          
     B          `     g                           "              o    I           2                    J                    _                    y   G              o     <          @w                                  `     .          `!     *                                              )    P     %                         `$     x      8   pe     ?      S   h%            `              s   K            ~                  $                    J          }#     t               u          @              &     8           @     8       ?              S                    z                  r!     T               Q                              
               r                                                   '   (     8       :   e     I       O   5            a   #     7       n   @                   F          @'              h
               O               tk                    1       '    P     X               Y                     ;   [
            R    >           ]   `           v   @     <          o            >     #     e      P+        W                         x              #               0w                      8                Z       3        Z      I   #     !      b   B           s    F            c                    `     8          p     [          {"     :          @     A              9               d          >     8                           '   `      M      F        3       \   `A     7       h               y                                            6#               !     q                             $     c          %     :       *   n     H      J   p     G       f   z
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     C       '               :                    N        @       Z   R           o   R     c          @                                                       @P     C                                  n                           	     v      0   @            Y   P            n   `               @o     W          p              &               Ї     &         h                                   $                     J       %   
            <   7           R        O      d        Z       s    -     E               <          @     8                              0     9          
	                           .   ޘ     +       B        9       Y "  %                y     P                             Y                              !                    9          @     &      !   P!            5   @     @       D   %     	      Z   P8!     a       q                       p"     m              w                          0&     l          K     5           ]     p         z            3   PX     >      D   py     J       X              d   p     #                           "  %     ^       [P   `O               m     C         r     g          0                                 L   o0     P       y         _       d                                                                              Y                                              V               Ϛ     P               |      (   p     S      1   `           J                    \        C      x        J          P#     `          0                             @n*                    V           P     <                      %   з     <       H   @z            Q   u!            _                    t   !     s          X                    ?                            "  L%     <                              м           !        @       3   `     E      S        /      i   Z     1       y                 R     \               @          0     `         &                                                                       
           1    9           L   `X     ]       _ "  ,%                              `     V         F               :              0     a          @                !                             #           /   hh     s       D         Q       W    !           e                                           f     :                h          
               .     b          @     C          @"     b                               *     b       /         u      J                    d        ?      w                       M                                    V
     @          p     Y                      Np    0     :         `!     >       )    #            =               W                    }   K               0     .          *                                    ~
             "  R%            &   
     4       7   ?            E   *     i       \        8       u        G                              b
     #          +     ;         Pr     U       T!                                 s!     5                       1   @)     I      A        8       R   !            a   p|     h       |   `T!     Z                             Q                              u     D               @                                   i       +   M     J      D   `M     E       Y        ;      l        6                         PV                             `[     7          @     @          
	                           $ "  0%     (       l   q!     2       z   0     X         p2#              P     Q               -         pN     8           q!     3        "  %     +       ,               :                    N   Y            _               u   @^                                  `     }          @>*                    0        "  %     D          %               @     @       -   @D     O       ?        :       Y   x     (       g   
                                   F
     l           _"     7          0                              `
     M              F          p                '            :   
            W   `l            i   h     p       |         %         
     0                g       ;'                       ;               =          4"                                
   p     X               J       6                    _   %           ~        @          $              PU               U     I                                                 G          v     <               y       !               7   0     y       G "  %     J       w   G               "     V                               R     A               6               i          PK     T       /                    T   
            e                                 p(     c                ;                        "              _               !     s                      %   `՚     `                           2   @            H   p            c   A           w   %     .          0                                                ,        b       "  L%               po     u         0            B   7            T "  p%     <       y   !     w       _        l               w       ^  "                       c          I     3          ;     i          	                                
              $        |       A        |       Q        H       o                    ՚     `          G%               0!     B         /     8           "              ¡     .          k     x        "  R%            ,   @Қ     `       @   D     5       Q         t      ]   P+     7       v         T          7     H         !                                                  
                                  j      %   PZ            2               B                    X                    k    F            ~   V!               3     +                                   y         y     &               8                                 .       7    +     3       E               Z    !     '      k    !             y         e               b           j
           )   p     i           0                PI     Q                                `                    [         p%     Q       +    ę     H       8   @Z     F       Q "  4%               00     2          0     B                              pn     3         9     <          0               p           -   P     {       ?               Q   `$     8       h        ]      z        G           :               4     p                         M
     @                              p     5         0D     2                          7   0     X       P        L       ^   N     |       o        2         g"                    6          p     j          0p            "  ,%     w       
                        4            @                    `        h       z   @                0     p          !              P                           "  %                                - "  %     ^       U   P     	      l   ?                    T          L     0          G     5          @     8                        ~               :     Q               =           в     ^          @            "   j!     8       >   _           W   pr     T       l        +                                                        a          @Ù               P     D          }              @t!     8          l           #   p            0   *             F   @     j       a                       o#               Џ              ~%     V              5          `                             0,     O          02     2          `            ,   P     8       E                    U        q       s        @           )               W!               pv               @"     L               Z       "  %     [       	    f            Xx    `]            	    '            .	 "  %     T       g:    \           t	        ;       	                    	   p           	    b           	   :
            	        K      	   @*             
                    '
         r       @
   b            a
   A            t
        m      
               
        @       
                    
               
   M     F       
   pv           
                                  0   0L     2       G              \                    o   @     e                                                   y!     H          !     k       ?   H>                                               ,   @     ^      E   b           _                    u   Po!               0Q#                                        %                       #                    @                           
   Z            ) "        3       E        O       `        =      o                                     @     @          )     D                                                              *             . "   #"     1       ?   T            N                b   pI%            w                                     u     6                           H                   `               @V*               y
                               !        8       3   o            H                    f   ?     7       q        1          ~               `o                               :                    j               D          
            It    p     ;       )   @r!     T       9              <        ]       K        (       T   `.           c                       p     p               %                        4               `]     l               X       "   Py            =   
            M   0-     *      f   0"            z                                                                              3                          `!                     5       !   @     i       /                    I               S                    e   `&            w   `     t          $                                                      P                            j                   Q               Z                       3   @H            E               a              l   E                     E       )p         :         @     8          F                c     V          TQ               -     @          `7     R                          =   H            L   2     8       ^   !     T       k   0               @               0     0         /     @         	               s!     2          @               T     g       #   `"     o      7   pv%     ?       =   Q#     ^       Q   @           ^                    o                       Pk#     c                                            D"                                                  @                                 *    C     f       <                    X                    p    9     9       }                       PW     <                              t     #               <               `          P            ,        5       A        Q       Y   `x            i              r        6               K          
     C          D     >                Z         p     M                                           &   Ц"     b       8        0       R   Z     9       j   }              @.*                    F                A                             >          pE#                             P            .   tv            >   @+     z      O   @z*            c               x    M     9           a     O         
               I                                             ,     `               @                           6        V       E   p"     a      _                     y    ]               p9               0                                   p                                  te               I              f[     M       *   [     k       E                    i                    |                       8          p     M                                          ;    0@     ]                           #                    < "  f%     e       a         V       q                  $     8          p!               pz                   B                              K     L         `     ~      #                    <                    P   ~#     B       a   t~
     <       z "  %     h                                                   "     <       
   `#               #     q       '               9 "  0%     (               5          P@     2         @/     h          "     $                        @^                                   @                          0               K   P#     O      p        `         @     6               B          .     Q          p                            @b*                     X                               6          n             %                     :    0     N       S                o                     q                `%                0     8           0v#     I           !                                 !   !            !   r     k       +!   P=     X       =!   P     y      S!               p!   6     &      !   (            !                    ! "  p     5       !               !                    "   1     5       "   11     ,      .n         a       ;"   @     Y       ^"                    -    <     8       m"   `     J      z"                    "   J     T       "                    "   0            "               "                     #   Є     k       C#   M           O#                    b#   E     q       s#   0r%     $      #                #   ,            #   p#     b      #        (       #        Z       #              $    p%     J       -$   U            F$               c$                    v$        S      $   p`#     y       $   2     6       $   Ѝ           $               $                    $        7       %                    $%   0           )%   0O"     a       >%   "
     +       ]% "  %     :       %   [     w      %   0            %   @:*            %   `{     S       %   
           %   ^     $      &   p            &        8       3&   0            L&   p
     I       g&   |!            y&                    &   @     8       &   0J     2       &                    &        `       14                    &                    &                    '                    4'   @2*            G'   o     R       W'                    m'                    '   *           '         8       '               '        W       '   0!            '   !     5      (   U!            (         8       ,(   w            G(   Y     :       ](                m(   U            (   p           (    p     9      (   #            (   `N     <       Ȗ    P     *      (   C     5       (               (                    )                    .)                    C)   @*            T)   1            n)                )               )   @7!     Q       )   0     T       )   h            )   1v     I       %   O     2      )   )            )   O#     U       	*   C     <       *    :!            5*                    [*                    o*   px            y*                    *   U/     n       *   {     +       *               *    \           * "  %            $+   `     A       <+   0#     ?      K+         5       a+   0p            u+        {                      +   %     X      +    P!     }      +                    n_               +        `       +   `     (       + "  %     4       J,   k#     ]      [,   a            o,   w            w,    К     X       ,   %           ,        `       ,   $     j       ,        h       ,   ;           -                    -        K       -   `@             7-        ;      K-    n     P       b-   m           |-   @     5       -        e      -    !     b      -   +            -               -        W       -                    -   `           .        8      !.   ;     Y       1.   Z           @.   pm            T.        r      l.               {.   0%     b       .   @&     O       .   
	            .   @            .   ҡ     %      .   PW!     t       .   0#     B       
/                     :&    p            &/   B     5       3/   0     (      Q/        6       d/                    y/              /   o     <       /   ؔ            /   @           /                    /   p#     n       0   ҧ
            0                10   r     T       Q0              _0   q     ?       u0 "  "     1       0   @           0                    0   p%     6      0 "  2%            @1        J       $t               N1   a            X1              l1        b       1 "  r%     <       1   a            >;         m       1        E       1   `1           2               2         @       #2 "  %     =       g2        9       2                    2   #     V       2   u
     1      2   p#     a       2         B      2   d            3        o       3              3                    13   H           >3   i            R3         z       i3 "  %            3                    3   P+     j       3              3   p     ;       3   `            3   PR     q       3   
            4                    4    G            04        `       =4                    X4   j%     R      k4         \       4   i
            4 "  F%            4   p            4        8       
5   [     A      #5                85   `P     X       =                    M5   p            g5 "                   5   |     b      5                    5   `     Y       5   pd            5   B     =      5    #               =     5       6   T     5       6        I       )6                    96   p            M6                    j6        D       6                    6    d     I       6   @w     6       6   A     o       6   >           6        M       6   P     X       7        v       -7        Y      >7   c     i       K7   0/     M       e7   &           x7    t!     6       7               7   `            7   "     4       7   *            7        3      7                    8                    )8   D     C       O8   *             c8                    u8   R!            8    !     :       8         :      8    (%           8               8                    8   @     o       9   0%            &9   =            89                    L9   pf     7       wg         :       Z9        5       g9                    9   !            9   T     b       9         @       9 "  %            9   p            9                     :   @            9:   `     ]       Y: "  ,%            :   @E     G       :   F            :              :   
     y       :                    ;        *      /;               N;   v     Q       g;                    z;   
            ;        V      7    r            ;    r!     4       ;               ;   p     
      ;               <   @F*            Fj   `     G       <                    5<   P           K<   B     3       V<   *             i<   h
     /      z<                    <   @?     (      <               <   \     8       =               '=   ߚ     @       :=                    N=        8       k=        6       =   .     2       =        W       =   E            =   N     5       =   P#           =                    =   p            >   &            ]w   0s            +>   @j*            ?>               Q>   2           j>   1"           z7    G     7       x>   V     i      >   `            >                    >                    >                    >               >   `R            ?                    %?                    M?                    i?                ?   p     `       ?        m       ?   !     6       ?         @       ?   y            ?        R       @        w      @   ]     I      %@        X       =@              Q@   *             e@   !           v@              @   hR            @   u     U      @    H            @   p!           @                    A         ?       A                    5A                    TA         "       gA        3       A   p_            A   %            A   >            A        @       A               A                    B   p            )B   `}            ?B        J      YB   ,     F       qB "  "%     2       B   0y            B   w!     5       B   "     =      C        L       )C               5C        ;       BC        ]       XC   `#     C       kC   (     y       C                    C   P     i       C   P     X       C   h           C    o     k       C        Q       D   Џ#     E       /D               AD   @*            WD        +       gD    @     +      ~D        z       D                    D   C     U       D        V       D   pb%           E   /     3       E                    (E   p     8       @E                    VE   P     o       rE   p            E   @&*            E                    E   t!            :J   
     >       E                    E   W     8       F   #            &F   5     <       8F   !     b      KF        d       fF                    F                    F   @     K      F   0           F   0a     m       F    ;!     K      F                G "  &%            QG   7     H      oG        @       G              G   j            G   >     h       G   0d#            G   
     F       G                    H   C!     /      #H   p           4H                    LH   л            aH                    }H               H   F            H   @*             H        5       H    D     B      H        /      H   (            I   Pn            I   0e            7I                    _I        V       |I        #       I              I   Қ     `       I        >       I                    I   z"     d       J   )     .       ã    9            J   p            8J   
     =       RJ   p            qJ   P           J   =            J    Ù            J        ;       J   p0           J                    J   M     Z       K   0
     =        K        6       3K                    QK   0b           `K   `            mK   p~#     d       K         E       K   @B*            K                    K   >            K              K         h       K   i     h       L   w"     f      -L   `Y           NL                    aL   @ߚ     @       uL   0            L                    L   @            L   `Q     q       L              L         !       *         5       L              L               M   '           M               /M   Jp
           DM   F     @       QM        8       lM               }M               M        a       M              M                        b            M        Q       N                     N                    5N "  |%     6       VN               gN   	     M      ~N   0     N       N               N   p      >       N   P     6       N   `     @       N   @     ~       O   0"           !O              *O   "            DO "  %     [       iO   H     `       yO         g       O   w     ?      O   `     $      O                    O                    O        /      O   6     6       V{   E     D       O   `*             P               +P   @*             AP   @)           VP   w     ^       iP   ;     }       uP   p            P                    P                    P                    P   0            P                    Q               *Q   X            EQ        (       SQ                    [Q   0            nQ        q       Q   @     M       Q        m       Q   Ћ%            Q                      c      Q "  l%     c       R   5m            %R               BR   '           bR    "           zR "  T%     M       R                    R   P     -      R   >     I       R   PX     ^       R   1     m       S   p     `            T!            S        8       8S   %     a       RS   P     g       iS   w#     ]       zS   z            S        2       S   p     P       S   u     z       S   #            S                    S   P             S   @+            T   @U     5       /T   :     :       HT   C     >       _T              T    N     h       T   pA     Z       T "  %     '       T               T        [      T   I      #      T         @       	U                    $U                    EU "  b%            }U   P     5       U                    U                       j     B       U                U               U   $     A      V   `a           !V               0V                    m                    VV              eV   "           {V        6       V         (       V        Y       V              V   d     h      V   p     O       V   N     P      W        I      W   %     .       'W               4W                    OW   *             cW   
            |W   i     p       W        @       W                    W   D     9      W        }      W   @s!     5       W              $X    +     I       FX              eX                    zX   t!     5       X   #     0      X                    X   `     S       X               X   0     s      X               X                    Y "  T%            NY   6Z            YY         @       fY   pG     N       vY    >     (       Y                    Y   `           Y   @            Y   В     n       Y   F            Y               Z                    'Z   P     L       HZ   "     ?       bZ                    tZ   p           q    `             Z               Z              Z                    Z   
     0       Z   {     1       Z   *             [               %[                    Q[        m       i[                    [                [   _            [   r
            [               [   Ù            ~                    [   P0            \        d       \                    *\              @\    $            Z\   @     N       s\   +     c       \   %     `      \        @      \        O      \   h           \   `     @       \                    ]                    ]                    8]   `            O]   `     O       j]               ~]   p            ]        @       ]                    ]   y            ]   /            ]                    ^              ^   P!           )^                    =^         K       O^               _^ "       7       |^                    *   Y     5       ^   >            ^                    ^   O     n      ^   @     V       ^                    ^                    _   `N"            d   P|            *_   )     0               7       7_   \K            G_        c       `_   \!           u_         >       _   0z     L      _                    _   3            _        z       _   p            `                `   `           &`              7`   p     G       O`              ]`                    u`   m%           `   3            `   `            `        @       `   "            `   `q     9       `   !     :      a   (            a   @H     9      0a   p           Ha   3           Ta   `*             ja                    a        C       a   0!            a   u           a "  %            a   \"     A      b3   @            b               *b                    =b   I           Nb    *             bb   p            |b        1       b   Jl            b        0      b   "     ,      b   !     8       b   W            c              c   @            2c                    Kc               uc   @     8       c        e       c   *             c   @)            c        <       c        :       c        N       W                d                    (d    !            7d               Nd                    ed                    wd               d        6       d   V     5       d                    d              d   {     K       e   @N!            e                    1e               =e    E     L       be   p     5       se        5       e        W       e        5       e   s           e   *             e   B           e   03     5       e   #           f   pL     8      "f                    ?f               `f               |f   }
            f        >       f   V     V       f                f   ޚ     `       f                    g   ,            g   {"     :       3g   @R*            Fg    !     c       Sg   !     :       dg   !           g   E
            g               g        1      g   @4     J       g   N           g        8       h   4)           "h   P            @h   H           Xh   !            kh   
            h                    h   O     X       h        @       h                    h "  %     J       i                    i               (i   m     L       <i   @$            Oi        f       hi        @       xi              i   x     ]       i        O       i         5       i   f!           i   0           j   +     `      j        \      8j                    `j "  
%     L       j                    j   q     P       j   0P%            j   
     L      k                #k   @            =k   7!     P       Vk   w     Q       tk                    k   @     J       k   .            k              k   j     +      k "  T%            l   %           4l   P     \       Ml    *             al         s       ul    `"           l   /     3       l   e!     \       l   p     D       l                    l                    l   "           m   ;            "m        i       /m              Om        K      ^m              im   @N*            |m "  %     m       m                    m   .            m    7     T       m                m                       '     h       n "  d%     P       >n   !           Un        8       pn   #            n   `            n                n                n   
            n   "            o   D            o   p     f      5o   `            Io   v!           ]o   %'            qo "  %     :       1   `=     8       o   #     -      o   F     `       o                    o   OV            o   \            p               :p   @           Rp   AP           lp   F            p   Й     n      p               u~                    p   @     @       p         Q       p                    p   p     Q        q   eZ     Q       q   '            $q               Eq   pk     k       Xq                    vq   Pr     n       q                    q   `<            q                    q "  
%     L       -r   =            ?r        Q       m;    @D     ]           $            ^r   0            vr   `&     8       r   m
           r               r        k       r   !           r    /!     h       s        N       s   `{"     :       :s               Is   #           \s   `     Y       ps   f           s   P     d       s   @           s "  0     4       s   `            s   p     m       $    }     x      s        w       s   V     V       	t                    t   *            $t   M     f       4t   p            Pt   H            _t   
     [       mt   PT            t   pt           t   p     @       t              t   }
     #       t   ^     .       t   [            t        K        u   `     >       3u        y      Iu        |       Uu                    vu                    u   R     5       u   @     @       u   Ё%     Z       u              u   0     @       u              v                    v   t     +       +v   wf
     *       ?v   !     b      Tv   6     5       ev   p0     6       wv                    v    0!     "      v   @     S       v               v    {     i       v               v   7     :       v        8       w   @6*            w    Z     m       5w "  q%             Xw   #     j      iw               zw   z#     [      w   *             w        %      w   "     e      w    #     P       w              w        Y       x   S!     H       x   @*            "x   P-     8       6x                    Px         K       dx   ߚ     @       wx   !           x        X       x   u     a       x   `            x                    /y   P            :y                    Ry   P     M       ky    e!            y   0	           y   +     U      y   `W            y                    i   P7     7       y        .      y   
     \       y                z                !z   p     k      ?z   q     D       Qz              ez        #       z               z         A       z   *            l               z    Ù             z               z "  %     %       ${                    ={   O"     :       N{        8       i{   `!     #      z{               {               {         W      {   {           {                    |   0     8       |   s!     4       (|                    ?|   @_     F       Q|   '            ^|   p           ||         
      |   %            |   @     p       |                    |   F            |   0             }   
            }                    '}        @       7}   -     y       W}    "            g}   PH%     L       {}   `     +       }   ~!     M       }                    }   @*            }               }   P!           }    #     k       ~   p     j       ~   %            +~               =~   q     V      O~   G"     9       e~                    q                    x~   "     Y       ~   p&            ~   @**            ~   -            ~   `           ~   <     N       ~   ^             ~                 C     Q                      '   @%           H                    _                        	     V        "  %     *          %     R       "  0%     <       
   T             __base_pr __libperf_pr cpumap.c cmp_cpu cpu_map__trim_new __warned.1 __warned.0 threadmap.c evsel.c empty_thread_map.0 empty_cpu_map.1 perf_evlist__munmap_filtered perf_evlist__mmap_cb_mmap perf_evlist__mmap_cb_get __perf_evlist__propagate_maps mmap_per_evsel mmap_per_evsel.cold __func__.0 __func__.1 perf_evlist__mmap_ops.cold mmap.c zalloc.c xyarray.c exec-cmd.c report.constprop.0 add_path help.c pretty_print_string_list list_commands_in_dir exclude_cmds.cold __PRETTY_FUNCTION__.0 pager.c wait_for_pager pager_process pager_preexec wait_for_pager_signal forced_pager pager_columns pager_argv spawned_pager parse-options.c option__cmp print_option_help usage_with_options_internal.part.0 opterror.isra.0 get_value run-command.c die.constprop.0 sigchain.c sigchain_push.isra.0 signals subcmd-config.c setup.c helpline.c nop_helpline__pop nop_helpline__push nop_helpline__show default_helpline_fns progress.c null_progress__update null_progress__ops util.c perf_stdio__error perf_stdio__warning perf_eops default_eops hist.c hpp__sort_mem_stat he_get_period he_get_latency he_get_period_sys he_get_period_us he_get_period_guest_sys he_get_period_guest_us he_get_acc_period he_get_acc_latency he_get_raw_nr_events he_get_weight1 he_get_weight2 he_get_weight3 hpp__nop_cmp hpp__equal hpp__header_fn hpp__equal_mem_stat hpp__width_fn hpp_entry_scnprintf hpp__header_mem_stat_fn he_get_raw_period hpp__sort_latency_acc hpp__sort_overhead_acc __hpp__fmt hpp__sort_overhead hpp__sort_weight3 hpp__sort_weight2 hpp__sort_weight1 hpp__sort_period hpp__sort_samples hpp__sort_overhead_guest_us hpp__sort_overhead_guest_sys hpp__sort_overhead_us hpp__sort_overhead_sys hpp__sort_latency hpp__entry_weight3 hpp__entry_weight2 hpp__entry_weight1 hpp__entry_period hpp__entry_samples hpp__entry_overhead_guest_us hpp__color_overhead_guest_us hpp__entry_overhead_guest_sys hpp__color_overhead_guest_sys hpp__entry_overhead_us hpp__color_overhead_us hpp__entry_overhead_sys hpp__color_overhead_sys hpp__entry_latency hpp__color_latency hpp__entry_overhead hpp__color_overhead hpp__entry_latency_acc hpp__color_latency_acc hpp__entry_overhead_acc hpp__color_overhead_acc hpp__entry_mem_stat_dtlb hpp__color_mem_stat_dtlb hpp__entry_mem_stat_snoop hpp__color_mem_stat_snoop hpp__entry_mem_stat_memory hpp__color_mem_stat_memory hpp__entry_mem_stat_cache hpp__color_mem_stat_cache hpp__entry_mem_stat_op hpp__color_mem_stat_op ipchain__fprintf_graph_line ipchain__fprintf_graph.constprop.0 ipchain__fprintf_graph __callchain__fprintf_graph rem_sq_bracket rem_hits __callchain__fprintf_flat.isra.0 __callchain__fprintf_folded callchain__fprintf_graph.constprop.0 hist_entry_callchain__fprintf.constprop.0 browser.c ui_browser__color_config ui_browser__colorsets __ui_browser__refresh.isra.0 keysyms.c annotate.c type_hash type_equal disasm_line__filter annotate_browser__write_graph annotate_browser__printf ui_browser__set_jumps_percent_color annotate_browser__set_color annotate_browser__set_percent_color annotate_browser__refresh annotate_browser__show_full_location annotate_browser__show_full_location.cold annotate_browser__write annotate_browser__calc_percent annotate_browser__show_function_title annotate_browser__symbol_annotate_error.isra.0 __annotate_browser__search __annotate_browser__search_reverse annotate_he seq.1 annotate_browser__callq.isra.0 annotate_browser__callq.isra.0.cold annotate-data.c browser__next_entry browser__next_entry.cold get_member_overhead.isra.0 add_child_entries browser__seek browser__seek.cold annotated_data_browser__fold.isra.0 annotated_data_browser__unfold.isra.0 annotated_data_browser__toggle_fold hists.c hist_browser__check_output_full hist_browser__check_dump_full __hpp_get_period __hpp_get_latency __hpp_get_period_sys __hpp_get_period_us __hpp_get_period_guest_sys __hpp_get_period_guest_us __hpp_get_acc_period __hpp_get_acc_latency do_exit_browser filter_group_entries hist_browser__fprintf_callchain_entry callchain_node__init_have_children_rb_tree hist_browser__hpp_color_mem_stat_dtlb hist_browser__hpp_color_mem_stat_snoop hist_browser__hpp_color_mem_stat_memory hist_browser__hpp_color_mem_stat_cache hist_browser__hpp_color_mem_stat_op hist_browser__hpp_color_overhead_guest_us hist_browser__hpp_color_overhead_guest_sys hist_browser__hpp_color_overhead_us hist_browser__hpp_color_overhead_sys hist_browser__hpp_color_latency hist_browser__hpp_color_overhead hist_browser__refresh_dimensions hist_browser__show_callchain_entry hists_browser__scnprintf_title do_annotate do_run_script do_annotate_type do_browse_map do_res_sample_script block_hists_browser__title perf_evsel_menu__write hist_entry__init_have_children.part.0 hist_browser__hpp_color_latency_acc hist_browser__hpp_color_overhead_acc hist_browser__show_callchain_list.part.0 switch_data_file is_input_name_malloced do_switch_data hist_browser__folded_callchain_str.isra.0 hist_browser__show_callchain_graph hist_browser__show_callchain hist_browser__show_entry hists_browser__hierarchy_headers hists_browser__headers hists__filter_entries ui_browser__hists_seek hist_browser__show_hierarchy_entry hist_browser__refresh hist_browser__nr_entries hist_browser__reset do_zoom_thread do_zoom_socket hists_browser__zoom_map.isra.0 add_script_opt callchain_node__set_folding_rb_tree.constprop.0 callchain_node__set_folding_rb_tree hist_browser__set_folding do_zoom_dso callchain_node__count_rows_rb_tree callchain__count_rows hierarchy_count_rows hist_browser__toggle_fold add_annotate_opt do_toggle_callchain seq.3 __warned.4 evsel__hists_browse top_help.1 report_help.2 help.0 map_browser__write scripts.c scripts_config header.c ui_browser__argv_write res_sample.c res_sample_config context_len ui__sigwinch ui__need_resize ui__sigcont tty.0 done.1 ui__signal_backtrace ui__signal buf.0 perf_tui__warning perf_tui__error tui_helpline__pop tui_helpline__show backlog.0 tui_helpline__push __tui_progress__init tui_progress__finish tui_progress__update tui_progress__ops annotate-arc.c annotate-arm.c arm__associate_instruction_ops annotate-arm64.c arm64__associate_instruction_ops arm64_mov_ops arm64_mov__parse annotate-csky.c csky__associate_ins_ops annotate-loongarch.c loongarch__associate_ins_ops loongarch_call_ops loongarch_jump_ops loongarch_jump__parse loongarch_call__parse annotate-mips.c mips__associate_ins_ops annotate-x86.c update_insn_state_x86 intel__ins_is_fused amd__ins_is_fused x86__instructions annotate-powerpc.c arithmetic__parse load_store__parse arithmetic__scnprintf update_insn_state_powerpc powerpc__associate_instruction_ops load_store__scnprintf arithmetic_two_ops ins_array load_store_ops arithmetic_ops arithmetic_ins_op_31 annotate-riscv64.c riscv64__associate_ins_ops annotate-s390.c s390__associate_ins_ops s390_call_ops s390_mov_ops s390_mov__parse s390_call__parse annotate-sparc.c sparc__associate_instruction_ops arm64-frame-pointer-unwind-support.c addr2line.c read_addr2line_record cached.3 style.2 __func__.4 addr_location.c sym_hist_hash sym_hist_equal FILE__set_percent_color FILE__set_jumps_percent_color FILE__set_color annotation__init_sharded_mutex FILE__write_graph FILE__printf annotation__calc_lines add_basic_block print_summary annotation__config __symbol__inc_addr_samples.isra.0 __func__.2 __hist_entry__get_data_type annotation_line__print prev_line.0 symbol__annotate_fprintf2.isra.0 di_cache blake2s.c blake2s_compress block-info.c block_column_width block_total_cycles_pct_sort block_branch_counter_entry block_column_header block_range_entry block_cycles_pct_entry block_avg_cycles_entry block_dso_entry block_total_cycles_pct_entry block_cycles_lbr_entry al.0 block_columns block-range.c build-id.c mark_dso_hit_callback lsdir_bid_tail_filter asnprintf lsdir_bid_head_filter machine__write_buildid_table_cb no_buildid_cache dso__cache_build_id cacheline.c size.0 perf_config_get_cb perf_config_scan_cb config_file_name system_wide.8 collect_config __func__.5 __func__.3 perf_config_from_file.constprop.0 config_linenr config_file_eof var.1 value.0 failed.7 config.6 walltime_nsecs_stats copyfile.c copyfile_mode_ns ctype.c db-export.c db_export__threads db_ids_from_al db_export__call_path.localalias disasm.c arch__cmp dec__scnprintf nop__scnprintf ins__cmp lock__delete dec__parse symbol__init_regexpr file_lineno num_archs.4 archs.3 arch_new_fn.2 lock__scnprintf lock__parse symbol__disassemble_objdump env.c errno_to_name__generic errno_to_name__alpha errno_to_name__mips errno_to_name__parisc errno_to_name__powerpc errno_to_name__sparc errno_to_name__x86 __perf_env__read_core_pmu_caps perf_env__read_arch uts.2 is_amd.1 is_intel.0 find_func_symbol_cb find_any_symbol_cb text_poke_printer perf_event__names perf_mmap__unmap_cb perf_evlist__mmap_cb_idx __evlist__enable.constprop.0 __evlist__disable.constprop.0 tags.3 idx.2 evlist__prepare_workload.cold evlist__start_workload.cold sideband_evlist.c perf_evlist__poll_thread evsel__no_extra_init evsel__no_extra_fini __open_attr__fprintf __has_attr_feature store_event store_event.cold dump_perf_event_processes find_process.constprop.0 perf_evsel__parse_id_sample.constprop.0.isra.0 evsel__add_modifiers.isra.0 perf_evsel__object evsel__disable_missing_features evsel__hw_cache_stat evsel__priv_destructor evsel__compute_deltas.cold evsel__read_counter.cold __evsel__read_on_cpu.cold empty_cpu_map empty_thread_map states.1 prev_state_field.0 evsel__store_ids.cold evsel__detect_missing_features detection_done.4 detection_done.5 detection_done.3 evsel__open_cpu test_attr__enabled_tested.7 test_attr__enabled.6 evsel__open_cpu.cold __warned.2 evsel_fprintf.c comma_fprintf __print_attr__fprintf perf_event_attr_fprintf.c perf_event_attr__fprintf.cold evswitch.c find_bit.c levenshtein.c llvm.c symbol_lookup_callback memswap.c parse-events.c get_config_cpu __parse_events_error__print get_config_terms event_types config_term_names.2 parse_events_terms__to_strbuf.isra.0 config_term_shrinked tracepoint_error add_tracepoint_multi_sys_cb add_tracepoint_multi_event_cb parse_events__modifier_list config_term_common __parse_events_add_numeric config_term_pmu parse_events_add_pmu print-events.c mep_delete mep_new mep_cmp metricgroup__add_to_mep_groups_callback tracepoint.c perf_regs.c perf_regs_aarch64.c sdt_op_regex1 initialized.0 sdt_op_regex2 perf_regs_arm.c perf_regs_csky.c perf_regs_loongarch.c perf_regs_mips.c perf_regs_powerpc.c perf_regs_riscv.c perf_regs_s390.c perf_regs_x86.c sdt_op_regex sdt_reg_tbl print_binary.c print_insn.c rlimit.c argv_split.c rbtree.c string.c bitmap.c hweight.c smt.c cached.1 cached_result.0 strbuf.c strbuf_addv __match_glob strlist.c strlist__node_delete strlist__node_new strlist__node_cmp strfilter.c get_token strfilter_node__compare strfilter_node__sprint strfilter_node__delete strfilter_node__new top.c usage.c usage_builtin find_file_offset dso__data_open_lock_init origin.5 debuglink_paths compressions dso__get_filename open_dso dso__data_open_cnt dso__data_open __warned.3 cached_io data_open_lock_once.2 dso_load__error_str.0 dsos.c dsos__hit_all_cb dsos__read_build_ids_cb dsos__cmp_long_name_id_short_name __dsos__find_by_longname_id dso__set_basename dsos__fprintf_buildid_cb dsos__fprintf_cb dsos__find_kernel_dso_cb symbols__sort_name_cmp __read_proc_modules remove_old_maps kcore_mapfn visible_dir_filter do_validate_kcore_modules_cb vmlinux_path__init vmlinux_paths_upd idle_symbols_list.0 map__process_kallsym_symbol maps__split_kallsyms symbols__find_by_name validate_kcore_modules dso__load_kcore binary_type_symtab symbol_fprintf.c map_symbol.c color.c color_config.c metricgroup.c metric_event_cmp metric_event_delete metric_event_new metricgroup__find_metric_callback metric_list_cmp metricgroup__topdown_max_level_callback metricgroup__sys_event_iter default_metricgroup_cmp match_metric_or_groups parse_ids metricgroup__has_metric_or_groups_callback metricgroup__add_metric_callback violate_nmi_constraint.0 __add_metric write_branch_stack cpu_cache_level__sort memory_node__sort cpu_cache_level__read print_e_machine print_cpu_domain_info print_hybrid_topology print_compressed print_dir_format print_clockid print_cache print_stat print_auxtrace print_branch_stack print_cpu_topology __desc_attr__fprintf print_total_mem print_cpuid print_cpudesc print_nrcpus print_arch print_version print_osrelease print_hostname print_bpf_btf print_mem_topology perf_file_section__fprintf_info perf_file_section__process print_sample_time print_group_desc print_pmu_mappings print_numa_topology print_cmdline write_build_id evlist__prepare_tracepoint_events print_cpu_pmu_caps print_clock_data write_auxtrace check_magic_endian.part.0 write_tracing_data write_stat __event_process_build_id.isra.0 perf_header__read_build_ids build_mem_topology.constprop.0 print_pmu_caps process_total_mem process_clockid process_dir_format process_sample_time process_mem_topology do_read_string process_cpuid process_cpudesc process_arch process_version process_osrelease process_hostname process_cmdline process_pmu_mappings __process_pmu_caps process_cpu_pmu_caps process_hybrid_topology process_nrcpus process_clock_data process_e_machine process_numa_topology process_compressed process_group_desc process_bpf_btf process_cache process_bpf_prog_info read_event_desc process_event_desc print_event_desc process_cpu_domain_info process_cpu_topology write_e_machine write_clock_data write_compressed write_bpf_btf write_bpf_prog_info write_dir_format write_clockid write_mem_topology write_sample_time write_total_mem write_nrcpus perf_header__adds_write feat_writer_cb perf_session__do_write_header zero_buf.7 write_pmu_mappings write_numa_topology write_hybrid_topology write_event_desc write_cpu_pmu_caps write_group_desc write_version write_arch write_osrelease write_hostname write_cmdline write_cpudesc write_cpu_topology write_pmu_caps printed.6 write_cpuid write_cache write_cpu_domain_info callchain.c parse_callchain_mode parse_callchain_sort_key add_child add_child.cold free_callchain_node init_callchain_cursor_key callchain_cursor__delete __sort_chain_graph_rel __sort_chain_graph_abs callchain_node_branch_counts_cumul.isra.0 decay_callchain_node append_chain_children append_chain_children.cold __sort_chain_flat __parse_callchain_report_opt merge_chain_branch once_control.1 values.c trace_event_printer trace_event_printer.cold _debug_file redirect_to_stderr pr_debug_wrapper pr_warning_wrapper debug_opts fncache.c fncache__hash fncache__init fncache__equal fncache fncache_once.0 machine.c machine__uses_kcore_cb machine__for_each_dso_cb machine_fprintf_cb thread_list_cb ip__resolve_ams append_inlines add_callchain_ip machine__init_live mmap_handler machine__map_x86_64_entry_trampolines_cb save_lbr_cursor_node.isra.0 lbr_callchain_add_lbr_ip.constprop.0 unwind_entry maps__set_modules_path_dir.constprop.5 machine__create_modules machine__create_module machine__update_thread_pid.part.0 seen.4 machine__get_running_kernel_start.constprop.0 thread__resolve_callchain_sample machine__process_kernel_mmap_event maps.c map__start_cmp map__strcmp maps__find_symbol_by_name_cb maps__fprintf_cb __maps__free_maps_by_name.part.0 __maps__insert maps__by_address_index maps__by_name_index __maps__remove __maps__insert_sorted __maps__fixup_overlap_and_insert pstack.c session.c perf_event__schedstat_cpu_swap perf_session__e_machine_cb perf_event__event_update_swap perf_event__thread_map_swap perf_event__event_type_swap perf_event__stat_swap perf_event__auxtrace_swap perf_event__tracing_data_swap perf_event__stat_config_swap perf_event__auxtrace_info_swap perf_event__text_poke_swap perf_event__namespaces_swap perf_event__all64_swap perf_session__flush_thread_stack perf_session__warn_about_errors reader__mmap dump_event.part.0 perf_event__time_conv_swap perf_event__cpu_map_swap perf_event__auxtrace_error_swap perf_event__switch_swap perf_event__task_swap perf_event__read_swap perf_event__comm_swap perf_event__mmap2_swap perf_event__mmap_swap perf_event__schedstat_domain_swap regs__printf regs_abi callchain__printf.isra.0 perf_event__stat_round_swap perf_event__itrace_start_swap perf_event__aux_swap perf_event__throttle_swap perf_event__cgroup_swap evlist__deliver_sample evlist__deliver_deferred_callchain session__flush_deferred_samples perf_session__process_user_event perf_session__process_user_event.cold ordered_events__deliver_event perf_event__hdr_attr_swap machines__deliver_event perf_session__deliver_event process_simple perf_event__swap_ops __perf_session__process_decomp_events reader__read_event tool.c delegate_read delegate_sample delegate_callchain_deferred delegate_attr delegate_event_update delegate_finished_round delegate_aux delegate_aux_output_hw_id delegate_bpf delegate_cgroup delegate_comm delegate_context_switch delegate_exit delegate_fork delegate_itrace_start delegate_ksymbol delegate_lost delegate_lost_samples delegate_mmap delegate_mmap2 delegate_namespaces delegate_text_poke delegate_throttle delegate_unthrottle delegate_auxtrace_error delegate_auxtrace_info delegate_bpf_metadata delegate_build_id delegate_cpu_map delegate_feature delegate_finished_init delegate_id_index delegate_stat delegate_stat_config delegate_stat_round delegate_thread_map delegate_time_conv delegate_tracing_data delegate_auxtrace delegate_compressed process_event_synth_tracing_data_stub process_event_stub perf_session__process_compressed_event_stub process_schedstat_domain_stub process_schedstat_cpu_stub perf_event__process_bpf_metadata_stub perf_session__process_compressed_event process_event_time_conv_stub process_stat_round_stub process_stat_stub process_event_stat_config_stub process_event_cpu_map_stub process_event_thread_map_stub process_event_synth_event_update_stub process_event_op2_stub skipn.isra.0 process_event_auxtrace_stub process_event_synth_attr_stub process_finished_round_stub s390-sample-raw.c get_counter_name_hash_fn get_counter_name_hashmap_equal_fn get_counter_name_callback get_counter_name cache_pmu.1 cache.0 amd-sample-raw.c ibs_fetch_type ibs_op_type cpu_family zen4_ibs_extensions ldlat_cap cpu_model dtlb_pgsize_cap data_src_str.1 data_src_str.2 dc_page_sizes.0 syscalltbl.c last_table_machine.1 syscalltbls last_table.0 syscall_num_to_name_EM_386 syscall_sorted_names_EM_386 syscall_num_to_name_EM_X86_64 syscall_sorted_names_EM_X86_64 syscall_num_to_name_EM_NONE syscall_sorted_names_EM_NONE ordered-events.c __ordered_events__flush namespaces.c nsinfo__get_nspid perf_ns__names comm.c comm_strs__init _comm_strs comm_str__put.part.0 comm_strs_type_once.0 comm_str__put.part.0.cold __comm_strs__find.constprop.0 comm_strs__findnew.part.0 thread.c thread__prepare_access_maps_cb thread__e_machine_callback thread__priv_destructor thread__e_machine.localalias threads.c key_hash key_equal thread_map.c thread_map__new_by_pid_str thread_map__new_all_cpus parse-events-flex.c yy_fatal_error.isra.0 parse_events_ensure_buffer_stack parse_events_restart.cold yy_base yy_accept yy_chk yy_nxt yy_def yy_meta yy_ec yy_rule_can_match_eol parse-events-bison.c yydestruct.isra.0 yyloc_default.0 yypact yycheck yydefact yytable yytranslate yystos yyr2 yypgoto yyr1 yydefgoto aliases__hash aliases__equal perf_pmu__match_wildcard perf_pmu__match_wildcard_uncore find_event_callback perf_pmu__format_parse pmu_add_cpu_aliases_map_callback pmu_add_sys_aliases_iter_fn perf_pmu__parse_event_source_bool perf_pmu__parse_unit.isra.0 perf_pmu__parse_scale.isra.0 update_alias pmu_id perf_pmu_format__load terms.0 is_sysfs_pmu_core perf_pmu__find_alias pmu_aliases_parse.part.0 perf_pmu__new_alias __pmu_aliases_parse.isra.0 pmus.c perf_pmus__print_pmu_events__callback build_format_string pmu_find other_pmus cmp_sevent pmu_read_sysfs read_pmu_types pmus_cmp perf_pmus__scan_skip_duplicates count.2 perf_pmus__init_supports_extended_type perf_pmus__do_support_extended_type extended_type_once.1 fake.0 pmu-flex.c perf_pmu_ensure_buffer_stack perf_pmu_restart.cold pmu-bison.c drm_pmu.c for_each_drm_fdinfo_in_dir for_each_drm_fdinfo read_drm_event read_drm_event_cb read_drm_pmus_cb drm_pmu_scale_unit_strs drm_pmu_unit_strs evsel__drm_pmu_read.cold hwmon_pmu.c hwmon_pmu__event_hashmap_hash hwmon_pmu__event_hashmap_equal hwmon_type_strs hwmon_item_strs hwmon_pmu__read_events.part.0 hwmon_scale_units.1 hwmon_desc.0 hwmon_units evsel__hwmon_pmu_open.cold evsel__hwmon_pmu_read.cold tool_pmu.c has_pmem has_pmem.0 read_pid_stat_field read_stat_field tool_pmu__event_names evsel__tool_pmu_open.cold evsel__tool_pmu_read.cold tp_pmu.c num_events_cb for_each_event_cb for_each_event_sys_cb num_events_sys_cb svghelper.c svgfile last_time total_height text.2 turbo_frequency cpu_m.1 buffer.0 trace-event-info.c tracepoint_id_to_path record_file output_fd copy_event_system trace-event-scripting.c flush_script_unsupported process_event_unsupported python_generate_script_unsupported python_start_script_unsupported perl_generate_script_unsupported perl_start_script_unsupported stop_script_unsupported script_specs branch_events trace-event.c tevent tevent_initialized trace-event-parse.c find_arg_field search_op offset.5 size.6 offset.3 size.4 offset.1 size.2 save_states.0 trace-event-read.c do_read input_fd repipe trace_data_size sort__thread_cmp sort__tgid_cmp sort__simd_cmp sort__srcline_from_cmp sort__srcline_to_cmp sort__callchain_branch_predicted_cmp sort__cpu_cmp sort__parallelism_cmp sort__cgroup_id_cmp sort__cgroup_cmp sort__socket_cmp hist_entry__socket_filter sort__time_cmp sort__mispredict_cmp sort__cycles_cmp sort__locked_cmp sort__tlb_cmp sort__lvl_cmp sort__snoop_cmp sort__weight_cmp sort__ins_lat_cmp sort__p_stage_cyc_cmp sort__blocked_cmp sort__phys_daddr_cmp sort__data_page_size_cmp sort__code_page_size_cmp sort__abort_cmp sort__in_tx_cmp sort__transaction_cmp sort__sym_size_cmp sort__dso_size_cmp sort__addr_cmp __sort__hpp_cmp __sort__hpp_collapse __sort__hpp_sort repsep_snprintf hist_entry__thread_snprintf hist_entry__srcline_snprintf hist_entry__srcline_from_snprintf hist_entry__srcline_to_snprintf hist_entry__srcfile_snprintf hist_entry__parent_snprintf hist_entry__cpu_snprintf hist_entry__parallelism_snprintf hist_entry__cgroup_id_snprintf hist_entry__socket_snprintf hist_entry__mispredict_snprintf out.2 hist_entry__local_weight_snprintf hist_entry__global_weight_snprintf hist_entry__local_ins_lat_snprintf hist_entry__global_ins_lat_snprintf hist_entry__p_stage_cyc_snprintf hist_entry__global_p_stage_cyc_snprintf hist_entry__phys_daddr_snprintf hist_entry__abort_snprintf out.1 hist_entry__in_tx_snprintf out.0 hist_entry__sym_size_snprintf hist_entry__dso_size_snprintf hist_entry__addr_snprintf hist_entry__type_snprintf hist_entry__tgid_snprintf hist_entry__comm_snprintf sort__comm_cmp sort__sym_sort sort__parent_cmp sort__srcline_from_init sort__srcline_from_collapse sort__srcline_to_init sort__srcline_to_collapse hist_entry__sym_ipc_snprintf hist_entry__sym_ipc_null_snprintf hist_entry__callchain_branch_predicted_snprintf hist_entry__callchain_branch_abort_snprintf hist_entry__callchain_branch_cycles_snprintf hist_entry__get_srcfile no_srcfile sort__srcfile_collapse hse_free hist_entry__cgroup_snprintf hist_entry__time_snprintf get_trace_output hist_entry__typecln_snprintf hist_entry__locked_snprintf hist_entry__tlb_snprintf hist_entry__lvl_snprintf hist_entry__snoop_snprintf hist_entry__blocked_snprintf hist_entry__data_page_size_snprintf hist_entry__code_page_size_snprintf hist_entry__typeoff_snprintf __sort__hpp_header __sort__hpp_entry __sort__hpp_width __sort__hde_cmp __sort_dimension__update __sort__hde_entry hist_entry__thread_filter hist_entry__simd_snprintf hist_entry__dso_to_snprintf hist_entry__cycles_snprintf sort__trace_cmp hist_entry__transaction_snprintf __sort_dimension__add_output hse_init sort__callchain_branch_cycles_cmp hist_entry__sym_to_filter hist_entry__sym_from_filter hist_entry__sym_filter hist_entry__symoff_snprintf hist_entry__dso_to_filter hist_entry__dso_from_filter hist_entry__parallelism_filter hist_entry__dso_filter hist_entry__sym_to_snprintf sort__callchain_branch_abort_cmp hpp_free hde_free add_evsel_fields __sort__hde_width __sort__hde_init hist_entry__trace_snprintf hist_entry__addr_from_snprintf sort__comm_collapse sort__comm_sort sort__srcfile_sort sort__symoff_sort sort__type_cmp sort__type_init hist_entry__dso_snprintf hist_entry__dso_daddr_snprintf hist_entry__dso_from_snprintf sort__srcline_from_sort sort__srcline_to_sort sort__typecln_sort __sort__hde_header __sort_dimension__add sort__type_sort sort__type_collapse sort__typeoff_sort sort__dso_cmp sort__dso_daddr_cmp sort__srcfile_init sort__srcfile_cmp sort__srcline_cmp hist_entry__addr_to_snprintf sort__dso_from_cmp sort__dso_to_cmp sort__addr_from_cmp sort__addr_to_cmp hist_entry__daddr_snprintf hist_entry__daddr_snprintf.cold hist_entry__iaddr_snprintf hist_entry__iaddr_snprintf.cold hist_entry__dcacheline_snprintf hist_entry__dcacheline_snprintf.cold hist_entry__sym_from_snprintf sort__sym_from_cmp sort__sym_to_cmp sort__symoff_cmp sort__srcline_init sort__srcline_collapse sort__srcline_sort __sort__hpp_equal __sort__hde_equal hpp_sort_dimensions common_sort_dimensions bstack_sort_dimensions memory_sort_dimensions iter_next_nop_entry hist_entry__free hist_entry__zalloc hist_entry__new default_ops iter_finish_cumulative_entry iter_prepare_mem_entry iter_next_branch_entry iter_prepare_branch_entry iter_prepare_cumulative_entry iter_next_cumulative_entry hist_entry__check_and_remove_filter iter_prepare_normal_entry hist_entry__cmp_impl.constprop.0 hists__match_hierarchy.isra.0 iter_add_next_nop_entry iter_add_single_branch_entry hist_entry__cmp_impl.constprop.1 hist_entry__cmp_impl.constprop.2 resort_filtered_entry hists__apply_filters hists__hierarchy_output_resort hists__remove_entry_filter hist_entry__delete.localalias hists__decay_entry hists__findnew_entry __hists__add_entry.constprop.0 iter_add_single_mem_entry iter_add_next_branch_entry iter_add_single_normal_entry iter_add_next_cumulative_entry hists_evsel__exit hists__link_hierarchy.isra.0 hists__filter_hierarchy iter_finish_mem_entry iter_finish_branch_entry iter_finish_normal_entry iter_add_single_cumulative_entry hists_evsel__init rm_rf_depth_pat rm_rf_a_kcore_dir kcore_dir_filter nmi_watchdog.0 cpu__get_topology_int get_max_num set_max_cpu_num max_present_cpu_num aggr_cpu_id__cmp set_max_node_num online.0 affinity.c cputopo.c has_die_topology build_cpu_topology topology.0 open_cgroup match_cgroups add_cgroup_name cgroup_list target.c target__error_str rblist.c __rblist__findnew intlist.c intlist__node_cmp intlist__node_new intlist__node_delete vdso.c machine__thread_dso_type_maps_cb vdso_info_init.0 counts.c pkg_id_hash pkg_id_equal evlist__copy_prev_raw_counts.cold zero.0 stat-shadow.c prepare_metric last_name.1 last_pmu.0 stat-display.c new_line_std print_metric_json print_metric_csv print_metric_only_csv print_metric_only_json print_metricgroup_header_std print_metric_header print_metric_headers aggr_header_csv aggr_header_lens aggr_printout new_line_json print_running new_line_csv print_metricgroup_header_csv print_metric_begin.part.0.constprop.0 print_metricgroup_header_json print_metric_only print_metric_std print_counter_aggrdata print_counter num_print_iv.0 aggr_header_std perf_api_probe.c perf_probe_sample_identifier perf_probe_comm_exec perf_probe_context_switch perf_probe_text_poke perf_probe_build_id perf_probe_cgroup perf_do_probe_api.constprop.0 pid.0 perf_probe_api.constprop.0 perf_do_probe_api.constprop.1 perf_probe_api.constprop.1 perf_do_probe_api.constprop.2 perf_probe_api.constprop.2 perf_do_probe_api.constprop.3 perf_probe_api.constprop.3 perf_do_probe_api.constprop.4 perf_probe_api.constprop.4 perf_do_probe_api.constprop.5 perf_probe_api.constprop.5 record.c srcline.c srcline__tree_insert.cold dso__parse_addr_inlines.cold srccode.c srcfile_htab srcfile_list num_srcfiles map_total_sz synthetic-events.c filter_task perf_event__get_ns_link_info perf_record_mmap2__read_build_id cpu_map_data__synthesize perf_event__get_comm_ids.constprop.0 io__get_dec __synthesize_schedstat_domain perf_event__walk_cgroup_tree perf_event__synthesize_modules_maps_cb anonstr.1 __event__synthesize_thread.constprop.0 __event__synthesize_thread.isra.0 __perf_event__synthesize_threads synthesize_threads_worker perf_event__synthesize_threads.part.0 check_backup tsc.c cloexec.c perf_flag_probe probed.2 call-path.c rwsem.c thread-stack.c thread_stack__call_return thread_stack__new __thread_stack__flush thread_stack__pop_ks.isra.0 spark.c ticks.0 topdown.c iostat.c stream.c print_stream_callchain.constprop.1.isra.0 print_stream_callchain.constprop.0.isra.0 print_callchain_pair.isra.0 kvm-stat.c kvm-stat-arm64.c arm64_exit_reasons arm64_trap_exit_reasons __kvm_events_tp __kvm_reg_events_ops __kvm_skip_events exit_events kvm-stat-loongarch.c event_gspr_get_key child_events loongarch_exit_reasons kvm-stat-powerpc.c ppc__setup_book3s_hv ppc_book3s_hv_kvm_tp hcall_event_decode_key hcall_reasons hcall_event_end hcall_event_begin hcall_events hv_exit_reasons kvm-stat-riscv.c riscv_exit_reasons kvm-stat-s390.c event_icpt_prog_get_key sie_icpt_prog_codes event_diag_get_key sie_diagnose_codes event_sigp_get_key sie_sigp_order_codes event_icpt_insn_get_key sie_icpt_insn_codes sie_exit_reasons kvm-stat-x86.c msr_event_decode_key ioport_event_decode_key mmio_event_decode_key ioport_event_end msr_event_begin ioport_event_begin mmio_event_begin msr_event_end mmio_event_end mmio_events ioport_events msr_events svm_exit_reasons vmx_exit_reasons lock-contention.c callstack_filters auxtrace.c get_flags parse_sym_idx parse_num_or_str addr_filter__to_str auxtrace_queue_data_cb.part.0 auxtrace_queue_data_cb find_entire_kern_cb evlist__regroup.isra.0 find_dso_sym print_kern_sym_cb find_kern_sym_cb find_kern_sym __auxtrace_mmap__read aux_action_opts auxtrace_queues__add_buffer auxtrace_queues__add_indexed_event auxtrace_error_type_name intel-pt-pkt-decoder.c intel-pt-insn-decoder.c CSWTCH.12 intel-pt-log.c log_buf__close log_buf__write intel_pt_log_open log_name intel_pt_dump_log_on_error intel_pt_log_on_error_size intel-pt-decoder.c intel_pt_get_data p_log intel_pt_get_next_packet intel_pt_scan_for_psb intel_pt_calc_cyc_timestamp intel_pt_calc_tma intel_pt_calc_cyc_cb intel_pt_walk_insn intel_pt_walk_tip intel_pt_fup_event intel_pt_walk_fup intel_pt_ff_cb intel_pt_calc_mtc_timestamp.part.0 intel_pt_calc_tsc_timestamp intel_pt_walk_psbend intel_pt_walk_fup_tip intel_pt_walk_psb intel_pt_walk_tnt intel_pt_walk_trace intel_pt_err_msgs inat.c intel-pt.c intel_pt_evsel_is_auxtrace intel_pt_free_events intel_pt_free intel_pt_alloc_queue intel_pt_walk_next_insn intel_pt_findnew_vmcs_info intel_pt_pgd_ip intel_pt_match_pgd_ip intel_pt_get_guest intel_pt_sample_flags intel_pt_set_pid_tid_cpu intel_pt_synth_error intel_pt_queue_data intel_pt_perf_config intel_pt_config_div intel_pt_do_synth_pebs_sample pebs_gp_regs pebs_data_source_cmt pebs_data_source_grt intel_pt_get_trace intel_pt_dump.isra.0 intel_pt_dump_sample intel_pt_process_auxtrace_event intel_pt_prep_sample intel_pt_cache_lookup intel_pt_lookahead intel_pt_sync_switch intel_pt_synth_transaction_sample intel_pt_synth_psb_sample intel_pt_synth_mwait_sample intel_pt_synth_pwre_sample intel_pt_synth_pwrx_sample intel_pt_synth_exstop_sample intel_pt_synth_cbr_sample intel_pt_synth_iflag_chg_sample intel_pt_synth_instruction_sample intel_pt_synth_events_sample intel_pt_next_tid intel_pt_synth_cycle_sample intel_pt_synth_branch_sample intel_pt_synth_ptwrite_sample intel_pt_run_decoder intel_pt_process_queues intel_pt_process_event intel_pt_flush intel_pt_info_fmts intel-bts.c intel_bts_evsel_is_auxtrace intel_bts_free_events intel_bts_lost intel_bts_synth_branch_sample intel_bts_setup_queues.constprop.0 intel_bts_synth_error.isra.0 intel_bts_process_queue intel_bts_process_queues intel_bts_process_event intel_bts_flush intel_bts_process_auxtrace_event intel_bts_free intel_bts_info_fmts arm-spe.c arm_spe_evsel_is_auxtrace arm_spe_free_events arm_spe_set_pid_tid_cpu arm_spe__update_queues.part.0 arm_spe_get_trace arm_spe__synth_data_source_hisi_hip arm_spe__synth_data_source_ampereone arm_spe__synth_instruction_sample arm_spe_dump.isra.0 arm_spe_process_auxtrace_event arm_spe__synth_data_source_common arm_spe_free arm_spe__synth_branch_sample arm_spe__synth_mem_sample arm_spe_run_decoder data_source_handles arm_spe_process_queues arm_spe_process_event arm_spe_flush metadata_hdr_fmts metadata_per_cpu_fmts metadata_hdr_v1_fmts common_ds_encoding_cpus ampereone_ds_encoding_cpus hisi_hip_ds_encoding_cpus arm-spe-pkt-decoder.c arm_spe_pkt_out_string arm_spe_packet_name idx_name.0 arm-spe-decoder.c seen_idx.0 hisi-ptt.c hisi_ptt_process_event hisi_ptt_flush hisi_ptt_free_events hisi_ptt_evsel_is_auxtrace hisi_ptt_free hisi_ptt_process_auxtrace_event hisi_ptt_pkt_size hisi-ptt-pkt-decoder.c hisi_ptt_print_pkt hisi_ptt_4dw_pkt_field_name s390-cpumsf.c s390_cpumsf_free_events s390_cpumsf_flush s390_cpumsf_evsel_is_auxtrace s390_cpumsf_make_event s390_cpumsf__config s390_cpumsf_synth_error.constprop.0 s390_cpumsf_free s390_cpumsf_process_auxtrace_event s390_cpumsf_process_event powerpc-vpadtl.c powerpc_vpadtl_flush powerpc_vpadtl_free_events powerpc_vpadtl_sample.isra.0 powerpc_vpadtl_process_auxtrace_event powerpc_vpadtl_free powerpc_vpadtl_process_event cs-etm-base.c cs_etm_global_header_fmts cs_ete_priv_fmts cs_etm_priv_fmts cs_etmv4_priv_fmts parse-branch-options.c branch_modes dump-insn.c parse-regs-options.c __parse_regs.isra.0 parse-sublevel-options.c term.c help-unknown-cmd.c levenshtein_compare perf_unknown_cmd_config autocorrect dlfilter.c dlfilter__args dlfilter__attr find_dlfilter dlfilter__al_cleanup dlfilter__insn dlfilter__srcline dlfilter__object_code dlfilter__resolve_ip dlfilter__resolve_address dlfilter__resolve_addr perf_dlfilter_fns list_filters mem-events.c perf_pmu__mem_events_name perf_pmu__mem_events_supported.isra.0 tlb_access mem_lvlnum mem_hops snoop_access mem_stat_index.cold mem_stat_name.cold mem-info.c vsprintf.c units.c time-utils.c percent_slash_split expr-flex.c normalize expr_ensure_buffer_stack expr_restart.cold expr-bison.c handle_id expr.c branch.c mem2node.c clockid.c clockids list_sort.c __func__.9 __func__.8 __func__.7 __func__.6 sharded_mutex.c intel-tpebs.c process_feature_event is_child_pid __sample_reader tpebs_cmd process_sample_event tpebs_retire_lat__find tpebs_results evsel__tpebs_prepare tpebs_mtx_init tpebs_mtx_once.1 tpebs_mtx tpebs_send_record_cmd control_fd ack_fd tpebs_reader_thread bpf_map.c symbol-elf.c cmp_offset kcore_copy__process_modules dso__process_kernel_symbol kcore_copy__process_kallsyms copy_bytes rel_cmp elf_read_build_id.constprop.0 dso__load_sym_internal probe-file.c probe_cache__open.constprop.0 probe_cache__load scan_ftrace_readme ftrace_readme_table scanned.0 __probe_file__get_namelist type_to_suffix probe-event.c synthesize_perf_probe_point find_module_name kernel_get_module_map_cb get_text_start_address.constprop.0 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K     1S                             W                     ;     y                             c     0                    \                           n     0               d     	                            ~                     t                                                       f     @/                                                      >                                                   8     x     (                   	                                                                                                               